1 /*
   2  * Copyright (c) 1997, 2013, Oracle and/or its affiliates. All rights reserved.
   3  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4  *
   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_MACROASSEMBLER_X86_HPP
  26 #define CPU_X86_VM_MACROASSEMBLER_X86_HPP
  27 
  28 #include "asm/assembler.hpp"
  29 #include "utilities/macros.hpp"
  30 #include "runtime/rtmLocking.hpp"
  31 
  32 
  33 // MacroAssembler extends Assembler by frequently used macros.
  34 //
  35 // Instructions for which a 'better' code sequence exists depending
  36 // on arguments should also go in here.
  37 
  38 class MacroAssembler: public Assembler {
  39   friend class LIR_Assembler;
  40   friend class Runtime1;      // as_Address()
  41 
  42  protected:
  43 
  44   Address as_Address(AddressLiteral adr);
  45   Address as_Address(ArrayAddress adr);
  46 
  47   // Support for VM calls
  48   //
  49   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  50   // may customize this version by overriding it for its purposes (e.g., to save/restore
  51   // additional registers when doing a VM call).
  52 #ifdef CC_INTERP
  53   // c++ interpreter never wants to use interp_masm version of call_VM
  54   #define VIRTUAL
  55 #else
  56   #define VIRTUAL virtual
  57 #endif
  58 
  59   VIRTUAL void call_VM_leaf_base(
  60     address entry_point,               // the entry point
  61     int     number_of_arguments        // the number of arguments to pop after the call
  62   );
  63 
  64   // This is the base routine called by the different versions of call_VM. The interpreter
  65   // may customize this version by overriding it for its purposes (e.g., to save/restore
  66   // additional registers when doing a VM call).
  67   //
  68   // If no java_thread register is specified (noreg) than rdi will be used instead. call_VM_base
  69   // returns the register which contains the thread upon return. If a thread register has been
  70   // specified, the return value will correspond to that register. If no last_java_sp is specified
  71   // (noreg) than rsp will be used instead.
  72   VIRTUAL void call_VM_base(           // returns the register containing the thread upon return
  73     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  74     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  75     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  76     address  entry_point,              // the entry point
  77     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  78     bool     check_exceptions          // whether to check for pending exceptions after return
  79   );
  80 
  81   // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  82   // The implementation is only non-empty for the InterpreterMacroAssembler,
  83   // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  84   virtual void check_and_handle_popframe(Register java_thread);
  85   virtual void check_and_handle_earlyret(Register java_thread);
  86 
  87   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  88 
  89   // helpers for FPU flag access
  90   // tmp is a temporary register, if none is available use noreg
  91   void save_rax   (Register tmp);
  92   void restore_rax(Register tmp);
  93 
  94  public:
  95   MacroAssembler(CodeBuffer* code) : Assembler(code) {}
  96 
  97   // Support for NULL-checks
  98   //
  99   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 100   // If the accessed location is M[reg + offset] and the offset is known, provide the
 101   // offset. No explicit code generation is needed if the offset is within a certain
 102   // range (0 <= offset <= page_size).
 103 
 104   void null_check(Register reg, int offset = -1);
 105   static bool needs_explicit_null_check(intptr_t offset);
 106 
 107   // Required platform-specific helpers for Label::patch_instructions.
 108   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 109   void pd_patch_instruction(address branch, address target) {
 110     unsigned char op = branch[0];
 111     assert(op == 0xE8 /* call */ ||
 112         op == 0xE9 /* jmp */ ||
 113         op == 0xEB /* short jmp */ ||
 114         (op & 0xF0) == 0x70 /* short jcc */ ||
 115         op == 0x0F && (branch[1] & 0xF0) == 0x80 /* jcc */ ||
 116         op == 0xC7 && branch[1] == 0xF8 /* xbegin */,
 117         "Invalid opcode at patch point");
 118 
 119     if (op == 0xEB || (op & 0xF0) == 0x70) {
 120       // short offset operators (jmp and jcc)
 121       char* disp = (char*) &branch[1];
 122       int imm8 = target - (address) &disp[1];
 123       guarantee(this->is8bit(imm8), "Short forward jump exceeds 8-bit offset");
 124       *disp = imm8;
 125     } else {
 126       int* disp = (int*) &branch[(op == 0x0F || op == 0xC7)? 2: 1];
 127       int imm32 = target - (address) &disp[1];
 128       *disp = imm32;
 129     }
 130   }
 131 
 132   // The following 4 methods return the offset of the appropriate move instruction
 133 
 134   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 135   int load_unsigned_byte(Register dst, Address src);
 136   int load_unsigned_short(Register dst, Address src);
 137 
 138   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 139   int load_signed_byte(Register dst, Address src);
 140   int load_signed_short(Register dst, Address src);
 141 
 142   // Support for sign-extension (hi:lo = extend_sign(lo))
 143   void extend_sign(Register hi, Register lo);
 144 
 145   // Load and store values by size and signed-ness
 146   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 147   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 148 
 149   // Support for inc/dec with optimal instruction selection depending on value
 150 
 151   void increment(Register reg, int value = 1) { LP64_ONLY(incrementq(reg, value)) NOT_LP64(incrementl(reg, value)) ; }
 152   void decrement(Register reg, int value = 1) { LP64_ONLY(decrementq(reg, value)) NOT_LP64(decrementl(reg, value)) ; }
 153 
 154   void decrementl(Address dst, int value = 1);
 155   void decrementl(Register reg, int value = 1);
 156 
 157   void decrementq(Register reg, int value = 1);
 158   void decrementq(Address dst, int value = 1);
 159 
 160   void incrementl(Address dst, int value = 1);
 161   void incrementl(Register reg, int value = 1);
 162 
 163   void incrementq(Register reg, int value = 1);
 164   void incrementq(Address dst, int value = 1);
 165 
 166   // Support optimal SSE move instructions.
 167   void movflt(XMMRegister dst, XMMRegister src) {
 168     if (UseXmmRegToRegMoveAll) { movaps(dst, src); return; }
 169     else                       { movss (dst, src); return; }
 170   }
 171   void movflt(XMMRegister dst, Address src) { movss(dst, src); }
 172   void movflt(XMMRegister dst, AddressLiteral src);
 173   void movflt(Address dst, XMMRegister src) { movss(dst, src); }
 174 
 175   void movdbl(XMMRegister dst, XMMRegister src) {
 176     if (UseXmmRegToRegMoveAll) { movapd(dst, src); return; }
 177     else                       { movsd (dst, src); return; }
 178   }
 179 
 180   void movdbl(XMMRegister dst, AddressLiteral src);
 181 
 182   void movdbl(XMMRegister dst, Address src) {
 183     if (UseXmmLoadAndClearUpper) { movsd (dst, src); return; }
 184     else                         { movlpd(dst, src); return; }
 185   }
 186   void movdbl(Address dst, XMMRegister src) { movsd(dst, src); }
 187 
 188   void incrementl(AddressLiteral dst);
 189   void incrementl(ArrayAddress dst);
 190 
 191   void incrementq(AddressLiteral dst);
 192 
 193   // Alignment
 194   void align(int modulus);
 195 
 196   // A 5 byte nop that is safe for patching (see patch_verified_entry)
 197   void fat_nop();
 198 
 199   // Stack frame creation/removal
 200   void enter();
 201   void leave();
 202 
 203   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 204   // The pointer will be loaded into the thread register.
 205   void get_thread(Register thread);
 206 
 207 
 208   // Support for VM calls
 209   //
 210   // It is imperative that all calls into the VM are handled via the call_VM macros.
 211   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 212   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 213 
 214 
 215   void call_VM(Register oop_result,
 216                address entry_point,
 217                bool check_exceptions = true);
 218   void call_VM(Register oop_result,
 219                address entry_point,
 220                Register arg_1,
 221                bool check_exceptions = true);
 222   void call_VM(Register oop_result,
 223                address entry_point,
 224                Register arg_1, Register arg_2,
 225                bool check_exceptions = true);
 226   void call_VM(Register oop_result,
 227                address entry_point,
 228                Register arg_1, Register arg_2, Register arg_3,
 229                bool check_exceptions = true);
 230 
 231   // Overloadings with last_Java_sp
 232   void call_VM(Register oop_result,
 233                Register last_java_sp,
 234                address entry_point,
 235                int number_of_arguments = 0,
 236                bool check_exceptions = true);
 237   void call_VM(Register oop_result,
 238                Register last_java_sp,
 239                address entry_point,
 240                Register arg_1, bool
 241                check_exceptions = true);
 242   void call_VM(Register oop_result,
 243                Register last_java_sp,
 244                address entry_point,
 245                Register arg_1, Register arg_2,
 246                bool check_exceptions = true);
 247   void call_VM(Register oop_result,
 248                Register last_java_sp,
 249                address entry_point,
 250                Register arg_1, Register arg_2, Register arg_3,
 251                bool check_exceptions = true);
 252 
 253   void get_vm_result  (Register oop_result, Register thread);
 254   void get_vm_result_2(Register metadata_result, Register thread);
 255 
 256   // These always tightly bind to MacroAssembler::call_VM_base
 257   // bypassing the virtual implementation
 258   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 259   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 260   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 261   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 262   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 263 
 264   void call_VM_leaf(address entry_point,
 265                     int number_of_arguments = 0);
 266   void call_VM_leaf(address entry_point,
 267                     Register arg_1);
 268   void call_VM_leaf(address entry_point,
 269                     Register arg_1, Register arg_2);
 270   void call_VM_leaf(address entry_point,
 271                     Register arg_1, Register arg_2, Register arg_3);
 272 
 273   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 274   // bypassing the virtual implementation
 275   void super_call_VM_leaf(address entry_point);
 276   void super_call_VM_leaf(address entry_point, Register arg_1);
 277   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 278   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 279   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 280 
 281   // last Java Frame (fills frame anchor)
 282   void set_last_Java_frame(Register thread,
 283                            Register last_java_sp,
 284                            Register last_java_fp,
 285                            address last_java_pc);
 286 
 287   // thread in the default location (r15_thread on 64bit)
 288   void set_last_Java_frame(Register last_java_sp,
 289                            Register last_java_fp,
 290                            address last_java_pc);
 291 
 292   void reset_last_Java_frame(Register thread, bool clear_fp, bool clear_pc);
 293 
 294   // thread in the default location (r15_thread on 64bit)
 295   void reset_last_Java_frame(bool clear_fp, bool clear_pc);
 296 
 297   // Stores
 298   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 299   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 300 
 301 #if INCLUDE_ALL_GCS
 302 
 303   void g1_write_barrier_pre(Register obj,
 304                             Register pre_val,
 305                             Register thread,
 306                             Register tmp,
 307                             bool tosca_live,
 308                             bool expand_call);
 309 
 310   void g1_write_barrier_post(Register store_addr,
 311                              Register new_val,
 312                              Register thread,
 313                              Register tmp,
 314                              Register tmp2);
 315 
 316 #endif // INCLUDE_ALL_GCS
 317 
 318   // C 'boolean' to Java boolean: x == 0 ? 0 : 1
 319   void c2bool(Register x);
 320 
 321   // C++ bool manipulation
 322 
 323   void movbool(Register dst, Address src);
 324   void movbool(Address dst, bool boolconst);
 325   void movbool(Address dst, Register src);
 326   void testbool(Register dst);
 327 
 328   // oop manipulations
 329   void load_klass(Register dst, Register src);
 330   void store_klass(Register dst, Register src);
 331 
 332   void load_heap_oop(Register dst, Address src);
 333   void load_heap_oop_not_null(Register dst, Address src);
 334   void store_heap_oop(Address dst, Register src);
 335   void cmp_heap_oop(Register src1, Address src2, Register tmp = noreg);
 336 
 337   // Used for storing NULL. All other oop constants should be
 338   // stored using routines that take a jobject.
 339   void store_heap_oop_null(Address dst);
 340 
 341   void load_prototype_header(Register dst, Register src);
 342 
 343 #ifdef _LP64
 344   void store_klass_gap(Register dst, Register src);
 345 
 346   // This dummy is to prevent a call to store_heap_oop from
 347   // converting a zero (like NULL) into a Register by giving
 348   // the compiler two choices it can't resolve
 349 
 350   void store_heap_oop(Address dst, void* dummy);
 351 
 352   void encode_heap_oop(Register r);
 353   void decode_heap_oop(Register r);
 354   void encode_heap_oop_not_null(Register r);
 355   void decode_heap_oop_not_null(Register r);
 356   void encode_heap_oop_not_null(Register dst, Register src);
 357   void decode_heap_oop_not_null(Register dst, Register src);
 358 
 359   void set_narrow_oop(Register dst, jobject obj);
 360   void set_narrow_oop(Address dst, jobject obj);
 361   void cmp_narrow_oop(Register dst, jobject obj);
 362   void cmp_narrow_oop(Address dst, jobject obj);
 363 
 364   void encode_klass_not_null(Register r);
 365   void decode_klass_not_null(Register r);
 366   void encode_klass_not_null(Register dst, Register src);
 367   void decode_klass_not_null(Register dst, Register src);
 368   void set_narrow_klass(Register dst, Klass* k);
 369   void set_narrow_klass(Address dst, Klass* k);
 370   void cmp_narrow_klass(Register dst, Klass* k);
 371   void cmp_narrow_klass(Address dst, Klass* k);
 372 
 373   // Returns the byte size of the instructions generated by decode_klass_not_null()
 374   // when compressed klass pointers are being used.
 375   static int instr_size_for_decode_klass_not_null();
 376 
 377   // if heap base register is used - reinit it with the correct value
 378   void reinit_heapbase();
 379 
 380   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 381 
 382 #endif // _LP64
 383 
 384   // Int division/remainder for Java
 385   // (as idivl, but checks for special case as described in JVM spec.)
 386   // returns idivl instruction offset for implicit exception handling
 387   int corrected_idivl(Register reg);
 388 
 389   // Long division/remainder for Java
 390   // (as idivq, but checks for special case as described in JVM spec.)
 391   // returns idivq instruction offset for implicit exception handling
 392   int corrected_idivq(Register reg);
 393 
 394   void int3();
 395 
 396   // Long operation macros for a 32bit cpu
 397   // Long negation for Java
 398   void lneg(Register hi, Register lo);
 399 
 400   // Long multiplication for Java
 401   // (destroys contents of eax, ebx, ecx and edx)
 402   void lmul(int x_rsp_offset, int y_rsp_offset); // rdx:rax = x * y
 403 
 404   // Long shifts for Java
 405   // (semantics as described in JVM spec.)
 406   void lshl(Register hi, Register lo);                               // hi:lo << (rcx & 0x3f)
 407   void lshr(Register hi, Register lo, bool sign_extension = false);  // hi:lo >> (rcx & 0x3f)
 408 
 409   // Long compare for Java
 410   // (semantics as described in JVM spec.)
 411   void lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo); // x_hi = lcmp(x, y)
 412 
 413 
 414   // misc
 415 
 416   // Sign extension
 417   void sign_extend_short(Register reg);
 418   void sign_extend_byte(Register reg);
 419 
 420   // Division by power of 2, rounding towards 0
 421   void division_with_shift(Register reg, int shift_value);
 422 
 423   // Compares the top-most stack entries on the FPU stack and sets the eflags as follows:
 424   //
 425   // CF (corresponds to C0) if x < y
 426   // PF (corresponds to C2) if unordered
 427   // ZF (corresponds to C3) if x = y
 428   //
 429   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 430   // tmp is a temporary register, if none is available use noreg (only matters for non-P6 code)
 431   void fcmp(Register tmp);
 432   // Variant of the above which allows y to be further down the stack
 433   // and which only pops x and y if specified. If pop_right is
 434   // specified then pop_left must also be specified.
 435   void fcmp(Register tmp, int index, bool pop_left, bool pop_right);
 436 
 437   // Floating-point comparison for Java
 438   // Compares the top-most stack entries on the FPU stack and stores the result in dst.
 439   // The arguments are in reversed order on the stack (i.e., top of stack is first argument).
 440   // (semantics as described in JVM spec.)
 441   void fcmp2int(Register dst, bool unordered_is_less);
 442   // Variant of the above which allows y to be further down the stack
 443   // and which only pops x and y if specified. If pop_right is
 444   // specified then pop_left must also be specified.
 445   void fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right);
 446 
 447   // Floating-point remainder for Java (ST0 = ST0 fremr ST1, ST1 is empty afterwards)
 448   // tmp is a temporary register, if none is available use noreg
 449   void fremr(Register tmp);
 450 
 451 
 452   // same as fcmp2int, but using SSE2
 453   void cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 454   void cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less);
 455 
 456   // Inlined sin/cos generator for Java; must not use CPU instruction
 457   // directly on Intel as it does not have high enough precision
 458   // outside of the range [-pi/4, pi/4]. Extra argument indicate the
 459   // number of FPU stack slots in use; all but the topmost will
 460   // require saving if a slow case is necessary. Assumes argument is
 461   // on FP TOS; result is on FP TOS.  No cpu registers are changed by
 462   // this code.
 463   void trigfunc(char trig, int num_fpu_regs_in_use = 1);
 464 
 465   // branch to L if FPU flag C2 is set/not set
 466   // tmp is a temporary register, if none is available use noreg
 467   void jC2 (Register tmp, Label& L);
 468   void jnC2(Register tmp, Label& L);
 469 
 470   // Pop ST (ffree & fincstp combined)
 471   void fpop();
 472 
 473   // pushes double TOS element of FPU stack on CPU stack; pops from FPU stack
 474   void push_fTOS();
 475 
 476   // pops double TOS element from CPU stack and pushes on FPU stack
 477   void pop_fTOS();
 478 
 479   void empty_FPU_stack();
 480 
 481   void push_IU_state();
 482   void pop_IU_state();
 483 
 484   void push_FPU_state();
 485   void pop_FPU_state();
 486 
 487   void push_CPU_state();
 488   void pop_CPU_state();
 489 
 490   // Round up to a power of two
 491   void round_to(Register reg, int modulus);
 492 
 493   // Callee saved registers handling
 494   void push_callee_saved_registers();
 495   void pop_callee_saved_registers();
 496 
 497   // allocation
 498   void eden_allocate(
 499     Register obj,                      // result: pointer to object after successful allocation
 500     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 501     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 502     Register t1,                       // temp register
 503     Label&   slow_case                 // continuation point if fast allocation fails
 504   );
 505   void tlab_allocate(
 506     Register obj,                      // result: pointer to object after successful allocation
 507     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 508     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 509     Register t1,                       // temp register
 510     Register t2,                       // temp register
 511     Label&   slow_case                 // continuation point if fast allocation fails
 512   );
 513   Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
 514   void incr_allocated_bytes(Register thread,
 515                             Register var_size_in_bytes, int con_size_in_bytes,
 516                             Register t1 = noreg);
 517 
 518   // interface method calling
 519   void lookup_interface_method(Register recv_klass,
 520                                Register intf_klass,
 521                                RegisterOrConstant itable_index,
 522                                Register method_result,
 523                                Register scan_temp,
 524                                Label& no_such_interface);
 525 
 526   // virtual method calling
 527   void lookup_virtual_method(Register recv_klass,
 528                              RegisterOrConstant vtable_index,
 529                              Register method_result);
 530 
 531   // Test sub_klass against super_klass, with fast and slow paths.
 532 
 533   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 534   // One of the three labels can be NULL, meaning take the fall-through.
 535   // If super_check_offset is -1, the value is loaded up from super_klass.
 536   // No registers are killed, except temp_reg.
 537   void check_klass_subtype_fast_path(Register sub_klass,
 538                                      Register super_klass,
 539                                      Register temp_reg,
 540                                      Label* L_success,
 541                                      Label* L_failure,
 542                                      Label* L_slow_path,
 543                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 544 
 545   // The rest of the type check; must be wired to a corresponding fast path.
 546   // It does not repeat the fast path logic, so don't use it standalone.
 547   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 548   // Updates the sub's secondary super cache as necessary.
 549   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 550   void check_klass_subtype_slow_path(Register sub_klass,
 551                                      Register super_klass,
 552                                      Register temp_reg,
 553                                      Register temp2_reg,
 554                                      Label* L_success,
 555                                      Label* L_failure,
 556                                      bool set_cond_codes = false);
 557 
 558   // Simplified, combined version, good for typical uses.
 559   // Falls through on failure.
 560   void check_klass_subtype(Register sub_klass,
 561                            Register super_klass,
 562                            Register temp_reg,
 563                            Label& L_success);
 564 
 565   // method handles (JSR 292)
 566   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 567 
 568   //----
 569   void set_word_if_not_zero(Register reg); // sets reg to 1 if not zero, otherwise 0
 570 
 571   // Debugging
 572 
 573   // only if +VerifyOops
 574   // TODO: Make these macros with file and line like sparc version!
 575   void verify_oop(Register reg, const char* s = "broken oop");
 576   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 577 
 578   // TODO: verify method and klass metadata (compare against vptr?)
 579   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 580   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 581 
 582 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 583 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 584 
 585   // only if +VerifyFPU
 586   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 587 
 588   // Verify or restore cpu control state after JNI call
 589   void restore_cpu_control_state_after_jni();
 590 
 591   // prints msg, dumps registers and stops execution
 592   void stop(const char* msg);
 593 
 594   // prints msg and continues
 595   void warn(const char* msg);
 596 
 597   // dumps registers and other state
 598   void print_state();
 599 
 600   static void debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg);
 601   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 602   static void print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip);
 603   static void print_state64(int64_t pc, int64_t regs[]);
 604 
 605   void os_breakpoint();
 606 
 607   void untested()                                { stop("untested"); }
 608 
 609   void unimplemented(const char* what = "")      { char* b = new char[1024];  jio_snprintf(b, 1024, "unimplemented: %s", what);  stop(b); }
 610 
 611   void should_not_reach_here()                   { stop("should not reach here"); }
 612 
 613   void print_CPU_state();
 614 
 615   // Stack overflow checking
 616   void bang_stack_with_offset(int offset) {
 617     // stack grows down, caller passes positive offset
 618     assert(offset > 0, "must bang with negative offset");
 619     movl(Address(rsp, (-offset)), rax);
 620   }
 621 
 622   // Writes to stack successive pages until offset reached to check for
 623   // stack overflow + shadow pages.  Also, clobbers tmp
 624   void bang_stack_size(Register size, Register tmp);
 625 
 626   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 627                                                 Register tmp,
 628                                                 int offset);
 629 
 630   // Support for serializing memory accesses between threads
 631   void serialize_memory(Register thread, Register tmp);
 632 
 633   void verify_tlab();
 634 
 635   // Biased locking support
 636   // lock_reg and obj_reg must be loaded up with the appropriate values.
 637   // swap_reg must be rax, and is killed.
 638   // tmp_reg is optional. If it is supplied (i.e., != noreg) it will
 639   // be killed; if not supplied, push/pop will be used internally to
 640   // allocate a temporary (inefficient, avoid if possible).
 641   // Optional slow case is for implementations (interpreter and C1) which branch to
 642   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 643   // Returns offset of first potentially-faulting instruction for null
 644   // check info (currently consumed only by C1). If
 645   // swap_reg_contains_mark is true then returns -1 as it is assumed
 646   // the calling code has already passed any potential faults.
 647   int biased_locking_enter(Register lock_reg, Register obj_reg,
 648                            Register swap_reg, Register tmp_reg,
 649                            bool swap_reg_contains_mark,
 650                            Label& done, Label* slow_case = NULL,
 651                            BiasedLockingCounters* counters = NULL);
 652   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 653 #ifdef COMPILER2
 654   // Code used by cmpFastLock and cmpFastUnlock mach instructions in .ad file.
 655   // See full desription in macroAssembler_x86.cpp.
 656   void fast_lock(Register obj, Register box, Register tmp,
 657                  Register scr, Register cx1, Register cx2,
 658                  BiasedLockingCounters* counters,
 659                  RTMLockingCounters* rtm_counters,
 660                  RTMLockingCounters* stack_rtm_counters,
 661                  Metadata* method_data,
 662                  bool use_rtm, bool profile_rtm);
 663   void fast_unlock(Register obj, Register box, Register tmp, bool use_rtm);
 664 #if INCLUDE_RTM_OPT
 665   void rtm_counters_update(Register abort_status, Register rtm_counters);
 666   void branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel);
 667   void rtm_abort_ratio_calculation(Register tmp, Register rtm_counters_reg,
 668                                    RTMLockingCounters* rtm_counters,
 669                                    Metadata* method_data);
 670   void rtm_profiling(Register abort_status_Reg, Register rtm_counters_Reg,
 671                      RTMLockingCounters* rtm_counters, Metadata* method_data, bool profile_rtm);
 672   void rtm_retry_lock_on_abort(Register retry_count, Register abort_status, Label& retryLabel);
 673   void rtm_retry_lock_on_busy(Register retry_count, Register box, Register tmp, Register scr, Label& retryLabel);
 674   void rtm_stack_locking(Register obj, Register tmp, Register scr,
 675                          Register retry_on_abort_count,
 676                          RTMLockingCounters* stack_rtm_counters,
 677                          Metadata* method_data, bool profile_rtm,
 678                          Label& DONE_LABEL, Label& IsInflated);
 679   void rtm_inflated_locking(Register obj, Register box, Register tmp,
 680                             Register scr, Register retry_on_busy_count,
 681                             Register retry_on_abort_count,
 682                             RTMLockingCounters* rtm_counters,
 683                             Metadata* method_data, bool profile_rtm,
 684                             Label& DONE_LABEL);
 685 #endif
 686 #endif
 687 
 688   Condition negate_condition(Condition cond);
 689 
 690   // Instructions that use AddressLiteral operands. These instruction can handle 32bit/64bit
 691   // operands. In general the names are modified to avoid hiding the instruction in Assembler
 692   // so that we don't need to implement all the varieties in the Assembler with trivial wrappers
 693   // here in MacroAssembler. The major exception to this rule is call
 694 
 695   // Arithmetics
 696 
 697 
 698   void addptr(Address dst, int32_t src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)) ; }
 699   void addptr(Address dst, Register src);
 700 
 701   void addptr(Register dst, Address src) { LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); }
 702   void addptr(Register dst, int32_t src);
 703   void addptr(Register dst, Register src);
 704   void addptr(Register dst, RegisterOrConstant src) {
 705     if (src.is_constant()) addptr(dst, (int) src.as_constant());
 706     else                   addptr(dst,       src.as_register());
 707   }
 708 
 709   void andptr(Register dst, int32_t src);
 710   void andptr(Register src1, Register src2) { LP64_ONLY(andq(src1, src2)) NOT_LP64(andl(src1, src2)) ; }
 711 
 712   void cmp8(AddressLiteral src1, int imm);
 713 
 714   // renamed to drag out the casting of address to int32_t/intptr_t
 715   void cmp32(Register src1, int32_t imm);
 716 
 717   void cmp32(AddressLiteral src1, int32_t imm);
 718   // compare reg - mem, or reg - &mem
 719   void cmp32(Register src1, AddressLiteral src2);
 720 
 721   void cmp32(Register src1, Address src2);
 722 
 723 #ifndef _LP64
 724   void cmpklass(Address dst, Metadata* obj);
 725   void cmpklass(Register dst, Metadata* obj);
 726   void cmpoop(Address dst, jobject obj);
 727   void cmpoop(Register dst, jobject obj);
 728 #endif // _LP64
 729 
 730   // NOTE src2 must be the lval. This is NOT an mem-mem compare
 731   void cmpptr(Address src1, AddressLiteral src2);
 732 
 733   void cmpptr(Register src1, AddressLiteral src2);
 734 
 735   void cmpptr(Register src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 736   void cmpptr(Register src1, Address src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 737   // void cmpptr(Address src1, Register src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 738 
 739   void cmpptr(Register src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 740   void cmpptr(Address src1, int32_t src2) { LP64_ONLY(cmpq(src1, src2)) NOT_LP64(cmpl(src1, src2)) ; }
 741 
 742   // cmp64 to avoild hiding cmpq
 743   void cmp64(Register src1, AddressLiteral src);
 744 
 745   void cmpxchgptr(Register reg, Address adr);
 746 
 747   void locked_cmpxchgptr(Register reg, AddressLiteral adr);
 748 
 749 
 750   void imulptr(Register dst, Register src) { LP64_ONLY(imulq(dst, src)) NOT_LP64(imull(dst, src)); }
 751   void imulptr(Register dst, Register src, int imm32) { LP64_ONLY(imulq(dst, src, imm32)) NOT_LP64(imull(dst, src, imm32)); }
 752 
 753 
 754   void negptr(Register dst) { LP64_ONLY(negq(dst)) NOT_LP64(negl(dst)); }
 755 
 756   void notptr(Register dst) { LP64_ONLY(notq(dst)) NOT_LP64(notl(dst)); }
 757 
 758   void shlptr(Register dst, int32_t shift);
 759   void shlptr(Register dst) { LP64_ONLY(shlq(dst)) NOT_LP64(shll(dst)); }
 760 
 761   void shrptr(Register dst, int32_t shift);
 762   void shrptr(Register dst) { LP64_ONLY(shrq(dst)) NOT_LP64(shrl(dst)); }
 763 
 764   void sarptr(Register dst) { LP64_ONLY(sarq(dst)) NOT_LP64(sarl(dst)); }
 765   void sarptr(Register dst, int32_t src) { LP64_ONLY(sarq(dst, src)) NOT_LP64(sarl(dst, src)); }
 766 
 767   void subptr(Address dst, int32_t src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 768 
 769   void subptr(Register dst, Address src) { LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); }
 770   void subptr(Register dst, int32_t src);
 771   // Force generation of a 4 byte immediate value even if it fits into 8bit
 772   void subptr_imm32(Register dst, int32_t src);
 773   void subptr(Register dst, Register src);
 774   void subptr(Register dst, RegisterOrConstant src) {
 775     if (src.is_constant()) subptr(dst, (int) src.as_constant());
 776     else                   subptr(dst,       src.as_register());
 777   }
 778 
 779   void sbbptr(Address dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 780   void sbbptr(Register dst, int32_t src) { LP64_ONLY(sbbq(dst, src)) NOT_LP64(sbbl(dst, src)); }
 781 
 782   void xchgptr(Register src1, Register src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 783   void xchgptr(Register src1, Address src2) { LP64_ONLY(xchgq(src1, src2)) NOT_LP64(xchgl(src1, src2)) ; }
 784 
 785   void xaddptr(Address src1, Register src2) { LP64_ONLY(xaddq(src1, src2)) NOT_LP64(xaddl(src1, src2)) ; }
 786 
 787 
 788 
 789   // Helper functions for statistics gathering.
 790   // Conditionally (atomically, on MPs) increments passed counter address, preserving condition codes.
 791   void cond_inc32(Condition cond, AddressLiteral counter_addr);
 792   // Unconditional atomic increment.
 793   void atomic_incl(Address counter_addr);
 794   void atomic_incl(AddressLiteral counter_addr, Register scr = rscratch1);
 795 #ifdef _LP64
 796   void atomic_incq(Address counter_addr);
 797   void atomic_incq(AddressLiteral counter_addr, Register scr = rscratch1);
 798 #endif
 799   void atomic_incptr(AddressLiteral counter_addr, Register scr = rscratch1) { LP64_ONLY(atomic_incq(counter_addr, scr)) NOT_LP64(atomic_incl(counter_addr, scr)) ; }
 800   void atomic_incptr(Address counter_addr) { LP64_ONLY(atomic_incq(counter_addr)) NOT_LP64(atomic_incl(counter_addr)) ; }
 801 
 802   void lea(Register dst, AddressLiteral adr);
 803   void lea(Address dst, AddressLiteral adr);
 804   void lea(Register dst, Address adr) { Assembler::lea(dst, adr); }
 805 
 806   void leal32(Register dst, Address src) { leal(dst, src); }
 807 
 808   // Import other testl() methods from the parent class or else
 809   // they will be hidden by the following overriding declaration.
 810   using Assembler::testl;
 811   void testl(Register dst, AddressLiteral src);
 812 
 813   void orptr(Register dst, Address src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 814   void orptr(Register dst, Register src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 815   void orptr(Register dst, int32_t src) { LP64_ONLY(orq(dst, src)) NOT_LP64(orl(dst, src)); }
 816   void orptr(Address dst, int32_t imm32) { LP64_ONLY(orq(dst, imm32)) NOT_LP64(orl(dst, imm32)); }
 817 
 818   void testptr(Register src, int32_t imm32) {  LP64_ONLY(testq(src, imm32)) NOT_LP64(testl(src, imm32)); }
 819   void testptr(Register src1, Register src2);
 820 
 821   void xorptr(Register dst, Register src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 822   void xorptr(Register dst, Address src) { LP64_ONLY(xorq(dst, src)) NOT_LP64(xorl(dst, src)); }
 823 
 824   // Calls
 825 
 826   void call(Label& L, relocInfo::relocType rtype);
 827   void call(Register entry);
 828 
 829   // NOTE: this call tranfers to the effective address of entry NOT
 830   // the address contained by entry. This is because this is more natural
 831   // for jumps/calls.
 832   void call(AddressLiteral entry);
 833 
 834   // Emit the CompiledIC call idiom
 835   void ic_call(address entry);
 836 
 837   // Jumps
 838 
 839   // NOTE: these jumps tranfer to the effective address of dst NOT
 840   // the address contained by dst. This is because this is more natural
 841   // for jumps/calls.
 842   void jump(AddressLiteral dst);
 843   void jump_cc(Condition cc, AddressLiteral dst);
 844 
 845   // 32bit can do a case table jump in one instruction but we no longer allow the base
 846   // to be installed in the Address class. This jump will tranfers to the address
 847   // contained in the location described by entry (not the address of entry)
 848   void jump(ArrayAddress entry);
 849 
 850   // Floating
 851 
 852   void andpd(XMMRegister dst, Address src) { Assembler::andpd(dst, src); }
 853   void andpd(XMMRegister dst, AddressLiteral src);
 854 
 855   void andps(XMMRegister dst, XMMRegister src) { Assembler::andps(dst, src); }
 856   void andps(XMMRegister dst, Address src) { Assembler::andps(dst, src); }
 857   void andps(XMMRegister dst, AddressLiteral src);
 858 
 859   void comiss(XMMRegister dst, XMMRegister src) { Assembler::comiss(dst, src); }
 860   void comiss(XMMRegister dst, Address src) { Assembler::comiss(dst, src); }
 861   void comiss(XMMRegister dst, AddressLiteral src);
 862 
 863   void comisd(XMMRegister dst, XMMRegister src) { Assembler::comisd(dst, src); }
 864   void comisd(XMMRegister dst, Address src) { Assembler::comisd(dst, src); }
 865   void comisd(XMMRegister dst, AddressLiteral src);
 866 
 867   void fadd_s(Address src)        { Assembler::fadd_s(src); }
 868   void fadd_s(AddressLiteral src) { Assembler::fadd_s(as_Address(src)); }
 869 
 870   void fldcw(Address src) { Assembler::fldcw(src); }
 871   void fldcw(AddressLiteral src);
 872 
 873   void fld_s(int index)   { Assembler::fld_s(index); }
 874   void fld_s(Address src) { Assembler::fld_s(src); }
 875   void fld_s(AddressLiteral src);
 876 
 877   void fld_d(Address src) { Assembler::fld_d(src); }
 878   void fld_d(AddressLiteral src);
 879 
 880   void fld_x(Address src) { Assembler::fld_x(src); }
 881   void fld_x(AddressLiteral src);
 882 
 883   void fmul_s(Address src)        { Assembler::fmul_s(src); }
 884   void fmul_s(AddressLiteral src) { Assembler::fmul_s(as_Address(src)); }
 885 
 886   void ldmxcsr(Address src) { Assembler::ldmxcsr(src); }
 887   void ldmxcsr(AddressLiteral src);
 888 
 889   // compute pow(x,y) and exp(x) with x86 instructions. Don't cover
 890   // all corner cases and may result in NaN and require fallback to a
 891   // runtime call.
 892   void fast_pow();
 893   void fast_exp();
 894   void increase_precision();
 895   void restore_precision();
 896 
 897   // computes exp(x). Fallback to runtime call included.
 898   void exp_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(true, num_fpu_regs_in_use); }
 899   // computes pow(x,y). Fallback to runtime call included.
 900   void pow_with_fallback(int num_fpu_regs_in_use) { pow_or_exp(false, num_fpu_regs_in_use); }
 901 
 902 private:
 903 
 904   // call runtime as a fallback for trig functions and pow/exp.
 905   void fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use);
 906 
 907   // computes 2^(Ylog2X); Ylog2X in ST(0)
 908   void pow_exp_core_encoding();
 909 
 910   // computes pow(x,y) or exp(x). Fallback to runtime call included.
 911   void pow_or_exp(bool is_exp, int num_fpu_regs_in_use);
 912 
 913   // these are private because users should be doing movflt/movdbl
 914 
 915   void movss(Address dst, XMMRegister src)     { Assembler::movss(dst, src); }
 916   void movss(XMMRegister dst, XMMRegister src) { Assembler::movss(dst, src); }
 917   void movss(XMMRegister dst, Address src)     { Assembler::movss(dst, src); }
 918   void movss(XMMRegister dst, AddressLiteral src);
 919 
 920   void movlpd(XMMRegister dst, Address src)    {Assembler::movlpd(dst, src); }
 921   void movlpd(XMMRegister dst, AddressLiteral src);
 922 
 923 public:
 924 
 925   void addsd(XMMRegister dst, XMMRegister src)    { Assembler::addsd(dst, src); }
 926   void addsd(XMMRegister dst, Address src)        { Assembler::addsd(dst, src); }
 927   void addsd(XMMRegister dst, AddressLiteral src);
 928 
 929   void addss(XMMRegister dst, XMMRegister src)    { Assembler::addss(dst, src); }
 930   void addss(XMMRegister dst, Address src)        { Assembler::addss(dst, src); }
 931   void addss(XMMRegister dst, AddressLiteral src);
 932 
 933   void divsd(XMMRegister dst, XMMRegister src)    { Assembler::divsd(dst, src); }
 934   void divsd(XMMRegister dst, Address src)        { Assembler::divsd(dst, src); }
 935   void divsd(XMMRegister dst, AddressLiteral src);
 936 
 937   void divss(XMMRegister dst, XMMRegister src)    { Assembler::divss(dst, src); }
 938   void divss(XMMRegister dst, Address src)        { Assembler::divss(dst, src); }
 939   void divss(XMMRegister dst, AddressLiteral src);
 940 
 941   // Move Unaligned Double Quadword
 942   void movdqu(Address     dst, XMMRegister src)   { Assembler::movdqu(dst, src); }
 943   void movdqu(XMMRegister dst, Address src)       { Assembler::movdqu(dst, src); }
 944   void movdqu(XMMRegister dst, XMMRegister src)   { Assembler::movdqu(dst, src); }
 945   void movdqu(XMMRegister dst, AddressLiteral src);
 946 
 947   // Move Aligned Double Quadword
 948   void movdqa(XMMRegister dst, Address src)       { Assembler::movdqa(dst, src); }
 949   void movdqa(XMMRegister dst, XMMRegister src)   { Assembler::movdqa(dst, src); }
 950   void movdqa(XMMRegister dst, AddressLiteral src);
 951 
 952   void movsd(XMMRegister dst, XMMRegister src) { Assembler::movsd(dst, src); }
 953   void movsd(Address dst, XMMRegister src)     { Assembler::movsd(dst, src); }
 954   void movsd(XMMRegister dst, Address src)     { Assembler::movsd(dst, src); }
 955   void movsd(XMMRegister dst, AddressLiteral src);
 956 
 957   void mulsd(XMMRegister dst, XMMRegister src)    { Assembler::mulsd(dst, src); }
 958   void mulsd(XMMRegister dst, Address src)        { Assembler::mulsd(dst, src); }
 959   void mulsd(XMMRegister dst, AddressLiteral src);
 960 
 961   void mulss(XMMRegister dst, XMMRegister src)    { Assembler::mulss(dst, src); }
 962   void mulss(XMMRegister dst, Address src)        { Assembler::mulss(dst, src); }
 963   void mulss(XMMRegister dst, AddressLiteral src);
 964 
 965   // Carry-Less Multiplication Quadword
 966   void pclmulldq(XMMRegister dst, XMMRegister src) {
 967     // 0x00 - multiply lower 64 bits [0:63]
 968     Assembler::pclmulqdq(dst, src, 0x00);
 969   }
 970   void pclmulhdq(XMMRegister dst, XMMRegister src) {
 971     // 0x11 - multiply upper 64 bits [64:127]
 972     Assembler::pclmulqdq(dst, src, 0x11);
 973   }
 974 
 975   void sqrtsd(XMMRegister dst, XMMRegister src)    { Assembler::sqrtsd(dst, src); }
 976   void sqrtsd(XMMRegister dst, Address src)        { Assembler::sqrtsd(dst, src); }
 977   void sqrtsd(XMMRegister dst, AddressLiteral src);
 978 
 979   void sqrtss(XMMRegister dst, XMMRegister src)    { Assembler::sqrtss(dst, src); }
 980   void sqrtss(XMMRegister dst, Address src)        { Assembler::sqrtss(dst, src); }
 981   void sqrtss(XMMRegister dst, AddressLiteral src);
 982 
 983   void subsd(XMMRegister dst, XMMRegister src)    { Assembler::subsd(dst, src); }
 984   void subsd(XMMRegister dst, Address src)        { Assembler::subsd(dst, src); }
 985   void subsd(XMMRegister dst, AddressLiteral src);
 986 
 987   void subss(XMMRegister dst, XMMRegister src)    { Assembler::subss(dst, src); }
 988   void subss(XMMRegister dst, Address src)        { Assembler::subss(dst, src); }
 989   void subss(XMMRegister dst, AddressLiteral src);
 990 
 991   void ucomiss(XMMRegister dst, XMMRegister src) { Assembler::ucomiss(dst, src); }
 992   void ucomiss(XMMRegister dst, Address src)     { Assembler::ucomiss(dst, src); }
 993   void ucomiss(XMMRegister dst, AddressLiteral src);
 994 
 995   void ucomisd(XMMRegister dst, XMMRegister src) { Assembler::ucomisd(dst, src); }
 996   void ucomisd(XMMRegister dst, Address src)     { Assembler::ucomisd(dst, src); }
 997   void ucomisd(XMMRegister dst, AddressLiteral src);
 998 
 999   // Bitwise Logical XOR of Packed Double-Precision Floating-Point Values
1000   void xorpd(XMMRegister dst, XMMRegister src) { Assembler::xorpd(dst, src); }
1001   void xorpd(XMMRegister dst, Address src)     { Assembler::xorpd(dst, src); }
1002   void xorpd(XMMRegister dst, AddressLiteral src);
1003 
1004   // Bitwise Logical XOR of Packed Single-Precision Floating-Point Values
1005   void xorps(XMMRegister dst, XMMRegister src) { Assembler::xorps(dst, src); }
1006   void xorps(XMMRegister dst, Address src)     { Assembler::xorps(dst, src); }
1007   void xorps(XMMRegister dst, AddressLiteral src);
1008 
1009   // Shuffle Bytes
1010   void pshufb(XMMRegister dst, XMMRegister src) { Assembler::pshufb(dst, src); }
1011   void pshufb(XMMRegister dst, Address src)     { Assembler::pshufb(dst, src); }
1012   void pshufb(XMMRegister dst, AddressLiteral src);
1013   // AVX 3-operands instructions
1014 
1015   void vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddsd(dst, nds, src); }
1016   void vaddsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddsd(dst, nds, src); }
1017   void vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1018 
1019   void vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vaddss(dst, nds, src); }
1020   void vaddss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vaddss(dst, nds, src); }
1021   void vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1022 
1023   void vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandpd(dst, nds, src, vector256); }
1024   void vandpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256)     { Assembler::vandpd(dst, nds, src, vector256); }
1025   void vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
1026 
1027   void vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vandps(dst, nds, src, vector256); }
1028   void vandps(XMMRegister dst, XMMRegister nds, Address src, bool vector256)     { Assembler::vandps(dst, nds, src, vector256); }
1029   void vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
1030 
1031   void vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivsd(dst, nds, src); }
1032   void vdivsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivsd(dst, nds, src); }
1033   void vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1034 
1035   void vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vdivss(dst, nds, src); }
1036   void vdivss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vdivss(dst, nds, src); }
1037   void vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1038 
1039   void vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulsd(dst, nds, src); }
1040   void vmulsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulsd(dst, nds, src); }
1041   void vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1042 
1043   void vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vmulss(dst, nds, src); }
1044   void vmulss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vmulss(dst, nds, src); }
1045   void vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1046 
1047   void vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubsd(dst, nds, src); }
1048   void vsubsd(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubsd(dst, nds, src); }
1049   void vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1050 
1051   void vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) { Assembler::vsubss(dst, nds, src); }
1052   void vsubss(XMMRegister dst, XMMRegister nds, Address src)     { Assembler::vsubss(dst, nds, src); }
1053   void vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src);
1054 
1055   // AVX Vector instructions
1056 
1057   void vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
1058   void vxorpd(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorpd(dst, nds, src, vector256); }
1059   void vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
1060 
1061   void vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
1062   void vxorps(XMMRegister dst, XMMRegister nds, Address src, bool vector256) { Assembler::vxorps(dst, nds, src, vector256); }
1063   void vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, bool vector256);
1064 
1065   void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, bool vector256) {
1066     if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
1067       Assembler::vpxor(dst, nds, src, vector256);
1068     else
1069       Assembler::vxorpd(dst, nds, src, vector256);
1070   }
1071   void vpxor(XMMRegister dst, XMMRegister nds, Address src, bool vector256) {
1072     if (UseAVX > 1 || !vector256) // vpxor 256 bit is available only in AVX2
1073       Assembler::vpxor(dst, nds, src, vector256);
1074     else
1075       Assembler::vxorpd(dst, nds, src, vector256);
1076   }
1077 
1078   // Simple version for AVX2 256bit vectors
1079   void vpxor(XMMRegister dst, XMMRegister src) { Assembler::vpxor(dst, dst, src, true); }
1080   void vpxor(XMMRegister dst, Address src) { Assembler::vpxor(dst, dst, src, true); }
1081 
1082   // Move packed integer values from low 128 bit to hign 128 bit in 256 bit vector.
1083   void vinserti128h(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1084     if (UseAVX > 1) // vinserti128h is available only in AVX2
1085       Assembler::vinserti128h(dst, nds, src);
1086     else
1087       Assembler::vinsertf128h(dst, nds, src);
1088   }
1089 
1090   // Carry-Less Multiplication Quadword
1091   void vpclmulldq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1092     // 0x00 - multiply lower 64 bits [0:63]
1093     Assembler::vpclmulqdq(dst, nds, src, 0x00);
1094   }
1095   void vpclmulhdq(XMMRegister dst, XMMRegister nds, XMMRegister src) {
1096     // 0x11 - multiply upper 64 bits [64:127]
1097     Assembler::vpclmulqdq(dst, nds, src, 0x11);
1098   }
1099 
1100   // Data
1101 
1102   void cmov32( Condition cc, Register dst, Address  src);
1103   void cmov32( Condition cc, Register dst, Register src);
1104 
1105   void cmov(   Condition cc, Register dst, Register src) { cmovptr(cc, dst, src); }
1106 
1107   void cmovptr(Condition cc, Register dst, Address  src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1108   void cmovptr(Condition cc, Register dst, Register src) { LP64_ONLY(cmovq(cc, dst, src)) NOT_LP64(cmov32(cc, dst, src)); }
1109 
1110   void movoop(Register dst, jobject obj);
1111   void movoop(Address dst, jobject obj);
1112 
1113   void mov_metadata(Register dst, Metadata* obj);
1114   void mov_metadata(Address dst, Metadata* obj);
1115 
1116   void movptr(ArrayAddress dst, Register src);
1117   // can this do an lea?
1118   void movptr(Register dst, ArrayAddress src);
1119 
1120   void movptr(Register dst, Address src);
1121 
1122 #ifdef _LP64
1123   void movptr(Register dst, AddressLiteral src, Register scratch=rscratch1);
1124 #else
1125   void movptr(Register dst, AddressLiteral src, Register scratch=noreg); // Scratch reg is ignored in 32-bit
1126 #endif
1127 
1128   void movptr(Register dst, intptr_t src);
1129   void movptr(Register dst, Register src);
1130   void movptr(Address dst, intptr_t src);
1131 
1132   void movptr(Address dst, Register src);
1133 
1134   void movptr(Register dst, RegisterOrConstant src) {
1135     if (src.is_constant()) movptr(dst, src.as_constant());
1136     else                   movptr(dst, src.as_register());
1137   }
1138 
1139 #ifdef _LP64
1140   // Generally the next two are only used for moving NULL
1141   // Although there are situations in initializing the mark word where
1142   // they could be used. They are dangerous.
1143 
1144   // They only exist on LP64 so that int32_t and intptr_t are not the same
1145   // and we have ambiguous declarations.
1146 
1147   void movptr(Address dst, int32_t imm32);
1148   void movptr(Register dst, int32_t imm32);
1149 #endif // _LP64
1150 
1151   // to avoid hiding movl
1152   void mov32(AddressLiteral dst, Register src);
1153   void mov32(Register dst, AddressLiteral src);
1154 
1155   // to avoid hiding movb
1156   void movbyte(ArrayAddress dst, int src);
1157 
1158   // Import other mov() methods from the parent class or else
1159   // they will be hidden by the following overriding declaration.
1160   using Assembler::movdl;
1161   using Assembler::movq;
1162   void movdl(XMMRegister dst, AddressLiteral src);
1163   void movq(XMMRegister dst, AddressLiteral src);
1164 
1165   // Can push value or effective address
1166   void pushptr(AddressLiteral src);
1167 
1168   void pushptr(Address src) { LP64_ONLY(pushq(src)) NOT_LP64(pushl(src)); }
1169   void popptr(Address src) { LP64_ONLY(popq(src)) NOT_LP64(popl(src)); }
1170 
1171   void pushoop(jobject obj);
1172   void pushklass(Metadata* obj);
1173 
1174   // sign extend as need a l to ptr sized element
1175   void movl2ptr(Register dst, Address src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(movl(dst, src)); }
1176   void movl2ptr(Register dst, Register src) { LP64_ONLY(movslq(dst, src)) NOT_LP64(if (dst != src) movl(dst, src)); }
1177 
1178   // C2 compiled method's prolog code.
1179   void verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b);
1180 
1181   // clear memory of size 'cnt' qwords, starting at 'base'.
1182   void clear_mem(Register base, Register cnt, Register rtmp);
1183 
1184   // IndexOf strings.
1185   // Small strings are loaded through stack if they cross page boundary.
1186   void string_indexof(Register str1, Register str2,
1187                       Register cnt1, Register cnt2,
1188                       int int_cnt2,  Register result,
1189                       XMMRegister vec, Register tmp);
1190 
1191   // IndexOf for constant substrings with size >= 8 elements
1192   // which don't need to be loaded through stack.
1193   void string_indexofC8(Register str1, Register str2,
1194                       Register cnt1, Register cnt2,
1195                       int int_cnt2,  Register result,
1196                       XMMRegister vec, Register tmp);
1197 
1198     // Smallest code: we don't need to load through stack,
1199     // check string tail.
1200 
1201   // Compare strings.
1202   void string_compare(Register str1, Register str2,
1203                       Register cnt1, Register cnt2, Register result,
1204                       XMMRegister vec1);
1205 
1206   // Compare char[] arrays.
1207   void char_arrays_equals(bool is_array_equ, Register ary1, Register ary2,
1208                           Register limit, Register result, Register chr,
1209                           XMMRegister vec1, XMMRegister vec2);
1210 
1211   // Fill primitive arrays
1212   void generate_fill(BasicType t, bool aligned,
1213                      Register to, Register value, Register count,
1214                      Register rtmp, XMMRegister xtmp);
1215 
1216   void encode_iso_array(Register src, Register dst, Register len,
1217                         XMMRegister tmp1, XMMRegister tmp2, XMMRegister tmp3,
1218                         XMMRegister tmp4, Register tmp5, Register result);
1219 
1220 #ifdef _LP64
1221   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2);
1222   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1223                              Register y, Register y_idx, Register z,
1224                              Register carry, Register product,
1225                              Register idx, Register kdx);
1226   void multiply_add_128_x_128(Register x_xstart, Register y, Register z,
1227                               Register yz_idx, Register idx,
1228                               Register carry, Register product, int offset);
1229   void multiply_128_x_128_bmi2_loop(Register y, Register z,
1230                                     Register carry, Register carry2,
1231                                     Register idx, Register jdx,
1232                                     Register yz_idx1, Register yz_idx2,
1233                                     Register tmp, Register tmp3, Register tmp4);
1234   void multiply_128_x_128_loop(Register x_xstart, Register y, Register z,
1235                                Register yz_idx, Register idx, Register jdx,
1236                                Register carry, Register product,
1237                                Register carry2);
1238   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen,
1239                        Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5);
1240 #endif
1241 
1242   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1243   void update_byte_crc32(Register crc, Register val, Register table);
1244   void kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp);
1245   // Fold 128-bit data chunk
1246   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset);
1247   void fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf);
1248   // Fold 8-bit data
1249   void fold_8bit_crc32(Register crc, Register table, Register tmp);
1250   void fold_8bit_crc32(XMMRegister crc, Register table, XMMRegister xtmp, Register tmp);
1251 
1252 #undef VIRTUAL
1253 
1254 };
1255 
1256 /**
1257  * class SkipIfEqual:
1258  *
1259  * Instantiating this class will result in assembly code being output that will
1260  * jump around any code emitted between the creation of the instance and it's
1261  * automatic destruction at the end of a scope block, depending on the value of
1262  * the flag passed to the constructor, which will be checked at run-time.
1263  */
1264 class SkipIfEqual {
1265  private:
1266   MacroAssembler* _masm;
1267   Label _label;
1268 
1269  public:
1270    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1271    ~SkipIfEqual();
1272 };
1273 
1274 #endif // CPU_X86_VM_MACROASSEMBLER_X86_HPP