1 /*
2 * Copyright (c) 1997, 2011, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #ifndef CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
27 #define CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP
28
29 #include "asm/register.hpp"
30
31 // definitions of various symbolic names for machine registers
32
33 // First intercalls between C and Java which use 8 general registers
34 // and 8 floating registers
35
36 // we also have to copy between x86 and ARM registers but that's a
37 // secondary complication -- not all code employing C call convention
38 // executes as x86 code though -- we generate some of it
39
40 class Argument VALUE_OBJ_CLASS_SPEC {
41 public:
42 enum {
43 n_int_register_parameters_c = 8, // r0, r1, ... r7 (c_rarg0, c_rarg1, ...)
44 n_float_register_parameters_c = 8, // v0, v1, ... v7 (c_farg0, c_farg1, ... )
45
46 n_int_register_parameters_j = 8, // r1, ... r7, r0 (rj_rarg0, j_rarg1, ...
47 n_float_register_parameters_j = 8 // v0, v1, ... v7 (j_farg0, j_farg1, ...
48 };
49 };
50
51 REGISTER_DECLARATION(Register, c_rarg0, r0);
52 REGISTER_DECLARATION(Register, c_rarg1, r1);
53 REGISTER_DECLARATION(Register, c_rarg2, r2);
54 REGISTER_DECLARATION(Register, c_rarg3, r3);
55 REGISTER_DECLARATION(Register, c_rarg4, r4);
56 REGISTER_DECLARATION(Register, c_rarg5, r5);
57 REGISTER_DECLARATION(Register, c_rarg6, r6);
58 REGISTER_DECLARATION(Register, c_rarg7, r7);
59
60 REGISTER_DECLARATION(FloatRegister, c_farg0, v0);
61 REGISTER_DECLARATION(FloatRegister, c_farg1, v1);
62 REGISTER_DECLARATION(FloatRegister, c_farg2, v2);
63 REGISTER_DECLARATION(FloatRegister, c_farg3, v3);
64 REGISTER_DECLARATION(FloatRegister, c_farg4, v4);
65 REGISTER_DECLARATION(FloatRegister, c_farg5, v5);
66 REGISTER_DECLARATION(FloatRegister, c_farg6, v6);
67 REGISTER_DECLARATION(FloatRegister, c_farg7, v7);
68
69 // Symbolically name the register arguments used by the Java calling convention.
70 // We have control over the convention for java so we can do what we please.
71 // What pleases us is to offset the java calling convention so that when
72 // we call a suitable jni method the arguments are lined up and we don't
73 // have to do much shuffling. A suitable jni method is non-static and a
74 // small number of arguments
75 //
76 // |--------------------------------------------------------------------|
77 // | c_rarg0 c_rarg1 c_rarg2 c_rarg3 c_rarg4 c_rarg5 c_rarg6 c_rarg7 |
78 // |--------------------------------------------------------------------|
79 // | r0 r1 r2 r3 r4 r5 r6 r7 |
80 // |--------------------------------------------------------------------|
81 // | j_rarg7 j_rarg0 j_rarg1 j_rarg2 j_rarg3 j_rarg4 j_rarg5 j_rarg6 |
82 // |--------------------------------------------------------------------|
83
84
85 REGISTER_DECLARATION(Register, j_rarg0, c_rarg1);
86 REGISTER_DECLARATION(Register, j_rarg1, c_rarg2);
87 REGISTER_DECLARATION(Register, j_rarg2, c_rarg3);
88 REGISTER_DECLARATION(Register, j_rarg3, c_rarg4);
89 REGISTER_DECLARATION(Register, j_rarg4, c_rarg5);
90 REGISTER_DECLARATION(Register, j_rarg5, c_rarg6);
91 REGISTER_DECLARATION(Register, j_rarg6, c_rarg7);
92 REGISTER_DECLARATION(Register, j_rarg7, c_rarg0);
93
94 // Java floating args are passed as per C
95
96 REGISTER_DECLARATION(FloatRegister, j_farg0, v0);
97 REGISTER_DECLARATION(FloatRegister, j_farg1, v1);
98 REGISTER_DECLARATION(FloatRegister, j_farg2, v2);
99 REGISTER_DECLARATION(FloatRegister, j_farg3, v3);
100 REGISTER_DECLARATION(FloatRegister, j_farg4, v4);
101 REGISTER_DECLARATION(FloatRegister, j_farg5, v5);
102 REGISTER_DECLARATION(FloatRegister, j_farg6, v6);
103 REGISTER_DECLARATION(FloatRegister, j_farg7, v7);
104
105 // registers used to hold VM data either temporarily within a method
106 // or across method calls
107
108 // volatile (caller-save) registers
109
110 // r8 is used for indirect result location return
111 // we use it and r9 as scratch registers
112 REGISTER_DECLARATION(Register, rscratch1, r8);
113 REGISTER_DECLARATION(Register, rscratch2, r9);
114
115 // current method -- must be in a call-clobbered register
116 REGISTER_DECLARATION(Register, rmethod, r12);
117
118 // non-volatile (callee-save) registers are r16-29
119 // of which the following are dedicated global state
120
121 // link register
122 REGISTER_DECLARATION(Register, lr, r30);
123 // frame pointer
124 REGISTER_DECLARATION(Register, rfp, r29);
125 // current thread
126 REGISTER_DECLARATION(Register, rthread, r28);
127 // base of heap
128 REGISTER_DECLARATION(Register, rheapbase, r27);
129 // constant pool cache
130 REGISTER_DECLARATION(Register, rcpool, r26);
131 // monitors allocated on stack
132 REGISTER_DECLARATION(Register, rmonitors, r25);
133 // locals on stack
134 REGISTER_DECLARATION(Register, rlocals, r24);
135 // bytecode pointer
136 REGISTER_DECLARATION(Register, rbcp, r22);
137 // Dispatch table base
138 REGISTER_DECLARATION(Register, rdispatch, r21);
139 // Java stack pointer
140 REGISTER_DECLARATION(Register, esp, r20);
141
142 // TODO : x86 uses rbp to save SP in method handle code
143 // we may need to do the same with fp
144 // JSR 292 fixed register usages:
145 //REGISTER_DECLARATION(Register, r_mh_SP_save, r29);
146
147 #define assert_cond(ARG1) assert(ARG1, #ARG1)
148
149 namespace asm_util {
150 uint32_t encode_logical_immediate(bool is32, uint64_t imm);
151 };
152
153 using namespace asm_util;
154
155
156 class Assembler;
157
158 class Instruction_aarch64 {
159 unsigned insn;
160 #ifdef ASSERT
161 unsigned bits;
162 #endif
163 Assembler *assem;
164
165 public:
166
167 Instruction_aarch64(class Assembler *as) {
168 #ifdef ASSERT
169 bits = 0;
170 #endif
171 insn = 0;
172 assem = as;
173 }
174
175 inline ~Instruction_aarch64();
176
177 unsigned &get_insn() { return insn; }
178 #ifdef ASSERT
179 unsigned &get_bits() { return bits; }
180 #endif
181
182 static inline int32_t extend(unsigned val, int hi = 31, int lo = 0) {
183 union {
184 unsigned u;
185 int n;
186 };
187
188 u = val << (31 - hi);
189 n = n >> (31 - hi + lo);
190 return n;
191 }
192
193 static inline uint32_t extract(uint32_t val, int msb, int lsb) {
194 int nbits = msb - lsb + 1;
195 assert_cond(msb >= lsb);
196 uint32_t mask = (1U << nbits) - 1;
197 uint32_t result = val >> lsb;
198 result &= mask;
199 return result;
200 }
201
202 static inline int32_t sextract(uint32_t val, int msb, int lsb) {
203 uint32_t uval = extract(val, msb, lsb);
204 return extend(uval, msb - lsb);
205 }
206
207 static void patch(address a, int msb, int lsb, unsigned long val) {
208 int nbits = msb - lsb + 1;
209 guarantee(val < (1U << nbits), "Field too big for insn");
210 assert_cond(msb >= lsb);
211 unsigned mask = (1U << nbits) - 1;
212 val <<= lsb;
213 mask <<= lsb;
214 unsigned target = *(unsigned *)a;
215 target &= ~mask;
216 target |= val;
217 *(unsigned *)a = target;
218 }
219
220 static void spatch(address a, int msb, int lsb, long val) {
221 int nbits = msb - lsb + 1;
222 long chk = val >> (nbits - 1);
223 guarantee (chk == -1 || chk == 0, "Field too big for insn");
224 unsigned uval = val;
225 unsigned mask = (1U << nbits) - 1;
226 uval &= mask;
227 uval <<= lsb;
228 mask <<= lsb;
229 unsigned target = *(unsigned *)a;
230 target &= ~mask;
231 target |= uval;
232 *(unsigned *)a = target;
233 }
234
235 void f(unsigned val, int msb, int lsb) {
236 int nbits = msb - lsb + 1;
237 guarantee(val < (1U << nbits), "Field too big for insn");
238 assert_cond(msb >= lsb);
239 unsigned mask = (1U << nbits) - 1;
240 val <<= lsb;
241 mask <<= lsb;
242 insn |= val;
243 assert_cond((bits & mask) == 0);
244 #ifdef ASSERT
245 bits |= mask;
246 #endif
247 }
248
249 void f(unsigned val, int bit) {
250 f(val, bit, bit);
251 }
252
253 void sf(long val, int msb, int lsb) {
254 int nbits = msb - lsb + 1;
255 long chk = val >> (nbits - 1);
256 guarantee (chk == -1 || chk == 0, "Field too big for insn");
257 unsigned uval = val;
258 unsigned mask = (1U << nbits) - 1;
259 uval &= mask;
260 f(uval, lsb + nbits - 1, lsb);
261 }
262
263 void rf(Register r, int lsb) {
264 f(r->encoding_nocheck(), lsb + 4, lsb);
265 }
266
267 // reg|ZR
268 void zrf(Register r, int lsb) {
269 f(r->encoding_nocheck() - (r == zr), lsb + 4, lsb);
270 }
271
272 // reg|SP
273 void srf(Register r, int lsb) {
274 f(r == sp ? 31 : r->encoding_nocheck(), lsb + 4, lsb);
275 }
276
277 void rf(FloatRegister r, int lsb) {
278 f(r->encoding_nocheck(), lsb + 4, lsb);
279 }
280
281 unsigned get(int msb = 31, int lsb = 0) {
282 int nbits = msb - lsb + 1;
283 unsigned mask = ((1U << nbits) - 1) << lsb;
284 assert_cond(bits & mask == mask);
285 return (insn & mask) >> lsb;
286 }
287
288 void fixed(unsigned value, unsigned mask) {
289 assert_cond ((mask & bits) == 0);
290 #ifdef ASSERT
291 bits |= mask;
292 #endif
293 insn |= value;
294 }
295 };
296
297 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
298
299 class PrePost {
300 int _offset;
301 Register _r;
302 public:
303 PrePost(Register reg, int o) : _r(reg), _offset(o) { }
304 int offset() { return _offset; }
305 Register reg() { return _r; }
306 };
307
308 class Pre : public PrePost {
309 public:
310 Pre(Register reg, int o) : PrePost(reg, o) { }
311 };
312 class Post : public PrePost {
313 public:
314 Post(Register reg, int o) : PrePost(reg, o) { }
315 };
316
317 namespace ext
318 {
319 enum operation { uxtb, uxth, uxtw, uxtx, sxtb, sxth, sxtw, sxtx };
320 };
321
322 // abs methods which cannot overflow and so are well-defined across
323 // the entire domain of integer types.
324 static inline unsigned int uabs(unsigned int n) {
325 union {
326 unsigned int result;
327 int value;
328 };
329 result = n;
330 if (value < 0) result = -result;
331 return result;
332 }
333 static inline unsigned long uabs(unsigned long n) {
334 union {
335 unsigned long result;
336 long value;
337 };
338 result = n;
339 if (value < 0) result = -result;
340 return result;
341 }
342 static inline unsigned long uabs(long n) { return uabs((unsigned long)n); }
343 static inline unsigned long uabs(int n) { return uabs((unsigned int)n); }
344
345 // Addressing modes
346 class Address VALUE_OBJ_CLASS_SPEC {
347 public:
348
349 enum mode { no_mode, base_plus_offset, pre, post, pcrel,
350 base_plus_offset_reg, literal };
351
352 // Shift and extend for base reg + reg offset addressing
353 class extend {
354 int _option, _shift;
355 ext::operation _op;
356 public:
357 extend() { }
358 extend(int s, int o, ext::operation op) : _shift(s), _option(o), _op(op) { }
359 int option() const{ return _option; }
360 int shift() const { return _shift; }
361 ext::operation op() const { return _op; }
362 };
363 class uxtw : public extend {
364 public:
365 uxtw(int shift = -1): extend(shift, 0b010, ext::uxtw) { }
366 };
367 class lsl : public extend {
368 public:
369 lsl(int shift = -1): extend(shift, 0b011, ext::uxtx) { }
370 };
371 class sxtw : public extend {
372 public:
373 sxtw(int shift = -1): extend(shift, 0b110, ext::sxtw) { }
374 };
375 class sxtx : public extend {
376 public:
377 sxtx(int shift = -1): extend(shift, 0b111, ext::sxtx) { }
378 };
379
380 private:
381 Register _base;
382 Register _index;
383 long _offset;
384 enum mode _mode;
385 extend _ext;
386
387 RelocationHolder _rspec;
388
389 // Typically we use AddressLiterals we want to use their rval
390 // However in some situations we want the lval (effect address) of
391 // the item. We provide a special factory for making those lvals.
392 bool _is_lval;
393
394 // If the target is far we'll need to load the ea of this to a
395 // register to reach it. Otherwise if near we can do PC-relative
396 // addressing.
397 address _target;
398
399 public:
400 Address()
401 : _mode(no_mode) { }
402 Address(Register r)
403 : _mode(base_plus_offset), _base(r), _offset(0), _index(noreg), _target(0) { }
404 Address(Register r, int o)
405 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
406 Address(Register r, long o)
407 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
408 Address(Register r, unsigned long o)
409 : _mode(base_plus_offset), _base(r), _offset(o), _index(noreg), _target(0) { }
410 #ifdef ASSERT
411 Address(Register r, ByteSize disp)
412 : _mode(base_plus_offset), _base(r), _offset(in_bytes(disp)),
413 _index(noreg), _target(0) { }
414 #endif
415 Address(Register r, Register r1, extend ext = lsl())
416 : _mode(base_plus_offset_reg), _base(r), _index(r1),
417 _ext(ext), _offset(0), _target(0) { }
418 Address(Pre p)
419 : _mode(pre), _base(p.reg()), _offset(p.offset()) { }
420 Address(Post p)
421 : _mode(post), _base(p.reg()), _offset(p.offset()), _target(0) { }
422 Address(address target, RelocationHolder const& rspec)
423 : _mode(literal),
424 _rspec(rspec),
425 _is_lval(false),
426 _target(target) { }
427 Address(address target, relocInfo::relocType rtype = relocInfo::external_word_type);
428 Address(Register base, RegisterOrConstant index, extend ext = lsl())
429 : _base (base),
430 _ext(ext), _offset(0), _target(0) {
431 if (index.is_register()) {
432 _mode = base_plus_offset_reg;
433 _index = index.as_register();
434 } else {
435 guarantee(ext.option() == ext::uxtx, "should be");
436 assert(index.is_constant(), "should be");
437 _mode = base_plus_offset;
438 _offset = index.as_constant() << ext.shift();
439 }
440 }
441
442 Register base() const {
443 guarantee((_mode == base_plus_offset | _mode == base_plus_offset_reg
444 | _mode == post),
445 "wrong mode");
446 return _base;
447 }
448 long offset() const {
449 return _offset;
450 }
451 Register index() const {
452 return _index;
453 }
454 mode getMode() const {
455 return _mode;
456 }
457 bool uses(Register reg) const { return _base == reg || _index == reg; }
458 address target() const { return _target; }
459 const RelocationHolder& rspec() const { return _rspec; }
460
461 void encode(Instruction_aarch64 *i) const {
462 i->f(0b111, 29, 27);
463 i->srf(_base, 5);
464
465 switch(_mode) {
466 case base_plus_offset:
467 {
468 unsigned size = i->get(31, 30);
469 if (i->get(26, 26) && i->get(23, 23)) {
470 // SIMD Q Type - Size = 128 bits
471 assert(size == 0, "bad size");
472 size = 0b100;
473 }
474 unsigned mask = (1 << size) - 1;
475 if (_offset < 0 || _offset & mask)
476 {
477 i->f(0b00, 25, 24);
478 i->f(0, 21), i->f(0b00, 11, 10);
479 i->sf(_offset, 20, 12);
480 } else {
481 i->f(0b01, 25, 24);
482 i->f(_offset >> size, 21, 10);
483 }
484 }
485 break;
486
487 case base_plus_offset_reg:
488 {
489 i->f(0b00, 25, 24);
490 i->f(1, 21);
491 i->rf(_index, 16);
492 i->f(_ext.option(), 15, 13);
493 unsigned size = i->get(31, 30);
494 if (i->get(26, 26) && i->get(23, 23)) {
495 // SIMD Q Type - Size = 128 bits
496 assert(size == 0, "bad size");
497 size = 0b100;
498 }
499 if (size == 0) // It's a byte
500 i->f(_ext.shift() >= 0, 12);
501 else {
502 if (_ext.shift() > 0)
503 assert(_ext.shift() == (int)size, "bad shift");
504 i->f(_ext.shift() > 0, 12);
505 }
506 i->f(0b10, 11, 10);
507 }
508 break;
509
510 case pre:
511 i->f(0b00, 25, 24);
512 i->f(0, 21), i->f(0b11, 11, 10);
513 i->sf(_offset, 20, 12);
514 break;
515
516 case post:
517 i->f(0b00, 25, 24);
518 i->f(0, 21), i->f(0b01, 11, 10);
519 i->sf(_offset, 20, 12);
520 break;
521
522 default:
523 ShouldNotReachHere();
524 }
525 }
526
527 void encode_pair(Instruction_aarch64 *i) const {
528 switch(_mode) {
529 case base_plus_offset:
530 i->f(0b010, 25, 23);
531 break;
532 case pre:
533 i->f(0b011, 25, 23);
534 break;
535 case post:
536 i->f(0b001, 25, 23);
537 break;
538 default:
539 ShouldNotReachHere();
540 }
541
542 unsigned size; // Operand shift in 32-bit words
543
544 if (i->get(26, 26)) { // float
545 switch(i->get(31, 30)) {
546 case 0b10:
547 size = 2; break;
548 case 0b01:
549 size = 1; break;
550 case 0b00:
551 size = 0; break;
552 default:
553 ShouldNotReachHere();
554 }
555 } else {
556 size = i->get(31, 31);
557 }
558
559 size = 4 << size;
560 guarantee(_offset % size == 0, "bad offset");
561 i->sf(_offset / size, 21, 15);
562 i->srf(_base, 5);
563 }
564
565 void encode_nontemporal_pair(Instruction_aarch64 *i) const {
566 // Only base + offset is allowed
567 i->f(0b000, 25, 23);
568 unsigned size = i->get(31, 31);
569 size = 4 << size;
570 guarantee(_offset % size == 0, "bad offset");
571 i->sf(_offset / size, 21, 15);
572 i->srf(_base, 5);
573 guarantee(_mode == Address::base_plus_offset,
574 "Bad addressing mode for non-temporal op");
575 }
576
577 void lea(MacroAssembler *, Register) const;
578
579 static bool offset_ok_for_immed(long offset, int shift = 0) {
580 unsigned mask = (1 << shift) - 1;
581 if (offset < 0 || offset & mask) {
582 return (uabs(offset) < (1 << (20 - 12))); // Unscaled offset
583 } else {
584 return ((offset >> shift) < (1 << (21 - 10 + 1))); // Scaled, unsigned offset
585 }
586 }
587 };
588
589 // Convience classes
590 class RuntimeAddress: public Address {
591
592 public:
593
594 RuntimeAddress(address target) : Address(target, relocInfo::runtime_call_type) {}
595
596 };
597
598 class OopAddress: public Address {
599
600 public:
601
602 OopAddress(address target) : Address(target, relocInfo::oop_type){}
603
604 };
605
606 class ExternalAddress: public Address {
607 private:
608 static relocInfo::relocType reloc_for_target(address target) {
609 // Sometimes ExternalAddress is used for values which aren't
610 // exactly addresses, like the card table base.
611 // external_word_type can't be used for values in the first page
612 // so just skip the reloc in that case.
613 return external_word_Relocation::can_be_relocated(target) ? relocInfo::external_word_type : relocInfo::none;
614 }
615
616 public:
617
618 ExternalAddress(address target) : Address(target, reloc_for_target(target)) {}
619
620 };
621
622 class InternalAddress: public Address {
623
624 public:
625
626 InternalAddress(address target) : Address(target, relocInfo::internal_word_type) {}
627 };
628
629 const int FPUStateSizeInWords = 32 * 2;
630 typedef enum {
631 PLDL1KEEP = 0b00000, PLDL1STRM, PLDL2KEEP, PLDL2STRM, PLDL3KEEP, PLDL3STRM,
632 PSTL1KEEP = 0b10000, PSTL1STRM, PSTL2KEEP, PSTL2STRM, PSTL3KEEP, PSTL3STRM,
633 PLIL1KEEP = 0b01000, PLIL1STRM, PLIL2KEEP, PLIL2STRM, PLIL3KEEP, PLIL3STRM
634 } prfop;
635
636 class Assembler : public AbstractAssembler {
637
638 #ifndef PRODUCT
639 static const unsigned long asm_bp;
640
641 void emit_long(jint x) {
642 if ((unsigned long)pc() == asm_bp)
643 asm volatile ("nop");
644 AbstractAssembler::emit_int32(x);
645 }
646 #else
647 void emit_long(jint x) {
648 AbstractAssembler::emit_int32(x);
649 }
650 #endif
651
652 public:
653
654 enum { instruction_size = 4 };
655
656 Address adjust(Register base, int offset, bool preIncrement) {
657 if (preIncrement)
658 return Address(Pre(base, offset));
659 else
660 return Address(Post(base, offset));
661 }
662
663 Address pre(Register base, int offset) {
664 return adjust(base, offset, true);
665 }
666
667 Address post (Register base, int offset) {
668 return adjust(base, offset, false);
669 }
670
671 Instruction_aarch64* current;
672
673 void set_current(Instruction_aarch64* i) { current = i; }
674
675 void f(unsigned val, int msb, int lsb) {
676 current->f(val, msb, lsb);
677 }
678 void f(unsigned val, int msb) {
679 current->f(val, msb, msb);
680 }
681 void sf(long val, int msb, int lsb) {
682 current->sf(val, msb, lsb);
683 }
684 void rf(Register reg, int lsb) {
685 current->rf(reg, lsb);
686 }
687 void srf(Register reg, int lsb) {
688 current->srf(reg, lsb);
689 }
690 void zrf(Register reg, int lsb) {
691 current->zrf(reg, lsb);
692 }
693 void rf(FloatRegister reg, int lsb) {
694 current->rf(reg, lsb);
695 }
696 void fixed(unsigned value, unsigned mask) {
697 current->fixed(value, mask);
698 }
699
700 void emit() {
701 emit_long(current->get_insn());
702 assert_cond(current->get_bits() == 0xffffffff);
703 current = NULL;
704 }
705
706 typedef void (Assembler::* uncond_branch_insn)(address dest);
707 typedef void (Assembler::* compare_and_branch_insn)(Register Rt, address dest);
708 typedef void (Assembler::* test_and_branch_insn)(Register Rt, int bitpos, address dest);
709 typedef void (Assembler::* prefetch_insn)(address target, prfop);
710
711 void wrap_label(Label &L, uncond_branch_insn insn);
712 void wrap_label(Register r, Label &L, compare_and_branch_insn insn);
713 void wrap_label(Register r, int bitpos, Label &L, test_and_branch_insn insn);
714 void wrap_label(Label &L, prfop, prefetch_insn insn);
715
716 // PC-rel. addressing
717
718 void adr(Register Rd, address dest);
719 void _adrp(Register Rd, address dest);
720
721 void adr(Register Rd, const Address &dest);
722 void _adrp(Register Rd, const Address &dest);
723
724 void adr(Register Rd, Label &L) {
725 wrap_label(Rd, L, &Assembler::Assembler::adr);
726 }
727 void _adrp(Register Rd, Label &L) {
728 wrap_label(Rd, L, &Assembler::_adrp);
729 }
730
731 void adrp(Register Rd, const Address &dest, unsigned long &offset);
732
733 #undef INSN
734
735 void add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
736 int negated_op);
737
738 // Add/subtract (immediate)
739 #define INSN(NAME, decode, negated) \
740 void NAME(Register Rd, Register Rn, unsigned imm, unsigned shift) { \
741 starti; \
742 f(decode, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10); \
743 zrf(Rd, 0), srf(Rn, 5); \
744 } \
745 \
746 void NAME(Register Rd, Register Rn, unsigned imm) { \
747 starti; \
748 add_sub_immediate(Rd, Rn, imm, decode, negated); \
749 }
750
751 INSN(addsw, 0b001, 0b011);
752 INSN(subsw, 0b011, 0b001);
753 INSN(adds, 0b101, 0b111);
754 INSN(subs, 0b111, 0b101);
755
756 #undef INSN
757
758 #define INSN(NAME, decode, negated) \
759 void NAME(Register Rd, Register Rn, unsigned imm) { \
760 starti; \
761 add_sub_immediate(Rd, Rn, imm, decode, negated); \
762 }
763
764 INSN(addw, 0b000, 0b010);
765 INSN(subw, 0b010, 0b000);
766 INSN(add, 0b100, 0b110);
767 INSN(sub, 0b110, 0b100);
768
769 #undef INSN
770
771 // Logical (immediate)
772 #define INSN(NAME, decode, is32) \
773 void NAME(Register Rd, Register Rn, uint64_t imm) { \
774 starti; \
775 uint32_t val = encode_logical_immediate(is32, imm); \
776 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
777 srf(Rd, 0), zrf(Rn, 5); \
778 }
779
780 INSN(andw, 0b000, true);
781 INSN(orrw, 0b001, true);
782 INSN(eorw, 0b010, true);
783 INSN(andr, 0b100, false);
784 INSN(orr, 0b101, false);
785 INSN(eor, 0b110, false);
786
787 #undef INSN
788
789 #define INSN(NAME, decode, is32) \
790 void NAME(Register Rd, Register Rn, uint64_t imm) { \
791 starti; \
792 uint32_t val = encode_logical_immediate(is32, imm); \
793 f(decode, 31, 29), f(0b100100, 28, 23), f(val, 22, 10); \
794 zrf(Rd, 0), zrf(Rn, 5); \
795 }
796
797 INSN(ands, 0b111, false);
798 INSN(andsw, 0b011, true);
799
800 #undef INSN
801
802 // Move wide (immediate)
803 #define INSN(NAME, opcode) \
804 void NAME(Register Rd, unsigned imm, unsigned shift = 0) { \
805 assert_cond((shift/16)*16 == shift); \
806 starti; \
807 f(opcode, 31, 29), f(0b100101, 28, 23), f(shift/16, 22, 21), \
808 f(imm, 20, 5); \
809 rf(Rd, 0); \
810 }
811
812 INSN(movnw, 0b000);
813 INSN(movzw, 0b010);
814 INSN(movkw, 0b011);
815 INSN(movn, 0b100);
816 INSN(movz, 0b110);
817 INSN(movk, 0b111);
818
819 #undef INSN
820
821 // Bitfield
822 #define INSN(NAME, opcode) \
823 void NAME(Register Rd, Register Rn, unsigned immr, unsigned imms) { \
824 starti; \
825 f(opcode, 31, 22), f(immr, 21, 16), f(imms, 15, 10); \
826 rf(Rn, 5), rf(Rd, 0); \
827 }
828
829 INSN(sbfmw, 0b0001001100);
830 INSN(bfmw, 0b0011001100);
831 INSN(ubfmw, 0b0101001100);
832 INSN(sbfm, 0b1001001101);
833 INSN(bfm, 0b1011001101);
834 INSN(ubfm, 0b1101001101);
835
836 #undef INSN
837
838 // Extract
839 #define INSN(NAME, opcode) \
840 void NAME(Register Rd, Register Rn, Register Rm, unsigned imms) { \
841 starti; \
842 f(opcode, 31, 21), f(imms, 15, 10); \
843 rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
844 }
845
846 INSN(extrw, 0b00010011100);
847 INSN(extr, 0b10010011110);
848
849 #undef INSN
850
851 // The maximum range of a branch is fixed for the AArch64
852 // architecture. In debug mode we shrink it in order to test
853 // trampolines, but not so small that branches in the interpreter
854 // are out of range.
855 static const unsigned long branch_range = NOT_DEBUG(128 * M) DEBUG_ONLY(2 * M);
856
857 static bool reachable_from_branch_at(address branch, address target) {
858 return uabs(target - branch) < branch_range;
859 }
860
861 // Unconditional branch (immediate)
862 #define INSN(NAME, opcode) \
863 void NAME(address dest) { \
864 starti; \
865 long offset = (dest - pc()) >> 2; \
866 DEBUG_ONLY(assert(reachable_from_branch_at(pc(), dest), "debug only")); \
867 f(opcode, 31), f(0b00101, 30, 26), sf(offset, 25, 0); \
868 } \
869 void NAME(Label &L) { \
870 wrap_label(L, &Assembler::NAME); \
871 } \
872 void NAME(const Address &dest);
873
874 INSN(b, 0);
875 INSN(bl, 1);
876
877 #undef INSN
878
879 // Compare & branch (immediate)
880 #define INSN(NAME, opcode) \
881 void NAME(Register Rt, address dest) { \
882 long offset = (dest - pc()) >> 2; \
883 starti; \
884 f(opcode, 31, 24), sf(offset, 23, 5), rf(Rt, 0); \
885 } \
886 void NAME(Register Rt, Label &L) { \
887 wrap_label(Rt, L, &Assembler::NAME); \
888 }
889
890 INSN(cbzw, 0b00110100);
891 INSN(cbnzw, 0b00110101);
892 INSN(cbz, 0b10110100);
893 INSN(cbnz, 0b10110101);
894
895 #undef INSN
896
897 // Test & branch (immediate)
898 #define INSN(NAME, opcode) \
899 void NAME(Register Rt, int bitpos, address dest) { \
900 long offset = (dest - pc()) >> 2; \
901 int b5 = bitpos >> 5; \
902 bitpos &= 0x1f; \
903 starti; \
904 f(b5, 31), f(opcode, 30, 24), f(bitpos, 23, 19), sf(offset, 18, 5); \
905 rf(Rt, 0); \
906 } \
907 void NAME(Register Rt, int bitpos, Label &L) { \
908 wrap_label(Rt, bitpos, L, &Assembler::NAME); \
909 }
910
911 INSN(tbz, 0b0110110);
912 INSN(tbnz, 0b0110111);
913
914 #undef INSN
915
916 // Conditional branch (immediate)
917 enum Condition
918 {EQ, NE, HS, CS=HS, LO, CC=LO, MI, PL, VS, VC, HI, LS, GE, LT, GT, LE, AL, NV};
919
920 void br(Condition cond, address dest) {
921 long offset = (dest - pc()) >> 2;
922 starti;
923 f(0b0101010, 31, 25), f(0, 24), sf(offset, 23, 5), f(0, 4), f(cond, 3, 0);
924 }
925
926 #define INSN(NAME, cond) \
927 void NAME(address dest) { \
928 br(cond, dest); \
929 }
930
931 INSN(beq, EQ);
932 INSN(bne, NE);
933 INSN(bhs, HS);
934 INSN(bcs, CS);
935 INSN(blo, LO);
936 INSN(bcc, CC);
937 INSN(bmi, MI);
938 INSN(bpl, PL);
939 INSN(bvs, VS);
940 INSN(bvc, VC);
941 INSN(bhi, HI);
942 INSN(bls, LS);
943 INSN(bge, GE);
944 INSN(blt, LT);
945 INSN(bgt, GT);
946 INSN(ble, LE);
947 INSN(bal, AL);
948 INSN(bnv, NV);
949
950 void br(Condition cc, Label &L);
951
952 #undef INSN
953
954 // Exception generation
955 void generate_exception(int opc, int op2, int LL, unsigned imm) {
956 starti;
957 f(0b11010100, 31, 24);
958 f(opc, 23, 21), f(imm, 20, 5), f(op2, 4, 2), f(LL, 1, 0);
959 }
960
961 #define INSN(NAME, opc, op2, LL) \
962 void NAME(unsigned imm) { \
963 generate_exception(opc, op2, LL, imm); \
964 }
965
966 INSN(svc, 0b000, 0, 0b01);
967 INSN(hvc, 0b000, 0, 0b10);
968 INSN(smc, 0b000, 0, 0b11);
969 INSN(brk, 0b001, 0, 0b00);
970 INSN(hlt, 0b010, 0, 0b00);
971 INSN(dpcs1, 0b101, 0, 0b01);
972 INSN(dpcs2, 0b101, 0, 0b10);
973 INSN(dpcs3, 0b101, 0, 0b11);
974
975 #undef INSN
976
977 // System
978 void system(int op0, int op1, int CRn, int CRm, int op2,
979 Register rt = (Register)0b11111)
980 {
981 starti;
982 f(0b11010101000, 31, 21);
983 f(op0, 20, 19);
984 f(op1, 18, 16);
985 f(CRn, 15, 12);
986 f(CRm, 11, 8);
987 f(op2, 7, 5);
988 rf(rt, 0);
989 }
990
991 void hint(int imm) {
992 system(0b00, 0b011, 0b0010, imm, 0b000);
993 }
994
995 void nop(int count = 1) {
996 for (int i = 0; i < count; i++)
997 hint(0);
998 }
999 // we only provide mrs and msr for the special purpose system
1000 // registers where op1 (instr[20:19]) == 11 and, (currently) only
1001 // use it for FPSR n.b msr has L (instr[21]) == 0 mrs has L == 1
1002
1003 void msr(int op1, int CRn, int CRm, int op2, Register rt) {
1004 starti;
1005 f(0b1101010100011, 31, 19);
1006 f(op1, 18, 16);
1007 f(CRn, 15, 12);
1008 f(CRm, 11, 8);
1009 f(op2, 7, 5);
1010 // writing zr is ok
1011 zrf(rt, 0);
1012 }
1013
1014 void mrs(int op1, int CRn, int CRm, int op2, Register rt) {
1015 starti;
1016 f(0b1101010100111, 31, 19);
1017 f(op1, 18, 16);
1018 f(CRn, 15, 12);
1019 f(CRm, 11, 8);
1020 f(op2, 7, 5);
1021 // reading to zr is a mistake
1022 rf(rt, 0);
1023 }
1024
1025 enum barrier {OSHLD = 0b0001, OSHST, OSH, NSHLD=0b0101, NSHST, NSH,
1026 ISHLD = 0b1001, ISHST, ISH, LD=0b1101, ST, SY};
1027
1028 void dsb(barrier imm) {
1029 system(0b00, 0b011, 0b00011, imm, 0b100);
1030 }
1031
1032 void dmb(barrier imm) {
1033 system(0b00, 0b011, 0b00011, imm, 0b101);
1034 }
1035
1036 void isb() {
1037 system(0b00, 0b011, 0b00011, SY, 0b110);
1038 }
1039
1040 void dc(Register Rt) {
1041 system(0b01, 0b011, 0b0111, 0b1011, 0b001, Rt);
1042 }
1043
1044 void ic(Register Rt) {
1045 system(0b01, 0b011, 0b0111, 0b0101, 0b001, Rt);
1046 }
1047
1048 // A more convenient access to dmb for our purposes
1049 enum Membar_mask_bits {
1050 // We can use ISH for a barrier because the ARM ARM says "This
1051 // architecture assumes that all Processing Elements that use the
1052 // same operating system or hypervisor are in the same Inner
1053 // Shareable shareability domain."
1054 StoreStore = ISHST,
1055 LoadStore = ISHLD,
1056 LoadLoad = ISHLD,
1057 StoreLoad = ISH,
1058 AnyAny = ISH
1059 };
1060
1061 void membar(Membar_mask_bits order_constraint) {
1062 dmb(Assembler::barrier(order_constraint));
1063 }
1064
1065 // Unconditional branch (register)
1066 void branch_reg(Register R, int opc) {
1067 starti;
1068 f(0b1101011, 31, 25);
1069 f(opc, 24, 21);
1070 f(0b11111000000, 20, 10);
1071 rf(R, 5);
1072 f(0b00000, 4, 0);
1073 }
1074
1075 #define INSN(NAME, opc) \
1076 void NAME(Register R) { \
1077 branch_reg(R, opc); \
1078 }
1079
1080 INSN(br, 0b0000);
1081 INSN(blr, 0b0001);
1082 INSN(ret, 0b0010);
1083
1084 void ret(void *p); // This forces a compile-time error for ret(0)
1085
1086 #undef INSN
1087
1088 #define INSN(NAME, opc) \
1089 void NAME() { \
1090 branch_reg((Register)0b11111, opc); \
1091 }
1092
1093 INSN(eret, 0b0100);
1094 INSN(drps, 0b0101);
1095
1096 #undef INSN
1097
1098 // Load/store exclusive
1099 enum operand_size { byte, halfword, word, xword };
1100
1101 void load_store_exclusive(Register Rs, Register Rt1, Register Rt2,
1102 Register Rn, enum operand_size sz, int op, int o0) {
1103 starti;
1104 f(sz, 31, 30), f(0b001000, 29, 24), f(op, 23, 21);
1105 rf(Rs, 16), f(o0, 15), rf(Rt2, 10), rf(Rn, 5), rf(Rt1, 0);
1106 }
1107
1108 #define INSN4(NAME, sz, op, o0) /* Four registers */ \
1109 void NAME(Register Rs, Register Rt1, Register Rt2, Register Rn) { \
1110 load_store_exclusive(Rs, Rt1, Rt2, Rn, sz, op, o0); \
1111 }
1112
1113 #define INSN3(NAME, sz, op, o0) /* Three registers */ \
1114 void NAME(Register Rs, Register Rt, Register Rn) { \
1115 load_store_exclusive(Rs, Rt, (Register)0b11111, Rn, sz, op, o0); \
1116 }
1117
1118 #define INSN2(NAME, sz, op, o0) /* Two registers */ \
1119 void NAME(Register Rt, Register Rn) { \
1120 load_store_exclusive((Register)0b11111, Rt, (Register)0b11111, \
1121 Rn, sz, op, o0); \
1122 }
1123
1124 #define INSN_FOO(NAME, sz, op, o0) /* Three registers, encoded differently */ \
1125 void NAME(Register Rt1, Register Rt2, Register Rn) { \
1126 load_store_exclusive((Register)0b11111, Rt1, Rt2, Rn, sz, op, o0); \
1127 }
1128
1129 // bytes
1130 INSN3(stxrb, byte, 0b000, 0);
1131 INSN3(stlxrb, byte, 0b000, 1);
1132 INSN2(ldxrb, byte, 0b010, 0);
1133 INSN2(ldaxrb, byte, 0b010, 1);
1134 INSN2(stlrb, byte, 0b100, 1);
1135 INSN2(ldarb, byte, 0b110, 1);
1136
1137 // halfwords
1138 INSN3(stxrh, halfword, 0b000, 0);
1139 INSN3(stlxrh, halfword, 0b000, 1);
1140 INSN2(ldxrh, halfword, 0b010, 0);
1141 INSN2(ldaxrh, halfword, 0b010, 1);
1142 INSN2(stlrh, halfword, 0b100, 1);
1143 INSN2(ldarh, halfword, 0b110, 1);
1144
1145 // words
1146 INSN3(stxrw, word, 0b000, 0);
1147 INSN3(stlxrw, word, 0b000, 1);
1148 INSN4(stxpw, word, 0b001, 0);
1149 INSN4(stlxpw, word, 0b001, 1);
1150 INSN2(ldxrw, word, 0b010, 0);
1151 INSN2(ldaxrw, word, 0b010, 1);
1152 INSN_FOO(ldxpw, word, 0b011, 0);
1153 INSN_FOO(ldaxpw, word, 0b011, 1);
1154 INSN2(stlrw, word, 0b100, 1);
1155 INSN2(ldarw, word, 0b110, 1);
1156
1157 // xwords
1158 INSN3(stxr, xword, 0b000, 0);
1159 INSN3(stlxr, xword, 0b000, 1);
1160 INSN4(stxp, xword, 0b001, 0);
1161 INSN4(stlxp, xword, 0b001, 1);
1162 INSN2(ldxr, xword, 0b010, 0);
1163 INSN2(ldaxr, xword, 0b010, 1);
1164 INSN_FOO(ldxp, xword, 0b011, 0);
1165 INSN_FOO(ldaxp, xword, 0b011, 1);
1166 INSN2(stlr, xword, 0b100, 1);
1167 INSN2(ldar, xword, 0b110, 1);
1168
1169 #undef INSN2
1170 #undef INSN3
1171 #undef INSN4
1172 #undef INSN_FOO
1173
1174 // Load register (literal)
1175 #define INSN(NAME, opc, V) \
1176 void NAME(Register Rt, address dest) { \
1177 long offset = (dest - pc()) >> 2; \
1178 starti; \
1179 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1180 sf(offset, 23, 5); \
1181 rf(Rt, 0); \
1182 } \
1183 void NAME(Register Rt, address dest, relocInfo::relocType rtype) { \
1184 InstructionMark im(this); \
1185 guarantee(rtype == relocInfo::internal_word_type, \
1186 "only internal_word_type relocs make sense here"); \
1187 code_section()->relocate(inst_mark(), InternalAddress(dest).rspec()); \
1188 NAME(Rt, dest); \
1189 } \
1190 void NAME(Register Rt, Label &L) { \
1191 wrap_label(Rt, L, &Assembler::NAME); \
1192 }
1193
1194 INSN(ldrw, 0b00, 0);
1195 INSN(ldr, 0b01, 0);
1196 INSN(ldrsw, 0b10, 0);
1197
1198 #undef INSN
1199
1200 #define INSN(NAME, opc, V) \
1201 void NAME(FloatRegister Rt, address dest) { \
1202 long offset = (dest - pc()) >> 2; \
1203 starti; \
1204 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1205 sf(offset, 23, 5); \
1206 rf((Register)Rt, 0); \
1207 }
1208
1209 INSN(ldrs, 0b00, 1);
1210 INSN(ldrd, 0b01, 1);
1211 INSN(ldrq, 0x10, 1);
1212
1213 #undef INSN
1214
1215 #define INSN(NAME, opc, V) \
1216 void NAME(address dest, prfop op = PLDL1KEEP) { \
1217 long offset = (dest - pc()) >> 2; \
1218 starti; \
1219 f(opc, 31, 30), f(0b011, 29, 27), f(V, 26), f(0b00, 25, 24), \
1220 sf(offset, 23, 5); \
1221 f(op, 4, 0); \
1222 } \
1223 void NAME(Label &L, prfop op = PLDL1KEEP) { \
1224 wrap_label(L, op, &Assembler::NAME); \
1225 }
1226
1227 INSN(prfm, 0b11, 0);
1228
1229 #undef INSN
1230
1231 // Load/store
1232 void ld_st1(int opc, int p1, int V, int L,
1233 Register Rt1, Register Rt2, Address adr, bool no_allocate) {
1234 starti;
1235 f(opc, 31, 30), f(p1, 29, 27), f(V, 26), f(L, 22);
1236 zrf(Rt2, 10), zrf(Rt1, 0);
1237 if (no_allocate) {
1238 adr.encode_nontemporal_pair(current);
1239 } else {
1240 adr.encode_pair(current);
1241 }
1242 }
1243
1244 // Load/store register pair (offset)
1245 #define INSN(NAME, size, p1, V, L, no_allocate) \
1246 void NAME(Register Rt1, Register Rt2, Address adr) { \
1247 ld_st1(size, p1, V, L, Rt1, Rt2, adr, no_allocate); \
1248 }
1249
1250 INSN(stpw, 0b00, 0b101, 0, 0, false);
1251 INSN(ldpw, 0b00, 0b101, 0, 1, false);
1252 INSN(ldpsw, 0b01, 0b101, 0, 1, false);
1253 INSN(stp, 0b10, 0b101, 0, 0, false);
1254 INSN(ldp, 0b10, 0b101, 0, 1, false);
1255
1256 // Load/store no-allocate pair (offset)
1257 INSN(stnpw, 0b00, 0b101, 0, 0, true);
1258 INSN(ldnpw, 0b00, 0b101, 0, 1, true);
1259 INSN(stnp, 0b10, 0b101, 0, 0, true);
1260 INSN(ldnp, 0b10, 0b101, 0, 1, true);
1261
1262 #undef INSN
1263
1264 #define INSN(NAME, size, p1, V, L, no_allocate) \
1265 void NAME(FloatRegister Rt1, FloatRegister Rt2, Address adr) { \
1266 ld_st1(size, p1, V, L, (Register)Rt1, (Register)Rt2, adr, no_allocate); \
1267 }
1268
1269 INSN(stps, 0b00, 0b101, 1, 0, false);
1270 INSN(ldps, 0b00, 0b101, 1, 1, false);
1271 INSN(stpd, 0b01, 0b101, 1, 0, false);
1272 INSN(ldpd, 0b01, 0b101, 1, 1, false);
1273 INSN(stpq, 0b10, 0b101, 1, 0, false);
1274 INSN(ldpq, 0b10, 0b101, 1, 1, false);
1275
1276 #undef INSN
1277
1278 // Load/store register (all modes)
1279 void ld_st2(Register Rt, const Address &adr, int size, int op, int V = 0) {
1280 starti;
1281
1282 f(V, 26); // general reg?
1283 zrf(Rt, 0);
1284
1285 // Encoding for literal loads is done here (rather than pushed
1286 // down into Address::encode) because the encoding of this
1287 // instruction is too different from all of the other forms to
1288 // make it worth sharing.
1289 if (adr.getMode() == Address::literal) {
1290 assert(size == 0b10 || size == 0b11, "bad operand size in ldr");
1291 assert(op == 0b01, "literal form can only be used with loads");
1292 f(size & 0b01, 31, 30), f(0b011, 29, 27), f(0b00, 25, 24);
1293 long offset = (adr.target() - pc()) >> 2;
1294 sf(offset, 23, 5);
1295 code_section()->relocate(pc(), adr.rspec());
1296 return;
1297 }
1298
1299 f(size, 31, 30);
1300 f(op, 23, 22); // str
1301 adr.encode(current);
1302 }
1303
1304 #define INSN(NAME, size, op) \
1305 void NAME(Register Rt, const Address &adr) { \
1306 ld_st2(Rt, adr, size, op); \
1307 } \
1308
1309 INSN(str, 0b11, 0b00);
1310 INSN(strw, 0b10, 0b00);
1311 INSN(strb, 0b00, 0b00);
1312 INSN(strh, 0b01, 0b00);
1313
1314 INSN(ldr, 0b11, 0b01);
1315 INSN(ldrw, 0b10, 0b01);
1316 INSN(ldrb, 0b00, 0b01);
1317 INSN(ldrh, 0b01, 0b01);
1318
1319 INSN(ldrsb, 0b00, 0b10);
1320 INSN(ldrsbw, 0b00, 0b11);
1321 INSN(ldrsh, 0b01, 0b10);
1322 INSN(ldrshw, 0b01, 0b11);
1323 INSN(ldrsw, 0b10, 0b10);
1324
1325 #undef INSN
1326
1327 #define INSN(NAME, size, op) \
1328 void NAME(const Address &adr, prfop pfop = PLDL1KEEP) { \
1329 ld_st2((Register)pfop, adr, size, op); \
1330 }
1331
1332 INSN(prfm, 0b11, 0b10); // FIXME: PRFM should not be used with
1333 // writeback modes, but the assembler
1334 // doesn't enfore that.
1335
1336 #undef INSN
1337
1338 #define INSN(NAME, size, op) \
1339 void NAME(FloatRegister Rt, const Address &adr) { \
1340 ld_st2((Register)Rt, adr, size, op, 1); \
1341 }
1342
1343 INSN(strd, 0b11, 0b00);
1344 INSN(strs, 0b10, 0b00);
1345 INSN(ldrd, 0b11, 0b01);
1346 INSN(ldrs, 0b10, 0b01);
1347 INSN(strq, 0b00, 0b10);
1348 INSN(ldrq, 0x00, 0b11);
1349
1350 #undef INSN
1351
1352 enum shift_kind { LSL, LSR, ASR, ROR };
1353
1354 void op_shifted_reg(unsigned decode,
1355 enum shift_kind kind, unsigned shift,
1356 unsigned size, unsigned op) {
1357 f(size, 31);
1358 f(op, 30, 29);
1359 f(decode, 28, 24);
1360 f(shift, 15, 10);
1361 f(kind, 23, 22);
1362 }
1363
1364 // Logical (shifted register)
1365 #define INSN(NAME, size, op, N) \
1366 void NAME(Register Rd, Register Rn, Register Rm, \
1367 enum shift_kind kind = LSL, unsigned shift = 0) { \
1368 starti; \
1369 f(N, 21); \
1370 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0); \
1371 op_shifted_reg(0b01010, kind, shift, size, op); \
1372 }
1373
1374 INSN(andr, 1, 0b00, 0);
1375 INSN(orr, 1, 0b01, 0);
1376 INSN(eor, 1, 0b10, 0);
1377 INSN(ands, 1, 0b11, 0);
1378 INSN(andw, 0, 0b00, 0);
1379 INSN(orrw, 0, 0b01, 0);
1380 INSN(eorw, 0, 0b10, 0);
1381 INSN(andsw, 0, 0b11, 0);
1382
1383 INSN(bic, 1, 0b00, 1);
1384 INSN(orn, 1, 0b01, 1);
1385 INSN(eon, 1, 0b10, 1);
1386 INSN(bics, 1, 0b11, 1);
1387 INSN(bicw, 0, 0b00, 1);
1388 INSN(ornw, 0, 0b01, 1);
1389 INSN(eonw, 0, 0b10, 1);
1390 INSN(bicsw, 0, 0b11, 1);
1391
1392 #undef INSN
1393
1394 // Add/subtract (shifted register)
1395 #define INSN(NAME, size, op) \
1396 void NAME(Register Rd, Register Rn, Register Rm, \
1397 enum shift_kind kind, unsigned shift = 0) { \
1398 starti; \
1399 f(0, 21); \
1400 assert_cond(kind != ROR); \
1401 zrf(Rd, 0), zrf(Rn, 5), zrf(Rm, 16); \
1402 op_shifted_reg(0b01011, kind, shift, size, op); \
1403 }
1404
1405 INSN(add, 1, 0b000);
1406 INSN(sub, 1, 0b10);
1407 INSN(addw, 0, 0b000);
1408 INSN(subw, 0, 0b10);
1409
1410 INSN(adds, 1, 0b001);
1411 INSN(subs, 1, 0b11);
1412 INSN(addsw, 0, 0b001);
1413 INSN(subsw, 0, 0b11);
1414
1415 #undef INSN
1416
1417 // Add/subtract (extended register)
1418 #define INSN(NAME, op) \
1419 void NAME(Register Rd, Register Rn, Register Rm, \
1420 ext::operation option, int amount = 0) { \
1421 starti; \
1422 zrf(Rm, 16), srf(Rn, 5), srf(Rd, 0); \
1423 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1424 }
1425
1426 void add_sub_extended_reg(unsigned op, unsigned decode,
1427 Register Rd, Register Rn, Register Rm,
1428 unsigned opt, ext::operation option, unsigned imm) {
1429 guarantee(imm <= 4, "shift amount must be < 4");
1430 f(op, 31, 29), f(decode, 28, 24), f(opt, 23, 22), f(1, 21);
1431 f(option, 15, 13), f(imm, 12, 10);
1432 }
1433
1434 INSN(addw, 0b000);
1435 INSN(subw, 0b010);
1436 INSN(add, 0b100);
1437 INSN(sub, 0b110);
1438
1439 #undef INSN
1440
1441 #define INSN(NAME, op) \
1442 void NAME(Register Rd, Register Rn, Register Rm, \
1443 ext::operation option, int amount = 0) { \
1444 starti; \
1445 zrf(Rm, 16), srf(Rn, 5), zrf(Rd, 0); \
1446 add_sub_extended_reg(op, 0b01011, Rd, Rn, Rm, 0b00, option, amount); \
1447 }
1448
1449 INSN(addsw, 0b001);
1450 INSN(subsw, 0b011);
1451 INSN(adds, 0b101);
1452 INSN(subs, 0b111);
1453
1454 #undef INSN
1455
1456 // Aliases for short forms of add and sub
1457 #define INSN(NAME) \
1458 void NAME(Register Rd, Register Rn, Register Rm) { \
1459 if (Rd == sp || Rn == sp) \
1460 NAME(Rd, Rn, Rm, ext::uxtx); \
1461 else \
1462 NAME(Rd, Rn, Rm, LSL); \
1463 }
1464
1465 INSN(addw);
1466 INSN(subw);
1467 INSN(add);
1468 INSN(sub);
1469
1470 INSN(addsw);
1471 INSN(subsw);
1472 INSN(adds);
1473 INSN(subs);
1474
1475 #undef INSN
1476
1477 // Add/subtract (with carry)
1478 void add_sub_carry(unsigned op, Register Rd, Register Rn, Register Rm) {
1479 starti;
1480 f(op, 31, 29);
1481 f(0b11010000, 28, 21);
1482 f(0b000000, 15, 10);
1483 zrf(Rm, 16), zrf(Rn, 5), zrf(Rd, 0);
1484 }
1485
1486 #define INSN(NAME, op) \
1487 void NAME(Register Rd, Register Rn, Register Rm) { \
1488 add_sub_carry(op, Rd, Rn, Rm); \
1489 }
1490
1491 INSN(adcw, 0b000);
1492 INSN(adcsw, 0b001);
1493 INSN(sbcw, 0b010);
1494 INSN(sbcsw, 0b011);
1495 INSN(adc, 0b100);
1496 INSN(adcs, 0b101);
1497 INSN(sbc,0b110);
1498 INSN(sbcs, 0b111);
1499
1500 #undef INSN
1501
1502 // Conditional compare (both kinds)
1503 void conditional_compare(unsigned op, int o2, int o3,
1504 Register Rn, unsigned imm5, unsigned nzcv,
1505 unsigned cond) {
1506 f(op, 31, 29);
1507 f(0b11010010, 28, 21);
1508 f(cond, 15, 12);
1509 f(o2, 10);
1510 f(o3, 4);
1511 f(nzcv, 3, 0);
1512 f(imm5, 20, 16), rf(Rn, 5);
1513 }
1514
1515 #define INSN(NAME, op) \
1516 void NAME(Register Rn, Register Rm, int imm, Condition cond) { \
1517 starti; \
1518 f(0, 11); \
1519 conditional_compare(op, 0, 0, Rn, (uintptr_t)Rm, imm, cond); \
1520 } \
1521 \
1522 void NAME(Register Rn, int imm5, int imm, Condition cond) { \
1523 starti; \
1524 f(1, 11); \
1525 conditional_compare(op, 0, 0, Rn, imm5, imm, cond); \
1526 }
1527
1528 INSN(ccmnw, 0b001);
1529 INSN(ccmpw, 0b011);
1530 INSN(ccmn, 0b101);
1531 INSN(ccmp, 0b111);
1532
1533 #undef INSN
1534
1535 // Conditional select
1536 void conditional_select(unsigned op, unsigned op2,
1537 Register Rd, Register Rn, Register Rm,
1538 unsigned cond) {
1539 starti;
1540 f(op, 31, 29);
1541 f(0b11010100, 28, 21);
1542 f(cond, 15, 12);
1543 f(op2, 11, 10);
1544 zrf(Rm, 16), zrf(Rn, 5), rf(Rd, 0);
1545 }
1546
1547 #define INSN(NAME, op, op2) \
1548 void NAME(Register Rd, Register Rn, Register Rm, Condition cond) { \
1549 conditional_select(op, op2, Rd, Rn, Rm, cond); \
1550 }
1551
1552 INSN(cselw, 0b000, 0b00);
1553 INSN(csincw, 0b000, 0b01);
1554 INSN(csinvw, 0b010, 0b00);
1555 INSN(csnegw, 0b010, 0b01);
1556 INSN(csel, 0b100, 0b00);
1557 INSN(csinc, 0b100, 0b01);
1558 INSN(csinv, 0b110, 0b00);
1559 INSN(csneg, 0b110, 0b01);
1560
1561 #undef INSN
1562
1563 // Data processing
1564 void data_processing(unsigned op29, unsigned opcode,
1565 Register Rd, Register Rn) {
1566 f(op29, 31, 29), f(0b11010110, 28, 21);
1567 f(opcode, 15, 10);
1568 rf(Rn, 5), rf(Rd, 0);
1569 }
1570
1571 // (1 source)
1572 #define INSN(NAME, op29, opcode2, opcode) \
1573 void NAME(Register Rd, Register Rn) { \
1574 starti; \
1575 f(opcode2, 20, 16); \
1576 data_processing(op29, opcode, Rd, Rn); \
1577 }
1578
1579 INSN(rbitw, 0b010, 0b00000, 0b00000);
1580 INSN(rev16w, 0b010, 0b00000, 0b00001);
1581 INSN(revw, 0b010, 0b00000, 0b00010);
1582 INSN(clzw, 0b010, 0b00000, 0b00100);
1583 INSN(clsw, 0b010, 0b00000, 0b00101);
1584
1585 INSN(rbit, 0b110, 0b00000, 0b00000);
1586 INSN(rev16, 0b110, 0b00000, 0b00001);
1587 INSN(rev32, 0b110, 0b00000, 0b00010);
1588 INSN(rev, 0b110, 0b00000, 0b00011);
1589 INSN(clz, 0b110, 0b00000, 0b00100);
1590 INSN(cls, 0b110, 0b00000, 0b00101);
1591
1592 #undef INSN
1593
1594 // (2 sources)
1595 #define INSN(NAME, op29, opcode) \
1596 void NAME(Register Rd, Register Rn, Register Rm) { \
1597 starti; \
1598 rf(Rm, 16); \
1599 data_processing(op29, opcode, Rd, Rn); \
1600 }
1601
1602 INSN(udivw, 0b000, 0b000010);
1603 INSN(sdivw, 0b000, 0b000011);
1604 INSN(lslvw, 0b000, 0b001000);
1605 INSN(lsrvw, 0b000, 0b001001);
1606 INSN(asrvw, 0b000, 0b001010);
1607 INSN(rorvw, 0b000, 0b001011);
1608
1609 INSN(udiv, 0b100, 0b000010);
1610 INSN(sdiv, 0b100, 0b000011);
1611 INSN(lslv, 0b100, 0b001000);
1612 INSN(lsrv, 0b100, 0b001001);
1613 INSN(asrv, 0b100, 0b001010);
1614 INSN(rorv, 0b100, 0b001011);
1615
1616 #undef INSN
1617
1618 // (3 sources)
1619 void data_processing(unsigned op54, unsigned op31, unsigned o0,
1620 Register Rd, Register Rn, Register Rm,
1621 Register Ra) {
1622 starti;
1623 f(op54, 31, 29), f(0b11011, 28, 24);
1624 f(op31, 23, 21), f(o0, 15);
1625 zrf(Rm, 16), zrf(Ra, 10), zrf(Rn, 5), zrf(Rd, 0);
1626 }
1627
1628 #define INSN(NAME, op54, op31, o0) \
1629 void NAME(Register Rd, Register Rn, Register Rm, Register Ra) { \
1630 data_processing(op54, op31, o0, Rd, Rn, Rm, Ra); \
1631 }
1632
1633 INSN(maddw, 0b000, 0b000, 0);
1634 INSN(msubw, 0b000, 0b000, 1);
1635 INSN(madd, 0b100, 0b000, 0);
1636 INSN(msub, 0b100, 0b000, 1);
1637 INSN(smaddl, 0b100, 0b001, 0);
1638 INSN(smsubl, 0b100, 0b001, 1);
1639 INSN(umaddl, 0b100, 0b101, 0);
1640 INSN(umsubl, 0b100, 0b101, 1);
1641
1642 #undef INSN
1643
1644 #define INSN(NAME, op54, op31, o0) \
1645 void NAME(Register Rd, Register Rn, Register Rm) { \
1646 data_processing(op54, op31, o0, Rd, Rn, Rm, (Register)31); \
1647 }
1648
1649 INSN(smulh, 0b100, 0b010, 0);
1650 INSN(umulh, 0b100, 0b110, 0);
1651
1652 #undef INSN
1653
1654 // Floating-point data-processing (1 source)
1655 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1656 FloatRegister Vd, FloatRegister Vn) {
1657 starti;
1658 f(op31, 31, 29);
1659 f(0b11110, 28, 24);
1660 f(type, 23, 22), f(1, 21), f(opcode, 20, 15), f(0b10000, 14, 10);
1661 rf(Vn, 5), rf(Vd, 0);
1662 }
1663
1664 #define INSN(NAME, op31, type, opcode) \
1665 void NAME(FloatRegister Vd, FloatRegister Vn) { \
1666 data_processing(op31, type, opcode, Vd, Vn); \
1667 }
1668
1669 private:
1670 INSN(i_fmovs, 0b000, 0b00, 0b000000);
1671 public:
1672 INSN(fabss, 0b000, 0b00, 0b000001);
1673 INSN(fnegs, 0b000, 0b00, 0b000010);
1674 INSN(fsqrts, 0b000, 0b00, 0b000011);
1675 INSN(fcvts, 0b000, 0b00, 0b000101); // Single-precision to double-precision
1676
1677 private:
1678 INSN(i_fmovd, 0b000, 0b01, 0b000000);
1679 public:
1680 INSN(fabsd, 0b000, 0b01, 0b000001);
1681 INSN(fnegd, 0b000, 0b01, 0b000010);
1682 INSN(fsqrtd, 0b000, 0b01, 0b000011);
1683 INSN(fcvtd, 0b000, 0b01, 0b000100); // Double-precision to single-precision
1684
1685 void fmovd(FloatRegister Vd, FloatRegister Vn) {
1686 assert(Vd != Vn, "should be");
1687 i_fmovd(Vd, Vn);
1688 }
1689
1690 void fmovs(FloatRegister Vd, FloatRegister Vn) {
1691 assert(Vd != Vn, "should be");
1692 i_fmovs(Vd, Vn);
1693 }
1694
1695 #undef INSN
1696
1697 // Floating-point data-processing (2 source)
1698 void data_processing(unsigned op31, unsigned type, unsigned opcode,
1699 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) {
1700 starti;
1701 f(op31, 31, 29);
1702 f(0b11110, 28, 24);
1703 f(type, 23, 22), f(1, 21), f(opcode, 15, 12), f(0b10, 11, 10);
1704 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1705 }
1706
1707 #define INSN(NAME, op31, type, opcode) \
1708 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm) { \
1709 data_processing(op31, type, opcode, Vd, Vn, Vm); \
1710 }
1711
1712 INSN(fmuls, 0b000, 0b00, 0b0000);
1713 INSN(fdivs, 0b000, 0b00, 0b0001);
1714 INSN(fadds, 0b000, 0b00, 0b0010);
1715 INSN(fsubs, 0b000, 0b00, 0b0011);
1716 INSN(fnmuls, 0b000, 0b00, 0b1000);
1717
1718 INSN(fmuld, 0b000, 0b01, 0b0000);
1719 INSN(fdivd, 0b000, 0b01, 0b0001);
1720 INSN(faddd, 0b000, 0b01, 0b0010);
1721 INSN(fsubd, 0b000, 0b01, 0b0011);
1722 INSN(fnmuld, 0b000, 0b01, 0b1000);
1723
1724 #undef INSN
1725
1726 // Floating-point data-processing (3 source)
1727 void data_processing(unsigned op31, unsigned type, unsigned o1, unsigned o0,
1728 FloatRegister Vd, FloatRegister Vn, FloatRegister Vm,
1729 FloatRegister Va) {
1730 starti;
1731 f(op31, 31, 29);
1732 f(0b11111, 28, 24);
1733 f(type, 23, 22), f(o1, 21), f(o0, 15);
1734 rf(Vm, 16), rf(Va, 10), rf(Vn, 5), rf(Vd, 0);
1735 }
1736
1737 #define INSN(NAME, op31, type, o1, o0) \
1738 void NAME(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, \
1739 FloatRegister Va) { \
1740 data_processing(op31, type, o1, o0, Vd, Vn, Vm, Va); \
1741 }
1742
1743 INSN(fmadds, 0b000, 0b00, 0, 0);
1744 INSN(fmsubs, 0b000, 0b00, 0, 1);
1745 INSN(fnmadds, 0b000, 0b00, 1, 0);
1746 INSN(fnmsubs, 0b000, 0b00, 1, 1);
1747
1748 INSN(fmaddd, 0b000, 0b01, 0, 0);
1749 INSN(fmsubd, 0b000, 0b01, 0, 1);
1750 INSN(fnmaddd, 0b000, 0b01, 1, 0);
1751 INSN(fnmsub, 0b000, 0b01, 1, 1);
1752
1753 #undef INSN
1754
1755 // Floating-point conditional select
1756 void fp_conditional_select(unsigned op31, unsigned type,
1757 unsigned op1, unsigned op2,
1758 Condition cond, FloatRegister Vd,
1759 FloatRegister Vn, FloatRegister Vm) {
1760 starti;
1761 f(op31, 31, 29);
1762 f(0b11110, 28, 24);
1763 f(type, 23, 22);
1764 f(op1, 21, 21);
1765 f(op2, 11, 10);
1766 f(cond, 15, 12);
1767 rf(Vm, 16), rf(Vn, 5), rf(Vd, 0);
1768 }
1769
1770 #define INSN(NAME, op31, type, op1, op2) \
1771 void NAME(FloatRegister Vd, FloatRegister Vn, \
1772 FloatRegister Vm, Condition cond) { \
1773 fp_conditional_select(op31, type, op1, op2, cond, Vd, Vn, Vm); \
1774 }
1775
1776 INSN(fcsels, 0b000, 0b00, 0b1, 0b11);
1777 INSN(fcseld, 0b000, 0b01, 0b1, 0b11);
1778
1779 #undef INSN
1780
1781 // Floating-point<->integer conversions
1782 void float_int_convert(unsigned op31, unsigned type,
1783 unsigned rmode, unsigned opcode,
1784 Register Rd, Register Rn) {
1785 starti;
1786 f(op31, 31, 29);
1787 f(0b11110, 28, 24);
1788 f(type, 23, 22), f(1, 21), f(rmode, 20, 19);
1789 f(opcode, 18, 16), f(0b000000, 15, 10);
1790 zrf(Rn, 5), zrf(Rd, 0);
1791 }
1792
1793 #define INSN(NAME, op31, type, rmode, opcode) \
1794 void NAME(Register Rd, FloatRegister Vn) { \
1795 float_int_convert(op31, type, rmode, opcode, Rd, (Register)Vn); \
1796 }
1797
1798 INSN(fcvtzsw, 0b000, 0b00, 0b11, 0b000);
1799 INSN(fcvtzs, 0b100, 0b00, 0b11, 0b000);
1800 INSN(fcvtzdw, 0b000, 0b01, 0b11, 0b000);
1801 INSN(fcvtzd, 0b100, 0b01, 0b11, 0b000);
1802
1803 INSN(fmovs, 0b000, 0b00, 0b00, 0b110);
1804 INSN(fmovd, 0b100, 0b01, 0b00, 0b110);
1805
1806 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b110);
1807
1808 #undef INSN
1809
1810 #define INSN(NAME, op31, type, rmode, opcode) \
1811 void NAME(FloatRegister Vd, Register Rn) { \
1812 float_int_convert(op31, type, rmode, opcode, (Register)Vd, Rn); \
1813 }
1814
1815 INSN(fmovs, 0b000, 0b00, 0b00, 0b111);
1816 INSN(fmovd, 0b100, 0b01, 0b00, 0b111);
1817
1818 INSN(scvtfws, 0b000, 0b00, 0b00, 0b010);
1819 INSN(scvtfs, 0b100, 0b00, 0b00, 0b010);
1820 INSN(scvtfwd, 0b000, 0b01, 0b00, 0b010);
1821 INSN(scvtfd, 0b100, 0b01, 0b00, 0b010);
1822
1823 // INSN(fmovhid, 0b100, 0b10, 0b01, 0b111);
1824
1825 #undef INSN
1826
1827 // Floating-point compare
1828 void float_compare(unsigned op31, unsigned type,
1829 unsigned op, unsigned op2,
1830 FloatRegister Vn, FloatRegister Vm = (FloatRegister)0) {
1831 starti;
1832 f(op31, 31, 29);
1833 f(0b11110, 28, 24);
1834 f(type, 23, 22), f(1, 21);
1835 f(op, 15, 14), f(0b1000, 13, 10), f(op2, 4, 0);
1836 rf(Vn, 5), rf(Vm, 16);
1837 }
1838
1839
1840 #define INSN(NAME, op31, type, op, op2) \
1841 void NAME(FloatRegister Vn, FloatRegister Vm) { \
1842 float_compare(op31, type, op, op2, Vn, Vm); \
1843 }
1844
1845 #define INSN1(NAME, op31, type, op, op2) \
1846 void NAME(FloatRegister Vn, double d) { \
1847 assert_cond(d == 0.0); \
1848 float_compare(op31, type, op, op2, Vn); \
1849 }
1850
1851 INSN(fcmps, 0b000, 0b00, 0b00, 0b00000);
1852 INSN1(fcmps, 0b000, 0b00, 0b00, 0b01000);
1853 // INSN(fcmpes, 0b000, 0b00, 0b00, 0b10000);
1854 // INSN1(fcmpes, 0b000, 0b00, 0b00, 0b11000);
1855
1856 INSN(fcmpd, 0b000, 0b01, 0b00, 0b00000);
1857 INSN1(fcmpd, 0b000, 0b01, 0b00, 0b01000);
1858 // INSN(fcmped, 0b000, 0b01, 0b00, 0b10000);
1859 // INSN1(fcmped, 0b000, 0b01, 0b00, 0b11000);
1860
1861 #undef INSN
1862 #undef INSN1
1863
1864 // Floating-point Move (immediate)
1865 private:
1866 unsigned pack(double value);
1867
1868 void fmov_imm(FloatRegister Vn, double value, unsigned size) {
1869 starti;
1870 f(0b00011110, 31, 24), f(size, 23, 22), f(1, 21);
1871 f(pack(value), 20, 13), f(0b10000000, 12, 5);
1872 rf(Vn, 0);
1873 }
1874
1875 public:
1876
1877 void fmovs(FloatRegister Vn, double value) {
1878 if (value)
1879 fmov_imm(Vn, value, 0b00);
1880 else
1881 fmovs(Vn, zr);
1882 }
1883 void fmovd(FloatRegister Vn, double value) {
1884 if (value)
1885 fmov_imm(Vn, value, 0b01);
1886 else
1887 fmovd(Vn, zr);
1888 }
1889
1890 /* SIMD extensions
1891 *
1892 * We just use FloatRegister in the following. They are exactly the same
1893 * as SIMD registers.
1894 */
1895 public:
1896
1897 enum SIMD_Arrangement {
1898 T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D
1899 };
1900
1901 enum SIMD_RegVariant {
1902 B, H, S, D, Q
1903 };
1904
1905 #define INSN(NAME, op) \
1906 void NAME(FloatRegister Rt, SIMD_RegVariant T, const Address &adr) { \
1907 ld_st2((Register)Rt, adr, (int)T & 3, op + ((T==Q) ? 0b10:0b00), 1); \
1908 } \
1909
1910 INSN(ldr, 1);
1911 INSN(str, 0);
1912
1913 #undef INSN
1914
1915 private:
1916
1917 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn, int op1, int op2) {
1918 starti;
1919 f(0,31), f((int)T & 1, 30);
1920 f(op1, 29, 21), f(0, 20, 16), f(op2, 15, 12);
1921 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1922 }
1923 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
1924 int imm, int op1, int op2) {
1925 starti;
1926 f(0,31), f((int)T & 1, 30);
1927 f(op1 | 0b100, 29, 21), f(0b11111, 20, 16), f(op2, 15, 12);
1928 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1929 }
1930 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Register Xn,
1931 Register Xm, int op1, int op2) {
1932 starti;
1933 f(0,31), f((int)T & 1, 30);
1934 f(op1 | 0b100, 29, 21), rf(Xm, 16), f(op2, 15, 12);
1935 f((int)T >> 1, 11, 10), rf(Xn, 5), rf(Vt, 0);
1936 }
1937
1938 void ld_st(FloatRegister Vt, SIMD_Arrangement T, Address a, int op1, int op2) {
1939 switch (a.getMode()) {
1940 case Address::base_plus_offset:
1941 guarantee(a.offset() == 0, "no offset allowed here");
1942 ld_st(Vt, T, a.base(), op1, op2);
1943 break;
1944 case Address::post:
1945 ld_st(Vt, T, a.base(), a.offset(), op1, op2);
1946 break;
1947 case Address::base_plus_offset_reg:
1948 ld_st(Vt, T, a.base(), a.index(), op1, op2);
1949 break;
1950 default:
1951 ShouldNotReachHere();
1952 }
1953 }
1954
1955 public:
1956
1957 #define INSN1(NAME, op1, op2) \
1958 void NAME(FloatRegister Vt, SIMD_Arrangement T, const Address &a) { \
1959 ld_st(Vt, T, a, op1, op2); \
1960 }
1961
1962 #define INSN2(NAME, op1, op2) \
1963 void NAME(FloatRegister Vt, FloatRegister Vt2, SIMD_Arrangement T, const Address &a) { \
1964 assert(Vt->successor() == Vt2, "Registers must be ordered"); \
1965 ld_st(Vt, T, a, op1, op2); \
1966 }
1967
1968 #define INSN3(NAME, op1, op2) \
1969 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
1970 SIMD_Arrangement T, const Address &a) { \
1971 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3, \
1972 "Registers must be ordered"); \
1973 ld_st(Vt, T, a, op1, op2); \
1974 }
1975
1976 #define INSN4(NAME, op1, op2) \
1977 void NAME(FloatRegister Vt, FloatRegister Vt2, FloatRegister Vt3, \
1978 FloatRegister Vt4, SIMD_Arrangement T, const Address &a) { \
1979 assert(Vt->successor() == Vt2 && Vt2->successor() == Vt3 && \
1980 Vt3->successor() == Vt4, "Registers must be ordered"); \
1981 ld_st(Vt, T, a, op1, op2); \
1982 }
1983
1984 INSN1(ld1, 0b001100010, 0b0111);
1985 INSN2(ld1, 0b001100010, 0b1010);
1986 INSN3(ld1, 0b001100010, 0b0110);
1987 INSN4(ld1, 0b001100010, 0b0010);
1988
1989 INSN2(ld2, 0b001100010, 0b1000);
1990 INSN3(ld3, 0b001100010, 0b0100);
1991 INSN4(ld4, 0b001100010, 0b0000);
1992
1993 INSN1(st1, 0b001100000, 0b0111);
1994 INSN2(st1, 0b001100000, 0b1010);
1995 INSN3(st1, 0b001100000, 0b0110);
1996 INSN4(st1, 0b001100000, 0b0010);
1997
1998 INSN2(st2, 0b001100000, 0b1000);
1999 INSN3(st3, 0b001100000, 0b0100);
2000 INSN4(st4, 0b001100000, 0b0000);
2001
2002 INSN1(ld1r, 0b001101010, 0b1100);
2003 INSN2(ld2r, 0b001101011, 0b1100);
2004 INSN3(ld3r, 0b001101010, 0b1110);
2005 INSN4(ld4r, 0b001101011, 0b1110);
2006
2007 #undef INSN1
2008 #undef INSN2
2009 #undef INSN3
2010 #undef INSN4
2011
2012 #define INSN(NAME, opc) \
2013 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2014 starti; \
2015 assert(T == T8B || T == T16B, "must be T8B or T16B"); \
2016 f(0, 31), f((int)T & 1, 30), f(opc, 29, 21); \
2017 rf(Vm, 16), f(0b000111, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2018 }
2019
2020 INSN(eor, 0b101110001);
2021 INSN(orr, 0b001110101);
2022 INSN(andr, 0b001110001);
2023 INSN(bic, 0b001110011);
2024 INSN(bif, 0b101110111);
2025 INSN(bit, 0b101110101);
2026 INSN(bsl, 0b101110011);
2027 INSN(orn, 0b001110111);
2028
2029 #undef INSN
2030
2031 #define INSN(NAME, opc, opc2) \
2032 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2033 starti; \
2034 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2035 f((int)T >> 1, 23, 22), f(1, 21), rf(Vm, 16), f(opc2, 15, 10); \
2036 rf(Vn, 5), rf(Vd, 0); \
2037 }
2038
2039 INSN(addv, 0, 0b100001);
2040 INSN(subv, 1, 0b100001);
2041 INSN(mulv, 0, 0b100111);
2042 INSN(sshl, 0, 0b010001);
2043 INSN(ushl, 1, 0b010001);
2044
2045 #undef INSN
2046
2047 #define INSN(NAME, opc, opc2) \
2048 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2049 starti; \
2050 f(0, 31), f((int)T & 1, 30), f(opc, 29), f(0b01110, 28, 24); \
2051 f((int)T >> 1, 23, 22), f(opc2, 21, 10); \
2052 rf(Vn, 5), rf(Vd, 0); \
2053 }
2054
2055 INSN(absr, 0, 0b100000101110);
2056 INSN(negr, 1, 0b100000101110);
2057 INSN(notr, 1, 0b100000010110);
2058 INSN(addv, 0, 0b110001101110);
2059 INSN(cls, 0, 0b100000010010);
2060 INSN(clz, 1, 0b100000010010);
2061 INSN(cnt, 0, 0b100000010110);
2062
2063 #undef INSN
2064
2065 #define INSN(NAME, op0, cmode0) \
2066 void NAME(FloatRegister Vd, SIMD_Arrangement T, unsigned imm8, unsigned lsl = 0) { \
2067 unsigned cmode = cmode0; \
2068 unsigned op = op0; \
2069 starti; \
2070 assert(lsl == 0 || \
2071 ((T == T4H || T == T8H) && lsl == 8) || \
2072 ((T == T2S || T == T4S) && ((lsl >> 3) < 4)), "invalid shift"); \
2073 cmode |= lsl >> 2; \
2074 if (T == T4H || T == T8H) cmode |= 0b1000; \
2075 if (!(T == T4H || T == T8H || T == T2S || T == T4S)) { \
2076 assert(op == 0 && cmode0 == 0, "must be MOVI"); \
2077 cmode = 0b1110; \
2078 if (T == T1D || T == T2D) op = 1; \
2079 } \
2080 f(0, 31), f((int)T & 1, 30), f(op, 29), f(0b0111100000, 28, 19); \
2081 f(imm8 >> 5, 18, 16), f(cmode, 15, 12), f(0x01, 11, 10), f(imm8 & 0b11111, 9, 5); \
2082 rf(Vd, 0); \
2083 }
2084
2085 INSN(movi, 0, 0);
2086 INSN(orri, 0, 1);
2087 INSN(mvni, 1, 0);
2088 INSN(bici, 1, 1);
2089
2090 #undef INSN
2091
2092 #define INSN(NAME, op1, op2, op3) \
2093 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2094 starti; \
2095 assert(T == T2S || T == T4S || T == T2D, "invalid arrangement"); \
2096 f(0, 31), f((int)T & 1, 30), f(op1, 29), f(0b01110, 28, 24), f(op2, 23); \
2097 f(T==T2D ? 1:0, 22); f(1, 21), rf(Vm, 16), f(op3, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2098 }
2099
2100 INSN(fadd, 0, 0, 0b110101);
2101 INSN(fdiv, 1, 0, 0b111111);
2102 INSN(fmul, 1, 0, 0b110111);
2103 INSN(fsub, 0, 1, 0b110101);
2104
2105 #undef INSN
2106
2107 #define INSN(NAME, opc) \
2108 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, FloatRegister Vm) { \
2109 starti; \
2110 assert(T == T4S, "arrangement must be T4S"); \
2111 f(0b01011110000, 31, 21), rf(Vm, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2112 }
2113
2114 INSN(sha1c, 0b000000);
2115 INSN(sha1m, 0b001000);
2116 INSN(sha1p, 0b000100);
2117 INSN(sha1su0, 0b001100);
2118 INSN(sha256h2, 0b010100);
2119 INSN(sha256h, 0b010000);
2120 INSN(sha256su1, 0b011000);
2121
2122 #undef INSN
2123
2124 #define INSN(NAME, opc) \
2125 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) { \
2126 starti; \
2127 assert(T == T4S, "arrangement must be T4S"); \
2128 f(0b0101111000101000, 31, 16), f(opc, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2129 }
2130
2131 INSN(sha1h, 0b000010);
2132 INSN(sha1su1, 0b000110);
2133 INSN(sha256su0, 0b001010);
2134
2135 #undef INSN
2136
2137 #define INSN(NAME, opc) \
2138 void NAME(FloatRegister Vd, FloatRegister Vn) { \
2139 starti; \
2140 f(opc, 31, 10), rf(Vn, 5), rf(Vd, 0); \
2141 }
2142
2143 INSN(aese, 0b0100111000101000010010);
2144 INSN(aesd, 0b0100111000101000010110);
2145 INSN(aesmc, 0b0100111000101000011010);
2146 INSN(aesimc, 0b0100111000101000011110);
2147
2148 #undef INSN
2149
2150 void ins(FloatRegister Vd, SIMD_RegVariant T, FloatRegister Vn, int didx, int sidx) {
2151 starti;
2152 assert(T != Q, "invalid register variant");
2153 f(0b01101110000, 31, 21), f(((didx<<1)|1)<<(int)T, 20, 16), f(0, 15);
2154 f(sidx<<(int)T, 14, 11), f(1, 10), rf(Vn, 5), rf(Vd, 0);
2155 }
2156
2157 void umov(Register Rd, FloatRegister Vn, SIMD_RegVariant T, int idx) {
2158 starti;
2159 f(0, 31), f(T==D ? 1:0, 30), f(0b001110000, 29, 21);
2160 f(((idx<<1)|1)<<(int)T, 20, 16), f(0b001111, 15, 10);
2161 rf(Vn, 5), rf(Rd, 0);
2162 }
2163
2164 #define INSN(NAME, opc, opc2) \
2165 void NAME(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int shift){ \
2166 starti; \
2167 /* The encodings for the immh:immb fields (bits 22:16) are \
2168 * 0001 xxx 8B/16B, shift = xxx \
2169 * 001x xxx 4H/8H, shift = xxxx \
2170 * 01xx xxx 2S/4S, shift = xxxxx \
2171 * 1xxx xxx 1D/2D, shift = xxxxxx (1D is RESERVED) \
2172 */ \
2173 assert((1 << ((T>>1)+3)) > shift, "Invalid Shift value"); \
2174 f(0, 31), f(T & 1, 30), f(opc, 29), f(0b011110, 28, 23), \
2175 f((1 << ((T>>1)+3))|shift, 22, 16); f(opc2, 15, 10), rf(Vn, 5), rf(Vd, 0); \
2176 }
2177
2178 INSN(shl, 0, 0b010101);
2179 INSN(sshr, 0, 0b000001);
2180 INSN(ushr, 1, 0b000001);
2181
2182 #undef INSN
2183
2184 void ushll(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2185 starti;
2186 /* The encodings for the immh:immb fields (bits 22:16) are
2187 * 0001 xxx 8H, 8B/16b shift = xxx
2188 * 001x xxx 4S, 4H/8H shift = xxxx
2189 * 01xx xxx 2D, 2S/4S shift = xxxxx
2190 * 1xxx xxx RESERVED
2191 */
2192 assert((Tb >> 1) + 1 == (Ta >> 1), "Incompatible arrangement");
2193 assert((1 << ((Tb>>1)+3)) > shift, "Invalid shift value");
2194 f(0, 31), f(Tb & 1, 30), f(0b1011110, 29, 23), f((1 << ((Tb>>1)+3))|shift, 22, 16);
2195 f(0b101001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2196 }
2197 void ushll2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, SIMD_Arrangement Tb, int shift) {
2198 ushll(Vd, Ta, Vn, Tb, shift);
2199 }
2200
2201 void uzp1(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T, int op = 0){
2202 starti;
2203 f(0, 31), f((T & 0x1), 30), f(0b001110, 29, 24), f((T >> 1), 23, 22), f(0, 21);
2204 rf(Vm, 16), f(0, 15), f(op, 14), f(0b0110, 13, 10), rf(Vn, 5), rf(Vd, 0);
2205 }
2206 void uzp2(FloatRegister Vd, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement T){
2207 uzp1(Vd, Vn, Vm, T, 1);
2208 }
2209
2210 // Move from general purpose register
2211 // mov Vd.T[index], Rn
2212 void mov(FloatRegister Vd, SIMD_Arrangement T, int index, Register Xn) {
2213 starti;
2214 f(0b01001110000, 31, 21), f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2215 f(0b000111, 15, 10), rf(Xn, 5), rf(Vd, 0);
2216 }
2217
2218 // Move to general purpose register
2219 // mov Rd, Vn.T[index]
2220 void mov(Register Xd, FloatRegister Vn, SIMD_Arrangement T, int index) {
2221 starti;
2222 f(0, 31), f((T >= T1D) ? 1:0, 30), f(0b001110000, 29, 21);
2223 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2224 f(0b001111, 15, 10), rf(Vn, 5), rf(Xd, 0);
2225 }
2226
2227 // We do not handle the 1Q arrangement.
2228 void pmull(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2229 starti;
2230 assert(Ta == T8H && (Tb == T8B || Tb == T16B), "Invalid Size specifier");
2231 f(0, 31), f(Tb & 1, 30), f(0b001110001, 29, 21), rf(Vm, 16), f(0b111000, 15, 10);
2232 rf(Vn, 5), rf(Vd, 0);
2233 }
2234 void pmull2(FloatRegister Vd, SIMD_Arrangement Ta, FloatRegister Vn, FloatRegister Vm, SIMD_Arrangement Tb) {
2235 pmull(Vd, Ta, Vn, Vm, Tb);
2236 }
2237
2238 void uqxtn(FloatRegister Vd, SIMD_Arrangement Tb, FloatRegister Vn, SIMD_Arrangement Ta) {
2239 starti;
2240 int size_b = (int)Tb >> 1;
2241 int size_a = (int)Ta >> 1;
2242 assert(size_b < 3 && size_b == size_a - 1, "Invalid size specifier");
2243 f(0, 31), f(Tb & 1, 30), f(0b101110, 29, 24), f(size_b, 23, 22);
2244 f(0b100001010010, 21, 10), rf(Vn, 5), rf(Vd, 0);
2245 }
2246
2247 void rev32(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn)
2248 {
2249 starti;
2250 assert(T <= T8H, "must be one of T8B, T16B, T4H, T8H");
2251 f(0, 31), f((int)T & 1, 30), f(0b101110, 29, 24);
2252 f(T <= T16B ? 0b00 : 0b01, 23, 22), f(0b100000000010, 21, 10);
2253 rf(Vn, 5), rf(Vd, 0);
2254 }
2255
2256 void dup(FloatRegister Vd, SIMD_Arrangement T, Register Xs)
2257 {
2258 starti;
2259 assert(T != T1D, "reserved encoding");
2260 f(0,31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2261 f((1 << (T >> 1)), 20, 16), f(0b000011, 15, 10), rf(Xs, 5), rf(Vd, 0);
2262 }
2263
2264 void dup(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn, int index = 0)
2265 {
2266 starti;
2267 assert(T != T1D, "reserved encoding");
2268 f(0, 31), f((int)T & 1, 30), f(0b001110000, 29, 21);
2269 f(((1 << (T >> 1)) | (index << ((T >> 1) + 1))), 20, 16);
2270 f(0b000001, 15, 10), rf(Vn, 5), rf(Vd, 0);
2271 }
2272
2273 // CRC32 instructions
2274 #define INSN(NAME, c, sf, sz) \
2275 void NAME(Register Rd, Register Rn, Register Rm) { \
2276 starti; \
2277 f(sf, 31), f(0b0011010110, 30, 21), f(0b010, 15, 13), f(c, 12); \
2278 f(sz, 11, 10), rf(Rm, 16), rf(Rn, 5), rf(Rd, 0); \
2279 }
2280
2281 INSN(crc32b, 0, 0, 0b00);
2282 INSN(crc32h, 0, 0, 0b01);
2283 INSN(crc32w, 0, 0, 0b10);
2284 INSN(crc32x, 0, 1, 0b11);
2285 INSN(crc32cb, 1, 0, 0b00);
2286 INSN(crc32ch, 1, 0, 0b01);
2287 INSN(crc32cw, 1, 0, 0b10);
2288 INSN(crc32cx, 1, 1, 0b11);
2289
2290 #undef INSN
2291
2292
2293 /* Simulator extensions to the ISA
2294
2295 haltsim
2296
2297 takes no arguments, causes the sim to enter a debug break and then
2298 return from the simulator run() call with STATUS_HALT? The linking
2299 code will call fatal() when it sees STATUS_HALT.
2300
2301 blrt Xn, Wm
2302 blrt Xn, #gpargs, #fpargs, #type
2303 Xn holds the 64 bit x86 branch_address
2304 call format is encoded either as immediate data in the call
2305 or in register Wm. In the latter case
2306 Wm[13..6] = #gpargs,
2307 Wm[5..2] = #fpargs,
2308 Wm[1,0] = #type
2309
2310 calls the x86 code address 'branch_address' supplied in Xn passing
2311 arguments taken from the general and floating point registers according
2312 to the supplied counts 'gpargs' and 'fpargs'. may return a result in r0
2313 or v0 according to the the return type #type' where
2314
2315 address branch_address;
2316 uimm4 gpargs;
2317 uimm4 fpargs;
2318 enum ReturnType type;
2319
2320 enum ReturnType
2321 {
2322 void_ret = 0,
2323 int_ret = 1,
2324 long_ret = 1,
2325 obj_ret = 1, // i.e. same as long
2326 float_ret = 2,
2327 double_ret = 3
2328 }
2329
2330 notify
2331
2332 notifies the simulator of a transfer of control. instr[14:0]
2333 identifies the type of change of control.
2334
2335 0 ==> initial entry to a method.
2336
2337 1 ==> return into a method from a submethod call.
2338
2339 2 ==> exit out of Java method code.
2340
2341 3 ==> start execution for a new bytecode.
2342
2343 in cases 1 and 2 the simulator is expected to use a JVM callback to
2344 identify the name of the specific method being executed. in case 4
2345 the simulator is expected to use a JVM callback to identify the
2346 bytecode index.
2347
2348 Instruction encodings
2349 ---------------------
2350
2351 These are encoded in the space with instr[28:25] = 00 which is
2352 unallocated. Encodings are
2353
2354 10987654321098765432109876543210
2355 PSEUDO_HALT = 0x11100000000000000000000000000000
2356 PSEUDO_BLRT = 0x11000000000000000_______________
2357 PSEUDO_BLRTR = 0x1100000000000000100000__________
2358 PSEUDO_NOTIFY = 0x10100000000000000_______________
2359
2360 instr[31,29] = op1 : 111 ==> HALT, 110 ==> BLRT/BLRTR, 101 ==> NOTIFY
2361
2362 for BLRT
2363 instr[14,11] = #gpargs, instr[10,7] = #fpargs
2364 instr[6,5] = #type, instr[4,0] = Rn
2365 for BLRTR
2366 instr[9,5] = Rm, instr[4,0] = Rn
2367 for NOTIFY
2368 instr[14:0] = type : 0 ==> entry, 1 ==> reentry, 2 ==> exit, 3 ==> bcstart
2369 */
2370
2371 enum NotifyType { method_entry, method_reentry, method_exit, bytecode_start };
2372
2373 virtual void notify(int type) {
2374 if (UseBuiltinSim) {
2375 starti;
2376 // 109
2377 f(0b101, 31, 29);
2378 // 87654321098765
2379 f(0b00000000000000, 28, 15);
2380 f(type, 14, 0);
2381 }
2382 }
2383
2384 void blrt(Register Rn, int gpargs, int fpargs, int type) {
2385 if (UseBuiltinSim) {
2386 starti;
2387 f(0b110, 31 ,29);
2388 f(0b00, 28, 25);
2389 // 4321098765
2390 f(0b0000000000, 24, 15);
2391 f(gpargs, 14, 11);
2392 f(fpargs, 10, 7);
2393 f(type, 6, 5);
2394 rf(Rn, 0);
2395 } else {
2396 blr(Rn);
2397 }
2398 }
2399
2400 void blrt(Register Rn, Register Rm) {
2401 if (UseBuiltinSim) {
2402 starti;
2403 f(0b110, 31 ,29);
2404 f(0b00, 28, 25);
2405 // 4321098765
2406 f(0b0000000001, 24, 15);
2407 // 43210
2408 f(0b00000, 14, 10);
2409 rf(Rm, 5);
2410 rf(Rn, 0);
2411 } else {
2412 blr(Rn);
2413 }
2414 }
2415
2416 void haltsim() {
2417 starti;
2418 f(0b111, 31 ,29);
2419 f(0b00, 28, 27);
2420 // 654321098765432109876543210
2421 f(0b000000000000000000000000000, 26, 0);
2422 }
2423
2424 Assembler(CodeBuffer* code) : AbstractAssembler(code) {
2425 }
2426
2427 virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
2428 Register tmp,
2429 int offset) {
2430 ShouldNotCallThis();
2431 return RegisterOrConstant();
2432 }
2433
2434 // Stack overflow checking
2435 virtual void bang_stack_with_offset(int offset);
2436
2437 static bool operand_valid_for_logical_immediate(bool is32, uint64_t imm);
2438 static bool operand_valid_for_add_sub_immediate(long imm);
2439 static bool operand_valid_for_float_immediate(double imm);
2440
2441 void emit_data64(jlong data, relocInfo::relocType rtype, int format = 0);
2442 void emit_data64(jlong data, RelocationHolder const& rspec, int format = 0);
2443 };
2444
2445 inline Assembler::Membar_mask_bits operator|(Assembler::Membar_mask_bits a,
2446 Assembler::Membar_mask_bits b) {
2447 return Assembler::Membar_mask_bits(unsigned(a)|unsigned(b));
2448 }
2449
2450 Instruction_aarch64::~Instruction_aarch64() {
2451 assem->emit();
2452 }
2453
2454 #undef starti
2455
2456 // Invert a condition
2457 inline const Assembler::Condition operator~(const Assembler::Condition cond) {
2458 return Assembler::Condition(int(cond) ^ 1);
2459 }
2460
2461 class BiasedLockingCounters;
2462
2463 extern "C" void das(uint64_t start, int len);
2464
2465 #endif // CPU_AARCH64_VM_ASSEMBLER_AARCH64_HPP