3408 return 0;
3409 }
3410
3411 const int Matcher::vector_shift_count_ideal_reg(int size) {
3412 return Op_VecX;
3413 }
3414
3415 // AES support not yet implemented
3416 const bool Matcher::pass_original_key_for_aes() {
3417 return false;
3418 }
3419
3420 // x86 supports misaligned vectors store/load.
3421 const bool Matcher::misaligned_vectors_ok() {
3422 return !AlignVector; // can be changed by flag
3423 }
3424
3425 // false => size gets scaled to BytesPerLong, ok.
3426 const bool Matcher::init_array_count_is_in_bytes = false;
3427
3428 // Threshold size for cleararray.
3429 const int Matcher::init_array_short_size = 18 * BytesPerLong;
3430
3431 // Use conditional move (CMOVL)
3432 const int Matcher::long_cmove_cost() {
3433 // long cmoves are no more expensive than int cmoves
3434 return 0;
3435 }
3436
3437 const int Matcher::float_cmove_cost() {
3438 // float cmoves are no more expensive than int cmoves
3439 return 0;
3440 }
3441
3442 // Does the CPU require late expand (see block.cpp for description of late expand)?
3443 const bool Matcher::require_postalloc_expand = false;
3444
3445 // Should the Matcher clone shifts on addressing modes, expecting them
3446 // to be subsumed into complex addressing expressions or compute them
3447 // into registers? True for Intel but false for most RISCs
3448 const bool Matcher::clone_shift_expressions = false;
3449
3450 // Do we need to mask the count passed to shift instructions or does
|
3408 return 0;
3409 }
3410
3411 const int Matcher::vector_shift_count_ideal_reg(int size) {
3412 return Op_VecX;
3413 }
3414
3415 // AES support not yet implemented
3416 const bool Matcher::pass_original_key_for_aes() {
3417 return false;
3418 }
3419
3420 // x86 supports misaligned vectors store/load.
3421 const bool Matcher::misaligned_vectors_ok() {
3422 return !AlignVector; // can be changed by flag
3423 }
3424
3425 // false => size gets scaled to BytesPerLong, ok.
3426 const bool Matcher::init_array_count_is_in_bytes = false;
3427
3428 // Use conditional move (CMOVL)
3429 const int Matcher::long_cmove_cost() {
3430 // long cmoves are no more expensive than int cmoves
3431 return 0;
3432 }
3433
3434 const int Matcher::float_cmove_cost() {
3435 // float cmoves are no more expensive than int cmoves
3436 return 0;
3437 }
3438
3439 // Does the CPU require late expand (see block.cpp for description of late expand)?
3440 const bool Matcher::require_postalloc_expand = false;
3441
3442 // Should the Matcher clone shifts on addressing modes, expecting them
3443 // to be subsumed into complex addressing expressions or compute them
3444 // into registers? True for Intel but false for most RISCs
3445 const bool Matcher::clone_shift_expressions = false;
3446
3447 // Do we need to mask the count passed to shift instructions or does
|