1 //
2 // Copyright (c) 1998, 2016, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Header information of the source block.
461 // Method declarations/definitions which are used outside
462 // the ad-scope can conveniently be defined here.
463 //
464 // To keep related declarations/definitions/uses close together,
465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
466
467 // Must be visible to the DFA in dfa_sparc.cpp
468 extern bool can_branch_register( Node *bol, Node *cmp );
469
470 extern bool use_block_zeroing(Node* count);
471
472 // Macros to extract hi & lo halves from a long pair.
473 // G0 is not part of any long pair, so assert on that.
474 // Prevents accidentally using G1 instead of G0.
475 #define LONG_HI_REG(x) (x)
476 #define LONG_LO_REG(x) (x)
477
478 class CallStubImpl {
479
480 //--------------------------------------------------------------
481 //---< Used for optimization in Compile::Shorten_branches >---
482 //--------------------------------------------------------------
483
484 public:
485 // Size of call trampoline stub.
486 static uint size_call_trampoline() {
487 return 0; // no call trampolines on this platform
488 }
489
490 // number of relocations needed by a call trampoline stub
491 static uint reloc_call_trampoline() {
492 return 0; // no call trampolines on this platform
493 }
494 };
495
496 class HandlerImpl {
497
498 public:
499
500 static int emit_exception_handler(CodeBuffer &cbuf);
501 static int emit_deopt_handler(CodeBuffer& cbuf);
502
503 static uint size_exception_handler() {
504 if (TraceJumps) {
505 return (400); // just a guess
506 }
507 return ( NativeJump::instruction_size ); // sethi;jmp;nop
508 }
509
510 static uint size_deopt_handler() {
511 if (TraceJumps) {
512 return (400); // just a guess
513 }
514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
515 }
516 };
517
518 %}
519
520 source %{
521 #define __ _masm.
522
523 // tertiary op of a LoadP or StoreP encoding
524 #define REGP_OP true
525
526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
528 static Register reg_to_register_object(int register_encoding);
529
530 // Used by the DFA in dfa_sparc.cpp.
531 // Check for being able to use a V9 branch-on-register. Requires a
532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
533 // extended. Doesn't work following an integer ADD, for example, because of
534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
536 // replace them with zero, which could become sign-extension in a different OS
537 // release. There's no obvious reason why an interrupt will ever fill these
538 // bits with non-zero junk (the registers are reloaded with standard LD
539 // instructions which either zero-fill or sign-fill).
540 bool can_branch_register( Node *bol, Node *cmp ) {
541 if( !BranchOnRegister ) return false;
542 #ifdef _LP64
543 if( cmp->Opcode() == Op_CmpP )
544 return true; // No problems with pointer compares
545 #endif
546 if( cmp->Opcode() == Op_CmpL )
547 return true; // No problems with long compares
548
549 if( !SparcV9RegsHiBitsZero ) return false;
550 if( bol->as_Bool()->_test._test != BoolTest::ne &&
551 bol->as_Bool()->_test._test != BoolTest::eq )
552 return false;
553
554 // Check for comparing against a 'safe' value. Any operation which
555 // clears out the high word is safe. Thus, loads and certain shifts
556 // are safe, as are non-negative constants. Any operation which
557 // preserves zero bits in the high word is safe as long as each of its
558 // inputs are safe. Thus, phis and bitwise booleans are safe if their
559 // inputs are safe. At present, the only important case to recognize
560 // seems to be loads. Constants should fold away, and shifts &
561 // logicals can use the 'cc' forms.
562 Node *x = cmp->in(1);
563 if( x->is_Load() ) return true;
564 if( x->is_Phi() ) {
565 for( uint i = 1; i < x->req(); i++ )
566 if( !x->in(i)->is_Load() )
567 return false;
568 return true;
569 }
570 return false;
571 }
572
573 bool use_block_zeroing(Node* count) {
574 // Use BIS for zeroing if count is not constant
575 // or it is >= BlockZeroingLowLimit.
576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
577 }
578
579 // ****************************************************************************
580
581 // REQUIRED FUNCTIONALITY
582
583 // !!!!! Special hack to get all type of calls to specify the byte offset
584 // from the start of the call to the point where the return address
585 // will point.
586 // The "return address" is the address of the call instruction, plus 8.
587
588 int MachCallStaticJavaNode::ret_addr_offset() {
589 int offset = NativeCall::instruction_size; // call; delay slot
590 if (_method_handle_invoke)
591 offset += 4; // restore SP
592 return offset;
593 }
594
595 int MachCallDynamicJavaNode::ret_addr_offset() {
596 int vtable_index = this->_vtable_index;
597 if (vtable_index < 0) {
598 // must be invalid_vtable_index, not nonvirtual_vtable_index
599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
600 return (NativeMovConstReg::instruction_size +
601 NativeCall::instruction_size); // sethi; setlo; call; delay slot
602 } else {
603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
604 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
605 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
606 int klass_load_size;
607 if (UseCompressedClassPointers) {
608 assert(Universe::heap() != NULL, "java heap should be initialized");
609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
610 } else {
611 klass_load_size = 1*BytesPerInstWord;
612 }
613 if (Assembler::is_simm13(v_off)) {
614 return klass_load_size +
615 (2*BytesPerInstWord + // ld_ptr, ld_ptr
616 NativeCall::instruction_size); // call; delay slot
617 } else {
618 return klass_load_size +
619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
620 NativeCall::instruction_size); // call; delay slot
621 }
622 }
623 }
624
625 int MachCallRuntimeNode::ret_addr_offset() {
626 #ifdef _LP64
627 if (MacroAssembler::is_far_target(entry_point())) {
628 return NativeFarCall::instruction_size;
629 } else {
630 return NativeCall::instruction_size;
631 }
632 #else
633 return NativeCall::instruction_size; // call; delay slot
634 #endif
635 }
636
637 // Indicate if the safepoint node needs the polling page as an input.
638 // Since Sparc does not have absolute addressing, it does.
639 bool SafePointNode::needs_polling_address_input() {
640 return true;
641 }
642
643 // emit an interrupt that is caught by the debugger (for debugging compiler)
644 void emit_break(CodeBuffer &cbuf) {
645 MacroAssembler _masm(&cbuf);
646 __ breakpoint_trap();
647 }
648
649 #ifndef PRODUCT
650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
651 st->print("TA");
652 }
653 #endif
654
655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
656 emit_break(cbuf);
657 }
658
659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
660 return MachNode::size(ra_);
661 }
662
663 // Traceable jump
664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
665 MacroAssembler _masm(&cbuf);
666 Register rdest = reg_to_register_object(jump_target);
667 __ JMP(rdest, 0);
668 __ delayed()->nop();
669 }
670
671 // Traceable jump and set exception pc
672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
673 MacroAssembler _masm(&cbuf);
674 Register rdest = reg_to_register_object(jump_target);
675 __ JMP(rdest, 0);
676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
677 }
678
679 void emit_nop(CodeBuffer &cbuf) {
680 MacroAssembler _masm(&cbuf);
681 __ nop();
682 }
683
684 void emit_illtrap(CodeBuffer &cbuf) {
685 MacroAssembler _masm(&cbuf);
686 __ illtrap(0);
687 }
688
689
690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
691 assert(n->rule() != loadUB_rule, "");
692
693 intptr_t offset = 0;
694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
695 const Node* addr = n->get_base_and_disp(offset, adr_type);
696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
697 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
698 assert(addr->bottom_type()->isa_oopptr() == atype, "");
699 atype = atype->add_offset(offset);
700 assert(disp32 == offset, "wrong disp32");
701 return atype->_offset;
702 }
703
704
705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
706 assert(n->rule() != loadUB_rule, "");
707
708 intptr_t offset = 0;
709 Node* addr = n->in(2);
710 assert(addr->bottom_type()->isa_oopptr() == atype, "");
711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
712 Node* a = addr->in(2/*AddPNode::Address*/);
713 Node* o = addr->in(3/*AddPNode::Offset*/);
714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
715 atype = a->bottom_type()->is_ptr()->add_offset(offset);
716 assert(atype->isa_oop_ptr(), "still an oop");
717 }
718 offset = atype->is_ptr()->_offset;
719 if (offset != Type::OffsetBot) offset += disp32;
720 return offset;
721 }
722
723 static inline jdouble replicate_immI(int con, int count, int width) {
724 // Load a constant replicated "count" times with width "width"
725 assert(count*width == 8 && width <= 4, "sanity");
726 int bit_width = width * 8;
727 jlong val = con;
728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
729 for (int i = 0; i < count - 1; i++) {
730 val |= (val << bit_width);
731 }
732 jdouble dval = *((jdouble*) &val); // coerce to double type
733 return dval;
734 }
735
736 static inline jdouble replicate_immF(float con) {
737 // Replicate float con 2 times and pack into vector.
738 int val = *((int*)&con);
739 jlong lval = val;
740 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
741 jdouble dval = *((jdouble*) &lval); // coerce to double type
742 return dval;
743 }
744
745 // Standard Sparc opcode form2 field breakdown
746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
747 f0 &= (1<<19)-1; // Mask displacement to 19 bits
748 int op = (f30 << 30) |
749 (f29 << 29) |
750 (f25 << 25) |
751 (f22 << 22) |
752 (f20 << 20) |
753 (f19 << 19) |
754 (f0 << 0);
755 cbuf.insts()->emit_int32(op);
756 }
757
758 // Standard Sparc opcode form2 field breakdown
759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
760 f0 >>= 10; // Drop 10 bits
761 f0 &= (1<<22)-1; // Mask displacement to 22 bits
762 int op = (f30 << 30) |
763 (f25 << 25) |
764 (f22 << 22) |
765 (f0 << 0);
766 cbuf.insts()->emit_int32(op);
767 }
768
769 // Standard Sparc opcode form3 field breakdown
770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
771 int op = (f30 << 30) |
772 (f25 << 25) |
773 (f19 << 19) |
774 (f14 << 14) |
775 (f5 << 5) |
776 (f0 << 0);
777 cbuf.insts()->emit_int32(op);
778 }
779
780 // Standard Sparc opcode form3 field breakdown
781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
782 simm13 &= (1<<13)-1; // Mask to 13 bits
783 int op = (f30 << 30) |
784 (f25 << 25) |
785 (f19 << 19) |
786 (f14 << 14) |
787 (1 << 13) | // bit to indicate immediate-mode
788 (simm13<<0);
789 cbuf.insts()->emit_int32(op);
790 }
791
792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
793 simm10 &= (1<<10)-1; // Mask to 10 bits
794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
795 }
796
797 #ifdef ASSERT
798 // Helper function for VerifyOops in emit_form3_mem_reg
799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
800 warning("VerifyOops encountered unexpected instruction:");
801 n->dump(2);
802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
803 }
804 #endif
805
806
807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
808 int src1_enc, int disp32, int src2_enc, int dst_enc) {
809
810 #ifdef ASSERT
811 // The following code implements the +VerifyOops feature.
812 // It verifies oop values which are loaded into or stored out of
813 // the current method activation. +VerifyOops complements techniques
814 // like ScavengeALot, because it eagerly inspects oops in transit,
815 // as they enter or leave the stack, as opposed to ScavengeALot,
816 // which inspects oops "at rest", in the stack or heap, at safepoints.
817 // For this reason, +VerifyOops can sometimes detect bugs very close
818 // to their point of creation. It can also serve as a cross-check
819 // on the validity of oop maps, when used toegether with ScavengeALot.
820
821 // It would be good to verify oops at other points, especially
822 // when an oop is used as a base pointer for a load or store.
823 // This is presently difficult, because it is hard to know when
824 // a base address is biased or not. (If we had such information,
825 // it would be easy and useful to make a two-argument version of
826 // verify_oop which unbiases the base, and performs verification.)
827
828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
829 bool is_verified_oop_base = false;
830 bool is_verified_oop_load = false;
831 bool is_verified_oop_store = false;
832 int tmp_enc = -1;
833 if (VerifyOops && src1_enc != R_SP_enc) {
834 // classify the op, mainly for an assert check
835 int st_op = 0, ld_op = 0;
836 switch (primary) {
837 case Assembler::stb_op3: st_op = Op_StoreB; break;
838 case Assembler::sth_op3: st_op = Op_StoreC; break;
839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
840 case Assembler::stw_op3: st_op = Op_StoreI; break;
841 case Assembler::std_op3: st_op = Op_StoreL; break;
842 case Assembler::stf_op3: st_op = Op_StoreF; break;
843 case Assembler::stdf_op3: st_op = Op_StoreD; break;
844
845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
849 case Assembler::ldx_op3: // may become LoadP or stay LoadI
850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
851 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
852 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
853 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
854 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
856
857 default: ShouldNotReachHere();
858 }
859 if (tertiary == REGP_OP) {
860 if (st_op == Op_StoreI) st_op = Op_StoreP;
861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
862 else ShouldNotReachHere();
863 if (st_op) {
864 // a store
865 // inputs are (0:control, 1:memory, 2:address, 3:value)
866 Node* n2 = n->in(3);
867 if (n2 != NULL) {
868 const Type* t = n2->bottom_type();
869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
870 }
871 } else {
872 // a load
873 const Type* t = n->bottom_type();
874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
875 }
876 }
877
878 if (ld_op) {
879 // a Load
880 // inputs are (0:control, 1:memory, 2:address)
881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
892 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
893 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
894 !(n->rule() == loadUB_rule)) {
895 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
896 }
897 } else if (st_op) {
898 // a Store
899 // inputs are (0:control, 1:memory, 2:address, 3:value)
900 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
901 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
902 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
903 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
904 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
905 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
906 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
907 verify_oops_warning(n, n->ideal_Opcode(), st_op);
908 }
909 }
910
911 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
912 Node* addr = n->in(2);
913 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
914 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
915 if (atype != NULL) {
916 intptr_t offset = get_offset_from_base(n, atype, disp32);
917 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
918 if (offset != offset_2) {
919 get_offset_from_base(n, atype, disp32);
920 get_offset_from_base_2(n, atype, disp32);
921 }
922 assert(offset == offset_2, "different offsets");
923 if (offset == disp32) {
924 // we now know that src1 is a true oop pointer
925 is_verified_oop_base = true;
926 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
927 if( primary == Assembler::ldd_op3 ) {
928 is_verified_oop_base = false; // Cannot 'ldd' into O7
929 } else {
930 tmp_enc = dst_enc;
931 dst_enc = R_O7_enc; // Load into O7; preserve source oop
932 assert(src1_enc != dst_enc, "");
933 }
934 }
935 }
936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
937 || offset == oopDesc::mark_offset_in_bytes())) {
938 // loading the mark should not be allowed either, but
939 // we don't check this since it conflicts with InlineObjectHash
940 // usage of LoadINode to get the mark. We could keep the
941 // check if we create a new LoadMarkNode
942 // but do not verify the object before its header is initialized
943 ShouldNotReachHere();
944 }
945 }
946 }
947 }
948 }
949 #endif
950
951 uint instr = (Assembler::ldst_op << 30)
952 | (dst_enc << 25)
953 | (primary << 19)
954 | (src1_enc << 14);
955
956 uint index = src2_enc;
957 int disp = disp32;
958
959 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
960 disp += STACK_BIAS;
961 // Check that stack offset fits, load into O7 if not
962 if (!Assembler::is_simm13(disp)) {
963 MacroAssembler _masm(&cbuf);
964 __ set(disp, O7);
965 if (index != R_G0_enc) {
966 __ add(O7, reg_to_register_object(index), O7);
967 }
968 index = R_O7_enc;
969 disp = 0;
970 }
971 }
972
973 if( disp == 0 ) {
974 // use reg-reg form
975 // bit 13 is already zero
976 instr |= index;
977 } else {
978 // use reg-imm form
979 instr |= 0x00002000; // set bit 13 to one
980 instr |= disp & 0x1FFF;
981 }
982
983 cbuf.insts()->emit_int32(instr);
984
985 #ifdef ASSERT
986 if (VerifyOops) {
987 MacroAssembler _masm(&cbuf);
988 if (is_verified_oop_base) {
989 __ verify_oop(reg_to_register_object(src1_enc));
990 }
991 if (is_verified_oop_store) {
992 __ verify_oop(reg_to_register_object(dst_enc));
993 }
994 if (tmp_enc != -1) {
995 __ mov(O7, reg_to_register_object(tmp_enc));
996 }
997 if (is_verified_oop_load) {
998 __ verify_oop(reg_to_register_object(dst_enc));
999 }
1000 }
1001 #endif
1002 }
1003
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
1005 // The method which records debug information at every safepoint
1006 // expects the call to be the first instruction in the snippet as
1007 // it creates a PcDesc structure which tracks the offset of a call
1008 // from the start of the codeBlob. This offset is computed as
1009 // code_end() - code_begin() of the code which has been emitted
1010 // so far.
1011 // In this particular case we have skirted around the problem by
1012 // putting the "mov" instruction in the delay slot but the problem
1013 // may bite us again at some other point and a cleaner/generic
1014 // solution using relocations would be needed.
1015 MacroAssembler _masm(&cbuf);
1016 __ set_inst_mark();
1017
1018 // We flush the current window just so that there is a valid stack copy
1019 // the fact that the current window becomes active again instantly is
1020 // not a problem there is nothing live in it.
1021
1022 #ifdef ASSERT
1023 int startpos = __ offset();
1024 #endif /* ASSERT */
1025
1026 __ call((address)entry_point, rspec);
1027
1028 if (preserve_g2) __ delayed()->mov(G2, L7);
1029 else __ delayed()->nop();
1030
1031 if (preserve_g2) __ mov(L7, G2);
1032
1033 #ifdef ASSERT
1034 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1035 #ifdef _LP64
1036 // Trash argument dump slots.
1037 __ set(0xb0b8ac0db0b8ac0d, G1);
1038 __ mov(G1, G5);
1039 __ stx(G1, SP, STACK_BIAS + 0x80);
1040 __ stx(G1, SP, STACK_BIAS + 0x88);
1041 __ stx(G1, SP, STACK_BIAS + 0x90);
1042 __ stx(G1, SP, STACK_BIAS + 0x98);
1043 __ stx(G1, SP, STACK_BIAS + 0xA0);
1044 __ stx(G1, SP, STACK_BIAS + 0xA8);
1045 #else // _LP64
1046 // this is also a native call, so smash the first 7 stack locations,
1047 // and the various registers
1048
1049 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1050 // while [SP+0x44..0x58] are the argument dump slots.
1051 __ set((intptr_t)0xbaadf00d, G1);
1052 __ mov(G1, G5);
1053 __ sllx(G1, 32, G1);
1054 __ or3(G1, G5, G1);
1055 __ mov(G1, G5);
1056 __ stx(G1, SP, 0x40);
1057 __ stx(G1, SP, 0x48);
1058 __ stx(G1, SP, 0x50);
1059 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1060 #endif // _LP64
1061 }
1062 #endif /*ASSERT*/
1063 }
1064
1065 //=============================================================================
1066 // REQUIRED FUNCTIONALITY for encoding
1067 void emit_lo(CodeBuffer &cbuf, int val) { }
1068 void emit_hi(CodeBuffer &cbuf, int val) { }
1069
1070
1071 //=============================================================================
1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1073
1074 int Compile::ConstantTable::calculate_table_base_offset() const {
1075 if (UseRDPCForConstantTableBase) {
1076 // The table base offset might be less but then it fits into
1077 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1078 return Assembler::min_simm13();
1079 } else {
1080 int offset = -(size() / 2);
1081 if (!Assembler::is_simm13(offset)) {
1082 offset = Assembler::min_simm13();
1083 }
1084 return offset;
1085 }
1086 }
1087
1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1090 ShouldNotReachHere();
1091 }
1092
1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1094 Compile* C = ra_->C;
1095 Compile::ConstantTable& constant_table = C->constant_table();
1096 MacroAssembler _masm(&cbuf);
1097
1098 Register r = as_Register(ra_->get_encode(this));
1099 CodeSection* consts_section = __ code()->consts();
1100 int consts_size = consts_section->align_at_start(consts_section->size());
1101 assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1102
1103 if (UseRDPCForConstantTableBase) {
1104 // For the following RDPC logic to work correctly the consts
1105 // section must be allocated right before the insts section. This
1106 // assert checks for that. The layout and the SECT_* constants
1107 // are defined in src/share/vm/asm/codeBuffer.hpp.
1108 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1109 int insts_offset = __ offset();
1110
1111 // Layout:
1112 //
1113 // |----------- consts section ------------|----------- insts section -----------...
1114 // |------ constant table -----|- padding -|------------------x----
1115 // \ current PC (RDPC instruction)
1116 // |<------------- consts_size ----------->|<- insts_offset ->|
1117 // \ table base
1118 // The table base offset is later added to the load displacement
1119 // so it has to be negative.
1120 int table_base_offset = -(consts_size + insts_offset);
1121 int disp;
1122
1123 // If the displacement from the current PC to the constant table
1124 // base fits into simm13 we set the constant table base to the
1125 // current PC.
1126 if (Assembler::is_simm13(table_base_offset)) {
1127 constant_table.set_table_base_offset(table_base_offset);
1128 disp = 0;
1129 } else {
1130 // Otherwise we set the constant table base offset to the
1131 // maximum negative displacement of load instructions to keep
1132 // the disp as small as possible:
1133 //
1134 // |<------------- consts_size ----------->|<- insts_offset ->|
1135 // |<--------- min_simm13 --------->|<-------- disp --------->|
1136 // \ table base
1137 table_base_offset = Assembler::min_simm13();
1138 constant_table.set_table_base_offset(table_base_offset);
1139 disp = (consts_size + insts_offset) + table_base_offset;
1140 }
1141
1142 __ rdpc(r);
1143
1144 if (disp != 0) {
1145 assert(r != O7, "need temporary");
1146 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1147 }
1148 }
1149 else {
1150 // Materialize the constant table base.
1151 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1152 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1153 AddressLiteral base(baseaddr, rspec);
1154 __ set(base, r);
1155 }
1156 }
1157
1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1159 if (UseRDPCForConstantTableBase) {
1160 // This is really the worst case but generally it's only 1 instruction.
1161 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1162 } else {
1163 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1164 }
1165 }
1166
1167 #ifndef PRODUCT
1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1169 char reg[128];
1170 ra_->dump_register(this, reg);
1171 if (UseRDPCForConstantTableBase) {
1172 st->print("RDPC %s\t! constant table base", reg);
1173 } else {
1174 st->print("SET &constanttable,%s\t! constant table base", reg);
1175 }
1176 }
1177 #endif
1178
1179
1180 //=============================================================================
1181
1182 #ifndef PRODUCT
1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184 Compile* C = ra_->C;
1185
1186 for (int i = 0; i < OptoPrologueNops; i++) {
1187 st->print_cr("NOP"); st->print("\t");
1188 }
1189
1190 if( VerifyThread ) {
1191 st->print_cr("Verify_Thread"); st->print("\t");
1192 }
1193
1194 size_t framesize = C->frame_size_in_bytes();
1195 int bangsize = C->bang_size_in_bytes();
1196
1197 // Calls to C2R adapters often do not accept exceptional returns.
1198 // We require that their callers must bang for them. But be careful, because
1199 // some VM calls (such as call site linkage) can use several kilobytes of
1200 // stack. But the stack safety zone should account for that.
1201 // See bugs 4446381, 4468289, 4497237.
1202 if (C->need_stack_bang(bangsize)) {
1203 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1204 }
1205
1206 if (Assembler::is_simm13(-framesize)) {
1207 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1208 } else {
1209 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1210 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1211 st->print ("SAVE R_SP,R_G3,R_SP");
1212 }
1213
1214 }
1215 #endif
1216
1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1218 Compile* C = ra_->C;
1219 MacroAssembler _masm(&cbuf);
1220
1221 for (int i = 0; i < OptoPrologueNops; i++) {
1222 __ nop();
1223 }
1224
1225 __ verify_thread();
1226
1227 size_t framesize = C->frame_size_in_bytes();
1228 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1229 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1230 int bangsize = C->bang_size_in_bytes();
1231
1232 // Calls to C2R adapters often do not accept exceptional returns.
1233 // We require that their callers must bang for them. But be careful, because
1234 // some VM calls (such as call site linkage) can use several kilobytes of
1235 // stack. But the stack safety zone should account for that.
1236 // See bugs 4446381, 4468289, 4497237.
1237 if (C->need_stack_bang(bangsize)) {
1238 __ generate_stack_overflow_check(bangsize);
1239 }
1240
1241 if (Assembler::is_simm13(-framesize)) {
1242 __ save(SP, -framesize, SP);
1243 } else {
1244 __ sethi(-framesize & ~0x3ff, G3);
1245 __ add(G3, -framesize & 0x3ff, G3);
1246 __ save(SP, G3, SP);
1247 }
1248 C->set_frame_complete( __ offset() );
1249
1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1251 // NOTE: We set the table base offset here because users might be
1252 // emitted before MachConstantBaseNode.
1253 Compile::ConstantTable& constant_table = C->constant_table();
1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1255 }
1256 }
1257
1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1261
1262 int MachPrologNode::reloc() const {
1263 return 10; // a large enough number
1264 }
1265
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1269 Compile* C = ra_->C;
1270
1271 if(do_polling() && ra_->C->is_method_compilation()) {
1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1273 #ifdef _LP64
1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1275 #else
1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1277 #endif
1278 }
1279
1280 if(do_polling()) {
1281 if (UseCBCond && !ra_->C->is_method_compilation()) {
1282 st->print("NOP\n\t");
1283 }
1284 st->print("RET\n\t");
1285 }
1286
1287 st->print("RESTORE");
1288 }
1289 #endif
1290
1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1292 MacroAssembler _masm(&cbuf);
1293 Compile* C = ra_->C;
1294
1295 __ verify_thread();
1296
1297 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1298 __ reserved_stack_check();
1299 }
1300
1301 // If this does safepoint polling, then do it here
1302 if(do_polling() && ra_->C->is_method_compilation()) {
1303 AddressLiteral polling_page(os::get_polling_page());
1304 __ sethi(polling_page, L0);
1305 __ relocate(relocInfo::poll_return_type);
1306 __ ld_ptr(L0, 0, G0);
1307 }
1308
1309 // If this is a return, then stuff the restore in the delay slot
1310 if(do_polling()) {
1311 if (UseCBCond && !ra_->C->is_method_compilation()) {
1312 // Insert extra padding for the case when the epilogue is preceded by
1313 // a cbcond jump, which can't be followed by a CTI instruction
1314 __ nop();
1315 }
1316 __ ret();
1317 __ delayed()->restore();
1318 } else {
1319 __ restore();
1320 }
1321 }
1322
1323 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1324 return MachNode::size(ra_);
1325 }
1326
1327 int MachEpilogNode::reloc() const {
1328 return 16; // a large enough number
1329 }
1330
1331 const Pipeline * MachEpilogNode::pipeline() const {
1332 return MachNode::pipeline_class();
1333 }
1334
1335 int MachEpilogNode::safepoint_offset() const {
1336 assert( do_polling(), "no return for this epilog node");
1337 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1338 }
1339
1340 //=============================================================================
1341
1342 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1343 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1344 static enum RC rc_class( OptoReg::Name reg ) {
1345 if (!OptoReg::is_valid(reg)) return rc_bad;
1346 if (OptoReg::is_stack(reg)) return rc_stack;
1347 VMReg r = OptoReg::as_VMReg(reg);
1348 if (r->is_Register()) return rc_int;
1349 assert(r->is_FloatRegister(), "must be");
1350 return rc_float;
1351 }
1352
1353 #ifndef PRODUCT
1354 ATTRIBUTE_PRINTF(2, 3)
1355 static void print_helper(outputStream* st, const char* format, ...) {
1356 if (st->position() > 0) {
1357 st->cr();
1358 st->sp();
1359 }
1360 va_list ap;
1361 va_start(ap, format);
1362 st->vprint(format, ap);
1363 va_end(ap);
1364 }
1365 #endif // !PRODUCT
1366
1367 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1368 if (cbuf) {
1369 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1370 }
1371 #ifndef PRODUCT
1372 else {
1373 if (is_load) {
1374 print_helper(st, "%s [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1375 } else {
1376 print_helper(st, "%s R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1377 }
1378 }
1379 #endif
1380 }
1381
1382 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1383 if (cbuf) {
1384 emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1385 }
1386 #ifndef PRODUCT
1387 else {
1388 print_helper(st, "%s R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1389 }
1390 #endif
1391 }
1392
1393 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1394 CodeBuffer *cbuf,
1395 PhaseRegAlloc *ra_,
1396 outputStream* st) {
1397 // Get registers to move
1398 OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1399 OptoReg::Name src_first = ra_->get_reg_first(mach->in(1));
1400 OptoReg::Name dst_second = ra_->get_reg_second(mach);
1401 OptoReg::Name dst_first = ra_->get_reg_first(mach);
1402
1403 enum RC src_second_rc = rc_class(src_second);
1404 enum RC src_first_rc = rc_class(src_first);
1405 enum RC dst_second_rc = rc_class(dst_second);
1406 enum RC dst_first_rc = rc_class(dst_first);
1407
1408 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1409
1410 if (src_first == dst_first && src_second == dst_second) {
1411 return; // Self copy, no move
1412 }
1413
1414 // --------------------------------------
1415 // Check for mem-mem move. Load into unused float registers and fall into
1416 // the float-store case.
1417 if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1418 int offset = ra_->reg2offset(src_first);
1419 // Further check for aligned-adjacent pair, so we can use a double load
1420 if ((src_first&1) == 0 && src_first+1 == src_second) {
1421 src_second = OptoReg::Name(R_F31_num);
1422 src_second_rc = rc_float;
1423 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1424 } else {
1425 impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1426 }
1427 src_first = OptoReg::Name(R_F30_num);
1428 src_first_rc = rc_float;
1429 }
1430
1431 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1432 int offset = ra_->reg2offset(src_second);
1433 impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1434 src_second = OptoReg::Name(R_F31_num);
1435 src_second_rc = rc_float;
1436 }
1437
1438 // --------------------------------------
1439 // Check for float->int copy; requires a trip through memory
1440 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1441 int offset = frame::register_save_words*wordSize;
1442 if (cbuf) {
1443 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1444 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1445 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1446 emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1447 }
1448 #ifndef PRODUCT
1449 else {
1450 print_helper(st, "SUB R_SP,16,R_SP");
1451 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1452 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1453 print_helper(st, "ADD R_SP,16,R_SP");
1454 }
1455 #endif
1456 }
1457
1458 // Check for float->int copy on T4
1459 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1460 // Further check for aligned-adjacent pair, so we can use a double move
1461 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1462 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1463 return;
1464 }
1465 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1466 }
1467 // Check for int->float copy on T4
1468 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1469 // Further check for aligned-adjacent pair, so we can use a double move
1470 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1471 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1472 return;
1473 }
1474 impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1475 }
1476
1477 // --------------------------------------
1478 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1479 // In such cases, I have to do the big-endian swap. For aligned targets, the
1480 // hardware does the flop for me. Doubles are always aligned, so no problem
1481 // there. Misaligned sources only come from native-long-returns (handled
1482 // special below).
1483 #ifndef _LP64
1484 if (src_first_rc == rc_int && // source is already big-endian
1485 src_second_rc != rc_bad && // 64-bit move
1486 ((dst_first & 1) != 0 || dst_second != dst_first + 1)) { // misaligned dst
1487 assert((src_first & 1) == 0 && src_second == src_first + 1, "source must be aligned");
1488 // Do the big-endian flop.
1489 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1490 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1491 }
1492 #endif
1493
1494 // --------------------------------------
1495 // Check for integer reg-reg copy
1496 if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1497 #ifndef _LP64
1498 if (src_first == R_O0_num && src_second == R_O1_num) { // Check for the evil O0/O1 native long-return case
1499 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1500 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1501 // operand contains the least significant word of the 64-bit value and vice versa.
1502 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1503 assert((dst_first & 1) == 0 && dst_second == dst_first + 1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1504 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1505 if ( cbuf ) {
1506 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020);
1507 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000);
1508 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second]);
1509 #ifndef PRODUCT
1510 } else {
1511 print_helper(st, "SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1512 print_helper(st, "SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1513 print_helper(st, "OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1514 #endif
1515 }
1516 return;
1517 } else if (dst_first == R_I0_num && dst_second == R_I1_num) {
1518 // returning a long value in I0/I1
1519 // a SpillCopy must be able to target a return instruction's reg_class
1520 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1521 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1522 // operand contains the least significant word of the 64-bit value and vice versa.
1523 OptoReg::Name tdest = dst_first;
1524
1525 if (src_first == dst_first) {
1526 tdest = OptoReg::Name(R_O7_num);
1527 }
1528
1529 if (cbuf) {
1530 assert((src_first & 1) == 0 && (src_first + 1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1531 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1532 // ShrL_reg_imm6
1533 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000);
1534 // ShrR_reg_imm6 src, 0, dst
1535 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000);
1536 if (tdest != dst_first) {
1537 emit3 (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest]);
1538 }
1539 }
1540 #ifndef PRODUCT
1541 else {
1542 print_helper(st, "SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1543 print_helper(st, "SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1544 if (tdest != dst_first) {
1545 print_helper(st, "MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1546 }
1547 }
1548 #endif // PRODUCT
1549 return size+8;
1550 }
1551 #endif // !_LP64
1552 // Else normal reg-reg copy
1553 assert(src_second != dst_first, "smashed second before evacuating it");
1554 impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV ", st);
1555 assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1556 // This moves an aligned adjacent pair.
1557 // See if we are done.
1558 if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1559 return;
1560 }
1561 }
1562
1563 // Check for integer store
1564 if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1565 int offset = ra_->reg2offset(dst_first);
1566 // Further check for aligned-adjacent pair, so we can use a double store
1567 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1568 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1569 return;
1570 }
1571 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1572 }
1573
1574 // Check for integer load
1575 if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1576 int offset = ra_->reg2offset(src_first);
1577 // Further check for aligned-adjacent pair, so we can use a double load
1578 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1579 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1580 return;
1581 }
1582 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1583 }
1584
1585 // Check for float reg-reg copy
1586 if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1587 // Further check for aligned-adjacent pair, so we can use a double move
1588 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1589 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1590 return;
1591 }
1592 impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1593 }
1594
1595 // Check for float store
1596 if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1597 int offset = ra_->reg2offset(dst_first);
1598 // Further check for aligned-adjacent pair, so we can use a double store
1599 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1600 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1601 return;
1602 }
1603 impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1604 }
1605
1606 // Check for float load
1607 if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1608 int offset = ra_->reg2offset(src_first);
1609 // Further check for aligned-adjacent pair, so we can use a double load
1610 if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1611 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1612 return;
1613 }
1614 impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1615 }
1616
1617 // --------------------------------------------------------------------
1618 // Check for hi bits still needing moving. Only happens for misaligned
1619 // arguments to native calls.
1620 if (src_second == dst_second) {
1621 return; // Self copy; no move
1622 }
1623 assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1624
1625 #ifndef _LP64
1626 // In the LP64 build, all registers can be moved as aligned/adjacent
1627 // pairs, so there's never any need to move the high bits separately.
1628 // The 32-bit builds have to deal with the 32-bit ABI which can force
1629 // all sorts of silly alignment problems.
1630
1631 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1632 // 32-bits of a 64-bit register, but are needed in low bits of another
1633 // register (else it's a hi-bits-to-hi-bits copy which should have
1634 // happened already as part of a 64-bit move)
1635 if (src_second_rc == rc_int && dst_second_rc == rc_int) {
1636 assert((src_second & 1) == 1, "its the evil O0/O1 native return case");
1637 assert((dst_second & 1) == 0, "should have moved with 1 64-bit move");
1638 // Shift src_second down to dst_second's low bits.
1639 if (cbuf) {
1640 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1641 #ifndef PRODUCT
1642 } else {
1643 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second - 1), OptoReg::regname(dst_second));
1644 #endif
1645 }
1646 return;
1647 }
1648
1649 // Check for high word integer store. Must down-shift the hi bits
1650 // into a temp register, then fall into the case of storing int bits.
1651 if (src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second & 1) == 1) {
1652 // Shift src_second down to dst_second's low bits.
1653 if (cbuf) {
1654 emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1655 #ifndef PRODUCT
1656 } else {
1657 print_helper(st, "SRLX R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second-1), OptoReg::regname(R_O7_num));
1658 #endif
1659 }
1660 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1661 }
1662
1663 // Check for high word integer load
1664 if (dst_second_rc == rc_int && src_second_rc == rc_stack)
1665 return impl_helper(this, cbuf, ra_, true, ra_->reg2offset(src_second), dst_second, Assembler::lduw_op3, "LDUW", size, st);
1666
1667 // Check for high word integer store
1668 if (src_second_rc == rc_int && dst_second_rc == rc_stack)
1669 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stw_op3, "STW ", size, st);
1670
1671 // Check for high word float store
1672 if (src_second_rc == rc_float && dst_second_rc == rc_stack)
1673 return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stf_op3, "STF ", size, st);
1674
1675 #endif // !_LP64
1676
1677 Unimplemented();
1678 }
1679
1680 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1681 PhaseRegAlloc *ra_,
1682 bool do_size,
1683 outputStream* st) const {
1684 assert(!do_size, "not supported");
1685 mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1686 return 0;
1687 }
1688
1689 #ifndef PRODUCT
1690 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1691 implementation( NULL, ra_, false, st );
1692 }
1693 #endif
1694
1695 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1696 implementation( &cbuf, ra_, false, NULL );
1697 }
1698
1699 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1700 return MachNode::size(ra_);
1701 }
1702
1703 //=============================================================================
1704 #ifndef PRODUCT
1705 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1706 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1707 }
1708 #endif
1709
1710 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1711 MacroAssembler _masm(&cbuf);
1712 for (int i = 0; i < _count; i += 1) {
1713 __ nop();
1714 }
1715 }
1716
1717 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1718 return 4 * _count;
1719 }
1720
1721
1722 //=============================================================================
1723 #ifndef PRODUCT
1724 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1725 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1726 int reg = ra_->get_reg_first(this);
1727 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1728 }
1729 #endif
1730
1731 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1732 MacroAssembler _masm(&cbuf);
1733 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1734 int reg = ra_->get_encode(this);
1735
1736 if (Assembler::is_simm13(offset)) {
1737 __ add(SP, offset, reg_to_register_object(reg));
1738 } else {
1739 __ set(offset, O7);
1740 __ add(SP, O7, reg_to_register_object(reg));
1741 }
1742 }
1743
1744 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1745 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1746 assert(ra_ == ra_->C->regalloc(), "sanity");
1747 return ra_->C->scratch_emit_size(this);
1748 }
1749
1750 //=============================================================================
1751 #ifndef PRODUCT
1752 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1753 st->print_cr("\nUEP:");
1754 #ifdef _LP64
1755 if (UseCompressedClassPointers) {
1756 assert(Universe::heap() != NULL, "java heap should be initialized");
1757 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1758 if (Universe::narrow_klass_base() != 0) {
1759 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1760 if (Universe::narrow_klass_shift() != 0) {
1761 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1762 }
1763 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1764 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1765 } else {
1766 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1767 }
1768 } else {
1769 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1770 }
1771 st->print_cr("\tCMP R_G5,R_G3" );
1772 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1773 #else // _LP64
1774 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1775 st->print_cr("\tCMP R_G5,R_G3" );
1776 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1777 #endif // _LP64
1778 }
1779 #endif
1780
1781 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1782 MacroAssembler _masm(&cbuf);
1783 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1784 Register temp_reg = G3;
1785 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1786
1787 // Load klass from receiver
1788 __ load_klass(O0, temp_reg);
1789 // Compare against expected klass
1790 __ cmp(temp_reg, G5_ic_reg);
1791 // Branch to miss code, checks xcc or icc depending
1792 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1793 }
1794
1795 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1796 return MachNode::size(ra_);
1797 }
1798
1799
1800 //=============================================================================
1801
1802
1803 // Emit exception handler code.
1804 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1805 Register temp_reg = G3;
1806 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1807 MacroAssembler _masm(&cbuf);
1808
1809 address base = __ start_a_stub(size_exception_handler());
1810 if (base == NULL) {
1811 ciEnv::current()->record_failure("CodeCache is full");
1812 return 0; // CodeBuffer::expand failed
1813 }
1814
1815 int offset = __ offset();
1816
1817 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1818 __ delayed()->nop();
1819
1820 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1821
1822 __ end_a_stub();
1823
1824 return offset;
1825 }
1826
1827 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1828 // Can't use any of the current frame's registers as we may have deopted
1829 // at a poll and everything (including G3) can be live.
1830 Register temp_reg = L0;
1831 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1832 MacroAssembler _masm(&cbuf);
1833
1834 address base = __ start_a_stub(size_deopt_handler());
1835 if (base == NULL) {
1836 ciEnv::current()->record_failure("CodeCache is full");
1837 return 0; // CodeBuffer::expand failed
1838 }
1839
1840 int offset = __ offset();
1841 __ save_frame(0);
1842 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1843 __ delayed()->restore();
1844
1845 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1846
1847 __ end_a_stub();
1848 return offset;
1849
1850 }
1851
1852 // Given a register encoding, produce a Integer Register object
1853 static Register reg_to_register_object(int register_encoding) {
1854 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1855 return as_Register(register_encoding);
1856 }
1857
1858 // Given a register encoding, produce a single-precision Float Register object
1859 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1860 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1861 return as_SingleFloatRegister(register_encoding);
1862 }
1863
1864 // Given a register encoding, produce a double-precision Float Register object
1865 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1866 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1867 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1868 return as_DoubleFloatRegister(register_encoding);
1869 }
1870
1871 const bool Matcher::match_rule_supported(int opcode) {
1872 if (!has_match_rule(opcode))
1873 return false;
1874
1875 switch (opcode) {
1876 case Op_CountLeadingZerosI:
1877 case Op_CountLeadingZerosL:
1878 case Op_CountTrailingZerosI:
1879 case Op_CountTrailingZerosL:
1880 case Op_PopCountI:
1881 case Op_PopCountL:
1882 if (!UsePopCountInstruction)
1883 return false;
1884 case Op_CompareAndSwapL:
1885 #ifdef _LP64
1886 case Op_CompareAndSwapP:
1887 #endif
1888 if (!VM_Version::supports_cx8())
1889 return false;
1890 break;
1891 }
1892
1893 return true; // Per default match rules are supported.
1894 }
1895
1896 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1897
1898 // TODO
1899 // identify extra cases that we might want to provide match rules for
1900 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1901 bool ret_value = match_rule_supported(opcode);
1902 // Add rules here.
1903
1904 return ret_value; // Per default match rules are supported.
1905 }
1906
1907 const int Matcher::float_pressure(int default_pressure_threshold) {
1908 return default_pressure_threshold;
1909 }
1910
1911 int Matcher::regnum_to_fpu_offset(int regnum) {
1912 return regnum - 32; // The FP registers are in the second chunk
1913 }
1914
1915 #ifdef ASSERT
1916 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1917 #endif
1918
1919 // Vector width in bytes
1920 const int Matcher::vector_width_in_bytes(BasicType bt) {
1921 assert(MaxVectorSize == 8, "");
1922 return 8;
1923 }
1924
1925 // Vector ideal reg
1926 const int Matcher::vector_ideal_reg(int size) {
1927 assert(MaxVectorSize == 8, "");
1928 return Op_RegD;
1929 }
1930
1931 const int Matcher::vector_shift_count_ideal_reg(int size) {
1932 fatal("vector shift is not supported");
1933 return Node::NotAMachineReg;
1934 }
1935
1936 // Limits on vector size (number of elements) loaded into vector.
1937 const int Matcher::max_vector_size(const BasicType bt) {
1938 assert(is_java_primitive(bt), "only primitive type vectors");
1939 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1940 }
1941
1942 const int Matcher::min_vector_size(const BasicType bt) {
1943 return max_vector_size(bt); // Same as max.
1944 }
1945
1946 // SPARC doesn't support misaligned vectors store/load.
1947 const bool Matcher::misaligned_vectors_ok() {
1948 return false;
1949 }
1950
1951 // Current (2013) SPARC platforms need to read original key
1952 // to construct decryption expanded key
1953 const bool Matcher::pass_original_key_for_aes() {
1954 return true;
1955 }
1956
1957 // USII supports fxtof through the whole range of number, USIII doesn't
1958 const bool Matcher::convL2FSupported(void) {
1959 return VM_Version::has_fast_fxtof();
1960 }
1961
1962 // Is this branch offset short enough that a short branch can be used?
1963 //
1964 // NOTE: If the platform does not provide any short branch variants, then
1965 // this method should return false for offset 0.
1966 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1967 // The passed offset is relative to address of the branch.
1968 // Don't need to adjust the offset.
1969 return UseCBCond && Assembler::is_simm12(offset);
1970 }
1971
1972 const bool Matcher::isSimpleConstant64(jlong value) {
1973 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1974 // Depends on optimizations in MacroAssembler::setx.
1975 int hi = (int)(value >> 32);
1976 int lo = (int)(value & ~0);
1977 return (hi == 0) || (hi == -1) || (lo == 0);
1978 }
1979
1980 // No scaling for the parameter the ClearArray node.
1981 const bool Matcher::init_array_count_is_in_bytes = true;
1982
1983 // No additional cost for CMOVL.
1984 const int Matcher::long_cmove_cost() { return 0; }
1985
1986 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1987 const int Matcher::float_cmove_cost() {
1988 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1989 }
1990
1991 // Does the CPU require late expand (see block.cpp for description of late expand)?
1992 const bool Matcher::require_postalloc_expand = false;
1993
1994 // Should the Matcher clone shifts on addressing modes, expecting them to
1995 // be subsumed into complex addressing expressions or compute them into
1996 // registers? True for Intel but false for most RISCs
1997 const bool Matcher::clone_shift_expressions = false;
1998
1999 // Do we need to mask the count passed to shift instructions or does
2000 // the cpu only look at the lower 5/6 bits anyway?
2001 const bool Matcher::need_masked_shift_count = false;
2002
2003 bool Matcher::narrow_oop_use_complex_address() {
2004 NOT_LP64(ShouldNotCallThis());
2005 assert(UseCompressedOops, "only for compressed oops code");
2006 return false;
2007 }
2008
2009 bool Matcher::narrow_klass_use_complex_address() {
2010 NOT_LP64(ShouldNotCallThis());
2011 assert(UseCompressedClassPointers, "only for compressed klass code");
2012 return false;
2013 }
2014
2015 // Is it better to copy float constants, or load them directly from memory?
2016 // Intel can load a float constant from a direct address, requiring no
2017 // extra registers. Most RISCs will have to materialize an address into a
2018 // register first, so they would do better to copy the constant from stack.
2019 const bool Matcher::rematerialize_float_constants = false;
2020
2021 // If CPU can load and store mis-aligned doubles directly then no fixup is
2022 // needed. Else we split the double into 2 integer pieces and move it
2023 // piece-by-piece. Only happens when passing doubles into C code as the
2024 // Java calling convention forces doubles to be aligned.
2025 #ifdef _LP64
2026 const bool Matcher::misaligned_doubles_ok = true;
2027 #else
2028 const bool Matcher::misaligned_doubles_ok = false;
2029 #endif
2030
2031 // No-op on SPARC.
2032 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2033 }
2034
2035 // Advertise here if the CPU requires explicit rounding operations
2036 // to implement the UseStrictFP mode.
2037 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2038
2039 // Are floats converted to double when stored to stack during deoptimization?
2040 // Sparc does not handle callee-save floats.
2041 bool Matcher::float_in_double() { return false; }
2042
2043 // Do ints take an entire long register or just half?
2044 // Note that we if-def off of _LP64.
2045 // The relevant question is how the int is callee-saved. In _LP64
2046 // the whole long is written but de-opt'ing will have to extract
2047 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2048 #ifdef _LP64
2049 const bool Matcher::int_in_long = true;
2050 #else
2051 const bool Matcher::int_in_long = false;
2052 #endif
2053
2054 // Return whether or not this register is ever used as an argument. This
2055 // function is used on startup to build the trampoline stubs in generateOptoStub.
2056 // Registers not mentioned will be killed by the VM call in the trampoline, and
2057 // arguments in those registers not be available to the callee.
2058 bool Matcher::can_be_java_arg( int reg ) {
2059 // Standard sparc 6 args in registers
2060 if( reg == R_I0_num ||
2061 reg == R_I1_num ||
2062 reg == R_I2_num ||
2063 reg == R_I3_num ||
2064 reg == R_I4_num ||
2065 reg == R_I5_num ) return true;
2066 #ifdef _LP64
2067 // 64-bit builds can pass 64-bit pointers and longs in
2068 // the high I registers
2069 if( reg == R_I0H_num ||
2070 reg == R_I1H_num ||
2071 reg == R_I2H_num ||
2072 reg == R_I3H_num ||
2073 reg == R_I4H_num ||
2074 reg == R_I5H_num ) return true;
2075
2076 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2077 return true;
2078 }
2079
2080 #else
2081 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2082 // Longs cannot be passed in O regs, because O regs become I regs
2083 // after a 'save' and I regs get their high bits chopped off on
2084 // interrupt.
2085 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2086 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2087 #endif
2088 // A few float args in registers
2089 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2090
2091 return false;
2092 }
2093
2094 bool Matcher::is_spillable_arg( int reg ) {
2095 return can_be_java_arg(reg);
2096 }
2097
2098 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2099 // Use hardware SDIVX instruction when it is
2100 // faster than a code which use multiply.
2101 return VM_Version::has_fast_idiv();
2102 }
2103
2104 // Register for DIVI projection of divmodI
2105 RegMask Matcher::divI_proj_mask() {
2106 ShouldNotReachHere();
2107 return RegMask();
2108 }
2109
2110 // Register for MODI projection of divmodI
2111 RegMask Matcher::modI_proj_mask() {
2112 ShouldNotReachHere();
2113 return RegMask();
2114 }
2115
2116 // Register for DIVL projection of divmodL
2117 RegMask Matcher::divL_proj_mask() {
2118 ShouldNotReachHere();
2119 return RegMask();
2120 }
2121
2122 // Register for MODL projection of divmodL
2123 RegMask Matcher::modL_proj_mask() {
2124 ShouldNotReachHere();
2125 return RegMask();
2126 }
2127
2128 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2129 return L7_REGP_mask();
2130 }
2131
2132 %}
2133
2134
2135 // The intptr_t operand types, defined by textual substitution.
2136 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2137 #ifdef _LP64
2138 #define immX immL
2139 #define immX13 immL13
2140 #define immX13m7 immL13m7
2141 #define iRegX iRegL
2142 #define g1RegX g1RegL
2143 #else
2144 #define immX immI
2145 #define immX13 immI13
2146 #define immX13m7 immI13m7
2147 #define iRegX iRegI
2148 #define g1RegX g1RegI
2149 #endif
2150
2151 //----------ENCODING BLOCK-----------------------------------------------------
2152 // This block specifies the encoding classes used by the compiler to output
2153 // byte streams. Encoding classes are parameterized macros used by
2154 // Machine Instruction Nodes in order to generate the bit encoding of the
2155 // instruction. Operands specify their base encoding interface with the
2156 // interface keyword. There are currently supported four interfaces,
2157 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2158 // operand to generate a function which returns its register number when
2159 // queried. CONST_INTER causes an operand to generate a function which
2160 // returns the value of the constant when queried. MEMORY_INTER causes an
2161 // operand to generate four functions which return the Base Register, the
2162 // Index Register, the Scale Value, and the Offset Value of the operand when
2163 // queried. COND_INTER causes an operand to generate six functions which
2164 // return the encoding code (ie - encoding bits for the instruction)
2165 // associated with each basic boolean condition for a conditional instruction.
2166 //
2167 // Instructions specify two basic values for encoding. Again, a function
2168 // is available to check if the constant displacement is an oop. They use the
2169 // ins_encode keyword to specify their encoding classes (which must be
2170 // a sequence of enc_class names, and their parameters, specified in
2171 // the encoding block), and they use the
2172 // opcode keyword to specify, in order, their primary, secondary, and
2173 // tertiary opcode. Only the opcode sections which a particular instruction
2174 // needs for encoding need to be specified.
2175 encode %{
2176 enc_class enc_untested %{
2177 #ifdef ASSERT
2178 MacroAssembler _masm(&cbuf);
2179 __ untested("encoding");
2180 #endif
2181 %}
2182
2183 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2184 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2185 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2186 %}
2187
2188 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2189 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2190 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2191 %}
2192
2193 enc_class form3_mem_prefetch_read( memory mem ) %{
2194 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2195 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2196 %}
2197
2198 enc_class form3_mem_prefetch_write( memory mem ) %{
2199 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2200 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2201 %}
2202
2203 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2204 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2205 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2206 guarantee($mem$$index == R_G0_enc, "double index?");
2207 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2208 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2209 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2210 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2211 %}
2212
2213 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2214 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2215 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2216 guarantee($mem$$index == R_G0_enc, "double index?");
2217 // Load long with 2 instructions
2218 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2219 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2220 %}
2221
2222 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2223 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2224 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2225 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2226 %}
2227
2228 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2229 // Encode a reg-reg copy. If it is useless, then empty encoding.
2230 if( $rs2$$reg != $rd$$reg )
2231 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2232 %}
2233
2234 // Target lo half of long
2235 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2236 // Encode a reg-reg copy. If it is useless, then empty encoding.
2237 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2238 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2239 %}
2240
2241 // Source lo half of long
2242 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2243 // Encode a reg-reg copy. If it is useless, then empty encoding.
2244 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2245 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2246 %}
2247
2248 // Target hi half of long
2249 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2250 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2251 %}
2252
2253 // Source lo half of long, and leave it sign extended.
2254 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2255 // Sign extend low half
2256 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2257 %}
2258
2259 // Source hi half of long, and leave it sign extended.
2260 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2261 // Shift high half to low half
2262 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2263 %}
2264
2265 // Source hi half of long
2266 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2267 // Encode a reg-reg copy. If it is useless, then empty encoding.
2268 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2269 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2270 %}
2271
2272 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2273 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2274 %}
2275
2276 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2277 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2278 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2279 %}
2280
2281 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2282 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2283 // clear if nothing else is happening
2284 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2285 // blt,a,pn done
2286 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2287 // mov dst,-1 in delay slot
2288 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2289 %}
2290
2291 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2292 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2293 %}
2294
2295 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2296 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2297 %}
2298
2299 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2300 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2301 %}
2302
2303 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2304 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2305 %}
2306
2307 enc_class move_return_pc_to_o1() %{
2308 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2309 %}
2310
2311 #ifdef _LP64
2312 /* %%% merge with enc_to_bool */
2313 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2314 MacroAssembler _masm(&cbuf);
2315
2316 Register src_reg = reg_to_register_object($src$$reg);
2317 Register dst_reg = reg_to_register_object($dst$$reg);
2318 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2319 %}
2320 #endif
2321
2322 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2323 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2324 MacroAssembler _masm(&cbuf);
2325
2326 Register p_reg = reg_to_register_object($p$$reg);
2327 Register q_reg = reg_to_register_object($q$$reg);
2328 Register y_reg = reg_to_register_object($y$$reg);
2329 Register tmp_reg = reg_to_register_object($tmp$$reg);
2330
2331 __ subcc( p_reg, q_reg, p_reg );
2332 __ add ( p_reg, y_reg, tmp_reg );
2333 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2334 %}
2335
2336 enc_class form_d2i_helper(regD src, regF dst) %{
2337 // fcmp %fcc0,$src,$src
2338 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2339 // branch %fcc0 not-nan, predict taken
2340 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2341 // fdtoi $src,$dst
2342 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2343 // fitos $dst,$dst (if nan)
2344 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2345 // clear $dst (if nan)
2346 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2347 // carry on here...
2348 %}
2349
2350 enc_class form_d2l_helper(regD src, regD dst) %{
2351 // fcmp %fcc0,$src,$src check for NAN
2352 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2353 // branch %fcc0 not-nan, predict taken
2354 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2355 // fdtox $src,$dst convert in delay slot
2356 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2357 // fxtod $dst,$dst (if nan)
2358 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2359 // clear $dst (if nan)
2360 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2361 // carry on here...
2362 %}
2363
2364 enc_class form_f2i_helper(regF src, regF dst) %{
2365 // fcmps %fcc0,$src,$src
2366 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2367 // branch %fcc0 not-nan, predict taken
2368 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2369 // fstoi $src,$dst
2370 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2371 // fitos $dst,$dst (if nan)
2372 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2373 // clear $dst (if nan)
2374 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2375 // carry on here...
2376 %}
2377
2378 enc_class form_f2l_helper(regF src, regD dst) %{
2379 // fcmps %fcc0,$src,$src
2380 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2381 // branch %fcc0 not-nan, predict taken
2382 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2383 // fstox $src,$dst
2384 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2385 // fxtod $dst,$dst (if nan)
2386 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2387 // clear $dst (if nan)
2388 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2389 // carry on here...
2390 %}
2391
2392 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2393 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2394 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2395 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2396
2397 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2398
2399 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2400 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2401
2402 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2403 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2404 %}
2405
2406 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2407 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2408 %}
2409
2410 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2411 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2412 %}
2413
2414 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2415 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2416 %}
2417
2418 enc_class form3_convI2F(regF rs2, regF rd) %{
2419 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2420 %}
2421
2422 // Encloding class for traceable jumps
2423 enc_class form_jmpl(g3RegP dest) %{
2424 emit_jmpl(cbuf, $dest$$reg);
2425 %}
2426
2427 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2428 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2429 %}
2430
2431 enc_class form2_nop() %{
2432 emit_nop(cbuf);
2433 %}
2434
2435 enc_class form2_illtrap() %{
2436 emit_illtrap(cbuf);
2437 %}
2438
2439
2440 // Compare longs and convert into -1, 0, 1.
2441 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2442 // CMP $src1,$src2
2443 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2444 // blt,a,pn done
2445 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2446 // mov dst,-1 in delay slot
2447 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2448 // bgt,a,pn done
2449 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2450 // mov dst,1 in delay slot
2451 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2452 // CLR $dst
2453 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2454 %}
2455
2456 enc_class enc_PartialSubtypeCheck() %{
2457 MacroAssembler _masm(&cbuf);
2458 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2459 __ delayed()->nop();
2460 %}
2461
2462 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2463 MacroAssembler _masm(&cbuf);
2464 Label* L = $labl$$label;
2465 Assembler::Predict predict_taken =
2466 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2467
2468 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2469 __ delayed()->nop();
2470 %}
2471
2472 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2473 MacroAssembler _masm(&cbuf);
2474 Label* L = $labl$$label;
2475 Assembler::Predict predict_taken =
2476 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2477
2478 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2479 __ delayed()->nop();
2480 %}
2481
2482 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2483 int op = (Assembler::arith_op << 30) |
2484 ($dst$$reg << 25) |
2485 (Assembler::movcc_op3 << 19) |
2486 (1 << 18) | // cc2 bit for 'icc'
2487 ($cmp$$cmpcode << 14) |
2488 (0 << 13) | // select register move
2489 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2490 ($src$$reg << 0);
2491 cbuf.insts()->emit_int32(op);
2492 %}
2493
2494 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2495 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2496 int op = (Assembler::arith_op << 30) |
2497 ($dst$$reg << 25) |
2498 (Assembler::movcc_op3 << 19) |
2499 (1 << 18) | // cc2 bit for 'icc'
2500 ($cmp$$cmpcode << 14) |
2501 (1 << 13) | // select immediate move
2502 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2503 (simm11 << 0);
2504 cbuf.insts()->emit_int32(op);
2505 %}
2506
2507 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2508 int op = (Assembler::arith_op << 30) |
2509 ($dst$$reg << 25) |
2510 (Assembler::movcc_op3 << 19) |
2511 (0 << 18) | // cc2 bit for 'fccX'
2512 ($cmp$$cmpcode << 14) |
2513 (0 << 13) | // select register move
2514 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2515 ($src$$reg << 0);
2516 cbuf.insts()->emit_int32(op);
2517 %}
2518
2519 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2520 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2521 int op = (Assembler::arith_op << 30) |
2522 ($dst$$reg << 25) |
2523 (Assembler::movcc_op3 << 19) |
2524 (0 << 18) | // cc2 bit for 'fccX'
2525 ($cmp$$cmpcode << 14) |
2526 (1 << 13) | // select immediate move
2527 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2528 (simm11 << 0);
2529 cbuf.insts()->emit_int32(op);
2530 %}
2531
2532 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2533 int op = (Assembler::arith_op << 30) |
2534 ($dst$$reg << 25) |
2535 (Assembler::fpop2_op3 << 19) |
2536 (0 << 18) |
2537 ($cmp$$cmpcode << 14) |
2538 (1 << 13) | // select register move
2539 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2540 ($primary << 5) | // select single, double or quad
2541 ($src$$reg << 0);
2542 cbuf.insts()->emit_int32(op);
2543 %}
2544
2545 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2546 int op = (Assembler::arith_op << 30) |
2547 ($dst$$reg << 25) |
2548 (Assembler::fpop2_op3 << 19) |
2549 (0 << 18) |
2550 ($cmp$$cmpcode << 14) |
2551 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2552 ($primary << 5) | // select single, double or quad
2553 ($src$$reg << 0);
2554 cbuf.insts()->emit_int32(op);
2555 %}
2556
2557 // Used by the MIN/MAX encodings. Same as a CMOV, but
2558 // the condition comes from opcode-field instead of an argument.
2559 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2560 int op = (Assembler::arith_op << 30) |
2561 ($dst$$reg << 25) |
2562 (Assembler::movcc_op3 << 19) |
2563 (1 << 18) | // cc2 bit for 'icc'
2564 ($primary << 14) |
2565 (0 << 13) | // select register move
2566 (0 << 11) | // cc1, cc0 bits for 'icc'
2567 ($src$$reg << 0);
2568 cbuf.insts()->emit_int32(op);
2569 %}
2570
2571 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2572 int op = (Assembler::arith_op << 30) |
2573 ($dst$$reg << 25) |
2574 (Assembler::movcc_op3 << 19) |
2575 (6 << 16) | // cc2 bit for 'xcc'
2576 ($primary << 14) |
2577 (0 << 13) | // select register move
2578 (0 << 11) | // cc1, cc0 bits for 'icc'
2579 ($src$$reg << 0);
2580 cbuf.insts()->emit_int32(op);
2581 %}
2582
2583 enc_class Set13( immI13 src, iRegI rd ) %{
2584 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2585 %}
2586
2587 enc_class SetHi22( immI src, iRegI rd ) %{
2588 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2589 %}
2590
2591 enc_class Set32( immI src, iRegI rd ) %{
2592 MacroAssembler _masm(&cbuf);
2593 __ set($src$$constant, reg_to_register_object($rd$$reg));
2594 %}
2595
2596 enc_class call_epilog %{
2597 if( VerifyStackAtCalls ) {
2598 MacroAssembler _masm(&cbuf);
2599 int framesize = ra_->C->frame_size_in_bytes();
2600 Register temp_reg = G3;
2601 __ add(SP, framesize, temp_reg);
2602 __ cmp(temp_reg, FP);
2603 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2604 }
2605 %}
2606
2607 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2608 // to G1 so the register allocator will not have to deal with the misaligned register
2609 // pair.
2610 enc_class adjust_long_from_native_call %{
2611 #ifndef _LP64
2612 if (returns_long()) {
2613 // sllx O0,32,O0
2614 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2615 // srl O1,0,O1
2616 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2617 // or O0,O1,G1
2618 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2619 }
2620 #endif
2621 %}
2622
2623 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2624 // CALL directly to the runtime
2625 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2626 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2627 %}
2628
2629 enc_class preserve_SP %{
2630 MacroAssembler _masm(&cbuf);
2631 __ mov(SP, L7_mh_SP_save);
2632 %}
2633
2634 enc_class restore_SP %{
2635 MacroAssembler _masm(&cbuf);
2636 __ mov(L7_mh_SP_save, SP);
2637 %}
2638
2639 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2640 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2641 // who we intended to call.
2642 if (!_method) {
2643 emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2644 } else {
2645 int method_index = resolved_method_index(cbuf);
2646 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2647 : static_call_Relocation::spec(method_index);
2648 emit_call_reloc(cbuf, $meth$$method, rspec);
2649
2650 // Emit stub for static call.
2651 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2652 // Stub does not fit into scratch buffer if TraceJumps is enabled
2653 if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2654 ciEnv::current()->record_failure("CodeCache is full");
2655 return;
2656 }
2657 }
2658 %}
2659
2660 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2661 MacroAssembler _masm(&cbuf);
2662 __ set_inst_mark();
2663 int vtable_index = this->_vtable_index;
2664 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2665 if (vtable_index < 0) {
2666 // must be invalid_vtable_index, not nonvirtual_vtable_index
2667 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2668 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2669 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2670 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2671 __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2672 } else {
2673 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2674 // Just go thru the vtable
2675 // get receiver klass (receiver already checked for non-null)
2676 // If we end up going thru a c2i adapter interpreter expects method in G5
2677 int off = __ offset();
2678 __ load_klass(O0, G3_scratch);
2679 int klass_load_size;
2680 if (UseCompressedClassPointers) {
2681 assert(Universe::heap() != NULL, "java heap should be initialized");
2682 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2683 } else {
2684 klass_load_size = 1*BytesPerInstWord;
2685 }
2686 int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2687 int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2688 if (Assembler::is_simm13(v_off)) {
2689 __ ld_ptr(G3, v_off, G5_method);
2690 } else {
2691 // Generate 2 instructions
2692 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2693 __ or3(G5_method, v_off & 0x3ff, G5_method);
2694 // ld_ptr, set_hi, set
2695 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2696 "Unexpected instruction size(s)");
2697 __ ld_ptr(G3, G5_method, G5_method);
2698 }
2699 // NOTE: for vtable dispatches, the vtable entry will never be null.
2700 // However it may very well end up in handle_wrong_method if the
2701 // method is abstract for the particular class.
2702 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2703 // jump to target (either compiled code or c2iadapter)
2704 __ jmpl(G3_scratch, G0, O7);
2705 __ delayed()->nop();
2706 }
2707 %}
2708
2709 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2710 MacroAssembler _masm(&cbuf);
2711
2712 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2713 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2714 // we might be calling a C2I adapter which needs it.
2715
2716 assert(temp_reg != G5_ic_reg, "conflicting registers");
2717 // Load nmethod
2718 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2719
2720 // CALL to compiled java, indirect the contents of G3
2721 __ set_inst_mark();
2722 __ callr(temp_reg, G0);
2723 __ delayed()->nop();
2724 %}
2725
2726 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2727 MacroAssembler _masm(&cbuf);
2728 Register Rdividend = reg_to_register_object($src1$$reg);
2729 Register Rdivisor = reg_to_register_object($src2$$reg);
2730 Register Rresult = reg_to_register_object($dst$$reg);
2731
2732 __ sra(Rdivisor, 0, Rdivisor);
2733 __ sra(Rdividend, 0, Rdividend);
2734 __ sdivx(Rdividend, Rdivisor, Rresult);
2735 %}
2736
2737 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2738 MacroAssembler _masm(&cbuf);
2739
2740 Register Rdividend = reg_to_register_object($src1$$reg);
2741 int divisor = $imm$$constant;
2742 Register Rresult = reg_to_register_object($dst$$reg);
2743
2744 __ sra(Rdividend, 0, Rdividend);
2745 __ sdivx(Rdividend, divisor, Rresult);
2746 %}
2747
2748 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2749 MacroAssembler _masm(&cbuf);
2750 Register Rsrc1 = reg_to_register_object($src1$$reg);
2751 Register Rsrc2 = reg_to_register_object($src2$$reg);
2752 Register Rdst = reg_to_register_object($dst$$reg);
2753
2754 __ sra( Rsrc1, 0, Rsrc1 );
2755 __ sra( Rsrc2, 0, Rsrc2 );
2756 __ mulx( Rsrc1, Rsrc2, Rdst );
2757 __ srlx( Rdst, 32, Rdst );
2758 %}
2759
2760 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2761 MacroAssembler _masm(&cbuf);
2762 Register Rdividend = reg_to_register_object($src1$$reg);
2763 Register Rdivisor = reg_to_register_object($src2$$reg);
2764 Register Rresult = reg_to_register_object($dst$$reg);
2765 Register Rscratch = reg_to_register_object($scratch$$reg);
2766
2767 assert(Rdividend != Rscratch, "");
2768 assert(Rdivisor != Rscratch, "");
2769
2770 __ sra(Rdividend, 0, Rdividend);
2771 __ sra(Rdivisor, 0, Rdivisor);
2772 __ sdivx(Rdividend, Rdivisor, Rscratch);
2773 __ mulx(Rscratch, Rdivisor, Rscratch);
2774 __ sub(Rdividend, Rscratch, Rresult);
2775 %}
2776
2777 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2778 MacroAssembler _masm(&cbuf);
2779
2780 Register Rdividend = reg_to_register_object($src1$$reg);
2781 int divisor = $imm$$constant;
2782 Register Rresult = reg_to_register_object($dst$$reg);
2783 Register Rscratch = reg_to_register_object($scratch$$reg);
2784
2785 assert(Rdividend != Rscratch, "");
2786
2787 __ sra(Rdividend, 0, Rdividend);
2788 __ sdivx(Rdividend, divisor, Rscratch);
2789 __ mulx(Rscratch, divisor, Rscratch);
2790 __ sub(Rdividend, Rscratch, Rresult);
2791 %}
2792
2793 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2794 MacroAssembler _masm(&cbuf);
2795
2796 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2797 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2798
2799 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2800 %}
2801
2802 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2803 MacroAssembler _masm(&cbuf);
2804
2805 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2806 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2807
2808 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2809 %}
2810
2811 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2812 MacroAssembler _masm(&cbuf);
2813
2814 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2815 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2816
2817 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2818 %}
2819
2820 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2821 MacroAssembler _masm(&cbuf);
2822
2823 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2824 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2825
2826 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2827 %}
2828
2829 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2830 MacroAssembler _masm(&cbuf);
2831
2832 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2833 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2834
2835 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2836 %}
2837
2838 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2839 MacroAssembler _masm(&cbuf);
2840
2841 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2842 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2843
2844 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2845 %}
2846
2847 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2848 MacroAssembler _masm(&cbuf);
2849
2850 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2851 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2852
2853 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2854 %}
2855
2856 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2857 MacroAssembler _masm(&cbuf);
2858
2859 Register Roop = reg_to_register_object($oop$$reg);
2860 Register Rbox = reg_to_register_object($box$$reg);
2861 Register Rscratch = reg_to_register_object($scratch$$reg);
2862 Register Rmark = reg_to_register_object($scratch2$$reg);
2863
2864 assert(Roop != Rscratch, "");
2865 assert(Roop != Rmark, "");
2866 assert(Rbox != Rscratch, "");
2867 assert(Rbox != Rmark, "");
2868
2869 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2870 %}
2871
2872 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2873 MacroAssembler _masm(&cbuf);
2874
2875 Register Roop = reg_to_register_object($oop$$reg);
2876 Register Rbox = reg_to_register_object($box$$reg);
2877 Register Rscratch = reg_to_register_object($scratch$$reg);
2878 Register Rmark = reg_to_register_object($scratch2$$reg);
2879
2880 assert(Roop != Rscratch, "");
2881 assert(Roop != Rmark, "");
2882 assert(Rbox != Rscratch, "");
2883 assert(Rbox != Rmark, "");
2884
2885 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2886 %}
2887
2888 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2889 MacroAssembler _masm(&cbuf);
2890 Register Rmem = reg_to_register_object($mem$$reg);
2891 Register Rold = reg_to_register_object($old$$reg);
2892 Register Rnew = reg_to_register_object($new$$reg);
2893
2894 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2895 __ cmp( Rold, Rnew );
2896 %}
2897
2898 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2899 Register Rmem = reg_to_register_object($mem$$reg);
2900 Register Rold = reg_to_register_object($old$$reg);
2901 Register Rnew = reg_to_register_object($new$$reg);
2902
2903 MacroAssembler _masm(&cbuf);
2904 __ mov(Rnew, O7);
2905 __ casx(Rmem, Rold, O7);
2906 __ cmp( Rold, O7 );
2907 %}
2908
2909 // raw int cas, used for compareAndSwap
2910 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2911 Register Rmem = reg_to_register_object($mem$$reg);
2912 Register Rold = reg_to_register_object($old$$reg);
2913 Register Rnew = reg_to_register_object($new$$reg);
2914
2915 MacroAssembler _masm(&cbuf);
2916 __ mov(Rnew, O7);
2917 __ cas(Rmem, Rold, O7);
2918 __ cmp( Rold, O7 );
2919 %}
2920
2921 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2922 Register Rres = reg_to_register_object($res$$reg);
2923
2924 MacroAssembler _masm(&cbuf);
2925 __ mov(1, Rres);
2926 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2927 %}
2928
2929 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2930 Register Rres = reg_to_register_object($res$$reg);
2931
2932 MacroAssembler _masm(&cbuf);
2933 __ mov(1, Rres);
2934 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2935 %}
2936
2937 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2938 MacroAssembler _masm(&cbuf);
2939 Register Rdst = reg_to_register_object($dst$$reg);
2940 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2941 : reg_to_DoubleFloatRegister_object($src1$$reg);
2942 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2943 : reg_to_DoubleFloatRegister_object($src2$$reg);
2944
2945 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2946 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2947 %}
2948
2949 enc_class enc_rethrow() %{
2950 cbuf.set_insts_mark();
2951 Register temp_reg = G3;
2952 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2953 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2954 MacroAssembler _masm(&cbuf);
2955 #ifdef ASSERT
2956 __ save_frame(0);
2957 AddressLiteral last_rethrow_addrlit(&last_rethrow);
2958 __ sethi(last_rethrow_addrlit, L1);
2959 Address addr(L1, last_rethrow_addrlit.low10());
2960 __ rdpc(L2);
2961 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
2962 __ st_ptr(L2, addr);
2963 __ restore();
2964 #endif
2965 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2966 __ delayed()->nop();
2967 %}
2968
2969 enc_class emit_mem_nop() %{
2970 // Generates the instruction LDUXA [o6,g0],#0x82,g0
2971 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2972 %}
2973
2974 enc_class emit_fadd_nop() %{
2975 // Generates the instruction FMOVS f31,f31
2976 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2977 %}
2978
2979 enc_class emit_br_nop() %{
2980 // Generates the instruction BPN,PN .
2981 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2982 %}
2983
2984 enc_class enc_membar_acquire %{
2985 MacroAssembler _masm(&cbuf);
2986 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
2987 %}
2988
2989 enc_class enc_membar_release %{
2990 MacroAssembler _masm(&cbuf);
2991 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
2992 %}
2993
2994 enc_class enc_membar_volatile %{
2995 MacroAssembler _masm(&cbuf);
2996 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
2997 %}
2998
2999 %}
3000
3001 //----------FRAME--------------------------------------------------------------
3002 // Definition of frame structure and management information.
3003 //
3004 // S T A C K L A Y O U T Allocators stack-slot number
3005 // | (to get allocators register number
3006 // G Owned by | | v add VMRegImpl::stack0)
3007 // r CALLER | |
3008 // o | +--------+ pad to even-align allocators stack-slot
3009 // w V | pad0 | numbers; owned by CALLER
3010 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3011 // h ^ | in | 5
3012 // | | args | 4 Holes in incoming args owned by SELF
3013 // | | | | 3
3014 // | | +--------+
3015 // V | | old out| Empty on Intel, window on Sparc
3016 // | old |preserve| Must be even aligned.
3017 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3018 // | | in | 3 area for Intel ret address
3019 // Owned by |preserve| Empty on Sparc.
3020 // SELF +--------+
3021 // | | pad2 | 2 pad to align old SP
3022 // | +--------+ 1
3023 // | | locks | 0
3024 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3025 // | | pad1 | 11 pad to align new SP
3026 // | +--------+
3027 // | | | 10
3028 // | | spills | 9 spills
3029 // V | | 8 (pad0 slot for callee)
3030 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3031 // ^ | out | 7
3032 // | | args | 6 Holes in outgoing args owned by CALLEE
3033 // Owned by +--------+
3034 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3035 // | new |preserve| Must be even-aligned.
3036 // | SP-+--------+----> Matcher::_new_SP, even aligned
3037 // | | |
3038 //
3039 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3040 // known from SELF's arguments and the Java calling convention.
3041 // Region 6-7 is determined per call site.
3042 // Note 2: If the calling convention leaves holes in the incoming argument
3043 // area, those holes are owned by SELF. Holes in the outgoing area
3044 // are owned by the CALLEE. Holes should not be nessecary in the
3045 // incoming area, as the Java calling convention is completely under
3046 // the control of the AD file. Doubles can be sorted and packed to
3047 // avoid holes. Holes in the outgoing arguments may be necessary for
3048 // varargs C calling conventions.
3049 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3050 // even aligned with pad0 as needed.
3051 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3052 // region 6-11 is even aligned; it may be padded out more so that
3053 // the region from SP to FP meets the minimum stack alignment.
3054
3055 frame %{
3056 // What direction does stack grow in (assumed to be same for native & Java)
3057 stack_direction(TOWARDS_LOW);
3058
3059 // These two registers define part of the calling convention
3060 // between compiled code and the interpreter.
3061 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3062 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3063
3064 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3065 cisc_spilling_operand_name(indOffset);
3066
3067 // Number of stack slots consumed by a Monitor enter
3068 #ifdef _LP64
3069 sync_stack_slots(2);
3070 #else
3071 sync_stack_slots(1);
3072 #endif
3073
3074 // Compiled code's Frame Pointer
3075 frame_pointer(R_SP);
3076
3077 // Stack alignment requirement
3078 stack_alignment(StackAlignmentInBytes);
3079 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3080 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3081
3082 // Number of stack slots between incoming argument block and the start of
3083 // a new frame. The PROLOG must add this many slots to the stack. The
3084 // EPILOG must remove this many slots.
3085 in_preserve_stack_slots(0);
3086
3087 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3088 // for calls to C. Supports the var-args backing area for register parms.
3089 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3090 #ifdef _LP64
3091 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3092 varargs_C_out_slots_killed(12);
3093 #else
3094 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3095 varargs_C_out_slots_killed( 7);
3096 #endif
3097
3098 // The after-PROLOG location of the return address. Location of
3099 // return address specifies a type (REG or STACK) and a number
3100 // representing the register number (i.e. - use a register name) or
3101 // stack slot.
3102 return_addr(REG R_I7); // Ret Addr is in register I7
3103
3104 // Body of function which returns an OptoRegs array locating
3105 // arguments either in registers or in stack slots for calling
3106 // java
3107 calling_convention %{
3108 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3109
3110 %}
3111
3112 // Body of function which returns an OptoRegs array locating
3113 // arguments either in registers or in stack slots for calling
3114 // C.
3115 c_calling_convention %{
3116 // This is obviously always outgoing
3117 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3118 %}
3119
3120 // Location of native (C/C++) and interpreter return values. This is specified to
3121 // be the same as Java. In the 32-bit VM, long values are actually returned from
3122 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3123 // to and from the register pairs is done by the appropriate call and epilog
3124 // opcodes. This simplifies the register allocator.
3125 c_return_value %{
3126 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3127 #ifdef _LP64
3128 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3129 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3130 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3131 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3132 #else // !_LP64
3133 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3134 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3135 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3136 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3137 #endif
3138 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3139 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3140 %}
3141
3142 // Location of compiled Java return values. Same as C
3143 return_value %{
3144 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3145 #ifdef _LP64
3146 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3147 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3148 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3149 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3150 #else // !_LP64
3151 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3152 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3153 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3154 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3155 #endif
3156 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3157 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3158 %}
3159
3160 %}
3161
3162
3163 //----------ATTRIBUTES---------------------------------------------------------
3164 //----------Operand Attributes-------------------------------------------------
3165 op_attrib op_cost(1); // Required cost attribute
3166
3167 //----------Instruction Attributes---------------------------------------------
3168 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3169 ins_attrib ins_size(32); // Required size attribute (in bits)
3170
3171 // avoid_back_to_back attribute is an expression that must return
3172 // one of the following values defined in MachNode:
3173 // AVOID_NONE - instruction can be placed anywhere
3174 // AVOID_BEFORE - instruction cannot be placed after an
3175 // instruction with MachNode::AVOID_AFTER
3176 // AVOID_AFTER - the next instruction cannot be the one
3177 // with MachNode::AVOID_BEFORE
3178 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3179 // the same time
3180 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3181
3182 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3183 // non-matching short branch variant of some
3184 // long branch?
3185
3186 //----------OPERANDS-----------------------------------------------------------
3187 // Operand definitions must precede instruction definitions for correct parsing
3188 // in the ADLC because operands constitute user defined types which are used in
3189 // instruction definitions.
3190
3191 //----------Simple Operands----------------------------------------------------
3192 // Immediate Operands
3193 // Integer Immediate: 32-bit
3194 operand immI() %{
3195 match(ConI);
3196
3197 op_cost(0);
3198 // formats are generated automatically for constants and base registers
3199 format %{ %}
3200 interface(CONST_INTER);
3201 %}
3202
3203 // Integer Immediate: 0-bit
3204 operand immI0() %{
3205 predicate(n->get_int() == 0);
3206 match(ConI);
3207 op_cost(0);
3208
3209 format %{ %}
3210 interface(CONST_INTER);
3211 %}
3212
3213 // Integer Immediate: 5-bit
3214 operand immI5() %{
3215 predicate(Assembler::is_simm5(n->get_int()));
3216 match(ConI);
3217 op_cost(0);
3218 format %{ %}
3219 interface(CONST_INTER);
3220 %}
3221
3222 // Integer Immediate: 8-bit
3223 operand immI8() %{
3224 predicate(Assembler::is_simm8(n->get_int()));
3225 match(ConI);
3226 op_cost(0);
3227 format %{ %}
3228 interface(CONST_INTER);
3229 %}
3230
3231 // Integer Immediate: the value 10
3232 operand immI10() %{
3233 predicate(n->get_int() == 10);
3234 match(ConI);
3235 op_cost(0);
3236
3237 format %{ %}
3238 interface(CONST_INTER);
3239 %}
3240
3241 // Integer Immediate: 11-bit
3242 operand immI11() %{
3243 predicate(Assembler::is_simm11(n->get_int()));
3244 match(ConI);
3245 op_cost(0);
3246 format %{ %}
3247 interface(CONST_INTER);
3248 %}
3249
3250 // Integer Immediate: 13-bit
3251 operand immI13() %{
3252 predicate(Assembler::is_simm13(n->get_int()));
3253 match(ConI);
3254 op_cost(0);
3255
3256 format %{ %}
3257 interface(CONST_INTER);
3258 %}
3259
3260 // Integer Immediate: 13-bit minus 7
3261 operand immI13m7() %{
3262 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3263 match(ConI);
3264 op_cost(0);
3265
3266 format %{ %}
3267 interface(CONST_INTER);
3268 %}
3269
3270 // Integer Immediate: 16-bit
3271 operand immI16() %{
3272 predicate(Assembler::is_simm16(n->get_int()));
3273 match(ConI);
3274 op_cost(0);
3275 format %{ %}
3276 interface(CONST_INTER);
3277 %}
3278
3279 // Integer Immediate: the values 1-31
3280 operand immI_1_31() %{
3281 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3282 match(ConI);
3283 op_cost(0);
3284
3285 format %{ %}
3286 interface(CONST_INTER);
3287 %}
3288
3289 // Integer Immediate: the values 32-63
3290 operand immI_32_63() %{
3291 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3292 match(ConI);
3293 op_cost(0);
3294
3295 format %{ %}
3296 interface(CONST_INTER);
3297 %}
3298
3299 // Immediates for special shifts (sign extend)
3300
3301 // Integer Immediate: the value 16
3302 operand immI_16() %{
3303 predicate(n->get_int() == 16);
3304 match(ConI);
3305 op_cost(0);
3306
3307 format %{ %}
3308 interface(CONST_INTER);
3309 %}
3310
3311 // Integer Immediate: the value 24
3312 operand immI_24() %{
3313 predicate(n->get_int() == 24);
3314 match(ConI);
3315 op_cost(0);
3316
3317 format %{ %}
3318 interface(CONST_INTER);
3319 %}
3320 // Integer Immediate: the value 255
3321 operand immI_255() %{
3322 predicate( n->get_int() == 255 );
3323 match(ConI);
3324 op_cost(0);
3325
3326 format %{ %}
3327 interface(CONST_INTER);
3328 %}
3329
3330 // Integer Immediate: the value 65535
3331 operand immI_65535() %{
3332 predicate(n->get_int() == 65535);
3333 match(ConI);
3334 op_cost(0);
3335
3336 format %{ %}
3337 interface(CONST_INTER);
3338 %}
3339
3340 // Integer Immediate: the values 0-31
3341 operand immU5() %{
3342 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3343 match(ConI);
3344 op_cost(0);
3345
3346 format %{ %}
3347 interface(CONST_INTER);
3348 %}
3349
3350 // Integer Immediate: 6-bit
3351 operand immU6() %{
3352 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3353 match(ConI);
3354 op_cost(0);
3355 format %{ %}
3356 interface(CONST_INTER);
3357 %}
3358
3359 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3360 operand immU12() %{
3361 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3362 match(ConI);
3363 op_cost(0);
3364
3365 format %{ %}
3366 interface(CONST_INTER);
3367 %}
3368
3369 // Integer Immediate non-negative
3370 operand immU31()
3371 %{
3372 predicate(n->get_int() >= 0);
3373 match(ConI);
3374
3375 op_cost(0);
3376 format %{ %}
3377 interface(CONST_INTER);
3378 %}
3379
3380 // Long Immediate: the value FF
3381 operand immL_FF() %{
3382 predicate( n->get_long() == 0xFFL );
3383 match(ConL);
3384 op_cost(0);
3385
3386 format %{ %}
3387 interface(CONST_INTER);
3388 %}
3389
3390 // Long Immediate: the value FFFF
3391 operand immL_FFFF() %{
3392 predicate( n->get_long() == 0xFFFFL );
3393 match(ConL);
3394 op_cost(0);
3395
3396 format %{ %}
3397 interface(CONST_INTER);
3398 %}
3399
3400 // Pointer Immediate: 32 or 64-bit
3401 operand immP() %{
3402 match(ConP);
3403
3404 op_cost(5);
3405 // formats are generated automatically for constants and base registers
3406 format %{ %}
3407 interface(CONST_INTER);
3408 %}
3409
3410 #ifdef _LP64
3411 // Pointer Immediate: 64-bit
3412 operand immP_set() %{
3413 predicate(!VM_Version::is_niagara_plus());
3414 match(ConP);
3415
3416 op_cost(5);
3417 // formats are generated automatically for constants and base registers
3418 format %{ %}
3419 interface(CONST_INTER);
3420 %}
3421
3422 // Pointer Immediate: 64-bit
3423 // From Niagara2 processors on a load should be better than materializing.
3424 operand immP_load() %{
3425 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3426 match(ConP);
3427
3428 op_cost(5);
3429 // formats are generated automatically for constants and base registers
3430 format %{ %}
3431 interface(CONST_INTER);
3432 %}
3433
3434 // Pointer Immediate: 64-bit
3435 operand immP_no_oop_cheap() %{
3436 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3437 match(ConP);
3438
3439 op_cost(5);
3440 // formats are generated automatically for constants and base registers
3441 format %{ %}
3442 interface(CONST_INTER);
3443 %}
3444 #endif
3445
3446 operand immP13() %{
3447 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3448 match(ConP);
3449 op_cost(0);
3450
3451 format %{ %}
3452 interface(CONST_INTER);
3453 %}
3454
3455 operand immP0() %{
3456 predicate(n->get_ptr() == 0);
3457 match(ConP);
3458 op_cost(0);
3459
3460 format %{ %}
3461 interface(CONST_INTER);
3462 %}
3463
3464 operand immP_poll() %{
3465 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3466 match(ConP);
3467
3468 // formats are generated automatically for constants and base registers
3469 format %{ %}
3470 interface(CONST_INTER);
3471 %}
3472
3473 // Pointer Immediate
3474 operand immN()
3475 %{
3476 match(ConN);
3477
3478 op_cost(10);
3479 format %{ %}
3480 interface(CONST_INTER);
3481 %}
3482
3483 operand immNKlass()
3484 %{
3485 match(ConNKlass);
3486
3487 op_cost(10);
3488 format %{ %}
3489 interface(CONST_INTER);
3490 %}
3491
3492 // NULL Pointer Immediate
3493 operand immN0()
3494 %{
3495 predicate(n->get_narrowcon() == 0);
3496 match(ConN);
3497
3498 op_cost(0);
3499 format %{ %}
3500 interface(CONST_INTER);
3501 %}
3502
3503 operand immL() %{
3504 match(ConL);
3505 op_cost(40);
3506 // formats are generated automatically for constants and base registers
3507 format %{ %}
3508 interface(CONST_INTER);
3509 %}
3510
3511 operand immL0() %{
3512 predicate(n->get_long() == 0L);
3513 match(ConL);
3514 op_cost(0);
3515 // formats are generated automatically for constants and base registers
3516 format %{ %}
3517 interface(CONST_INTER);
3518 %}
3519
3520 // Integer Immediate: 5-bit
3521 operand immL5() %{
3522 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3523 match(ConL);
3524 op_cost(0);
3525 format %{ %}
3526 interface(CONST_INTER);
3527 %}
3528
3529 // Long Immediate: 13-bit
3530 operand immL13() %{
3531 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3532 match(ConL);
3533 op_cost(0);
3534
3535 format %{ %}
3536 interface(CONST_INTER);
3537 %}
3538
3539 // Long Immediate: 13-bit minus 7
3540 operand immL13m7() %{
3541 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3542 match(ConL);
3543 op_cost(0);
3544
3545 format %{ %}
3546 interface(CONST_INTER);
3547 %}
3548
3549 // Long Immediate: low 32-bit mask
3550 operand immL_32bits() %{
3551 predicate(n->get_long() == 0xFFFFFFFFL);
3552 match(ConL);
3553 op_cost(0);
3554
3555 format %{ %}
3556 interface(CONST_INTER);
3557 %}
3558
3559 // Long Immediate: cheap (materialize in <= 3 instructions)
3560 operand immL_cheap() %{
3561 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3562 match(ConL);
3563 op_cost(0);
3564
3565 format %{ %}
3566 interface(CONST_INTER);
3567 %}
3568
3569 // Long Immediate: expensive (materialize in > 3 instructions)
3570 operand immL_expensive() %{
3571 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3572 match(ConL);
3573 op_cost(0);
3574
3575 format %{ %}
3576 interface(CONST_INTER);
3577 %}
3578
3579 // Double Immediate
3580 operand immD() %{
3581 match(ConD);
3582
3583 op_cost(40);
3584 format %{ %}
3585 interface(CONST_INTER);
3586 %}
3587
3588 // Double Immediate: +0.0d
3589 operand immD0() %{
3590 predicate(jlong_cast(n->getd()) == 0);
3591 match(ConD);
3592
3593 op_cost(0);
3594 format %{ %}
3595 interface(CONST_INTER);
3596 %}
3597
3598 // Float Immediate
3599 operand immF() %{
3600 match(ConF);
3601
3602 op_cost(20);
3603 format %{ %}
3604 interface(CONST_INTER);
3605 %}
3606
3607 // Float Immediate: +0.0f
3608 operand immF0() %{
3609 predicate(jint_cast(n->getf()) == 0);
3610 match(ConF);
3611
3612 op_cost(0);
3613 format %{ %}
3614 interface(CONST_INTER);
3615 %}
3616
3617 // Integer Register Operands
3618 // Integer Register
3619 operand iRegI() %{
3620 constraint(ALLOC_IN_RC(int_reg));
3621 match(RegI);
3622
3623 match(notemp_iRegI);
3624 match(g1RegI);
3625 match(o0RegI);
3626 match(iRegIsafe);
3627
3628 format %{ %}
3629 interface(REG_INTER);
3630 %}
3631
3632 operand notemp_iRegI() %{
3633 constraint(ALLOC_IN_RC(notemp_int_reg));
3634 match(RegI);
3635
3636 match(o0RegI);
3637
3638 format %{ %}
3639 interface(REG_INTER);
3640 %}
3641
3642 operand o0RegI() %{
3643 constraint(ALLOC_IN_RC(o0_regI));
3644 match(iRegI);
3645
3646 format %{ %}
3647 interface(REG_INTER);
3648 %}
3649
3650 // Pointer Register
3651 operand iRegP() %{
3652 constraint(ALLOC_IN_RC(ptr_reg));
3653 match(RegP);
3654
3655 match(lock_ptr_RegP);
3656 match(g1RegP);
3657 match(g2RegP);
3658 match(g3RegP);
3659 match(g4RegP);
3660 match(i0RegP);
3661 match(o0RegP);
3662 match(o1RegP);
3663 match(l7RegP);
3664
3665 format %{ %}
3666 interface(REG_INTER);
3667 %}
3668
3669 operand sp_ptr_RegP() %{
3670 constraint(ALLOC_IN_RC(sp_ptr_reg));
3671 match(RegP);
3672 match(iRegP);
3673
3674 format %{ %}
3675 interface(REG_INTER);
3676 %}
3677
3678 operand lock_ptr_RegP() %{
3679 constraint(ALLOC_IN_RC(lock_ptr_reg));
3680 match(RegP);
3681 match(i0RegP);
3682 match(o0RegP);
3683 match(o1RegP);
3684 match(l7RegP);
3685
3686 format %{ %}
3687 interface(REG_INTER);
3688 %}
3689
3690 operand g1RegP() %{
3691 constraint(ALLOC_IN_RC(g1_regP));
3692 match(iRegP);
3693
3694 format %{ %}
3695 interface(REG_INTER);
3696 %}
3697
3698 operand g2RegP() %{
3699 constraint(ALLOC_IN_RC(g2_regP));
3700 match(iRegP);
3701
3702 format %{ %}
3703 interface(REG_INTER);
3704 %}
3705
3706 operand g3RegP() %{
3707 constraint(ALLOC_IN_RC(g3_regP));
3708 match(iRegP);
3709
3710 format %{ %}
3711 interface(REG_INTER);
3712 %}
3713
3714 operand g1RegI() %{
3715 constraint(ALLOC_IN_RC(g1_regI));
3716 match(iRegI);
3717
3718 format %{ %}
3719 interface(REG_INTER);
3720 %}
3721
3722 operand g3RegI() %{
3723 constraint(ALLOC_IN_RC(g3_regI));
3724 match(iRegI);
3725
3726 format %{ %}
3727 interface(REG_INTER);
3728 %}
3729
3730 operand g4RegI() %{
3731 constraint(ALLOC_IN_RC(g4_regI));
3732 match(iRegI);
3733
3734 format %{ %}
3735 interface(REG_INTER);
3736 %}
3737
3738 operand g4RegP() %{
3739 constraint(ALLOC_IN_RC(g4_regP));
3740 match(iRegP);
3741
3742 format %{ %}
3743 interface(REG_INTER);
3744 %}
3745
3746 operand i0RegP() %{
3747 constraint(ALLOC_IN_RC(i0_regP));
3748 match(iRegP);
3749
3750 format %{ %}
3751 interface(REG_INTER);
3752 %}
3753
3754 operand o0RegP() %{
3755 constraint(ALLOC_IN_RC(o0_regP));
3756 match(iRegP);
3757
3758 format %{ %}
3759 interface(REG_INTER);
3760 %}
3761
3762 operand o1RegP() %{
3763 constraint(ALLOC_IN_RC(o1_regP));
3764 match(iRegP);
3765
3766 format %{ %}
3767 interface(REG_INTER);
3768 %}
3769
3770 operand o2RegP() %{
3771 constraint(ALLOC_IN_RC(o2_regP));
3772 match(iRegP);
3773
3774 format %{ %}
3775 interface(REG_INTER);
3776 %}
3777
3778 operand o7RegP() %{
3779 constraint(ALLOC_IN_RC(o7_regP));
3780 match(iRegP);
3781
3782 format %{ %}
3783 interface(REG_INTER);
3784 %}
3785
3786 operand l7RegP() %{
3787 constraint(ALLOC_IN_RC(l7_regP));
3788 match(iRegP);
3789
3790 format %{ %}
3791 interface(REG_INTER);
3792 %}
3793
3794 operand o7RegI() %{
3795 constraint(ALLOC_IN_RC(o7_regI));
3796 match(iRegI);
3797
3798 format %{ %}
3799 interface(REG_INTER);
3800 %}
3801
3802 operand iRegN() %{
3803 constraint(ALLOC_IN_RC(int_reg));
3804 match(RegN);
3805
3806 format %{ %}
3807 interface(REG_INTER);
3808 %}
3809
3810 // Long Register
3811 operand iRegL() %{
3812 constraint(ALLOC_IN_RC(long_reg));
3813 match(RegL);
3814
3815 format %{ %}
3816 interface(REG_INTER);
3817 %}
3818
3819 operand o2RegL() %{
3820 constraint(ALLOC_IN_RC(o2_regL));
3821 match(iRegL);
3822
3823 format %{ %}
3824 interface(REG_INTER);
3825 %}
3826
3827 operand o7RegL() %{
3828 constraint(ALLOC_IN_RC(o7_regL));
3829 match(iRegL);
3830
3831 format %{ %}
3832 interface(REG_INTER);
3833 %}
3834
3835 operand g1RegL() %{
3836 constraint(ALLOC_IN_RC(g1_regL));
3837 match(iRegL);
3838
3839 format %{ %}
3840 interface(REG_INTER);
3841 %}
3842
3843 operand g3RegL() %{
3844 constraint(ALLOC_IN_RC(g3_regL));
3845 match(iRegL);
3846
3847 format %{ %}
3848 interface(REG_INTER);
3849 %}
3850
3851 // Int Register safe
3852 // This is 64bit safe
3853 operand iRegIsafe() %{
3854 constraint(ALLOC_IN_RC(long_reg));
3855
3856 match(iRegI);
3857
3858 format %{ %}
3859 interface(REG_INTER);
3860 %}
3861
3862 // Condition Code Flag Register
3863 operand flagsReg() %{
3864 constraint(ALLOC_IN_RC(int_flags));
3865 match(RegFlags);
3866
3867 format %{ "ccr" %} // both ICC and XCC
3868 interface(REG_INTER);
3869 %}
3870
3871 // Condition Code Register, unsigned comparisons.
3872 operand flagsRegU() %{
3873 constraint(ALLOC_IN_RC(int_flags));
3874 match(RegFlags);
3875
3876 format %{ "icc_U" %}
3877 interface(REG_INTER);
3878 %}
3879
3880 // Condition Code Register, pointer comparisons.
3881 operand flagsRegP() %{
3882 constraint(ALLOC_IN_RC(int_flags));
3883 match(RegFlags);
3884
3885 #ifdef _LP64
3886 format %{ "xcc_P" %}
3887 #else
3888 format %{ "icc_P" %}
3889 #endif
3890 interface(REG_INTER);
3891 %}
3892
3893 // Condition Code Register, long comparisons.
3894 operand flagsRegL() %{
3895 constraint(ALLOC_IN_RC(int_flags));
3896 match(RegFlags);
3897
3898 format %{ "xcc_L" %}
3899 interface(REG_INTER);
3900 %}
3901
3902 // Condition Code Register, floating comparisons, unordered same as "less".
3903 operand flagsRegF() %{
3904 constraint(ALLOC_IN_RC(float_flags));
3905 match(RegFlags);
3906 match(flagsRegF0);
3907
3908 format %{ %}
3909 interface(REG_INTER);
3910 %}
3911
3912 operand flagsRegF0() %{
3913 constraint(ALLOC_IN_RC(float_flag0));
3914 match(RegFlags);
3915
3916 format %{ %}
3917 interface(REG_INTER);
3918 %}
3919
3920
3921 // Condition Code Flag Register used by long compare
3922 operand flagsReg_long_LTGE() %{
3923 constraint(ALLOC_IN_RC(int_flags));
3924 match(RegFlags);
3925 format %{ "icc_LTGE" %}
3926 interface(REG_INTER);
3927 %}
3928 operand flagsReg_long_EQNE() %{
3929 constraint(ALLOC_IN_RC(int_flags));
3930 match(RegFlags);
3931 format %{ "icc_EQNE" %}
3932 interface(REG_INTER);
3933 %}
3934 operand flagsReg_long_LEGT() %{
3935 constraint(ALLOC_IN_RC(int_flags));
3936 match(RegFlags);
3937 format %{ "icc_LEGT" %}
3938 interface(REG_INTER);
3939 %}
3940
3941
3942 operand regD() %{
3943 constraint(ALLOC_IN_RC(dflt_reg));
3944 match(RegD);
3945
3946 match(regD_low);
3947
3948 format %{ %}
3949 interface(REG_INTER);
3950 %}
3951
3952 operand regF() %{
3953 constraint(ALLOC_IN_RC(sflt_reg));
3954 match(RegF);
3955
3956 format %{ %}
3957 interface(REG_INTER);
3958 %}
3959
3960 operand regD_low() %{
3961 constraint(ALLOC_IN_RC(dflt_low_reg));
3962 match(regD);
3963
3964 format %{ %}
3965 interface(REG_INTER);
3966 %}
3967
3968 // Special Registers
3969
3970 // Method Register
3971 operand inline_cache_regP(iRegP reg) %{
3972 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3973 match(reg);
3974 format %{ %}
3975 interface(REG_INTER);
3976 %}
3977
3978 operand interpreter_method_oop_regP(iRegP reg) %{
3979 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3980 match(reg);
3981 format %{ %}
3982 interface(REG_INTER);
3983 %}
3984
3985
3986 //----------Complex Operands---------------------------------------------------
3987 // Indirect Memory Reference
3988 operand indirect(sp_ptr_RegP reg) %{
3989 constraint(ALLOC_IN_RC(sp_ptr_reg));
3990 match(reg);
3991
3992 op_cost(100);
3993 format %{ "[$reg]" %}
3994 interface(MEMORY_INTER) %{
3995 base($reg);
3996 index(0x0);
3997 scale(0x0);
3998 disp(0x0);
3999 %}
4000 %}
4001
4002 // Indirect with simm13 Offset
4003 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4004 constraint(ALLOC_IN_RC(sp_ptr_reg));
4005 match(AddP reg offset);
4006
4007 op_cost(100);
4008 format %{ "[$reg + $offset]" %}
4009 interface(MEMORY_INTER) %{
4010 base($reg);
4011 index(0x0);
4012 scale(0x0);
4013 disp($offset);
4014 %}
4015 %}
4016
4017 // Indirect with simm13 Offset minus 7
4018 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4019 constraint(ALLOC_IN_RC(sp_ptr_reg));
4020 match(AddP reg offset);
4021
4022 op_cost(100);
4023 format %{ "[$reg + $offset]" %}
4024 interface(MEMORY_INTER) %{
4025 base($reg);
4026 index(0x0);
4027 scale(0x0);
4028 disp($offset);
4029 %}
4030 %}
4031
4032 // Note: Intel has a swapped version also, like this:
4033 //operand indOffsetX(iRegI reg, immP offset) %{
4034 // constraint(ALLOC_IN_RC(int_reg));
4035 // match(AddP offset reg);
4036 //
4037 // op_cost(100);
4038 // format %{ "[$reg + $offset]" %}
4039 // interface(MEMORY_INTER) %{
4040 // base($reg);
4041 // index(0x0);
4042 // scale(0x0);
4043 // disp($offset);
4044 // %}
4045 //%}
4046 //// However, it doesn't make sense for SPARC, since
4047 // we have no particularly good way to embed oops in
4048 // single instructions.
4049
4050 // Indirect with Register Index
4051 operand indIndex(iRegP addr, iRegX index) %{
4052 constraint(ALLOC_IN_RC(ptr_reg));
4053 match(AddP addr index);
4054
4055 op_cost(100);
4056 format %{ "[$addr + $index]" %}
4057 interface(MEMORY_INTER) %{
4058 base($addr);
4059 index($index);
4060 scale(0x0);
4061 disp(0x0);
4062 %}
4063 %}
4064
4065 //----------Special Memory Operands--------------------------------------------
4066 // Stack Slot Operand - This operand is used for loading and storing temporary
4067 // values on the stack where a match requires a value to
4068 // flow through memory.
4069 operand stackSlotI(sRegI reg) %{
4070 constraint(ALLOC_IN_RC(stack_slots));
4071 op_cost(100);
4072 //match(RegI);
4073 format %{ "[$reg]" %}
4074 interface(MEMORY_INTER) %{
4075 base(0xE); // R_SP
4076 index(0x0);
4077 scale(0x0);
4078 disp($reg); // Stack Offset
4079 %}
4080 %}
4081
4082 operand stackSlotP(sRegP reg) %{
4083 constraint(ALLOC_IN_RC(stack_slots));
4084 op_cost(100);
4085 //match(RegP);
4086 format %{ "[$reg]" %}
4087 interface(MEMORY_INTER) %{
4088 base(0xE); // R_SP
4089 index(0x0);
4090 scale(0x0);
4091 disp($reg); // Stack Offset
4092 %}
4093 %}
4094
4095 operand stackSlotF(sRegF reg) %{
4096 constraint(ALLOC_IN_RC(stack_slots));
4097 op_cost(100);
4098 //match(RegF);
4099 format %{ "[$reg]" %}
4100 interface(MEMORY_INTER) %{
4101 base(0xE); // R_SP
4102 index(0x0);
4103 scale(0x0);
4104 disp($reg); // Stack Offset
4105 %}
4106 %}
4107 operand stackSlotD(sRegD reg) %{
4108 constraint(ALLOC_IN_RC(stack_slots));
4109 op_cost(100);
4110 //match(RegD);
4111 format %{ "[$reg]" %}
4112 interface(MEMORY_INTER) %{
4113 base(0xE); // R_SP
4114 index(0x0);
4115 scale(0x0);
4116 disp($reg); // Stack Offset
4117 %}
4118 %}
4119 operand stackSlotL(sRegL reg) %{
4120 constraint(ALLOC_IN_RC(stack_slots));
4121 op_cost(100);
4122 //match(RegL);
4123 format %{ "[$reg]" %}
4124 interface(MEMORY_INTER) %{
4125 base(0xE); // R_SP
4126 index(0x0);
4127 scale(0x0);
4128 disp($reg); // Stack Offset
4129 %}
4130 %}
4131
4132 // Operands for expressing Control Flow
4133 // NOTE: Label is a predefined operand which should not be redefined in
4134 // the AD file. It is generically handled within the ADLC.
4135
4136 //----------Conditional Branch Operands----------------------------------------
4137 // Comparison Op - This is the operation of the comparison, and is limited to
4138 // the following set of codes:
4139 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4140 //
4141 // Other attributes of the comparison, such as unsignedness, are specified
4142 // by the comparison instruction that sets a condition code flags register.
4143 // That result is represented by a flags operand whose subtype is appropriate
4144 // to the unsignedness (etc.) of the comparison.
4145 //
4146 // Later, the instruction which matches both the Comparison Op (a Bool) and
4147 // the flags (produced by the Cmp) specifies the coding of the comparison op
4148 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4149
4150 operand cmpOp() %{
4151 match(Bool);
4152
4153 format %{ "" %}
4154 interface(COND_INTER) %{
4155 equal(0x1);
4156 not_equal(0x9);
4157 less(0x3);
4158 greater_equal(0xB);
4159 less_equal(0x2);
4160 greater(0xA);
4161 overflow(0x7);
4162 no_overflow(0xF);
4163 %}
4164 %}
4165
4166 // Comparison Op, unsigned
4167 operand cmpOpU() %{
4168 match(Bool);
4169 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4170 n->as_Bool()->_test._test != BoolTest::no_overflow);
4171
4172 format %{ "u" %}
4173 interface(COND_INTER) %{
4174 equal(0x1);
4175 not_equal(0x9);
4176 less(0x5);
4177 greater_equal(0xD);
4178 less_equal(0x4);
4179 greater(0xC);
4180 overflow(0x7);
4181 no_overflow(0xF);
4182 %}
4183 %}
4184
4185 // Comparison Op, pointer (same as unsigned)
4186 operand cmpOpP() %{
4187 match(Bool);
4188 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4189 n->as_Bool()->_test._test != BoolTest::no_overflow);
4190
4191 format %{ "p" %}
4192 interface(COND_INTER) %{
4193 equal(0x1);
4194 not_equal(0x9);
4195 less(0x5);
4196 greater_equal(0xD);
4197 less_equal(0x4);
4198 greater(0xC);
4199 overflow(0x7);
4200 no_overflow(0xF);
4201 %}
4202 %}
4203
4204 // Comparison Op, branch-register encoding
4205 operand cmpOp_reg() %{
4206 match(Bool);
4207 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4208 n->as_Bool()->_test._test != BoolTest::no_overflow);
4209
4210 format %{ "" %}
4211 interface(COND_INTER) %{
4212 equal (0x1);
4213 not_equal (0x5);
4214 less (0x3);
4215 greater_equal(0x7);
4216 less_equal (0x2);
4217 greater (0x6);
4218 overflow(0x7); // not supported
4219 no_overflow(0xF); // not supported
4220 %}
4221 %}
4222
4223 // Comparison Code, floating, unordered same as less
4224 operand cmpOpF() %{
4225 match(Bool);
4226 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4227 n->as_Bool()->_test._test != BoolTest::no_overflow);
4228
4229 format %{ "fl" %}
4230 interface(COND_INTER) %{
4231 equal(0x9);
4232 not_equal(0x1);
4233 less(0x3);
4234 greater_equal(0xB);
4235 less_equal(0xE);
4236 greater(0x6);
4237
4238 overflow(0x7); // not supported
4239 no_overflow(0xF); // not supported
4240 %}
4241 %}
4242
4243 // Used by long compare
4244 operand cmpOp_commute() %{
4245 match(Bool);
4246 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4247 n->as_Bool()->_test._test != BoolTest::no_overflow);
4248
4249 format %{ "" %}
4250 interface(COND_INTER) %{
4251 equal(0x1);
4252 not_equal(0x9);
4253 less(0xA);
4254 greater_equal(0x2);
4255 less_equal(0xB);
4256 greater(0x3);
4257 overflow(0x7);
4258 no_overflow(0xF);
4259 %}
4260 %}
4261
4262 //----------OPERAND CLASSES----------------------------------------------------
4263 // Operand Classes are groups of operands that are used to simplify
4264 // instruction definitions by not requiring the AD writer to specify separate
4265 // instructions for every form of operand when the instruction accepts
4266 // multiple operand types with the same basic encoding and format. The classic
4267 // case of this is memory operands.
4268 opclass memory( indirect, indOffset13, indIndex );
4269 opclass indIndexMemory( indIndex );
4270
4271 //----------PIPELINE-----------------------------------------------------------
4272 pipeline %{
4273
4274 //----------ATTRIBUTES---------------------------------------------------------
4275 attributes %{
4276 fixed_size_instructions; // Fixed size instructions
4277 branch_has_delay_slot; // Branch has delay slot following
4278 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4279 instruction_unit_size = 4; // An instruction is 4 bytes long
4280 instruction_fetch_unit_size = 16; // The processor fetches one line
4281 instruction_fetch_units = 1; // of 16 bytes
4282
4283 // List of nop instructions
4284 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4285 %}
4286
4287 //----------RESOURCES----------------------------------------------------------
4288 // Resources are the functional units available to the machine
4289 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4290
4291 //----------PIPELINE DESCRIPTION-----------------------------------------------
4292 // Pipeline Description specifies the stages in the machine's pipeline
4293
4294 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4295
4296 //----------PIPELINE CLASSES---------------------------------------------------
4297 // Pipeline Classes describe the stages in which input and output are
4298 // referenced by the hardware pipeline.
4299
4300 // Integer ALU reg-reg operation
4301 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4302 single_instruction;
4303 dst : E(write);
4304 src1 : R(read);
4305 src2 : R(read);
4306 IALU : R;
4307 %}
4308
4309 // Integer ALU reg-reg long operation
4310 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4311 instruction_count(2);
4312 dst : E(write);
4313 src1 : R(read);
4314 src2 : R(read);
4315 IALU : R;
4316 IALU : R;
4317 %}
4318
4319 // Integer ALU reg-reg long dependent operation
4320 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4321 instruction_count(1); multiple_bundles;
4322 dst : E(write);
4323 src1 : R(read);
4324 src2 : R(read);
4325 cr : E(write);
4326 IALU : R(2);
4327 %}
4328
4329 // Integer ALU reg-imm operaion
4330 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4331 single_instruction;
4332 dst : E(write);
4333 src1 : R(read);
4334 IALU : R;
4335 %}
4336
4337 // Integer ALU reg-reg operation with condition code
4338 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4339 single_instruction;
4340 dst : E(write);
4341 cr : E(write);
4342 src1 : R(read);
4343 src2 : R(read);
4344 IALU : R;
4345 %}
4346
4347 // Integer ALU reg-imm operation with condition code
4348 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4349 single_instruction;
4350 dst : E(write);
4351 cr : E(write);
4352 src1 : R(read);
4353 IALU : R;
4354 %}
4355
4356 // Integer ALU zero-reg operation
4357 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4358 single_instruction;
4359 dst : E(write);
4360 src2 : R(read);
4361 IALU : R;
4362 %}
4363
4364 // Integer ALU zero-reg operation with condition code only
4365 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4366 single_instruction;
4367 cr : E(write);
4368 src : R(read);
4369 IALU : R;
4370 %}
4371
4372 // Integer ALU reg-reg operation with condition code only
4373 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4374 single_instruction;
4375 cr : E(write);
4376 src1 : R(read);
4377 src2 : R(read);
4378 IALU : R;
4379 %}
4380
4381 // Integer ALU reg-imm operation with condition code only
4382 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4383 single_instruction;
4384 cr : E(write);
4385 src1 : R(read);
4386 IALU : R;
4387 %}
4388
4389 // Integer ALU reg-reg-zero operation with condition code only
4390 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4391 single_instruction;
4392 cr : E(write);
4393 src1 : R(read);
4394 src2 : R(read);
4395 IALU : R;
4396 %}
4397
4398 // Integer ALU reg-imm-zero operation with condition code only
4399 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4400 single_instruction;
4401 cr : E(write);
4402 src1 : R(read);
4403 IALU : R;
4404 %}
4405
4406 // Integer ALU reg-reg operation with condition code, src1 modified
4407 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4408 single_instruction;
4409 cr : E(write);
4410 src1 : E(write);
4411 src1 : R(read);
4412 src2 : R(read);
4413 IALU : R;
4414 %}
4415
4416 // Integer ALU reg-imm operation with condition code, src1 modified
4417 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4418 single_instruction;
4419 cr : E(write);
4420 src1 : E(write);
4421 src1 : R(read);
4422 IALU : R;
4423 %}
4424
4425 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4426 multiple_bundles;
4427 dst : E(write)+4;
4428 cr : E(write);
4429 src1 : R(read);
4430 src2 : R(read);
4431 IALU : R(3);
4432 BR : R(2);
4433 %}
4434
4435 // Integer ALU operation
4436 pipe_class ialu_none(iRegI dst) %{
4437 single_instruction;
4438 dst : E(write);
4439 IALU : R;
4440 %}
4441
4442 // Integer ALU reg operation
4443 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4444 single_instruction; may_have_no_code;
4445 dst : E(write);
4446 src : R(read);
4447 IALU : R;
4448 %}
4449
4450 // Integer ALU reg conditional operation
4451 // This instruction has a 1 cycle stall, and cannot execute
4452 // in the same cycle as the instruction setting the condition
4453 // code. We kludge this by pretending to read the condition code
4454 // 1 cycle earlier, and by marking the functional units as busy
4455 // for 2 cycles with the result available 1 cycle later than
4456 // is really the case.
4457 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4458 single_instruction;
4459 op2_out : C(write);
4460 op1 : R(read);
4461 cr : R(read); // This is really E, with a 1 cycle stall
4462 BR : R(2);
4463 MS : R(2);
4464 %}
4465
4466 #ifdef _LP64
4467 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4468 instruction_count(1); multiple_bundles;
4469 dst : C(write)+1;
4470 src : R(read)+1;
4471 IALU : R(1);
4472 BR : E(2);
4473 MS : E(2);
4474 %}
4475 #endif
4476
4477 // Integer ALU reg operation
4478 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4479 single_instruction; may_have_no_code;
4480 dst : E(write);
4481 src : R(read);
4482 IALU : R;
4483 %}
4484 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4485 single_instruction; may_have_no_code;
4486 dst : E(write);
4487 src : R(read);
4488 IALU : R;
4489 %}
4490
4491 // Two integer ALU reg operations
4492 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4493 instruction_count(2);
4494 dst : E(write);
4495 src : R(read);
4496 A0 : R;
4497 A1 : R;
4498 %}
4499
4500 // Two integer ALU reg operations
4501 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4502 instruction_count(2); may_have_no_code;
4503 dst : E(write);
4504 src : R(read);
4505 A0 : R;
4506 A1 : R;
4507 %}
4508
4509 // Integer ALU imm operation
4510 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4511 single_instruction;
4512 dst : E(write);
4513 IALU : R;
4514 %}
4515
4516 // Integer ALU reg-reg with carry operation
4517 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4518 single_instruction;
4519 dst : E(write);
4520 src1 : R(read);
4521 src2 : R(read);
4522 IALU : R;
4523 %}
4524
4525 // Integer ALU cc operation
4526 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4527 single_instruction;
4528 dst : E(write);
4529 cc : R(read);
4530 IALU : R;
4531 %}
4532
4533 // Integer ALU cc / second IALU operation
4534 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4535 instruction_count(1); multiple_bundles;
4536 dst : E(write)+1;
4537 src : R(read);
4538 IALU : R;
4539 %}
4540
4541 // Integer ALU cc / second IALU operation
4542 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4543 instruction_count(1); multiple_bundles;
4544 dst : E(write)+1;
4545 p : R(read);
4546 q : R(read);
4547 IALU : R;
4548 %}
4549
4550 // Integer ALU hi-lo-reg operation
4551 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4552 instruction_count(1); multiple_bundles;
4553 dst : E(write)+1;
4554 IALU : R(2);
4555 %}
4556
4557 // Float ALU hi-lo-reg operation (with temp)
4558 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4559 instruction_count(1); multiple_bundles;
4560 dst : E(write)+1;
4561 IALU : R(2);
4562 %}
4563
4564 // Long Constant
4565 pipe_class loadConL( iRegL dst, immL src ) %{
4566 instruction_count(2); multiple_bundles;
4567 dst : E(write)+1;
4568 IALU : R(2);
4569 IALU : R(2);
4570 %}
4571
4572 // Pointer Constant
4573 pipe_class loadConP( iRegP dst, immP src ) %{
4574 instruction_count(0); multiple_bundles;
4575 fixed_latency(6);
4576 %}
4577
4578 // Polling Address
4579 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4580 #ifdef _LP64
4581 instruction_count(0); multiple_bundles;
4582 fixed_latency(6);
4583 #else
4584 dst : E(write);
4585 IALU : R;
4586 #endif
4587 %}
4588
4589 // Long Constant small
4590 pipe_class loadConLlo( iRegL dst, immL src ) %{
4591 instruction_count(2);
4592 dst : E(write);
4593 IALU : R;
4594 IALU : R;
4595 %}
4596
4597 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4598 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4599 instruction_count(1); multiple_bundles;
4600 src : R(read);
4601 dst : M(write)+1;
4602 IALU : R;
4603 MS : E;
4604 %}
4605
4606 // Integer ALU nop operation
4607 pipe_class ialu_nop() %{
4608 single_instruction;
4609 IALU : R;
4610 %}
4611
4612 // Integer ALU nop operation
4613 pipe_class ialu_nop_A0() %{
4614 single_instruction;
4615 A0 : R;
4616 %}
4617
4618 // Integer ALU nop operation
4619 pipe_class ialu_nop_A1() %{
4620 single_instruction;
4621 A1 : R;
4622 %}
4623
4624 // Integer Multiply reg-reg operation
4625 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4626 single_instruction;
4627 dst : E(write);
4628 src1 : R(read);
4629 src2 : R(read);
4630 MS : R(5);
4631 %}
4632
4633 // Integer Multiply reg-imm operation
4634 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4635 single_instruction;
4636 dst : E(write);
4637 src1 : R(read);
4638 MS : R(5);
4639 %}
4640
4641 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4642 single_instruction;
4643 dst : E(write)+4;
4644 src1 : R(read);
4645 src2 : R(read);
4646 MS : R(6);
4647 %}
4648
4649 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4650 single_instruction;
4651 dst : E(write)+4;
4652 src1 : R(read);
4653 MS : R(6);
4654 %}
4655
4656 // Integer Divide reg-reg
4657 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4658 instruction_count(1); multiple_bundles;
4659 dst : E(write);
4660 temp : E(write);
4661 src1 : R(read);
4662 src2 : R(read);
4663 temp : R(read);
4664 MS : R(38);
4665 %}
4666
4667 // Integer Divide reg-imm
4668 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4669 instruction_count(1); multiple_bundles;
4670 dst : E(write);
4671 temp : E(write);
4672 src1 : R(read);
4673 temp : R(read);
4674 MS : R(38);
4675 %}
4676
4677 // Long Divide
4678 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4679 dst : E(write)+71;
4680 src1 : R(read);
4681 src2 : R(read)+1;
4682 MS : R(70);
4683 %}
4684
4685 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4686 dst : E(write)+71;
4687 src1 : R(read);
4688 MS : R(70);
4689 %}
4690
4691 // Floating Point Add Float
4692 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4693 single_instruction;
4694 dst : X(write);
4695 src1 : E(read);
4696 src2 : E(read);
4697 FA : R;
4698 %}
4699
4700 // Floating Point Add Double
4701 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4702 single_instruction;
4703 dst : X(write);
4704 src1 : E(read);
4705 src2 : E(read);
4706 FA : R;
4707 %}
4708
4709 // Floating Point Conditional Move based on integer flags
4710 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4711 single_instruction;
4712 dst : X(write);
4713 src : E(read);
4714 cr : R(read);
4715 FA : R(2);
4716 BR : R(2);
4717 %}
4718
4719 // Floating Point Conditional Move based on integer flags
4720 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4721 single_instruction;
4722 dst : X(write);
4723 src : E(read);
4724 cr : R(read);
4725 FA : R(2);
4726 BR : R(2);
4727 %}
4728
4729 // Floating Point Multiply Float
4730 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4731 single_instruction;
4732 dst : X(write);
4733 src1 : E(read);
4734 src2 : E(read);
4735 FM : R;
4736 %}
4737
4738 // Floating Point Multiply Double
4739 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4740 single_instruction;
4741 dst : X(write);
4742 src1 : E(read);
4743 src2 : E(read);
4744 FM : R;
4745 %}
4746
4747 // Floating Point Divide Float
4748 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4749 single_instruction;
4750 dst : X(write);
4751 src1 : E(read);
4752 src2 : E(read);
4753 FM : R;
4754 FDIV : C(14);
4755 %}
4756
4757 // Floating Point Divide Double
4758 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4759 single_instruction;
4760 dst : X(write);
4761 src1 : E(read);
4762 src2 : E(read);
4763 FM : R;
4764 FDIV : C(17);
4765 %}
4766
4767 // Floating Point Move/Negate/Abs Float
4768 pipe_class faddF_reg(regF dst, regF src) %{
4769 single_instruction;
4770 dst : W(write);
4771 src : E(read);
4772 FA : R(1);
4773 %}
4774
4775 // Floating Point Move/Negate/Abs Double
4776 pipe_class faddD_reg(regD dst, regD src) %{
4777 single_instruction;
4778 dst : W(write);
4779 src : E(read);
4780 FA : R;
4781 %}
4782
4783 // Floating Point Convert F->D
4784 pipe_class fcvtF2D(regD dst, regF src) %{
4785 single_instruction;
4786 dst : X(write);
4787 src : E(read);
4788 FA : R;
4789 %}
4790
4791 // Floating Point Convert I->D
4792 pipe_class fcvtI2D(regD dst, regF src) %{
4793 single_instruction;
4794 dst : X(write);
4795 src : E(read);
4796 FA : R;
4797 %}
4798
4799 // Floating Point Convert LHi->D
4800 pipe_class fcvtLHi2D(regD dst, regD src) %{
4801 single_instruction;
4802 dst : X(write);
4803 src : E(read);
4804 FA : R;
4805 %}
4806
4807 // Floating Point Convert L->D
4808 pipe_class fcvtL2D(regD dst, regF src) %{
4809 single_instruction;
4810 dst : X(write);
4811 src : E(read);
4812 FA : R;
4813 %}
4814
4815 // Floating Point Convert L->F
4816 pipe_class fcvtL2F(regD dst, regF src) %{
4817 single_instruction;
4818 dst : X(write);
4819 src : E(read);
4820 FA : R;
4821 %}
4822
4823 // Floating Point Convert D->F
4824 pipe_class fcvtD2F(regD dst, regF src) %{
4825 single_instruction;
4826 dst : X(write);
4827 src : E(read);
4828 FA : R;
4829 %}
4830
4831 // Floating Point Convert I->L
4832 pipe_class fcvtI2L(regD dst, regF src) %{
4833 single_instruction;
4834 dst : X(write);
4835 src : E(read);
4836 FA : R;
4837 %}
4838
4839 // Floating Point Convert D->F
4840 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4841 instruction_count(1); multiple_bundles;
4842 dst : X(write)+6;
4843 src : E(read);
4844 FA : R;
4845 %}
4846
4847 // Floating Point Convert D->L
4848 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4849 instruction_count(1); multiple_bundles;
4850 dst : X(write)+6;
4851 src : E(read);
4852 FA : R;
4853 %}
4854
4855 // Floating Point Convert F->I
4856 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4857 instruction_count(1); multiple_bundles;
4858 dst : X(write)+6;
4859 src : E(read);
4860 FA : R;
4861 %}
4862
4863 // Floating Point Convert F->L
4864 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4865 instruction_count(1); multiple_bundles;
4866 dst : X(write)+6;
4867 src : E(read);
4868 FA : R;
4869 %}
4870
4871 // Floating Point Convert I->F
4872 pipe_class fcvtI2F(regF dst, regF src) %{
4873 single_instruction;
4874 dst : X(write);
4875 src : E(read);
4876 FA : R;
4877 %}
4878
4879 // Floating Point Compare
4880 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4881 single_instruction;
4882 cr : X(write);
4883 src1 : E(read);
4884 src2 : E(read);
4885 FA : R;
4886 %}
4887
4888 // Floating Point Compare
4889 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4890 single_instruction;
4891 cr : X(write);
4892 src1 : E(read);
4893 src2 : E(read);
4894 FA : R;
4895 %}
4896
4897 // Floating Add Nop
4898 pipe_class fadd_nop() %{
4899 single_instruction;
4900 FA : R;
4901 %}
4902
4903 // Integer Store to Memory
4904 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4905 single_instruction;
4906 mem : R(read);
4907 src : C(read);
4908 MS : R;
4909 %}
4910
4911 // Integer Store to Memory
4912 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4913 single_instruction;
4914 mem : R(read);
4915 src : C(read);
4916 MS : R;
4917 %}
4918
4919 // Integer Store Zero to Memory
4920 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4921 single_instruction;
4922 mem : R(read);
4923 MS : R;
4924 %}
4925
4926 // Special Stack Slot Store
4927 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4928 single_instruction;
4929 stkSlot : R(read);
4930 src : C(read);
4931 MS : R;
4932 %}
4933
4934 // Special Stack Slot Store
4935 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4936 instruction_count(2); multiple_bundles;
4937 stkSlot : R(read);
4938 src : C(read);
4939 MS : R(2);
4940 %}
4941
4942 // Float Store
4943 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4944 single_instruction;
4945 mem : R(read);
4946 src : C(read);
4947 MS : R;
4948 %}
4949
4950 // Float Store
4951 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4952 single_instruction;
4953 mem : R(read);
4954 MS : R;
4955 %}
4956
4957 // Double Store
4958 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4959 instruction_count(1);
4960 mem : R(read);
4961 src : C(read);
4962 MS : R;
4963 %}
4964
4965 // Double Store
4966 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4967 single_instruction;
4968 mem : R(read);
4969 MS : R;
4970 %}
4971
4972 // Special Stack Slot Float Store
4973 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4974 single_instruction;
4975 stkSlot : R(read);
4976 src : C(read);
4977 MS : R;
4978 %}
4979
4980 // Special Stack Slot Double Store
4981 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4982 single_instruction;
4983 stkSlot : R(read);
4984 src : C(read);
4985 MS : R;
4986 %}
4987
4988 // Integer Load (when sign bit propagation not needed)
4989 pipe_class iload_mem(iRegI dst, memory mem) %{
4990 single_instruction;
4991 mem : R(read);
4992 dst : C(write);
4993 MS : R;
4994 %}
4995
4996 // Integer Load from stack operand
4997 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
4998 single_instruction;
4999 mem : R(read);
5000 dst : C(write);
5001 MS : R;
5002 %}
5003
5004 // Integer Load (when sign bit propagation or masking is needed)
5005 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5006 single_instruction;
5007 mem : R(read);
5008 dst : M(write);
5009 MS : R;
5010 %}
5011
5012 // Float Load
5013 pipe_class floadF_mem(regF dst, memory mem) %{
5014 single_instruction;
5015 mem : R(read);
5016 dst : M(write);
5017 MS : R;
5018 %}
5019
5020 // Float Load
5021 pipe_class floadD_mem(regD dst, memory mem) %{
5022 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5023 mem : R(read);
5024 dst : M(write);
5025 MS : R;
5026 %}
5027
5028 // Float Load
5029 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5030 single_instruction;
5031 stkSlot : R(read);
5032 dst : M(write);
5033 MS : R;
5034 %}
5035
5036 // Float Load
5037 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5038 single_instruction;
5039 stkSlot : R(read);
5040 dst : M(write);
5041 MS : R;
5042 %}
5043
5044 // Memory Nop
5045 pipe_class mem_nop() %{
5046 single_instruction;
5047 MS : R;
5048 %}
5049
5050 pipe_class sethi(iRegP dst, immI src) %{
5051 single_instruction;
5052 dst : E(write);
5053 IALU : R;
5054 %}
5055
5056 pipe_class loadPollP(iRegP poll) %{
5057 single_instruction;
5058 poll : R(read);
5059 MS : R;
5060 %}
5061
5062 pipe_class br(Universe br, label labl) %{
5063 single_instruction_with_delay_slot;
5064 BR : R;
5065 %}
5066
5067 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5068 single_instruction_with_delay_slot;
5069 cr : E(read);
5070 BR : R;
5071 %}
5072
5073 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5074 single_instruction_with_delay_slot;
5075 op1 : E(read);
5076 BR : R;
5077 MS : R;
5078 %}
5079
5080 // Compare and branch
5081 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5082 instruction_count(2); has_delay_slot;
5083 cr : E(write);
5084 src1 : R(read);
5085 src2 : R(read);
5086 IALU : R;
5087 BR : R;
5088 %}
5089
5090 // Compare and branch
5091 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5092 instruction_count(2); has_delay_slot;
5093 cr : E(write);
5094 src1 : R(read);
5095 IALU : R;
5096 BR : R;
5097 %}
5098
5099 // Compare and branch using cbcond
5100 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5101 single_instruction;
5102 src1 : E(read);
5103 src2 : E(read);
5104 IALU : R;
5105 BR : R;
5106 %}
5107
5108 // Compare and branch using cbcond
5109 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5110 single_instruction;
5111 src1 : E(read);
5112 IALU : R;
5113 BR : R;
5114 %}
5115
5116 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5117 single_instruction_with_delay_slot;
5118 cr : E(read);
5119 BR : R;
5120 %}
5121
5122 pipe_class br_nop() %{
5123 single_instruction;
5124 BR : R;
5125 %}
5126
5127 pipe_class simple_call(method meth) %{
5128 instruction_count(2); multiple_bundles; force_serialization;
5129 fixed_latency(100);
5130 BR : R(1);
5131 MS : R(1);
5132 A0 : R(1);
5133 %}
5134
5135 pipe_class compiled_call(method meth) %{
5136 instruction_count(1); multiple_bundles; force_serialization;
5137 fixed_latency(100);
5138 MS : R(1);
5139 %}
5140
5141 pipe_class call(method meth) %{
5142 instruction_count(0); multiple_bundles; force_serialization;
5143 fixed_latency(100);
5144 %}
5145
5146 pipe_class tail_call(Universe ignore, label labl) %{
5147 single_instruction; has_delay_slot;
5148 fixed_latency(100);
5149 BR : R(1);
5150 MS : R(1);
5151 %}
5152
5153 pipe_class ret(Universe ignore) %{
5154 single_instruction; has_delay_slot;
5155 BR : R(1);
5156 MS : R(1);
5157 %}
5158
5159 pipe_class ret_poll(g3RegP poll) %{
5160 instruction_count(3); has_delay_slot;
5161 poll : E(read);
5162 MS : R;
5163 %}
5164
5165 // The real do-nothing guy
5166 pipe_class empty( ) %{
5167 instruction_count(0);
5168 %}
5169
5170 pipe_class long_memory_op() %{
5171 instruction_count(0); multiple_bundles; force_serialization;
5172 fixed_latency(25);
5173 MS : R(1);
5174 %}
5175
5176 // Check-cast
5177 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5178 array : R(read);
5179 match : R(read);
5180 IALU : R(2);
5181 BR : R(2);
5182 MS : R;
5183 %}
5184
5185 // Convert FPU flags into +1,0,-1
5186 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5187 src1 : E(read);
5188 src2 : E(read);
5189 dst : E(write);
5190 FA : R;
5191 MS : R(2);
5192 BR : R(2);
5193 %}
5194
5195 // Compare for p < q, and conditionally add y
5196 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5197 p : E(read);
5198 q : E(read);
5199 y : E(read);
5200 IALU : R(3)
5201 %}
5202
5203 // Perform a compare, then move conditionally in a branch delay slot.
5204 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5205 src2 : E(read);
5206 srcdst : E(read);
5207 IALU : R;
5208 BR : R;
5209 %}
5210
5211 // Define the class for the Nop node
5212 define %{
5213 MachNop = ialu_nop;
5214 %}
5215
5216 %}
5217
5218 //----------INSTRUCTIONS-------------------------------------------------------
5219
5220 //------------Special Stack Slot instructions - no match rules-----------------
5221 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5222 // No match rule to avoid chain rule match.
5223 effect(DEF dst, USE src);
5224 ins_cost(MEMORY_REF_COST);
5225 format %{ "LDF $src,$dst\t! stkI to regF" %}
5226 opcode(Assembler::ldf_op3);
5227 ins_encode(simple_form3_mem_reg(src, dst));
5228 ins_pipe(floadF_stk);
5229 %}
5230
5231 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5232 // No match rule to avoid chain rule match.
5233 effect(DEF dst, USE src);
5234 ins_cost(MEMORY_REF_COST);
5235 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5236 opcode(Assembler::lddf_op3);
5237 ins_encode(simple_form3_mem_reg(src, dst));
5238 ins_pipe(floadD_stk);
5239 %}
5240
5241 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5242 // No match rule to avoid chain rule match.
5243 effect(DEF dst, USE src);
5244 ins_cost(MEMORY_REF_COST);
5245 format %{ "STF $src,$dst\t! regF to stkI" %}
5246 opcode(Assembler::stf_op3);
5247 ins_encode(simple_form3_mem_reg(dst, src));
5248 ins_pipe(fstoreF_stk_reg);
5249 %}
5250
5251 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5252 // No match rule to avoid chain rule match.
5253 effect(DEF dst, USE src);
5254 ins_cost(MEMORY_REF_COST);
5255 format %{ "STDF $src,$dst\t! regD to stkL" %}
5256 opcode(Assembler::stdf_op3);
5257 ins_encode(simple_form3_mem_reg(dst, src));
5258 ins_pipe(fstoreD_stk_reg);
5259 %}
5260
5261 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5262 effect(DEF dst, USE src);
5263 ins_cost(MEMORY_REF_COST*2);
5264 format %{ "STW $src,$dst.hi\t! long\n\t"
5265 "STW R_G0,$dst.lo" %}
5266 opcode(Assembler::stw_op3);
5267 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5268 ins_pipe(lstoreI_stk_reg);
5269 %}
5270
5271 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5272 // No match rule to avoid chain rule match.
5273 effect(DEF dst, USE src);
5274 ins_cost(MEMORY_REF_COST);
5275 format %{ "STX $src,$dst\t! regL to stkD" %}
5276 opcode(Assembler::stx_op3);
5277 ins_encode(simple_form3_mem_reg( dst, src ) );
5278 ins_pipe(istore_stk_reg);
5279 %}
5280
5281 //---------- Chain stack slots between similar types --------
5282
5283 // Load integer from stack slot
5284 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5285 match(Set dst src);
5286 ins_cost(MEMORY_REF_COST);
5287
5288 format %{ "LDUW $src,$dst\t!stk" %}
5289 opcode(Assembler::lduw_op3);
5290 ins_encode(simple_form3_mem_reg( src, dst ) );
5291 ins_pipe(iload_mem);
5292 %}
5293
5294 // Store integer to stack slot
5295 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5296 match(Set dst src);
5297 ins_cost(MEMORY_REF_COST);
5298
5299 format %{ "STW $src,$dst\t!stk" %}
5300 opcode(Assembler::stw_op3);
5301 ins_encode(simple_form3_mem_reg( dst, src ) );
5302 ins_pipe(istore_mem_reg);
5303 %}
5304
5305 // Load long from stack slot
5306 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5307 match(Set dst src);
5308
5309 ins_cost(MEMORY_REF_COST);
5310 format %{ "LDX $src,$dst\t! long" %}
5311 opcode(Assembler::ldx_op3);
5312 ins_encode(simple_form3_mem_reg( src, dst ) );
5313 ins_pipe(iload_mem);
5314 %}
5315
5316 // Store long to stack slot
5317 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5318 match(Set dst src);
5319
5320 ins_cost(MEMORY_REF_COST);
5321 format %{ "STX $src,$dst\t! long" %}
5322 opcode(Assembler::stx_op3);
5323 ins_encode(simple_form3_mem_reg( dst, src ) );
5324 ins_pipe(istore_mem_reg);
5325 %}
5326
5327 #ifdef _LP64
5328 // Load pointer from stack slot, 64-bit encoding
5329 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5330 match(Set dst src);
5331 ins_cost(MEMORY_REF_COST);
5332 format %{ "LDX $src,$dst\t!ptr" %}
5333 opcode(Assembler::ldx_op3);
5334 ins_encode(simple_form3_mem_reg( src, dst ) );
5335 ins_pipe(iload_mem);
5336 %}
5337
5338 // Store pointer to stack slot
5339 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5340 match(Set dst src);
5341 ins_cost(MEMORY_REF_COST);
5342 format %{ "STX $src,$dst\t!ptr" %}
5343 opcode(Assembler::stx_op3);
5344 ins_encode(simple_form3_mem_reg( dst, src ) );
5345 ins_pipe(istore_mem_reg);
5346 %}
5347 #else // _LP64
5348 // Load pointer from stack slot, 32-bit encoding
5349 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5350 match(Set dst src);
5351 ins_cost(MEMORY_REF_COST);
5352 format %{ "LDUW $src,$dst\t!ptr" %}
5353 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5354 ins_encode(simple_form3_mem_reg( src, dst ) );
5355 ins_pipe(iload_mem);
5356 %}
5357
5358 // Store pointer to stack slot
5359 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5360 match(Set dst src);
5361 ins_cost(MEMORY_REF_COST);
5362 format %{ "STW $src,$dst\t!ptr" %}
5363 opcode(Assembler::stw_op3, Assembler::ldst_op);
5364 ins_encode(simple_form3_mem_reg( dst, src ) );
5365 ins_pipe(istore_mem_reg);
5366 %}
5367 #endif // _LP64
5368
5369 //------------Special Nop instructions for bundling - no match rules-----------
5370 // Nop using the A0 functional unit
5371 instruct Nop_A0() %{
5372 ins_cost(0);
5373
5374 format %{ "NOP ! Alu Pipeline" %}
5375 opcode(Assembler::or_op3, Assembler::arith_op);
5376 ins_encode( form2_nop() );
5377 ins_pipe(ialu_nop_A0);
5378 %}
5379
5380 // Nop using the A1 functional unit
5381 instruct Nop_A1( ) %{
5382 ins_cost(0);
5383
5384 format %{ "NOP ! Alu Pipeline" %}
5385 opcode(Assembler::or_op3, Assembler::arith_op);
5386 ins_encode( form2_nop() );
5387 ins_pipe(ialu_nop_A1);
5388 %}
5389
5390 // Nop using the memory functional unit
5391 instruct Nop_MS( ) %{
5392 ins_cost(0);
5393
5394 format %{ "NOP ! Memory Pipeline" %}
5395 ins_encode( emit_mem_nop );
5396 ins_pipe(mem_nop);
5397 %}
5398
5399 // Nop using the floating add functional unit
5400 instruct Nop_FA( ) %{
5401 ins_cost(0);
5402
5403 format %{ "NOP ! Floating Add Pipeline" %}
5404 ins_encode( emit_fadd_nop );
5405 ins_pipe(fadd_nop);
5406 %}
5407
5408 // Nop using the branch functional unit
5409 instruct Nop_BR( ) %{
5410 ins_cost(0);
5411
5412 format %{ "NOP ! Branch Pipeline" %}
5413 ins_encode( emit_br_nop );
5414 ins_pipe(br_nop);
5415 %}
5416
5417 //----------Load/Store/Move Instructions---------------------------------------
5418 //----------Load Instructions--------------------------------------------------
5419 // Load Byte (8bit signed)
5420 instruct loadB(iRegI dst, memory mem) %{
5421 match(Set dst (LoadB mem));
5422 ins_cost(MEMORY_REF_COST);
5423
5424 size(4);
5425 format %{ "LDSB $mem,$dst\t! byte" %}
5426 ins_encode %{
5427 __ ldsb($mem$$Address, $dst$$Register);
5428 %}
5429 ins_pipe(iload_mask_mem);
5430 %}
5431
5432 // Load Byte (8bit signed) into a Long Register
5433 instruct loadB2L(iRegL dst, memory mem) %{
5434 match(Set dst (ConvI2L (LoadB mem)));
5435 ins_cost(MEMORY_REF_COST);
5436
5437 size(4);
5438 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5439 ins_encode %{
5440 __ ldsb($mem$$Address, $dst$$Register);
5441 %}
5442 ins_pipe(iload_mask_mem);
5443 %}
5444
5445 // Load Unsigned Byte (8bit UNsigned) into an int reg
5446 instruct loadUB(iRegI dst, memory mem) %{
5447 match(Set dst (LoadUB mem));
5448 ins_cost(MEMORY_REF_COST);
5449
5450 size(4);
5451 format %{ "LDUB $mem,$dst\t! ubyte" %}
5452 ins_encode %{
5453 __ ldub($mem$$Address, $dst$$Register);
5454 %}
5455 ins_pipe(iload_mem);
5456 %}
5457
5458 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5459 instruct loadUB2L(iRegL dst, memory mem) %{
5460 match(Set dst (ConvI2L (LoadUB mem)));
5461 ins_cost(MEMORY_REF_COST);
5462
5463 size(4);
5464 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5465 ins_encode %{
5466 __ ldub($mem$$Address, $dst$$Register);
5467 %}
5468 ins_pipe(iload_mem);
5469 %}
5470
5471 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5472 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5473 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5474 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5475
5476 size(2*4);
5477 format %{ "LDUB $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5478 "AND $dst,right_n_bits($mask, 8),$dst" %}
5479 ins_encode %{
5480 __ ldub($mem$$Address, $dst$$Register);
5481 __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5482 %}
5483 ins_pipe(iload_mem);
5484 %}
5485
5486 // Load Short (16bit signed)
5487 instruct loadS(iRegI dst, memory mem) %{
5488 match(Set dst (LoadS mem));
5489 ins_cost(MEMORY_REF_COST);
5490
5491 size(4);
5492 format %{ "LDSH $mem,$dst\t! short" %}
5493 ins_encode %{
5494 __ ldsh($mem$$Address, $dst$$Register);
5495 %}
5496 ins_pipe(iload_mask_mem);
5497 %}
5498
5499 // Load Short (16 bit signed) to Byte (8 bit signed)
5500 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5501 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5502 ins_cost(MEMORY_REF_COST);
5503
5504 size(4);
5505
5506 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5507 ins_encode %{
5508 __ ldsb($mem$$Address, $dst$$Register, 1);
5509 %}
5510 ins_pipe(iload_mask_mem);
5511 %}
5512
5513 // Load Short (16bit signed) into a Long Register
5514 instruct loadS2L(iRegL dst, memory mem) %{
5515 match(Set dst (ConvI2L (LoadS mem)));
5516 ins_cost(MEMORY_REF_COST);
5517
5518 size(4);
5519 format %{ "LDSH $mem,$dst\t! short -> long" %}
5520 ins_encode %{
5521 __ ldsh($mem$$Address, $dst$$Register);
5522 %}
5523 ins_pipe(iload_mask_mem);
5524 %}
5525
5526 // Load Unsigned Short/Char (16bit UNsigned)
5527 instruct loadUS(iRegI dst, memory mem) %{
5528 match(Set dst (LoadUS mem));
5529 ins_cost(MEMORY_REF_COST);
5530
5531 size(4);
5532 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5533 ins_encode %{
5534 __ lduh($mem$$Address, $dst$$Register);
5535 %}
5536 ins_pipe(iload_mem);
5537 %}
5538
5539 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5540 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5541 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5542 ins_cost(MEMORY_REF_COST);
5543
5544 size(4);
5545 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5546 ins_encode %{
5547 __ ldsb($mem$$Address, $dst$$Register, 1);
5548 %}
5549 ins_pipe(iload_mask_mem);
5550 %}
5551
5552 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5553 instruct loadUS2L(iRegL dst, memory mem) %{
5554 match(Set dst (ConvI2L (LoadUS mem)));
5555 ins_cost(MEMORY_REF_COST);
5556
5557 size(4);
5558 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5559 ins_encode %{
5560 __ lduh($mem$$Address, $dst$$Register);
5561 %}
5562 ins_pipe(iload_mem);
5563 %}
5564
5565 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5566 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5567 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5568 ins_cost(MEMORY_REF_COST);
5569
5570 size(4);
5571 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5572 ins_encode %{
5573 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5574 %}
5575 ins_pipe(iload_mem);
5576 %}
5577
5578 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5579 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5580 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5581 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5582
5583 size(2*4);
5584 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5585 "AND $dst,$mask,$dst" %}
5586 ins_encode %{
5587 Register Rdst = $dst$$Register;
5588 __ lduh($mem$$Address, Rdst);
5589 __ and3(Rdst, $mask$$constant, Rdst);
5590 %}
5591 ins_pipe(iload_mem);
5592 %}
5593
5594 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5595 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5596 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5597 effect(TEMP dst, TEMP tmp);
5598 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5599
5600 format %{ "LDUH $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5601 "SET right_n_bits($mask, 16),$tmp\n\t"
5602 "AND $dst,$tmp,$dst" %}
5603 ins_encode %{
5604 Register Rdst = $dst$$Register;
5605 Register Rtmp = $tmp$$Register;
5606 __ lduh($mem$$Address, Rdst);
5607 __ set($mask$$constant & right_n_bits(16), Rtmp);
5608 __ and3(Rdst, Rtmp, Rdst);
5609 %}
5610 ins_pipe(iload_mem);
5611 %}
5612
5613 // Load Integer
5614 instruct loadI(iRegI dst, memory mem) %{
5615 match(Set dst (LoadI mem));
5616 ins_cost(MEMORY_REF_COST);
5617
5618 size(4);
5619 format %{ "LDUW $mem,$dst\t! int" %}
5620 ins_encode %{
5621 __ lduw($mem$$Address, $dst$$Register);
5622 %}
5623 ins_pipe(iload_mem);
5624 %}
5625
5626 // Load Integer to Byte (8 bit signed)
5627 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5628 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5629 ins_cost(MEMORY_REF_COST);
5630
5631 size(4);
5632
5633 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5634 ins_encode %{
5635 __ ldsb($mem$$Address, $dst$$Register, 3);
5636 %}
5637 ins_pipe(iload_mask_mem);
5638 %}
5639
5640 // Load Integer to Unsigned Byte (8 bit UNsigned)
5641 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5642 match(Set dst (AndI (LoadI mem) mask));
5643 ins_cost(MEMORY_REF_COST);
5644
5645 size(4);
5646
5647 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5648 ins_encode %{
5649 __ ldub($mem$$Address, $dst$$Register, 3);
5650 %}
5651 ins_pipe(iload_mask_mem);
5652 %}
5653
5654 // Load Integer to Short (16 bit signed)
5655 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5656 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5657 ins_cost(MEMORY_REF_COST);
5658
5659 size(4);
5660
5661 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5662 ins_encode %{
5663 __ ldsh($mem$$Address, $dst$$Register, 2);
5664 %}
5665 ins_pipe(iload_mask_mem);
5666 %}
5667
5668 // Load Integer to Unsigned Short (16 bit UNsigned)
5669 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5670 match(Set dst (AndI (LoadI mem) mask));
5671 ins_cost(MEMORY_REF_COST);
5672
5673 size(4);
5674
5675 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5676 ins_encode %{
5677 __ lduh($mem$$Address, $dst$$Register, 2);
5678 %}
5679 ins_pipe(iload_mask_mem);
5680 %}
5681
5682 // Load Integer into a Long Register
5683 instruct loadI2L(iRegL dst, memory mem) %{
5684 match(Set dst (ConvI2L (LoadI mem)));
5685 ins_cost(MEMORY_REF_COST);
5686
5687 size(4);
5688 format %{ "LDSW $mem,$dst\t! int -> long" %}
5689 ins_encode %{
5690 __ ldsw($mem$$Address, $dst$$Register);
5691 %}
5692 ins_pipe(iload_mask_mem);
5693 %}
5694
5695 // Load Integer with mask 0xFF into a Long Register
5696 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5697 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5698 ins_cost(MEMORY_REF_COST);
5699
5700 size(4);
5701 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5702 ins_encode %{
5703 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5704 %}
5705 ins_pipe(iload_mem);
5706 %}
5707
5708 // Load Integer with mask 0xFFFF into a Long Register
5709 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5710 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5711 ins_cost(MEMORY_REF_COST);
5712
5713 size(4);
5714 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5715 ins_encode %{
5716 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5717 %}
5718 ins_pipe(iload_mem);
5719 %}
5720
5721 // Load Integer with a 12-bit mask into a Long Register
5722 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5723 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5724 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5725
5726 size(2*4);
5727 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5728 "AND $dst,$mask,$dst" %}
5729 ins_encode %{
5730 Register Rdst = $dst$$Register;
5731 __ lduw($mem$$Address, Rdst);
5732 __ and3(Rdst, $mask$$constant, Rdst);
5733 %}
5734 ins_pipe(iload_mem);
5735 %}
5736
5737 // Load Integer with a 31-bit mask into a Long Register
5738 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5739 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5740 effect(TEMP dst, TEMP tmp);
5741 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5742
5743 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5744 "SET $mask,$tmp\n\t"
5745 "AND $dst,$tmp,$dst" %}
5746 ins_encode %{
5747 Register Rdst = $dst$$Register;
5748 Register Rtmp = $tmp$$Register;
5749 __ lduw($mem$$Address, Rdst);
5750 __ set($mask$$constant, Rtmp);
5751 __ and3(Rdst, Rtmp, Rdst);
5752 %}
5753 ins_pipe(iload_mem);
5754 %}
5755
5756 // Load Unsigned Integer into a Long Register
5757 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5758 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5759 ins_cost(MEMORY_REF_COST);
5760
5761 size(4);
5762 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5763 ins_encode %{
5764 __ lduw($mem$$Address, $dst$$Register);
5765 %}
5766 ins_pipe(iload_mem);
5767 %}
5768
5769 // Load Long - aligned
5770 instruct loadL(iRegL dst, memory mem ) %{
5771 match(Set dst (LoadL mem));
5772 ins_cost(MEMORY_REF_COST);
5773
5774 size(4);
5775 format %{ "LDX $mem,$dst\t! long" %}
5776 ins_encode %{
5777 __ ldx($mem$$Address, $dst$$Register);
5778 %}
5779 ins_pipe(iload_mem);
5780 %}
5781
5782 // Load Long - UNaligned
5783 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5784 match(Set dst (LoadL_unaligned mem));
5785 effect(KILL tmp);
5786 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5787 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5788 "\tLDUW $mem ,$dst\n"
5789 "\tSLLX #32, $dst, $dst\n"
5790 "\tOR $dst, R_O7, $dst" %}
5791 opcode(Assembler::lduw_op3);
5792 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5793 ins_pipe(iload_mem);
5794 %}
5795
5796 // Load Range
5797 instruct loadRange(iRegI dst, memory mem) %{
5798 match(Set dst (LoadRange mem));
5799 ins_cost(MEMORY_REF_COST);
5800
5801 format %{ "LDUW $mem,$dst\t! range" %}
5802 opcode(Assembler::lduw_op3);
5803 ins_encode(simple_form3_mem_reg( mem, dst ) );
5804 ins_pipe(iload_mem);
5805 %}
5806
5807 // Load Integer into %f register (for fitos/fitod)
5808 instruct loadI_freg(regF dst, memory mem) %{
5809 match(Set dst (LoadI mem));
5810 ins_cost(MEMORY_REF_COST);
5811
5812 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
5813 opcode(Assembler::ldf_op3);
5814 ins_encode(simple_form3_mem_reg( mem, dst ) );
5815 ins_pipe(floadF_mem);
5816 %}
5817
5818 // Load Pointer
5819 instruct loadP(iRegP dst, memory mem) %{
5820 match(Set dst (LoadP mem));
5821 ins_cost(MEMORY_REF_COST);
5822 size(4);
5823
5824 #ifndef _LP64
5825 format %{ "LDUW $mem,$dst\t! ptr" %}
5826 ins_encode %{
5827 __ lduw($mem$$Address, $dst$$Register);
5828 %}
5829 #else
5830 format %{ "LDX $mem,$dst\t! ptr" %}
5831 ins_encode %{
5832 __ ldx($mem$$Address, $dst$$Register);
5833 %}
5834 #endif
5835 ins_pipe(iload_mem);
5836 %}
5837
5838 // Load Compressed Pointer
5839 instruct loadN(iRegN dst, memory mem) %{
5840 match(Set dst (LoadN mem));
5841 ins_cost(MEMORY_REF_COST);
5842 size(4);
5843
5844 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
5845 ins_encode %{
5846 __ lduw($mem$$Address, $dst$$Register);
5847 %}
5848 ins_pipe(iload_mem);
5849 %}
5850
5851 // Load Klass Pointer
5852 instruct loadKlass(iRegP dst, memory mem) %{
5853 match(Set dst (LoadKlass mem));
5854 ins_cost(MEMORY_REF_COST);
5855 size(4);
5856
5857 #ifndef _LP64
5858 format %{ "LDUW $mem,$dst\t! klass ptr" %}
5859 ins_encode %{
5860 __ lduw($mem$$Address, $dst$$Register);
5861 %}
5862 #else
5863 format %{ "LDX $mem,$dst\t! klass ptr" %}
5864 ins_encode %{
5865 __ ldx($mem$$Address, $dst$$Register);
5866 %}
5867 #endif
5868 ins_pipe(iload_mem);
5869 %}
5870
5871 // Load narrow Klass Pointer
5872 instruct loadNKlass(iRegN dst, memory mem) %{
5873 match(Set dst (LoadNKlass mem));
5874 ins_cost(MEMORY_REF_COST);
5875 size(4);
5876
5877 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
5878 ins_encode %{
5879 __ lduw($mem$$Address, $dst$$Register);
5880 %}
5881 ins_pipe(iload_mem);
5882 %}
5883
5884 // Load Double
5885 instruct loadD(regD dst, memory mem) %{
5886 match(Set dst (LoadD mem));
5887 ins_cost(MEMORY_REF_COST);
5888
5889 format %{ "LDDF $mem,$dst" %}
5890 opcode(Assembler::lddf_op3);
5891 ins_encode(simple_form3_mem_reg( mem, dst ) );
5892 ins_pipe(floadD_mem);
5893 %}
5894
5895 // Load Double - UNaligned
5896 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5897 match(Set dst (LoadD_unaligned mem));
5898 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5899 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
5900 "\tLDF $mem+4,$dst.lo\t!" %}
5901 opcode(Assembler::ldf_op3);
5902 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5903 ins_pipe(iload_mem);
5904 %}
5905
5906 // Load Float
5907 instruct loadF(regF dst, memory mem) %{
5908 match(Set dst (LoadF mem));
5909 ins_cost(MEMORY_REF_COST);
5910
5911 format %{ "LDF $mem,$dst" %}
5912 opcode(Assembler::ldf_op3);
5913 ins_encode(simple_form3_mem_reg( mem, dst ) );
5914 ins_pipe(floadF_mem);
5915 %}
5916
5917 // Load Constant
5918 instruct loadConI( iRegI dst, immI src ) %{
5919 match(Set dst src);
5920 ins_cost(DEFAULT_COST * 3/2);
5921 format %{ "SET $src,$dst" %}
5922 ins_encode( Set32(src, dst) );
5923 ins_pipe(ialu_hi_lo_reg);
5924 %}
5925
5926 instruct loadConI13( iRegI dst, immI13 src ) %{
5927 match(Set dst src);
5928
5929 size(4);
5930 format %{ "MOV $src,$dst" %}
5931 ins_encode( Set13( src, dst ) );
5932 ins_pipe(ialu_imm);
5933 %}
5934
5935 #ifndef _LP64
5936 instruct loadConP(iRegP dst, immP con) %{
5937 match(Set dst con);
5938 ins_cost(DEFAULT_COST * 3/2);
5939 format %{ "SET $con,$dst\t!ptr" %}
5940 ins_encode %{
5941 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5942 intptr_t val = $con$$constant;
5943 if (constant_reloc == relocInfo::oop_type) {
5944 __ set_oop_constant((jobject) val, $dst$$Register);
5945 } else if (constant_reloc == relocInfo::metadata_type) {
5946 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5947 } else { // non-oop pointers, e.g. card mark base, heap top
5948 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5949 __ set(val, $dst$$Register);
5950 }
5951 %}
5952 ins_pipe(loadConP);
5953 %}
5954 #else
5955 instruct loadConP_set(iRegP dst, immP_set con) %{
5956 match(Set dst con);
5957 ins_cost(DEFAULT_COST * 3/2);
5958 format %{ "SET $con,$dst\t! ptr" %}
5959 ins_encode %{
5960 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5961 intptr_t val = $con$$constant;
5962 if (constant_reloc == relocInfo::oop_type) {
5963 __ set_oop_constant((jobject) val, $dst$$Register);
5964 } else if (constant_reloc == relocInfo::metadata_type) {
5965 __ set_metadata_constant((Metadata*)val, $dst$$Register);
5966 } else { // non-oop pointers, e.g. card mark base, heap top
5967 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5968 __ set(val, $dst$$Register);
5969 }
5970 %}
5971 ins_pipe(loadConP);
5972 %}
5973
5974 instruct loadConP_load(iRegP dst, immP_load con) %{
5975 match(Set dst con);
5976 ins_cost(MEMORY_REF_COST);
5977 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5978 ins_encode %{
5979 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5980 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5981 %}
5982 ins_pipe(loadConP);
5983 %}
5984
5985 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
5986 match(Set dst con);
5987 ins_cost(DEFAULT_COST * 3/2);
5988 format %{ "SET $con,$dst\t! non-oop ptr" %}
5989 ins_encode %{
5990 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
5991 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
5992 } else {
5993 __ set($con$$constant, $dst$$Register);
5994 }
5995 %}
5996 ins_pipe(loadConP);
5997 %}
5998 #endif // _LP64
5999
6000 instruct loadConP0(iRegP dst, immP0 src) %{
6001 match(Set dst src);
6002
6003 size(4);
6004 format %{ "CLR $dst\t!ptr" %}
6005 ins_encode %{
6006 __ clr($dst$$Register);
6007 %}
6008 ins_pipe(ialu_imm);
6009 %}
6010
6011 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6012 match(Set dst src);
6013 ins_cost(DEFAULT_COST);
6014 format %{ "SET $src,$dst\t!ptr" %}
6015 ins_encode %{
6016 AddressLiteral polling_page(os::get_polling_page());
6017 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6018 %}
6019 ins_pipe(loadConP_poll);
6020 %}
6021
6022 instruct loadConN0(iRegN dst, immN0 src) %{
6023 match(Set dst src);
6024
6025 size(4);
6026 format %{ "CLR $dst\t! compressed NULL ptr" %}
6027 ins_encode %{
6028 __ clr($dst$$Register);
6029 %}
6030 ins_pipe(ialu_imm);
6031 %}
6032
6033 instruct loadConN(iRegN dst, immN src) %{
6034 match(Set dst src);
6035 ins_cost(DEFAULT_COST * 3/2);
6036 format %{ "SET $src,$dst\t! compressed ptr" %}
6037 ins_encode %{
6038 Register dst = $dst$$Register;
6039 __ set_narrow_oop((jobject)$src$$constant, dst);
6040 %}
6041 ins_pipe(ialu_hi_lo_reg);
6042 %}
6043
6044 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6045 match(Set dst src);
6046 ins_cost(DEFAULT_COST * 3/2);
6047 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6048 ins_encode %{
6049 Register dst = $dst$$Register;
6050 __ set_narrow_klass((Klass*)$src$$constant, dst);
6051 %}
6052 ins_pipe(ialu_hi_lo_reg);
6053 %}
6054
6055 // Materialize long value (predicated by immL_cheap).
6056 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6057 match(Set dst con);
6058 effect(KILL tmp);
6059 ins_cost(DEFAULT_COST * 3);
6060 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6061 ins_encode %{
6062 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6063 %}
6064 ins_pipe(loadConL);
6065 %}
6066
6067 // Load long value from constant table (predicated by immL_expensive).
6068 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6069 match(Set dst con);
6070 ins_cost(MEMORY_REF_COST);
6071 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6072 ins_encode %{
6073 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6074 __ ldx($constanttablebase, con_offset, $dst$$Register);
6075 %}
6076 ins_pipe(loadConL);
6077 %}
6078
6079 instruct loadConL0( iRegL dst, immL0 src ) %{
6080 match(Set dst src);
6081 ins_cost(DEFAULT_COST);
6082 size(4);
6083 format %{ "CLR $dst\t! long" %}
6084 ins_encode( Set13( src, dst ) );
6085 ins_pipe(ialu_imm);
6086 %}
6087
6088 instruct loadConL13( iRegL dst, immL13 src ) %{
6089 match(Set dst src);
6090 ins_cost(DEFAULT_COST * 2);
6091
6092 size(4);
6093 format %{ "MOV $src,$dst\t! long" %}
6094 ins_encode( Set13( src, dst ) );
6095 ins_pipe(ialu_imm);
6096 %}
6097
6098 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6099 match(Set dst con);
6100 effect(KILL tmp);
6101 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6102 ins_encode %{
6103 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6104 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6105 %}
6106 ins_pipe(loadConFD);
6107 %}
6108
6109 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6110 match(Set dst con);
6111 effect(KILL tmp);
6112 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6113 ins_encode %{
6114 // XXX This is a quick fix for 6833573.
6115 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6116 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6117 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6118 %}
6119 ins_pipe(loadConFD);
6120 %}
6121
6122 // Prefetch instructions for allocation.
6123 // Must be safe to execute with invalid address (cannot fault).
6124
6125 instruct prefetchAlloc( memory mem ) %{
6126 predicate(AllocatePrefetchInstr == 0);
6127 match( PrefetchAllocation mem );
6128 ins_cost(MEMORY_REF_COST);
6129
6130 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6131 opcode(Assembler::prefetch_op3);
6132 ins_encode( form3_mem_prefetch_write( mem ) );
6133 ins_pipe(iload_mem);
6134 %}
6135
6136 // Use BIS instruction to prefetch for allocation.
6137 // Could fault, need space at the end of TLAB.
6138 instruct prefetchAlloc_bis( iRegP dst ) %{
6139 predicate(AllocatePrefetchInstr == 1);
6140 match( PrefetchAllocation dst );
6141 ins_cost(MEMORY_REF_COST);
6142 size(4);
6143
6144 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6145 ins_encode %{
6146 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6147 %}
6148 ins_pipe(istore_mem_reg);
6149 %}
6150
6151 // Next code is used for finding next cache line address to prefetch.
6152 #ifndef _LP64
6153 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6154 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6155 ins_cost(DEFAULT_COST);
6156 size(4);
6157
6158 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6159 ins_encode %{
6160 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6161 %}
6162 ins_pipe(ialu_reg_imm);
6163 %}
6164 #else
6165 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6166 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6167 ins_cost(DEFAULT_COST);
6168 size(4);
6169
6170 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6171 ins_encode %{
6172 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6173 %}
6174 ins_pipe(ialu_reg_imm);
6175 %}
6176 #endif
6177
6178 //----------Store Instructions-------------------------------------------------
6179 // Store Byte
6180 instruct storeB(memory mem, iRegI src) %{
6181 match(Set mem (StoreB mem src));
6182 ins_cost(MEMORY_REF_COST);
6183
6184 format %{ "STB $src,$mem\t! byte" %}
6185 opcode(Assembler::stb_op3);
6186 ins_encode(simple_form3_mem_reg( mem, src ) );
6187 ins_pipe(istore_mem_reg);
6188 %}
6189
6190 instruct storeB0(memory mem, immI0 src) %{
6191 match(Set mem (StoreB mem src));
6192 ins_cost(MEMORY_REF_COST);
6193
6194 format %{ "STB $src,$mem\t! byte" %}
6195 opcode(Assembler::stb_op3);
6196 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6197 ins_pipe(istore_mem_zero);
6198 %}
6199
6200 instruct storeCM0(memory mem, immI0 src) %{
6201 match(Set mem (StoreCM mem src));
6202 ins_cost(MEMORY_REF_COST);
6203
6204 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6205 opcode(Assembler::stb_op3);
6206 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6207 ins_pipe(istore_mem_zero);
6208 %}
6209
6210 // Store Char/Short
6211 instruct storeC(memory mem, iRegI src) %{
6212 match(Set mem (StoreC mem src));
6213 ins_cost(MEMORY_REF_COST);
6214
6215 format %{ "STH $src,$mem\t! short" %}
6216 opcode(Assembler::sth_op3);
6217 ins_encode(simple_form3_mem_reg( mem, src ) );
6218 ins_pipe(istore_mem_reg);
6219 %}
6220
6221 instruct storeC0(memory mem, immI0 src) %{
6222 match(Set mem (StoreC mem src));
6223 ins_cost(MEMORY_REF_COST);
6224
6225 format %{ "STH $src,$mem\t! short" %}
6226 opcode(Assembler::sth_op3);
6227 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6228 ins_pipe(istore_mem_zero);
6229 %}
6230
6231 // Store Integer
6232 instruct storeI(memory mem, iRegI src) %{
6233 match(Set mem (StoreI mem src));
6234 ins_cost(MEMORY_REF_COST);
6235
6236 format %{ "STW $src,$mem" %}
6237 opcode(Assembler::stw_op3);
6238 ins_encode(simple_form3_mem_reg( mem, src ) );
6239 ins_pipe(istore_mem_reg);
6240 %}
6241
6242 // Store Long
6243 instruct storeL(memory mem, iRegL src) %{
6244 match(Set mem (StoreL mem src));
6245 ins_cost(MEMORY_REF_COST);
6246 format %{ "STX $src,$mem\t! long" %}
6247 opcode(Assembler::stx_op3);
6248 ins_encode(simple_form3_mem_reg( mem, src ) );
6249 ins_pipe(istore_mem_reg);
6250 %}
6251
6252 instruct storeI0(memory mem, immI0 src) %{
6253 match(Set mem (StoreI mem src));
6254 ins_cost(MEMORY_REF_COST);
6255
6256 format %{ "STW $src,$mem" %}
6257 opcode(Assembler::stw_op3);
6258 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6259 ins_pipe(istore_mem_zero);
6260 %}
6261
6262 instruct storeL0(memory mem, immL0 src) %{
6263 match(Set mem (StoreL mem src));
6264 ins_cost(MEMORY_REF_COST);
6265
6266 format %{ "STX $src,$mem" %}
6267 opcode(Assembler::stx_op3);
6268 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6269 ins_pipe(istore_mem_zero);
6270 %}
6271
6272 // Store Integer from float register (used after fstoi)
6273 instruct storeI_Freg(memory mem, regF src) %{
6274 match(Set mem (StoreI mem src));
6275 ins_cost(MEMORY_REF_COST);
6276
6277 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6278 opcode(Assembler::stf_op3);
6279 ins_encode(simple_form3_mem_reg( mem, src ) );
6280 ins_pipe(fstoreF_mem_reg);
6281 %}
6282
6283 // Store Pointer
6284 instruct storeP(memory dst, sp_ptr_RegP src) %{
6285 match(Set dst (StoreP dst src));
6286 ins_cost(MEMORY_REF_COST);
6287
6288 #ifndef _LP64
6289 format %{ "STW $src,$dst\t! ptr" %}
6290 opcode(Assembler::stw_op3, 0, REGP_OP);
6291 #else
6292 format %{ "STX $src,$dst\t! ptr" %}
6293 opcode(Assembler::stx_op3, 0, REGP_OP);
6294 #endif
6295 ins_encode( form3_mem_reg( dst, src ) );
6296 ins_pipe(istore_mem_spORreg);
6297 %}
6298
6299 instruct storeP0(memory dst, immP0 src) %{
6300 match(Set dst (StoreP dst src));
6301 ins_cost(MEMORY_REF_COST);
6302
6303 #ifndef _LP64
6304 format %{ "STW $src,$dst\t! ptr" %}
6305 opcode(Assembler::stw_op3, 0, REGP_OP);
6306 #else
6307 format %{ "STX $src,$dst\t! ptr" %}
6308 opcode(Assembler::stx_op3, 0, REGP_OP);
6309 #endif
6310 ins_encode( form3_mem_reg( dst, R_G0 ) );
6311 ins_pipe(istore_mem_zero);
6312 %}
6313
6314 // Store Compressed Pointer
6315 instruct storeN(memory dst, iRegN src) %{
6316 match(Set dst (StoreN dst src));
6317 ins_cost(MEMORY_REF_COST);
6318 size(4);
6319
6320 format %{ "STW $src,$dst\t! compressed ptr" %}
6321 ins_encode %{
6322 Register base = as_Register($dst$$base);
6323 Register index = as_Register($dst$$index);
6324 Register src = $src$$Register;
6325 if (index != G0) {
6326 __ stw(src, base, index);
6327 } else {
6328 __ stw(src, base, $dst$$disp);
6329 }
6330 %}
6331 ins_pipe(istore_mem_spORreg);
6332 %}
6333
6334 instruct storeNKlass(memory dst, iRegN src) %{
6335 match(Set dst (StoreNKlass dst src));
6336 ins_cost(MEMORY_REF_COST);
6337 size(4);
6338
6339 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6340 ins_encode %{
6341 Register base = as_Register($dst$$base);
6342 Register index = as_Register($dst$$index);
6343 Register src = $src$$Register;
6344 if (index != G0) {
6345 __ stw(src, base, index);
6346 } else {
6347 __ stw(src, base, $dst$$disp);
6348 }
6349 %}
6350 ins_pipe(istore_mem_spORreg);
6351 %}
6352
6353 instruct storeN0(memory dst, immN0 src) %{
6354 match(Set dst (StoreN dst src));
6355 ins_cost(MEMORY_REF_COST);
6356 size(4);
6357
6358 format %{ "STW $src,$dst\t! compressed ptr" %}
6359 ins_encode %{
6360 Register base = as_Register($dst$$base);
6361 Register index = as_Register($dst$$index);
6362 if (index != G0) {
6363 __ stw(0, base, index);
6364 } else {
6365 __ stw(0, base, $dst$$disp);
6366 }
6367 %}
6368 ins_pipe(istore_mem_zero);
6369 %}
6370
6371 // Store Double
6372 instruct storeD( memory mem, regD src) %{
6373 match(Set mem (StoreD mem src));
6374 ins_cost(MEMORY_REF_COST);
6375
6376 format %{ "STDF $src,$mem" %}
6377 opcode(Assembler::stdf_op3);
6378 ins_encode(simple_form3_mem_reg( mem, src ) );
6379 ins_pipe(fstoreD_mem_reg);
6380 %}
6381
6382 instruct storeD0( memory mem, immD0 src) %{
6383 match(Set mem (StoreD mem src));
6384 ins_cost(MEMORY_REF_COST);
6385
6386 format %{ "STX $src,$mem" %}
6387 opcode(Assembler::stx_op3);
6388 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6389 ins_pipe(fstoreD_mem_zero);
6390 %}
6391
6392 // Store Float
6393 instruct storeF( memory mem, regF src) %{
6394 match(Set mem (StoreF mem src));
6395 ins_cost(MEMORY_REF_COST);
6396
6397 format %{ "STF $src,$mem" %}
6398 opcode(Assembler::stf_op3);
6399 ins_encode(simple_form3_mem_reg( mem, src ) );
6400 ins_pipe(fstoreF_mem_reg);
6401 %}
6402
6403 instruct storeF0( memory mem, immF0 src) %{
6404 match(Set mem (StoreF mem src));
6405 ins_cost(MEMORY_REF_COST);
6406
6407 format %{ "STW $src,$mem\t! storeF0" %}
6408 opcode(Assembler::stw_op3);
6409 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6410 ins_pipe(fstoreF_mem_zero);
6411 %}
6412
6413 // Convert oop pointer into compressed form
6414 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6415 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6416 match(Set dst (EncodeP src));
6417 format %{ "encode_heap_oop $src, $dst" %}
6418 ins_encode %{
6419 __ encode_heap_oop($src$$Register, $dst$$Register);
6420 %}
6421 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6422 ins_pipe(ialu_reg);
6423 %}
6424
6425 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6426 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6427 match(Set dst (EncodeP src));
6428 format %{ "encode_heap_oop_not_null $src, $dst" %}
6429 ins_encode %{
6430 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6431 %}
6432 ins_pipe(ialu_reg);
6433 %}
6434
6435 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6436 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6437 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6438 match(Set dst (DecodeN src));
6439 format %{ "decode_heap_oop $src, $dst" %}
6440 ins_encode %{
6441 __ decode_heap_oop($src$$Register, $dst$$Register);
6442 %}
6443 ins_pipe(ialu_reg);
6444 %}
6445
6446 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6447 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6448 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6449 match(Set dst (DecodeN src));
6450 format %{ "decode_heap_oop_not_null $src, $dst" %}
6451 ins_encode %{
6452 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6453 %}
6454 ins_pipe(ialu_reg);
6455 %}
6456
6457 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6458 match(Set dst (EncodePKlass src));
6459 format %{ "encode_klass_not_null $src, $dst" %}
6460 ins_encode %{
6461 __ encode_klass_not_null($src$$Register, $dst$$Register);
6462 %}
6463 ins_pipe(ialu_reg);
6464 %}
6465
6466 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6467 match(Set dst (DecodeNKlass src));
6468 format %{ "decode_klass_not_null $src, $dst" %}
6469 ins_encode %{
6470 __ decode_klass_not_null($src$$Register, $dst$$Register);
6471 %}
6472 ins_pipe(ialu_reg);
6473 %}
6474
6475 //----------MemBar Instructions-----------------------------------------------
6476 // Memory barrier flavors
6477
6478 instruct membar_acquire() %{
6479 match(MemBarAcquire);
6480 match(LoadFence);
6481 ins_cost(4*MEMORY_REF_COST);
6482
6483 size(0);
6484 format %{ "MEMBAR-acquire" %}
6485 ins_encode( enc_membar_acquire );
6486 ins_pipe(long_memory_op);
6487 %}
6488
6489 instruct membar_acquire_lock() %{
6490 match(MemBarAcquireLock);
6491 ins_cost(0);
6492
6493 size(0);
6494 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6495 ins_encode( );
6496 ins_pipe(empty);
6497 %}
6498
6499 instruct membar_release() %{
6500 match(MemBarRelease);
6501 match(StoreFence);
6502 ins_cost(4*MEMORY_REF_COST);
6503
6504 size(0);
6505 format %{ "MEMBAR-release" %}
6506 ins_encode( enc_membar_release );
6507 ins_pipe(long_memory_op);
6508 %}
6509
6510 instruct membar_release_lock() %{
6511 match(MemBarReleaseLock);
6512 ins_cost(0);
6513
6514 size(0);
6515 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6516 ins_encode( );
6517 ins_pipe(empty);
6518 %}
6519
6520 instruct membar_volatile() %{
6521 match(MemBarVolatile);
6522 ins_cost(4*MEMORY_REF_COST);
6523
6524 size(4);
6525 format %{ "MEMBAR-volatile" %}
6526 ins_encode( enc_membar_volatile );
6527 ins_pipe(long_memory_op);
6528 %}
6529
6530 instruct unnecessary_membar_volatile() %{
6531 match(MemBarVolatile);
6532 predicate(Matcher::post_store_load_barrier(n));
6533 ins_cost(0);
6534
6535 size(0);
6536 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6537 ins_encode( );
6538 ins_pipe(empty);
6539 %}
6540
6541 instruct membar_storestore() %{
6542 match(MemBarStoreStore);
6543 ins_cost(0);
6544
6545 size(0);
6546 format %{ "!MEMBAR-storestore (empty encoding)" %}
6547 ins_encode( );
6548 ins_pipe(empty);
6549 %}
6550
6551 //----------Register Move Instructions-----------------------------------------
6552 instruct roundDouble_nop(regD dst) %{
6553 match(Set dst (RoundDouble dst));
6554 ins_cost(0);
6555 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6556 ins_encode( );
6557 ins_pipe(empty);
6558 %}
6559
6560
6561 instruct roundFloat_nop(regF dst) %{
6562 match(Set dst (RoundFloat dst));
6563 ins_cost(0);
6564 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6565 ins_encode( );
6566 ins_pipe(empty);
6567 %}
6568
6569
6570 // Cast Index to Pointer for unsafe natives
6571 instruct castX2P(iRegX src, iRegP dst) %{
6572 match(Set dst (CastX2P src));
6573
6574 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6575 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6576 ins_pipe(ialu_reg);
6577 %}
6578
6579 // Cast Pointer to Index for unsafe natives
6580 instruct castP2X(iRegP src, iRegX dst) %{
6581 match(Set dst (CastP2X src));
6582
6583 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6584 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6585 ins_pipe(ialu_reg);
6586 %}
6587
6588 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6589 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6590 match(Set stkSlot src); // chain rule
6591 ins_cost(MEMORY_REF_COST);
6592 format %{ "STDF $src,$stkSlot\t!stk" %}
6593 opcode(Assembler::stdf_op3);
6594 ins_encode(simple_form3_mem_reg(stkSlot, src));
6595 ins_pipe(fstoreD_stk_reg);
6596 %}
6597
6598 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6599 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6600 match(Set dst stkSlot); // chain rule
6601 ins_cost(MEMORY_REF_COST);
6602 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6603 opcode(Assembler::lddf_op3);
6604 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6605 ins_pipe(floadD_stk);
6606 %}
6607
6608 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6609 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6610 match(Set stkSlot src); // chain rule
6611 ins_cost(MEMORY_REF_COST);
6612 format %{ "STF $src,$stkSlot\t!stk" %}
6613 opcode(Assembler::stf_op3);
6614 ins_encode(simple_form3_mem_reg(stkSlot, src));
6615 ins_pipe(fstoreF_stk_reg);
6616 %}
6617
6618 //----------Conditional Move---------------------------------------------------
6619 // Conditional move
6620 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6621 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6622 ins_cost(150);
6623 format %{ "MOV$cmp $pcc,$src,$dst" %}
6624 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6625 ins_pipe(ialu_reg);
6626 %}
6627
6628 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6629 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6630 ins_cost(140);
6631 format %{ "MOV$cmp $pcc,$src,$dst" %}
6632 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6633 ins_pipe(ialu_imm);
6634 %}
6635
6636 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6637 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6638 ins_cost(150);
6639 size(4);
6640 format %{ "MOV$cmp $icc,$src,$dst" %}
6641 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6642 ins_pipe(ialu_reg);
6643 %}
6644
6645 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6646 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6647 ins_cost(140);
6648 size(4);
6649 format %{ "MOV$cmp $icc,$src,$dst" %}
6650 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6651 ins_pipe(ialu_imm);
6652 %}
6653
6654 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6655 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6656 ins_cost(150);
6657 size(4);
6658 format %{ "MOV$cmp $icc,$src,$dst" %}
6659 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6660 ins_pipe(ialu_reg);
6661 %}
6662
6663 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6664 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6665 ins_cost(140);
6666 size(4);
6667 format %{ "MOV$cmp $icc,$src,$dst" %}
6668 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6669 ins_pipe(ialu_imm);
6670 %}
6671
6672 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6673 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6674 ins_cost(150);
6675 size(4);
6676 format %{ "MOV$cmp $fcc,$src,$dst" %}
6677 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6678 ins_pipe(ialu_reg);
6679 %}
6680
6681 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6682 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6683 ins_cost(140);
6684 size(4);
6685 format %{ "MOV$cmp $fcc,$src,$dst" %}
6686 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6687 ins_pipe(ialu_imm);
6688 %}
6689
6690 // Conditional move for RegN. Only cmov(reg,reg).
6691 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6692 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6693 ins_cost(150);
6694 format %{ "MOV$cmp $pcc,$src,$dst" %}
6695 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6696 ins_pipe(ialu_reg);
6697 %}
6698
6699 // This instruction also works with CmpN so we don't need cmovNN_reg.
6700 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6701 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6702 ins_cost(150);
6703 size(4);
6704 format %{ "MOV$cmp $icc,$src,$dst" %}
6705 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6706 ins_pipe(ialu_reg);
6707 %}
6708
6709 // This instruction also works with CmpN so we don't need cmovNN_reg.
6710 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6711 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6712 ins_cost(150);
6713 size(4);
6714 format %{ "MOV$cmp $icc,$src,$dst" %}
6715 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6716 ins_pipe(ialu_reg);
6717 %}
6718
6719 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6720 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6721 ins_cost(150);
6722 size(4);
6723 format %{ "MOV$cmp $fcc,$src,$dst" %}
6724 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6725 ins_pipe(ialu_reg);
6726 %}
6727
6728 // Conditional move
6729 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6730 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6731 ins_cost(150);
6732 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6733 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6734 ins_pipe(ialu_reg);
6735 %}
6736
6737 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6738 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6739 ins_cost(140);
6740 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6741 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6742 ins_pipe(ialu_imm);
6743 %}
6744
6745 // This instruction also works with CmpN so we don't need cmovPN_reg.
6746 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6747 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6748 ins_cost(150);
6749
6750 size(4);
6751 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6752 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6753 ins_pipe(ialu_reg);
6754 %}
6755
6756 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6757 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6758 ins_cost(150);
6759
6760 size(4);
6761 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6762 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6763 ins_pipe(ialu_reg);
6764 %}
6765
6766 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6767 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6768 ins_cost(140);
6769
6770 size(4);
6771 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6772 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6773 ins_pipe(ialu_imm);
6774 %}
6775
6776 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6777 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6778 ins_cost(140);
6779
6780 size(4);
6781 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6782 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6783 ins_pipe(ialu_imm);
6784 %}
6785
6786 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6787 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6788 ins_cost(150);
6789 size(4);
6790 format %{ "MOV$cmp $fcc,$src,$dst" %}
6791 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6792 ins_pipe(ialu_imm);
6793 %}
6794
6795 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6796 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6797 ins_cost(140);
6798 size(4);
6799 format %{ "MOV$cmp $fcc,$src,$dst" %}
6800 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6801 ins_pipe(ialu_imm);
6802 %}
6803
6804 // Conditional move
6805 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6806 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6807 ins_cost(150);
6808 opcode(0x101);
6809 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6810 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6811 ins_pipe(int_conditional_float_move);
6812 %}
6813
6814 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6815 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6816 ins_cost(150);
6817
6818 size(4);
6819 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6820 opcode(0x101);
6821 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6822 ins_pipe(int_conditional_float_move);
6823 %}
6824
6825 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6826 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6827 ins_cost(150);
6828
6829 size(4);
6830 format %{ "FMOVS$cmp $icc,$src,$dst" %}
6831 opcode(0x101);
6832 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6833 ins_pipe(int_conditional_float_move);
6834 %}
6835
6836 // Conditional move,
6837 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6838 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6839 ins_cost(150);
6840 size(4);
6841 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6842 opcode(0x1);
6843 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6844 ins_pipe(int_conditional_double_move);
6845 %}
6846
6847 // Conditional move
6848 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6849 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6850 ins_cost(150);
6851 size(4);
6852 opcode(0x102);
6853 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6854 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6855 ins_pipe(int_conditional_double_move);
6856 %}
6857
6858 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6859 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6860 ins_cost(150);
6861
6862 size(4);
6863 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6864 opcode(0x102);
6865 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6866 ins_pipe(int_conditional_double_move);
6867 %}
6868
6869 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6870 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6871 ins_cost(150);
6872
6873 size(4);
6874 format %{ "FMOVD$cmp $icc,$src,$dst" %}
6875 opcode(0x102);
6876 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6877 ins_pipe(int_conditional_double_move);
6878 %}
6879
6880 // Conditional move,
6881 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6882 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6883 ins_cost(150);
6884 size(4);
6885 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6886 opcode(0x2);
6887 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6888 ins_pipe(int_conditional_double_move);
6889 %}
6890
6891 // Conditional move
6892 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6893 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6894 ins_cost(150);
6895 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6896 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6897 ins_pipe(ialu_reg);
6898 %}
6899
6900 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6901 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6902 ins_cost(140);
6903 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6904 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6905 ins_pipe(ialu_imm);
6906 %}
6907
6908 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6909 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6910 ins_cost(150);
6911
6912 size(4);
6913 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6914 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6915 ins_pipe(ialu_reg);
6916 %}
6917
6918
6919 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6920 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6921 ins_cost(150);
6922
6923 size(4);
6924 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
6925 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6926 ins_pipe(ialu_reg);
6927 %}
6928
6929
6930 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6931 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6932 ins_cost(150);
6933
6934 size(4);
6935 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
6936 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6937 ins_pipe(ialu_reg);
6938 %}
6939
6940
6941
6942 //----------OS and Locking Instructions----------------------------------------
6943
6944 // This name is KNOWN by the ADLC and cannot be changed.
6945 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6946 // for this guy.
6947 instruct tlsLoadP(g2RegP dst) %{
6948 match(Set dst (ThreadLocal));
6949
6950 size(0);
6951 ins_cost(0);
6952 format %{ "# TLS is in G2" %}
6953 ins_encode( /*empty encoding*/ );
6954 ins_pipe(ialu_none);
6955 %}
6956
6957 instruct checkCastPP( iRegP dst ) %{
6958 match(Set dst (CheckCastPP dst));
6959
6960 size(0);
6961 format %{ "# checkcastPP of $dst" %}
6962 ins_encode( /*empty encoding*/ );
6963 ins_pipe(empty);
6964 %}
6965
6966
6967 instruct castPP( iRegP dst ) %{
6968 match(Set dst (CastPP dst));
6969 format %{ "# castPP of $dst" %}
6970 ins_encode( /*empty encoding*/ );
6971 ins_pipe(empty);
6972 %}
6973
6974 instruct castII( iRegI dst ) %{
6975 match(Set dst (CastII dst));
6976 format %{ "# castII of $dst" %}
6977 ins_encode( /*empty encoding*/ );
6978 ins_cost(0);
6979 ins_pipe(empty);
6980 %}
6981
6982 //----------Arithmetic Instructions--------------------------------------------
6983 // Addition Instructions
6984 // Register Addition
6985 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6986 match(Set dst (AddI src1 src2));
6987
6988 size(4);
6989 format %{ "ADD $src1,$src2,$dst" %}
6990 ins_encode %{
6991 __ add($src1$$Register, $src2$$Register, $dst$$Register);
6992 %}
6993 ins_pipe(ialu_reg_reg);
6994 %}
6995
6996 // Immediate Addition
6997 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
6998 match(Set dst (AddI src1 src2));
6999
7000 size(4);
7001 format %{ "ADD $src1,$src2,$dst" %}
7002 opcode(Assembler::add_op3, Assembler::arith_op);
7003 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7004 ins_pipe(ialu_reg_imm);
7005 %}
7006
7007 // Pointer Register Addition
7008 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7009 match(Set dst (AddP src1 src2));
7010
7011 size(4);
7012 format %{ "ADD $src1,$src2,$dst" %}
7013 opcode(Assembler::add_op3, Assembler::arith_op);
7014 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7015 ins_pipe(ialu_reg_reg);
7016 %}
7017
7018 // Pointer Immediate Addition
7019 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7020 match(Set dst (AddP src1 src2));
7021
7022 size(4);
7023 format %{ "ADD $src1,$src2,$dst" %}
7024 opcode(Assembler::add_op3, Assembler::arith_op);
7025 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7026 ins_pipe(ialu_reg_imm);
7027 %}
7028
7029 // Long Addition
7030 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7031 match(Set dst (AddL src1 src2));
7032
7033 size(4);
7034 format %{ "ADD $src1,$src2,$dst\t! long" %}
7035 opcode(Assembler::add_op3, Assembler::arith_op);
7036 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7037 ins_pipe(ialu_reg_reg);
7038 %}
7039
7040 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7041 match(Set dst (AddL src1 con));
7042
7043 size(4);
7044 format %{ "ADD $src1,$con,$dst" %}
7045 opcode(Assembler::add_op3, Assembler::arith_op);
7046 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7047 ins_pipe(ialu_reg_imm);
7048 %}
7049
7050 //----------Conditional_store--------------------------------------------------
7051 // Conditional-store of the updated heap-top.
7052 // Used during allocation of the shared heap.
7053 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7054
7055 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7056 instruct loadPLocked(iRegP dst, memory mem) %{
7057 match(Set dst (LoadPLocked mem));
7058 ins_cost(MEMORY_REF_COST);
7059
7060 #ifndef _LP64
7061 format %{ "LDUW $mem,$dst\t! ptr" %}
7062 opcode(Assembler::lduw_op3, 0, REGP_OP);
7063 #else
7064 format %{ "LDX $mem,$dst\t! ptr" %}
7065 opcode(Assembler::ldx_op3, 0, REGP_OP);
7066 #endif
7067 ins_encode( form3_mem_reg( mem, dst ) );
7068 ins_pipe(iload_mem);
7069 %}
7070
7071 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7072 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7073 effect( KILL newval );
7074 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7075 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7076 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7077 ins_pipe( long_memory_op );
7078 %}
7079
7080 // Conditional-store of an int value.
7081 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7082 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7083 effect( KILL newval );
7084 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7085 "CMP $oldval,$newval\t\t! See if we made progress" %}
7086 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7087 ins_pipe( long_memory_op );
7088 %}
7089
7090 // Conditional-store of a long value.
7091 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7092 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7093 effect( KILL newval );
7094 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7095 "CMP $oldval,$newval\t\t! See if we made progress" %}
7096 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7097 ins_pipe( long_memory_op );
7098 %}
7099
7100 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7101
7102 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7103 predicate(VM_Version::supports_cx8());
7104 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7105 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7106 format %{
7107 "MOV $newval,O7\n\t"
7108 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7109 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7110 "MOV 1,$res\n\t"
7111 "MOVne xcc,R_G0,$res"
7112 %}
7113 ins_encode( enc_casx(mem_ptr, oldval, newval),
7114 enc_lflags_ne_to_boolean(res) );
7115 ins_pipe( long_memory_op );
7116 %}
7117
7118
7119 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7120 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7121 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7122 format %{
7123 "MOV $newval,O7\n\t"
7124 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7125 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7126 "MOV 1,$res\n\t"
7127 "MOVne icc,R_G0,$res"
7128 %}
7129 ins_encode( enc_casi(mem_ptr, oldval, newval),
7130 enc_iflags_ne_to_boolean(res) );
7131 ins_pipe( long_memory_op );
7132 %}
7133
7134 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7135 #ifdef _LP64
7136 predicate(VM_Version::supports_cx8());
7137 #endif
7138 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7139 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7140 format %{
7141 "MOV $newval,O7\n\t"
7142 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7143 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7144 "MOV 1,$res\n\t"
7145 "MOVne xcc,R_G0,$res"
7146 %}
7147 #ifdef _LP64
7148 ins_encode( enc_casx(mem_ptr, oldval, newval),
7149 enc_lflags_ne_to_boolean(res) );
7150 #else
7151 ins_encode( enc_casi(mem_ptr, oldval, newval),
7152 enc_iflags_ne_to_boolean(res) );
7153 #endif
7154 ins_pipe( long_memory_op );
7155 %}
7156
7157 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7158 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7159 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7160 format %{
7161 "MOV $newval,O7\n\t"
7162 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7163 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7164 "MOV 1,$res\n\t"
7165 "MOVne icc,R_G0,$res"
7166 %}
7167 ins_encode( enc_casi(mem_ptr, oldval, newval),
7168 enc_iflags_ne_to_boolean(res) );
7169 ins_pipe( long_memory_op );
7170 %}
7171
7172 instruct xchgI( memory mem, iRegI newval) %{
7173 match(Set newval (GetAndSetI mem newval));
7174 format %{ "SWAP [$mem],$newval" %}
7175 size(4);
7176 ins_encode %{
7177 __ swap($mem$$Address, $newval$$Register);
7178 %}
7179 ins_pipe( long_memory_op );
7180 %}
7181
7182 #ifndef _LP64
7183 instruct xchgP( memory mem, iRegP newval) %{
7184 match(Set newval (GetAndSetP mem newval));
7185 format %{ "SWAP [$mem],$newval" %}
7186 size(4);
7187 ins_encode %{
7188 __ swap($mem$$Address, $newval$$Register);
7189 %}
7190 ins_pipe( long_memory_op );
7191 %}
7192 #endif
7193
7194 instruct xchgN( memory mem, iRegN newval) %{
7195 match(Set newval (GetAndSetN mem newval));
7196 format %{ "SWAP [$mem],$newval" %}
7197 size(4);
7198 ins_encode %{
7199 __ swap($mem$$Address, $newval$$Register);
7200 %}
7201 ins_pipe( long_memory_op );
7202 %}
7203
7204 //---------------------
7205 // Subtraction Instructions
7206 // Register Subtraction
7207 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7208 match(Set dst (SubI src1 src2));
7209
7210 size(4);
7211 format %{ "SUB $src1,$src2,$dst" %}
7212 opcode(Assembler::sub_op3, Assembler::arith_op);
7213 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7214 ins_pipe(ialu_reg_reg);
7215 %}
7216
7217 // Immediate Subtraction
7218 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7219 match(Set dst (SubI src1 src2));
7220
7221 size(4);
7222 format %{ "SUB $src1,$src2,$dst" %}
7223 opcode(Assembler::sub_op3, Assembler::arith_op);
7224 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7225 ins_pipe(ialu_reg_imm);
7226 %}
7227
7228 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7229 match(Set dst (SubI zero src2));
7230
7231 size(4);
7232 format %{ "NEG $src2,$dst" %}
7233 opcode(Assembler::sub_op3, Assembler::arith_op);
7234 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7235 ins_pipe(ialu_zero_reg);
7236 %}
7237
7238 // Long subtraction
7239 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7240 match(Set dst (SubL src1 src2));
7241
7242 size(4);
7243 format %{ "SUB $src1,$src2,$dst\t! long" %}
7244 opcode(Assembler::sub_op3, Assembler::arith_op);
7245 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7246 ins_pipe(ialu_reg_reg);
7247 %}
7248
7249 // Immediate Subtraction
7250 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7251 match(Set dst (SubL src1 con));
7252
7253 size(4);
7254 format %{ "SUB $src1,$con,$dst\t! long" %}
7255 opcode(Assembler::sub_op3, Assembler::arith_op);
7256 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7257 ins_pipe(ialu_reg_imm);
7258 %}
7259
7260 // Long negation
7261 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7262 match(Set dst (SubL zero src2));
7263
7264 size(4);
7265 format %{ "NEG $src2,$dst\t! long" %}
7266 opcode(Assembler::sub_op3, Assembler::arith_op);
7267 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7268 ins_pipe(ialu_zero_reg);
7269 %}
7270
7271 // Multiplication Instructions
7272 // Integer Multiplication
7273 // Register Multiplication
7274 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7275 match(Set dst (MulI src1 src2));
7276
7277 size(4);
7278 format %{ "MULX $src1,$src2,$dst" %}
7279 opcode(Assembler::mulx_op3, Assembler::arith_op);
7280 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7281 ins_pipe(imul_reg_reg);
7282 %}
7283
7284 // Immediate Multiplication
7285 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7286 match(Set dst (MulI src1 src2));
7287
7288 size(4);
7289 format %{ "MULX $src1,$src2,$dst" %}
7290 opcode(Assembler::mulx_op3, Assembler::arith_op);
7291 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7292 ins_pipe(imul_reg_imm);
7293 %}
7294
7295 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7296 match(Set dst (MulL src1 src2));
7297 ins_cost(DEFAULT_COST * 5);
7298 size(4);
7299 format %{ "MULX $src1,$src2,$dst\t! long" %}
7300 opcode(Assembler::mulx_op3, Assembler::arith_op);
7301 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7302 ins_pipe(mulL_reg_reg);
7303 %}
7304
7305 // Immediate Multiplication
7306 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7307 match(Set dst (MulL src1 src2));
7308 ins_cost(DEFAULT_COST * 5);
7309 size(4);
7310 format %{ "MULX $src1,$src2,$dst" %}
7311 opcode(Assembler::mulx_op3, Assembler::arith_op);
7312 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7313 ins_pipe(mulL_reg_imm);
7314 %}
7315
7316 // Integer Division
7317 // Register Division
7318 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7319 match(Set dst (DivI src1 src2));
7320 ins_cost((2+71)*DEFAULT_COST);
7321
7322 format %{ "SRA $src2,0,$src2\n\t"
7323 "SRA $src1,0,$src1\n\t"
7324 "SDIVX $src1,$src2,$dst" %}
7325 ins_encode( idiv_reg( src1, src2, dst ) );
7326 ins_pipe(sdiv_reg_reg);
7327 %}
7328
7329 // Immediate Division
7330 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7331 match(Set dst (DivI src1 src2));
7332 ins_cost((2+71)*DEFAULT_COST);
7333
7334 format %{ "SRA $src1,0,$src1\n\t"
7335 "SDIVX $src1,$src2,$dst" %}
7336 ins_encode( idiv_imm( src1, src2, dst ) );
7337 ins_pipe(sdiv_reg_imm);
7338 %}
7339
7340 //----------Div-By-10-Expansion------------------------------------------------
7341 // Extract hi bits of a 32x32->64 bit multiply.
7342 // Expand rule only, not matched
7343 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7344 effect( DEF dst, USE src1, USE src2 );
7345 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7346 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7347 ins_encode( enc_mul_hi(dst,src1,src2));
7348 ins_pipe(sdiv_reg_reg);
7349 %}
7350
7351 // Magic constant, reciprocal of 10
7352 instruct loadConI_x66666667(iRegIsafe dst) %{
7353 effect( DEF dst );
7354
7355 size(8);
7356 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7357 ins_encode( Set32(0x66666667, dst) );
7358 ins_pipe(ialu_hi_lo_reg);
7359 %}
7360
7361 // Register Shift Right Arithmetic Long by 32-63
7362 instruct sra_31( iRegI dst, iRegI src ) %{
7363 effect( DEF dst, USE src );
7364 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7365 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7366 ins_pipe(ialu_reg_reg);
7367 %}
7368
7369 // Arithmetic Shift Right by 8-bit immediate
7370 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7371 effect( DEF dst, USE src );
7372 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7373 opcode(Assembler::sra_op3, Assembler::arith_op);
7374 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7375 ins_pipe(ialu_reg_imm);
7376 %}
7377
7378 // Integer DIV with 10
7379 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7380 match(Set dst (DivI src div));
7381 ins_cost((6+6)*DEFAULT_COST);
7382 expand %{
7383 iRegIsafe tmp1; // Killed temps;
7384 iRegIsafe tmp2; // Killed temps;
7385 iRegI tmp3; // Killed temps;
7386 iRegI tmp4; // Killed temps;
7387 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7388 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7389 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7390 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7391 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7392 %}
7393 %}
7394
7395 // Register Long Division
7396 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7397 match(Set dst (DivL src1 src2));
7398 ins_cost(DEFAULT_COST*71);
7399 size(4);
7400 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7401 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7402 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7403 ins_pipe(divL_reg_reg);
7404 %}
7405
7406 // Register Long Division
7407 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7408 match(Set dst (DivL src1 src2));
7409 ins_cost(DEFAULT_COST*71);
7410 size(4);
7411 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7412 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7413 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7414 ins_pipe(divL_reg_imm);
7415 %}
7416
7417 // Integer Remainder
7418 // Register Remainder
7419 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7420 match(Set dst (ModI src1 src2));
7421 effect( KILL ccr, KILL temp);
7422
7423 format %{ "SREM $src1,$src2,$dst" %}
7424 ins_encode( irem_reg(src1, src2, dst, temp) );
7425 ins_pipe(sdiv_reg_reg);
7426 %}
7427
7428 // Immediate Remainder
7429 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7430 match(Set dst (ModI src1 src2));
7431 effect( KILL ccr, KILL temp);
7432
7433 format %{ "SREM $src1,$src2,$dst" %}
7434 ins_encode( irem_imm(src1, src2, dst, temp) );
7435 ins_pipe(sdiv_reg_imm);
7436 %}
7437
7438 // Register Long Remainder
7439 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7440 effect(DEF dst, USE src1, USE src2);
7441 size(4);
7442 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7443 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7444 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7445 ins_pipe(divL_reg_reg);
7446 %}
7447
7448 // Register Long Division
7449 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7450 effect(DEF dst, USE src1, USE src2);
7451 size(4);
7452 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7453 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7454 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7455 ins_pipe(divL_reg_imm);
7456 %}
7457
7458 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7459 effect(DEF dst, USE src1, USE src2);
7460 size(4);
7461 format %{ "MULX $src1,$src2,$dst\t! long" %}
7462 opcode(Assembler::mulx_op3, Assembler::arith_op);
7463 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7464 ins_pipe(mulL_reg_reg);
7465 %}
7466
7467 // Immediate Multiplication
7468 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7469 effect(DEF dst, USE src1, USE src2);
7470 size(4);
7471 format %{ "MULX $src1,$src2,$dst" %}
7472 opcode(Assembler::mulx_op3, Assembler::arith_op);
7473 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7474 ins_pipe(mulL_reg_imm);
7475 %}
7476
7477 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7478 effect(DEF dst, USE src1, USE src2);
7479 size(4);
7480 format %{ "SUB $src1,$src2,$dst\t! long" %}
7481 opcode(Assembler::sub_op3, Assembler::arith_op);
7482 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7483 ins_pipe(ialu_reg_reg);
7484 %}
7485
7486 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7487 effect(DEF dst, USE src1, USE src2);
7488 size(4);
7489 format %{ "SUB $src1,$src2,$dst\t! long" %}
7490 opcode(Assembler::sub_op3, Assembler::arith_op);
7491 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7492 ins_pipe(ialu_reg_reg);
7493 %}
7494
7495 // Register Long Remainder
7496 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7497 match(Set dst (ModL src1 src2));
7498 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7499 expand %{
7500 iRegL tmp1;
7501 iRegL tmp2;
7502 divL_reg_reg_1(tmp1, src1, src2);
7503 mulL_reg_reg_1(tmp2, tmp1, src2);
7504 subL_reg_reg_1(dst, src1, tmp2);
7505 %}
7506 %}
7507
7508 // Register Long Remainder
7509 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7510 match(Set dst (ModL src1 src2));
7511 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7512 expand %{
7513 iRegL tmp1;
7514 iRegL tmp2;
7515 divL_reg_imm13_1(tmp1, src1, src2);
7516 mulL_reg_imm13_1(tmp2, tmp1, src2);
7517 subL_reg_reg_2 (dst, src1, tmp2);
7518 %}
7519 %}
7520
7521 // Integer Shift Instructions
7522 // Register Shift Left
7523 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7524 match(Set dst (LShiftI src1 src2));
7525
7526 size(4);
7527 format %{ "SLL $src1,$src2,$dst" %}
7528 opcode(Assembler::sll_op3, Assembler::arith_op);
7529 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7530 ins_pipe(ialu_reg_reg);
7531 %}
7532
7533 // Register Shift Left Immediate
7534 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7535 match(Set dst (LShiftI src1 src2));
7536
7537 size(4);
7538 format %{ "SLL $src1,$src2,$dst" %}
7539 opcode(Assembler::sll_op3, Assembler::arith_op);
7540 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7541 ins_pipe(ialu_reg_imm);
7542 %}
7543
7544 // Register Shift Left
7545 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7546 match(Set dst (LShiftL src1 src2));
7547
7548 size(4);
7549 format %{ "SLLX $src1,$src2,$dst" %}
7550 opcode(Assembler::sllx_op3, Assembler::arith_op);
7551 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7552 ins_pipe(ialu_reg_reg);
7553 %}
7554
7555 // Register Shift Left Immediate
7556 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7557 match(Set dst (LShiftL src1 src2));
7558
7559 size(4);
7560 format %{ "SLLX $src1,$src2,$dst" %}
7561 opcode(Assembler::sllx_op3, Assembler::arith_op);
7562 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7563 ins_pipe(ialu_reg_imm);
7564 %}
7565
7566 // Register Arithmetic Shift Right
7567 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7568 match(Set dst (RShiftI src1 src2));
7569 size(4);
7570 format %{ "SRA $src1,$src2,$dst" %}
7571 opcode(Assembler::sra_op3, Assembler::arith_op);
7572 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7573 ins_pipe(ialu_reg_reg);
7574 %}
7575
7576 // Register Arithmetic Shift Right Immediate
7577 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7578 match(Set dst (RShiftI src1 src2));
7579
7580 size(4);
7581 format %{ "SRA $src1,$src2,$dst" %}
7582 opcode(Assembler::sra_op3, Assembler::arith_op);
7583 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7584 ins_pipe(ialu_reg_imm);
7585 %}
7586
7587 // Register Shift Right Arithmatic Long
7588 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7589 match(Set dst (RShiftL src1 src2));
7590
7591 size(4);
7592 format %{ "SRAX $src1,$src2,$dst" %}
7593 opcode(Assembler::srax_op3, Assembler::arith_op);
7594 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7595 ins_pipe(ialu_reg_reg);
7596 %}
7597
7598 // Register Shift Left Immediate
7599 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7600 match(Set dst (RShiftL src1 src2));
7601
7602 size(4);
7603 format %{ "SRAX $src1,$src2,$dst" %}
7604 opcode(Assembler::srax_op3, Assembler::arith_op);
7605 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7606 ins_pipe(ialu_reg_imm);
7607 %}
7608
7609 // Register Shift Right
7610 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7611 match(Set dst (URShiftI src1 src2));
7612
7613 size(4);
7614 format %{ "SRL $src1,$src2,$dst" %}
7615 opcode(Assembler::srl_op3, Assembler::arith_op);
7616 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7617 ins_pipe(ialu_reg_reg);
7618 %}
7619
7620 // Register Shift Right Immediate
7621 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7622 match(Set dst (URShiftI src1 src2));
7623
7624 size(4);
7625 format %{ "SRL $src1,$src2,$dst" %}
7626 opcode(Assembler::srl_op3, Assembler::arith_op);
7627 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7628 ins_pipe(ialu_reg_imm);
7629 %}
7630
7631 // Register Shift Right
7632 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7633 match(Set dst (URShiftL src1 src2));
7634
7635 size(4);
7636 format %{ "SRLX $src1,$src2,$dst" %}
7637 opcode(Assembler::srlx_op3, Assembler::arith_op);
7638 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7639 ins_pipe(ialu_reg_reg);
7640 %}
7641
7642 // Register Shift Right Immediate
7643 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7644 match(Set dst (URShiftL src1 src2));
7645
7646 size(4);
7647 format %{ "SRLX $src1,$src2,$dst" %}
7648 opcode(Assembler::srlx_op3, Assembler::arith_op);
7649 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7650 ins_pipe(ialu_reg_imm);
7651 %}
7652
7653 // Register Shift Right Immediate with a CastP2X
7654 #ifdef _LP64
7655 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7656 match(Set dst (URShiftL (CastP2X src1) src2));
7657 size(4);
7658 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7659 opcode(Assembler::srlx_op3, Assembler::arith_op);
7660 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7661 ins_pipe(ialu_reg_imm);
7662 %}
7663 #else
7664 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7665 match(Set dst (URShiftI (CastP2X src1) src2));
7666 size(4);
7667 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7668 opcode(Assembler::srl_op3, Assembler::arith_op);
7669 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7670 ins_pipe(ialu_reg_imm);
7671 %}
7672 #endif
7673
7674
7675 //----------Floating Point Arithmetic Instructions-----------------------------
7676
7677 // Add float single precision
7678 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7679 match(Set dst (AddF src1 src2));
7680
7681 size(4);
7682 format %{ "FADDS $src1,$src2,$dst" %}
7683 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7684 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7685 ins_pipe(faddF_reg_reg);
7686 %}
7687
7688 // Add float double precision
7689 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7690 match(Set dst (AddD src1 src2));
7691
7692 size(4);
7693 format %{ "FADDD $src1,$src2,$dst" %}
7694 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7695 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7696 ins_pipe(faddD_reg_reg);
7697 %}
7698
7699 // Sub float single precision
7700 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7701 match(Set dst (SubF src1 src2));
7702
7703 size(4);
7704 format %{ "FSUBS $src1,$src2,$dst" %}
7705 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7706 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7707 ins_pipe(faddF_reg_reg);
7708 %}
7709
7710 // Sub float double precision
7711 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7712 match(Set dst (SubD src1 src2));
7713
7714 size(4);
7715 format %{ "FSUBD $src1,$src2,$dst" %}
7716 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7717 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7718 ins_pipe(faddD_reg_reg);
7719 %}
7720
7721 // Mul float single precision
7722 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7723 match(Set dst (MulF src1 src2));
7724
7725 size(4);
7726 format %{ "FMULS $src1,$src2,$dst" %}
7727 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7728 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7729 ins_pipe(fmulF_reg_reg);
7730 %}
7731
7732 // Mul float double precision
7733 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7734 match(Set dst (MulD src1 src2));
7735
7736 size(4);
7737 format %{ "FMULD $src1,$src2,$dst" %}
7738 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7739 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7740 ins_pipe(fmulD_reg_reg);
7741 %}
7742
7743 // Div float single precision
7744 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7745 match(Set dst (DivF src1 src2));
7746
7747 size(4);
7748 format %{ "FDIVS $src1,$src2,$dst" %}
7749 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7750 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7751 ins_pipe(fdivF_reg_reg);
7752 %}
7753
7754 // Div float double precision
7755 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7756 match(Set dst (DivD src1 src2));
7757
7758 size(4);
7759 format %{ "FDIVD $src1,$src2,$dst" %}
7760 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7761 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7762 ins_pipe(fdivD_reg_reg);
7763 %}
7764
7765 // Absolute float double precision
7766 instruct absD_reg(regD dst, regD src) %{
7767 match(Set dst (AbsD src));
7768
7769 format %{ "FABSd $src,$dst" %}
7770 ins_encode(fabsd(dst, src));
7771 ins_pipe(faddD_reg);
7772 %}
7773
7774 // Absolute float single precision
7775 instruct absF_reg(regF dst, regF src) %{
7776 match(Set dst (AbsF src));
7777
7778 format %{ "FABSs $src,$dst" %}
7779 ins_encode(fabss(dst, src));
7780 ins_pipe(faddF_reg);
7781 %}
7782
7783 instruct negF_reg(regF dst, regF src) %{
7784 match(Set dst (NegF src));
7785
7786 size(4);
7787 format %{ "FNEGs $src,$dst" %}
7788 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7789 ins_encode(form3_opf_rs2F_rdF(src, dst));
7790 ins_pipe(faddF_reg);
7791 %}
7792
7793 instruct negD_reg(regD dst, regD src) %{
7794 match(Set dst (NegD src));
7795
7796 format %{ "FNEGd $src,$dst" %}
7797 ins_encode(fnegd(dst, src));
7798 ins_pipe(faddD_reg);
7799 %}
7800
7801 // Sqrt float double precision
7802 instruct sqrtF_reg_reg(regF dst, regF src) %{
7803 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7804
7805 size(4);
7806 format %{ "FSQRTS $src,$dst" %}
7807 ins_encode(fsqrts(dst, src));
7808 ins_pipe(fdivF_reg_reg);
7809 %}
7810
7811 // Sqrt float double precision
7812 instruct sqrtD_reg_reg(regD dst, regD src) %{
7813 match(Set dst (SqrtD src));
7814
7815 size(4);
7816 format %{ "FSQRTD $src,$dst" %}
7817 ins_encode(fsqrtd(dst, src));
7818 ins_pipe(fdivD_reg_reg);
7819 %}
7820
7821 //----------Logical Instructions-----------------------------------------------
7822 // And Instructions
7823 // Register And
7824 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7825 match(Set dst (AndI src1 src2));
7826
7827 size(4);
7828 format %{ "AND $src1,$src2,$dst" %}
7829 opcode(Assembler::and_op3, Assembler::arith_op);
7830 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7831 ins_pipe(ialu_reg_reg);
7832 %}
7833
7834 // Immediate And
7835 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7836 match(Set dst (AndI src1 src2));
7837
7838 size(4);
7839 format %{ "AND $src1,$src2,$dst" %}
7840 opcode(Assembler::and_op3, Assembler::arith_op);
7841 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7842 ins_pipe(ialu_reg_imm);
7843 %}
7844
7845 // Register And Long
7846 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7847 match(Set dst (AndL src1 src2));
7848
7849 ins_cost(DEFAULT_COST);
7850 size(4);
7851 format %{ "AND $src1,$src2,$dst\t! long" %}
7852 opcode(Assembler::and_op3, Assembler::arith_op);
7853 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7854 ins_pipe(ialu_reg_reg);
7855 %}
7856
7857 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7858 match(Set dst (AndL src1 con));
7859
7860 ins_cost(DEFAULT_COST);
7861 size(4);
7862 format %{ "AND $src1,$con,$dst\t! long" %}
7863 opcode(Assembler::and_op3, Assembler::arith_op);
7864 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7865 ins_pipe(ialu_reg_imm);
7866 %}
7867
7868 // Or Instructions
7869 // Register Or
7870 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7871 match(Set dst (OrI src1 src2));
7872
7873 size(4);
7874 format %{ "OR $src1,$src2,$dst" %}
7875 opcode(Assembler::or_op3, Assembler::arith_op);
7876 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7877 ins_pipe(ialu_reg_reg);
7878 %}
7879
7880 // Immediate Or
7881 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7882 match(Set dst (OrI src1 src2));
7883
7884 size(4);
7885 format %{ "OR $src1,$src2,$dst" %}
7886 opcode(Assembler::or_op3, Assembler::arith_op);
7887 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7888 ins_pipe(ialu_reg_imm);
7889 %}
7890
7891 // Register Or Long
7892 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7893 match(Set dst (OrL src1 src2));
7894
7895 ins_cost(DEFAULT_COST);
7896 size(4);
7897 format %{ "OR $src1,$src2,$dst\t! long" %}
7898 opcode(Assembler::or_op3, Assembler::arith_op);
7899 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7900 ins_pipe(ialu_reg_reg);
7901 %}
7902
7903 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7904 match(Set dst (OrL src1 con));
7905 ins_cost(DEFAULT_COST*2);
7906
7907 ins_cost(DEFAULT_COST);
7908 size(4);
7909 format %{ "OR $src1,$con,$dst\t! long" %}
7910 opcode(Assembler::or_op3, Assembler::arith_op);
7911 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7912 ins_pipe(ialu_reg_imm);
7913 %}
7914
7915 #ifndef _LP64
7916
7917 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7918 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7919 match(Set dst (OrI src1 (CastP2X src2)));
7920
7921 size(4);
7922 format %{ "OR $src1,$src2,$dst" %}
7923 opcode(Assembler::or_op3, Assembler::arith_op);
7924 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7925 ins_pipe(ialu_reg_reg);
7926 %}
7927
7928 #else
7929
7930 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7931 match(Set dst (OrL src1 (CastP2X src2)));
7932
7933 ins_cost(DEFAULT_COST);
7934 size(4);
7935 format %{ "OR $src1,$src2,$dst\t! long" %}
7936 opcode(Assembler::or_op3, Assembler::arith_op);
7937 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7938 ins_pipe(ialu_reg_reg);
7939 %}
7940
7941 #endif
7942
7943 // Xor Instructions
7944 // Register Xor
7945 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7946 match(Set dst (XorI src1 src2));
7947
7948 size(4);
7949 format %{ "XOR $src1,$src2,$dst" %}
7950 opcode(Assembler::xor_op3, Assembler::arith_op);
7951 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7952 ins_pipe(ialu_reg_reg);
7953 %}
7954
7955 // Immediate Xor
7956 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7957 match(Set dst (XorI src1 src2));
7958
7959 size(4);
7960 format %{ "XOR $src1,$src2,$dst" %}
7961 opcode(Assembler::xor_op3, Assembler::arith_op);
7962 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7963 ins_pipe(ialu_reg_imm);
7964 %}
7965
7966 // Register Xor Long
7967 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7968 match(Set dst (XorL src1 src2));
7969
7970 ins_cost(DEFAULT_COST);
7971 size(4);
7972 format %{ "XOR $src1,$src2,$dst\t! long" %}
7973 opcode(Assembler::xor_op3, Assembler::arith_op);
7974 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7975 ins_pipe(ialu_reg_reg);
7976 %}
7977
7978 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7979 match(Set dst (XorL src1 con));
7980
7981 ins_cost(DEFAULT_COST);
7982 size(4);
7983 format %{ "XOR $src1,$con,$dst\t! long" %}
7984 opcode(Assembler::xor_op3, Assembler::arith_op);
7985 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7986 ins_pipe(ialu_reg_imm);
7987 %}
7988
7989 //----------Convert to Boolean-------------------------------------------------
7990 // Nice hack for 32-bit tests but doesn't work for
7991 // 64-bit pointers.
7992 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7993 match(Set dst (Conv2B src));
7994 effect( KILL ccr );
7995 ins_cost(DEFAULT_COST*2);
7996 format %{ "CMP R_G0,$src\n\t"
7997 "ADDX R_G0,0,$dst" %}
7998 ins_encode( enc_to_bool( src, dst ) );
7999 ins_pipe(ialu_reg_ialu);
8000 %}
8001
8002 #ifndef _LP64
8003 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8004 match(Set dst (Conv2B src));
8005 effect( KILL ccr );
8006 ins_cost(DEFAULT_COST*2);
8007 format %{ "CMP R_G0,$src\n\t"
8008 "ADDX R_G0,0,$dst" %}
8009 ins_encode( enc_to_bool( src, dst ) );
8010 ins_pipe(ialu_reg_ialu);
8011 %}
8012 #else
8013 instruct convP2B( iRegI dst, iRegP src ) %{
8014 match(Set dst (Conv2B src));
8015 ins_cost(DEFAULT_COST*2);
8016 format %{ "MOV $src,$dst\n\t"
8017 "MOVRNZ $src,1,$dst" %}
8018 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8019 ins_pipe(ialu_clr_and_mover);
8020 %}
8021 #endif
8022
8023 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8024 match(Set dst (CmpLTMask src zero));
8025 effect(KILL ccr);
8026 size(4);
8027 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8028 ins_encode %{
8029 __ sra($src$$Register, 31, $dst$$Register);
8030 %}
8031 ins_pipe(ialu_reg_imm);
8032 %}
8033
8034 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8035 match(Set dst (CmpLTMask p q));
8036 effect( KILL ccr );
8037 ins_cost(DEFAULT_COST*4);
8038 format %{ "CMP $p,$q\n\t"
8039 "MOV #0,$dst\n\t"
8040 "BLT,a .+8\n\t"
8041 "MOV #-1,$dst" %}
8042 ins_encode( enc_ltmask(p,q,dst) );
8043 ins_pipe(ialu_reg_reg_ialu);
8044 %}
8045
8046 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8047 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8048 effect(KILL ccr, TEMP tmp);
8049 ins_cost(DEFAULT_COST*3);
8050
8051 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8052 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8053 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8054 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8055 ins_pipe(cadd_cmpltmask);
8056 %}
8057
8058 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8059 match(Set p (AndI (CmpLTMask p q) y));
8060 effect(KILL ccr);
8061 ins_cost(DEFAULT_COST*3);
8062
8063 format %{ "CMP $p,$q\n\t"
8064 "MOV $y,$p\n\t"
8065 "MOVge G0,$p" %}
8066 ins_encode %{
8067 __ cmp($p$$Register, $q$$Register);
8068 __ mov($y$$Register, $p$$Register);
8069 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8070 %}
8071 ins_pipe(ialu_reg_reg_ialu);
8072 %}
8073
8074 //-----------------------------------------------------------------
8075 // Direct raw moves between float and general registers using VIS3.
8076
8077 // ins_pipe(faddF_reg);
8078 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8079 predicate(UseVIS >= 3);
8080 match(Set dst (MoveF2I src));
8081
8082 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8083 ins_encode %{
8084 __ movstouw($src$$FloatRegister, $dst$$Register);
8085 %}
8086 ins_pipe(ialu_reg_reg);
8087 %}
8088
8089 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8090 predicate(UseVIS >= 3);
8091 match(Set dst (MoveI2F src));
8092
8093 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8094 ins_encode %{
8095 __ movwtos($src$$Register, $dst$$FloatRegister);
8096 %}
8097 ins_pipe(ialu_reg_reg);
8098 %}
8099
8100 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8101 predicate(UseVIS >= 3);
8102 match(Set dst (MoveD2L src));
8103
8104 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8105 ins_encode %{
8106 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8107 %}
8108 ins_pipe(ialu_reg_reg);
8109 %}
8110
8111 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8112 predicate(UseVIS >= 3);
8113 match(Set dst (MoveL2D src));
8114
8115 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8116 ins_encode %{
8117 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8118 %}
8119 ins_pipe(ialu_reg_reg);
8120 %}
8121
8122
8123 // Raw moves between float and general registers using stack.
8124
8125 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8126 match(Set dst (MoveF2I src));
8127 effect(DEF dst, USE src);
8128 ins_cost(MEMORY_REF_COST);
8129
8130 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8131 opcode(Assembler::lduw_op3);
8132 ins_encode(simple_form3_mem_reg( src, dst ) );
8133 ins_pipe(iload_mem);
8134 %}
8135
8136 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8137 match(Set dst (MoveI2F src));
8138 effect(DEF dst, USE src);
8139 ins_cost(MEMORY_REF_COST);
8140
8141 format %{ "LDF $src,$dst\t! MoveI2F" %}
8142 opcode(Assembler::ldf_op3);
8143 ins_encode(simple_form3_mem_reg(src, dst));
8144 ins_pipe(floadF_stk);
8145 %}
8146
8147 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8148 match(Set dst (MoveD2L src));
8149 effect(DEF dst, USE src);
8150 ins_cost(MEMORY_REF_COST);
8151
8152 format %{ "LDX $src,$dst\t! MoveD2L" %}
8153 opcode(Assembler::ldx_op3);
8154 ins_encode(simple_form3_mem_reg( src, dst ) );
8155 ins_pipe(iload_mem);
8156 %}
8157
8158 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8159 match(Set dst (MoveL2D src));
8160 effect(DEF dst, USE src);
8161 ins_cost(MEMORY_REF_COST);
8162
8163 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8164 opcode(Assembler::lddf_op3);
8165 ins_encode(simple_form3_mem_reg(src, dst));
8166 ins_pipe(floadD_stk);
8167 %}
8168
8169 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8170 match(Set dst (MoveF2I src));
8171 effect(DEF dst, USE src);
8172 ins_cost(MEMORY_REF_COST);
8173
8174 format %{ "STF $src,$dst\t! MoveF2I" %}
8175 opcode(Assembler::stf_op3);
8176 ins_encode(simple_form3_mem_reg(dst, src));
8177 ins_pipe(fstoreF_stk_reg);
8178 %}
8179
8180 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8181 match(Set dst (MoveI2F src));
8182 effect(DEF dst, USE src);
8183 ins_cost(MEMORY_REF_COST);
8184
8185 format %{ "STW $src,$dst\t! MoveI2F" %}
8186 opcode(Assembler::stw_op3);
8187 ins_encode(simple_form3_mem_reg( dst, src ) );
8188 ins_pipe(istore_mem_reg);
8189 %}
8190
8191 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8192 match(Set dst (MoveD2L src));
8193 effect(DEF dst, USE src);
8194 ins_cost(MEMORY_REF_COST);
8195
8196 format %{ "STDF $src,$dst\t! MoveD2L" %}
8197 opcode(Assembler::stdf_op3);
8198 ins_encode(simple_form3_mem_reg(dst, src));
8199 ins_pipe(fstoreD_stk_reg);
8200 %}
8201
8202 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8203 match(Set dst (MoveL2D src));
8204 effect(DEF dst, USE src);
8205 ins_cost(MEMORY_REF_COST);
8206
8207 format %{ "STX $src,$dst\t! MoveL2D" %}
8208 opcode(Assembler::stx_op3);
8209 ins_encode(simple_form3_mem_reg( dst, src ) );
8210 ins_pipe(istore_mem_reg);
8211 %}
8212
8213
8214 //----------Arithmetic Conversion Instructions---------------------------------
8215 // The conversions operations are all Alpha sorted. Please keep it that way!
8216
8217 instruct convD2F_reg(regF dst, regD src) %{
8218 match(Set dst (ConvD2F src));
8219 size(4);
8220 format %{ "FDTOS $src,$dst" %}
8221 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8222 ins_encode(form3_opf_rs2D_rdF(src, dst));
8223 ins_pipe(fcvtD2F);
8224 %}
8225
8226
8227 // Convert a double to an int in a float register.
8228 // If the double is a NAN, stuff a zero in instead.
8229 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8230 effect(DEF dst, USE src, KILL fcc0);
8231 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8232 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8233 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8234 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8235 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8236 "skip:" %}
8237 ins_encode(form_d2i_helper(src,dst));
8238 ins_pipe(fcvtD2I);
8239 %}
8240
8241 instruct convD2I_stk(stackSlotI dst, regD src) %{
8242 match(Set dst (ConvD2I src));
8243 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8244 expand %{
8245 regF tmp;
8246 convD2I_helper(tmp, src);
8247 regF_to_stkI(dst, tmp);
8248 %}
8249 %}
8250
8251 instruct convD2I_reg(iRegI dst, regD src) %{
8252 predicate(UseVIS >= 3);
8253 match(Set dst (ConvD2I src));
8254 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8255 expand %{
8256 regF tmp;
8257 convD2I_helper(tmp, src);
8258 MoveF2I_reg_reg(dst, tmp);
8259 %}
8260 %}
8261
8262
8263 // Convert a double to a long in a double register.
8264 // If the double is a NAN, stuff a zero in instead.
8265 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8266 effect(DEF dst, USE src, KILL fcc0);
8267 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8268 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8269 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8270 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8271 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8272 "skip:" %}
8273 ins_encode(form_d2l_helper(src,dst));
8274 ins_pipe(fcvtD2L);
8275 %}
8276
8277 instruct convD2L_stk(stackSlotL dst, regD src) %{
8278 match(Set dst (ConvD2L src));
8279 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8280 expand %{
8281 regD tmp;
8282 convD2L_helper(tmp, src);
8283 regD_to_stkL(dst, tmp);
8284 %}
8285 %}
8286
8287 instruct convD2L_reg(iRegL dst, regD src) %{
8288 predicate(UseVIS >= 3);
8289 match(Set dst (ConvD2L src));
8290 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8291 expand %{
8292 regD tmp;
8293 convD2L_helper(tmp, src);
8294 MoveD2L_reg_reg(dst, tmp);
8295 %}
8296 %}
8297
8298
8299 instruct convF2D_reg(regD dst, regF src) %{
8300 match(Set dst (ConvF2D src));
8301 format %{ "FSTOD $src,$dst" %}
8302 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8303 ins_encode(form3_opf_rs2F_rdD(src, dst));
8304 ins_pipe(fcvtF2D);
8305 %}
8306
8307
8308 // Convert a float to an int in a float register.
8309 // If the float is a NAN, stuff a zero in instead.
8310 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8311 effect(DEF dst, USE src, KILL fcc0);
8312 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8313 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8314 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8315 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8316 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8317 "skip:" %}
8318 ins_encode(form_f2i_helper(src,dst));
8319 ins_pipe(fcvtF2I);
8320 %}
8321
8322 instruct convF2I_stk(stackSlotI dst, regF src) %{
8323 match(Set dst (ConvF2I src));
8324 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8325 expand %{
8326 regF tmp;
8327 convF2I_helper(tmp, src);
8328 regF_to_stkI(dst, tmp);
8329 %}
8330 %}
8331
8332 instruct convF2I_reg(iRegI dst, regF src) %{
8333 predicate(UseVIS >= 3);
8334 match(Set dst (ConvF2I src));
8335 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8336 expand %{
8337 regF tmp;
8338 convF2I_helper(tmp, src);
8339 MoveF2I_reg_reg(dst, tmp);
8340 %}
8341 %}
8342
8343
8344 // Convert a float to a long in a float register.
8345 // If the float is a NAN, stuff a zero in instead.
8346 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8347 effect(DEF dst, USE src, KILL fcc0);
8348 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8349 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8350 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8351 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8352 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8353 "skip:" %}
8354 ins_encode(form_f2l_helper(src,dst));
8355 ins_pipe(fcvtF2L);
8356 %}
8357
8358 instruct convF2L_stk(stackSlotL dst, regF src) %{
8359 match(Set dst (ConvF2L src));
8360 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8361 expand %{
8362 regD tmp;
8363 convF2L_helper(tmp, src);
8364 regD_to_stkL(dst, tmp);
8365 %}
8366 %}
8367
8368 instruct convF2L_reg(iRegL dst, regF src) %{
8369 predicate(UseVIS >= 3);
8370 match(Set dst (ConvF2L src));
8371 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8372 expand %{
8373 regD tmp;
8374 convF2L_helper(tmp, src);
8375 MoveD2L_reg_reg(dst, tmp);
8376 %}
8377 %}
8378
8379
8380 instruct convI2D_helper(regD dst, regF tmp) %{
8381 effect(USE tmp, DEF dst);
8382 format %{ "FITOD $tmp,$dst" %}
8383 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8384 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8385 ins_pipe(fcvtI2D);
8386 %}
8387
8388 instruct convI2D_stk(stackSlotI src, regD dst) %{
8389 match(Set dst (ConvI2D src));
8390 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8391 expand %{
8392 regF tmp;
8393 stkI_to_regF(tmp, src);
8394 convI2D_helper(dst, tmp);
8395 %}
8396 %}
8397
8398 instruct convI2D_reg(regD_low dst, iRegI src) %{
8399 predicate(UseVIS >= 3);
8400 match(Set dst (ConvI2D src));
8401 expand %{
8402 regF tmp;
8403 MoveI2F_reg_reg(tmp, src);
8404 convI2D_helper(dst, tmp);
8405 %}
8406 %}
8407
8408 instruct convI2D_mem(regD_low dst, memory mem) %{
8409 match(Set dst (ConvI2D (LoadI mem)));
8410 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8411 format %{ "LDF $mem,$dst\n\t"
8412 "FITOD $dst,$dst" %}
8413 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8414 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8415 ins_pipe(floadF_mem);
8416 %}
8417
8418
8419 instruct convI2F_helper(regF dst, regF tmp) %{
8420 effect(DEF dst, USE tmp);
8421 format %{ "FITOS $tmp,$dst" %}
8422 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8423 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8424 ins_pipe(fcvtI2F);
8425 %}
8426
8427 instruct convI2F_stk(regF dst, stackSlotI src) %{
8428 match(Set dst (ConvI2F src));
8429 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8430 expand %{
8431 regF tmp;
8432 stkI_to_regF(tmp,src);
8433 convI2F_helper(dst, tmp);
8434 %}
8435 %}
8436
8437 instruct convI2F_reg(regF dst, iRegI src) %{
8438 predicate(UseVIS >= 3);
8439 match(Set dst (ConvI2F src));
8440 ins_cost(DEFAULT_COST);
8441 expand %{
8442 regF tmp;
8443 MoveI2F_reg_reg(tmp, src);
8444 convI2F_helper(dst, tmp);
8445 %}
8446 %}
8447
8448 instruct convI2F_mem( regF dst, memory mem ) %{
8449 match(Set dst (ConvI2F (LoadI mem)));
8450 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8451 format %{ "LDF $mem,$dst\n\t"
8452 "FITOS $dst,$dst" %}
8453 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8454 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8455 ins_pipe(floadF_mem);
8456 %}
8457
8458
8459 instruct convI2L_reg(iRegL dst, iRegI src) %{
8460 match(Set dst (ConvI2L src));
8461 size(4);
8462 format %{ "SRA $src,0,$dst\t! int->long" %}
8463 opcode(Assembler::sra_op3, Assembler::arith_op);
8464 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8465 ins_pipe(ialu_reg_reg);
8466 %}
8467
8468 // Zero-extend convert int to long
8469 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8470 match(Set dst (AndL (ConvI2L src) mask) );
8471 size(4);
8472 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8473 opcode(Assembler::srl_op3, Assembler::arith_op);
8474 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8475 ins_pipe(ialu_reg_reg);
8476 %}
8477
8478 // Zero-extend long
8479 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8480 match(Set dst (AndL src mask) );
8481 size(4);
8482 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8483 opcode(Assembler::srl_op3, Assembler::arith_op);
8484 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8485 ins_pipe(ialu_reg_reg);
8486 %}
8487
8488
8489 //-----------
8490 // Long to Double conversion using V8 opcodes.
8491 // Still useful because cheetah traps and becomes
8492 // amazingly slow for some common numbers.
8493
8494 // Magic constant, 0x43300000
8495 instruct loadConI_x43300000(iRegI dst) %{
8496 effect(DEF dst);
8497 size(4);
8498 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8499 ins_encode(SetHi22(0x43300000, dst));
8500 ins_pipe(ialu_none);
8501 %}
8502
8503 // Magic constant, 0x41f00000
8504 instruct loadConI_x41f00000(iRegI dst) %{
8505 effect(DEF dst);
8506 size(4);
8507 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8508 ins_encode(SetHi22(0x41f00000, dst));
8509 ins_pipe(ialu_none);
8510 %}
8511
8512 // Construct a double from two float halves
8513 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8514 effect(DEF dst, USE src1, USE src2);
8515 size(8);
8516 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8517 "FMOVS $src2.lo,$dst.lo" %}
8518 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8519 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8520 ins_pipe(faddD_reg_reg);
8521 %}
8522
8523 // Convert integer in high half of a double register (in the lower half of
8524 // the double register file) to double
8525 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8526 effect(DEF dst, USE src);
8527 size(4);
8528 format %{ "FITOD $src,$dst" %}
8529 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8530 ins_encode(form3_opf_rs2D_rdD(src, dst));
8531 ins_pipe(fcvtLHi2D);
8532 %}
8533
8534 // Add float double precision
8535 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8536 effect(DEF dst, USE src1, USE src2);
8537 size(4);
8538 format %{ "FADDD $src1,$src2,$dst" %}
8539 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8540 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8541 ins_pipe(faddD_reg_reg);
8542 %}
8543
8544 // Sub float double precision
8545 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8546 effect(DEF dst, USE src1, USE src2);
8547 size(4);
8548 format %{ "FSUBD $src1,$src2,$dst" %}
8549 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8550 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8551 ins_pipe(faddD_reg_reg);
8552 %}
8553
8554 // Mul float double precision
8555 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8556 effect(DEF dst, USE src1, USE src2);
8557 size(4);
8558 format %{ "FMULD $src1,$src2,$dst" %}
8559 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8560 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8561 ins_pipe(fmulD_reg_reg);
8562 %}
8563
8564 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8565 match(Set dst (ConvL2D src));
8566 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8567
8568 expand %{
8569 regD_low tmpsrc;
8570 iRegI ix43300000;
8571 iRegI ix41f00000;
8572 stackSlotL lx43300000;
8573 stackSlotL lx41f00000;
8574 regD_low dx43300000;
8575 regD dx41f00000;
8576 regD tmp1;
8577 regD_low tmp2;
8578 regD tmp3;
8579 regD tmp4;
8580
8581 stkL_to_regD(tmpsrc, src);
8582
8583 loadConI_x43300000(ix43300000);
8584 loadConI_x41f00000(ix41f00000);
8585 regI_to_stkLHi(lx43300000, ix43300000);
8586 regI_to_stkLHi(lx41f00000, ix41f00000);
8587 stkL_to_regD(dx43300000, lx43300000);
8588 stkL_to_regD(dx41f00000, lx41f00000);
8589
8590 convI2D_regDHi_regD(tmp1, tmpsrc);
8591 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8592 subD_regD_regD(tmp3, tmp2, dx43300000);
8593 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8594 addD_regD_regD(dst, tmp3, tmp4);
8595 %}
8596 %}
8597
8598 // Long to Double conversion using fast fxtof
8599 instruct convL2D_helper(regD dst, regD tmp) %{
8600 effect(DEF dst, USE tmp);
8601 size(4);
8602 format %{ "FXTOD $tmp,$dst" %}
8603 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8604 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8605 ins_pipe(fcvtL2D);
8606 %}
8607
8608 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8609 predicate(VM_Version::has_fast_fxtof());
8610 match(Set dst (ConvL2D src));
8611 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8612 expand %{
8613 regD tmp;
8614 stkL_to_regD(tmp, src);
8615 convL2D_helper(dst, tmp);
8616 %}
8617 %}
8618
8619 instruct convL2D_reg(regD dst, iRegL src) %{
8620 predicate(UseVIS >= 3);
8621 match(Set dst (ConvL2D src));
8622 expand %{
8623 regD tmp;
8624 MoveL2D_reg_reg(tmp, src);
8625 convL2D_helper(dst, tmp);
8626 %}
8627 %}
8628
8629 // Long to Float conversion using fast fxtof
8630 instruct convL2F_helper(regF dst, regD tmp) %{
8631 effect(DEF dst, USE tmp);
8632 size(4);
8633 format %{ "FXTOS $tmp,$dst" %}
8634 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8635 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8636 ins_pipe(fcvtL2F);
8637 %}
8638
8639 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8640 match(Set dst (ConvL2F src));
8641 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8642 expand %{
8643 regD tmp;
8644 stkL_to_regD(tmp, src);
8645 convL2F_helper(dst, tmp);
8646 %}
8647 %}
8648
8649 instruct convL2F_reg(regF dst, iRegL src) %{
8650 predicate(UseVIS >= 3);
8651 match(Set dst (ConvL2F src));
8652 ins_cost(DEFAULT_COST);
8653 expand %{
8654 regD tmp;
8655 MoveL2D_reg_reg(tmp, src);
8656 convL2F_helper(dst, tmp);
8657 %}
8658 %}
8659
8660 //-----------
8661
8662 instruct convL2I_reg(iRegI dst, iRegL src) %{
8663 match(Set dst (ConvL2I src));
8664 #ifndef _LP64
8665 format %{ "MOV $src.lo,$dst\t! long->int" %}
8666 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8667 ins_pipe(ialu_move_reg_I_to_L);
8668 #else
8669 size(4);
8670 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8671 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8672 ins_pipe(ialu_reg);
8673 #endif
8674 %}
8675
8676 // Register Shift Right Immediate
8677 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8678 match(Set dst (ConvL2I (RShiftL src cnt)));
8679
8680 size(4);
8681 format %{ "SRAX $src,$cnt,$dst" %}
8682 opcode(Assembler::srax_op3, Assembler::arith_op);
8683 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8684 ins_pipe(ialu_reg_imm);
8685 %}
8686
8687 //----------Control Flow Instructions------------------------------------------
8688 // Compare Instructions
8689 // Compare Integers
8690 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8691 match(Set icc (CmpI op1 op2));
8692 effect( DEF icc, USE op1, USE op2 );
8693
8694 size(4);
8695 format %{ "CMP $op1,$op2" %}
8696 opcode(Assembler::subcc_op3, Assembler::arith_op);
8697 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8698 ins_pipe(ialu_cconly_reg_reg);
8699 %}
8700
8701 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8702 match(Set icc (CmpU op1 op2));
8703
8704 size(4);
8705 format %{ "CMP $op1,$op2\t! unsigned" %}
8706 opcode(Assembler::subcc_op3, Assembler::arith_op);
8707 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8708 ins_pipe(ialu_cconly_reg_reg);
8709 %}
8710
8711 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8712 match(Set icc (CmpI op1 op2));
8713 effect( DEF icc, USE op1 );
8714
8715 size(4);
8716 format %{ "CMP $op1,$op2" %}
8717 opcode(Assembler::subcc_op3, Assembler::arith_op);
8718 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8719 ins_pipe(ialu_cconly_reg_imm);
8720 %}
8721
8722 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8723 match(Set icc (CmpI (AndI op1 op2) zero));
8724
8725 size(4);
8726 format %{ "BTST $op2,$op1" %}
8727 opcode(Assembler::andcc_op3, Assembler::arith_op);
8728 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8729 ins_pipe(ialu_cconly_reg_reg_zero);
8730 %}
8731
8732 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8733 match(Set icc (CmpI (AndI op1 op2) zero));
8734
8735 size(4);
8736 format %{ "BTST $op2,$op1" %}
8737 opcode(Assembler::andcc_op3, Assembler::arith_op);
8738 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8739 ins_pipe(ialu_cconly_reg_imm_zero);
8740 %}
8741
8742 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8743 match(Set xcc (CmpL op1 op2));
8744 effect( DEF xcc, USE op1, USE op2 );
8745
8746 size(4);
8747 format %{ "CMP $op1,$op2\t\t! long" %}
8748 opcode(Assembler::subcc_op3, Assembler::arith_op);
8749 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8750 ins_pipe(ialu_cconly_reg_reg);
8751 %}
8752
8753 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8754 match(Set xcc (CmpL op1 con));
8755 effect( DEF xcc, USE op1, USE con );
8756
8757 size(4);
8758 format %{ "CMP $op1,$con\t\t! long" %}
8759 opcode(Assembler::subcc_op3, Assembler::arith_op);
8760 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8761 ins_pipe(ialu_cconly_reg_reg);
8762 %}
8763
8764 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8765 match(Set xcc (CmpL (AndL op1 op2) zero));
8766 effect( DEF xcc, USE op1, USE op2 );
8767
8768 size(4);
8769 format %{ "BTST $op1,$op2\t\t! long" %}
8770 opcode(Assembler::andcc_op3, Assembler::arith_op);
8771 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8772 ins_pipe(ialu_cconly_reg_reg);
8773 %}
8774
8775 // useful for checking the alignment of a pointer:
8776 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8777 match(Set xcc (CmpL (AndL op1 con) zero));
8778 effect( DEF xcc, USE op1, USE con );
8779
8780 size(4);
8781 format %{ "BTST $op1,$con\t\t! long" %}
8782 opcode(Assembler::andcc_op3, Assembler::arith_op);
8783 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8784 ins_pipe(ialu_cconly_reg_reg);
8785 %}
8786
8787 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8788 match(Set icc (CmpU op1 op2));
8789
8790 size(4);
8791 format %{ "CMP $op1,$op2\t! unsigned" %}
8792 opcode(Assembler::subcc_op3, Assembler::arith_op);
8793 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8794 ins_pipe(ialu_cconly_reg_imm);
8795 %}
8796
8797 // Compare Pointers
8798 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8799 match(Set pcc (CmpP op1 op2));
8800
8801 size(4);
8802 format %{ "CMP $op1,$op2\t! ptr" %}
8803 opcode(Assembler::subcc_op3, Assembler::arith_op);
8804 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8805 ins_pipe(ialu_cconly_reg_reg);
8806 %}
8807
8808 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8809 match(Set pcc (CmpP op1 op2));
8810
8811 size(4);
8812 format %{ "CMP $op1,$op2\t! ptr" %}
8813 opcode(Assembler::subcc_op3, Assembler::arith_op);
8814 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8815 ins_pipe(ialu_cconly_reg_imm);
8816 %}
8817
8818 // Compare Narrow oops
8819 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8820 match(Set icc (CmpN op1 op2));
8821
8822 size(4);
8823 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8824 opcode(Assembler::subcc_op3, Assembler::arith_op);
8825 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8826 ins_pipe(ialu_cconly_reg_reg);
8827 %}
8828
8829 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8830 match(Set icc (CmpN op1 op2));
8831
8832 size(4);
8833 format %{ "CMP $op1,$op2\t! compressed ptr" %}
8834 opcode(Assembler::subcc_op3, Assembler::arith_op);
8835 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8836 ins_pipe(ialu_cconly_reg_imm);
8837 %}
8838
8839 //----------Max and Min--------------------------------------------------------
8840 // Min Instructions
8841 // Conditional move for min
8842 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8843 effect( USE_DEF op2, USE op1, USE icc );
8844
8845 size(4);
8846 format %{ "MOVlt icc,$op1,$op2\t! min" %}
8847 opcode(Assembler::less);
8848 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8849 ins_pipe(ialu_reg_flags);
8850 %}
8851
8852 // Min Register with Register.
8853 instruct minI_eReg(iRegI op1, iRegI op2) %{
8854 match(Set op2 (MinI op1 op2));
8855 ins_cost(DEFAULT_COST*2);
8856 expand %{
8857 flagsReg icc;
8858 compI_iReg(icc,op1,op2);
8859 cmovI_reg_lt(op2,op1,icc);
8860 %}
8861 %}
8862
8863 // Max Instructions
8864 // Conditional move for max
8865 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8866 effect( USE_DEF op2, USE op1, USE icc );
8867 format %{ "MOVgt icc,$op1,$op2\t! max" %}
8868 opcode(Assembler::greater);
8869 ins_encode( enc_cmov_reg_minmax(op2,op1) );
8870 ins_pipe(ialu_reg_flags);
8871 %}
8872
8873 // Max Register with Register
8874 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8875 match(Set op2 (MaxI op1 op2));
8876 ins_cost(DEFAULT_COST*2);
8877 expand %{
8878 flagsReg icc;
8879 compI_iReg(icc,op1,op2);
8880 cmovI_reg_gt(op2,op1,icc);
8881 %}
8882 %}
8883
8884
8885 //----------Float Compares----------------------------------------------------
8886 // Compare floating, generate condition code
8887 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8888 match(Set fcc (CmpF src1 src2));
8889
8890 size(4);
8891 format %{ "FCMPs $fcc,$src1,$src2" %}
8892 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8893 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8894 ins_pipe(faddF_fcc_reg_reg_zero);
8895 %}
8896
8897 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8898 match(Set fcc (CmpD src1 src2));
8899
8900 size(4);
8901 format %{ "FCMPd $fcc,$src1,$src2" %}
8902 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8903 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8904 ins_pipe(faddD_fcc_reg_reg_zero);
8905 %}
8906
8907
8908 // Compare floating, generate -1,0,1
8909 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8910 match(Set dst (CmpF3 src1 src2));
8911 effect(KILL fcc0);
8912 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8913 format %{ "fcmpl $dst,$src1,$src2" %}
8914 // Primary = float
8915 opcode( true );
8916 ins_encode( floating_cmp( dst, src1, src2 ) );
8917 ins_pipe( floating_cmp );
8918 %}
8919
8920 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8921 match(Set dst (CmpD3 src1 src2));
8922 effect(KILL fcc0);
8923 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8924 format %{ "dcmpl $dst,$src1,$src2" %}
8925 // Primary = double (not float)
8926 opcode( false );
8927 ins_encode( floating_cmp( dst, src1, src2 ) );
8928 ins_pipe( floating_cmp );
8929 %}
8930
8931 //----------Branches---------------------------------------------------------
8932 // Jump
8933 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8934 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8935 match(Jump switch_val);
8936 effect(TEMP table);
8937
8938 ins_cost(350);
8939
8940 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
8941 "LD [O7 + $switch_val], O7\n\t"
8942 "JUMP O7" %}
8943 ins_encode %{
8944 // Calculate table address into a register.
8945 Register table_reg;
8946 Register label_reg = O7;
8947 // If we are calculating the size of this instruction don't trust
8948 // zero offsets because they might change when
8949 // MachConstantBaseNode decides to optimize the constant table
8950 // base.
8951 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8952 table_reg = $constanttablebase;
8953 } else {
8954 table_reg = O7;
8955 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8956 __ add($constanttablebase, con_offset, table_reg);
8957 }
8958
8959 // Jump to base address + switch value
8960 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8961 __ jmp(label_reg, G0);
8962 __ delayed()->nop();
8963 %}
8964 ins_pipe(ialu_reg_reg);
8965 %}
8966
8967 // Direct Branch. Use V8 version with longer range.
8968 instruct branch(label labl) %{
8969 match(Goto);
8970 effect(USE labl);
8971
8972 size(8);
8973 ins_cost(BRANCH_COST);
8974 format %{ "BA $labl" %}
8975 ins_encode %{
8976 Label* L = $labl$$label;
8977 __ ba(*L);
8978 __ delayed()->nop();
8979 %}
8980 ins_avoid_back_to_back(AVOID_BEFORE);
8981 ins_pipe(br);
8982 %}
8983
8984 // Direct Branch, short with no delay slot
8985 instruct branch_short(label labl) %{
8986 match(Goto);
8987 predicate(UseCBCond);
8988 effect(USE labl);
8989
8990 size(4);
8991 ins_cost(BRANCH_COST);
8992 format %{ "BA $labl\t! short branch" %}
8993 ins_encode %{
8994 Label* L = $labl$$label;
8995 assert(__ use_cbcond(*L), "back to back cbcond");
8996 __ ba_short(*L);
8997 %}
8998 ins_short_branch(1);
8999 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9000 ins_pipe(cbcond_reg_imm);
9001 %}
9002
9003 // Conditional Direct Branch
9004 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9005 match(If cmp icc);
9006 effect(USE labl);
9007
9008 size(8);
9009 ins_cost(BRANCH_COST);
9010 format %{ "BP$cmp $icc,$labl" %}
9011 // Prim = bits 24-22, Secnd = bits 31-30
9012 ins_encode( enc_bp( labl, cmp, icc ) );
9013 ins_avoid_back_to_back(AVOID_BEFORE);
9014 ins_pipe(br_cc);
9015 %}
9016
9017 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9018 match(If cmp icc);
9019 effect(USE labl);
9020
9021 ins_cost(BRANCH_COST);
9022 format %{ "BP$cmp $icc,$labl" %}
9023 // Prim = bits 24-22, Secnd = bits 31-30
9024 ins_encode( enc_bp( labl, cmp, icc ) );
9025 ins_avoid_back_to_back(AVOID_BEFORE);
9026 ins_pipe(br_cc);
9027 %}
9028
9029 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9030 match(If cmp pcc);
9031 effect(USE labl);
9032
9033 size(8);
9034 ins_cost(BRANCH_COST);
9035 format %{ "BP$cmp $pcc,$labl" %}
9036 ins_encode %{
9037 Label* L = $labl$$label;
9038 Assembler::Predict predict_taken =
9039 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9040
9041 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9042 __ delayed()->nop();
9043 %}
9044 ins_avoid_back_to_back(AVOID_BEFORE);
9045 ins_pipe(br_cc);
9046 %}
9047
9048 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9049 match(If cmp fcc);
9050 effect(USE labl);
9051
9052 size(8);
9053 ins_cost(BRANCH_COST);
9054 format %{ "FBP$cmp $fcc,$labl" %}
9055 ins_encode %{
9056 Label* L = $labl$$label;
9057 Assembler::Predict predict_taken =
9058 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9059
9060 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9061 __ delayed()->nop();
9062 %}
9063 ins_avoid_back_to_back(AVOID_BEFORE);
9064 ins_pipe(br_fcc);
9065 %}
9066
9067 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9068 match(CountedLoopEnd cmp icc);
9069 effect(USE labl);
9070
9071 size(8);
9072 ins_cost(BRANCH_COST);
9073 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9074 // Prim = bits 24-22, Secnd = bits 31-30
9075 ins_encode( enc_bp( labl, cmp, icc ) );
9076 ins_avoid_back_to_back(AVOID_BEFORE);
9077 ins_pipe(br_cc);
9078 %}
9079
9080 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9081 match(CountedLoopEnd cmp icc);
9082 effect(USE labl);
9083
9084 size(8);
9085 ins_cost(BRANCH_COST);
9086 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9087 // Prim = bits 24-22, Secnd = bits 31-30
9088 ins_encode( enc_bp( labl, cmp, icc ) );
9089 ins_avoid_back_to_back(AVOID_BEFORE);
9090 ins_pipe(br_cc);
9091 %}
9092
9093 // Compare and branch instructions
9094 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9095 match(If cmp (CmpI op1 op2));
9096 effect(USE labl, KILL icc);
9097
9098 size(12);
9099 ins_cost(BRANCH_COST);
9100 format %{ "CMP $op1,$op2\t! int\n\t"
9101 "BP$cmp $labl" %}
9102 ins_encode %{
9103 Label* L = $labl$$label;
9104 Assembler::Predict predict_taken =
9105 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9106 __ cmp($op1$$Register, $op2$$Register);
9107 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9108 __ delayed()->nop();
9109 %}
9110 ins_pipe(cmp_br_reg_reg);
9111 %}
9112
9113 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9114 match(If cmp (CmpI op1 op2));
9115 effect(USE labl, KILL icc);
9116
9117 size(12);
9118 ins_cost(BRANCH_COST);
9119 format %{ "CMP $op1,$op2\t! int\n\t"
9120 "BP$cmp $labl" %}
9121 ins_encode %{
9122 Label* L = $labl$$label;
9123 Assembler::Predict predict_taken =
9124 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9125 __ cmp($op1$$Register, $op2$$constant);
9126 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9127 __ delayed()->nop();
9128 %}
9129 ins_pipe(cmp_br_reg_imm);
9130 %}
9131
9132 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9133 match(If cmp (CmpU op1 op2));
9134 effect(USE labl, KILL icc);
9135
9136 size(12);
9137 ins_cost(BRANCH_COST);
9138 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9139 "BP$cmp $labl" %}
9140 ins_encode %{
9141 Label* L = $labl$$label;
9142 Assembler::Predict predict_taken =
9143 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9144 __ cmp($op1$$Register, $op2$$Register);
9145 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9146 __ delayed()->nop();
9147 %}
9148 ins_pipe(cmp_br_reg_reg);
9149 %}
9150
9151 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9152 match(If cmp (CmpU op1 op2));
9153 effect(USE labl, KILL icc);
9154
9155 size(12);
9156 ins_cost(BRANCH_COST);
9157 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9158 "BP$cmp $labl" %}
9159 ins_encode %{
9160 Label* L = $labl$$label;
9161 Assembler::Predict predict_taken =
9162 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9163 __ cmp($op1$$Register, $op2$$constant);
9164 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9165 __ delayed()->nop();
9166 %}
9167 ins_pipe(cmp_br_reg_imm);
9168 %}
9169
9170 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9171 match(If cmp (CmpL op1 op2));
9172 effect(USE labl, KILL xcc);
9173
9174 size(12);
9175 ins_cost(BRANCH_COST);
9176 format %{ "CMP $op1,$op2\t! long\n\t"
9177 "BP$cmp $labl" %}
9178 ins_encode %{
9179 Label* L = $labl$$label;
9180 Assembler::Predict predict_taken =
9181 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9182 __ cmp($op1$$Register, $op2$$Register);
9183 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9184 __ delayed()->nop();
9185 %}
9186 ins_pipe(cmp_br_reg_reg);
9187 %}
9188
9189 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9190 match(If cmp (CmpL op1 op2));
9191 effect(USE labl, KILL xcc);
9192
9193 size(12);
9194 ins_cost(BRANCH_COST);
9195 format %{ "CMP $op1,$op2\t! long\n\t"
9196 "BP$cmp $labl" %}
9197 ins_encode %{
9198 Label* L = $labl$$label;
9199 Assembler::Predict predict_taken =
9200 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9201 __ cmp($op1$$Register, $op2$$constant);
9202 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9203 __ delayed()->nop();
9204 %}
9205 ins_pipe(cmp_br_reg_imm);
9206 %}
9207
9208 // Compare Pointers and branch
9209 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9210 match(If cmp (CmpP op1 op2));
9211 effect(USE labl, KILL pcc);
9212
9213 size(12);
9214 ins_cost(BRANCH_COST);
9215 format %{ "CMP $op1,$op2\t! ptr\n\t"
9216 "B$cmp $labl" %}
9217 ins_encode %{
9218 Label* L = $labl$$label;
9219 Assembler::Predict predict_taken =
9220 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9221 __ cmp($op1$$Register, $op2$$Register);
9222 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9223 __ delayed()->nop();
9224 %}
9225 ins_pipe(cmp_br_reg_reg);
9226 %}
9227
9228 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9229 match(If cmp (CmpP op1 null));
9230 effect(USE labl, KILL pcc);
9231
9232 size(12);
9233 ins_cost(BRANCH_COST);
9234 format %{ "CMP $op1,0\t! ptr\n\t"
9235 "B$cmp $labl" %}
9236 ins_encode %{
9237 Label* L = $labl$$label;
9238 Assembler::Predict predict_taken =
9239 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9240 __ cmp($op1$$Register, G0);
9241 // bpr() is not used here since it has shorter distance.
9242 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9243 __ delayed()->nop();
9244 %}
9245 ins_pipe(cmp_br_reg_reg);
9246 %}
9247
9248 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9249 match(If cmp (CmpN op1 op2));
9250 effect(USE labl, KILL icc);
9251
9252 size(12);
9253 ins_cost(BRANCH_COST);
9254 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9255 "BP$cmp $labl" %}
9256 ins_encode %{
9257 Label* L = $labl$$label;
9258 Assembler::Predict predict_taken =
9259 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9260 __ cmp($op1$$Register, $op2$$Register);
9261 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9262 __ delayed()->nop();
9263 %}
9264 ins_pipe(cmp_br_reg_reg);
9265 %}
9266
9267 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9268 match(If cmp (CmpN op1 null));
9269 effect(USE labl, KILL icc);
9270
9271 size(12);
9272 ins_cost(BRANCH_COST);
9273 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9274 "BP$cmp $labl" %}
9275 ins_encode %{
9276 Label* L = $labl$$label;
9277 Assembler::Predict predict_taken =
9278 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9279 __ cmp($op1$$Register, G0);
9280 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9281 __ delayed()->nop();
9282 %}
9283 ins_pipe(cmp_br_reg_reg);
9284 %}
9285
9286 // Loop back branch
9287 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9288 match(CountedLoopEnd cmp (CmpI op1 op2));
9289 effect(USE labl, KILL icc);
9290
9291 size(12);
9292 ins_cost(BRANCH_COST);
9293 format %{ "CMP $op1,$op2\t! int\n\t"
9294 "BP$cmp $labl\t! Loop end" %}
9295 ins_encode %{
9296 Label* L = $labl$$label;
9297 Assembler::Predict predict_taken =
9298 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9299 __ cmp($op1$$Register, $op2$$Register);
9300 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9301 __ delayed()->nop();
9302 %}
9303 ins_pipe(cmp_br_reg_reg);
9304 %}
9305
9306 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9307 match(CountedLoopEnd cmp (CmpI op1 op2));
9308 effect(USE labl, KILL icc);
9309
9310 size(12);
9311 ins_cost(BRANCH_COST);
9312 format %{ "CMP $op1,$op2\t! int\n\t"
9313 "BP$cmp $labl\t! Loop end" %}
9314 ins_encode %{
9315 Label* L = $labl$$label;
9316 Assembler::Predict predict_taken =
9317 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9318 __ cmp($op1$$Register, $op2$$constant);
9319 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9320 __ delayed()->nop();
9321 %}
9322 ins_pipe(cmp_br_reg_imm);
9323 %}
9324
9325 // Short compare and branch instructions
9326 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9327 match(If cmp (CmpI op1 op2));
9328 predicate(UseCBCond);
9329 effect(USE labl, KILL icc);
9330
9331 size(4);
9332 ins_cost(BRANCH_COST);
9333 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9334 ins_encode %{
9335 Label* L = $labl$$label;
9336 assert(__ use_cbcond(*L), "back to back cbcond");
9337 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9338 %}
9339 ins_short_branch(1);
9340 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9341 ins_pipe(cbcond_reg_reg);
9342 %}
9343
9344 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9345 match(If cmp (CmpI op1 op2));
9346 predicate(UseCBCond);
9347 effect(USE labl, KILL icc);
9348
9349 size(4);
9350 ins_cost(BRANCH_COST);
9351 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9352 ins_encode %{
9353 Label* L = $labl$$label;
9354 assert(__ use_cbcond(*L), "back to back cbcond");
9355 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9356 %}
9357 ins_short_branch(1);
9358 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9359 ins_pipe(cbcond_reg_imm);
9360 %}
9361
9362 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9363 match(If cmp (CmpU op1 op2));
9364 predicate(UseCBCond);
9365 effect(USE labl, KILL icc);
9366
9367 size(4);
9368 ins_cost(BRANCH_COST);
9369 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9370 ins_encode %{
9371 Label* L = $labl$$label;
9372 assert(__ use_cbcond(*L), "back to back cbcond");
9373 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9374 %}
9375 ins_short_branch(1);
9376 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9377 ins_pipe(cbcond_reg_reg);
9378 %}
9379
9380 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9381 match(If cmp (CmpU op1 op2));
9382 predicate(UseCBCond);
9383 effect(USE labl, KILL icc);
9384
9385 size(4);
9386 ins_cost(BRANCH_COST);
9387 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9388 ins_encode %{
9389 Label* L = $labl$$label;
9390 assert(__ use_cbcond(*L), "back to back cbcond");
9391 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9392 %}
9393 ins_short_branch(1);
9394 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9395 ins_pipe(cbcond_reg_imm);
9396 %}
9397
9398 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9399 match(If cmp (CmpL op1 op2));
9400 predicate(UseCBCond);
9401 effect(USE labl, KILL xcc);
9402
9403 size(4);
9404 ins_cost(BRANCH_COST);
9405 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9406 ins_encode %{
9407 Label* L = $labl$$label;
9408 assert(__ use_cbcond(*L), "back to back cbcond");
9409 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9410 %}
9411 ins_short_branch(1);
9412 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9413 ins_pipe(cbcond_reg_reg);
9414 %}
9415
9416 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9417 match(If cmp (CmpL op1 op2));
9418 predicate(UseCBCond);
9419 effect(USE labl, KILL xcc);
9420
9421 size(4);
9422 ins_cost(BRANCH_COST);
9423 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9424 ins_encode %{
9425 Label* L = $labl$$label;
9426 assert(__ use_cbcond(*L), "back to back cbcond");
9427 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9428 %}
9429 ins_short_branch(1);
9430 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9431 ins_pipe(cbcond_reg_imm);
9432 %}
9433
9434 // Compare Pointers and branch
9435 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9436 match(If cmp (CmpP op1 op2));
9437 predicate(UseCBCond);
9438 effect(USE labl, KILL pcc);
9439
9440 size(4);
9441 ins_cost(BRANCH_COST);
9442 #ifdef _LP64
9443 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9444 #else
9445 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9446 #endif
9447 ins_encode %{
9448 Label* L = $labl$$label;
9449 assert(__ use_cbcond(*L), "back to back cbcond");
9450 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9451 %}
9452 ins_short_branch(1);
9453 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9454 ins_pipe(cbcond_reg_reg);
9455 %}
9456
9457 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9458 match(If cmp (CmpP op1 null));
9459 predicate(UseCBCond);
9460 effect(USE labl, KILL pcc);
9461
9462 size(4);
9463 ins_cost(BRANCH_COST);
9464 #ifdef _LP64
9465 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9466 #else
9467 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9468 #endif
9469 ins_encode %{
9470 Label* L = $labl$$label;
9471 assert(__ use_cbcond(*L), "back to back cbcond");
9472 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9473 %}
9474 ins_short_branch(1);
9475 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9476 ins_pipe(cbcond_reg_reg);
9477 %}
9478
9479 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9480 match(If cmp (CmpN op1 op2));
9481 predicate(UseCBCond);
9482 effect(USE labl, KILL icc);
9483
9484 size(4);
9485 ins_cost(BRANCH_COST);
9486 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9487 ins_encode %{
9488 Label* L = $labl$$label;
9489 assert(__ use_cbcond(*L), "back to back cbcond");
9490 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9491 %}
9492 ins_short_branch(1);
9493 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9494 ins_pipe(cbcond_reg_reg);
9495 %}
9496
9497 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9498 match(If cmp (CmpN op1 null));
9499 predicate(UseCBCond);
9500 effect(USE labl, KILL icc);
9501
9502 size(4);
9503 ins_cost(BRANCH_COST);
9504 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9505 ins_encode %{
9506 Label* L = $labl$$label;
9507 assert(__ use_cbcond(*L), "back to back cbcond");
9508 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9509 %}
9510 ins_short_branch(1);
9511 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9512 ins_pipe(cbcond_reg_reg);
9513 %}
9514
9515 // Loop back branch
9516 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9517 match(CountedLoopEnd cmp (CmpI op1 op2));
9518 predicate(UseCBCond);
9519 effect(USE labl, KILL icc);
9520
9521 size(4);
9522 ins_cost(BRANCH_COST);
9523 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9524 ins_encode %{
9525 Label* L = $labl$$label;
9526 assert(__ use_cbcond(*L), "back to back cbcond");
9527 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9528 %}
9529 ins_short_branch(1);
9530 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9531 ins_pipe(cbcond_reg_reg);
9532 %}
9533
9534 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9535 match(CountedLoopEnd cmp (CmpI op1 op2));
9536 predicate(UseCBCond);
9537 effect(USE labl, KILL icc);
9538
9539 size(4);
9540 ins_cost(BRANCH_COST);
9541 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9542 ins_encode %{
9543 Label* L = $labl$$label;
9544 assert(__ use_cbcond(*L), "back to back cbcond");
9545 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9546 %}
9547 ins_short_branch(1);
9548 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9549 ins_pipe(cbcond_reg_imm);
9550 %}
9551
9552 // Branch-on-register tests all 64 bits. We assume that values
9553 // in 64-bit registers always remains zero or sign extended
9554 // unless our code munges the high bits. Interrupts can chop
9555 // the high order bits to zero or sign at any time.
9556 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9557 match(If cmp (CmpI op1 zero));
9558 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9559 effect(USE labl);
9560
9561 size(8);
9562 ins_cost(BRANCH_COST);
9563 format %{ "BR$cmp $op1,$labl" %}
9564 ins_encode( enc_bpr( labl, cmp, op1 ) );
9565 ins_avoid_back_to_back(AVOID_BEFORE);
9566 ins_pipe(br_reg);
9567 %}
9568
9569 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9570 match(If cmp (CmpP op1 null));
9571 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9572 effect(USE labl);
9573
9574 size(8);
9575 ins_cost(BRANCH_COST);
9576 format %{ "BR$cmp $op1,$labl" %}
9577 ins_encode( enc_bpr( labl, cmp, op1 ) );
9578 ins_avoid_back_to_back(AVOID_BEFORE);
9579 ins_pipe(br_reg);
9580 %}
9581
9582 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9583 match(If cmp (CmpL op1 zero));
9584 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9585 effect(USE labl);
9586
9587 size(8);
9588 ins_cost(BRANCH_COST);
9589 format %{ "BR$cmp $op1,$labl" %}
9590 ins_encode( enc_bpr( labl, cmp, op1 ) );
9591 ins_avoid_back_to_back(AVOID_BEFORE);
9592 ins_pipe(br_reg);
9593 %}
9594
9595
9596 // ============================================================================
9597 // Long Compare
9598 //
9599 // Currently we hold longs in 2 registers. Comparing such values efficiently
9600 // is tricky. The flavor of compare used depends on whether we are testing
9601 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9602 // The GE test is the negated LT test. The LE test can be had by commuting
9603 // the operands (yielding a GE test) and then negating; negate again for the
9604 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9605 // NE test is negated from that.
9606
9607 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9608 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9609 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9610 // are collapsed internally in the ADLC's dfa-gen code. The match for
9611 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9612 // foo match ends up with the wrong leaf. One fix is to not match both
9613 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9614 // both forms beat the trinary form of long-compare and both are very useful
9615 // on Intel which has so few registers.
9616
9617 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9618 match(If cmp xcc);
9619 effect(USE labl);
9620
9621 size(8);
9622 ins_cost(BRANCH_COST);
9623 format %{ "BP$cmp $xcc,$labl" %}
9624 ins_encode %{
9625 Label* L = $labl$$label;
9626 Assembler::Predict predict_taken =
9627 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9628
9629 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9630 __ delayed()->nop();
9631 %}
9632 ins_avoid_back_to_back(AVOID_BEFORE);
9633 ins_pipe(br_cc);
9634 %}
9635
9636 // Manifest a CmpL3 result in an integer register. Very painful.
9637 // This is the test to avoid.
9638 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9639 match(Set dst (CmpL3 src1 src2) );
9640 effect( KILL ccr );
9641 ins_cost(6*DEFAULT_COST);
9642 size(24);
9643 format %{ "CMP $src1,$src2\t\t! long\n"
9644 "\tBLT,a,pn done\n"
9645 "\tMOV -1,$dst\t! delay slot\n"
9646 "\tBGT,a,pn done\n"
9647 "\tMOV 1,$dst\t! delay slot\n"
9648 "\tCLR $dst\n"
9649 "done:" %}
9650 ins_encode( cmpl_flag(src1,src2,dst) );
9651 ins_pipe(cmpL_reg);
9652 %}
9653
9654 // Conditional move
9655 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9656 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9657 ins_cost(150);
9658 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9659 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9660 ins_pipe(ialu_reg);
9661 %}
9662
9663 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9664 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9665 ins_cost(140);
9666 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9667 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9668 ins_pipe(ialu_imm);
9669 %}
9670
9671 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9672 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9673 ins_cost(150);
9674 format %{ "MOV$cmp $xcc,$src,$dst" %}
9675 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9676 ins_pipe(ialu_reg);
9677 %}
9678
9679 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9680 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9681 ins_cost(140);
9682 format %{ "MOV$cmp $xcc,$src,$dst" %}
9683 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9684 ins_pipe(ialu_imm);
9685 %}
9686
9687 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9688 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9689 ins_cost(150);
9690 format %{ "MOV$cmp $xcc,$src,$dst" %}
9691 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9692 ins_pipe(ialu_reg);
9693 %}
9694
9695 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9696 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9697 ins_cost(150);
9698 format %{ "MOV$cmp $xcc,$src,$dst" %}
9699 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9700 ins_pipe(ialu_reg);
9701 %}
9702
9703 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9704 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9705 ins_cost(140);
9706 format %{ "MOV$cmp $xcc,$src,$dst" %}
9707 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9708 ins_pipe(ialu_imm);
9709 %}
9710
9711 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9712 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9713 ins_cost(150);
9714 opcode(0x101);
9715 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9716 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9717 ins_pipe(int_conditional_float_move);
9718 %}
9719
9720 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9721 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9722 ins_cost(150);
9723 opcode(0x102);
9724 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9725 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9726 ins_pipe(int_conditional_float_move);
9727 %}
9728
9729 // ============================================================================
9730 // Safepoint Instruction
9731 instruct safePoint_poll(iRegP poll) %{
9732 match(SafePoint poll);
9733 effect(USE poll);
9734
9735 size(4);
9736 #ifdef _LP64
9737 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9738 #else
9739 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9740 #endif
9741 ins_encode %{
9742 __ relocate(relocInfo::poll_type);
9743 __ ld_ptr($poll$$Register, 0, G0);
9744 %}
9745 ins_pipe(loadPollP);
9746 %}
9747
9748 // ============================================================================
9749 // Call Instructions
9750 // Call Java Static Instruction
9751 instruct CallStaticJavaDirect( method meth ) %{
9752 match(CallStaticJava);
9753 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9754 effect(USE meth);
9755
9756 size(8);
9757 ins_cost(CALL_COST);
9758 format %{ "CALL,static ; NOP ==> " %}
9759 ins_encode( Java_Static_Call( meth ), call_epilog );
9760 ins_avoid_back_to_back(AVOID_BEFORE);
9761 ins_pipe(simple_call);
9762 %}
9763
9764 // Call Java Static Instruction (method handle version)
9765 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9766 match(CallStaticJava);
9767 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9768 effect(USE meth, KILL l7_mh_SP_save);
9769
9770 size(16);
9771 ins_cost(CALL_COST);
9772 format %{ "CALL,static/MethodHandle" %}
9773 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9774 ins_pipe(simple_call);
9775 %}
9776
9777 // Call Java Dynamic Instruction
9778 instruct CallDynamicJavaDirect( method meth ) %{
9779 match(CallDynamicJava);
9780 effect(USE meth);
9781
9782 ins_cost(CALL_COST);
9783 format %{ "SET (empty),R_G5\n\t"
9784 "CALL,dynamic ; NOP ==> " %}
9785 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9786 ins_pipe(call);
9787 %}
9788
9789 // Call Runtime Instruction
9790 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9791 match(CallRuntime);
9792 effect(USE meth, KILL l7);
9793 ins_cost(CALL_COST);
9794 format %{ "CALL,runtime" %}
9795 ins_encode( Java_To_Runtime( meth ),
9796 call_epilog, adjust_long_from_native_call );
9797 ins_avoid_back_to_back(AVOID_BEFORE);
9798 ins_pipe(simple_call);
9799 %}
9800
9801 // Call runtime without safepoint - same as CallRuntime
9802 instruct CallLeafDirect(method meth, l7RegP l7) %{
9803 match(CallLeaf);
9804 effect(USE meth, KILL l7);
9805 ins_cost(CALL_COST);
9806 format %{ "CALL,runtime leaf" %}
9807 ins_encode( Java_To_Runtime( meth ),
9808 call_epilog,
9809 adjust_long_from_native_call );
9810 ins_avoid_back_to_back(AVOID_BEFORE);
9811 ins_pipe(simple_call);
9812 %}
9813
9814 // Call runtime without safepoint - same as CallLeaf
9815 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9816 match(CallLeafNoFP);
9817 effect(USE meth, KILL l7);
9818 ins_cost(CALL_COST);
9819 format %{ "CALL,runtime leaf nofp" %}
9820 ins_encode( Java_To_Runtime( meth ),
9821 call_epilog,
9822 adjust_long_from_native_call );
9823 ins_avoid_back_to_back(AVOID_BEFORE);
9824 ins_pipe(simple_call);
9825 %}
9826
9827 // Tail Call; Jump from runtime stub to Java code.
9828 // Also known as an 'interprocedural jump'.
9829 // Target of jump will eventually return to caller.
9830 // TailJump below removes the return address.
9831 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9832 match(TailCall jump_target method_oop );
9833
9834 ins_cost(CALL_COST);
9835 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
9836 ins_encode(form_jmpl(jump_target));
9837 ins_avoid_back_to_back(AVOID_BEFORE);
9838 ins_pipe(tail_call);
9839 %}
9840
9841
9842 // Return Instruction
9843 instruct Ret() %{
9844 match(Return);
9845
9846 // The epilogue node did the ret already.
9847 size(0);
9848 format %{ "! return" %}
9849 ins_encode();
9850 ins_pipe(empty);
9851 %}
9852
9853
9854 // Tail Jump; remove the return address; jump to target.
9855 // TailCall above leaves the return address around.
9856 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9857 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9858 // "restore" before this instruction (in Epilogue), we need to materialize it
9859 // in %i0.
9860 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9861 match( TailJump jump_target ex_oop );
9862 ins_cost(CALL_COST);
9863 format %{ "! discard R_O7\n\t"
9864 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9865 ins_encode(form_jmpl_set_exception_pc(jump_target));
9866 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9867 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9868 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9869 ins_avoid_back_to_back(AVOID_BEFORE);
9870 ins_pipe(tail_call);
9871 %}
9872
9873 // Create exception oop: created by stack-crawling runtime code.
9874 // Created exception is now available to this handler, and is setup
9875 // just prior to jumping to this handler. No code emitted.
9876 instruct CreateException( o0RegP ex_oop )
9877 %{
9878 match(Set ex_oop (CreateEx));
9879 ins_cost(0);
9880
9881 size(0);
9882 // use the following format syntax
9883 format %{ "! exception oop is in R_O0; no code emitted" %}
9884 ins_encode();
9885 ins_pipe(empty);
9886 %}
9887
9888
9889 // Rethrow exception:
9890 // The exception oop will come in the first argument position.
9891 // Then JUMP (not call) to the rethrow stub code.
9892 instruct RethrowException()
9893 %{
9894 match(Rethrow);
9895 ins_cost(CALL_COST);
9896
9897 // use the following format syntax
9898 format %{ "Jmp rethrow_stub" %}
9899 ins_encode(enc_rethrow);
9900 ins_avoid_back_to_back(AVOID_BEFORE);
9901 ins_pipe(tail_call);
9902 %}
9903
9904
9905 // Die now
9906 instruct ShouldNotReachHere( )
9907 %{
9908 match(Halt);
9909 ins_cost(CALL_COST);
9910
9911 size(4);
9912 // Use the following format syntax
9913 format %{ "ILLTRAP ; ShouldNotReachHere" %}
9914 ins_encode( form2_illtrap() );
9915 ins_pipe(tail_call);
9916 %}
9917
9918 // ============================================================================
9919 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
9920 // array for an instance of the superklass. Set a hidden internal cache on a
9921 // hit (cache is checked with exposed code in gen_subtype_check()). Return
9922 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
9923 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9924 match(Set index (PartialSubtypeCheck sub super));
9925 effect( KILL pcc, KILL o7 );
9926 ins_cost(DEFAULT_COST*10);
9927 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
9928 ins_encode( enc_PartialSubtypeCheck() );
9929 ins_avoid_back_to_back(AVOID_BEFORE);
9930 ins_pipe(partial_subtype_check_pipe);
9931 %}
9932
9933 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9934 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9935 effect( KILL idx, KILL o7 );
9936 ins_cost(DEFAULT_COST*10);
9937 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9938 ins_encode( enc_PartialSubtypeCheck() );
9939 ins_avoid_back_to_back(AVOID_BEFORE);
9940 ins_pipe(partial_subtype_check_pipe);
9941 %}
9942
9943
9944 // ============================================================================
9945 // inlined locking and unlocking
9946
9947 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9948 match(Set pcc (FastLock object box));
9949
9950 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9951 ins_cost(100);
9952
9953 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9954 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9955 ins_pipe(long_memory_op);
9956 %}
9957
9958
9959 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9960 match(Set pcc (FastUnlock object box));
9961 effect(TEMP scratch2, USE_KILL box, KILL scratch);
9962 ins_cost(100);
9963
9964 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
9965 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9966 ins_pipe(long_memory_op);
9967 %}
9968
9969 // The encodings are generic.
9970 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9971 predicate(!use_block_zeroing(n->in(2)) );
9972 match(Set dummy (ClearArray cnt base));
9973 effect(TEMP temp, KILL ccr);
9974 ins_cost(300);
9975 format %{ "MOV $cnt,$temp\n"
9976 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
9977 " BRge loop\t\t! Clearing loop\n"
9978 " STX G0,[$base+$temp]\t! delay slot" %}
9979
9980 ins_encode %{
9981 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9982 Register nof_bytes_arg = $cnt$$Register;
9983 Register nof_bytes_tmp = $temp$$Register;
9984 Register base_pointer_arg = $base$$Register;
9985
9986 Label loop;
9987 __ mov(nof_bytes_arg, nof_bytes_tmp);
9988
9989 // Loop and clear, walking backwards through the array.
9990 // nof_bytes_tmp (if >0) is always the number of bytes to zero
9991 __ bind(loop);
9992 __ deccc(nof_bytes_tmp, 8);
9993 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
9994 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
9995 // %%%% this mini-loop must not cross a cache boundary!
9996 %}
9997 ins_pipe(long_memory_op);
9998 %}
9999
10000 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10001 predicate(use_block_zeroing(n->in(2)));
10002 match(Set dummy (ClearArray cnt base));
10003 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10004 ins_cost(300);
10005 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10006
10007 ins_encode %{
10008
10009 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10010 Register to = $base$$Register;
10011 Register count = $cnt$$Register;
10012
10013 Label Ldone;
10014 __ nop(); // Separate short branches
10015 // Use BIS for zeroing (temp is not used).
10016 __ bis_zeroing(to, count, G0, Ldone);
10017 __ bind(Ldone);
10018
10019 %}
10020 ins_pipe(long_memory_op);
10021 %}
10022
10023 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10024 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10025 match(Set dummy (ClearArray cnt base));
10026 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10027 ins_cost(300);
10028 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10029
10030 ins_encode %{
10031
10032 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10033 Register to = $base$$Register;
10034 Register count = $cnt$$Register;
10035 Register temp = $tmp$$Register;
10036
10037 Label Ldone;
10038 __ nop(); // Separate short branches
10039 // Use BIS for zeroing
10040 __ bis_zeroing(to, count, temp, Ldone);
10041 __ bind(Ldone);
10042
10043 %}
10044 ins_pipe(long_memory_op);
10045 %}
10046
10047 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10048 o7RegI tmp, flagsReg ccr) %{
10049 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10050 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10051 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10052 ins_cost(300);
10053 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10054 ins_encode %{
10055 __ string_compare($str1$$Register, $str2$$Register,
10056 $cnt1$$Register, $cnt2$$Register,
10057 $tmp$$Register, $tmp$$Register,
10058 $result$$Register, StrIntrinsicNode::LL);
10059 %}
10060 ins_pipe(long_memory_op);
10061 %}
10062
10063 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10064 o7RegI tmp, flagsReg ccr) %{
10065 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10066 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10067 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10068 ins_cost(300);
10069 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10070 ins_encode %{
10071 __ string_compare($str1$$Register, $str2$$Register,
10072 $cnt1$$Register, $cnt2$$Register,
10073 $tmp$$Register, $tmp$$Register,
10074 $result$$Register, StrIntrinsicNode::UU);
10075 %}
10076 ins_pipe(long_memory_op);
10077 %}
10078
10079 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10080 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10081 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10082 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10083 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10084 ins_cost(300);
10085 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10086 ins_encode %{
10087 __ string_compare($str1$$Register, $str2$$Register,
10088 $cnt1$$Register, $cnt2$$Register,
10089 $tmp1$$Register, $tmp2$$Register,
10090 $result$$Register, StrIntrinsicNode::LU);
10091 %}
10092 ins_pipe(long_memory_op);
10093 %}
10094
10095 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10096 o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10097 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10098 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10099 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10100 ins_cost(300);
10101 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1,$tmp2" %}
10102 ins_encode %{
10103 __ string_compare($str2$$Register, $str1$$Register,
10104 $cnt2$$Register, $cnt1$$Register,
10105 $tmp1$$Register, $tmp2$$Register,
10106 $result$$Register, StrIntrinsicNode::UL);
10107 %}
10108 ins_pipe(long_memory_op);
10109 %}
10110
10111 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10112 o7RegI tmp, flagsReg ccr) %{
10113 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10114 match(Set result (StrEquals (Binary str1 str2) cnt));
10115 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10116 ins_cost(300);
10117 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10118 ins_encode %{
10119 __ array_equals(false, $str1$$Register, $str2$$Register,
10120 $cnt$$Register, $tmp$$Register,
10121 $result$$Register, true /* byte */);
10122 %}
10123 ins_pipe(long_memory_op);
10124 %}
10125
10126 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10127 o7RegI tmp, flagsReg ccr) %{
10128 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10129 match(Set result (StrEquals (Binary str1 str2) cnt));
10130 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10131 ins_cost(300);
10132 format %{ "String Equals char[] $str1,$str2,$cnt -> $result // KILL $tmp" %}
10133 ins_encode %{
10134 __ array_equals(false, $str1$$Register, $str2$$Register,
10135 $cnt$$Register, $tmp$$Register,
10136 $result$$Register, false /* byte */);
10137 %}
10138 ins_pipe(long_memory_op);
10139 %}
10140
10141 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10142 o7RegI tmp2, flagsReg ccr) %{
10143 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10144 match(Set result (AryEq ary1 ary2));
10145 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10146 ins_cost(300);
10147 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10148 ins_encode %{
10149 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10150 $tmp1$$Register, $tmp2$$Register,
10151 $result$$Register, true /* byte */);
10152 %}
10153 ins_pipe(long_memory_op);
10154 %}
10155
10156 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10157 o7RegI tmp2, flagsReg ccr) %{
10158 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10159 match(Set result (AryEq ary1 ary2));
10160 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10161 ins_cost(300);
10162 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10163 ins_encode %{
10164 __ array_equals(true, $ary1$$Register, $ary2$$Register,
10165 $tmp1$$Register, $tmp2$$Register,
10166 $result$$Register, false /* byte */);
10167 %}
10168 ins_pipe(long_memory_op);
10169 %}
10170
10171 // char[] to byte[] compression
10172 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10173 predicate(UseVIS < 3);
10174 match(Set result (StrCompressedCopy src (Binary dst len)));
10175 effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10176 ins_cost(300);
10177 format %{ "String Compress $src,$dst,$len -> $result // KILL $tmp" %}
10178 ins_encode %{
10179 Label Ldone;
10180 __ signx($len$$Register);
10181 __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10182 __ delayed()->mov($len$$Register, $result$$Register); // copy count
10183 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10184 __ bind(Ldone);
10185 %}
10186 ins_pipe(long_memory_op);
10187 %}
10188
10189 // fast char[] to byte[] compression using VIS instructions
10190 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10191 iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10192 regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10193 predicate(UseVIS >= 3);
10194 match(Set result (StrCompressedCopy src (Binary dst len)));
10195 effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10196 ins_cost(300);
10197 format %{ "String Compress Fast $src,$dst,$len -> $result // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10198 ins_encode %{
10199 Label Ldone;
10200 __ signx($len$$Register);
10201 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10202 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10203 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10204 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10205 __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10206 __ bind(Ldone);
10207 %}
10208 ins_pipe(long_memory_op);
10209 %}
10210
10211 // byte[] to char[] inflation
10212 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10213 iRegL tmp, flagsReg ccr) %{
10214 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10215 effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10216 ins_cost(300);
10217 format %{ "String Inflate $src,$dst,$len // KILL $tmp" %}
10218 ins_encode %{
10219 Label Ldone;
10220 __ signx($len$$Register);
10221 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10222 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10223 __ bind(Ldone);
10224 %}
10225 ins_pipe(long_memory_op);
10226 %}
10227
10228 // fast byte[] to char[] inflation using VIS instructions
10229 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10230 iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10231 predicate(UseVIS >= 3);
10232 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10233 effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10234 ins_cost(300);
10235 format %{ "String Inflate Fast $src,$dst,$len // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10236 ins_encode %{
10237 Label Ldone;
10238 __ signx($len$$Register);
10239 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10240 $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10241 __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10242 __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10243 __ bind(Ldone);
10244 %}
10245 ins_pipe(long_memory_op);
10246 %}
10247
10248
10249 //---------- Zeros Count Instructions ------------------------------------------
10250
10251 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10252 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10253 match(Set dst (CountLeadingZerosI src));
10254 effect(TEMP dst, TEMP tmp, KILL cr);
10255
10256 // x |= (x >> 1);
10257 // x |= (x >> 2);
10258 // x |= (x >> 4);
10259 // x |= (x >> 8);
10260 // x |= (x >> 16);
10261 // return (WORDBITS - popc(x));
10262 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10263 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10264 "OR $dst,$tmp,$dst\n\t"
10265 "SRL $dst,2,$tmp\n\t"
10266 "OR $dst,$tmp,$dst\n\t"
10267 "SRL $dst,4,$tmp\n\t"
10268 "OR $dst,$tmp,$dst\n\t"
10269 "SRL $dst,8,$tmp\n\t"
10270 "OR $dst,$tmp,$dst\n\t"
10271 "SRL $dst,16,$tmp\n\t"
10272 "OR $dst,$tmp,$dst\n\t"
10273 "POPC $dst,$dst\n\t"
10274 "MOV 32,$tmp\n\t"
10275 "SUB $tmp,$dst,$dst" %}
10276 ins_encode %{
10277 Register Rdst = $dst$$Register;
10278 Register Rsrc = $src$$Register;
10279 Register Rtmp = $tmp$$Register;
10280 __ srl(Rsrc, 1, Rtmp);
10281 __ srl(Rsrc, 0, Rdst);
10282 __ or3(Rdst, Rtmp, Rdst);
10283 __ srl(Rdst, 2, Rtmp);
10284 __ or3(Rdst, Rtmp, Rdst);
10285 __ srl(Rdst, 4, Rtmp);
10286 __ or3(Rdst, Rtmp, Rdst);
10287 __ srl(Rdst, 8, Rtmp);
10288 __ or3(Rdst, Rtmp, Rdst);
10289 __ srl(Rdst, 16, Rtmp);
10290 __ or3(Rdst, Rtmp, Rdst);
10291 __ popc(Rdst, Rdst);
10292 __ mov(BitsPerInt, Rtmp);
10293 __ sub(Rtmp, Rdst, Rdst);
10294 %}
10295 ins_pipe(ialu_reg);
10296 %}
10297
10298 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10299 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10300 match(Set dst (CountLeadingZerosL src));
10301 effect(TEMP dst, TEMP tmp, KILL cr);
10302
10303 // x |= (x >> 1);
10304 // x |= (x >> 2);
10305 // x |= (x >> 4);
10306 // x |= (x >> 8);
10307 // x |= (x >> 16);
10308 // x |= (x >> 32);
10309 // return (WORDBITS - popc(x));
10310 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10311 "OR $src,$tmp,$dst\n\t"
10312 "SRLX $dst,2,$tmp\n\t"
10313 "OR $dst,$tmp,$dst\n\t"
10314 "SRLX $dst,4,$tmp\n\t"
10315 "OR $dst,$tmp,$dst\n\t"
10316 "SRLX $dst,8,$tmp\n\t"
10317 "OR $dst,$tmp,$dst\n\t"
10318 "SRLX $dst,16,$tmp\n\t"
10319 "OR $dst,$tmp,$dst\n\t"
10320 "SRLX $dst,32,$tmp\n\t"
10321 "OR $dst,$tmp,$dst\n\t"
10322 "POPC $dst,$dst\n\t"
10323 "MOV 64,$tmp\n\t"
10324 "SUB $tmp,$dst,$dst" %}
10325 ins_encode %{
10326 Register Rdst = $dst$$Register;
10327 Register Rsrc = $src$$Register;
10328 Register Rtmp = $tmp$$Register;
10329 __ srlx(Rsrc, 1, Rtmp);
10330 __ or3( Rsrc, Rtmp, Rdst);
10331 __ srlx(Rdst, 2, Rtmp);
10332 __ or3( Rdst, Rtmp, Rdst);
10333 __ srlx(Rdst, 4, Rtmp);
10334 __ or3( Rdst, Rtmp, Rdst);
10335 __ srlx(Rdst, 8, Rtmp);
10336 __ or3( Rdst, Rtmp, Rdst);
10337 __ srlx(Rdst, 16, Rtmp);
10338 __ or3( Rdst, Rtmp, Rdst);
10339 __ srlx(Rdst, 32, Rtmp);
10340 __ or3( Rdst, Rtmp, Rdst);
10341 __ popc(Rdst, Rdst);
10342 __ mov(BitsPerLong, Rtmp);
10343 __ sub(Rtmp, Rdst, Rdst);
10344 %}
10345 ins_pipe(ialu_reg);
10346 %}
10347
10348 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10349 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10350 match(Set dst (CountTrailingZerosI src));
10351 effect(TEMP dst, KILL cr);
10352
10353 // return popc(~x & (x - 1));
10354 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10355 "ANDN $dst,$src,$dst\n\t"
10356 "SRL $dst,R_G0,$dst\n\t"
10357 "POPC $dst,$dst" %}
10358 ins_encode %{
10359 Register Rdst = $dst$$Register;
10360 Register Rsrc = $src$$Register;
10361 __ sub(Rsrc, 1, Rdst);
10362 __ andn(Rdst, Rsrc, Rdst);
10363 __ srl(Rdst, G0, Rdst);
10364 __ popc(Rdst, Rdst);
10365 %}
10366 ins_pipe(ialu_reg);
10367 %}
10368
10369 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10370 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10371 match(Set dst (CountTrailingZerosL src));
10372 effect(TEMP dst, KILL cr);
10373
10374 // return popc(~x & (x - 1));
10375 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10376 "ANDN $dst,$src,$dst\n\t"
10377 "POPC $dst,$dst" %}
10378 ins_encode %{
10379 Register Rdst = $dst$$Register;
10380 Register Rsrc = $src$$Register;
10381 __ sub(Rsrc, 1, Rdst);
10382 __ andn(Rdst, Rsrc, Rdst);
10383 __ popc(Rdst, Rdst);
10384 %}
10385 ins_pipe(ialu_reg);
10386 %}
10387
10388
10389 //---------- Population Count Instructions -------------------------------------
10390
10391 instruct popCountI(iRegIsafe dst, iRegI src) %{
10392 predicate(UsePopCountInstruction);
10393 match(Set dst (PopCountI src));
10394
10395 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10396 "POPC $dst, $dst" %}
10397 ins_encode %{
10398 __ srl($src$$Register, G0, $dst$$Register);
10399 __ popc($dst$$Register, $dst$$Register);
10400 %}
10401 ins_pipe(ialu_reg);
10402 %}
10403
10404 // Note: Long.bitCount(long) returns an int.
10405 instruct popCountL(iRegIsafe dst, iRegL src) %{
10406 predicate(UsePopCountInstruction);
10407 match(Set dst (PopCountL src));
10408
10409 format %{ "POPC $src, $dst" %}
10410 ins_encode %{
10411 __ popc($src$$Register, $dst$$Register);
10412 %}
10413 ins_pipe(ialu_reg);
10414 %}
10415
10416
10417 // ============================================================================
10418 //------------Bytes reverse--------------------------------------------------
10419
10420 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10421 match(Set dst (ReverseBytesI src));
10422
10423 // Op cost is artificially doubled to make sure that load or store
10424 // instructions are preferred over this one which requires a spill
10425 // onto a stack slot.
10426 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10427 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10428
10429 ins_encode %{
10430 __ set($src$$disp + STACK_BIAS, O7);
10431 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10432 %}
10433 ins_pipe( iload_mem );
10434 %}
10435
10436 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10437 match(Set dst (ReverseBytesL src));
10438
10439 // Op cost is artificially doubled to make sure that load or store
10440 // instructions are preferred over this one which requires a spill
10441 // onto a stack slot.
10442 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10443 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10444
10445 ins_encode %{
10446 __ set($src$$disp + STACK_BIAS, O7);
10447 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10448 %}
10449 ins_pipe( iload_mem );
10450 %}
10451
10452 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10453 match(Set dst (ReverseBytesUS src));
10454
10455 // Op cost is artificially doubled to make sure that load or store
10456 // instructions are preferred over this one which requires a spill
10457 // onto a stack slot.
10458 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10459 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10460
10461 ins_encode %{
10462 // the value was spilled as an int so bias the load
10463 __ set($src$$disp + STACK_BIAS + 2, O7);
10464 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10465 %}
10466 ins_pipe( iload_mem );
10467 %}
10468
10469 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10470 match(Set dst (ReverseBytesS src));
10471
10472 // Op cost is artificially doubled to make sure that load or store
10473 // instructions are preferred over this one which requires a spill
10474 // onto a stack slot.
10475 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10476 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10477
10478 ins_encode %{
10479 // the value was spilled as an int so bias the load
10480 __ set($src$$disp + STACK_BIAS + 2, O7);
10481 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10482 %}
10483 ins_pipe( iload_mem );
10484 %}
10485
10486 // Load Integer reversed byte order
10487 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10488 match(Set dst (ReverseBytesI (LoadI src)));
10489
10490 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10491 size(4);
10492 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10493
10494 ins_encode %{
10495 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10496 %}
10497 ins_pipe(iload_mem);
10498 %}
10499
10500 // Load Long - aligned and reversed
10501 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10502 match(Set dst (ReverseBytesL (LoadL src)));
10503
10504 ins_cost(MEMORY_REF_COST);
10505 size(4);
10506 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10507
10508 ins_encode %{
10509 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10510 %}
10511 ins_pipe(iload_mem);
10512 %}
10513
10514 // Load unsigned short / char reversed byte order
10515 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10516 match(Set dst (ReverseBytesUS (LoadUS src)));
10517
10518 ins_cost(MEMORY_REF_COST);
10519 size(4);
10520 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10521
10522 ins_encode %{
10523 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10524 %}
10525 ins_pipe(iload_mem);
10526 %}
10527
10528 // Load short reversed byte order
10529 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10530 match(Set dst (ReverseBytesS (LoadS src)));
10531
10532 ins_cost(MEMORY_REF_COST);
10533 size(4);
10534 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10535
10536 ins_encode %{
10537 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10538 %}
10539 ins_pipe(iload_mem);
10540 %}
10541
10542 // Store Integer reversed byte order
10543 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10544 match(Set dst (StoreI dst (ReverseBytesI src)));
10545
10546 ins_cost(MEMORY_REF_COST);
10547 size(4);
10548 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10549
10550 ins_encode %{
10551 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10552 %}
10553 ins_pipe(istore_mem_reg);
10554 %}
10555
10556 // Store Long reversed byte order
10557 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10558 match(Set dst (StoreL dst (ReverseBytesL src)));
10559
10560 ins_cost(MEMORY_REF_COST);
10561 size(4);
10562 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10563
10564 ins_encode %{
10565 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10566 %}
10567 ins_pipe(istore_mem_reg);
10568 %}
10569
10570 // Store unsighed short/char reversed byte order
10571 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10572 match(Set dst (StoreC dst (ReverseBytesUS src)));
10573
10574 ins_cost(MEMORY_REF_COST);
10575 size(4);
10576 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10577
10578 ins_encode %{
10579 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10580 %}
10581 ins_pipe(istore_mem_reg);
10582 %}
10583
10584 // Store short reversed byte order
10585 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10586 match(Set dst (StoreC dst (ReverseBytesS src)));
10587
10588 ins_cost(MEMORY_REF_COST);
10589 size(4);
10590 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10591
10592 ins_encode %{
10593 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10594 %}
10595 ins_pipe(istore_mem_reg);
10596 %}
10597
10598 // ====================VECTOR INSTRUCTIONS=====================================
10599
10600 // Load Aligned Packed values into a Double Register
10601 instruct loadV8(regD dst, memory mem) %{
10602 predicate(n->as_LoadVector()->memory_size() == 8);
10603 match(Set dst (LoadVector mem));
10604 ins_cost(MEMORY_REF_COST);
10605 size(4);
10606 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10607 ins_encode %{
10608 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10609 %}
10610 ins_pipe(floadD_mem);
10611 %}
10612
10613 // Store Vector in Double register to memory
10614 instruct storeV8(memory mem, regD src) %{
10615 predicate(n->as_StoreVector()->memory_size() == 8);
10616 match(Set mem (StoreVector mem src));
10617 ins_cost(MEMORY_REF_COST);
10618 size(4);
10619 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10620 ins_encode %{
10621 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10622 %}
10623 ins_pipe(fstoreD_mem_reg);
10624 %}
10625
10626 // Store Zero into vector in memory
10627 instruct storeV8B_zero(memory mem, immI0 zero) %{
10628 predicate(n->as_StoreVector()->memory_size() == 8);
10629 match(Set mem (StoreVector mem (ReplicateB zero)));
10630 ins_cost(MEMORY_REF_COST);
10631 size(4);
10632 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10633 ins_encode %{
10634 __ stx(G0, $mem$$Address);
10635 %}
10636 ins_pipe(fstoreD_mem_zero);
10637 %}
10638
10639 instruct storeV4S_zero(memory mem, immI0 zero) %{
10640 predicate(n->as_StoreVector()->memory_size() == 8);
10641 match(Set mem (StoreVector mem (ReplicateS zero)));
10642 ins_cost(MEMORY_REF_COST);
10643 size(4);
10644 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10645 ins_encode %{
10646 __ stx(G0, $mem$$Address);
10647 %}
10648 ins_pipe(fstoreD_mem_zero);
10649 %}
10650
10651 instruct storeV2I_zero(memory mem, immI0 zero) %{
10652 predicate(n->as_StoreVector()->memory_size() == 8);
10653 match(Set mem (StoreVector mem (ReplicateI zero)));
10654 ins_cost(MEMORY_REF_COST);
10655 size(4);
10656 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10657 ins_encode %{
10658 __ stx(G0, $mem$$Address);
10659 %}
10660 ins_pipe(fstoreD_mem_zero);
10661 %}
10662
10663 instruct storeV2F_zero(memory mem, immF0 zero) %{
10664 predicate(n->as_StoreVector()->memory_size() == 8);
10665 match(Set mem (StoreVector mem (ReplicateF zero)));
10666 ins_cost(MEMORY_REF_COST);
10667 size(4);
10668 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10669 ins_encode %{
10670 __ stx(G0, $mem$$Address);
10671 %}
10672 ins_pipe(fstoreD_mem_zero);
10673 %}
10674
10675 // Replicate scalar to packed byte values into Double register
10676 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10677 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10678 match(Set dst (ReplicateB src));
10679 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10680 format %{ "SLLX $src,56,$tmp\n\t"
10681 "SRLX $tmp, 8,$tmp2\n\t"
10682 "OR $tmp,$tmp2,$tmp\n\t"
10683 "SRLX $tmp,16,$tmp2\n\t"
10684 "OR $tmp,$tmp2,$tmp\n\t"
10685 "SRLX $tmp,32,$tmp2\n\t"
10686 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10687 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10688 ins_encode %{
10689 Register Rsrc = $src$$Register;
10690 Register Rtmp = $tmp$$Register;
10691 Register Rtmp2 = $tmp2$$Register;
10692 __ sllx(Rsrc, 56, Rtmp);
10693 __ srlx(Rtmp, 8, Rtmp2);
10694 __ or3 (Rtmp, Rtmp2, Rtmp);
10695 __ srlx(Rtmp, 16, Rtmp2);
10696 __ or3 (Rtmp, Rtmp2, Rtmp);
10697 __ srlx(Rtmp, 32, Rtmp2);
10698 __ or3 (Rtmp, Rtmp2, Rtmp);
10699 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10700 %}
10701 ins_pipe(ialu_reg);
10702 %}
10703
10704 // Replicate scalar to packed byte values into Double stack
10705 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10706 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10707 match(Set dst (ReplicateB src));
10708 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10709 format %{ "SLLX $src,56,$tmp\n\t"
10710 "SRLX $tmp, 8,$tmp2\n\t"
10711 "OR $tmp,$tmp2,$tmp\n\t"
10712 "SRLX $tmp,16,$tmp2\n\t"
10713 "OR $tmp,$tmp2,$tmp\n\t"
10714 "SRLX $tmp,32,$tmp2\n\t"
10715 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10716 "STX $tmp,$dst\t! regL to stkD" %}
10717 ins_encode %{
10718 Register Rsrc = $src$$Register;
10719 Register Rtmp = $tmp$$Register;
10720 Register Rtmp2 = $tmp2$$Register;
10721 __ sllx(Rsrc, 56, Rtmp);
10722 __ srlx(Rtmp, 8, Rtmp2);
10723 __ or3 (Rtmp, Rtmp2, Rtmp);
10724 __ srlx(Rtmp, 16, Rtmp2);
10725 __ or3 (Rtmp, Rtmp2, Rtmp);
10726 __ srlx(Rtmp, 32, Rtmp2);
10727 __ or3 (Rtmp, Rtmp2, Rtmp);
10728 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10729 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10730 %}
10731 ins_pipe(ialu_reg);
10732 %}
10733
10734 // Replicate scalar constant to packed byte values in Double register
10735 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10736 predicate(n->as_Vector()->length() == 8);
10737 match(Set dst (ReplicateB con));
10738 effect(KILL tmp);
10739 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10740 ins_encode %{
10741 // XXX This is a quick fix for 6833573.
10742 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10743 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10744 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10745 %}
10746 ins_pipe(loadConFD);
10747 %}
10748
10749 // Replicate scalar to packed char/short values into Double register
10750 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10751 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10752 match(Set dst (ReplicateS src));
10753 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10754 format %{ "SLLX $src,48,$tmp\n\t"
10755 "SRLX $tmp,16,$tmp2\n\t"
10756 "OR $tmp,$tmp2,$tmp\n\t"
10757 "SRLX $tmp,32,$tmp2\n\t"
10758 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10759 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10760 ins_encode %{
10761 Register Rsrc = $src$$Register;
10762 Register Rtmp = $tmp$$Register;
10763 Register Rtmp2 = $tmp2$$Register;
10764 __ sllx(Rsrc, 48, Rtmp);
10765 __ srlx(Rtmp, 16, Rtmp2);
10766 __ or3 (Rtmp, Rtmp2, Rtmp);
10767 __ srlx(Rtmp, 32, Rtmp2);
10768 __ or3 (Rtmp, Rtmp2, Rtmp);
10769 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10770 %}
10771 ins_pipe(ialu_reg);
10772 %}
10773
10774 // Replicate scalar to packed char/short values into Double stack
10775 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10776 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10777 match(Set dst (ReplicateS src));
10778 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10779 format %{ "SLLX $src,48,$tmp\n\t"
10780 "SRLX $tmp,16,$tmp2\n\t"
10781 "OR $tmp,$tmp2,$tmp\n\t"
10782 "SRLX $tmp,32,$tmp2\n\t"
10783 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10784 "STX $tmp,$dst\t! regL to stkD" %}
10785 ins_encode %{
10786 Register Rsrc = $src$$Register;
10787 Register Rtmp = $tmp$$Register;
10788 Register Rtmp2 = $tmp2$$Register;
10789 __ sllx(Rsrc, 48, Rtmp);
10790 __ srlx(Rtmp, 16, Rtmp2);
10791 __ or3 (Rtmp, Rtmp2, Rtmp);
10792 __ srlx(Rtmp, 32, Rtmp2);
10793 __ or3 (Rtmp, Rtmp2, Rtmp);
10794 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10795 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10796 %}
10797 ins_pipe(ialu_reg);
10798 %}
10799
10800 // Replicate scalar constant to packed char/short values in Double register
10801 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10802 predicate(n->as_Vector()->length() == 4);
10803 match(Set dst (ReplicateS con));
10804 effect(KILL tmp);
10805 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10806 ins_encode %{
10807 // XXX This is a quick fix for 6833573.
10808 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10809 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10810 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10811 %}
10812 ins_pipe(loadConFD);
10813 %}
10814
10815 // Replicate scalar to packed int values into Double register
10816 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10817 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10818 match(Set dst (ReplicateI src));
10819 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10820 format %{ "SLLX $src,32,$tmp\n\t"
10821 "SRLX $tmp,32,$tmp2\n\t"
10822 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10823 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10824 ins_encode %{
10825 Register Rsrc = $src$$Register;
10826 Register Rtmp = $tmp$$Register;
10827 Register Rtmp2 = $tmp2$$Register;
10828 __ sllx(Rsrc, 32, Rtmp);
10829 __ srlx(Rtmp, 32, Rtmp2);
10830 __ or3 (Rtmp, Rtmp2, Rtmp);
10831 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10832 %}
10833 ins_pipe(ialu_reg);
10834 %}
10835
10836 // Replicate scalar to packed int values into Double stack
10837 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10838 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10839 match(Set dst (ReplicateI src));
10840 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10841 format %{ "SLLX $src,32,$tmp\n\t"
10842 "SRLX $tmp,32,$tmp2\n\t"
10843 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10844 "STX $tmp,$dst\t! regL to stkD" %}
10845 ins_encode %{
10846 Register Rsrc = $src$$Register;
10847 Register Rtmp = $tmp$$Register;
10848 Register Rtmp2 = $tmp2$$Register;
10849 __ sllx(Rsrc, 32, Rtmp);
10850 __ srlx(Rtmp, 32, Rtmp2);
10851 __ or3 (Rtmp, Rtmp2, Rtmp);
10852 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10853 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10854 %}
10855 ins_pipe(ialu_reg);
10856 %}
10857
10858 // Replicate scalar zero constant to packed int values in Double register
10859 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10860 predicate(n->as_Vector()->length() == 2);
10861 match(Set dst (ReplicateI con));
10862 effect(KILL tmp);
10863 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10864 ins_encode %{
10865 // XXX This is a quick fix for 6833573.
10866 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10867 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10868 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10869 %}
10870 ins_pipe(loadConFD);
10871 %}
10872
10873 // Replicate scalar to packed float values into Double stack
10874 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10875 predicate(n->as_Vector()->length() == 2);
10876 match(Set dst (ReplicateF src));
10877 ins_cost(MEMORY_REF_COST*2);
10878 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10879 "STF $src,$dst.lo" %}
10880 opcode(Assembler::stf_op3);
10881 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10882 ins_pipe(fstoreF_stk_reg);
10883 %}
10884
10885 // Replicate scalar zero constant to packed float values in Double register
10886 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10887 predicate(n->as_Vector()->length() == 2);
10888 match(Set dst (ReplicateF con));
10889 effect(KILL tmp);
10890 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10891 ins_encode %{
10892 // XXX This is a quick fix for 6833573.
10893 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10894 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10895 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10896 %}
10897 ins_pipe(loadConFD);
10898 %}
10899
10900 //----------PEEPHOLE RULES-----------------------------------------------------
10901 // These must follow all instruction definitions as they use the names
10902 // defined in the instructions definitions.
10903 //
10904 // peepmatch ( root_instr_name [preceding_instruction]* );
10905 //
10906 // peepconstraint %{
10907 // (instruction_number.operand_name relational_op instruction_number.operand_name
10908 // [, ...] );
10909 // // instruction numbers are zero-based using left to right order in peepmatch
10910 //
10911 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10912 // // provide an instruction_number.operand_name for each operand that appears
10913 // // in the replacement instruction's match rule
10914 //
10915 // ---------VM FLAGS---------------------------------------------------------
10916 //
10917 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10918 //
10919 // Each peephole rule is given an identifying number starting with zero and
10920 // increasing by one in the order seen by the parser. An individual peephole
10921 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10922 // on the command-line.
10923 //
10924 // ---------CURRENT LIMITATIONS----------------------------------------------
10925 //
10926 // Only match adjacent instructions in same basic block
10927 // Only equality constraints
10928 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10929 // Only one replacement instruction
10930 //
10931 // ---------EXAMPLE----------------------------------------------------------
10932 //
10933 // // pertinent parts of existing instructions in architecture description
10934 // instruct movI(eRegI dst, eRegI src) %{
10935 // match(Set dst (CopyI src));
10936 // %}
10937 //
10938 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10939 // match(Set dst (AddI dst src));
10940 // effect(KILL cr);
10941 // %}
10942 //
10943 // // Change (inc mov) to lea
10944 // peephole %{
10945 // // increment preceeded by register-register move
10946 // peepmatch ( incI_eReg movI );
10947 // // require that the destination register of the increment
10948 // // match the destination register of the move
10949 // peepconstraint ( 0.dst == 1.dst );
10950 // // construct a replacement instruction that sets
10951 // // the destination to ( move's source register + one )
10952 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10953 // %}
10954 //
10955
10956 // // Change load of spilled value to only a spill
10957 // instruct storeI(memory mem, eRegI src) %{
10958 // match(Set mem (StoreI mem src));
10959 // %}
10960 //
10961 // instruct loadI(eRegI dst, memory mem) %{
10962 // match(Set dst (LoadI mem));
10963 // %}
10964 //
10965 // peephole %{
10966 // peepmatch ( loadI storeI );
10967 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10968 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10969 // %}
10970
10971 //----------SMARTSPILL RULES---------------------------------------------------
10972 // These must follow all instruction definitions as they use the names
10973 // defined in the instructions definitions.
10974 //
10975 // SPARC will probably not have any of these rules due to RISC instruction set.
10976
10977 //----------PIPELINE-----------------------------------------------------------
10978 // Rules which define the behavior of the target architectures pipeline.