1403   // The passed offset is relative to address of the branch.
1404   // On 86 a branch displacement is calculated relative to address
1405   // of a next instruction.
1406   offset -= br_size;
1407 
1408   // the short version of jmpConUCF2 contains multiple branches,
1409   // making the reach slightly less
1410   if (rule == jmpConUCF2_rule)
1411     return (-126 <= offset && offset <= 125);
1412   return (-128 <= offset && offset <= 127);
1413 }
1414 
1415 const bool Matcher::isSimpleConstant64(jlong value) {
1416   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1417   return false;
1418 }
1419 
1420 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1421 const bool Matcher::init_array_count_is_in_bytes = false;
1422 
1423 // Threshold size for cleararray.
1424 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1425 
1426 // Needs 2 CMOV's for longs.
1427 const int Matcher::long_cmove_cost() { return 1; }
1428 
1429 // No CMOVF/CMOVD with SSE/SSE2
1430 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1431 
1432 // Does the CPU require late expand (see block.cpp for description of late expand)?
1433 const bool Matcher::require_postalloc_expand = false;
1434 
1435 // Should the Matcher clone shifts on addressing modes, expecting them to
1436 // be subsumed into complex addressing expressions or compute them into
1437 // registers?  True for Intel but false for most RISCs
1438 const bool Matcher::clone_shift_expressions = true;
1439 
1440 // Do we need to mask the count passed to shift instructions or does
1441 // the cpu only look at the lower 5/6 bits anyway?
1442 const bool Matcher::need_masked_shift_count = false;
1443 
1444 bool Matcher::narrow_oop_use_complex_address() {
1445   ShouldNotCallThis();

1403   // The passed offset is relative to address of the branch.
1404   // On 86 a branch displacement is calculated relative to address
1405   // of a next instruction.
1406   offset -= br_size;
1407 
1408   // the short version of jmpConUCF2 contains multiple branches,
1409   // making the reach slightly less
1410   if (rule == jmpConUCF2_rule)
1411     return (-126 <= offset && offset <= 125);
1412   return (-128 <= offset && offset <= 127);
1413 }
1414 
1415 const bool Matcher::isSimpleConstant64(jlong value) {
1416   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1417   return false;
1418 }
1419 
1420 // The ecx parameter to rep stos for the ClearArray node is in dwords.
1421 const bool Matcher::init_array_count_is_in_bytes = false;
1422 



1423 // Needs 2 CMOV's for longs.
1424 const int Matcher::long_cmove_cost() { return 1; }
1425 
1426 // No CMOVF/CMOVD with SSE/SSE2
1427 const int Matcher::float_cmove_cost() { return (UseSSE>=1) ? ConditionalMoveLimit : 0; }
1428 
1429 // Does the CPU require late expand (see block.cpp for description of late expand)?
1430 const bool Matcher::require_postalloc_expand = false;
1431 
1432 // Should the Matcher clone shifts on addressing modes, expecting them to
1433 // be subsumed into complex addressing expressions or compute them into
1434 // registers?  True for Intel but false for most RISCs
1435 const bool Matcher::clone_shift_expressions = true;
1436 
1437 // Do we need to mask the count passed to shift instructions or does
1438 // the cpu only look at the lower 5/6 bits anyway?
1439 const bool Matcher::need_masked_shift_count = false;
1440 
1441 bool Matcher::narrow_oop_use_complex_address() {
1442   ShouldNotCallThis();