1 //
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   3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   4 //
   5 // This code is free software; you can redistribute it and/or modify it
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   7 // published by the Free Software Foundation.
   8 //
   9 // This code is distributed in the hope that it will be useful, but WITHOUT
  10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11 // FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12 // version 2 for more details (a copy is included in the LICENSE file that
  13 // accompanied this code).
  14 //
  15 // You should have received a copy of the GNU General Public License version
  16 // 2 along with this work; if not, write to the Free Software Foundation,
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  18 //
  19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20 // or visit www.oracle.com if you need additional information or have any
  21 // questions.
  22 //
  23 //
  24 
  25 // SPARC Architecture Description File
  26 
  27 //----------REGISTER DEFINITION BLOCK------------------------------------------
  28 // This information is used by the matcher and the register allocator to
  29 // describe individual registers and classes of registers within the target
  30 // archtecture.
  31 register %{
  32 //----------Architecture Description Register Definitions----------------------
  33 // General Registers
  34 // "reg_def"  name ( register save type, C convention save type,
  35 //                   ideal register type, encoding, vm name );
  36 // Register Save Types:
  37 //
  38 // NS  = No-Save:       The register allocator assumes that these registers
  39 //                      can be used without saving upon entry to the method, &
  40 //                      that they do not need to be saved at call sites.
  41 //
  42 // SOC = Save-On-Call:  The register allocator assumes that these registers
  43 //                      can be used without saving upon entry to the method,
  44 //                      but that they must be saved at call sites.
  45 //
  46 // SOE = Save-On-Entry: The register allocator assumes that these registers
  47 //                      must be saved before using them upon entry to the
  48 //                      method, but they do not need to be saved at call
  49 //                      sites.
  50 //
  51 // AS  = Always-Save:   The register allocator assumes that these registers
  52 //                      must be saved before using them upon entry to the
  53 //                      method, & that they must be saved at call sites.
  54 //
  55 // Ideal Register Type is used to determine how to save & restore a
  56 // register.  Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
  57 // spilled with LoadP/StoreP.  If the register supports both, use Op_RegI.
  58 //
  59 // The encoding number is the actual bit-pattern placed into the opcodes.
  60 
  61 
  62 // ----------------------------
  63 // Integer/Long Registers
  64 // ----------------------------
  65 
  66 // Need to expose the hi/lo aspect of 64-bit registers
  67 // This register set is used for both the 64-bit build and
  68 // the 32-bit build with 1-register longs.
  69 
  70 // Global Registers 0-7
  71 reg_def R_G0H( NS,  NS, Op_RegI,128, G0->as_VMReg()->next());
  72 reg_def R_G0 ( NS,  NS, Op_RegI,  0, G0->as_VMReg());
  73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
  74 reg_def R_G1 (SOC, SOC, Op_RegI,  1, G1->as_VMReg());
  75 reg_def R_G2H( NS,  NS, Op_RegI,130, G2->as_VMReg()->next());
  76 reg_def R_G2 ( NS,  NS, Op_RegI,  2, G2->as_VMReg());
  77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
  78 reg_def R_G3 (SOC, SOC, Op_RegI,  3, G3->as_VMReg());
  79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
  80 reg_def R_G4 (SOC, SOC, Op_RegI,  4, G4->as_VMReg());
  81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
  82 reg_def R_G5 (SOC, SOC, Op_RegI,  5, G5->as_VMReg());
  83 reg_def R_G6H( NS,  NS, Op_RegI,134, G6->as_VMReg()->next());
  84 reg_def R_G6 ( NS,  NS, Op_RegI,  6, G6->as_VMReg());
  85 reg_def R_G7H( NS,  NS, Op_RegI,135, G7->as_VMReg()->next());
  86 reg_def R_G7 ( NS,  NS, Op_RegI,  7, G7->as_VMReg());
  87 
  88 // Output Registers 0-7
  89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
  90 reg_def R_O0 (SOC, SOC, Op_RegI,  8, O0->as_VMReg());
  91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
  92 reg_def R_O1 (SOC, SOC, Op_RegI,  9, O1->as_VMReg());
  93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
  94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
  95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
  96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
  97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
  98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
  99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
 100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
 101 reg_def R_SPH( NS,  NS, Op_RegI,142, SP->as_VMReg()->next());
 102 reg_def R_SP ( NS,  NS, Op_RegI, 14, SP->as_VMReg());
 103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
 104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
 105 
 106 // Local Registers 0-7
 107 reg_def R_L0H( NS,  NS, Op_RegI,144, L0->as_VMReg()->next());
 108 reg_def R_L0 ( NS,  NS, Op_RegI, 16, L0->as_VMReg());
 109 reg_def R_L1H( NS,  NS, Op_RegI,145, L1->as_VMReg()->next());
 110 reg_def R_L1 ( NS,  NS, Op_RegI, 17, L1->as_VMReg());
 111 reg_def R_L2H( NS,  NS, Op_RegI,146, L2->as_VMReg()->next());
 112 reg_def R_L2 ( NS,  NS, Op_RegI, 18, L2->as_VMReg());
 113 reg_def R_L3H( NS,  NS, Op_RegI,147, L3->as_VMReg()->next());
 114 reg_def R_L3 ( NS,  NS, Op_RegI, 19, L3->as_VMReg());
 115 reg_def R_L4H( NS,  NS, Op_RegI,148, L4->as_VMReg()->next());
 116 reg_def R_L4 ( NS,  NS, Op_RegI, 20, L4->as_VMReg());
 117 reg_def R_L5H( NS,  NS, Op_RegI,149, L5->as_VMReg()->next());
 118 reg_def R_L5 ( NS,  NS, Op_RegI, 21, L5->as_VMReg());
 119 reg_def R_L6H( NS,  NS, Op_RegI,150, L6->as_VMReg()->next());
 120 reg_def R_L6 ( NS,  NS, Op_RegI, 22, L6->as_VMReg());
 121 reg_def R_L7H( NS,  NS, Op_RegI,151, L7->as_VMReg()->next());
 122 reg_def R_L7 ( NS,  NS, Op_RegI, 23, L7->as_VMReg());
 123 
 124 // Input Registers 0-7
 125 reg_def R_I0H( NS,  NS, Op_RegI,152, I0->as_VMReg()->next());
 126 reg_def R_I0 ( NS,  NS, Op_RegI, 24, I0->as_VMReg());
 127 reg_def R_I1H( NS,  NS, Op_RegI,153, I1->as_VMReg()->next());
 128 reg_def R_I1 ( NS,  NS, Op_RegI, 25, I1->as_VMReg());
 129 reg_def R_I2H( NS,  NS, Op_RegI,154, I2->as_VMReg()->next());
 130 reg_def R_I2 ( NS,  NS, Op_RegI, 26, I2->as_VMReg());
 131 reg_def R_I3H( NS,  NS, Op_RegI,155, I3->as_VMReg()->next());
 132 reg_def R_I3 ( NS,  NS, Op_RegI, 27, I3->as_VMReg());
 133 reg_def R_I4H( NS,  NS, Op_RegI,156, I4->as_VMReg()->next());
 134 reg_def R_I4 ( NS,  NS, Op_RegI, 28, I4->as_VMReg());
 135 reg_def R_I5H( NS,  NS, Op_RegI,157, I5->as_VMReg()->next());
 136 reg_def R_I5 ( NS,  NS, Op_RegI, 29, I5->as_VMReg());
 137 reg_def R_FPH( NS,  NS, Op_RegI,158, FP->as_VMReg()->next());
 138 reg_def R_FP ( NS,  NS, Op_RegI, 30, FP->as_VMReg());
 139 reg_def R_I7H( NS,  NS, Op_RegI,159, I7->as_VMReg()->next());
 140 reg_def R_I7 ( NS,  NS, Op_RegI, 31, I7->as_VMReg());
 141 
 142 // ----------------------------
 143 // Float/Double Registers
 144 // ----------------------------
 145 
 146 // Float Registers
 147 reg_def R_F0 ( SOC, SOC, Op_RegF,  0, F0->as_VMReg());
 148 reg_def R_F1 ( SOC, SOC, Op_RegF,  1, F1->as_VMReg());
 149 reg_def R_F2 ( SOC, SOC, Op_RegF,  2, F2->as_VMReg());
 150 reg_def R_F3 ( SOC, SOC, Op_RegF,  3, F3->as_VMReg());
 151 reg_def R_F4 ( SOC, SOC, Op_RegF,  4, F4->as_VMReg());
 152 reg_def R_F5 ( SOC, SOC, Op_RegF,  5, F5->as_VMReg());
 153 reg_def R_F6 ( SOC, SOC, Op_RegF,  6, F6->as_VMReg());
 154 reg_def R_F7 ( SOC, SOC, Op_RegF,  7, F7->as_VMReg());
 155 reg_def R_F8 ( SOC, SOC, Op_RegF,  8, F8->as_VMReg());
 156 reg_def R_F9 ( SOC, SOC, Op_RegF,  9, F9->as_VMReg());
 157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
 158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
 159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
 160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
 161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
 162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
 163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
 164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
 165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
 166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
 167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
 168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
 169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
 170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
 171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
 172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
 173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
 174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
 175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
 176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
 177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
 178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
 179 
 180 // Double Registers
 181 // The rules of ADL require that double registers be defined in pairs.
 182 // Each pair must be two 32-bit values, but not necessarily a pair of
 183 // single float registers.  In each pair, ADLC-assigned register numbers
 184 // must be adjacent, with the lower number even.  Finally, when the
 185 // CPU stores such a register pair to memory, the word associated with
 186 // the lower ADLC-assigned number must be stored to the lower address.
 187 
 188 // These definitions specify the actual bit encodings of the sparc
 189 // double fp register numbers.  FloatRegisterImpl in register_sparc.hpp
 190 // wants 0-63, so we have to convert every time we want to use fp regs
 191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
 192 // 255 is a flag meaning "don't go here".
 193 // I believe we can't handle callee-save doubles D32 and up until
 194 // the place in the sparc stack crawler that asserts on the 255 is
 195 // fixed up.
 196 reg_def R_D32 (SOC, SOC, Op_RegD,  1, F32->as_VMReg());
 197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
 198 reg_def R_D34 (SOC, SOC, Op_RegD,  3, F34->as_VMReg());
 199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
 200 reg_def R_D36 (SOC, SOC, Op_RegD,  5, F36->as_VMReg());
 201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
 202 reg_def R_D38 (SOC, SOC, Op_RegD,  7, F38->as_VMReg());
 203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
 204 reg_def R_D40 (SOC, SOC, Op_RegD,  9, F40->as_VMReg());
 205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
 206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
 207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
 208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
 209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
 210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
 211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
 212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
 213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
 214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
 215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
 216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
 217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
 218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
 219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
 220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
 221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
 222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
 223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
 224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
 225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
 226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
 227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
 228 
 229 
 230 // ----------------------------
 231 // Special Registers
 232 // Condition Codes Flag Registers
 233 // I tried to break out ICC and XCC but it's not very pretty.
 234 // Every Sparc instruction which defs/kills one also kills the other.
 235 // Hence every compare instruction which defs one kind of flags ends
 236 // up needing a kill of the other.
 237 reg_def CCR (SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
 238 
 239 reg_def FCC0(SOC, SOC,  Op_RegFlags, 0, VMRegImpl::Bad());
 240 reg_def FCC1(SOC, SOC,  Op_RegFlags, 1, VMRegImpl::Bad());
 241 reg_def FCC2(SOC, SOC,  Op_RegFlags, 2, VMRegImpl::Bad());
 242 reg_def FCC3(SOC, SOC,  Op_RegFlags, 3, VMRegImpl::Bad());
 243 
 244 // ----------------------------
 245 // Specify the enum values for the registers.  These enums are only used by the
 246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
 247 // for visibility to the rest of the vm. The order of this enum influences the
 248 // register allocator so having the freedom to set this order and not be stuck
 249 // with the order that is natural for the rest of the vm is worth it.
 250 alloc_class chunk0(
 251   R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
 252   R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
 253   R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
 254   R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
 255 
 256 // Note that a register is not allocatable unless it is also mentioned
 257 // in a widely-used reg_class below.  Thus, R_G7 and R_G0 are outside i_reg.
 258 
 259 alloc_class chunk1(
 260   // The first registers listed here are those most likely to be used
 261   // as temporaries.  We move F0..F7 away from the front of the list,
 262   // to reduce the likelihood of interferences with parameters and
 263   // return values.  Likewise, we avoid using F0/F1 for parameters,
 264   // since they are used for return values.
 265   // This FPU fine-tuning is worth about 1% on the SPEC geomean.
 266   R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 267   R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
 268   R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
 269   R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
 270   R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
 271   R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
 272   R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
 273   R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
 274 
 275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
 276 
 277 //----------Architecture Description Register Classes--------------------------
 278 // Several register classes are automatically defined based upon information in
 279 // this architecture description.
 280 // 1) reg_class inline_cache_reg           ( as defined in frame section )
 281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
 282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
 283 //
 284 
 285 // G0 is not included in integer class since it has special meaning.
 286 reg_class g0_reg(R_G0);
 287 
 288 // ----------------------------
 289 // Integer Register Classes
 290 // ----------------------------
 291 // Exclusions from i_reg:
 292 // R_G0: hardwired zero
 293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
 294 // R_G6: reserved by Solaris ABI to tools
 295 // R_G7: reserved by Solaris ABI to libthread
 296 // R_O7: Used as a temp in many encodings
 297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 298 
 299 // Class for all integer registers, except the G registers.  This is used for
 300 // encodings which use G registers as temps.  The regular inputs to such
 301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
 302 // will not put an input into a temp register.
 303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 304 
 305 reg_class g1_regI(R_G1);
 306 reg_class g3_regI(R_G3);
 307 reg_class g4_regI(R_G4);
 308 reg_class o0_regI(R_O0);
 309 reg_class o7_regI(R_O7);
 310 
 311 // ----------------------------
 312 // Pointer Register Classes
 313 // ----------------------------
 314 #ifdef _LP64
 315 // 64-bit build means 64-bit pointers means hi/lo pairs
 316 reg_class ptr_reg(            R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
 317                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
 318                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 319                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
 320 // Lock encodings use G3 and G4 internally
 321 reg_class lock_ptr_reg(       R_G1H,R_G1,                                     R_G5H,R_G5,
 322                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
 323                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 324                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
 325 // Special class for storeP instructions, which can store SP or RPC to TLS.
 326 // It is also used for memory addressing, allowing direct TLS addressing.
 327 reg_class sp_ptr_reg(         R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
 328                   R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
 329                   R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
 330                   R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
 331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
 332 // We use it to save R_G2 across calls out of Java.
 333 reg_class l7_regP(R_L7H,R_L7);
 334 
 335 // Other special pointer regs
 336 reg_class g1_regP(R_G1H,R_G1);
 337 reg_class g2_regP(R_G2H,R_G2);
 338 reg_class g3_regP(R_G3H,R_G3);
 339 reg_class g4_regP(R_G4H,R_G4);
 340 reg_class g5_regP(R_G5H,R_G5);
 341 reg_class i0_regP(R_I0H,R_I0);
 342 reg_class o0_regP(R_O0H,R_O0);
 343 reg_class o1_regP(R_O1H,R_O1);
 344 reg_class o2_regP(R_O2H,R_O2);
 345 reg_class o7_regP(R_O7H,R_O7);
 346 
 347 #else // _LP64
 348 // 32-bit build means 32-bit pointers means 1 register.
 349 reg_class ptr_reg(     R_G1,     R_G3,R_G4,R_G5,
 350                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
 351                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 352                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 353 // Lock encodings use G3 and G4 internally
 354 reg_class lock_ptr_reg(R_G1,               R_G5,
 355                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
 356                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 357                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
 358 // Special class for storeP instructions, which can store SP or RPC to TLS.
 359 // It is also used for memory addressing, allowing direct TLS addressing.
 360 reg_class sp_ptr_reg(  R_G1,R_G2,R_G3,R_G4,R_G5,
 361                   R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
 362                   R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
 363                   R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
 364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
 365 // We use it to save R_G2 across calls out of Java.
 366 reg_class l7_regP(R_L7);
 367 
 368 // Other special pointer regs
 369 reg_class g1_regP(R_G1);
 370 reg_class g2_regP(R_G2);
 371 reg_class g3_regP(R_G3);
 372 reg_class g4_regP(R_G4);
 373 reg_class g5_regP(R_G5);
 374 reg_class i0_regP(R_I0);
 375 reg_class o0_regP(R_O0);
 376 reg_class o1_regP(R_O1);
 377 reg_class o2_regP(R_O2);
 378 reg_class o7_regP(R_O7);
 379 #endif // _LP64
 380 
 381 
 382 // ----------------------------
 383 // Long Register Classes
 384 // ----------------------------
 385 // Longs in 1 register.  Aligned adjacent hi/lo pairs.
 386 // Note:  O7 is never in this class; it is sometimes used as an encoding temp.
 387 reg_class long_reg(             R_G1H,R_G1,             R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
 388                    ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
 389 #ifdef _LP64
 390 // 64-bit, longs in 1 register: use all 64-bit integer registers
 391 // 32-bit, longs in 1 register: cannot use I's and L's.  Restrict to O's and G's.
 392                    ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
 393                    ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
 394 #endif // _LP64
 395                   );
 396 
 397 reg_class g1_regL(R_G1H,R_G1);
 398 reg_class g3_regL(R_G3H,R_G3);
 399 reg_class o2_regL(R_O2H,R_O2);
 400 reg_class o7_regL(R_O7H,R_O7);
 401 
 402 // ----------------------------
 403 // Special Class for Condition Code Flags Register
 404 reg_class int_flags(CCR);
 405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
 406 reg_class float_flag0(FCC0);
 407 
 408 
 409 // ----------------------------
 410 // Float Point Register Classes
 411 // ----------------------------
 412 // Skip F30/F31, they are reserved for mem-mem copies
 413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
 414 
 415 // Paired floating point registers--they show up in the same order as the floats,
 416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
 417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 418                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
 419                    /* Use extra V9 double registers; this AD file does not support V8 */
 420                    R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
 421                    R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
 422                    );
 423 
 424 // Paired floating point registers--they show up in the same order as the floats,
 425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
 426 // This class is usable for mis-aligned loads as happen in I2C adapters.
 427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
 428                    R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
 429 %}
 430 
 431 //----------DEFINITION BLOCK---------------------------------------------------
 432 // Define name --> value mappings to inform the ADLC of an integer valued name
 433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
 434 // Format:
 435 //        int_def  <name>         ( <int_value>, <expression>);
 436 // Generated Code in ad_<arch>.hpp
 437 //        #define  <name>   (<expression>)
 438 //        // value == <int_value>
 439 // Generated code in ad_<arch>.cpp adlc_verification()
 440 //        assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
 441 //
 442 definitions %{
 443 // The default cost (of an ALU instruction).
 444   int_def DEFAULT_COST      (    100,     100);
 445   int_def HUGE_COST         (1000000, 1000000);
 446 
 447 // Memory refs are twice as expensive as run-of-the-mill.
 448   int_def MEMORY_REF_COST   (    200, DEFAULT_COST * 2);
 449 
 450 // Branches are even more expensive.
 451   int_def BRANCH_COST       (    300, DEFAULT_COST * 3);
 452   int_def CALL_COST         (    300, DEFAULT_COST * 3);
 453 %}
 454 
 455 
 456 //----------SOURCE BLOCK-------------------------------------------------------
 457 // This is a block of C++ code which provides values, functions, and
 458 // definitions necessary in the rest of the architecture description
 459 source_hpp %{
 460 // Header information of the source block.
 461 // Method declarations/definitions which are used outside
 462 // the ad-scope can conveniently be defined here.
 463 //
 464 // To keep related declarations/definitions/uses close together,
 465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
 466 
 467 // Must be visible to the DFA in dfa_sparc.cpp
 468 extern bool can_branch_register( Node *bol, Node *cmp );
 469 
 470 extern bool use_block_zeroing(Node* count);
 471 
 472 // Macros to extract hi & lo halves from a long pair.
 473 // G0 is not part of any long pair, so assert on that.
 474 // Prevents accidentally using G1 instead of G0.
 475 #define LONG_HI_REG(x) (x)
 476 #define LONG_LO_REG(x) (x)
 477 
 478 class CallStubImpl {
 479 
 480   //--------------------------------------------------------------
 481   //---<  Used for optimization in Compile::Shorten_branches  >---
 482   //--------------------------------------------------------------
 483 
 484  public:
 485   // Size of call trampoline stub.
 486   static uint size_call_trampoline() {
 487     return 0; // no call trampolines on this platform
 488   }
 489 
 490   // number of relocations needed by a call trampoline stub
 491   static uint reloc_call_trampoline() {
 492     return 0; // no call trampolines on this platform
 493   }
 494 };
 495 
 496 class HandlerImpl {
 497 
 498  public:
 499 
 500   static int emit_exception_handler(CodeBuffer &cbuf);
 501   static int emit_deopt_handler(CodeBuffer& cbuf);
 502 
 503   static uint size_exception_handler() {
 504     if (TraceJumps) {
 505       return (400); // just a guess
 506     }
 507     return ( NativeJump::instruction_size ); // sethi;jmp;nop
 508   }
 509 
 510   static uint size_deopt_handler() {
 511     if (TraceJumps) {
 512       return (400); // just a guess
 513     }
 514     return ( 4+  NativeJump::instruction_size ); // save;sethi;jmp;restore
 515   }
 516 };
 517 
 518 %}
 519 
 520 source %{
 521 #define __ _masm.
 522 
 523 // tertiary op of a LoadP or StoreP encoding
 524 #define REGP_OP true
 525 
 526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
 527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
 528 static Register reg_to_register_object(int register_encoding);
 529 
 530 // Used by the DFA in dfa_sparc.cpp.
 531 // Check for being able to use a V9 branch-on-register.  Requires a
 532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
 533 // extended.  Doesn't work following an integer ADD, for example, because of
 534 // overflow (-1 incremented yields 0 plus a carry in the high-order word).  On
 535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
 536 // replace them with zero, which could become sign-extension in a different OS
 537 // release.  There's no obvious reason why an interrupt will ever fill these
 538 // bits with non-zero junk (the registers are reloaded with standard LD
 539 // instructions which either zero-fill or sign-fill).
 540 bool can_branch_register( Node *bol, Node *cmp ) {
 541   if( !BranchOnRegister ) return false;
 542 #ifdef _LP64
 543   if( cmp->Opcode() == Op_CmpP )
 544     return true;  // No problems with pointer compares
 545 #endif
 546   if( cmp->Opcode() == Op_CmpL )
 547     return true;  // No problems with long compares
 548 
 549   if( !SparcV9RegsHiBitsZero ) return false;
 550   if( bol->as_Bool()->_test._test != BoolTest::ne &&
 551       bol->as_Bool()->_test._test != BoolTest::eq )
 552      return false;
 553 
 554   // Check for comparing against a 'safe' value.  Any operation which
 555   // clears out the high word is safe.  Thus, loads and certain shifts
 556   // are safe, as are non-negative constants.  Any operation which
 557   // preserves zero bits in the high word is safe as long as each of its
 558   // inputs are safe.  Thus, phis and bitwise booleans are safe if their
 559   // inputs are safe.  At present, the only important case to recognize
 560   // seems to be loads.  Constants should fold away, and shifts &
 561   // logicals can use the 'cc' forms.
 562   Node *x = cmp->in(1);
 563   if( x->is_Load() ) return true;
 564   if( x->is_Phi() ) {
 565     for( uint i = 1; i < x->req(); i++ )
 566       if( !x->in(i)->is_Load() )
 567         return false;
 568     return true;
 569   }
 570   return false;
 571 }
 572 
 573 bool use_block_zeroing(Node* count) {
 574   // Use BIS for zeroing if count is not constant
 575   // or it is >= BlockZeroingLowLimit.
 576   return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
 577 }
 578 
 579 // ****************************************************************************
 580 
 581 // REQUIRED FUNCTIONALITY
 582 
 583 // !!!!! Special hack to get all type of calls to specify the byte offset
 584 //       from the start of the call to the point where the return address
 585 //       will point.
 586 //       The "return address" is the address of the call instruction, plus 8.
 587 
 588 int MachCallStaticJavaNode::ret_addr_offset() {
 589   int offset = NativeCall::instruction_size;  // call; delay slot
 590   if (_method_handle_invoke)
 591     offset += 4;  // restore SP
 592   return offset;
 593 }
 594 
 595 int MachCallDynamicJavaNode::ret_addr_offset() {
 596   int vtable_index = this->_vtable_index;
 597   if (vtable_index < 0) {
 598     // must be invalid_vtable_index, not nonvirtual_vtable_index
 599     assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
 600     return (NativeMovConstReg::instruction_size +
 601            NativeCall::instruction_size);  // sethi; setlo; call; delay slot
 602   } else {
 603     assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
 604     int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
 605     int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
 606     int klass_load_size;
 607     if (UseCompressedClassPointers) {
 608       assert(Universe::heap() != NULL, "java heap should be initialized");
 609       klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
 610     } else {
 611       klass_load_size = 1*BytesPerInstWord;
 612     }
 613     if (Assembler::is_simm13(v_off)) {
 614       return klass_load_size +
 615              (2*BytesPerInstWord +           // ld_ptr, ld_ptr
 616              NativeCall::instruction_size);  // call; delay slot
 617     } else {
 618       return klass_load_size +
 619              (4*BytesPerInstWord +           // set_hi, set, ld_ptr, ld_ptr
 620              NativeCall::instruction_size);  // call; delay slot
 621     }
 622   }
 623 }
 624 
 625 int MachCallRuntimeNode::ret_addr_offset() {
 626 #ifdef _LP64
 627   if (MacroAssembler::is_far_target(entry_point())) {
 628     return NativeFarCall::instruction_size;
 629   } else {
 630     return NativeCall::instruction_size;
 631   }
 632 #else
 633   return NativeCall::instruction_size;  // call; delay slot
 634 #endif
 635 }
 636 
 637 // Indicate if the safepoint node needs the polling page as an input.
 638 // Since Sparc does not have absolute addressing, it does.
 639 bool SafePointNode::needs_polling_address_input() {
 640   return true;
 641 }
 642 
 643 // emit an interrupt that is caught by the debugger (for debugging compiler)
 644 void emit_break(CodeBuffer &cbuf) {
 645   MacroAssembler _masm(&cbuf);
 646   __ breakpoint_trap();
 647 }
 648 
 649 #ifndef PRODUCT
 650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
 651   st->print("TA");
 652 }
 653 #endif
 654 
 655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
 656   emit_break(cbuf);
 657 }
 658 
 659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
 660   return MachNode::size(ra_);
 661 }
 662 
 663 // Traceable jump
 664 void  emit_jmpl(CodeBuffer &cbuf, int jump_target) {
 665   MacroAssembler _masm(&cbuf);
 666   Register rdest = reg_to_register_object(jump_target);
 667   __ JMP(rdest, 0);
 668   __ delayed()->nop();
 669 }
 670 
 671 // Traceable jump and set exception pc
 672 void  emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
 673   MacroAssembler _masm(&cbuf);
 674   Register rdest = reg_to_register_object(jump_target);
 675   __ JMP(rdest, 0);
 676   __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
 677 }
 678 
 679 void emit_nop(CodeBuffer &cbuf) {
 680   MacroAssembler _masm(&cbuf);
 681   __ nop();
 682 }
 683 
 684 void emit_illtrap(CodeBuffer &cbuf) {
 685   MacroAssembler _masm(&cbuf);
 686   __ illtrap(0);
 687 }
 688 
 689 
 690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
 691   assert(n->rule() != loadUB_rule, "");
 692 
 693   intptr_t offset = 0;
 694   const TypePtr *adr_type = TYPE_PTR_SENTINAL;  // Check for base==RegI, disp==immP
 695   const Node* addr = n->get_base_and_disp(offset, adr_type);
 696   assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
 697   assert(addr != NULL && addr != (Node*)-1, "invalid addr");
 698   assert(addr->bottom_type()->isa_oopptr() == atype, "");
 699   atype = atype->add_offset(offset);
 700   assert(disp32 == offset, "wrong disp32");
 701   return atype->_offset;
 702 }
 703 
 704 
 705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
 706   assert(n->rule() != loadUB_rule, "");
 707 
 708   intptr_t offset = 0;
 709   Node* addr = n->in(2);
 710   assert(addr->bottom_type()->isa_oopptr() == atype, "");
 711   if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
 712     Node* a = addr->in(2/*AddPNode::Address*/);
 713     Node* o = addr->in(3/*AddPNode::Offset*/);
 714     offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
 715     atype = a->bottom_type()->is_ptr()->add_offset(offset);
 716     assert(atype->isa_oop_ptr(), "still an oop");
 717   }
 718   offset = atype->is_ptr()->_offset;
 719   if (offset != Type::OffsetBot)  offset += disp32;
 720   return offset;
 721 }
 722 
 723 static inline jdouble replicate_immI(int con, int count, int width) {
 724   // Load a constant replicated "count" times with width "width"
 725   assert(count*width == 8 && width <= 4, "sanity");
 726   int bit_width = width * 8;
 727   jlong val = con;
 728   val &= (((jlong) 1) << bit_width) - 1;  // mask off sign bits
 729   for (int i = 0; i < count - 1; i++) {
 730     val |= (val << bit_width);
 731   }
 732   jdouble dval = *((jdouble*) &val);  // coerce to double type
 733   return dval;
 734 }
 735 
 736 static inline jdouble replicate_immF(float con) {
 737   // Replicate float con 2 times and pack into vector.
 738   int val = *((int*)&con);
 739   jlong lval = val;
 740   lval = (lval << 32) | (lval & 0xFFFFFFFFl);
 741   jdouble dval = *((jdouble*) &lval);  // coerce to double type
 742   return dval;
 743 }
 744 
 745 // Standard Sparc opcode form2 field breakdown
 746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
 747   f0 &= (1<<19)-1;     // Mask displacement to 19 bits
 748   int op = (f30 << 30) |
 749            (f29 << 29) |
 750            (f25 << 25) |
 751            (f22 << 22) |
 752            (f20 << 20) |
 753            (f19 << 19) |
 754            (f0  <<  0);
 755   cbuf.insts()->emit_int32(op);
 756 }
 757 
 758 // Standard Sparc opcode form2 field breakdown
 759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
 760   f0 >>= 10;           // Drop 10 bits
 761   f0 &= (1<<22)-1;     // Mask displacement to 22 bits
 762   int op = (f30 << 30) |
 763            (f25 << 25) |
 764            (f22 << 22) |
 765            (f0  <<  0);
 766   cbuf.insts()->emit_int32(op);
 767 }
 768 
 769 // Standard Sparc opcode form3 field breakdown
 770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
 771   int op = (f30 << 30) |
 772            (f25 << 25) |
 773            (f19 << 19) |
 774            (f14 << 14) |
 775            (f5  <<  5) |
 776            (f0  <<  0);
 777   cbuf.insts()->emit_int32(op);
 778 }
 779 
 780 // Standard Sparc opcode form3 field breakdown
 781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
 782   simm13 &= (1<<13)-1; // Mask to 13 bits
 783   int op = (f30 << 30) |
 784            (f25 << 25) |
 785            (f19 << 19) |
 786            (f14 << 14) |
 787            (1   << 13) | // bit to indicate immediate-mode
 788            (simm13<<0);
 789   cbuf.insts()->emit_int32(op);
 790 }
 791 
 792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
 793   simm10 &= (1<<10)-1; // Mask to 10 bits
 794   emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
 795 }
 796 
 797 #ifdef ASSERT
 798 // Helper function for VerifyOops in emit_form3_mem_reg
 799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
 800   warning("VerifyOops encountered unexpected instruction:");
 801   n->dump(2);
 802   warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
 803 }
 804 #endif
 805 
 806 
 807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
 808                         int src1_enc, int disp32, int src2_enc, int dst_enc) {
 809 
 810 #ifdef ASSERT
 811   // The following code implements the +VerifyOops feature.
 812   // It verifies oop values which are loaded into or stored out of
 813   // the current method activation.  +VerifyOops complements techniques
 814   // like ScavengeALot, because it eagerly inspects oops in transit,
 815   // as they enter or leave the stack, as opposed to ScavengeALot,
 816   // which inspects oops "at rest", in the stack or heap, at safepoints.
 817   // For this reason, +VerifyOops can sometimes detect bugs very close
 818   // to their point of creation.  It can also serve as a cross-check
 819   // on the validity of oop maps, when used toegether with ScavengeALot.
 820 
 821   // It would be good to verify oops at other points, especially
 822   // when an oop is used as a base pointer for a load or store.
 823   // This is presently difficult, because it is hard to know when
 824   // a base address is biased or not.  (If we had such information,
 825   // it would be easy and useful to make a two-argument version of
 826   // verify_oop which unbiases the base, and performs verification.)
 827 
 828   assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
 829   bool is_verified_oop_base  = false;
 830   bool is_verified_oop_load  = false;
 831   bool is_verified_oop_store = false;
 832   int tmp_enc = -1;
 833   if (VerifyOops && src1_enc != R_SP_enc) {
 834     // classify the op, mainly for an assert check
 835     int st_op = 0, ld_op = 0;
 836     switch (primary) {
 837     case Assembler::stb_op3:  st_op = Op_StoreB; break;
 838     case Assembler::sth_op3:  st_op = Op_StoreC; break;
 839     case Assembler::stx_op3:  // may become StoreP or stay StoreI or StoreD0
 840     case Assembler::stw_op3:  st_op = Op_StoreI; break;
 841     case Assembler::std_op3:  st_op = Op_StoreL; break;
 842     case Assembler::stf_op3:  st_op = Op_StoreF; break;
 843     case Assembler::stdf_op3: st_op = Op_StoreD; break;
 844 
 845     case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
 846     case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
 847     case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
 848     case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
 849     case Assembler::ldx_op3:  // may become LoadP or stay LoadI
 850     case Assembler::ldsw_op3: // may become LoadP or stay LoadI
 851     case Assembler::lduw_op3: ld_op = Op_LoadI; break;
 852     case Assembler::ldd_op3:  ld_op = Op_LoadL; break;
 853     case Assembler::ldf_op3:  ld_op = Op_LoadF; break;
 854     case Assembler::lddf_op3: ld_op = Op_LoadD; break;
 855     case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
 856 
 857     default: ShouldNotReachHere();
 858     }
 859     if (tertiary == REGP_OP) {
 860       if      (st_op == Op_StoreI)  st_op = Op_StoreP;
 861       else if (ld_op == Op_LoadI)   ld_op = Op_LoadP;
 862       else                          ShouldNotReachHere();
 863       if (st_op) {
 864         // a store
 865         // inputs are (0:control, 1:memory, 2:address, 3:value)
 866         Node* n2 = n->in(3);
 867         if (n2 != NULL) {
 868           const Type* t = n2->bottom_type();
 869           is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
 870         }
 871       } else {
 872         // a load
 873         const Type* t = n->bottom_type();
 874         is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
 875       }
 876     }
 877 
 878     if (ld_op) {
 879       // a Load
 880       // inputs are (0:control, 1:memory, 2:address)
 881       if (!(n->ideal_Opcode()==ld_op)       && // Following are special cases
 882           !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
 883           !(n->ideal_Opcode()==Op_LoadI     && ld_op==Op_LoadF) &&
 884           !(n->ideal_Opcode()==Op_LoadF     && ld_op==Op_LoadI) &&
 885           !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
 886           !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
 887           !(n->ideal_Opcode()==Op_LoadL     && ld_op==Op_LoadI) &&
 888           !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
 889           !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
 890           !(n->ideal_Opcode()==Op_ConvI2F   && ld_op==Op_LoadF) &&
 891           !(n->ideal_Opcode()==Op_ConvI2D   && ld_op==Op_LoadF) &&
 892           !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
 893           !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
 894           !(n->rule() == loadUB_rule)) {
 895         verify_oops_warning(n, n->ideal_Opcode(), ld_op);
 896       }
 897     } else if (st_op) {
 898       // a Store
 899       // inputs are (0:control, 1:memory, 2:address, 3:value)
 900       if (!(n->ideal_Opcode()==st_op)    && // Following are special cases
 901           !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
 902           !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
 903           !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
 904           !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
 905           !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
 906           !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
 907         verify_oops_warning(n, n->ideal_Opcode(), st_op);
 908       }
 909     }
 910 
 911     if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
 912       Node* addr = n->in(2);
 913       if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
 914         const TypeOopPtr* atype = addr->bottom_type()->isa_instptr();  // %%% oopptr?
 915         if (atype != NULL) {
 916           intptr_t offset = get_offset_from_base(n, atype, disp32);
 917           intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
 918           if (offset != offset_2) {
 919             get_offset_from_base(n, atype, disp32);
 920             get_offset_from_base_2(n, atype, disp32);
 921           }
 922           assert(offset == offset_2, "different offsets");
 923           if (offset == disp32) {
 924             // we now know that src1 is a true oop pointer
 925             is_verified_oop_base = true;
 926             if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
 927               if( primary == Assembler::ldd_op3 ) {
 928                 is_verified_oop_base = false; // Cannot 'ldd' into O7
 929               } else {
 930                 tmp_enc = dst_enc;
 931                 dst_enc = R_O7_enc; // Load into O7; preserve source oop
 932                 assert(src1_enc != dst_enc, "");
 933               }
 934             }
 935           }
 936           if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
 937                        || offset == oopDesc::mark_offset_in_bytes())) {
 938                       // loading the mark should not be allowed either, but
 939                       // we don't check this since it conflicts with InlineObjectHash
 940                       // usage of LoadINode to get the mark. We could keep the
 941                       // check if we create a new LoadMarkNode
 942             // but do not verify the object before its header is initialized
 943             ShouldNotReachHere();
 944           }
 945         }
 946       }
 947     }
 948   }
 949 #endif
 950 
 951   uint instr = (Assembler::ldst_op << 30)
 952              | (dst_enc        << 25)
 953              | (primary        << 19)
 954              | (src1_enc       << 14);
 955 
 956   uint index = src2_enc;
 957   int disp = disp32;
 958 
 959   if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
 960     disp += STACK_BIAS;
 961     // Check that stack offset fits, load into O7 if not
 962     if (!Assembler::is_simm13(disp)) {
 963       MacroAssembler _masm(&cbuf);
 964       __ set(disp, O7);
 965       if (index != R_G0_enc) {
 966         __ add(O7, reg_to_register_object(index), O7);
 967       }
 968       index = R_O7_enc;
 969       disp = 0;
 970     }
 971   }
 972 
 973   if( disp == 0 ) {
 974     // use reg-reg form
 975     // bit 13 is already zero
 976     instr |= index;
 977   } else {
 978     // use reg-imm form
 979     instr |= 0x00002000;          // set bit 13 to one
 980     instr |= disp & 0x1FFF;
 981   }
 982 
 983   cbuf.insts()->emit_int32(instr);
 984 
 985 #ifdef ASSERT
 986   if (VerifyOops) {
 987     MacroAssembler _masm(&cbuf);
 988     if (is_verified_oop_base) {
 989       __ verify_oop(reg_to_register_object(src1_enc));
 990     }
 991     if (is_verified_oop_store) {
 992       __ verify_oop(reg_to_register_object(dst_enc));
 993     }
 994     if (tmp_enc != -1) {
 995       __ mov(O7, reg_to_register_object(tmp_enc));
 996     }
 997     if (is_verified_oop_load) {
 998       __ verify_oop(reg_to_register_object(dst_enc));
 999     }
1000   }
1001 #endif
1002 }
1003 
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, RelocationHolder const& rspec, bool preserve_g2 = false) {
1005   // The method which records debug information at every safepoint
1006   // expects the call to be the first instruction in the snippet as
1007   // it creates a PcDesc structure which tracks the offset of a call
1008   // from the start of the codeBlob. This offset is computed as
1009   // code_end() - code_begin() of the code which has been emitted
1010   // so far.
1011   // In this particular case we have skirted around the problem by
1012   // putting the "mov" instruction in the delay slot but the problem
1013   // may bite us again at some other point and a cleaner/generic
1014   // solution using relocations would be needed.
1015   MacroAssembler _masm(&cbuf);
1016   __ set_inst_mark();
1017 
1018   // We flush the current window just so that there is a valid stack copy
1019   // the fact that the current window becomes active again instantly is
1020   // not a problem there is nothing live in it.
1021 
1022 #ifdef ASSERT
1023   int startpos = __ offset();
1024 #endif /* ASSERT */
1025 
1026   __ call((address)entry_point, rspec);
1027 
1028   if (preserve_g2)   __ delayed()->mov(G2, L7);
1029   else __ delayed()->nop();
1030 
1031   if (preserve_g2)   __ mov(L7, G2);
1032 
1033 #ifdef ASSERT
1034   if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1035 #ifdef _LP64
1036     // Trash argument dump slots.
1037     __ set(0xb0b8ac0db0b8ac0d, G1);
1038     __ mov(G1, G5);
1039     __ stx(G1, SP, STACK_BIAS + 0x80);
1040     __ stx(G1, SP, STACK_BIAS + 0x88);
1041     __ stx(G1, SP, STACK_BIAS + 0x90);
1042     __ stx(G1, SP, STACK_BIAS + 0x98);
1043     __ stx(G1, SP, STACK_BIAS + 0xA0);
1044     __ stx(G1, SP, STACK_BIAS + 0xA8);
1045 #else // _LP64
1046     // this is also a native call, so smash the first 7 stack locations,
1047     // and the various registers
1048 
1049     // Note:  [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1050     // while [SP+0x44..0x58] are the argument dump slots.
1051     __ set((intptr_t)0xbaadf00d, G1);
1052     __ mov(G1, G5);
1053     __ sllx(G1, 32, G1);
1054     __ or3(G1, G5, G1);
1055     __ mov(G1, G5);
1056     __ stx(G1, SP, 0x40);
1057     __ stx(G1, SP, 0x48);
1058     __ stx(G1, SP, 0x50);
1059     __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1060 #endif // _LP64
1061   }
1062 #endif /*ASSERT*/
1063 }
1064 
1065 //=============================================================================
1066 // REQUIRED FUNCTIONALITY for encoding
1067 void emit_lo(CodeBuffer &cbuf, int val) {  }
1068 void emit_hi(CodeBuffer &cbuf, int val) {  }
1069 
1070 
1071 //=============================================================================
1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1073 
1074 int Compile::ConstantTable::calculate_table_base_offset() const {
1075   if (UseRDPCForConstantTableBase) {
1076     // The table base offset might be less but then it fits into
1077     // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1078     return Assembler::min_simm13();
1079   } else {
1080     int offset = -(size() / 2);
1081     if (!Assembler::is_simm13(offset)) {
1082       offset = Assembler::min_simm13();
1083     }
1084     return offset;
1085   }
1086 }
1087 
1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1090   ShouldNotReachHere();
1091 }
1092 
1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1094   Compile* C = ra_->C;
1095   Compile::ConstantTable& constant_table = C->constant_table();
1096   MacroAssembler _masm(&cbuf);
1097 
1098   Register r = as_Register(ra_->get_encode(this));
1099   CodeSection* consts_section = __ code()->consts();
1100   int consts_size = consts_section->align_at_start(consts_section->size());
1101   assert(constant_table.size() == consts_size, "must be: %d == %d", constant_table.size(), consts_size);
1102 
1103   if (UseRDPCForConstantTableBase) {
1104     // For the following RDPC logic to work correctly the consts
1105     // section must be allocated right before the insts section.  This
1106     // assert checks for that.  The layout and the SECT_* constants
1107     // are defined in src/share/vm/asm/codeBuffer.hpp.
1108     assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1109     int insts_offset = __ offset();
1110 
1111     // Layout:
1112     //
1113     // |----------- consts section ------------|----------- insts section -----------...
1114     // |------ constant table -----|- padding -|------------------x----
1115     //                                                            \ current PC (RDPC instruction)
1116     // |<------------- consts_size ----------->|<- insts_offset ->|
1117     //                                                            \ table base
1118     // The table base offset is later added to the load displacement
1119     // so it has to be negative.
1120     int table_base_offset = -(consts_size + insts_offset);
1121     int disp;
1122 
1123     // If the displacement from the current PC to the constant table
1124     // base fits into simm13 we set the constant table base to the
1125     // current PC.
1126     if (Assembler::is_simm13(table_base_offset)) {
1127       constant_table.set_table_base_offset(table_base_offset);
1128       disp = 0;
1129     } else {
1130       // Otherwise we set the constant table base offset to the
1131       // maximum negative displacement of load instructions to keep
1132       // the disp as small as possible:
1133       //
1134       // |<------------- consts_size ----------->|<- insts_offset ->|
1135       // |<--------- min_simm13 --------->|<-------- disp --------->|
1136       //                                  \ table base
1137       table_base_offset = Assembler::min_simm13();
1138       constant_table.set_table_base_offset(table_base_offset);
1139       disp = (consts_size + insts_offset) + table_base_offset;
1140     }
1141 
1142     __ rdpc(r);
1143 
1144     if (disp != 0) {
1145       assert(r != O7, "need temporary");
1146       __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1147     }
1148   }
1149   else {
1150     // Materialize the constant table base.
1151     address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1152     RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1153     AddressLiteral base(baseaddr, rspec);
1154     __ set(base, r);
1155   }
1156 }
1157 
1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1159   if (UseRDPCForConstantTableBase) {
1160     // This is really the worst case but generally it's only 1 instruction.
1161     return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1162   } else {
1163     return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1164   }
1165 }
1166 
1167 #ifndef PRODUCT
1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1169   char reg[128];
1170   ra_->dump_register(this, reg);
1171   if (UseRDPCForConstantTableBase) {
1172     st->print("RDPC   %s\t! constant table base", reg);
1173   } else {
1174     st->print("SET    &constanttable,%s\t! constant table base", reg);
1175   }
1176 }
1177 #endif
1178 
1179 
1180 //=============================================================================
1181 
1182 #ifndef PRODUCT
1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184   Compile* C = ra_->C;
1185 
1186   for (int i = 0; i < OptoPrologueNops; i++) {
1187     st->print_cr("NOP"); st->print("\t");
1188   }
1189 
1190   if( VerifyThread ) {
1191     st->print_cr("Verify_Thread"); st->print("\t");
1192   }
1193 
1194   size_t framesize = C->frame_size_in_bytes();
1195   int bangsize = C->bang_size_in_bytes();
1196 
1197   // Calls to C2R adapters often do not accept exceptional returns.
1198   // We require that their callers must bang for them.  But be careful, because
1199   // some VM calls (such as call site linkage) can use several kilobytes of
1200   // stack.  But the stack safety zone should account for that.
1201   // See bugs 4446381, 4468289, 4497237.
1202   if (C->need_stack_bang(bangsize)) {
1203     st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1204   }
1205 
1206   if (Assembler::is_simm13(-framesize)) {
1207     st->print   ("SAVE   R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1208   } else {
1209     st->print_cr("SETHI  R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1210     st->print_cr("ADD    R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1211     st->print   ("SAVE   R_SP,R_G3,R_SP");
1212   }
1213 
1214 }
1215 #endif
1216 
1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1218   Compile* C = ra_->C;
1219   MacroAssembler _masm(&cbuf);
1220 
1221   for (int i = 0; i < OptoPrologueNops; i++) {
1222     __ nop();
1223   }
1224 
1225   __ verify_thread();
1226 
1227   size_t framesize = C->frame_size_in_bytes();
1228   assert(framesize >= 16*wordSize, "must have room for reg. save area");
1229   assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1230   int bangsize = C->bang_size_in_bytes();
1231 
1232   // Calls to C2R adapters often do not accept exceptional returns.
1233   // We require that their callers must bang for them.  But be careful, because
1234   // some VM calls (such as call site linkage) can use several kilobytes of
1235   // stack.  But the stack safety zone should account for that.
1236   // See bugs 4446381, 4468289, 4497237.
1237   if (C->need_stack_bang(bangsize)) {
1238     __ generate_stack_overflow_check(bangsize);
1239   }
1240 
1241   if (Assembler::is_simm13(-framesize)) {
1242     __ save(SP, -framesize, SP);
1243   } else {
1244     __ sethi(-framesize & ~0x3ff, G3);
1245     __ add(G3, -framesize & 0x3ff, G3);
1246     __ save(SP, G3, SP);
1247   }
1248   C->set_frame_complete( __ offset() );
1249 
1250   if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1251     // NOTE: We set the table base offset here because users might be
1252     // emitted before MachConstantBaseNode.
1253     Compile::ConstantTable& constant_table = C->constant_table();
1254     constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1255   }
1256 }
1257 
1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1259   return MachNode::size(ra_);
1260 }
1261 
1262 int MachPrologNode::reloc() const {
1263   return 10; // a large enough number
1264 }
1265 
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1269   Compile* C = ra_->C;
1270 
1271   if(do_polling() && ra_->C->is_method_compilation()) {
1272     st->print("SETHI  #PollAddr,L0\t! Load Polling address\n\t");
1273 #ifdef _LP64
1274     st->print("LDX    [L0],G0\t!Poll for Safepointing\n\t");
1275 #else
1276     st->print("LDUW   [L0],G0\t!Poll for Safepointing\n\t");
1277 #endif
1278   }
1279 
1280   if(do_polling()) {
1281     if (UseCBCond && !ra_->C->is_method_compilation()) {
1282       st->print("NOP\n\t");
1283     }
1284     st->print("RET\n\t");
1285   }
1286 
1287   st->print("RESTORE");
1288 }
1289 #endif
1290 
1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1292   MacroAssembler _masm(&cbuf);
1293   Compile* C = ra_->C;
1294 
1295   __ verify_thread();
1296 
1297   if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
1298     __ reserved_stack_check();
1299   }
1300 
1301   // If this does safepoint polling, then do it here
1302   if(do_polling() && ra_->C->is_method_compilation()) {
1303     AddressLiteral polling_page(os::get_polling_page());
1304     __ sethi(polling_page, L0);
1305     __ relocate(relocInfo::poll_return_type);
1306     __ ld_ptr(L0, 0, G0);
1307   }
1308 
1309   // If this is a return, then stuff the restore in the delay slot
1310   if(do_polling()) {
1311     if (UseCBCond && !ra_->C->is_method_compilation()) {
1312       // Insert extra padding for the case when the epilogue is preceded by
1313       // a cbcond jump, which can't be followed by a CTI instruction
1314       __ nop();
1315     }
1316     __ ret();
1317     __ delayed()->restore();
1318   } else {
1319     __ restore();
1320   }
1321 }
1322 
1323 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1324   return MachNode::size(ra_);
1325 }
1326 
1327 int MachEpilogNode::reloc() const {
1328   return 16; // a large enough number
1329 }
1330 
1331 const Pipeline * MachEpilogNode::pipeline() const {
1332   return MachNode::pipeline_class();
1333 }
1334 
1335 int MachEpilogNode::safepoint_offset() const {
1336   assert( do_polling(), "no return for this epilog node");
1337   return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1338 }
1339 
1340 //=============================================================================
1341 
1342 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1343 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1344 static enum RC rc_class( OptoReg::Name reg ) {
1345   if (!OptoReg::is_valid(reg)) return rc_bad;
1346   if (OptoReg::is_stack(reg)) return rc_stack;
1347   VMReg r = OptoReg::as_VMReg(reg);
1348   if (r->is_Register()) return rc_int;
1349   assert(r->is_FloatRegister(), "must be");
1350   return rc_float;
1351 }
1352 
1353 #ifndef PRODUCT
1354 ATTRIBUTE_PRINTF(2, 3)
1355 static void print_helper(outputStream* st, const char* format, ...) {
1356   if (st->position() > 0) {
1357     st->cr();
1358     st->sp();
1359   }
1360   va_list ap;
1361   va_start(ap, format);
1362   st->vprint(format, ap);
1363   va_end(ap);
1364 }
1365 #endif // !PRODUCT
1366 
1367 static void impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool is_load, int offset, int reg, int opcode, const char *op_str, outputStream* st) {
1368   if (cbuf) {
1369     emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1370   }
1371 #ifndef PRODUCT
1372   else {
1373     if (is_load) {
1374       print_helper(st, "%s   [R_SP + #%d],R_%s\t! spill", op_str, offset, OptoReg::regname(reg));
1375     } else {
1376       print_helper(st, "%s   R_%s,[R_SP + #%d]\t! spill", op_str, OptoReg::regname(reg), offset);
1377     }
1378   }
1379 #endif
1380 }
1381 
1382 static void impl_mov_helper(CodeBuffer *cbuf, int src, int dst, int op1, int op2, const char *op_str, outputStream* st) {
1383   if (cbuf) {
1384     emit3(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src]);
1385   }
1386 #ifndef PRODUCT
1387   else {
1388     print_helper(st, "%s  R_%s,R_%s\t! spill", op_str, OptoReg::regname(src), OptoReg::regname(dst));
1389   }
1390 #endif
1391 }
1392 
1393 static void mach_spill_copy_implementation_helper(const MachNode* mach,
1394                                                   CodeBuffer *cbuf,
1395                                                   PhaseRegAlloc *ra_,
1396                                                   outputStream* st) {
1397   // Get registers to move
1398   OptoReg::Name src_second = ra_->get_reg_second(mach->in(1));
1399   OptoReg::Name src_first  = ra_->get_reg_first(mach->in(1));
1400   OptoReg::Name dst_second = ra_->get_reg_second(mach);
1401   OptoReg::Name dst_first  = ra_->get_reg_first(mach);
1402 
1403   enum RC src_second_rc = rc_class(src_second);
1404   enum RC src_first_rc  = rc_class(src_first);
1405   enum RC dst_second_rc = rc_class(dst_second);
1406   enum RC dst_first_rc  = rc_class(dst_first);
1407 
1408   assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register");
1409 
1410   if (src_first == dst_first && src_second == dst_second) {
1411     return; // Self copy, no move
1412   }
1413 
1414   // --------------------------------------
1415   // Check for mem-mem move.  Load into unused float registers and fall into
1416   // the float-store case.
1417   if (src_first_rc == rc_stack && dst_first_rc == rc_stack) {
1418     int offset = ra_->reg2offset(src_first);
1419     // Further check for aligned-adjacent pair, so we can use a double load
1420     if ((src_first&1) == 0 && src_first+1 == src_second) {
1421       src_second    = OptoReg::Name(R_F31_num);
1422       src_second_rc = rc_float;
1423       impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::lddf_op3, "LDDF", st);
1424     } else {
1425       impl_helper(mach, cbuf, ra_, true, offset, R_F30_num, Assembler::ldf_op3, "LDF ", st);
1426     }
1427     src_first    = OptoReg::Name(R_F30_num);
1428     src_first_rc = rc_float;
1429   }
1430 
1431   if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1432     int offset = ra_->reg2offset(src_second);
1433     impl_helper(mach, cbuf, ra_, true, offset, R_F31_num, Assembler::ldf_op3, "LDF ", st);
1434     src_second    = OptoReg::Name(R_F31_num);
1435     src_second_rc = rc_float;
1436   }
1437 
1438   // --------------------------------------
1439   // Check for float->int copy; requires a trip through memory
1440   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1441     int offset = frame::register_save_words*wordSize;
1442     if (cbuf) {
1443       emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16);
1444       impl_helper(mach, cbuf, ra_, false, offset, src_first,  Assembler::stf_op3, "STF ", st);
1445       impl_helper(mach, cbuf, ra_,  true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1446       emit3_simm13(*cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16);
1447     }
1448 #ifndef PRODUCT
1449     else {
1450       print_helper(st, "SUB    R_SP,16,R_SP");
1451       impl_helper(mach, cbuf, ra_, false, offset, src_first,  Assembler::stf_op3, "STF ", st);
1452       impl_helper(mach, cbuf, ra_,  true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1453       print_helper(st, "ADD    R_SP,16,R_SP");
1454     }
1455 #endif
1456   }
1457 
1458   // Check for float->int copy on T4
1459   if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1460     // Further check for aligned-adjacent pair, so we can use a double move
1461     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1462       impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mdtox_opf, "MOVDTOX", st);
1463       return;
1464     }
1465     impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mstouw_opf, "MOVSTOUW", st);
1466   }
1467   // Check for int->float copy on T4
1468   if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1469     // Further check for aligned-adjacent pair, so we can use a double move
1470     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1471       impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mxtod_opf, "MOVXTOD", st);
1472       return;
1473     }
1474     impl_mov_helper(cbuf, src_first, dst_first, Assembler::mftoi_op3, Assembler::mwtos_opf, "MOVWTOS", st);
1475   }
1476 
1477   // --------------------------------------
1478   // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1479   // In such cases, I have to do the big-endian swap.  For aligned targets, the
1480   // hardware does the flop for me.  Doubles are always aligned, so no problem
1481   // there.  Misaligned sources only come from native-long-returns (handled
1482   // special below).
1483 #ifndef _LP64
1484   if (src_first_rc == rc_int &&     // source is already big-endian
1485       src_second_rc != rc_bad &&    // 64-bit move
1486       ((dst_first & 1) != 0 || dst_second != dst_first + 1)) { // misaligned dst
1487     assert((src_first & 1) == 0 && src_second == src_first + 1, "source must be aligned");
1488     // Do the big-endian flop.
1489     OptoReg::Name tmp    = dst_first   ; dst_first    = dst_second   ; dst_second    = tmp   ;
1490     enum RC       tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1491   }
1492 #endif
1493 
1494   // --------------------------------------
1495   // Check for integer reg-reg copy
1496   if (src_first_rc == rc_int && dst_first_rc == rc_int) {
1497 #ifndef _LP64
1498     if (src_first == R_O0_num && src_second == R_O1_num) {  // Check for the evil O0/O1 native long-return case
1499       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1500       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
1501       //       operand contains the least significant word of the 64-bit value and vice versa.
1502       OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1503       assert((dst_first & 1) == 0 && dst_second == dst_first + 1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1504       // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1505       if ( cbuf ) {
1506         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020);
1507         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000);
1508         emit3       (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second]);
1509 #ifndef PRODUCT
1510       } else {
1511         print_helper(st, "SLLX   R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1512         print_helper(st, "SRL    R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1513         print_helper(st, "OR     R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1514 #endif
1515       }
1516       return;
1517     } else if (dst_first == R_I0_num && dst_second == R_I1_num) {
1518       // returning a long value in I0/I1
1519       // a SpillCopy must be able to target a return instruction's reg_class
1520       // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1521       //       as stored in memory.  On a big-endian machine like SPARC, this means that the _second
1522       //       operand contains the least significant word of the 64-bit value and vice versa.
1523       OptoReg::Name tdest = dst_first;
1524 
1525       if (src_first == dst_first) {
1526         tdest = OptoReg::Name(R_O7_num);
1527       }
1528 
1529       if (cbuf) {
1530         assert((src_first & 1) == 0 && (src_first + 1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1531         // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1532         // ShrL_reg_imm6
1533         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000);
1534         // ShrR_reg_imm6  src, 0, dst
1535         emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000);
1536         if (tdest != dst_first) {
1537           emit3     (*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest]);
1538         }
1539       }
1540 #ifndef PRODUCT
1541       else {
1542         print_helper(st, "SRLX   R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1543         print_helper(st, "SRL    R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1544         if (tdest != dst_first) {
1545           print_helper(st, "MOV    R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1546         }
1547       }
1548 #endif // PRODUCT
1549       return size+8;
1550     }
1551 #endif // !_LP64
1552     // Else normal reg-reg copy
1553     assert(src_second != dst_first, "smashed second before evacuating it");
1554     impl_mov_helper(cbuf, src_first, dst_first, Assembler::or_op3, 0, "MOV  ", st);
1555     assert((src_first & 1) == 0 && (dst_first & 1) == 0, "never move second-halves of int registers");
1556     // This moves an aligned adjacent pair.
1557     // See if we are done.
1558     if (src_first + 1 == src_second && dst_first + 1 == dst_second) {
1559       return;
1560     }
1561   }
1562 
1563   // Check for integer store
1564   if (src_first_rc == rc_int && dst_first_rc == rc_stack) {
1565     int offset = ra_->reg2offset(dst_first);
1566     // Further check for aligned-adjacent pair, so we can use a double store
1567     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1568       impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stx_op3, "STX ", st);
1569       return;
1570     }
1571     impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stw_op3, "STW ", st);
1572   }
1573 
1574   // Check for integer load
1575   if (dst_first_rc == rc_int && src_first_rc == rc_stack) {
1576     int offset = ra_->reg2offset(src_first);
1577     // Further check for aligned-adjacent pair, so we can use a double load
1578     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1579       impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldx_op3, "LDX ", st);
1580       return;
1581     }
1582     impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lduw_op3, "LDUW", st);
1583   }
1584 
1585   // Check for float reg-reg copy
1586   if (src_first_rc == rc_float && dst_first_rc == rc_float) {
1587     // Further check for aligned-adjacent pair, so we can use a double move
1588     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1589       impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovd_opf, "FMOVD", st);
1590       return;
1591     }
1592     impl_mov_helper(cbuf, src_first, dst_first, Assembler::fpop1_op3, Assembler::fmovs_opf, "FMOVS", st);
1593   }
1594 
1595   // Check for float store
1596   if (src_first_rc == rc_float && dst_first_rc == rc_stack) {
1597     int offset = ra_->reg2offset(dst_first);
1598     // Further check for aligned-adjacent pair, so we can use a double store
1599     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1600       impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stdf_op3, "STDF", st);
1601       return;
1602     }
1603     impl_helper(mach, cbuf, ra_, false, offset, src_first, Assembler::stf_op3, "STF ", st);
1604   }
1605 
1606   // Check for float load
1607   if (dst_first_rc == rc_float && src_first_rc == rc_stack) {
1608     int offset = ra_->reg2offset(src_first);
1609     // Further check for aligned-adjacent pair, so we can use a double load
1610     if ((src_first & 1) == 0 && src_first + 1 == src_second && (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1611       impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::lddf_op3, "LDDF", st);
1612       return;
1613     }
1614     impl_helper(mach, cbuf, ra_, true, offset, dst_first, Assembler::ldf_op3, "LDF ", st);
1615   }
1616 
1617   // --------------------------------------------------------------------
1618   // Check for hi bits still needing moving.  Only happens for misaligned
1619   // arguments to native calls.
1620   if (src_second == dst_second) {
1621     return; // Self copy; no move
1622   }
1623   assert(src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad");
1624 
1625 #ifndef _LP64
1626   // In the LP64 build, all registers can be moved as aligned/adjacent
1627   // pairs, so there's never any need to move the high bits separately.
1628   // The 32-bit builds have to deal with the 32-bit ABI which can force
1629   // all sorts of silly alignment problems.
1630 
1631   // Check for integer reg-reg copy.  Hi bits are stuck up in the top
1632   // 32-bits of a 64-bit register, but are needed in low bits of another
1633   // register (else it's a hi-bits-to-hi-bits copy which should have
1634   // happened already as part of a 64-bit move)
1635   if (src_second_rc == rc_int && dst_second_rc == rc_int) {
1636     assert((src_second & 1) == 1, "its the evil O0/O1 native return case");
1637     assert((dst_second & 1) == 0, "should have moved with 1 64-bit move");
1638     // Shift src_second down to dst_second's low bits.
1639     if (cbuf) {
1640       emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1641 #ifndef PRODUCT
1642     } else  {
1643       print_helper(st, "SRLX   R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second - 1), OptoReg::regname(dst_second));
1644 #endif
1645     }
1646     return;
1647   }
1648 
1649   // Check for high word integer store.  Must down-shift the hi bits
1650   // into a temp register, then fall into the case of storing int bits.
1651   if (src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second & 1) == 1) {
1652     // Shift src_second down to dst_second's low bits.
1653     if (cbuf) {
1654       emit3_simm13(*cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020);
1655 #ifndef PRODUCT
1656     } else {
1657       print_helper(st, "SRLX   R_%s,32,R_%s\t! spill: Move high bits down low", OptoReg::regname(src_second-1), OptoReg::regname(R_O7_num));
1658 #endif
1659     }
1660     src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1661   }
1662 
1663   // Check for high word integer load
1664   if (dst_second_rc == rc_int && src_second_rc == rc_stack)
1665     return impl_helper(this, cbuf, ra_, true, ra_->reg2offset(src_second), dst_second, Assembler::lduw_op3, "LDUW", size, st);
1666 
1667   // Check for high word integer store
1668   if (src_second_rc == rc_int && dst_second_rc == rc_stack)
1669     return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stw_op3, "STW ", size, st);
1670 
1671   // Check for high word float store
1672   if (src_second_rc == rc_float && dst_second_rc == rc_stack)
1673     return impl_helper(this, cbuf, ra_, false, ra_->reg2offset(dst_second), src_second, Assembler::stf_op3, "STF ", size, st);
1674 
1675 #endif // !_LP64
1676 
1677   Unimplemented();
1678 }
1679 
1680 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf,
1681                                        PhaseRegAlloc *ra_,
1682                                        bool do_size,
1683                                        outputStream* st) const {
1684   assert(!do_size, "not supported");
1685   mach_spill_copy_implementation_helper(this, cbuf, ra_, st);
1686   return 0;
1687 }
1688 
1689 #ifndef PRODUCT
1690 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1691   implementation( NULL, ra_, false, st );
1692 }
1693 #endif
1694 
1695 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1696   implementation( &cbuf, ra_, false, NULL );
1697 }
1698 
1699 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1700   return MachNode::size(ra_);
1701 }
1702 
1703 //=============================================================================
1704 #ifndef PRODUCT
1705 void MachNopNode::format(PhaseRegAlloc *, outputStream *st) const {
1706   st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1707 }
1708 #endif
1709 
1710 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const {
1711   MacroAssembler _masm(&cbuf);
1712   for (int i = 0; i < _count; i += 1) {
1713     __ nop();
1714   }
1715 }
1716 
1717 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1718   return 4 * _count;
1719 }
1720 
1721 
1722 //=============================================================================
1723 #ifndef PRODUCT
1724 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1725   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1726   int reg = ra_->get_reg_first(this);
1727   st->print("LEA    [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1728 }
1729 #endif
1730 
1731 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1732   MacroAssembler _masm(&cbuf);
1733   int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1734   int reg = ra_->get_encode(this);
1735 
1736   if (Assembler::is_simm13(offset)) {
1737      __ add(SP, offset, reg_to_register_object(reg));
1738   } else {
1739      __ set(offset, O7);
1740      __ add(SP, O7, reg_to_register_object(reg));
1741   }
1742 }
1743 
1744 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1745   // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1746   assert(ra_ == ra_->C->regalloc(), "sanity");
1747   return ra_->C->scratch_emit_size(this);
1748 }
1749 
1750 //=============================================================================
1751 #ifndef PRODUCT
1752 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1753   st->print_cr("\nUEP:");
1754 #ifdef    _LP64
1755   if (UseCompressedClassPointers) {
1756     assert(Universe::heap() != NULL, "java heap should be initialized");
1757     st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1758     if (Universe::narrow_klass_base() != 0) {
1759       st->print_cr("\tSET    Universe::narrow_klass_base,R_G6_heap_base");
1760       if (Universe::narrow_klass_shift() != 0) {
1761         st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");
1762       }
1763       st->print_cr("\tADD    R_G5,R_G6_heap_base,R_G5");
1764       st->print_cr("\tSET    Universe::narrow_ptrs_base,R_G6_heap_base");
1765     } else {
1766       st->print_cr("\tSLL    R_G5,Universe::narrow_klass_shift,R_G5");
1767     }
1768   } else {
1769     st->print_cr("\tLDX    [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1770   }
1771   st->print_cr("\tCMP    R_G5,R_G3" );
1772   st->print   ("\tTne    xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1773 #else  // _LP64
1774   st->print_cr("\tLDUW   [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1775   st->print_cr("\tCMP    R_G5,R_G3" );
1776   st->print   ("\tTne    icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1777 #endif // _LP64
1778 }
1779 #endif
1780 
1781 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1782   MacroAssembler _masm(&cbuf);
1783   Register G5_ic_reg  = reg_to_register_object(Matcher::inline_cache_reg_encode());
1784   Register temp_reg   = G3;
1785   assert( G5_ic_reg != temp_reg, "conflicting registers" );
1786 
1787   // Load klass from receiver
1788   __ load_klass(O0, temp_reg);
1789   // Compare against expected klass
1790   __ cmp(temp_reg, G5_ic_reg);
1791   // Branch to miss code, checks xcc or icc depending
1792   __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1793 }
1794 
1795 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1796   return MachNode::size(ra_);
1797 }
1798 
1799 
1800 //=============================================================================
1801 
1802 
1803 // Emit exception handler code.
1804 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1805   Register temp_reg = G3;
1806   AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1807   MacroAssembler _masm(&cbuf);
1808 
1809   address base = __ start_a_stub(size_exception_handler());
1810   if (base == NULL) {
1811     ciEnv::current()->record_failure("CodeCache is full");
1812     return 0;  // CodeBuffer::expand failed
1813   }
1814 
1815   int offset = __ offset();
1816 
1817   __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1818   __ delayed()->nop();
1819 
1820   assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1821 
1822   __ end_a_stub();
1823 
1824   return offset;
1825 }
1826 
1827 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1828   // Can't use any of the current frame's registers as we may have deopted
1829   // at a poll and everything (including G3) can be live.
1830   Register temp_reg = L0;
1831   AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1832   MacroAssembler _masm(&cbuf);
1833 
1834   address base = __ start_a_stub(size_deopt_handler());
1835   if (base == NULL) {
1836     ciEnv::current()->record_failure("CodeCache is full");
1837     return 0;  // CodeBuffer::expand failed
1838   }
1839 
1840   int offset = __ offset();
1841   __ save_frame(0);
1842   __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1843   __ delayed()->restore();
1844 
1845   assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1846 
1847   __ end_a_stub();
1848   return offset;
1849 
1850 }
1851 
1852 // Given a register encoding, produce a Integer Register object
1853 static Register reg_to_register_object(int register_encoding) {
1854   assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1855   return as_Register(register_encoding);
1856 }
1857 
1858 // Given a register encoding, produce a single-precision Float Register object
1859 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1860   assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1861   return as_SingleFloatRegister(register_encoding);
1862 }
1863 
1864 // Given a register encoding, produce a double-precision Float Register object
1865 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1866   assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1867   assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1868   return as_DoubleFloatRegister(register_encoding);
1869 }
1870 
1871 const bool Matcher::match_rule_supported(int opcode) {
1872   if (!has_match_rule(opcode))
1873     return false;
1874 
1875   switch (opcode) {
1876   case Op_CountLeadingZerosI:
1877   case Op_CountLeadingZerosL:
1878   case Op_CountTrailingZerosI:
1879   case Op_CountTrailingZerosL:
1880   case Op_PopCountI:
1881   case Op_PopCountL:
1882     if (!UsePopCountInstruction)
1883       return false;
1884   case Op_CompareAndSwapL:
1885 #ifdef _LP64
1886   case Op_CompareAndSwapP:
1887 #endif
1888     if (!VM_Version::supports_cx8())
1889       return false;
1890     break;
1891   }
1892 
1893   return true;  // Per default match rules are supported.
1894 }
1895 
1896 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) {
1897 
1898   // TODO
1899   // identify extra cases that we might want to provide match rules for
1900   // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
1901   bool ret_value = match_rule_supported(opcode);
1902   // Add rules here.
1903 
1904   return ret_value;  // Per default match rules are supported.
1905 }
1906 
1907 const int Matcher::float_pressure(int default_pressure_threshold) {
1908   return default_pressure_threshold;
1909 }
1910 
1911 int Matcher::regnum_to_fpu_offset(int regnum) {
1912   return regnum - 32; // The FP registers are in the second chunk
1913 }
1914 
1915 #ifdef ASSERT
1916 address last_rethrow = NULL;  // debugging aid for Rethrow encoding
1917 #endif
1918 
1919 // Vector width in bytes
1920 const int Matcher::vector_width_in_bytes(BasicType bt) {
1921   assert(MaxVectorSize == 8, "");
1922   return 8;
1923 }
1924 
1925 // Vector ideal reg
1926 const int Matcher::vector_ideal_reg(int size) {
1927   assert(MaxVectorSize == 8, "");
1928   return Op_RegD;
1929 }
1930 
1931 const int Matcher::vector_shift_count_ideal_reg(int size) {
1932   fatal("vector shift is not supported");
1933   return Node::NotAMachineReg;
1934 }
1935 
1936 // Limits on vector size (number of elements) loaded into vector.
1937 const int Matcher::max_vector_size(const BasicType bt) {
1938   assert(is_java_primitive(bt), "only primitive type vectors");
1939   return vector_width_in_bytes(bt)/type2aelembytes(bt);
1940 }
1941 
1942 const int Matcher::min_vector_size(const BasicType bt) {
1943   return max_vector_size(bt); // Same as max.
1944 }
1945 
1946 // SPARC doesn't support misaligned vectors store/load.
1947 const bool Matcher::misaligned_vectors_ok() {
1948   return false;
1949 }
1950 
1951 // Current (2013) SPARC platforms need to read original key
1952 // to construct decryption expanded key
1953 const bool Matcher::pass_original_key_for_aes() {
1954   return true;
1955 }
1956 
1957 // USII supports fxtof through the whole range of number, USIII doesn't
1958 const bool Matcher::convL2FSupported(void) {
1959   return VM_Version::has_fast_fxtof();
1960 }
1961 
1962 // Is this branch offset short enough that a short branch can be used?
1963 //
1964 // NOTE: If the platform does not provide any short branch variants, then
1965 //       this method should return false for offset 0.
1966 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1967   // The passed offset is relative to address of the branch.
1968   // Don't need to adjust the offset.
1969   return UseCBCond && Assembler::is_simm12(offset);
1970 }
1971 
1972 const bool Matcher::isSimpleConstant64(jlong value) {
1973   // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1974   // Depends on optimizations in MacroAssembler::setx.
1975   int hi = (int)(value >> 32);
1976   int lo = (int)(value & ~0);
1977   return (hi == 0) || (hi == -1) || (lo == 0);
1978 }
1979 
1980 // No scaling for the parameter the ClearArray node.
1981 const bool Matcher::init_array_count_is_in_bytes = true;
1982 
1983 // Threshold size for cleararray.
1984 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1985 
1986 // No additional cost for CMOVL.
1987 const int Matcher::long_cmove_cost() { return 0; }
1988 
1989 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1990 const int Matcher::float_cmove_cost() {
1991   return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1992 }
1993 
1994 // Does the CPU require late expand (see block.cpp for description of late expand)?
1995 const bool Matcher::require_postalloc_expand = false;
1996 
1997 // Should the Matcher clone shifts on addressing modes, expecting them to
1998 // be subsumed into complex addressing expressions or compute them into
1999 // registers?  True for Intel but false for most RISCs
2000 const bool Matcher::clone_shift_expressions = false;
2001 
2002 // Do we need to mask the count passed to shift instructions or does
2003 // the cpu only look at the lower 5/6 bits anyway?
2004 const bool Matcher::need_masked_shift_count = false;
2005 
2006 bool Matcher::narrow_oop_use_complex_address() {
2007   NOT_LP64(ShouldNotCallThis());
2008   assert(UseCompressedOops, "only for compressed oops code");
2009   return false;
2010 }
2011 
2012 bool Matcher::narrow_klass_use_complex_address() {
2013   NOT_LP64(ShouldNotCallThis());
2014   assert(UseCompressedClassPointers, "only for compressed klass code");
2015   return false;
2016 }
2017 
2018 // Is it better to copy float constants, or load them directly from memory?
2019 // Intel can load a float constant from a direct address, requiring no
2020 // extra registers.  Most RISCs will have to materialize an address into a
2021 // register first, so they would do better to copy the constant from stack.
2022 const bool Matcher::rematerialize_float_constants = false;
2023 
2024 // If CPU can load and store mis-aligned doubles directly then no fixup is
2025 // needed.  Else we split the double into 2 integer pieces and move it
2026 // piece-by-piece.  Only happens when passing doubles into C code as the
2027 // Java calling convention forces doubles to be aligned.
2028 #ifdef _LP64
2029 const bool Matcher::misaligned_doubles_ok = true;
2030 #else
2031 const bool Matcher::misaligned_doubles_ok = false;
2032 #endif
2033 
2034 // No-op on SPARC.
2035 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
2036 }
2037 
2038 // Advertise here if the CPU requires explicit rounding operations
2039 // to implement the UseStrictFP mode.
2040 const bool Matcher::strict_fp_requires_explicit_rounding = false;
2041 
2042 // Are floats converted to double when stored to stack during deoptimization?
2043 // Sparc does not handle callee-save floats.
2044 bool Matcher::float_in_double() { return false; }
2045 
2046 // Do ints take an entire long register or just half?
2047 // Note that we if-def off of _LP64.
2048 // The relevant question is how the int is callee-saved.  In _LP64
2049 // the whole long is written but de-opt'ing will have to extract
2050 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
2051 #ifdef _LP64
2052 const bool Matcher::int_in_long = true;
2053 #else
2054 const bool Matcher::int_in_long = false;
2055 #endif
2056 
2057 // Return whether or not this register is ever used as an argument.  This
2058 // function is used on startup to build the trampoline stubs in generateOptoStub.
2059 // Registers not mentioned will be killed by the VM call in the trampoline, and
2060 // arguments in those registers not be available to the callee.
2061 bool Matcher::can_be_java_arg( int reg ) {
2062   // Standard sparc 6 args in registers
2063   if( reg == R_I0_num ||
2064       reg == R_I1_num ||
2065       reg == R_I2_num ||
2066       reg == R_I3_num ||
2067       reg == R_I4_num ||
2068       reg == R_I5_num ) return true;
2069 #ifdef _LP64
2070   // 64-bit builds can pass 64-bit pointers and longs in
2071   // the high I registers
2072   if( reg == R_I0H_num ||
2073       reg == R_I1H_num ||
2074       reg == R_I2H_num ||
2075       reg == R_I3H_num ||
2076       reg == R_I4H_num ||
2077       reg == R_I5H_num ) return true;
2078 
2079   if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2080     return true;
2081   }
2082 
2083 #else
2084   // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2085   // Longs cannot be passed in O regs, because O regs become I regs
2086   // after a 'save' and I regs get their high bits chopped off on
2087   // interrupt.
2088   if( reg == R_G1H_num || reg == R_G1_num ) return true;
2089   if( reg == R_G4H_num || reg == R_G4_num ) return true;
2090 #endif
2091   // A few float args in registers
2092   if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2093 
2094   return false;
2095 }
2096 
2097 bool Matcher::is_spillable_arg( int reg ) {
2098   return can_be_java_arg(reg);
2099 }
2100 
2101 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2102   // Use hardware SDIVX instruction when it is
2103   // faster than a code which use multiply.
2104   return VM_Version::has_fast_idiv();
2105 }
2106 
2107 // Register for DIVI projection of divmodI
2108 RegMask Matcher::divI_proj_mask() {
2109   ShouldNotReachHere();
2110   return RegMask();
2111 }
2112 
2113 // Register for MODI projection of divmodI
2114 RegMask Matcher::modI_proj_mask() {
2115   ShouldNotReachHere();
2116   return RegMask();
2117 }
2118 
2119 // Register for DIVL projection of divmodL
2120 RegMask Matcher::divL_proj_mask() {
2121   ShouldNotReachHere();
2122   return RegMask();
2123 }
2124 
2125 // Register for MODL projection of divmodL
2126 RegMask Matcher::modL_proj_mask() {
2127   ShouldNotReachHere();
2128   return RegMask();
2129 }
2130 
2131 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2132   return L7_REGP_mask();
2133 }
2134 
2135 %}
2136 
2137 
2138 // The intptr_t operand types, defined by textual substitution.
2139 // (Cf. opto/type.hpp.  This lets us avoid many, many other ifdefs.)
2140 #ifdef _LP64
2141 #define immX      immL
2142 #define immX13    immL13
2143 #define immX13m7  immL13m7
2144 #define iRegX     iRegL
2145 #define g1RegX    g1RegL
2146 #else
2147 #define immX      immI
2148 #define immX13    immI13
2149 #define immX13m7  immI13m7
2150 #define iRegX     iRegI
2151 #define g1RegX    g1RegI
2152 #endif
2153 
2154 //----------ENCODING BLOCK-----------------------------------------------------
2155 // This block specifies the encoding classes used by the compiler to output
2156 // byte streams.  Encoding classes are parameterized macros used by
2157 // Machine Instruction Nodes in order to generate the bit encoding of the
2158 // instruction.  Operands specify their base encoding interface with the
2159 // interface keyword.  There are currently supported four interfaces,
2160 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER.  REG_INTER causes an
2161 // operand to generate a function which returns its register number when
2162 // queried.   CONST_INTER causes an operand to generate a function which
2163 // returns the value of the constant when queried.  MEMORY_INTER causes an
2164 // operand to generate four functions which return the Base Register, the
2165 // Index Register, the Scale Value, and the Offset Value of the operand when
2166 // queried.  COND_INTER causes an operand to generate six functions which
2167 // return the encoding code (ie - encoding bits for the instruction)
2168 // associated with each basic boolean condition for a conditional instruction.
2169 //
2170 // Instructions specify two basic values for encoding.  Again, a function
2171 // is available to check if the constant displacement is an oop. They use the
2172 // ins_encode keyword to specify their encoding classes (which must be
2173 // a sequence of enc_class names, and their parameters, specified in
2174 // the encoding block), and they use the
2175 // opcode keyword to specify, in order, their primary, secondary, and
2176 // tertiary opcode.  Only the opcode sections which a particular instruction
2177 // needs for encoding need to be specified.
2178 encode %{
2179   enc_class enc_untested %{
2180 #ifdef ASSERT
2181     MacroAssembler _masm(&cbuf);
2182     __ untested("encoding");
2183 #endif
2184   %}
2185 
2186   enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2187     emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2188                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2189   %}
2190 
2191   enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2192     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2193                        $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2194   %}
2195 
2196   enc_class form3_mem_prefetch_read( memory mem ) %{
2197     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2198                        $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2199   %}
2200 
2201   enc_class form3_mem_prefetch_write( memory mem ) %{
2202     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2203                        $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2204   %}
2205 
2206   enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2207     assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
2208     assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2209     guarantee($mem$$index == R_G0_enc, "double index?");
2210     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2211     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg );
2212     emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2213     emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2214   %}
2215 
2216   enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2217     assert(Assembler::is_simm13($mem$$disp  ), "need disp and disp+4");
2218     assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2219     guarantee($mem$$index == R_G0_enc, "double index?");
2220     // Load long with 2 instructions
2221     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp,   R_G0_enc, $reg$$reg+0 );
2222     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2223   %}
2224 
2225   //%%% form3_mem_plus_4_reg is a hack--get rid of it
2226   enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2227     guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2228     emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2229   %}
2230 
2231   enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2232     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2233     if( $rs2$$reg != $rd$$reg )
2234       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2235   %}
2236 
2237   // Target lo half of long
2238   enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2239     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2240     if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2241       emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2242   %}
2243 
2244   // Source lo half of long
2245   enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2246     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2247     if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2248       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2249   %}
2250 
2251   // Target hi half of long
2252   enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2253     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2254   %}
2255 
2256   // Source lo half of long, and leave it sign extended.
2257   enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2258     // Sign extend low half
2259     emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2260   %}
2261 
2262   // Source hi half of long, and leave it sign extended.
2263   enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2264     // Shift high half to low half
2265     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2266   %}
2267 
2268   // Source hi half of long
2269   enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2270     // Encode a reg-reg copy.  If it is useless, then empty encoding.
2271     if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2272       emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2273   %}
2274 
2275   enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2276     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2277   %}
2278 
2279   enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2280     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, 0, 0, $src$$reg );
2281     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2282   %}
2283 
2284   enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2285     emit3       ( cbuf, Assembler::arith_op,         0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2286     // clear if nothing else is happening
2287     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  0 );
2288     // blt,a,pn done
2289     emit2_19    ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2290     // mov dst,-1 in delay slot
2291     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2292   %}
2293 
2294   enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2295     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2296   %}
2297 
2298   enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2299     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2300   %}
2301 
2302   enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2303     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2304   %}
2305 
2306   enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2307     emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2308   %}
2309 
2310   enc_class move_return_pc_to_o1() %{
2311     emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2312   %}
2313 
2314 #ifdef _LP64
2315   /* %%% merge with enc_to_bool */
2316   enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2317     MacroAssembler _masm(&cbuf);
2318 
2319     Register   src_reg = reg_to_register_object($src$$reg);
2320     Register   dst_reg = reg_to_register_object($dst$$reg);
2321     __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2322   %}
2323 #endif
2324 
2325   enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2326     // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2327     MacroAssembler _masm(&cbuf);
2328 
2329     Register   p_reg = reg_to_register_object($p$$reg);
2330     Register   q_reg = reg_to_register_object($q$$reg);
2331     Register   y_reg = reg_to_register_object($y$$reg);
2332     Register tmp_reg = reg_to_register_object($tmp$$reg);
2333 
2334     __ subcc( p_reg, q_reg,   p_reg );
2335     __ add  ( p_reg, y_reg, tmp_reg );
2336     __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2337   %}
2338 
2339   enc_class form_d2i_helper(regD src, regF dst) %{
2340     // fcmp %fcc0,$src,$src
2341     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2342     // branch %fcc0 not-nan, predict taken
2343     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2344     // fdtoi $src,$dst
2345     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtoi_opf, $src$$reg );
2346     // fitos $dst,$dst (if nan)
2347     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
2348     // clear $dst (if nan)
2349     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2350     // carry on here...
2351   %}
2352 
2353   enc_class form_d2l_helper(regD src, regD dst) %{
2354     // fcmp %fcc0,$src,$src  check for NAN
2355     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2356     // branch %fcc0 not-nan, predict taken
2357     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2358     // fdtox $src,$dst   convert in delay slot
2359     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fdtox_opf, $src$$reg );
2360     // fxtod $dst,$dst  (if nan)
2361     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
2362     // clear $dst (if nan)
2363     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2364     // carry on here...
2365   %}
2366 
2367   enc_class form_f2i_helper(regF src, regF dst) %{
2368     // fcmps %fcc0,$src,$src
2369     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2370     // branch %fcc0 not-nan, predict taken
2371     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2372     // fstoi $src,$dst
2373     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstoi_opf, $src$$reg );
2374     // fitos $dst,$dst (if nan)
2375     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fitos_opf, $dst$$reg );
2376     // clear $dst (if nan)
2377     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2378     // carry on here...
2379   %}
2380 
2381   enc_class form_f2l_helper(regF src, regD dst) %{
2382     // fcmps %fcc0,$src,$src
2383     emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2384     // branch %fcc0 not-nan, predict taken
2385     emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2386     // fstox $src,$dst
2387     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fstox_opf, $src$$reg );
2388     // fxtod $dst,$dst (if nan)
2389     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3,         0, Assembler::fxtod_opf, $dst$$reg );
2390     // clear $dst (if nan)
2391     emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2392     // carry on here...
2393   %}
2394 
2395   enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2396   enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2397   enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2398   enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2399 
2400   enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2401 
2402   enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2403   enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2404 
2405   enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2406     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2407   %}
2408 
2409   enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2410     emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2411   %}
2412 
2413   enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2414     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2415   %}
2416 
2417   enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2418     emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2419   %}
2420 
2421   enc_class form3_convI2F(regF rs2, regF rd) %{
2422     emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2423   %}
2424 
2425   // Encloding class for traceable jumps
2426   enc_class form_jmpl(g3RegP dest) %{
2427     emit_jmpl(cbuf, $dest$$reg);
2428   %}
2429 
2430   enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2431     emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2432   %}
2433 
2434   enc_class form2_nop() %{
2435     emit_nop(cbuf);
2436   %}
2437 
2438   enc_class form2_illtrap() %{
2439     emit_illtrap(cbuf);
2440   %}
2441 
2442 
2443   // Compare longs and convert into -1, 0, 1.
2444   enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2445     // CMP $src1,$src2
2446     emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2447     // blt,a,pn done
2448     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less   , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2449     // mov dst,-1 in delay slot
2450     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2451     // bgt,a,pn done
2452     emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2453     // mov dst,1 in delay slot
2454     emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0,  1 );
2455     // CLR    $dst
2456     emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2457   %}
2458 
2459   enc_class enc_PartialSubtypeCheck() %{
2460     MacroAssembler _masm(&cbuf);
2461     __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2462     __ delayed()->nop();
2463   %}
2464 
2465   enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2466     MacroAssembler _masm(&cbuf);
2467     Label* L = $labl$$label;
2468     Assembler::Predict predict_taken =
2469       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2470 
2471     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2472     __ delayed()->nop();
2473   %}
2474 
2475   enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2476     MacroAssembler _masm(&cbuf);
2477     Label* L = $labl$$label;
2478     Assembler::Predict predict_taken =
2479       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2480 
2481     __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2482     __ delayed()->nop();
2483   %}
2484 
2485   enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2486     int op = (Assembler::arith_op << 30) |
2487              ($dst$$reg << 25) |
2488              (Assembler::movcc_op3 << 19) |
2489              (1 << 18) |                    // cc2 bit for 'icc'
2490              ($cmp$$cmpcode << 14) |
2491              (0 << 13) |                    // select register move
2492              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc' or 'xcc'
2493              ($src$$reg << 0);
2494     cbuf.insts()->emit_int32(op);
2495   %}
2496 
2497   enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2498     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2499     int op = (Assembler::arith_op << 30) |
2500              ($dst$$reg << 25) |
2501              (Assembler::movcc_op3 << 19) |
2502              (1 << 18) |                    // cc2 bit for 'icc'
2503              ($cmp$$cmpcode << 14) |
2504              (1 << 13) |                    // select immediate move
2505              ($pcc$$constant << 11) |       // cc1, cc0 bits for 'icc'
2506              (simm11 << 0);
2507     cbuf.insts()->emit_int32(op);
2508   %}
2509 
2510   enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2511     int op = (Assembler::arith_op << 30) |
2512              ($dst$$reg << 25) |
2513              (Assembler::movcc_op3 << 19) |
2514              (0 << 18) |                    // cc2 bit for 'fccX'
2515              ($cmp$$cmpcode << 14) |
2516              (0 << 13) |                    // select register move
2517              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
2518              ($src$$reg << 0);
2519     cbuf.insts()->emit_int32(op);
2520   %}
2521 
2522   enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2523     int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2524     int op = (Assembler::arith_op << 30) |
2525              ($dst$$reg << 25) |
2526              (Assembler::movcc_op3 << 19) |
2527              (0 << 18) |                    // cc2 bit for 'fccX'
2528              ($cmp$$cmpcode << 14) |
2529              (1 << 13) |                    // select immediate move
2530              ($fcc$$reg << 11) |            // cc1, cc0 bits for fcc0-fcc3
2531              (simm11 << 0);
2532     cbuf.insts()->emit_int32(op);
2533   %}
2534 
2535   enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2536     int op = (Assembler::arith_op << 30) |
2537              ($dst$$reg << 25) |
2538              (Assembler::fpop2_op3 << 19) |
2539              (0 << 18) |
2540              ($cmp$$cmpcode << 14) |
2541              (1 << 13) |                    // select register move
2542              ($pcc$$constant << 11) |       // cc1-cc0 bits for 'icc' or 'xcc'
2543              ($primary << 5) |              // select single, double or quad
2544              ($src$$reg << 0);
2545     cbuf.insts()->emit_int32(op);
2546   %}
2547 
2548   enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2549     int op = (Assembler::arith_op << 30) |
2550              ($dst$$reg << 25) |
2551              (Assembler::fpop2_op3 << 19) |
2552              (0 << 18) |
2553              ($cmp$$cmpcode << 14) |
2554              ($fcc$$reg << 11) |            // cc2-cc0 bits for 'fccX'
2555              ($primary << 5) |              // select single, double or quad
2556              ($src$$reg << 0);
2557     cbuf.insts()->emit_int32(op);
2558   %}
2559 
2560   // Used by the MIN/MAX encodings.  Same as a CMOV, but
2561   // the condition comes from opcode-field instead of an argument.
2562   enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2563     int op = (Assembler::arith_op << 30) |
2564              ($dst$$reg << 25) |
2565              (Assembler::movcc_op3 << 19) |
2566              (1 << 18) |                    // cc2 bit for 'icc'
2567              ($primary << 14) |
2568              (0 << 13) |                    // select register move
2569              (0 << 11) |                    // cc1, cc0 bits for 'icc'
2570              ($src$$reg << 0);
2571     cbuf.insts()->emit_int32(op);
2572   %}
2573 
2574   enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2575     int op = (Assembler::arith_op << 30) |
2576              ($dst$$reg << 25) |
2577              (Assembler::movcc_op3 << 19) |
2578              (6 << 16) |                    // cc2 bit for 'xcc'
2579              ($primary << 14) |
2580              (0 << 13) |                    // select register move
2581              (0 << 11) |                    // cc1, cc0 bits for 'icc'
2582              ($src$$reg << 0);
2583     cbuf.insts()->emit_int32(op);
2584   %}
2585 
2586   enc_class Set13( immI13 src, iRegI rd ) %{
2587     emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2588   %}
2589 
2590   enc_class SetHi22( immI src, iRegI rd ) %{
2591     emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2592   %}
2593 
2594   enc_class Set32( immI src, iRegI rd ) %{
2595     MacroAssembler _masm(&cbuf);
2596     __ set($src$$constant, reg_to_register_object($rd$$reg));
2597   %}
2598 
2599   enc_class call_epilog %{
2600     if( VerifyStackAtCalls ) {
2601       MacroAssembler _masm(&cbuf);
2602       int framesize = ra_->C->frame_size_in_bytes();
2603       Register temp_reg = G3;
2604       __ add(SP, framesize, temp_reg);
2605       __ cmp(temp_reg, FP);
2606       __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2607     }
2608   %}
2609 
2610   // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2611   // to G1 so the register allocator will not have to deal with the misaligned register
2612   // pair.
2613   enc_class adjust_long_from_native_call %{
2614 #ifndef _LP64
2615     if (returns_long()) {
2616       //    sllx  O0,32,O0
2617       emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2618       //    srl   O1,0,O1
2619       emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2620       //    or    O0,O1,G1
2621       emit3       ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2622     }
2623 #endif
2624   %}
2625 
2626   enc_class Java_To_Runtime (method meth) %{    // CALL Java_To_Runtime
2627     // CALL directly to the runtime
2628     // The user of this is responsible for ensuring that R_L7 is empty (killed).
2629     emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec(), /*preserve_g2=*/true);
2630   %}
2631 
2632   enc_class preserve_SP %{
2633     MacroAssembler _masm(&cbuf);
2634     __ mov(SP, L7_mh_SP_save);
2635   %}
2636 
2637   enc_class restore_SP %{
2638     MacroAssembler _masm(&cbuf);
2639     __ mov(L7_mh_SP_save, SP);
2640   %}
2641 
2642   enc_class Java_Static_Call (method meth) %{    // JAVA STATIC CALL
2643     // CALL to fixup routine.  Fixup routine uses ScopeDesc info to determine
2644     // who we intended to call.
2645     if (!_method) {
2646       emit_call_reloc(cbuf, $meth$$method, runtime_call_Relocation::spec());
2647     } else {
2648       int method_index = resolved_method_index(cbuf);
2649       RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2650                                                   : static_call_Relocation::spec(method_index);
2651       emit_call_reloc(cbuf, $meth$$method, rspec);
2652 
2653       // Emit stub for static call.
2654       address stub = CompiledStaticCall::emit_to_interp_stub(cbuf);
2655       // Stub does not fit into scratch buffer if TraceJumps is enabled
2656       if (stub == NULL && !(TraceJumps && Compile::current()->in_scratch_emit_size())) {
2657         ciEnv::current()->record_failure("CodeCache is full");
2658         return;
2659       }
2660     }
2661   %}
2662 
2663   enc_class Java_Dynamic_Call (method meth) %{    // JAVA DYNAMIC CALL
2664     MacroAssembler _masm(&cbuf);
2665     __ set_inst_mark();
2666     int vtable_index = this->_vtable_index;
2667     // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2668     if (vtable_index < 0) {
2669       // must be invalid_vtable_index, not nonvirtual_vtable_index
2670       assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2671       Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2672       assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2673       assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2674       __ ic_call((address)$meth$$method, /*emit_delay=*/true, resolved_method_index(cbuf));
2675     } else {
2676       assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2677       // Just go thru the vtable
2678       // get receiver klass (receiver already checked for non-null)
2679       // If we end up going thru a c2i adapter interpreter expects method in G5
2680       int off = __ offset();
2681       __ load_klass(O0, G3_scratch);
2682       int klass_load_size;
2683       if (UseCompressedClassPointers) {
2684         assert(Universe::heap() != NULL, "java heap should be initialized");
2685         klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2686       } else {
2687         klass_load_size = 1*BytesPerInstWord;
2688       }
2689       int entry_offset = in_bytes(Klass::vtable_start_offset()) + vtable_index*vtableEntry::size_in_bytes();
2690       int v_off = entry_offset + vtableEntry::method_offset_in_bytes();
2691       if (Assembler::is_simm13(v_off)) {
2692         __ ld_ptr(G3, v_off, G5_method);
2693       } else {
2694         // Generate 2 instructions
2695         __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2696         __ or3(G5_method, v_off & 0x3ff, G5_method);
2697         // ld_ptr, set_hi, set
2698         assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2699                "Unexpected instruction size(s)");
2700         __ ld_ptr(G3, G5_method, G5_method);
2701       }
2702       // NOTE: for vtable dispatches, the vtable entry will never be null.
2703       // However it may very well end up in handle_wrong_method if the
2704       // method is abstract for the particular class.
2705       __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2706       // jump to target (either compiled code or c2iadapter)
2707       __ jmpl(G3_scratch, G0, O7);
2708       __ delayed()->nop();
2709     }
2710   %}
2711 
2712   enc_class Java_Compiled_Call (method meth) %{    // JAVA COMPILED CALL
2713     MacroAssembler _masm(&cbuf);
2714 
2715     Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2716     Register temp_reg = G3;   // caller must kill G3!  We cannot reuse G5_ic_reg here because
2717                               // we might be calling a C2I adapter which needs it.
2718 
2719     assert(temp_reg != G5_ic_reg, "conflicting registers");
2720     // Load nmethod
2721     __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2722 
2723     // CALL to compiled java, indirect the contents of G3
2724     __ set_inst_mark();
2725     __ callr(temp_reg, G0);
2726     __ delayed()->nop();
2727   %}
2728 
2729 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2730     MacroAssembler _masm(&cbuf);
2731     Register Rdividend = reg_to_register_object($src1$$reg);
2732     Register Rdivisor = reg_to_register_object($src2$$reg);
2733     Register Rresult = reg_to_register_object($dst$$reg);
2734 
2735     __ sra(Rdivisor, 0, Rdivisor);
2736     __ sra(Rdividend, 0, Rdividend);
2737     __ sdivx(Rdividend, Rdivisor, Rresult);
2738 %}
2739 
2740 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2741     MacroAssembler _masm(&cbuf);
2742 
2743     Register Rdividend = reg_to_register_object($src1$$reg);
2744     int divisor = $imm$$constant;
2745     Register Rresult = reg_to_register_object($dst$$reg);
2746 
2747     __ sra(Rdividend, 0, Rdividend);
2748     __ sdivx(Rdividend, divisor, Rresult);
2749 %}
2750 
2751 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2752     MacroAssembler _masm(&cbuf);
2753     Register Rsrc1 = reg_to_register_object($src1$$reg);
2754     Register Rsrc2 = reg_to_register_object($src2$$reg);
2755     Register Rdst  = reg_to_register_object($dst$$reg);
2756 
2757     __ sra( Rsrc1, 0, Rsrc1 );
2758     __ sra( Rsrc2, 0, Rsrc2 );
2759     __ mulx( Rsrc1, Rsrc2, Rdst );
2760     __ srlx( Rdst, 32, Rdst );
2761 %}
2762 
2763 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2764     MacroAssembler _masm(&cbuf);
2765     Register Rdividend = reg_to_register_object($src1$$reg);
2766     Register Rdivisor = reg_to_register_object($src2$$reg);
2767     Register Rresult = reg_to_register_object($dst$$reg);
2768     Register Rscratch = reg_to_register_object($scratch$$reg);
2769 
2770     assert(Rdividend != Rscratch, "");
2771     assert(Rdivisor  != Rscratch, "");
2772 
2773     __ sra(Rdividend, 0, Rdividend);
2774     __ sra(Rdivisor, 0, Rdivisor);
2775     __ sdivx(Rdividend, Rdivisor, Rscratch);
2776     __ mulx(Rscratch, Rdivisor, Rscratch);
2777     __ sub(Rdividend, Rscratch, Rresult);
2778 %}
2779 
2780 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2781     MacroAssembler _masm(&cbuf);
2782 
2783     Register Rdividend = reg_to_register_object($src1$$reg);
2784     int divisor = $imm$$constant;
2785     Register Rresult = reg_to_register_object($dst$$reg);
2786     Register Rscratch = reg_to_register_object($scratch$$reg);
2787 
2788     assert(Rdividend != Rscratch, "");
2789 
2790     __ sra(Rdividend, 0, Rdividend);
2791     __ sdivx(Rdividend, divisor, Rscratch);
2792     __ mulx(Rscratch, divisor, Rscratch);
2793     __ sub(Rdividend, Rscratch, Rresult);
2794 %}
2795 
2796 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2797     MacroAssembler _masm(&cbuf);
2798 
2799     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2800     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2801 
2802     __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2803 %}
2804 
2805 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2806     MacroAssembler _masm(&cbuf);
2807 
2808     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2809     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2810 
2811     __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2812 %}
2813 
2814 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2815     MacroAssembler _masm(&cbuf);
2816 
2817     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2818     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2819 
2820     __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2821 %}
2822 
2823 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2824     MacroAssembler _masm(&cbuf);
2825 
2826     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2827     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2828 
2829     __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2830 %}
2831 
2832 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2833     MacroAssembler _masm(&cbuf);
2834 
2835     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2836     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2837 
2838     __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2839 %}
2840 
2841 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2842     MacroAssembler _masm(&cbuf);
2843 
2844     FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2845     FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2846 
2847     __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2848 %}
2849 
2850 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2851     MacroAssembler _masm(&cbuf);
2852 
2853     FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2854     FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2855 
2856     __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2857 %}
2858 
2859 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2860     MacroAssembler _masm(&cbuf);
2861 
2862     Register Roop  = reg_to_register_object($oop$$reg);
2863     Register Rbox  = reg_to_register_object($box$$reg);
2864     Register Rscratch = reg_to_register_object($scratch$$reg);
2865     Register Rmark =    reg_to_register_object($scratch2$$reg);
2866 
2867     assert(Roop  != Rscratch, "");
2868     assert(Roop  != Rmark, "");
2869     assert(Rbox  != Rscratch, "");
2870     assert(Rbox  != Rmark, "");
2871 
2872     __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2873 %}
2874 
2875 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2876     MacroAssembler _masm(&cbuf);
2877 
2878     Register Roop  = reg_to_register_object($oop$$reg);
2879     Register Rbox  = reg_to_register_object($box$$reg);
2880     Register Rscratch = reg_to_register_object($scratch$$reg);
2881     Register Rmark =    reg_to_register_object($scratch2$$reg);
2882 
2883     assert(Roop  != Rscratch, "");
2884     assert(Roop  != Rmark, "");
2885     assert(Rbox  != Rscratch, "");
2886     assert(Rbox  != Rmark, "");
2887 
2888     __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2889   %}
2890 
2891   enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2892     MacroAssembler _masm(&cbuf);
2893     Register Rmem = reg_to_register_object($mem$$reg);
2894     Register Rold = reg_to_register_object($old$$reg);
2895     Register Rnew = reg_to_register_object($new$$reg);
2896 
2897     __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2898     __ cmp( Rold, Rnew );
2899   %}
2900 
2901   enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2902     Register Rmem = reg_to_register_object($mem$$reg);
2903     Register Rold = reg_to_register_object($old$$reg);
2904     Register Rnew = reg_to_register_object($new$$reg);
2905 
2906     MacroAssembler _masm(&cbuf);
2907     __ mov(Rnew, O7);
2908     __ casx(Rmem, Rold, O7);
2909     __ cmp( Rold, O7 );
2910   %}
2911 
2912   // raw int cas, used for compareAndSwap
2913   enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2914     Register Rmem = reg_to_register_object($mem$$reg);
2915     Register Rold = reg_to_register_object($old$$reg);
2916     Register Rnew = reg_to_register_object($new$$reg);
2917 
2918     MacroAssembler _masm(&cbuf);
2919     __ mov(Rnew, O7);
2920     __ cas(Rmem, Rold, O7);
2921     __ cmp( Rold, O7 );
2922   %}
2923 
2924   enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2925     Register Rres = reg_to_register_object($res$$reg);
2926 
2927     MacroAssembler _masm(&cbuf);
2928     __ mov(1, Rres);
2929     __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2930   %}
2931 
2932   enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2933     Register Rres = reg_to_register_object($res$$reg);
2934 
2935     MacroAssembler _masm(&cbuf);
2936     __ mov(1, Rres);
2937     __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2938   %}
2939 
2940   enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2941     MacroAssembler _masm(&cbuf);
2942     Register Rdst = reg_to_register_object($dst$$reg);
2943     FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2944                                      : reg_to_DoubleFloatRegister_object($src1$$reg);
2945     FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2946                                      : reg_to_DoubleFloatRegister_object($src2$$reg);
2947 
2948     // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2949     __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2950   %}
2951 
2952   enc_class enc_rethrow() %{
2953     cbuf.set_insts_mark();
2954     Register temp_reg = G3;
2955     AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
2956     assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
2957     MacroAssembler _masm(&cbuf);
2958 #ifdef ASSERT
2959     __ save_frame(0);
2960     AddressLiteral last_rethrow_addrlit(&last_rethrow);
2961     __ sethi(last_rethrow_addrlit, L1);
2962     Address addr(L1, last_rethrow_addrlit.low10());
2963     __ rdpc(L2);
2964     __ inc(L2, 3 * BytesPerInstWord);  // skip this & 2 more insns to point at jump_to
2965     __ st_ptr(L2, addr);
2966     __ restore();
2967 #endif
2968     __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
2969     __ delayed()->nop();
2970   %}
2971 
2972   enc_class emit_mem_nop() %{
2973     // Generates the instruction LDUXA [o6,g0],#0x82,g0
2974     cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
2975   %}
2976 
2977   enc_class emit_fadd_nop() %{
2978     // Generates the instruction FMOVS f31,f31
2979     cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
2980   %}
2981 
2982   enc_class emit_br_nop() %{
2983     // Generates the instruction BPN,PN .
2984     cbuf.insts()->emit_int32((unsigned int) 0x00400000);
2985   %}
2986 
2987   enc_class enc_membar_acquire %{
2988     MacroAssembler _masm(&cbuf);
2989     __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
2990   %}
2991 
2992   enc_class enc_membar_release %{
2993     MacroAssembler _masm(&cbuf);
2994     __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
2995   %}
2996 
2997   enc_class enc_membar_volatile %{
2998     MacroAssembler _masm(&cbuf);
2999     __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3000   %}
3001 
3002 %}
3003 
3004 //----------FRAME--------------------------------------------------------------
3005 // Definition of frame structure and management information.
3006 //
3007 //  S T A C K   L A Y O U T    Allocators stack-slot number
3008 //                             |   (to get allocators register number
3009 //  G  Owned by    |        |  v    add VMRegImpl::stack0)
3010 //  r   CALLER     |        |
3011 //  o     |        +--------+      pad to even-align allocators stack-slot
3012 //  w     V        |  pad0  |        numbers; owned by CALLER
3013 //  t   -----------+--------+----> Matcher::_in_arg_limit, unaligned
3014 //  h     ^        |   in   |  5
3015 //        |        |  args  |  4   Holes in incoming args owned by SELF
3016 //  |     |        |        |  3
3017 //  |     |        +--------+
3018 //  V     |        | old out|      Empty on Intel, window on Sparc
3019 //        |    old |preserve|      Must be even aligned.
3020 //        |     SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3021 //        |        |   in   |  3   area for Intel ret address
3022 //     Owned by    |preserve|      Empty on Sparc.
3023 //       SELF      +--------+
3024 //        |        |  pad2  |  2   pad to align old SP
3025 //        |        +--------+  1
3026 //        |        | locks  |  0
3027 //        |        +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3028 //        |        |  pad1  | 11   pad to align new SP
3029 //        |        +--------+
3030 //        |        |        | 10
3031 //        |        | spills |  9   spills
3032 //        V        |        |  8   (pad0 slot for callee)
3033 //      -----------+--------+----> Matcher::_out_arg_limit, unaligned
3034 //        ^        |  out   |  7
3035 //        |        |  args  |  6   Holes in outgoing args owned by CALLEE
3036 //     Owned by    +--------+
3037 //      CALLEE     | new out|  6   Empty on Intel, window on Sparc
3038 //        |    new |preserve|      Must be even-aligned.
3039 //        |     SP-+--------+----> Matcher::_new_SP, even aligned
3040 //        |        |        |
3041 //
3042 // Note 1: Only region 8-11 is determined by the allocator.  Region 0-5 is
3043 //         known from SELF's arguments and the Java calling convention.
3044 //         Region 6-7 is determined per call site.
3045 // Note 2: If the calling convention leaves holes in the incoming argument
3046 //         area, those holes are owned by SELF.  Holes in the outgoing area
3047 //         are owned by the CALLEE.  Holes should not be nessecary in the
3048 //         incoming area, as the Java calling convention is completely under
3049 //         the control of the AD file.  Doubles can be sorted and packed to
3050 //         avoid holes.  Holes in the outgoing arguments may be necessary for
3051 //         varargs C calling conventions.
3052 // Note 3: Region 0-3 is even aligned, with pad2 as needed.  Region 3-5 is
3053 //         even aligned with pad0 as needed.
3054 //         Region 6 is even aligned.  Region 6-7 is NOT even aligned;
3055 //         region 6-11 is even aligned; it may be padded out more so that
3056 //         the region from SP to FP meets the minimum stack alignment.
3057 
3058 frame %{
3059   // What direction does stack grow in (assumed to be same for native & Java)
3060   stack_direction(TOWARDS_LOW);
3061 
3062   // These two registers define part of the calling convention
3063   // between compiled code and the interpreter.
3064   inline_cache_reg(R_G5);                // Inline Cache Register or Method* for I2C
3065   interpreter_method_oop_reg(R_G5);      // Method Oop Register when calling interpreter
3066 
3067   // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3068   cisc_spilling_operand_name(indOffset);
3069 
3070   // Number of stack slots consumed by a Monitor enter
3071 #ifdef _LP64
3072   sync_stack_slots(2);
3073 #else
3074   sync_stack_slots(1);
3075 #endif
3076 
3077   // Compiled code's Frame Pointer
3078   frame_pointer(R_SP);
3079 
3080   // Stack alignment requirement
3081   stack_alignment(StackAlignmentInBytes);
3082   //  LP64: Alignment size in bytes (128-bit -> 16 bytes)
3083   // !LP64: Alignment size in bytes (64-bit  ->  8 bytes)
3084 
3085   // Number of stack slots between incoming argument block and the start of
3086   // a new frame.  The PROLOG must add this many slots to the stack.  The
3087   // EPILOG must remove this many slots.
3088   in_preserve_stack_slots(0);
3089 
3090   // Number of outgoing stack slots killed above the out_preserve_stack_slots
3091   // for calls to C.  Supports the var-args backing area for register parms.
3092   // ADLC doesn't support parsing expressions, so I folded the math by hand.
3093 #ifdef _LP64
3094   // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3095   varargs_C_out_slots_killed(12);
3096 #else
3097   // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3098   varargs_C_out_slots_killed( 7);
3099 #endif
3100 
3101   // The after-PROLOG location of the return address.  Location of
3102   // return address specifies a type (REG or STACK) and a number
3103   // representing the register number (i.e. - use a register name) or
3104   // stack slot.
3105   return_addr(REG R_I7);          // Ret Addr is in register I7
3106 
3107   // Body of function which returns an OptoRegs array locating
3108   // arguments either in registers or in stack slots for calling
3109   // java
3110   calling_convention %{
3111     (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3112 
3113   %}
3114 
3115   // Body of function which returns an OptoRegs array locating
3116   // arguments either in registers or in stack slots for calling
3117   // C.
3118   c_calling_convention %{
3119     // This is obviously always outgoing
3120     (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3121   %}
3122 
3123   // Location of native (C/C++) and interpreter return values.  This is specified to
3124   // be the  same as Java.  In the 32-bit VM, long values are actually returned from
3125   // native calls in O0:O1 and returned to the interpreter in I0:I1.  The copying
3126   // to and from the register pairs is done by the appropriate call and epilog
3127   // opcodes.  This simplifies the register allocator.
3128   c_return_value %{
3129     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3130 #ifdef     _LP64
3131     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
3132     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
3133     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
3134     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
3135 #else  // !_LP64
3136     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
3137     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3138     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
3139     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3140 #endif
3141     return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3142                         (is_outgoing?lo_out:lo_in)[ideal_reg] );
3143   %}
3144 
3145   // Location of compiled Java return values.  Same as C
3146   return_value %{
3147     assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3148 #ifdef     _LP64
3149     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_O0_num };
3150     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num,    OptoReg::Bad, R_F1_num, R_O0H_num};
3151     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_I0_num };
3152     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num,    OptoReg::Bad, R_F1_num, R_I0H_num};
3153 #else  // !_LP64
3154     static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num,     R_O0_num,     R_O0_num,     R_F0_num,     R_F0_num, R_G1_num };
3155     static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3156     static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num,     R_I0_num,     R_I0_num,     R_F0_num,     R_F0_num, R_G1_num };
3157     static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3158 #endif
3159     return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3160                         (is_outgoing?lo_out:lo_in)[ideal_reg] );
3161   %}
3162 
3163 %}
3164 
3165 
3166 //----------ATTRIBUTES---------------------------------------------------------
3167 //----------Operand Attributes-------------------------------------------------
3168 op_attrib op_cost(1);          // Required cost attribute
3169 
3170 //----------Instruction Attributes---------------------------------------------
3171 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3172 ins_attrib ins_size(32);           // Required size attribute (in bits)
3173 
3174 // avoid_back_to_back attribute is an expression that must return
3175 // one of the following values defined in MachNode:
3176 // AVOID_NONE   - instruction can be placed anywhere
3177 // AVOID_BEFORE - instruction cannot be placed after an
3178 //                instruction with MachNode::AVOID_AFTER
3179 // AVOID_AFTER  - the next instruction cannot be the one
3180 //                with MachNode::AVOID_BEFORE
3181 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3182 //                          the same time
3183 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3184 
3185 ins_attrib ins_short_branch(0);    // Required flag: is this instruction a
3186                                    // non-matching short branch variant of some
3187                                                             // long branch?
3188 
3189 //----------OPERANDS-----------------------------------------------------------
3190 // Operand definitions must precede instruction definitions for correct parsing
3191 // in the ADLC because operands constitute user defined types which are used in
3192 // instruction definitions.
3193 
3194 //----------Simple Operands----------------------------------------------------
3195 // Immediate Operands
3196 // Integer Immediate: 32-bit
3197 operand immI() %{
3198   match(ConI);
3199 
3200   op_cost(0);
3201   // formats are generated automatically for constants and base registers
3202   format %{ %}
3203   interface(CONST_INTER);
3204 %}
3205 
3206 // Integer Immediate: 0-bit
3207 operand immI0() %{
3208   predicate(n->get_int() == 0);
3209   match(ConI);
3210   op_cost(0);
3211 
3212   format %{ %}
3213   interface(CONST_INTER);
3214 %}
3215 
3216 // Integer Immediate: 5-bit
3217 operand immI5() %{
3218   predicate(Assembler::is_simm5(n->get_int()));
3219   match(ConI);
3220   op_cost(0);
3221   format %{ %}
3222   interface(CONST_INTER);
3223 %}
3224 
3225 // Integer Immediate: 8-bit
3226 operand immI8() %{
3227   predicate(Assembler::is_simm8(n->get_int()));
3228   match(ConI);
3229   op_cost(0);
3230   format %{ %}
3231   interface(CONST_INTER);
3232 %}
3233 
3234 // Integer Immediate: the value 10
3235 operand immI10() %{
3236   predicate(n->get_int() == 10);
3237   match(ConI);
3238   op_cost(0);
3239 
3240   format %{ %}
3241   interface(CONST_INTER);
3242 %}
3243 
3244 // Integer Immediate: 11-bit
3245 operand immI11() %{
3246   predicate(Assembler::is_simm11(n->get_int()));
3247   match(ConI);
3248   op_cost(0);
3249   format %{ %}
3250   interface(CONST_INTER);
3251 %}
3252 
3253 // Integer Immediate: 13-bit
3254 operand immI13() %{
3255   predicate(Assembler::is_simm13(n->get_int()));
3256   match(ConI);
3257   op_cost(0);
3258 
3259   format %{ %}
3260   interface(CONST_INTER);
3261 %}
3262 
3263 // Integer Immediate: 13-bit minus 7
3264 operand immI13m7() %{
3265   predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3266   match(ConI);
3267   op_cost(0);
3268 
3269   format %{ %}
3270   interface(CONST_INTER);
3271 %}
3272 
3273 // Integer Immediate: 16-bit
3274 operand immI16() %{
3275   predicate(Assembler::is_simm16(n->get_int()));
3276   match(ConI);
3277   op_cost(0);
3278   format %{ %}
3279   interface(CONST_INTER);
3280 %}
3281 
3282 // Integer Immediate: the values 1-31
3283 operand immI_1_31() %{
3284   predicate(n->get_int() >= 1 && n->get_int() <= 31);
3285   match(ConI);
3286   op_cost(0);
3287 
3288   format %{ %}
3289   interface(CONST_INTER);
3290 %}
3291 
3292 // Integer Immediate: the values 32-63
3293 operand immI_32_63() %{
3294   predicate(n->get_int() >= 32 && n->get_int() <= 63);
3295   match(ConI);
3296   op_cost(0);
3297 
3298   format %{ %}
3299   interface(CONST_INTER);
3300 %}
3301 
3302 // Immediates for special shifts (sign extend)
3303 
3304 // Integer Immediate: the value 16
3305 operand immI_16() %{
3306   predicate(n->get_int() == 16);
3307   match(ConI);
3308   op_cost(0);
3309 
3310   format %{ %}
3311   interface(CONST_INTER);
3312 %}
3313 
3314 // Integer Immediate: the value 24
3315 operand immI_24() %{
3316   predicate(n->get_int() == 24);
3317   match(ConI);
3318   op_cost(0);
3319 
3320   format %{ %}
3321   interface(CONST_INTER);
3322 %}
3323 // Integer Immediate: the value 255
3324 operand immI_255() %{
3325   predicate( n->get_int() == 255 );
3326   match(ConI);
3327   op_cost(0);
3328 
3329   format %{ %}
3330   interface(CONST_INTER);
3331 %}
3332 
3333 // Integer Immediate: the value 65535
3334 operand immI_65535() %{
3335   predicate(n->get_int() == 65535);
3336   match(ConI);
3337   op_cost(0);
3338 
3339   format %{ %}
3340   interface(CONST_INTER);
3341 %}
3342 
3343 // Integer Immediate: the values 0-31
3344 operand immU5() %{
3345   predicate(n->get_int() >= 0 && n->get_int() <= 31);
3346   match(ConI);
3347   op_cost(0);
3348 
3349   format %{ %}
3350   interface(CONST_INTER);
3351 %}
3352 
3353 // Integer Immediate: 6-bit
3354 operand immU6() %{
3355   predicate(n->get_int() >= 0 && n->get_int() <= 63);
3356   match(ConI);
3357   op_cost(0);
3358   format %{ %}
3359   interface(CONST_INTER);
3360 %}
3361 
3362 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3363 operand immU12() %{
3364   predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3365   match(ConI);
3366   op_cost(0);
3367 
3368   format %{ %}
3369   interface(CONST_INTER);
3370 %}
3371 
3372 // Integer Immediate non-negative
3373 operand immU31()
3374 %{
3375   predicate(n->get_int() >= 0);
3376   match(ConI);
3377 
3378   op_cost(0);
3379   format %{ %}
3380   interface(CONST_INTER);
3381 %}
3382 
3383 // Long Immediate: the value FF
3384 operand immL_FF() %{
3385   predicate( n->get_long() == 0xFFL );
3386   match(ConL);
3387   op_cost(0);
3388 
3389   format %{ %}
3390   interface(CONST_INTER);
3391 %}
3392 
3393 // Long Immediate: the value FFFF
3394 operand immL_FFFF() %{
3395   predicate( n->get_long() == 0xFFFFL );
3396   match(ConL);
3397   op_cost(0);
3398 
3399   format %{ %}
3400   interface(CONST_INTER);
3401 %}
3402 
3403 // Pointer Immediate: 32 or 64-bit
3404 operand immP() %{
3405   match(ConP);
3406 
3407   op_cost(5);
3408   // formats are generated automatically for constants and base registers
3409   format %{ %}
3410   interface(CONST_INTER);
3411 %}
3412 
3413 #ifdef _LP64
3414 // Pointer Immediate: 64-bit
3415 operand immP_set() %{
3416   predicate(!VM_Version::is_niagara_plus());
3417   match(ConP);
3418 
3419   op_cost(5);
3420   // formats are generated automatically for constants and base registers
3421   format %{ %}
3422   interface(CONST_INTER);
3423 %}
3424 
3425 // Pointer Immediate: 64-bit
3426 // From Niagara2 processors on a load should be better than materializing.
3427 operand immP_load() %{
3428   predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3429   match(ConP);
3430 
3431   op_cost(5);
3432   // formats are generated automatically for constants and base registers
3433   format %{ %}
3434   interface(CONST_INTER);
3435 %}
3436 
3437 // Pointer Immediate: 64-bit
3438 operand immP_no_oop_cheap() %{
3439   predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3440   match(ConP);
3441 
3442   op_cost(5);
3443   // formats are generated automatically for constants and base registers
3444   format %{ %}
3445   interface(CONST_INTER);
3446 %}
3447 #endif
3448 
3449 operand immP13() %{
3450   predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3451   match(ConP);
3452   op_cost(0);
3453 
3454   format %{ %}
3455   interface(CONST_INTER);
3456 %}
3457 
3458 operand immP0() %{
3459   predicate(n->get_ptr() == 0);
3460   match(ConP);
3461   op_cost(0);
3462 
3463   format %{ %}
3464   interface(CONST_INTER);
3465 %}
3466 
3467 operand immP_poll() %{
3468   predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3469   match(ConP);
3470 
3471   // formats are generated automatically for constants and base registers
3472   format %{ %}
3473   interface(CONST_INTER);
3474 %}
3475 
3476 // Pointer Immediate
3477 operand immN()
3478 %{
3479   match(ConN);
3480 
3481   op_cost(10);
3482   format %{ %}
3483   interface(CONST_INTER);
3484 %}
3485 
3486 operand immNKlass()
3487 %{
3488   match(ConNKlass);
3489 
3490   op_cost(10);
3491   format %{ %}
3492   interface(CONST_INTER);
3493 %}
3494 
3495 // NULL Pointer Immediate
3496 operand immN0()
3497 %{
3498   predicate(n->get_narrowcon() == 0);
3499   match(ConN);
3500 
3501   op_cost(0);
3502   format %{ %}
3503   interface(CONST_INTER);
3504 %}
3505 
3506 operand immL() %{
3507   match(ConL);
3508   op_cost(40);
3509   // formats are generated automatically for constants and base registers
3510   format %{ %}
3511   interface(CONST_INTER);
3512 %}
3513 
3514 operand immL0() %{
3515   predicate(n->get_long() == 0L);
3516   match(ConL);
3517   op_cost(0);
3518   // formats are generated automatically for constants and base registers
3519   format %{ %}
3520   interface(CONST_INTER);
3521 %}
3522 
3523 // Integer Immediate: 5-bit
3524 operand immL5() %{
3525   predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3526   match(ConL);
3527   op_cost(0);
3528   format %{ %}
3529   interface(CONST_INTER);
3530 %}
3531 
3532 // Long Immediate: 13-bit
3533 operand immL13() %{
3534   predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3535   match(ConL);
3536   op_cost(0);
3537 
3538   format %{ %}
3539   interface(CONST_INTER);
3540 %}
3541 
3542 // Long Immediate: 13-bit minus 7
3543 operand immL13m7() %{
3544   predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3545   match(ConL);
3546   op_cost(0);
3547 
3548   format %{ %}
3549   interface(CONST_INTER);
3550 %}
3551 
3552 // Long Immediate: low 32-bit mask
3553 operand immL_32bits() %{
3554   predicate(n->get_long() == 0xFFFFFFFFL);
3555   match(ConL);
3556   op_cost(0);
3557 
3558   format %{ %}
3559   interface(CONST_INTER);
3560 %}
3561 
3562 // Long Immediate: cheap (materialize in <= 3 instructions)
3563 operand immL_cheap() %{
3564   predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3565   match(ConL);
3566   op_cost(0);
3567 
3568   format %{ %}
3569   interface(CONST_INTER);
3570 %}
3571 
3572 // Long Immediate: expensive (materialize in > 3 instructions)
3573 operand immL_expensive() %{
3574   predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3575   match(ConL);
3576   op_cost(0);
3577 
3578   format %{ %}
3579   interface(CONST_INTER);
3580 %}
3581 
3582 // Double Immediate
3583 operand immD() %{
3584   match(ConD);
3585 
3586   op_cost(40);
3587   format %{ %}
3588   interface(CONST_INTER);
3589 %}
3590 
3591 // Double Immediate: +0.0d
3592 operand immD0() %{
3593   predicate(jlong_cast(n->getd()) == 0);
3594   match(ConD);
3595 
3596   op_cost(0);
3597   format %{ %}
3598   interface(CONST_INTER);
3599 %}
3600 
3601 // Float Immediate
3602 operand immF() %{
3603   match(ConF);
3604 
3605   op_cost(20);
3606   format %{ %}
3607   interface(CONST_INTER);
3608 %}
3609 
3610 // Float Immediate: +0.0f
3611 operand immF0() %{
3612   predicate(jint_cast(n->getf()) == 0);
3613   match(ConF);
3614 
3615   op_cost(0);
3616   format %{ %}
3617   interface(CONST_INTER);
3618 %}
3619 
3620 // Integer Register Operands
3621 // Integer Register
3622 operand iRegI() %{
3623   constraint(ALLOC_IN_RC(int_reg));
3624   match(RegI);
3625 
3626   match(notemp_iRegI);
3627   match(g1RegI);
3628   match(o0RegI);
3629   match(iRegIsafe);
3630 
3631   format %{ %}
3632   interface(REG_INTER);
3633 %}
3634 
3635 operand notemp_iRegI() %{
3636   constraint(ALLOC_IN_RC(notemp_int_reg));
3637   match(RegI);
3638 
3639   match(o0RegI);
3640 
3641   format %{ %}
3642   interface(REG_INTER);
3643 %}
3644 
3645 operand o0RegI() %{
3646   constraint(ALLOC_IN_RC(o0_regI));
3647   match(iRegI);
3648 
3649   format %{ %}
3650   interface(REG_INTER);
3651 %}
3652 
3653 // Pointer Register
3654 operand iRegP() %{
3655   constraint(ALLOC_IN_RC(ptr_reg));
3656   match(RegP);
3657 
3658   match(lock_ptr_RegP);
3659   match(g1RegP);
3660   match(g2RegP);
3661   match(g3RegP);
3662   match(g4RegP);
3663   match(i0RegP);
3664   match(o0RegP);
3665   match(o1RegP);
3666   match(l7RegP);
3667 
3668   format %{ %}
3669   interface(REG_INTER);
3670 %}
3671 
3672 operand sp_ptr_RegP() %{
3673   constraint(ALLOC_IN_RC(sp_ptr_reg));
3674   match(RegP);
3675   match(iRegP);
3676 
3677   format %{ %}
3678   interface(REG_INTER);
3679 %}
3680 
3681 operand lock_ptr_RegP() %{
3682   constraint(ALLOC_IN_RC(lock_ptr_reg));
3683   match(RegP);
3684   match(i0RegP);
3685   match(o0RegP);
3686   match(o1RegP);
3687   match(l7RegP);
3688 
3689   format %{ %}
3690   interface(REG_INTER);
3691 %}
3692 
3693 operand g1RegP() %{
3694   constraint(ALLOC_IN_RC(g1_regP));
3695   match(iRegP);
3696 
3697   format %{ %}
3698   interface(REG_INTER);
3699 %}
3700 
3701 operand g2RegP() %{
3702   constraint(ALLOC_IN_RC(g2_regP));
3703   match(iRegP);
3704 
3705   format %{ %}
3706   interface(REG_INTER);
3707 %}
3708 
3709 operand g3RegP() %{
3710   constraint(ALLOC_IN_RC(g3_regP));
3711   match(iRegP);
3712 
3713   format %{ %}
3714   interface(REG_INTER);
3715 %}
3716 
3717 operand g1RegI() %{
3718   constraint(ALLOC_IN_RC(g1_regI));
3719   match(iRegI);
3720 
3721   format %{ %}
3722   interface(REG_INTER);
3723 %}
3724 
3725 operand g3RegI() %{
3726   constraint(ALLOC_IN_RC(g3_regI));
3727   match(iRegI);
3728 
3729   format %{ %}
3730   interface(REG_INTER);
3731 %}
3732 
3733 operand g4RegI() %{
3734   constraint(ALLOC_IN_RC(g4_regI));
3735   match(iRegI);
3736 
3737   format %{ %}
3738   interface(REG_INTER);
3739 %}
3740 
3741 operand g4RegP() %{
3742   constraint(ALLOC_IN_RC(g4_regP));
3743   match(iRegP);
3744 
3745   format %{ %}
3746   interface(REG_INTER);
3747 %}
3748 
3749 operand i0RegP() %{
3750   constraint(ALLOC_IN_RC(i0_regP));
3751   match(iRegP);
3752 
3753   format %{ %}
3754   interface(REG_INTER);
3755 %}
3756 
3757 operand o0RegP() %{
3758   constraint(ALLOC_IN_RC(o0_regP));
3759   match(iRegP);
3760 
3761   format %{ %}
3762   interface(REG_INTER);
3763 %}
3764 
3765 operand o1RegP() %{
3766   constraint(ALLOC_IN_RC(o1_regP));
3767   match(iRegP);
3768 
3769   format %{ %}
3770   interface(REG_INTER);
3771 %}
3772 
3773 operand o2RegP() %{
3774   constraint(ALLOC_IN_RC(o2_regP));
3775   match(iRegP);
3776 
3777   format %{ %}
3778   interface(REG_INTER);
3779 %}
3780 
3781 operand o7RegP() %{
3782   constraint(ALLOC_IN_RC(o7_regP));
3783   match(iRegP);
3784 
3785   format %{ %}
3786   interface(REG_INTER);
3787 %}
3788 
3789 operand l7RegP() %{
3790   constraint(ALLOC_IN_RC(l7_regP));
3791   match(iRegP);
3792 
3793   format %{ %}
3794   interface(REG_INTER);
3795 %}
3796 
3797 operand o7RegI() %{
3798   constraint(ALLOC_IN_RC(o7_regI));
3799   match(iRegI);
3800 
3801   format %{ %}
3802   interface(REG_INTER);
3803 %}
3804 
3805 operand iRegN() %{
3806   constraint(ALLOC_IN_RC(int_reg));
3807   match(RegN);
3808 
3809   format %{ %}
3810   interface(REG_INTER);
3811 %}
3812 
3813 // Long Register
3814 operand iRegL() %{
3815   constraint(ALLOC_IN_RC(long_reg));
3816   match(RegL);
3817 
3818   format %{ %}
3819   interface(REG_INTER);
3820 %}
3821 
3822 operand o2RegL() %{
3823   constraint(ALLOC_IN_RC(o2_regL));
3824   match(iRegL);
3825 
3826   format %{ %}
3827   interface(REG_INTER);
3828 %}
3829 
3830 operand o7RegL() %{
3831   constraint(ALLOC_IN_RC(o7_regL));
3832   match(iRegL);
3833 
3834   format %{ %}
3835   interface(REG_INTER);
3836 %}
3837 
3838 operand g1RegL() %{
3839   constraint(ALLOC_IN_RC(g1_regL));
3840   match(iRegL);
3841 
3842   format %{ %}
3843   interface(REG_INTER);
3844 %}
3845 
3846 operand g3RegL() %{
3847   constraint(ALLOC_IN_RC(g3_regL));
3848   match(iRegL);
3849 
3850   format %{ %}
3851   interface(REG_INTER);
3852 %}
3853 
3854 // Int Register safe
3855 // This is 64bit safe
3856 operand iRegIsafe() %{
3857   constraint(ALLOC_IN_RC(long_reg));
3858 
3859   match(iRegI);
3860 
3861   format %{ %}
3862   interface(REG_INTER);
3863 %}
3864 
3865 // Condition Code Flag Register
3866 operand flagsReg() %{
3867   constraint(ALLOC_IN_RC(int_flags));
3868   match(RegFlags);
3869 
3870   format %{ "ccr" %} // both ICC and XCC
3871   interface(REG_INTER);
3872 %}
3873 
3874 // Condition Code Register, unsigned comparisons.
3875 operand flagsRegU() %{
3876   constraint(ALLOC_IN_RC(int_flags));
3877   match(RegFlags);
3878 
3879   format %{ "icc_U" %}
3880   interface(REG_INTER);
3881 %}
3882 
3883 // Condition Code Register, pointer comparisons.
3884 operand flagsRegP() %{
3885   constraint(ALLOC_IN_RC(int_flags));
3886   match(RegFlags);
3887 
3888 #ifdef _LP64
3889   format %{ "xcc_P" %}
3890 #else
3891   format %{ "icc_P" %}
3892 #endif
3893   interface(REG_INTER);
3894 %}
3895 
3896 // Condition Code Register, long comparisons.
3897 operand flagsRegL() %{
3898   constraint(ALLOC_IN_RC(int_flags));
3899   match(RegFlags);
3900 
3901   format %{ "xcc_L" %}
3902   interface(REG_INTER);
3903 %}
3904 
3905 // Condition Code Register, floating comparisons, unordered same as "less".
3906 operand flagsRegF() %{
3907   constraint(ALLOC_IN_RC(float_flags));
3908   match(RegFlags);
3909   match(flagsRegF0);
3910 
3911   format %{ %}
3912   interface(REG_INTER);
3913 %}
3914 
3915 operand flagsRegF0() %{
3916   constraint(ALLOC_IN_RC(float_flag0));
3917   match(RegFlags);
3918 
3919   format %{ %}
3920   interface(REG_INTER);
3921 %}
3922 
3923 
3924 // Condition Code Flag Register used by long compare
3925 operand flagsReg_long_LTGE() %{
3926   constraint(ALLOC_IN_RC(int_flags));
3927   match(RegFlags);
3928   format %{ "icc_LTGE" %}
3929   interface(REG_INTER);
3930 %}
3931 operand flagsReg_long_EQNE() %{
3932   constraint(ALLOC_IN_RC(int_flags));
3933   match(RegFlags);
3934   format %{ "icc_EQNE" %}
3935   interface(REG_INTER);
3936 %}
3937 operand flagsReg_long_LEGT() %{
3938   constraint(ALLOC_IN_RC(int_flags));
3939   match(RegFlags);
3940   format %{ "icc_LEGT" %}
3941   interface(REG_INTER);
3942 %}
3943 
3944 
3945 operand regD() %{
3946   constraint(ALLOC_IN_RC(dflt_reg));
3947   match(RegD);
3948 
3949   match(regD_low);
3950 
3951   format %{ %}
3952   interface(REG_INTER);
3953 %}
3954 
3955 operand regF() %{
3956   constraint(ALLOC_IN_RC(sflt_reg));
3957   match(RegF);
3958 
3959   format %{ %}
3960   interface(REG_INTER);
3961 %}
3962 
3963 operand regD_low() %{
3964   constraint(ALLOC_IN_RC(dflt_low_reg));
3965   match(regD);
3966 
3967   format %{ %}
3968   interface(REG_INTER);
3969 %}
3970 
3971 // Special Registers
3972 
3973 // Method Register
3974 operand inline_cache_regP(iRegP reg) %{
3975   constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
3976   match(reg);
3977   format %{ %}
3978   interface(REG_INTER);
3979 %}
3980 
3981 operand interpreter_method_oop_regP(iRegP reg) %{
3982   constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
3983   match(reg);
3984   format %{ %}
3985   interface(REG_INTER);
3986 %}
3987 
3988 
3989 //----------Complex Operands---------------------------------------------------
3990 // Indirect Memory Reference
3991 operand indirect(sp_ptr_RegP reg) %{
3992   constraint(ALLOC_IN_RC(sp_ptr_reg));
3993   match(reg);
3994 
3995   op_cost(100);
3996   format %{ "[$reg]" %}
3997   interface(MEMORY_INTER) %{
3998     base($reg);
3999     index(0x0);
4000     scale(0x0);
4001     disp(0x0);
4002   %}
4003 %}
4004 
4005 // Indirect with simm13 Offset
4006 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4007   constraint(ALLOC_IN_RC(sp_ptr_reg));
4008   match(AddP reg offset);
4009 
4010   op_cost(100);
4011   format %{ "[$reg + $offset]" %}
4012   interface(MEMORY_INTER) %{
4013     base($reg);
4014     index(0x0);
4015     scale(0x0);
4016     disp($offset);
4017   %}
4018 %}
4019 
4020 // Indirect with simm13 Offset minus 7
4021 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4022   constraint(ALLOC_IN_RC(sp_ptr_reg));
4023   match(AddP reg offset);
4024 
4025   op_cost(100);
4026   format %{ "[$reg + $offset]" %}
4027   interface(MEMORY_INTER) %{
4028     base($reg);
4029     index(0x0);
4030     scale(0x0);
4031     disp($offset);
4032   %}
4033 %}
4034 
4035 // Note:  Intel has a swapped version also, like this:
4036 //operand indOffsetX(iRegI reg, immP offset) %{
4037 //  constraint(ALLOC_IN_RC(int_reg));
4038 //  match(AddP offset reg);
4039 //
4040 //  op_cost(100);
4041 //  format %{ "[$reg + $offset]" %}
4042 //  interface(MEMORY_INTER) %{
4043 //    base($reg);
4044 //    index(0x0);
4045 //    scale(0x0);
4046 //    disp($offset);
4047 //  %}
4048 //%}
4049 //// However, it doesn't make sense for SPARC, since
4050 // we have no particularly good way to embed oops in
4051 // single instructions.
4052 
4053 // Indirect with Register Index
4054 operand indIndex(iRegP addr, iRegX index) %{
4055   constraint(ALLOC_IN_RC(ptr_reg));
4056   match(AddP addr index);
4057 
4058   op_cost(100);
4059   format %{ "[$addr + $index]" %}
4060   interface(MEMORY_INTER) %{
4061     base($addr);
4062     index($index);
4063     scale(0x0);
4064     disp(0x0);
4065   %}
4066 %}
4067 
4068 //----------Special Memory Operands--------------------------------------------
4069 // Stack Slot Operand - This operand is used for loading and storing temporary
4070 //                      values on the stack where a match requires a value to
4071 //                      flow through memory.
4072 operand stackSlotI(sRegI reg) %{
4073   constraint(ALLOC_IN_RC(stack_slots));
4074   op_cost(100);
4075   //match(RegI);
4076   format %{ "[$reg]" %}
4077   interface(MEMORY_INTER) %{
4078     base(0xE);   // R_SP
4079     index(0x0);
4080     scale(0x0);
4081     disp($reg);  // Stack Offset
4082   %}
4083 %}
4084 
4085 operand stackSlotP(sRegP reg) %{
4086   constraint(ALLOC_IN_RC(stack_slots));
4087   op_cost(100);
4088   //match(RegP);
4089   format %{ "[$reg]" %}
4090   interface(MEMORY_INTER) %{
4091     base(0xE);   // R_SP
4092     index(0x0);
4093     scale(0x0);
4094     disp($reg);  // Stack Offset
4095   %}
4096 %}
4097 
4098 operand stackSlotF(sRegF reg) %{
4099   constraint(ALLOC_IN_RC(stack_slots));
4100   op_cost(100);
4101   //match(RegF);
4102   format %{ "[$reg]" %}
4103   interface(MEMORY_INTER) %{
4104     base(0xE);   // R_SP
4105     index(0x0);
4106     scale(0x0);
4107     disp($reg);  // Stack Offset
4108   %}
4109 %}
4110 operand stackSlotD(sRegD reg) %{
4111   constraint(ALLOC_IN_RC(stack_slots));
4112   op_cost(100);
4113   //match(RegD);
4114   format %{ "[$reg]" %}
4115   interface(MEMORY_INTER) %{
4116     base(0xE);   // R_SP
4117     index(0x0);
4118     scale(0x0);
4119     disp($reg);  // Stack Offset
4120   %}
4121 %}
4122 operand stackSlotL(sRegL reg) %{
4123   constraint(ALLOC_IN_RC(stack_slots));
4124   op_cost(100);
4125   //match(RegL);
4126   format %{ "[$reg]" %}
4127   interface(MEMORY_INTER) %{
4128     base(0xE);   // R_SP
4129     index(0x0);
4130     scale(0x0);
4131     disp($reg);  // Stack Offset
4132   %}
4133 %}
4134 
4135 // Operands for expressing Control Flow
4136 // NOTE:  Label is a predefined operand which should not be redefined in
4137 //        the AD file.  It is generically handled within the ADLC.
4138 
4139 //----------Conditional Branch Operands----------------------------------------
4140 // Comparison Op  - This is the operation of the comparison, and is limited to
4141 //                  the following set of codes:
4142 //                  L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4143 //
4144 // Other attributes of the comparison, such as unsignedness, are specified
4145 // by the comparison instruction that sets a condition code flags register.
4146 // That result is represented by a flags operand whose subtype is appropriate
4147 // to the unsignedness (etc.) of the comparison.
4148 //
4149 // Later, the instruction which matches both the Comparison Op (a Bool) and
4150 // the flags (produced by the Cmp) specifies the coding of the comparison op
4151 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4152 
4153 operand cmpOp() %{
4154   match(Bool);
4155 
4156   format %{ "" %}
4157   interface(COND_INTER) %{
4158     equal(0x1);
4159     not_equal(0x9);
4160     less(0x3);
4161     greater_equal(0xB);
4162     less_equal(0x2);
4163     greater(0xA);
4164     overflow(0x7);
4165     no_overflow(0xF);
4166   %}
4167 %}
4168 
4169 // Comparison Op, unsigned
4170 operand cmpOpU() %{
4171   match(Bool);
4172   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4173             n->as_Bool()->_test._test != BoolTest::no_overflow);
4174 
4175   format %{ "u" %}
4176   interface(COND_INTER) %{
4177     equal(0x1);
4178     not_equal(0x9);
4179     less(0x5);
4180     greater_equal(0xD);
4181     less_equal(0x4);
4182     greater(0xC);
4183     overflow(0x7);
4184     no_overflow(0xF);
4185   %}
4186 %}
4187 
4188 // Comparison Op, pointer (same as unsigned)
4189 operand cmpOpP() %{
4190   match(Bool);
4191   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4192             n->as_Bool()->_test._test != BoolTest::no_overflow);
4193 
4194   format %{ "p" %}
4195   interface(COND_INTER) %{
4196     equal(0x1);
4197     not_equal(0x9);
4198     less(0x5);
4199     greater_equal(0xD);
4200     less_equal(0x4);
4201     greater(0xC);
4202     overflow(0x7);
4203     no_overflow(0xF);
4204   %}
4205 %}
4206 
4207 // Comparison Op, branch-register encoding
4208 operand cmpOp_reg() %{
4209   match(Bool);
4210   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4211             n->as_Bool()->_test._test != BoolTest::no_overflow);
4212 
4213   format %{ "" %}
4214   interface(COND_INTER) %{
4215     equal        (0x1);
4216     not_equal    (0x5);
4217     less         (0x3);
4218     greater_equal(0x7);
4219     less_equal   (0x2);
4220     greater      (0x6);
4221     overflow(0x7); // not supported
4222     no_overflow(0xF); // not supported
4223   %}
4224 %}
4225 
4226 // Comparison Code, floating, unordered same as less
4227 operand cmpOpF() %{
4228   match(Bool);
4229   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4230             n->as_Bool()->_test._test != BoolTest::no_overflow);
4231 
4232   format %{ "fl" %}
4233   interface(COND_INTER) %{
4234     equal(0x9);
4235     not_equal(0x1);
4236     less(0x3);
4237     greater_equal(0xB);
4238     less_equal(0xE);
4239     greater(0x6);
4240 
4241     overflow(0x7); // not supported
4242     no_overflow(0xF); // not supported
4243   %}
4244 %}
4245 
4246 // Used by long compare
4247 operand cmpOp_commute() %{
4248   match(Bool);
4249   predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4250             n->as_Bool()->_test._test != BoolTest::no_overflow);
4251 
4252   format %{ "" %}
4253   interface(COND_INTER) %{
4254     equal(0x1);
4255     not_equal(0x9);
4256     less(0xA);
4257     greater_equal(0x2);
4258     less_equal(0xB);
4259     greater(0x3);
4260     overflow(0x7);
4261     no_overflow(0xF);
4262   %}
4263 %}
4264 
4265 //----------OPERAND CLASSES----------------------------------------------------
4266 // Operand Classes are groups of operands that are used to simplify
4267 // instruction definitions by not requiring the AD writer to specify separate
4268 // instructions for every form of operand when the instruction accepts
4269 // multiple operand types with the same basic encoding and format.  The classic
4270 // case of this is memory operands.
4271 opclass memory( indirect, indOffset13, indIndex );
4272 opclass indIndexMemory( indIndex );
4273 
4274 //----------PIPELINE-----------------------------------------------------------
4275 pipeline %{
4276 
4277 //----------ATTRIBUTES---------------------------------------------------------
4278 attributes %{
4279   fixed_size_instructions;           // Fixed size instructions
4280   branch_has_delay_slot;             // Branch has delay slot following
4281   max_instructions_per_bundle = 4;   // Up to 4 instructions per bundle
4282   instruction_unit_size = 4;         // An instruction is 4 bytes long
4283   instruction_fetch_unit_size = 16;  // The processor fetches one line
4284   instruction_fetch_units = 1;       // of 16 bytes
4285 
4286   // List of nop instructions
4287   nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4288 %}
4289 
4290 //----------RESOURCES----------------------------------------------------------
4291 // Resources are the functional units available to the machine
4292 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4293 
4294 //----------PIPELINE DESCRIPTION-----------------------------------------------
4295 // Pipeline Description specifies the stages in the machine's pipeline
4296 
4297 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4298 
4299 //----------PIPELINE CLASSES---------------------------------------------------
4300 // Pipeline Classes describe the stages in which input and output are
4301 // referenced by the hardware pipeline.
4302 
4303 // Integer ALU reg-reg operation
4304 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4305     single_instruction;
4306     dst   : E(write);
4307     src1  : R(read);
4308     src2  : R(read);
4309     IALU  : R;
4310 %}
4311 
4312 // Integer ALU reg-reg long operation
4313 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4314     instruction_count(2);
4315     dst   : E(write);
4316     src1  : R(read);
4317     src2  : R(read);
4318     IALU  : R;
4319     IALU  : R;
4320 %}
4321 
4322 // Integer ALU reg-reg long dependent operation
4323 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4324     instruction_count(1); multiple_bundles;
4325     dst   : E(write);
4326     src1  : R(read);
4327     src2  : R(read);
4328     cr    : E(write);
4329     IALU  : R(2);
4330 %}
4331 
4332 // Integer ALU reg-imm operaion
4333 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4334     single_instruction;
4335     dst   : E(write);
4336     src1  : R(read);
4337     IALU  : R;
4338 %}
4339 
4340 // Integer ALU reg-reg operation with condition code
4341 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4342     single_instruction;
4343     dst   : E(write);
4344     cr    : E(write);
4345     src1  : R(read);
4346     src2  : R(read);
4347     IALU  : R;
4348 %}
4349 
4350 // Integer ALU reg-imm operation with condition code
4351 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4352     single_instruction;
4353     dst   : E(write);
4354     cr    : E(write);
4355     src1  : R(read);
4356     IALU  : R;
4357 %}
4358 
4359 // Integer ALU zero-reg operation
4360 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4361     single_instruction;
4362     dst   : E(write);
4363     src2  : R(read);
4364     IALU  : R;
4365 %}
4366 
4367 // Integer ALU zero-reg operation with condition code only
4368 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4369     single_instruction;
4370     cr    : E(write);
4371     src   : R(read);
4372     IALU  : R;
4373 %}
4374 
4375 // Integer ALU reg-reg operation with condition code only
4376 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4377     single_instruction;
4378     cr    : E(write);
4379     src1  : R(read);
4380     src2  : R(read);
4381     IALU  : R;
4382 %}
4383 
4384 // Integer ALU reg-imm operation with condition code only
4385 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4386     single_instruction;
4387     cr    : E(write);
4388     src1  : R(read);
4389     IALU  : R;
4390 %}
4391 
4392 // Integer ALU reg-reg-zero operation with condition code only
4393 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4394     single_instruction;
4395     cr    : E(write);
4396     src1  : R(read);
4397     src2  : R(read);
4398     IALU  : R;
4399 %}
4400 
4401 // Integer ALU reg-imm-zero operation with condition code only
4402 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4403     single_instruction;
4404     cr    : E(write);
4405     src1  : R(read);
4406     IALU  : R;
4407 %}
4408 
4409 // Integer ALU reg-reg operation with condition code, src1 modified
4410 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4411     single_instruction;
4412     cr    : E(write);
4413     src1  : E(write);
4414     src1  : R(read);
4415     src2  : R(read);
4416     IALU  : R;
4417 %}
4418 
4419 // Integer ALU reg-imm operation with condition code, src1 modified
4420 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4421     single_instruction;
4422     cr    : E(write);
4423     src1  : E(write);
4424     src1  : R(read);
4425     IALU  : R;
4426 %}
4427 
4428 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4429     multiple_bundles;
4430     dst   : E(write)+4;
4431     cr    : E(write);
4432     src1  : R(read);
4433     src2  : R(read);
4434     IALU  : R(3);
4435     BR    : R(2);
4436 %}
4437 
4438 // Integer ALU operation
4439 pipe_class ialu_none(iRegI dst) %{
4440     single_instruction;
4441     dst   : E(write);
4442     IALU  : R;
4443 %}
4444 
4445 // Integer ALU reg operation
4446 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4447     single_instruction; may_have_no_code;
4448     dst   : E(write);
4449     src   : R(read);
4450     IALU  : R;
4451 %}
4452 
4453 // Integer ALU reg conditional operation
4454 // This instruction has a 1 cycle stall, and cannot execute
4455 // in the same cycle as the instruction setting the condition
4456 // code. We kludge this by pretending to read the condition code
4457 // 1 cycle earlier, and by marking the functional units as busy
4458 // for 2 cycles with the result available 1 cycle later than
4459 // is really the case.
4460 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4461     single_instruction;
4462     op2_out : C(write);
4463     op1     : R(read);
4464     cr      : R(read);       // This is really E, with a 1 cycle stall
4465     BR      : R(2);
4466     MS      : R(2);
4467 %}
4468 
4469 #ifdef _LP64
4470 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4471     instruction_count(1); multiple_bundles;
4472     dst     : C(write)+1;
4473     src     : R(read)+1;
4474     IALU    : R(1);
4475     BR      : E(2);
4476     MS      : E(2);
4477 %}
4478 #endif
4479 
4480 // Integer ALU reg operation
4481 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4482     single_instruction; may_have_no_code;
4483     dst   : E(write);
4484     src   : R(read);
4485     IALU  : R;
4486 %}
4487 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4488     single_instruction; may_have_no_code;
4489     dst   : E(write);
4490     src   : R(read);
4491     IALU  : R;
4492 %}
4493 
4494 // Two integer ALU reg operations
4495 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4496     instruction_count(2);
4497     dst   : E(write);
4498     src   : R(read);
4499     A0    : R;
4500     A1    : R;
4501 %}
4502 
4503 // Two integer ALU reg operations
4504 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4505     instruction_count(2); may_have_no_code;
4506     dst   : E(write);
4507     src   : R(read);
4508     A0    : R;
4509     A1    : R;
4510 %}
4511 
4512 // Integer ALU imm operation
4513 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4514     single_instruction;
4515     dst   : E(write);
4516     IALU  : R;
4517 %}
4518 
4519 // Integer ALU reg-reg with carry operation
4520 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4521     single_instruction;
4522     dst   : E(write);
4523     src1  : R(read);
4524     src2  : R(read);
4525     IALU  : R;
4526 %}
4527 
4528 // Integer ALU cc operation
4529 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4530     single_instruction;
4531     dst   : E(write);
4532     cc    : R(read);
4533     IALU  : R;
4534 %}
4535 
4536 // Integer ALU cc / second IALU operation
4537 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4538     instruction_count(1); multiple_bundles;
4539     dst   : E(write)+1;
4540     src   : R(read);
4541     IALU  : R;
4542 %}
4543 
4544 // Integer ALU cc / second IALU operation
4545 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4546     instruction_count(1); multiple_bundles;
4547     dst   : E(write)+1;
4548     p     : R(read);
4549     q     : R(read);
4550     IALU  : R;
4551 %}
4552 
4553 // Integer ALU hi-lo-reg operation
4554 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4555     instruction_count(1); multiple_bundles;
4556     dst   : E(write)+1;
4557     IALU  : R(2);
4558 %}
4559 
4560 // Float ALU hi-lo-reg operation (with temp)
4561 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4562     instruction_count(1); multiple_bundles;
4563     dst   : E(write)+1;
4564     IALU  : R(2);
4565 %}
4566 
4567 // Long Constant
4568 pipe_class loadConL( iRegL dst, immL src ) %{
4569     instruction_count(2); multiple_bundles;
4570     dst   : E(write)+1;
4571     IALU  : R(2);
4572     IALU  : R(2);
4573 %}
4574 
4575 // Pointer Constant
4576 pipe_class loadConP( iRegP dst, immP src ) %{
4577     instruction_count(0); multiple_bundles;
4578     fixed_latency(6);
4579 %}
4580 
4581 // Polling Address
4582 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4583 #ifdef _LP64
4584     instruction_count(0); multiple_bundles;
4585     fixed_latency(6);
4586 #else
4587     dst   : E(write);
4588     IALU  : R;
4589 #endif
4590 %}
4591 
4592 // Long Constant small
4593 pipe_class loadConLlo( iRegL dst, immL src ) %{
4594     instruction_count(2);
4595     dst   : E(write);
4596     IALU  : R;
4597     IALU  : R;
4598 %}
4599 
4600 // [PHH] This is wrong for 64-bit.  See LdImmF/D.
4601 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4602     instruction_count(1); multiple_bundles;
4603     src   : R(read);
4604     dst   : M(write)+1;
4605     IALU  : R;
4606     MS    : E;
4607 %}
4608 
4609 // Integer ALU nop operation
4610 pipe_class ialu_nop() %{
4611     single_instruction;
4612     IALU  : R;
4613 %}
4614 
4615 // Integer ALU nop operation
4616 pipe_class ialu_nop_A0() %{
4617     single_instruction;
4618     A0    : R;
4619 %}
4620 
4621 // Integer ALU nop operation
4622 pipe_class ialu_nop_A1() %{
4623     single_instruction;
4624     A1    : R;
4625 %}
4626 
4627 // Integer Multiply reg-reg operation
4628 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4629     single_instruction;
4630     dst   : E(write);
4631     src1  : R(read);
4632     src2  : R(read);
4633     MS    : R(5);
4634 %}
4635 
4636 // Integer Multiply reg-imm operation
4637 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4638     single_instruction;
4639     dst   : E(write);
4640     src1  : R(read);
4641     MS    : R(5);
4642 %}
4643 
4644 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4645     single_instruction;
4646     dst   : E(write)+4;
4647     src1  : R(read);
4648     src2  : R(read);
4649     MS    : R(6);
4650 %}
4651 
4652 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4653     single_instruction;
4654     dst   : E(write)+4;
4655     src1  : R(read);
4656     MS    : R(6);
4657 %}
4658 
4659 // Integer Divide reg-reg
4660 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4661     instruction_count(1); multiple_bundles;
4662     dst   : E(write);
4663     temp  : E(write);
4664     src1  : R(read);
4665     src2  : R(read);
4666     temp  : R(read);
4667     MS    : R(38);
4668 %}
4669 
4670 // Integer Divide reg-imm
4671 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4672     instruction_count(1); multiple_bundles;
4673     dst   : E(write);
4674     temp  : E(write);
4675     src1  : R(read);
4676     temp  : R(read);
4677     MS    : R(38);
4678 %}
4679 
4680 // Long Divide
4681 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4682     dst  : E(write)+71;
4683     src1 : R(read);
4684     src2 : R(read)+1;
4685     MS   : R(70);
4686 %}
4687 
4688 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4689     dst  : E(write)+71;
4690     src1 : R(read);
4691     MS   : R(70);
4692 %}
4693 
4694 // Floating Point Add Float
4695 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4696     single_instruction;
4697     dst   : X(write);
4698     src1  : E(read);
4699     src2  : E(read);
4700     FA    : R;
4701 %}
4702 
4703 // Floating Point Add Double
4704 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4705     single_instruction;
4706     dst   : X(write);
4707     src1  : E(read);
4708     src2  : E(read);
4709     FA    : R;
4710 %}
4711 
4712 // Floating Point Conditional Move based on integer flags
4713 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4714     single_instruction;
4715     dst   : X(write);
4716     src   : E(read);
4717     cr    : R(read);
4718     FA    : R(2);
4719     BR    : R(2);
4720 %}
4721 
4722 // Floating Point Conditional Move based on integer flags
4723 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4724     single_instruction;
4725     dst   : X(write);
4726     src   : E(read);
4727     cr    : R(read);
4728     FA    : R(2);
4729     BR    : R(2);
4730 %}
4731 
4732 // Floating Point Multiply Float
4733 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4734     single_instruction;
4735     dst   : X(write);
4736     src1  : E(read);
4737     src2  : E(read);
4738     FM    : R;
4739 %}
4740 
4741 // Floating Point Multiply Double
4742 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4743     single_instruction;
4744     dst   : X(write);
4745     src1  : E(read);
4746     src2  : E(read);
4747     FM    : R;
4748 %}
4749 
4750 // Floating Point Divide Float
4751 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4752     single_instruction;
4753     dst   : X(write);
4754     src1  : E(read);
4755     src2  : E(read);
4756     FM    : R;
4757     FDIV  : C(14);
4758 %}
4759 
4760 // Floating Point Divide Double
4761 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4762     single_instruction;
4763     dst   : X(write);
4764     src1  : E(read);
4765     src2  : E(read);
4766     FM    : R;
4767     FDIV  : C(17);
4768 %}
4769 
4770 // Floating Point Move/Negate/Abs Float
4771 pipe_class faddF_reg(regF dst, regF src) %{
4772     single_instruction;
4773     dst   : W(write);
4774     src   : E(read);
4775     FA    : R(1);
4776 %}
4777 
4778 // Floating Point Move/Negate/Abs Double
4779 pipe_class faddD_reg(regD dst, regD src) %{
4780     single_instruction;
4781     dst   : W(write);
4782     src   : E(read);
4783     FA    : R;
4784 %}
4785 
4786 // Floating Point Convert F->D
4787 pipe_class fcvtF2D(regD dst, regF src) %{
4788     single_instruction;
4789     dst   : X(write);
4790     src   : E(read);
4791     FA    : R;
4792 %}
4793 
4794 // Floating Point Convert I->D
4795 pipe_class fcvtI2D(regD dst, regF src) %{
4796     single_instruction;
4797     dst   : X(write);
4798     src   : E(read);
4799     FA    : R;
4800 %}
4801 
4802 // Floating Point Convert LHi->D
4803 pipe_class fcvtLHi2D(regD dst, regD src) %{
4804     single_instruction;
4805     dst   : X(write);
4806     src   : E(read);
4807     FA    : R;
4808 %}
4809 
4810 // Floating Point Convert L->D
4811 pipe_class fcvtL2D(regD dst, regF src) %{
4812     single_instruction;
4813     dst   : X(write);
4814     src   : E(read);
4815     FA    : R;
4816 %}
4817 
4818 // Floating Point Convert L->F
4819 pipe_class fcvtL2F(regD dst, regF src) %{
4820     single_instruction;
4821     dst   : X(write);
4822     src   : E(read);
4823     FA    : R;
4824 %}
4825 
4826 // Floating Point Convert D->F
4827 pipe_class fcvtD2F(regD dst, regF src) %{
4828     single_instruction;
4829     dst   : X(write);
4830     src   : E(read);
4831     FA    : R;
4832 %}
4833 
4834 // Floating Point Convert I->L
4835 pipe_class fcvtI2L(regD dst, regF src) %{
4836     single_instruction;
4837     dst   : X(write);
4838     src   : E(read);
4839     FA    : R;
4840 %}
4841 
4842 // Floating Point Convert D->F
4843 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
4844     instruction_count(1); multiple_bundles;
4845     dst   : X(write)+6;
4846     src   : E(read);
4847     FA    : R;
4848 %}
4849 
4850 // Floating Point Convert D->L
4851 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
4852     instruction_count(1); multiple_bundles;
4853     dst   : X(write)+6;
4854     src   : E(read);
4855     FA    : R;
4856 %}
4857 
4858 // Floating Point Convert F->I
4859 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
4860     instruction_count(1); multiple_bundles;
4861     dst   : X(write)+6;
4862     src   : E(read);
4863     FA    : R;
4864 %}
4865 
4866 // Floating Point Convert F->L
4867 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
4868     instruction_count(1); multiple_bundles;
4869     dst   : X(write)+6;
4870     src   : E(read);
4871     FA    : R;
4872 %}
4873 
4874 // Floating Point Convert I->F
4875 pipe_class fcvtI2F(regF dst, regF src) %{
4876     single_instruction;
4877     dst   : X(write);
4878     src   : E(read);
4879     FA    : R;
4880 %}
4881 
4882 // Floating Point Compare
4883 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
4884     single_instruction;
4885     cr    : X(write);
4886     src1  : E(read);
4887     src2  : E(read);
4888     FA    : R;
4889 %}
4890 
4891 // Floating Point Compare
4892 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
4893     single_instruction;
4894     cr    : X(write);
4895     src1  : E(read);
4896     src2  : E(read);
4897     FA    : R;
4898 %}
4899 
4900 // Floating Add Nop
4901 pipe_class fadd_nop() %{
4902     single_instruction;
4903     FA  : R;
4904 %}
4905 
4906 // Integer Store to Memory
4907 pipe_class istore_mem_reg(memory mem, iRegI src) %{
4908     single_instruction;
4909     mem   : R(read);
4910     src   : C(read);
4911     MS    : R;
4912 %}
4913 
4914 // Integer Store to Memory
4915 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
4916     single_instruction;
4917     mem   : R(read);
4918     src   : C(read);
4919     MS    : R;
4920 %}
4921 
4922 // Integer Store Zero to Memory
4923 pipe_class istore_mem_zero(memory mem, immI0 src) %{
4924     single_instruction;
4925     mem   : R(read);
4926     MS    : R;
4927 %}
4928 
4929 // Special Stack Slot Store
4930 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
4931     single_instruction;
4932     stkSlot : R(read);
4933     src     : C(read);
4934     MS      : R;
4935 %}
4936 
4937 // Special Stack Slot Store
4938 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
4939     instruction_count(2); multiple_bundles;
4940     stkSlot : R(read);
4941     src     : C(read);
4942     MS      : R(2);
4943 %}
4944 
4945 // Float Store
4946 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
4947     single_instruction;
4948     mem : R(read);
4949     src : C(read);
4950     MS  : R;
4951 %}
4952 
4953 // Float Store
4954 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
4955     single_instruction;
4956     mem : R(read);
4957     MS  : R;
4958 %}
4959 
4960 // Double Store
4961 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
4962     instruction_count(1);
4963     mem : R(read);
4964     src : C(read);
4965     MS  : R;
4966 %}
4967 
4968 // Double Store
4969 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
4970     single_instruction;
4971     mem : R(read);
4972     MS  : R;
4973 %}
4974 
4975 // Special Stack Slot Float Store
4976 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
4977     single_instruction;
4978     stkSlot : R(read);
4979     src     : C(read);
4980     MS      : R;
4981 %}
4982 
4983 // Special Stack Slot Double Store
4984 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
4985     single_instruction;
4986     stkSlot : R(read);
4987     src     : C(read);
4988     MS      : R;
4989 %}
4990 
4991 // Integer Load (when sign bit propagation not needed)
4992 pipe_class iload_mem(iRegI dst, memory mem) %{
4993     single_instruction;
4994     mem : R(read);
4995     dst : C(write);
4996     MS  : R;
4997 %}
4998 
4999 // Integer Load from stack operand
5000 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5001     single_instruction;
5002     mem : R(read);
5003     dst : C(write);
5004     MS  : R;
5005 %}
5006 
5007 // Integer Load (when sign bit propagation or masking is needed)
5008 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5009     single_instruction;
5010     mem : R(read);
5011     dst : M(write);
5012     MS  : R;
5013 %}
5014 
5015 // Float Load
5016 pipe_class floadF_mem(regF dst, memory mem) %{
5017     single_instruction;
5018     mem : R(read);
5019     dst : M(write);
5020     MS  : R;
5021 %}
5022 
5023 // Float Load
5024 pipe_class floadD_mem(regD dst, memory mem) %{
5025     instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5026     mem : R(read);
5027     dst : M(write);
5028     MS  : R;
5029 %}
5030 
5031 // Float Load
5032 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5033     single_instruction;
5034     stkSlot : R(read);
5035     dst : M(write);
5036     MS  : R;
5037 %}
5038 
5039 // Float Load
5040 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5041     single_instruction;
5042     stkSlot : R(read);
5043     dst : M(write);
5044     MS  : R;
5045 %}
5046 
5047 // Memory Nop
5048 pipe_class mem_nop() %{
5049     single_instruction;
5050     MS  : R;
5051 %}
5052 
5053 pipe_class sethi(iRegP dst, immI src) %{
5054     single_instruction;
5055     dst  : E(write);
5056     IALU : R;
5057 %}
5058 
5059 pipe_class loadPollP(iRegP poll) %{
5060     single_instruction;
5061     poll : R(read);
5062     MS   : R;
5063 %}
5064 
5065 pipe_class br(Universe br, label labl) %{
5066     single_instruction_with_delay_slot;
5067     BR  : R;
5068 %}
5069 
5070 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5071     single_instruction_with_delay_slot;
5072     cr    : E(read);
5073     BR    : R;
5074 %}
5075 
5076 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5077     single_instruction_with_delay_slot;
5078     op1 : E(read);
5079     BR  : R;
5080     MS  : R;
5081 %}
5082 
5083 // Compare and branch
5084 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5085     instruction_count(2); has_delay_slot;
5086     cr    : E(write);
5087     src1  : R(read);
5088     src2  : R(read);
5089     IALU  : R;
5090     BR    : R;
5091 %}
5092 
5093 // Compare and branch
5094 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5095     instruction_count(2); has_delay_slot;
5096     cr    : E(write);
5097     src1  : R(read);
5098     IALU  : R;
5099     BR    : R;
5100 %}
5101 
5102 // Compare and branch using cbcond
5103 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5104     single_instruction;
5105     src1  : E(read);
5106     src2  : E(read);
5107     IALU  : R;
5108     BR    : R;
5109 %}
5110 
5111 // Compare and branch using cbcond
5112 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5113     single_instruction;
5114     src1  : E(read);
5115     IALU  : R;
5116     BR    : R;
5117 %}
5118 
5119 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5120     single_instruction_with_delay_slot;
5121     cr    : E(read);
5122     BR    : R;
5123 %}
5124 
5125 pipe_class br_nop() %{
5126     single_instruction;
5127     BR  : R;
5128 %}
5129 
5130 pipe_class simple_call(method meth) %{
5131     instruction_count(2); multiple_bundles; force_serialization;
5132     fixed_latency(100);
5133     BR  : R(1);
5134     MS  : R(1);
5135     A0  : R(1);
5136 %}
5137 
5138 pipe_class compiled_call(method meth) %{
5139     instruction_count(1); multiple_bundles; force_serialization;
5140     fixed_latency(100);
5141     MS  : R(1);
5142 %}
5143 
5144 pipe_class call(method meth) %{
5145     instruction_count(0); multiple_bundles; force_serialization;
5146     fixed_latency(100);
5147 %}
5148 
5149 pipe_class tail_call(Universe ignore, label labl) %{
5150     single_instruction; has_delay_slot;
5151     fixed_latency(100);
5152     BR  : R(1);
5153     MS  : R(1);
5154 %}
5155 
5156 pipe_class ret(Universe ignore) %{
5157     single_instruction; has_delay_slot;
5158     BR  : R(1);
5159     MS  : R(1);
5160 %}
5161 
5162 pipe_class ret_poll(g3RegP poll) %{
5163     instruction_count(3); has_delay_slot;
5164     poll : E(read);
5165     MS   : R;
5166 %}
5167 
5168 // The real do-nothing guy
5169 pipe_class empty( ) %{
5170     instruction_count(0);
5171 %}
5172 
5173 pipe_class long_memory_op() %{
5174     instruction_count(0); multiple_bundles; force_serialization;
5175     fixed_latency(25);
5176     MS  : R(1);
5177 %}
5178 
5179 // Check-cast
5180 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5181     array : R(read);
5182     match  : R(read);
5183     IALU   : R(2);
5184     BR     : R(2);
5185     MS     : R;
5186 %}
5187 
5188 // Convert FPU flags into +1,0,-1
5189 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5190     src1  : E(read);
5191     src2  : E(read);
5192     dst   : E(write);
5193     FA    : R;
5194     MS    : R(2);
5195     BR    : R(2);
5196 %}
5197 
5198 // Compare for p < q, and conditionally add y
5199 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5200     p     : E(read);
5201     q     : E(read);
5202     y     : E(read);
5203     IALU  : R(3)
5204 %}
5205 
5206 // Perform a compare, then move conditionally in a branch delay slot.
5207 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5208     src2   : E(read);
5209     srcdst : E(read);
5210     IALU   : R;
5211     BR     : R;
5212 %}
5213 
5214 // Define the class for the Nop node
5215 define %{
5216    MachNop = ialu_nop;
5217 %}
5218 
5219 %}
5220 
5221 //----------INSTRUCTIONS-------------------------------------------------------
5222 
5223 //------------Special Stack Slot instructions - no match rules-----------------
5224 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5225   // No match rule to avoid chain rule match.
5226   effect(DEF dst, USE src);
5227   ins_cost(MEMORY_REF_COST);
5228   format %{ "LDF    $src,$dst\t! stkI to regF" %}
5229   opcode(Assembler::ldf_op3);
5230   ins_encode(simple_form3_mem_reg(src, dst));
5231   ins_pipe(floadF_stk);
5232 %}
5233 
5234 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5235   // No match rule to avoid chain rule match.
5236   effect(DEF dst, USE src);
5237   ins_cost(MEMORY_REF_COST);
5238   format %{ "LDDF   $src,$dst\t! stkL to regD" %}
5239   opcode(Assembler::lddf_op3);
5240   ins_encode(simple_form3_mem_reg(src, dst));
5241   ins_pipe(floadD_stk);
5242 %}
5243 
5244 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5245   // No match rule to avoid chain rule match.
5246   effect(DEF dst, USE src);
5247   ins_cost(MEMORY_REF_COST);
5248   format %{ "STF    $src,$dst\t! regF to stkI" %}
5249   opcode(Assembler::stf_op3);
5250   ins_encode(simple_form3_mem_reg(dst, src));
5251   ins_pipe(fstoreF_stk_reg);
5252 %}
5253 
5254 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5255   // No match rule to avoid chain rule match.
5256   effect(DEF dst, USE src);
5257   ins_cost(MEMORY_REF_COST);
5258   format %{ "STDF   $src,$dst\t! regD to stkL" %}
5259   opcode(Assembler::stdf_op3);
5260   ins_encode(simple_form3_mem_reg(dst, src));
5261   ins_pipe(fstoreD_stk_reg);
5262 %}
5263 
5264 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5265   effect(DEF dst, USE src);
5266   ins_cost(MEMORY_REF_COST*2);
5267   format %{ "STW    $src,$dst.hi\t! long\n\t"
5268             "STW    R_G0,$dst.lo" %}
5269   opcode(Assembler::stw_op3);
5270   ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5271   ins_pipe(lstoreI_stk_reg);
5272 %}
5273 
5274 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5275   // No match rule to avoid chain rule match.
5276   effect(DEF dst, USE src);
5277   ins_cost(MEMORY_REF_COST);
5278   format %{ "STX    $src,$dst\t! regL to stkD" %}
5279   opcode(Assembler::stx_op3);
5280   ins_encode(simple_form3_mem_reg( dst, src ) );
5281   ins_pipe(istore_stk_reg);
5282 %}
5283 
5284 //---------- Chain stack slots between similar types --------
5285 
5286 // Load integer from stack slot
5287 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5288   match(Set dst src);
5289   ins_cost(MEMORY_REF_COST);
5290 
5291   format %{ "LDUW   $src,$dst\t!stk" %}
5292   opcode(Assembler::lduw_op3);
5293   ins_encode(simple_form3_mem_reg( src, dst ) );
5294   ins_pipe(iload_mem);
5295 %}
5296 
5297 // Store integer to stack slot
5298 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5299   match(Set dst src);
5300   ins_cost(MEMORY_REF_COST);
5301 
5302   format %{ "STW    $src,$dst\t!stk" %}
5303   opcode(Assembler::stw_op3);
5304   ins_encode(simple_form3_mem_reg( dst, src ) );
5305   ins_pipe(istore_mem_reg);
5306 %}
5307 
5308 // Load long from stack slot
5309 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5310   match(Set dst src);
5311 
5312   ins_cost(MEMORY_REF_COST);
5313   format %{ "LDX    $src,$dst\t! long" %}
5314   opcode(Assembler::ldx_op3);
5315   ins_encode(simple_form3_mem_reg( src, dst ) );
5316   ins_pipe(iload_mem);
5317 %}
5318 
5319 // Store long to stack slot
5320 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5321   match(Set dst src);
5322 
5323   ins_cost(MEMORY_REF_COST);
5324   format %{ "STX    $src,$dst\t! long" %}
5325   opcode(Assembler::stx_op3);
5326   ins_encode(simple_form3_mem_reg( dst, src ) );
5327   ins_pipe(istore_mem_reg);
5328 %}
5329 
5330 #ifdef _LP64
5331 // Load pointer from stack slot, 64-bit encoding
5332 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5333   match(Set dst src);
5334   ins_cost(MEMORY_REF_COST);
5335   format %{ "LDX    $src,$dst\t!ptr" %}
5336   opcode(Assembler::ldx_op3);
5337   ins_encode(simple_form3_mem_reg( src, dst ) );
5338   ins_pipe(iload_mem);
5339 %}
5340 
5341 // Store pointer to stack slot
5342 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5343   match(Set dst src);
5344   ins_cost(MEMORY_REF_COST);
5345   format %{ "STX    $src,$dst\t!ptr" %}
5346   opcode(Assembler::stx_op3);
5347   ins_encode(simple_form3_mem_reg( dst, src ) );
5348   ins_pipe(istore_mem_reg);
5349 %}
5350 #else // _LP64
5351 // Load pointer from stack slot, 32-bit encoding
5352 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5353   match(Set dst src);
5354   ins_cost(MEMORY_REF_COST);
5355   format %{ "LDUW   $src,$dst\t!ptr" %}
5356   opcode(Assembler::lduw_op3, Assembler::ldst_op);
5357   ins_encode(simple_form3_mem_reg( src, dst ) );
5358   ins_pipe(iload_mem);
5359 %}
5360 
5361 // Store pointer to stack slot
5362 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5363   match(Set dst src);
5364   ins_cost(MEMORY_REF_COST);
5365   format %{ "STW    $src,$dst\t!ptr" %}
5366   opcode(Assembler::stw_op3, Assembler::ldst_op);
5367   ins_encode(simple_form3_mem_reg( dst, src ) );
5368   ins_pipe(istore_mem_reg);
5369 %}
5370 #endif // _LP64
5371 
5372 //------------Special Nop instructions for bundling - no match rules-----------
5373 // Nop using the A0 functional unit
5374 instruct Nop_A0() %{
5375   ins_cost(0);
5376 
5377   format %{ "NOP    ! Alu Pipeline" %}
5378   opcode(Assembler::or_op3, Assembler::arith_op);
5379   ins_encode( form2_nop() );
5380   ins_pipe(ialu_nop_A0);
5381 %}
5382 
5383 // Nop using the A1 functional unit
5384 instruct Nop_A1( ) %{
5385   ins_cost(0);
5386 
5387   format %{ "NOP    ! Alu Pipeline" %}
5388   opcode(Assembler::or_op3, Assembler::arith_op);
5389   ins_encode( form2_nop() );
5390   ins_pipe(ialu_nop_A1);
5391 %}
5392 
5393 // Nop using the memory functional unit
5394 instruct Nop_MS( ) %{
5395   ins_cost(0);
5396 
5397   format %{ "NOP    ! Memory Pipeline" %}
5398   ins_encode( emit_mem_nop );
5399   ins_pipe(mem_nop);
5400 %}
5401 
5402 // Nop using the floating add functional unit
5403 instruct Nop_FA( ) %{
5404   ins_cost(0);
5405 
5406   format %{ "NOP    ! Floating Add Pipeline" %}
5407   ins_encode( emit_fadd_nop );
5408   ins_pipe(fadd_nop);
5409 %}
5410 
5411 // Nop using the branch functional unit
5412 instruct Nop_BR( ) %{
5413   ins_cost(0);
5414 
5415   format %{ "NOP    ! Branch Pipeline" %}
5416   ins_encode( emit_br_nop );
5417   ins_pipe(br_nop);
5418 %}
5419 
5420 //----------Load/Store/Move Instructions---------------------------------------
5421 //----------Load Instructions--------------------------------------------------
5422 // Load Byte (8bit signed)
5423 instruct loadB(iRegI dst, memory mem) %{
5424   match(Set dst (LoadB mem));
5425   ins_cost(MEMORY_REF_COST);
5426 
5427   size(4);
5428   format %{ "LDSB   $mem,$dst\t! byte" %}
5429   ins_encode %{
5430     __ ldsb($mem$$Address, $dst$$Register);
5431   %}
5432   ins_pipe(iload_mask_mem);
5433 %}
5434 
5435 // Load Byte (8bit signed) into a Long Register
5436 instruct loadB2L(iRegL dst, memory mem) %{
5437   match(Set dst (ConvI2L (LoadB mem)));
5438   ins_cost(MEMORY_REF_COST);
5439 
5440   size(4);
5441   format %{ "LDSB   $mem,$dst\t! byte -> long" %}
5442   ins_encode %{
5443     __ ldsb($mem$$Address, $dst$$Register);
5444   %}
5445   ins_pipe(iload_mask_mem);
5446 %}
5447 
5448 // Load Unsigned Byte (8bit UNsigned) into an int reg
5449 instruct loadUB(iRegI dst, memory mem) %{
5450   match(Set dst (LoadUB mem));
5451   ins_cost(MEMORY_REF_COST);
5452 
5453   size(4);
5454   format %{ "LDUB   $mem,$dst\t! ubyte" %}
5455   ins_encode %{
5456     __ ldub($mem$$Address, $dst$$Register);
5457   %}
5458   ins_pipe(iload_mem);
5459 %}
5460 
5461 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5462 instruct loadUB2L(iRegL dst, memory mem) %{
5463   match(Set dst (ConvI2L (LoadUB mem)));
5464   ins_cost(MEMORY_REF_COST);
5465 
5466   size(4);
5467   format %{ "LDUB   $mem,$dst\t! ubyte -> long" %}
5468   ins_encode %{
5469     __ ldub($mem$$Address, $dst$$Register);
5470   %}
5471   ins_pipe(iload_mem);
5472 %}
5473 
5474 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
5475 instruct loadUB2L_immI(iRegL dst, memory mem, immI mask) %{
5476   match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5477   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5478 
5479   size(2*4);
5480   format %{ "LDUB   $mem,$dst\t# ubyte & 32-bit mask -> long\n\t"
5481             "AND    $dst,right_n_bits($mask, 8),$dst" %}
5482   ins_encode %{
5483     __ ldub($mem$$Address, $dst$$Register);
5484     __ and3($dst$$Register, $mask$$constant & right_n_bits(8), $dst$$Register);
5485   %}
5486   ins_pipe(iload_mem);
5487 %}
5488 
5489 // Load Short (16bit signed)
5490 instruct loadS(iRegI dst, memory mem) %{
5491   match(Set dst (LoadS mem));
5492   ins_cost(MEMORY_REF_COST);
5493 
5494   size(4);
5495   format %{ "LDSH   $mem,$dst\t! short" %}
5496   ins_encode %{
5497     __ ldsh($mem$$Address, $dst$$Register);
5498   %}
5499   ins_pipe(iload_mask_mem);
5500 %}
5501 
5502 // Load Short (16 bit signed) to Byte (8 bit signed)
5503 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5504   match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5505   ins_cost(MEMORY_REF_COST);
5506 
5507   size(4);
5508 
5509   format %{ "LDSB   $mem+1,$dst\t! short -> byte" %}
5510   ins_encode %{
5511     __ ldsb($mem$$Address, $dst$$Register, 1);
5512   %}
5513   ins_pipe(iload_mask_mem);
5514 %}
5515 
5516 // Load Short (16bit signed) into a Long Register
5517 instruct loadS2L(iRegL dst, memory mem) %{
5518   match(Set dst (ConvI2L (LoadS mem)));
5519   ins_cost(MEMORY_REF_COST);
5520 
5521   size(4);
5522   format %{ "LDSH   $mem,$dst\t! short -> long" %}
5523   ins_encode %{
5524     __ ldsh($mem$$Address, $dst$$Register);
5525   %}
5526   ins_pipe(iload_mask_mem);
5527 %}
5528 
5529 // Load Unsigned Short/Char (16bit UNsigned)
5530 instruct loadUS(iRegI dst, memory mem) %{
5531   match(Set dst (LoadUS mem));
5532   ins_cost(MEMORY_REF_COST);
5533 
5534   size(4);
5535   format %{ "LDUH   $mem,$dst\t! ushort/char" %}
5536   ins_encode %{
5537     __ lduh($mem$$Address, $dst$$Register);
5538   %}
5539   ins_pipe(iload_mem);
5540 %}
5541 
5542 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5543 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5544   match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5545   ins_cost(MEMORY_REF_COST);
5546 
5547   size(4);
5548   format %{ "LDSB   $mem+1,$dst\t! ushort -> byte" %}
5549   ins_encode %{
5550     __ ldsb($mem$$Address, $dst$$Register, 1);
5551   %}
5552   ins_pipe(iload_mask_mem);
5553 %}
5554 
5555 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5556 instruct loadUS2L(iRegL dst, memory mem) %{
5557   match(Set dst (ConvI2L (LoadUS mem)));
5558   ins_cost(MEMORY_REF_COST);
5559 
5560   size(4);
5561   format %{ "LDUH   $mem,$dst\t! ushort/char -> long" %}
5562   ins_encode %{
5563     __ lduh($mem$$Address, $dst$$Register);
5564   %}
5565   ins_pipe(iload_mem);
5566 %}
5567 
5568 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5569 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5570   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5571   ins_cost(MEMORY_REF_COST);
5572 
5573   size(4);
5574   format %{ "LDUB   $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5575   ins_encode %{
5576     __ ldub($mem$$Address, $dst$$Register, 1);  // LSB is index+1 on BE
5577   %}
5578   ins_pipe(iload_mem);
5579 %}
5580 
5581 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5582 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5583   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5584   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5585 
5586   size(2*4);
5587   format %{ "LDUH   $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5588             "AND    $dst,$mask,$dst" %}
5589   ins_encode %{
5590     Register Rdst = $dst$$Register;
5591     __ lduh($mem$$Address, Rdst);
5592     __ and3(Rdst, $mask$$constant, Rdst);
5593   %}
5594   ins_pipe(iload_mem);
5595 %}
5596 
5597 // Load Unsigned Short/Char (16bit UNsigned) with a 32-bit mask into a Long Register
5598 instruct loadUS2L_immI(iRegL dst, memory mem, immI mask, iRegL tmp) %{
5599   match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5600   effect(TEMP dst, TEMP tmp);
5601   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5602 
5603   format %{ "LDUH   $mem,$dst\t! ushort/char & 32-bit mask -> long\n\t"
5604             "SET    right_n_bits($mask, 16),$tmp\n\t"
5605             "AND    $dst,$tmp,$dst" %}
5606   ins_encode %{
5607     Register Rdst = $dst$$Register;
5608     Register Rtmp = $tmp$$Register;
5609     __ lduh($mem$$Address, Rdst);
5610     __ set($mask$$constant & right_n_bits(16), Rtmp);
5611     __ and3(Rdst, Rtmp, Rdst);
5612   %}
5613   ins_pipe(iload_mem);
5614 %}
5615 
5616 // Load Integer
5617 instruct loadI(iRegI dst, memory mem) %{
5618   match(Set dst (LoadI mem));
5619   ins_cost(MEMORY_REF_COST);
5620 
5621   size(4);
5622   format %{ "LDUW   $mem,$dst\t! int" %}
5623   ins_encode %{
5624     __ lduw($mem$$Address, $dst$$Register);
5625   %}
5626   ins_pipe(iload_mem);
5627 %}
5628 
5629 // Load Integer to Byte (8 bit signed)
5630 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5631   match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5632   ins_cost(MEMORY_REF_COST);
5633 
5634   size(4);
5635 
5636   format %{ "LDSB   $mem+3,$dst\t! int -> byte" %}
5637   ins_encode %{
5638     __ ldsb($mem$$Address, $dst$$Register, 3);
5639   %}
5640   ins_pipe(iload_mask_mem);
5641 %}
5642 
5643 // Load Integer to Unsigned Byte (8 bit UNsigned)
5644 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5645   match(Set dst (AndI (LoadI mem) mask));
5646   ins_cost(MEMORY_REF_COST);
5647 
5648   size(4);
5649 
5650   format %{ "LDUB   $mem+3,$dst\t! int -> ubyte" %}
5651   ins_encode %{
5652     __ ldub($mem$$Address, $dst$$Register, 3);
5653   %}
5654   ins_pipe(iload_mask_mem);
5655 %}
5656 
5657 // Load Integer to Short (16 bit signed)
5658 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5659   match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5660   ins_cost(MEMORY_REF_COST);
5661 
5662   size(4);
5663 
5664   format %{ "LDSH   $mem+2,$dst\t! int -> short" %}
5665   ins_encode %{
5666     __ ldsh($mem$$Address, $dst$$Register, 2);
5667   %}
5668   ins_pipe(iload_mask_mem);
5669 %}
5670 
5671 // Load Integer to Unsigned Short (16 bit UNsigned)
5672 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5673   match(Set dst (AndI (LoadI mem) mask));
5674   ins_cost(MEMORY_REF_COST);
5675 
5676   size(4);
5677 
5678   format %{ "LDUH   $mem+2,$dst\t! int -> ushort/char" %}
5679   ins_encode %{
5680     __ lduh($mem$$Address, $dst$$Register, 2);
5681   %}
5682   ins_pipe(iload_mask_mem);
5683 %}
5684 
5685 // Load Integer into a Long Register
5686 instruct loadI2L(iRegL dst, memory mem) %{
5687   match(Set dst (ConvI2L (LoadI mem)));
5688   ins_cost(MEMORY_REF_COST);
5689 
5690   size(4);
5691   format %{ "LDSW   $mem,$dst\t! int -> long" %}
5692   ins_encode %{
5693     __ ldsw($mem$$Address, $dst$$Register);
5694   %}
5695   ins_pipe(iload_mask_mem);
5696 %}
5697 
5698 // Load Integer with mask 0xFF into a Long Register
5699 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5700   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5701   ins_cost(MEMORY_REF_COST);
5702 
5703   size(4);
5704   format %{ "LDUB   $mem+3,$dst\t! int & 0xFF -> long" %}
5705   ins_encode %{
5706     __ ldub($mem$$Address, $dst$$Register, 3);  // LSB is index+3 on BE
5707   %}
5708   ins_pipe(iload_mem);
5709 %}
5710 
5711 // Load Integer with mask 0xFFFF into a Long Register
5712 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5713   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5714   ins_cost(MEMORY_REF_COST);
5715 
5716   size(4);
5717   format %{ "LDUH   $mem+2,$dst\t! int & 0xFFFF -> long" %}
5718   ins_encode %{
5719     __ lduh($mem$$Address, $dst$$Register, 2);  // LSW is index+2 on BE
5720   %}
5721   ins_pipe(iload_mem);
5722 %}
5723 
5724 // Load Integer with a 12-bit mask into a Long Register
5725 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5726   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5727   ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5728 
5729   size(2*4);
5730   format %{ "LDUW   $mem,$dst\t! int & 12-bit mask -> long\n\t"
5731             "AND    $dst,$mask,$dst" %}
5732   ins_encode %{
5733     Register Rdst = $dst$$Register;
5734     __ lduw($mem$$Address, Rdst);
5735     __ and3(Rdst, $mask$$constant, Rdst);
5736   %}
5737   ins_pipe(iload_mem);
5738 %}
5739 
5740 // Load Integer with a 31-bit mask into a Long Register
5741 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5742   match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5743   effect(TEMP dst, TEMP tmp);
5744   ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5745 
5746   format %{ "LDUW   $mem,$dst\t! int & 31-bit mask -> long\n\t"
5747             "SET    $mask,$tmp\n\t"
5748             "AND    $dst,$tmp,$dst" %}
5749   ins_encode %{
5750     Register Rdst = $dst$$Register;
5751     Register Rtmp = $tmp$$Register;
5752     __ lduw($mem$$Address, Rdst);
5753     __ set($mask$$constant, Rtmp);
5754     __ and3(Rdst, Rtmp, Rdst);
5755   %}
5756   ins_pipe(iload_mem);
5757 %}
5758 
5759 // Load Unsigned Integer into a Long Register
5760 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5761   match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5762   ins_cost(MEMORY_REF_COST);
5763 
5764   size(4);
5765   format %{ "LDUW   $mem,$dst\t! uint -> long" %}
5766   ins_encode %{
5767     __ lduw($mem$$Address, $dst$$Register);
5768   %}
5769   ins_pipe(iload_mem);
5770 %}
5771 
5772 // Load Long - aligned
5773 instruct loadL(iRegL dst, memory mem ) %{
5774   match(Set dst (LoadL mem));
5775   ins_cost(MEMORY_REF_COST);
5776 
5777   size(4);
5778   format %{ "LDX    $mem,$dst\t! long" %}
5779   ins_encode %{
5780     __ ldx($mem$$Address, $dst$$Register);
5781   %}
5782   ins_pipe(iload_mem);
5783 %}
5784 
5785 // Load Long - UNaligned
5786 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5787   match(Set dst (LoadL_unaligned mem));
5788   effect(KILL tmp);
5789   ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5790   format %{ "LDUW   $mem+4,R_O7\t! misaligned long\n"
5791           "\tLDUW   $mem  ,$dst\n"
5792           "\tSLLX   #32, $dst, $dst\n"
5793           "\tOR     $dst, R_O7, $dst" %}
5794   opcode(Assembler::lduw_op3);
5795   ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5796   ins_pipe(iload_mem);
5797 %}
5798 
5799 // Load Range
5800 instruct loadRange(iRegI dst, memory mem) %{
5801   match(Set dst (LoadRange mem));
5802   ins_cost(MEMORY_REF_COST);
5803 
5804   format %{ "LDUW   $mem,$dst\t! range" %}
5805   opcode(Assembler::lduw_op3);
5806   ins_encode(simple_form3_mem_reg( mem, dst ) );
5807   ins_pipe(iload_mem);
5808 %}
5809 
5810 // Load Integer into %f register (for fitos/fitod)
5811 instruct loadI_freg(regF dst, memory mem) %{
5812   match(Set dst (LoadI mem));
5813   ins_cost(MEMORY_REF_COST);
5814 
5815   format %{ "LDF    $mem,$dst\t! for fitos/fitod" %}
5816   opcode(Assembler::ldf_op3);
5817   ins_encode(simple_form3_mem_reg( mem, dst ) );
5818   ins_pipe(floadF_mem);
5819 %}
5820 
5821 // Load Pointer
5822 instruct loadP(iRegP dst, memory mem) %{
5823   match(Set dst (LoadP mem));
5824   ins_cost(MEMORY_REF_COST);
5825   size(4);
5826 
5827 #ifndef _LP64
5828   format %{ "LDUW   $mem,$dst\t! ptr" %}
5829   ins_encode %{
5830     __ lduw($mem$$Address, $dst$$Register);
5831   %}
5832 #else
5833   format %{ "LDX    $mem,$dst\t! ptr" %}
5834   ins_encode %{
5835     __ ldx($mem$$Address, $dst$$Register);
5836   %}
5837 #endif
5838   ins_pipe(iload_mem);
5839 %}
5840 
5841 // Load Compressed Pointer
5842 instruct loadN(iRegN dst, memory mem) %{
5843   match(Set dst (LoadN mem));
5844   ins_cost(MEMORY_REF_COST);
5845   size(4);
5846 
5847   format %{ "LDUW   $mem,$dst\t! compressed ptr" %}
5848   ins_encode %{
5849     __ lduw($mem$$Address, $dst$$Register);
5850   %}
5851   ins_pipe(iload_mem);
5852 %}
5853 
5854 // Load Klass Pointer
5855 instruct loadKlass(iRegP dst, memory mem) %{
5856   match(Set dst (LoadKlass mem));
5857   ins_cost(MEMORY_REF_COST);
5858   size(4);
5859 
5860 #ifndef _LP64
5861   format %{ "LDUW   $mem,$dst\t! klass ptr" %}
5862   ins_encode %{
5863     __ lduw($mem$$Address, $dst$$Register);
5864   %}
5865 #else
5866   format %{ "LDX    $mem,$dst\t! klass ptr" %}
5867   ins_encode %{
5868     __ ldx($mem$$Address, $dst$$Register);
5869   %}
5870 #endif
5871   ins_pipe(iload_mem);
5872 %}
5873 
5874 // Load narrow Klass Pointer
5875 instruct loadNKlass(iRegN dst, memory mem) %{
5876   match(Set dst (LoadNKlass mem));
5877   ins_cost(MEMORY_REF_COST);
5878   size(4);
5879 
5880   format %{ "LDUW   $mem,$dst\t! compressed klass ptr" %}
5881   ins_encode %{
5882     __ lduw($mem$$Address, $dst$$Register);
5883   %}
5884   ins_pipe(iload_mem);
5885 %}
5886 
5887 // Load Double
5888 instruct loadD(regD dst, memory mem) %{
5889   match(Set dst (LoadD mem));
5890   ins_cost(MEMORY_REF_COST);
5891 
5892   format %{ "LDDF   $mem,$dst" %}
5893   opcode(Assembler::lddf_op3);
5894   ins_encode(simple_form3_mem_reg( mem, dst ) );
5895   ins_pipe(floadD_mem);
5896 %}
5897 
5898 // Load Double - UNaligned
5899 instruct loadD_unaligned(regD_low dst, memory mem ) %{
5900   match(Set dst (LoadD_unaligned mem));
5901   ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5902   format %{ "LDF    $mem  ,$dst.hi\t! misaligned double\n"
5903           "\tLDF    $mem+4,$dst.lo\t!" %}
5904   opcode(Assembler::ldf_op3);
5905   ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
5906   ins_pipe(iload_mem);
5907 %}
5908 
5909 // Load Float
5910 instruct loadF(regF dst, memory mem) %{
5911   match(Set dst (LoadF mem));
5912   ins_cost(MEMORY_REF_COST);
5913 
5914   format %{ "LDF    $mem,$dst" %}
5915   opcode(Assembler::ldf_op3);
5916   ins_encode(simple_form3_mem_reg( mem, dst ) );
5917   ins_pipe(floadF_mem);
5918 %}
5919 
5920 // Load Constant
5921 instruct loadConI( iRegI dst, immI src ) %{
5922   match(Set dst src);
5923   ins_cost(DEFAULT_COST * 3/2);
5924   format %{ "SET    $src,$dst" %}
5925   ins_encode( Set32(src, dst) );
5926   ins_pipe(ialu_hi_lo_reg);
5927 %}
5928 
5929 instruct loadConI13( iRegI dst, immI13 src ) %{
5930   match(Set dst src);
5931 
5932   size(4);
5933   format %{ "MOV    $src,$dst" %}
5934   ins_encode( Set13( src, dst ) );
5935   ins_pipe(ialu_imm);
5936 %}
5937 
5938 #ifndef _LP64
5939 instruct loadConP(iRegP dst, immP con) %{
5940   match(Set dst con);
5941   ins_cost(DEFAULT_COST * 3/2);
5942   format %{ "SET    $con,$dst\t!ptr" %}
5943   ins_encode %{
5944     relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5945       intptr_t val = $con$$constant;
5946     if (constant_reloc == relocInfo::oop_type) {
5947       __ set_oop_constant((jobject) val, $dst$$Register);
5948     } else if (constant_reloc == relocInfo::metadata_type) {
5949       __ set_metadata_constant((Metadata*)val, $dst$$Register);
5950     } else {          // non-oop pointers, e.g. card mark base, heap top
5951       assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5952       __ set(val, $dst$$Register);
5953     }
5954   %}
5955   ins_pipe(loadConP);
5956 %}
5957 #else
5958 instruct loadConP_set(iRegP dst, immP_set con) %{
5959   match(Set dst con);
5960   ins_cost(DEFAULT_COST * 3/2);
5961   format %{ "SET    $con,$dst\t! ptr" %}
5962   ins_encode %{
5963     relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
5964       intptr_t val = $con$$constant;
5965     if (constant_reloc == relocInfo::oop_type) {
5966       __ set_oop_constant((jobject) val, $dst$$Register);
5967     } else if (constant_reloc == relocInfo::metadata_type) {
5968       __ set_metadata_constant((Metadata*)val, $dst$$Register);
5969     } else {          // non-oop pointers, e.g. card mark base, heap top
5970       assert(constant_reloc == relocInfo::none, "unexpected reloc type");
5971       __ set(val, $dst$$Register);
5972     }
5973   %}
5974   ins_pipe(loadConP);
5975 %}
5976 
5977 instruct loadConP_load(iRegP dst, immP_load con) %{
5978   match(Set dst con);
5979   ins_cost(MEMORY_REF_COST);
5980   format %{ "LD     [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
5981   ins_encode %{
5982     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
5983     __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
5984   %}
5985   ins_pipe(loadConP);
5986 %}
5987 
5988 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
5989   match(Set dst con);
5990   ins_cost(DEFAULT_COST * 3/2);
5991   format %{ "SET    $con,$dst\t! non-oop ptr" %}
5992   ins_encode %{
5993     if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
5994       __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
5995     } else {
5996       __ set($con$$constant, $dst$$Register);
5997     }
5998   %}
5999   ins_pipe(loadConP);
6000 %}
6001 #endif // _LP64
6002 
6003 instruct loadConP0(iRegP dst, immP0 src) %{
6004   match(Set dst src);
6005 
6006   size(4);
6007   format %{ "CLR    $dst\t!ptr" %}
6008   ins_encode %{
6009     __ clr($dst$$Register);
6010   %}
6011   ins_pipe(ialu_imm);
6012 %}
6013 
6014 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6015   match(Set dst src);
6016   ins_cost(DEFAULT_COST);
6017   format %{ "SET    $src,$dst\t!ptr" %}
6018   ins_encode %{
6019     AddressLiteral polling_page(os::get_polling_page());
6020     __ sethi(polling_page, reg_to_register_object($dst$$reg));
6021   %}
6022   ins_pipe(loadConP_poll);
6023 %}
6024 
6025 instruct loadConN0(iRegN dst, immN0 src) %{
6026   match(Set dst src);
6027 
6028   size(4);
6029   format %{ "CLR    $dst\t! compressed NULL ptr" %}
6030   ins_encode %{
6031     __ clr($dst$$Register);
6032   %}
6033   ins_pipe(ialu_imm);
6034 %}
6035 
6036 instruct loadConN(iRegN dst, immN src) %{
6037   match(Set dst src);
6038   ins_cost(DEFAULT_COST * 3/2);
6039   format %{ "SET    $src,$dst\t! compressed ptr" %}
6040   ins_encode %{
6041     Register dst = $dst$$Register;
6042     __ set_narrow_oop((jobject)$src$$constant, dst);
6043   %}
6044   ins_pipe(ialu_hi_lo_reg);
6045 %}
6046 
6047 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6048   match(Set dst src);
6049   ins_cost(DEFAULT_COST * 3/2);
6050   format %{ "SET    $src,$dst\t! compressed klass ptr" %}
6051   ins_encode %{
6052     Register dst = $dst$$Register;
6053     __ set_narrow_klass((Klass*)$src$$constant, dst);
6054   %}
6055   ins_pipe(ialu_hi_lo_reg);
6056 %}
6057 
6058 // Materialize long value (predicated by immL_cheap).
6059 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6060   match(Set dst con);
6061   effect(KILL tmp);
6062   ins_cost(DEFAULT_COST * 3);
6063   format %{ "SET64   $con,$dst KILL $tmp\t! cheap long" %}
6064   ins_encode %{
6065     __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6066   %}
6067   ins_pipe(loadConL);
6068 %}
6069 
6070 // Load long value from constant table (predicated by immL_expensive).
6071 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6072   match(Set dst con);
6073   ins_cost(MEMORY_REF_COST);
6074   format %{ "LDX     [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6075   ins_encode %{
6076       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6077     __ ldx($constanttablebase, con_offset, $dst$$Register);
6078   %}
6079   ins_pipe(loadConL);
6080 %}
6081 
6082 instruct loadConL0( iRegL dst, immL0 src ) %{
6083   match(Set dst src);
6084   ins_cost(DEFAULT_COST);
6085   size(4);
6086   format %{ "CLR    $dst\t! long" %}
6087   ins_encode( Set13( src, dst ) );
6088   ins_pipe(ialu_imm);
6089 %}
6090 
6091 instruct loadConL13( iRegL dst, immL13 src ) %{
6092   match(Set dst src);
6093   ins_cost(DEFAULT_COST * 2);
6094 
6095   size(4);
6096   format %{ "MOV    $src,$dst\t! long" %}
6097   ins_encode( Set13( src, dst ) );
6098   ins_pipe(ialu_imm);
6099 %}
6100 
6101 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6102   match(Set dst con);
6103   effect(KILL tmp);
6104   format %{ "LDF    [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6105   ins_encode %{
6106       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6107     __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6108   %}
6109   ins_pipe(loadConFD);
6110 %}
6111 
6112 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6113   match(Set dst con);
6114   effect(KILL tmp);
6115   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6116   ins_encode %{
6117     // XXX This is a quick fix for 6833573.
6118     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6119     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6120     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6121   %}
6122   ins_pipe(loadConFD);
6123 %}
6124 
6125 // Prefetch instructions for allocation.
6126 // Must be safe to execute with invalid address (cannot fault).
6127 
6128 instruct prefetchAlloc( memory mem ) %{
6129   predicate(AllocatePrefetchInstr == 0);
6130   match( PrefetchAllocation mem );
6131   ins_cost(MEMORY_REF_COST);
6132 
6133   format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6134   opcode(Assembler::prefetch_op3);
6135   ins_encode( form3_mem_prefetch_write( mem ) );
6136   ins_pipe(iload_mem);
6137 %}
6138 
6139 // Use BIS instruction to prefetch for allocation.
6140 // Could fault, need space at the end of TLAB.
6141 instruct prefetchAlloc_bis( iRegP dst ) %{
6142   predicate(AllocatePrefetchInstr == 1);
6143   match( PrefetchAllocation dst );
6144   ins_cost(MEMORY_REF_COST);
6145   size(4);
6146 
6147   format %{ "STXA   [$dst]\t! // Prefetch allocation using BIS" %}
6148   ins_encode %{
6149     __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6150   %}
6151   ins_pipe(istore_mem_reg);
6152 %}
6153 
6154 // Next code is used for finding next cache line address to prefetch.
6155 #ifndef _LP64
6156 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6157   match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6158   ins_cost(DEFAULT_COST);
6159   size(4);
6160 
6161   format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
6162   ins_encode %{
6163     __ and3($src$$Register, $mask$$constant, $dst$$Register);
6164   %}
6165   ins_pipe(ialu_reg_imm);
6166 %}
6167 #else
6168 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6169   match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6170   ins_cost(DEFAULT_COST);
6171   size(4);
6172 
6173   format %{ "AND    $src,$mask,$dst\t! next cache line address" %}
6174   ins_encode %{
6175     __ and3($src$$Register, $mask$$constant, $dst$$Register);
6176   %}
6177   ins_pipe(ialu_reg_imm);
6178 %}
6179 #endif
6180 
6181 //----------Store Instructions-------------------------------------------------
6182 // Store Byte
6183 instruct storeB(memory mem, iRegI src) %{
6184   match(Set mem (StoreB mem src));
6185   ins_cost(MEMORY_REF_COST);
6186 
6187   format %{ "STB    $src,$mem\t! byte" %}
6188   opcode(Assembler::stb_op3);
6189   ins_encode(simple_form3_mem_reg( mem, src ) );
6190   ins_pipe(istore_mem_reg);
6191 %}
6192 
6193 instruct storeB0(memory mem, immI0 src) %{
6194   match(Set mem (StoreB mem src));
6195   ins_cost(MEMORY_REF_COST);
6196 
6197   format %{ "STB    $src,$mem\t! byte" %}
6198   opcode(Assembler::stb_op3);
6199   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6200   ins_pipe(istore_mem_zero);
6201 %}
6202 
6203 instruct storeCM0(memory mem, immI0 src) %{
6204   match(Set mem (StoreCM mem src));
6205   ins_cost(MEMORY_REF_COST);
6206 
6207   format %{ "STB    $src,$mem\t! CMS card-mark byte 0" %}
6208   opcode(Assembler::stb_op3);
6209   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6210   ins_pipe(istore_mem_zero);
6211 %}
6212 
6213 // Store Char/Short
6214 instruct storeC(memory mem, iRegI src) %{
6215   match(Set mem (StoreC mem src));
6216   ins_cost(MEMORY_REF_COST);
6217 
6218   format %{ "STH    $src,$mem\t! short" %}
6219   opcode(Assembler::sth_op3);
6220   ins_encode(simple_form3_mem_reg( mem, src ) );
6221   ins_pipe(istore_mem_reg);
6222 %}
6223 
6224 instruct storeC0(memory mem, immI0 src) %{
6225   match(Set mem (StoreC mem src));
6226   ins_cost(MEMORY_REF_COST);
6227 
6228   format %{ "STH    $src,$mem\t! short" %}
6229   opcode(Assembler::sth_op3);
6230   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6231   ins_pipe(istore_mem_zero);
6232 %}
6233 
6234 // Store Integer
6235 instruct storeI(memory mem, iRegI src) %{
6236   match(Set mem (StoreI mem src));
6237   ins_cost(MEMORY_REF_COST);
6238 
6239   format %{ "STW    $src,$mem" %}
6240   opcode(Assembler::stw_op3);
6241   ins_encode(simple_form3_mem_reg( mem, src ) );
6242   ins_pipe(istore_mem_reg);
6243 %}
6244 
6245 // Store Long
6246 instruct storeL(memory mem, iRegL src) %{
6247   match(Set mem (StoreL mem src));
6248   ins_cost(MEMORY_REF_COST);
6249   format %{ "STX    $src,$mem\t! long" %}
6250   opcode(Assembler::stx_op3);
6251   ins_encode(simple_form3_mem_reg( mem, src ) );
6252   ins_pipe(istore_mem_reg);
6253 %}
6254 
6255 instruct storeI0(memory mem, immI0 src) %{
6256   match(Set mem (StoreI mem src));
6257   ins_cost(MEMORY_REF_COST);
6258 
6259   format %{ "STW    $src,$mem" %}
6260   opcode(Assembler::stw_op3);
6261   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6262   ins_pipe(istore_mem_zero);
6263 %}
6264 
6265 instruct storeL0(memory mem, immL0 src) %{
6266   match(Set mem (StoreL mem src));
6267   ins_cost(MEMORY_REF_COST);
6268 
6269   format %{ "STX    $src,$mem" %}
6270   opcode(Assembler::stx_op3);
6271   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6272   ins_pipe(istore_mem_zero);
6273 %}
6274 
6275 // Store Integer from float register (used after fstoi)
6276 instruct storeI_Freg(memory mem, regF src) %{
6277   match(Set mem (StoreI mem src));
6278   ins_cost(MEMORY_REF_COST);
6279 
6280   format %{ "STF    $src,$mem\t! after fstoi/fdtoi" %}
6281   opcode(Assembler::stf_op3);
6282   ins_encode(simple_form3_mem_reg( mem, src ) );
6283   ins_pipe(fstoreF_mem_reg);
6284 %}
6285 
6286 // Store Pointer
6287 instruct storeP(memory dst, sp_ptr_RegP src) %{
6288   match(Set dst (StoreP dst src));
6289   ins_cost(MEMORY_REF_COST);
6290 
6291 #ifndef _LP64
6292   format %{ "STW    $src,$dst\t! ptr" %}
6293   opcode(Assembler::stw_op3, 0, REGP_OP);
6294 #else
6295   format %{ "STX    $src,$dst\t! ptr" %}
6296   opcode(Assembler::stx_op3, 0, REGP_OP);
6297 #endif
6298   ins_encode( form3_mem_reg( dst, src ) );
6299   ins_pipe(istore_mem_spORreg);
6300 %}
6301 
6302 instruct storeP0(memory dst, immP0 src) %{
6303   match(Set dst (StoreP dst src));
6304   ins_cost(MEMORY_REF_COST);
6305 
6306 #ifndef _LP64
6307   format %{ "STW    $src,$dst\t! ptr" %}
6308   opcode(Assembler::stw_op3, 0, REGP_OP);
6309 #else
6310   format %{ "STX    $src,$dst\t! ptr" %}
6311   opcode(Assembler::stx_op3, 0, REGP_OP);
6312 #endif
6313   ins_encode( form3_mem_reg( dst, R_G0 ) );
6314   ins_pipe(istore_mem_zero);
6315 %}
6316 
6317 // Store Compressed Pointer
6318 instruct storeN(memory dst, iRegN src) %{
6319    match(Set dst (StoreN dst src));
6320    ins_cost(MEMORY_REF_COST);
6321    size(4);
6322 
6323    format %{ "STW    $src,$dst\t! compressed ptr" %}
6324    ins_encode %{
6325      Register base = as_Register($dst$$base);
6326      Register index = as_Register($dst$$index);
6327      Register src = $src$$Register;
6328      if (index != G0) {
6329        __ stw(src, base, index);
6330      } else {
6331        __ stw(src, base, $dst$$disp);
6332      }
6333    %}
6334    ins_pipe(istore_mem_spORreg);
6335 %}
6336 
6337 instruct storeNKlass(memory dst, iRegN src) %{
6338    match(Set dst (StoreNKlass dst src));
6339    ins_cost(MEMORY_REF_COST);
6340    size(4);
6341 
6342    format %{ "STW    $src,$dst\t! compressed klass ptr" %}
6343    ins_encode %{
6344      Register base = as_Register($dst$$base);
6345      Register index = as_Register($dst$$index);
6346      Register src = $src$$Register;
6347      if (index != G0) {
6348        __ stw(src, base, index);
6349      } else {
6350        __ stw(src, base, $dst$$disp);
6351      }
6352    %}
6353    ins_pipe(istore_mem_spORreg);
6354 %}
6355 
6356 instruct storeN0(memory dst, immN0 src) %{
6357    match(Set dst (StoreN dst src));
6358    ins_cost(MEMORY_REF_COST);
6359    size(4);
6360 
6361    format %{ "STW    $src,$dst\t! compressed ptr" %}
6362    ins_encode %{
6363      Register base = as_Register($dst$$base);
6364      Register index = as_Register($dst$$index);
6365      if (index != G0) {
6366        __ stw(0, base, index);
6367      } else {
6368        __ stw(0, base, $dst$$disp);
6369      }
6370    %}
6371    ins_pipe(istore_mem_zero);
6372 %}
6373 
6374 // Store Double
6375 instruct storeD( memory mem, regD src) %{
6376   match(Set mem (StoreD mem src));
6377   ins_cost(MEMORY_REF_COST);
6378 
6379   format %{ "STDF   $src,$mem" %}
6380   opcode(Assembler::stdf_op3);
6381   ins_encode(simple_form3_mem_reg( mem, src ) );
6382   ins_pipe(fstoreD_mem_reg);
6383 %}
6384 
6385 instruct storeD0( memory mem, immD0 src) %{
6386   match(Set mem (StoreD mem src));
6387   ins_cost(MEMORY_REF_COST);
6388 
6389   format %{ "STX    $src,$mem" %}
6390   opcode(Assembler::stx_op3);
6391   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6392   ins_pipe(fstoreD_mem_zero);
6393 %}
6394 
6395 // Store Float
6396 instruct storeF( memory mem, regF src) %{
6397   match(Set mem (StoreF mem src));
6398   ins_cost(MEMORY_REF_COST);
6399 
6400   format %{ "STF    $src,$mem" %}
6401   opcode(Assembler::stf_op3);
6402   ins_encode(simple_form3_mem_reg( mem, src ) );
6403   ins_pipe(fstoreF_mem_reg);
6404 %}
6405 
6406 instruct storeF0( memory mem, immF0 src) %{
6407   match(Set mem (StoreF mem src));
6408   ins_cost(MEMORY_REF_COST);
6409 
6410   format %{ "STW    $src,$mem\t! storeF0" %}
6411   opcode(Assembler::stw_op3);
6412   ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6413   ins_pipe(fstoreF_mem_zero);
6414 %}
6415 
6416 // Convert oop pointer into compressed form
6417 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6418   predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6419   match(Set dst (EncodeP src));
6420   format %{ "encode_heap_oop $src, $dst" %}
6421   ins_encode %{
6422     __ encode_heap_oop($src$$Register, $dst$$Register);
6423   %}
6424   ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6425   ins_pipe(ialu_reg);
6426 %}
6427 
6428 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6429   predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6430   match(Set dst (EncodeP src));
6431   format %{ "encode_heap_oop_not_null $src, $dst" %}
6432   ins_encode %{
6433     __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6434   %}
6435   ins_pipe(ialu_reg);
6436 %}
6437 
6438 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6439   predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6440             n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6441   match(Set dst (DecodeN src));
6442   format %{ "decode_heap_oop $src, $dst" %}
6443   ins_encode %{
6444     __ decode_heap_oop($src$$Register, $dst$$Register);
6445   %}
6446   ins_pipe(ialu_reg);
6447 %}
6448 
6449 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6450   predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6451             n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6452   match(Set dst (DecodeN src));
6453   format %{ "decode_heap_oop_not_null $src, $dst" %}
6454   ins_encode %{
6455     __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6456   %}
6457   ins_pipe(ialu_reg);
6458 %}
6459 
6460 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6461   match(Set dst (EncodePKlass src));
6462   format %{ "encode_klass_not_null $src, $dst" %}
6463   ins_encode %{
6464     __ encode_klass_not_null($src$$Register, $dst$$Register);
6465   %}
6466   ins_pipe(ialu_reg);
6467 %}
6468 
6469 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6470   match(Set dst (DecodeNKlass src));
6471   format %{ "decode_klass_not_null $src, $dst" %}
6472   ins_encode %{
6473     __ decode_klass_not_null($src$$Register, $dst$$Register);
6474   %}
6475   ins_pipe(ialu_reg);
6476 %}
6477 
6478 //----------MemBar Instructions-----------------------------------------------
6479 // Memory barrier flavors
6480 
6481 instruct membar_acquire() %{
6482   match(MemBarAcquire);
6483   match(LoadFence);
6484   ins_cost(4*MEMORY_REF_COST);
6485 
6486   size(0);
6487   format %{ "MEMBAR-acquire" %}
6488   ins_encode( enc_membar_acquire );
6489   ins_pipe(long_memory_op);
6490 %}
6491 
6492 instruct membar_acquire_lock() %{
6493   match(MemBarAcquireLock);
6494   ins_cost(0);
6495 
6496   size(0);
6497   format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6498   ins_encode( );
6499   ins_pipe(empty);
6500 %}
6501 
6502 instruct membar_release() %{
6503   match(MemBarRelease);
6504   match(StoreFence);
6505   ins_cost(4*MEMORY_REF_COST);
6506 
6507   size(0);
6508   format %{ "MEMBAR-release" %}
6509   ins_encode( enc_membar_release );
6510   ins_pipe(long_memory_op);
6511 %}
6512 
6513 instruct membar_release_lock() %{
6514   match(MemBarReleaseLock);
6515   ins_cost(0);
6516 
6517   size(0);
6518   format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6519   ins_encode( );
6520   ins_pipe(empty);
6521 %}
6522 
6523 instruct membar_volatile() %{
6524   match(MemBarVolatile);
6525   ins_cost(4*MEMORY_REF_COST);
6526 
6527   size(4);
6528   format %{ "MEMBAR-volatile" %}
6529   ins_encode( enc_membar_volatile );
6530   ins_pipe(long_memory_op);
6531 %}
6532 
6533 instruct unnecessary_membar_volatile() %{
6534   match(MemBarVolatile);
6535   predicate(Matcher::post_store_load_barrier(n));
6536   ins_cost(0);
6537 
6538   size(0);
6539   format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6540   ins_encode( );
6541   ins_pipe(empty);
6542 %}
6543 
6544 instruct membar_storestore() %{
6545   match(MemBarStoreStore);
6546   ins_cost(0);
6547 
6548   size(0);
6549   format %{ "!MEMBAR-storestore (empty encoding)" %}
6550   ins_encode( );
6551   ins_pipe(empty);
6552 %}
6553 
6554 //----------Register Move Instructions-----------------------------------------
6555 instruct roundDouble_nop(regD dst) %{
6556   match(Set dst (RoundDouble dst));
6557   ins_cost(0);
6558   // SPARC results are already "rounded" (i.e., normal-format IEEE)
6559   ins_encode( );
6560   ins_pipe(empty);
6561 %}
6562 
6563 
6564 instruct roundFloat_nop(regF dst) %{
6565   match(Set dst (RoundFloat dst));
6566   ins_cost(0);
6567   // SPARC results are already "rounded" (i.e., normal-format IEEE)
6568   ins_encode( );
6569   ins_pipe(empty);
6570 %}
6571 
6572 
6573 // Cast Index to Pointer for unsafe natives
6574 instruct castX2P(iRegX src, iRegP dst) %{
6575   match(Set dst (CastX2P src));
6576 
6577   format %{ "MOV    $src,$dst\t! IntX->Ptr" %}
6578   ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6579   ins_pipe(ialu_reg);
6580 %}
6581 
6582 // Cast Pointer to Index for unsafe natives
6583 instruct castP2X(iRegP src, iRegX dst) %{
6584   match(Set dst (CastP2X src));
6585 
6586   format %{ "MOV    $src,$dst\t! Ptr->IntX" %}
6587   ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6588   ins_pipe(ialu_reg);
6589 %}
6590 
6591 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6592   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6593   match(Set stkSlot src);   // chain rule
6594   ins_cost(MEMORY_REF_COST);
6595   format %{ "STDF   $src,$stkSlot\t!stk" %}
6596   opcode(Assembler::stdf_op3);
6597   ins_encode(simple_form3_mem_reg(stkSlot, src));
6598   ins_pipe(fstoreD_stk_reg);
6599 %}
6600 
6601 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6602   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6603   match(Set dst stkSlot);   // chain rule
6604   ins_cost(MEMORY_REF_COST);
6605   format %{ "LDDF   $stkSlot,$dst\t!stk" %}
6606   opcode(Assembler::lddf_op3);
6607   ins_encode(simple_form3_mem_reg(stkSlot, dst));
6608   ins_pipe(floadD_stk);
6609 %}
6610 
6611 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6612   // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6613   match(Set stkSlot src);   // chain rule
6614   ins_cost(MEMORY_REF_COST);
6615   format %{ "STF   $src,$stkSlot\t!stk" %}
6616   opcode(Assembler::stf_op3);
6617   ins_encode(simple_form3_mem_reg(stkSlot, src));
6618   ins_pipe(fstoreF_stk_reg);
6619 %}
6620 
6621 //----------Conditional Move---------------------------------------------------
6622 // Conditional move
6623 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6624   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6625   ins_cost(150);
6626   format %{ "MOV$cmp $pcc,$src,$dst" %}
6627   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6628   ins_pipe(ialu_reg);
6629 %}
6630 
6631 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6632   match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6633   ins_cost(140);
6634   format %{ "MOV$cmp $pcc,$src,$dst" %}
6635   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6636   ins_pipe(ialu_imm);
6637 %}
6638 
6639 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6640   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6641   ins_cost(150);
6642   size(4);
6643   format %{ "MOV$cmp  $icc,$src,$dst" %}
6644   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6645   ins_pipe(ialu_reg);
6646 %}
6647 
6648 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6649   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6650   ins_cost(140);
6651   size(4);
6652   format %{ "MOV$cmp  $icc,$src,$dst" %}
6653   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6654   ins_pipe(ialu_imm);
6655 %}
6656 
6657 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6658   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6659   ins_cost(150);
6660   size(4);
6661   format %{ "MOV$cmp  $icc,$src,$dst" %}
6662   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6663   ins_pipe(ialu_reg);
6664 %}
6665 
6666 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6667   match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6668   ins_cost(140);
6669   size(4);
6670   format %{ "MOV$cmp  $icc,$src,$dst" %}
6671   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6672   ins_pipe(ialu_imm);
6673 %}
6674 
6675 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6676   match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6677   ins_cost(150);
6678   size(4);
6679   format %{ "MOV$cmp $fcc,$src,$dst" %}
6680   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6681   ins_pipe(ialu_reg);
6682 %}
6683 
6684 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6685   match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6686   ins_cost(140);
6687   size(4);
6688   format %{ "MOV$cmp $fcc,$src,$dst" %}
6689   ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6690   ins_pipe(ialu_imm);
6691 %}
6692 
6693 // Conditional move for RegN. Only cmov(reg,reg).
6694 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6695   match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6696   ins_cost(150);
6697   format %{ "MOV$cmp $pcc,$src,$dst" %}
6698   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6699   ins_pipe(ialu_reg);
6700 %}
6701 
6702 // This instruction also works with CmpN so we don't need cmovNN_reg.
6703 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6704   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6705   ins_cost(150);
6706   size(4);
6707   format %{ "MOV$cmp  $icc,$src,$dst" %}
6708   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6709   ins_pipe(ialu_reg);
6710 %}
6711 
6712 // This instruction also works with CmpN so we don't need cmovNN_reg.
6713 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6714   match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6715   ins_cost(150);
6716   size(4);
6717   format %{ "MOV$cmp  $icc,$src,$dst" %}
6718   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6719   ins_pipe(ialu_reg);
6720 %}
6721 
6722 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6723   match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6724   ins_cost(150);
6725   size(4);
6726   format %{ "MOV$cmp $fcc,$src,$dst" %}
6727   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6728   ins_pipe(ialu_reg);
6729 %}
6730 
6731 // Conditional move
6732 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6733   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6734   ins_cost(150);
6735   format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6736   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6737   ins_pipe(ialu_reg);
6738 %}
6739 
6740 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6741   match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6742   ins_cost(140);
6743   format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6744   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6745   ins_pipe(ialu_imm);
6746 %}
6747 
6748 // This instruction also works with CmpN so we don't need cmovPN_reg.
6749 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6750   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6751   ins_cost(150);
6752 
6753   size(4);
6754   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6755   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6756   ins_pipe(ialu_reg);
6757 %}
6758 
6759 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6760   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6761   ins_cost(150);
6762 
6763   size(4);
6764   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6765   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6766   ins_pipe(ialu_reg);
6767 %}
6768 
6769 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6770   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6771   ins_cost(140);
6772 
6773   size(4);
6774   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6775   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6776   ins_pipe(ialu_imm);
6777 %}
6778 
6779 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6780   match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6781   ins_cost(140);
6782 
6783   size(4);
6784   format %{ "MOV$cmp  $icc,$src,$dst\t! ptr" %}
6785   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6786   ins_pipe(ialu_imm);
6787 %}
6788 
6789 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6790   match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6791   ins_cost(150);
6792   size(4);
6793   format %{ "MOV$cmp $fcc,$src,$dst" %}
6794   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6795   ins_pipe(ialu_imm);
6796 %}
6797 
6798 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
6799   match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
6800   ins_cost(140);
6801   size(4);
6802   format %{ "MOV$cmp $fcc,$src,$dst" %}
6803   ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6804   ins_pipe(ialu_imm);
6805 %}
6806 
6807 // Conditional move
6808 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
6809   match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
6810   ins_cost(150);
6811   opcode(0x101);
6812   format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6813   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6814   ins_pipe(int_conditional_float_move);
6815 %}
6816 
6817 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
6818   match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6819   ins_cost(150);
6820 
6821   size(4);
6822   format %{ "FMOVS$cmp $icc,$src,$dst" %}
6823   opcode(0x101);
6824   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6825   ins_pipe(int_conditional_float_move);
6826 %}
6827 
6828 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
6829   match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
6830   ins_cost(150);
6831 
6832   size(4);
6833   format %{ "FMOVS$cmp $icc,$src,$dst" %}
6834   opcode(0x101);
6835   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6836   ins_pipe(int_conditional_float_move);
6837 %}
6838 
6839 // Conditional move,
6840 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
6841   match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
6842   ins_cost(150);
6843   size(4);
6844   format %{ "FMOVF$cmp $fcc,$src,$dst" %}
6845   opcode(0x1);
6846   ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6847   ins_pipe(int_conditional_double_move);
6848 %}
6849 
6850 // Conditional move
6851 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
6852   match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
6853   ins_cost(150);
6854   size(4);
6855   opcode(0x102);
6856   format %{ "FMOVD$cmp $pcc,$src,$dst" %}
6857   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6858   ins_pipe(int_conditional_double_move);
6859 %}
6860 
6861 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
6862   match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6863   ins_cost(150);
6864 
6865   size(4);
6866   format %{ "FMOVD$cmp $icc,$src,$dst" %}
6867   opcode(0x102);
6868   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6869   ins_pipe(int_conditional_double_move);
6870 %}
6871 
6872 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
6873   match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
6874   ins_cost(150);
6875 
6876   size(4);
6877   format %{ "FMOVD$cmp $icc,$src,$dst" %}
6878   opcode(0x102);
6879   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
6880   ins_pipe(int_conditional_double_move);
6881 %}
6882 
6883 // Conditional move,
6884 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
6885   match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
6886   ins_cost(150);
6887   size(4);
6888   format %{ "FMOVD$cmp $fcc,$src,$dst" %}
6889   opcode(0x2);
6890   ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
6891   ins_pipe(int_conditional_double_move);
6892 %}
6893 
6894 // Conditional move
6895 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
6896   match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6897   ins_cost(150);
6898   format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6899   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6900   ins_pipe(ialu_reg);
6901 %}
6902 
6903 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
6904   match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
6905   ins_cost(140);
6906   format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
6907   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6908   ins_pipe(ialu_imm);
6909 %}
6910 
6911 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
6912   match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6913   ins_cost(150);
6914 
6915   size(4);
6916   format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
6917   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6918   ins_pipe(ialu_reg);
6919 %}
6920 
6921 
6922 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
6923   match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
6924   ins_cost(150);
6925 
6926   size(4);
6927   format %{ "MOV$cmp  $icc,$src,$dst\t! long" %}
6928   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6929   ins_pipe(ialu_reg);
6930 %}
6931 
6932 
6933 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
6934   match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
6935   ins_cost(150);
6936 
6937   size(4);
6938   format %{ "MOV$cmp  $fcc,$src,$dst\t! long" %}
6939   ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6940   ins_pipe(ialu_reg);
6941 %}
6942 
6943 
6944 
6945 //----------OS and Locking Instructions----------------------------------------
6946 
6947 // This name is KNOWN by the ADLC and cannot be changed.
6948 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
6949 // for this guy.
6950 instruct tlsLoadP(g2RegP dst) %{
6951   match(Set dst (ThreadLocal));
6952 
6953   size(0);
6954   ins_cost(0);
6955   format %{ "# TLS is in G2" %}
6956   ins_encode( /*empty encoding*/ );
6957   ins_pipe(ialu_none);
6958 %}
6959 
6960 instruct checkCastPP( iRegP dst ) %{
6961   match(Set dst (CheckCastPP dst));
6962 
6963   size(0);
6964   format %{ "# checkcastPP of $dst" %}
6965   ins_encode( /*empty encoding*/ );
6966   ins_pipe(empty);
6967 %}
6968 
6969 
6970 instruct castPP( iRegP dst ) %{
6971   match(Set dst (CastPP dst));
6972   format %{ "# castPP of $dst" %}
6973   ins_encode( /*empty encoding*/ );
6974   ins_pipe(empty);
6975 %}
6976 
6977 instruct castII( iRegI dst ) %{
6978   match(Set dst (CastII dst));
6979   format %{ "# castII of $dst" %}
6980   ins_encode( /*empty encoding*/ );
6981   ins_cost(0);
6982   ins_pipe(empty);
6983 %}
6984 
6985 //----------Arithmetic Instructions--------------------------------------------
6986 // Addition Instructions
6987 // Register Addition
6988 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
6989   match(Set dst (AddI src1 src2));
6990 
6991   size(4);
6992   format %{ "ADD    $src1,$src2,$dst" %}
6993   ins_encode %{
6994     __ add($src1$$Register, $src2$$Register, $dst$$Register);
6995   %}
6996   ins_pipe(ialu_reg_reg);
6997 %}
6998 
6999 // Immediate Addition
7000 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7001   match(Set dst (AddI src1 src2));
7002 
7003   size(4);
7004   format %{ "ADD    $src1,$src2,$dst" %}
7005   opcode(Assembler::add_op3, Assembler::arith_op);
7006   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7007   ins_pipe(ialu_reg_imm);
7008 %}
7009 
7010 // Pointer Register Addition
7011 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7012   match(Set dst (AddP src1 src2));
7013 
7014   size(4);
7015   format %{ "ADD    $src1,$src2,$dst" %}
7016   opcode(Assembler::add_op3, Assembler::arith_op);
7017   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7018   ins_pipe(ialu_reg_reg);
7019 %}
7020 
7021 // Pointer Immediate Addition
7022 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7023   match(Set dst (AddP src1 src2));
7024 
7025   size(4);
7026   format %{ "ADD    $src1,$src2,$dst" %}
7027   opcode(Assembler::add_op3, Assembler::arith_op);
7028   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7029   ins_pipe(ialu_reg_imm);
7030 %}
7031 
7032 // Long Addition
7033 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7034   match(Set dst (AddL src1 src2));
7035 
7036   size(4);
7037   format %{ "ADD    $src1,$src2,$dst\t! long" %}
7038   opcode(Assembler::add_op3, Assembler::arith_op);
7039   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7040   ins_pipe(ialu_reg_reg);
7041 %}
7042 
7043 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7044   match(Set dst (AddL src1 con));
7045 
7046   size(4);
7047   format %{ "ADD    $src1,$con,$dst" %}
7048   opcode(Assembler::add_op3, Assembler::arith_op);
7049   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7050   ins_pipe(ialu_reg_imm);
7051 %}
7052 
7053 //----------Conditional_store--------------------------------------------------
7054 // Conditional-store of the updated heap-top.
7055 // Used during allocation of the shared heap.
7056 // Sets flags (EQ) on success.  Implemented with a CASA on Sparc.
7057 
7058 // LoadP-locked.  Same as a regular pointer load when used with a compare-swap
7059 instruct loadPLocked(iRegP dst, memory mem) %{
7060   match(Set dst (LoadPLocked mem));
7061   ins_cost(MEMORY_REF_COST);
7062 
7063 #ifndef _LP64
7064   format %{ "LDUW   $mem,$dst\t! ptr" %}
7065   opcode(Assembler::lduw_op3, 0, REGP_OP);
7066 #else
7067   format %{ "LDX    $mem,$dst\t! ptr" %}
7068   opcode(Assembler::ldx_op3, 0, REGP_OP);
7069 #endif
7070   ins_encode( form3_mem_reg( mem, dst ) );
7071   ins_pipe(iload_mem);
7072 %}
7073 
7074 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7075   match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7076   effect( KILL newval );
7077   format %{ "CASA   [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7078             "CMP    R_G3,$oldval\t\t! See if we made progress"  %}
7079   ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7080   ins_pipe( long_memory_op );
7081 %}
7082 
7083 // Conditional-store of an int value.
7084 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7085   match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7086   effect( KILL newval );
7087   format %{ "CASA   [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7088             "CMP    $oldval,$newval\t\t! See if we made progress"  %}
7089   ins_encode( enc_cas(mem_ptr,oldval,newval) );
7090   ins_pipe( long_memory_op );
7091 %}
7092 
7093 // Conditional-store of a long value.
7094 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7095   match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7096   effect( KILL newval );
7097   format %{ "CASXA  [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7098             "CMP    $oldval,$newval\t\t! See if we made progress"  %}
7099   ins_encode( enc_cas(mem_ptr,oldval,newval) );
7100   ins_pipe( long_memory_op );
7101 %}
7102 
7103 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7104 
7105 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7106   predicate(VM_Version::supports_cx8());
7107   match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7108   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7109   format %{
7110             "MOV    $newval,O7\n\t"
7111             "CASXA  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7112             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7113             "MOV    1,$res\n\t"
7114             "MOVne  xcc,R_G0,$res"
7115   %}
7116   ins_encode( enc_casx(mem_ptr, oldval, newval),
7117               enc_lflags_ne_to_boolean(res) );
7118   ins_pipe( long_memory_op );
7119 %}
7120 
7121 
7122 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7123   match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7124   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7125   format %{
7126             "MOV    $newval,O7\n\t"
7127             "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7128             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7129             "MOV    1,$res\n\t"
7130             "MOVne  icc,R_G0,$res"
7131   %}
7132   ins_encode( enc_casi(mem_ptr, oldval, newval),
7133               enc_iflags_ne_to_boolean(res) );
7134   ins_pipe( long_memory_op );
7135 %}
7136 
7137 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7138 #ifdef _LP64
7139   predicate(VM_Version::supports_cx8());
7140 #endif
7141   match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7142   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7143   format %{
7144             "MOV    $newval,O7\n\t"
7145             "CASA_PTR  [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7146             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7147             "MOV    1,$res\n\t"
7148             "MOVne  xcc,R_G0,$res"
7149   %}
7150 #ifdef _LP64
7151   ins_encode( enc_casx(mem_ptr, oldval, newval),
7152               enc_lflags_ne_to_boolean(res) );
7153 #else
7154   ins_encode( enc_casi(mem_ptr, oldval, newval),
7155               enc_iflags_ne_to_boolean(res) );
7156 #endif
7157   ins_pipe( long_memory_op );
7158 %}
7159 
7160 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7161   match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7162   effect( USE mem_ptr, KILL ccr, KILL tmp1);
7163   format %{
7164             "MOV    $newval,O7\n\t"
7165             "CASA   [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7166             "CMP    $oldval,O7\t\t! See if we made progress\n\t"
7167             "MOV    1,$res\n\t"
7168             "MOVne  icc,R_G0,$res"
7169   %}
7170   ins_encode( enc_casi(mem_ptr, oldval, newval),
7171               enc_iflags_ne_to_boolean(res) );
7172   ins_pipe( long_memory_op );
7173 %}
7174 
7175 instruct xchgI( memory mem, iRegI newval) %{
7176   match(Set newval (GetAndSetI mem newval));
7177   format %{ "SWAP  [$mem],$newval" %}
7178   size(4);
7179   ins_encode %{
7180     __ swap($mem$$Address, $newval$$Register);
7181   %}
7182   ins_pipe( long_memory_op );
7183 %}
7184 
7185 #ifndef _LP64
7186 instruct xchgP( memory mem, iRegP newval) %{
7187   match(Set newval (GetAndSetP mem newval));
7188   format %{ "SWAP  [$mem],$newval" %}
7189   size(4);
7190   ins_encode %{
7191     __ swap($mem$$Address, $newval$$Register);
7192   %}
7193   ins_pipe( long_memory_op );
7194 %}
7195 #endif
7196 
7197 instruct xchgN( memory mem, iRegN newval) %{
7198   match(Set newval (GetAndSetN mem newval));
7199   format %{ "SWAP  [$mem],$newval" %}
7200   size(4);
7201   ins_encode %{
7202     __ swap($mem$$Address, $newval$$Register);
7203   %}
7204   ins_pipe( long_memory_op );
7205 %}
7206 
7207 //---------------------
7208 // Subtraction Instructions
7209 // Register Subtraction
7210 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7211   match(Set dst (SubI src1 src2));
7212 
7213   size(4);
7214   format %{ "SUB    $src1,$src2,$dst" %}
7215   opcode(Assembler::sub_op3, Assembler::arith_op);
7216   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7217   ins_pipe(ialu_reg_reg);
7218 %}
7219 
7220 // Immediate Subtraction
7221 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7222   match(Set dst (SubI src1 src2));
7223 
7224   size(4);
7225   format %{ "SUB    $src1,$src2,$dst" %}
7226   opcode(Assembler::sub_op3, Assembler::arith_op);
7227   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7228   ins_pipe(ialu_reg_imm);
7229 %}
7230 
7231 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7232   match(Set dst (SubI zero src2));
7233 
7234   size(4);
7235   format %{ "NEG    $src2,$dst" %}
7236   opcode(Assembler::sub_op3, Assembler::arith_op);
7237   ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7238   ins_pipe(ialu_zero_reg);
7239 %}
7240 
7241 // Long subtraction
7242 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7243   match(Set dst (SubL src1 src2));
7244 
7245   size(4);
7246   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7247   opcode(Assembler::sub_op3, Assembler::arith_op);
7248   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7249   ins_pipe(ialu_reg_reg);
7250 %}
7251 
7252 // Immediate Subtraction
7253 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7254   match(Set dst (SubL src1 con));
7255 
7256   size(4);
7257   format %{ "SUB    $src1,$con,$dst\t! long" %}
7258   opcode(Assembler::sub_op3, Assembler::arith_op);
7259   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7260   ins_pipe(ialu_reg_imm);
7261 %}
7262 
7263 // Long negation
7264 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7265   match(Set dst (SubL zero src2));
7266 
7267   size(4);
7268   format %{ "NEG    $src2,$dst\t! long" %}
7269   opcode(Assembler::sub_op3, Assembler::arith_op);
7270   ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7271   ins_pipe(ialu_zero_reg);
7272 %}
7273 
7274 // Multiplication Instructions
7275 // Integer Multiplication
7276 // Register Multiplication
7277 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7278   match(Set dst (MulI src1 src2));
7279 
7280   size(4);
7281   format %{ "MULX   $src1,$src2,$dst" %}
7282   opcode(Assembler::mulx_op3, Assembler::arith_op);
7283   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7284   ins_pipe(imul_reg_reg);
7285 %}
7286 
7287 // Immediate Multiplication
7288 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7289   match(Set dst (MulI src1 src2));
7290 
7291   size(4);
7292   format %{ "MULX   $src1,$src2,$dst" %}
7293   opcode(Assembler::mulx_op3, Assembler::arith_op);
7294   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7295   ins_pipe(imul_reg_imm);
7296 %}
7297 
7298 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7299   match(Set dst (MulL src1 src2));
7300   ins_cost(DEFAULT_COST * 5);
7301   size(4);
7302   format %{ "MULX   $src1,$src2,$dst\t! long" %}
7303   opcode(Assembler::mulx_op3, Assembler::arith_op);
7304   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7305   ins_pipe(mulL_reg_reg);
7306 %}
7307 
7308 // Immediate Multiplication
7309 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7310   match(Set dst (MulL src1 src2));
7311   ins_cost(DEFAULT_COST * 5);
7312   size(4);
7313   format %{ "MULX   $src1,$src2,$dst" %}
7314   opcode(Assembler::mulx_op3, Assembler::arith_op);
7315   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7316   ins_pipe(mulL_reg_imm);
7317 %}
7318 
7319 // Integer Division
7320 // Register Division
7321 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7322   match(Set dst (DivI src1 src2));
7323   ins_cost((2+71)*DEFAULT_COST);
7324 
7325   format %{ "SRA     $src2,0,$src2\n\t"
7326             "SRA     $src1,0,$src1\n\t"
7327             "SDIVX   $src1,$src2,$dst" %}
7328   ins_encode( idiv_reg( src1, src2, dst ) );
7329   ins_pipe(sdiv_reg_reg);
7330 %}
7331 
7332 // Immediate Division
7333 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7334   match(Set dst (DivI src1 src2));
7335   ins_cost((2+71)*DEFAULT_COST);
7336 
7337   format %{ "SRA     $src1,0,$src1\n\t"
7338             "SDIVX   $src1,$src2,$dst" %}
7339   ins_encode( idiv_imm( src1, src2, dst ) );
7340   ins_pipe(sdiv_reg_imm);
7341 %}
7342 
7343 //----------Div-By-10-Expansion------------------------------------------------
7344 // Extract hi bits of a 32x32->64 bit multiply.
7345 // Expand rule only, not matched
7346 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7347   effect( DEF dst, USE src1, USE src2 );
7348   format %{ "MULX   $src1,$src2,$dst\t! Used in div-by-10\n\t"
7349             "SRLX   $dst,#32,$dst\t\t! Extract only hi word of result" %}
7350   ins_encode( enc_mul_hi(dst,src1,src2));
7351   ins_pipe(sdiv_reg_reg);
7352 %}
7353 
7354 // Magic constant, reciprocal of 10
7355 instruct loadConI_x66666667(iRegIsafe dst) %{
7356   effect( DEF dst );
7357 
7358   size(8);
7359   format %{ "SET    0x66666667,$dst\t! Used in div-by-10" %}
7360   ins_encode( Set32(0x66666667, dst) );
7361   ins_pipe(ialu_hi_lo_reg);
7362 %}
7363 
7364 // Register Shift Right Arithmetic Long by 32-63
7365 instruct sra_31( iRegI dst, iRegI src ) %{
7366   effect( DEF dst, USE src );
7367   format %{ "SRA    $src,31,$dst\t! Used in div-by-10" %}
7368   ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7369   ins_pipe(ialu_reg_reg);
7370 %}
7371 
7372 // Arithmetic Shift Right by 8-bit immediate
7373 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7374   effect( DEF dst, USE src );
7375   format %{ "SRA    $src,2,$dst\t! Used in div-by-10" %}
7376   opcode(Assembler::sra_op3, Assembler::arith_op);
7377   ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7378   ins_pipe(ialu_reg_imm);
7379 %}
7380 
7381 // Integer DIV with 10
7382 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7383   match(Set dst (DivI src div));
7384   ins_cost((6+6)*DEFAULT_COST);
7385   expand %{
7386     iRegIsafe tmp1;               // Killed temps;
7387     iRegIsafe tmp2;               // Killed temps;
7388     iRegI tmp3;                   // Killed temps;
7389     iRegI tmp4;                   // Killed temps;
7390     loadConI_x66666667( tmp1 );   // SET  0x66666667 -> tmp1
7391     mul_hi( tmp2, src, tmp1 );    // MUL  hibits(src * tmp1) -> tmp2
7392     sra_31( tmp3, src );          // SRA  src,31 -> tmp3
7393     sra_reg_2( tmp4, tmp2 );      // SRA  tmp2,2 -> tmp4
7394     subI_reg_reg( dst,tmp4,tmp3); // SUB  tmp4 - tmp3 -> dst
7395   %}
7396 %}
7397 
7398 // Register Long Division
7399 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7400   match(Set dst (DivL src1 src2));
7401   ins_cost(DEFAULT_COST*71);
7402   size(4);
7403   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7404   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7405   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7406   ins_pipe(divL_reg_reg);
7407 %}
7408 
7409 // Register Long Division
7410 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7411   match(Set dst (DivL src1 src2));
7412   ins_cost(DEFAULT_COST*71);
7413   size(4);
7414   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7415   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7416   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7417   ins_pipe(divL_reg_imm);
7418 %}
7419 
7420 // Integer Remainder
7421 // Register Remainder
7422 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7423   match(Set dst (ModI src1 src2));
7424   effect( KILL ccr, KILL temp);
7425 
7426   format %{ "SREM   $src1,$src2,$dst" %}
7427   ins_encode( irem_reg(src1, src2, dst, temp) );
7428   ins_pipe(sdiv_reg_reg);
7429 %}
7430 
7431 // Immediate Remainder
7432 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7433   match(Set dst (ModI src1 src2));
7434   effect( KILL ccr, KILL temp);
7435 
7436   format %{ "SREM   $src1,$src2,$dst" %}
7437   ins_encode( irem_imm(src1, src2, dst, temp) );
7438   ins_pipe(sdiv_reg_imm);
7439 %}
7440 
7441 // Register Long Remainder
7442 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7443   effect(DEF dst, USE src1, USE src2);
7444   size(4);
7445   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7446   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7447   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7448   ins_pipe(divL_reg_reg);
7449 %}
7450 
7451 // Register Long Division
7452 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7453   effect(DEF dst, USE src1, USE src2);
7454   size(4);
7455   format %{ "SDIVX  $src1,$src2,$dst\t! long" %}
7456   opcode(Assembler::sdivx_op3, Assembler::arith_op);
7457   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7458   ins_pipe(divL_reg_imm);
7459 %}
7460 
7461 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7462   effect(DEF dst, USE src1, USE src2);
7463   size(4);
7464   format %{ "MULX   $src1,$src2,$dst\t! long" %}
7465   opcode(Assembler::mulx_op3, Assembler::arith_op);
7466   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7467   ins_pipe(mulL_reg_reg);
7468 %}
7469 
7470 // Immediate Multiplication
7471 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7472   effect(DEF dst, USE src1, USE src2);
7473   size(4);
7474   format %{ "MULX   $src1,$src2,$dst" %}
7475   opcode(Assembler::mulx_op3, Assembler::arith_op);
7476   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7477   ins_pipe(mulL_reg_imm);
7478 %}
7479 
7480 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7481   effect(DEF dst, USE src1, USE src2);
7482   size(4);
7483   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7484   opcode(Assembler::sub_op3, Assembler::arith_op);
7485   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7486   ins_pipe(ialu_reg_reg);
7487 %}
7488 
7489 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7490   effect(DEF dst, USE src1, USE src2);
7491   size(4);
7492   format %{ "SUB    $src1,$src2,$dst\t! long" %}
7493   opcode(Assembler::sub_op3, Assembler::arith_op);
7494   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7495   ins_pipe(ialu_reg_reg);
7496 %}
7497 
7498 // Register Long Remainder
7499 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7500   match(Set dst (ModL src1 src2));
7501   ins_cost(DEFAULT_COST*(71 + 6 + 1));
7502   expand %{
7503     iRegL tmp1;
7504     iRegL tmp2;
7505     divL_reg_reg_1(tmp1, src1, src2);
7506     mulL_reg_reg_1(tmp2, tmp1, src2);
7507     subL_reg_reg_1(dst,  src1, tmp2);
7508   %}
7509 %}
7510 
7511 // Register Long Remainder
7512 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7513   match(Set dst (ModL src1 src2));
7514   ins_cost(DEFAULT_COST*(71 + 6 + 1));
7515   expand %{
7516     iRegL tmp1;
7517     iRegL tmp2;
7518     divL_reg_imm13_1(tmp1, src1, src2);
7519     mulL_reg_imm13_1(tmp2, tmp1, src2);
7520     subL_reg_reg_2  (dst,  src1, tmp2);
7521   %}
7522 %}
7523 
7524 // Integer Shift Instructions
7525 // Register Shift Left
7526 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7527   match(Set dst (LShiftI src1 src2));
7528 
7529   size(4);
7530   format %{ "SLL    $src1,$src2,$dst" %}
7531   opcode(Assembler::sll_op3, Assembler::arith_op);
7532   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7533   ins_pipe(ialu_reg_reg);
7534 %}
7535 
7536 // Register Shift Left Immediate
7537 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7538   match(Set dst (LShiftI src1 src2));
7539 
7540   size(4);
7541   format %{ "SLL    $src1,$src2,$dst" %}
7542   opcode(Assembler::sll_op3, Assembler::arith_op);
7543   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7544   ins_pipe(ialu_reg_imm);
7545 %}
7546 
7547 // Register Shift Left
7548 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7549   match(Set dst (LShiftL src1 src2));
7550 
7551   size(4);
7552   format %{ "SLLX   $src1,$src2,$dst" %}
7553   opcode(Assembler::sllx_op3, Assembler::arith_op);
7554   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7555   ins_pipe(ialu_reg_reg);
7556 %}
7557 
7558 // Register Shift Left Immediate
7559 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7560   match(Set dst (LShiftL src1 src2));
7561 
7562   size(4);
7563   format %{ "SLLX   $src1,$src2,$dst" %}
7564   opcode(Assembler::sllx_op3, Assembler::arith_op);
7565   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7566   ins_pipe(ialu_reg_imm);
7567 %}
7568 
7569 // Register Arithmetic Shift Right
7570 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7571   match(Set dst (RShiftI src1 src2));
7572   size(4);
7573   format %{ "SRA    $src1,$src2,$dst" %}
7574   opcode(Assembler::sra_op3, Assembler::arith_op);
7575   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7576   ins_pipe(ialu_reg_reg);
7577 %}
7578 
7579 // Register Arithmetic Shift Right Immediate
7580 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7581   match(Set dst (RShiftI src1 src2));
7582 
7583   size(4);
7584   format %{ "SRA    $src1,$src2,$dst" %}
7585   opcode(Assembler::sra_op3, Assembler::arith_op);
7586   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7587   ins_pipe(ialu_reg_imm);
7588 %}
7589 
7590 // Register Shift Right Arithmatic Long
7591 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7592   match(Set dst (RShiftL src1 src2));
7593 
7594   size(4);
7595   format %{ "SRAX   $src1,$src2,$dst" %}
7596   opcode(Assembler::srax_op3, Assembler::arith_op);
7597   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7598   ins_pipe(ialu_reg_reg);
7599 %}
7600 
7601 // Register Shift Left Immediate
7602 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7603   match(Set dst (RShiftL src1 src2));
7604 
7605   size(4);
7606   format %{ "SRAX   $src1,$src2,$dst" %}
7607   opcode(Assembler::srax_op3, Assembler::arith_op);
7608   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7609   ins_pipe(ialu_reg_imm);
7610 %}
7611 
7612 // Register Shift Right
7613 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7614   match(Set dst (URShiftI src1 src2));
7615 
7616   size(4);
7617   format %{ "SRL    $src1,$src2,$dst" %}
7618   opcode(Assembler::srl_op3, Assembler::arith_op);
7619   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7620   ins_pipe(ialu_reg_reg);
7621 %}
7622 
7623 // Register Shift Right Immediate
7624 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7625   match(Set dst (URShiftI src1 src2));
7626 
7627   size(4);
7628   format %{ "SRL    $src1,$src2,$dst" %}
7629   opcode(Assembler::srl_op3, Assembler::arith_op);
7630   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7631   ins_pipe(ialu_reg_imm);
7632 %}
7633 
7634 // Register Shift Right
7635 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7636   match(Set dst (URShiftL src1 src2));
7637 
7638   size(4);
7639   format %{ "SRLX   $src1,$src2,$dst" %}
7640   opcode(Assembler::srlx_op3, Assembler::arith_op);
7641   ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7642   ins_pipe(ialu_reg_reg);
7643 %}
7644 
7645 // Register Shift Right Immediate
7646 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7647   match(Set dst (URShiftL src1 src2));
7648 
7649   size(4);
7650   format %{ "SRLX   $src1,$src2,$dst" %}
7651   opcode(Assembler::srlx_op3, Assembler::arith_op);
7652   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7653   ins_pipe(ialu_reg_imm);
7654 %}
7655 
7656 // Register Shift Right Immediate with a CastP2X
7657 #ifdef _LP64
7658 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7659   match(Set dst (URShiftL (CastP2X src1) src2));
7660   size(4);
7661   format %{ "SRLX   $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7662   opcode(Assembler::srlx_op3, Assembler::arith_op);
7663   ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7664   ins_pipe(ialu_reg_imm);
7665 %}
7666 #else
7667 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7668   match(Set dst (URShiftI (CastP2X src1) src2));
7669   size(4);
7670   format %{ "SRL    $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7671   opcode(Assembler::srl_op3, Assembler::arith_op);
7672   ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7673   ins_pipe(ialu_reg_imm);
7674 %}
7675 #endif
7676 
7677 
7678 //----------Floating Point Arithmetic Instructions-----------------------------
7679 
7680 //  Add float single precision
7681 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7682   match(Set dst (AddF src1 src2));
7683 
7684   size(4);
7685   format %{ "FADDS  $src1,$src2,$dst" %}
7686   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7687   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7688   ins_pipe(faddF_reg_reg);
7689 %}
7690 
7691 //  Add float double precision
7692 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7693   match(Set dst (AddD src1 src2));
7694 
7695   size(4);
7696   format %{ "FADDD  $src1,$src2,$dst" %}
7697   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7698   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7699   ins_pipe(faddD_reg_reg);
7700 %}
7701 
7702 //  Sub float single precision
7703 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7704   match(Set dst (SubF src1 src2));
7705 
7706   size(4);
7707   format %{ "FSUBS  $src1,$src2,$dst" %}
7708   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7709   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7710   ins_pipe(faddF_reg_reg);
7711 %}
7712 
7713 //  Sub float double precision
7714 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7715   match(Set dst (SubD src1 src2));
7716 
7717   size(4);
7718   format %{ "FSUBD  $src1,$src2,$dst" %}
7719   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7720   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7721   ins_pipe(faddD_reg_reg);
7722 %}
7723 
7724 //  Mul float single precision
7725 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7726   match(Set dst (MulF src1 src2));
7727 
7728   size(4);
7729   format %{ "FMULS  $src1,$src2,$dst" %}
7730   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7731   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7732   ins_pipe(fmulF_reg_reg);
7733 %}
7734 
7735 //  Mul float double precision
7736 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7737   match(Set dst (MulD src1 src2));
7738 
7739   size(4);
7740   format %{ "FMULD  $src1,$src2,$dst" %}
7741   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7742   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7743   ins_pipe(fmulD_reg_reg);
7744 %}
7745 
7746 //  Div float single precision
7747 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7748   match(Set dst (DivF src1 src2));
7749 
7750   size(4);
7751   format %{ "FDIVS  $src1,$src2,$dst" %}
7752   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7753   ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7754   ins_pipe(fdivF_reg_reg);
7755 %}
7756 
7757 //  Div float double precision
7758 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7759   match(Set dst (DivD src1 src2));
7760 
7761   size(4);
7762   format %{ "FDIVD  $src1,$src2,$dst" %}
7763   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7764   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7765   ins_pipe(fdivD_reg_reg);
7766 %}
7767 
7768 //  Absolute float double precision
7769 instruct absD_reg(regD dst, regD src) %{
7770   match(Set dst (AbsD src));
7771 
7772   format %{ "FABSd  $src,$dst" %}
7773   ins_encode(fabsd(dst, src));
7774   ins_pipe(faddD_reg);
7775 %}
7776 
7777 //  Absolute float single precision
7778 instruct absF_reg(regF dst, regF src) %{
7779   match(Set dst (AbsF src));
7780 
7781   format %{ "FABSs  $src,$dst" %}
7782   ins_encode(fabss(dst, src));
7783   ins_pipe(faddF_reg);
7784 %}
7785 
7786 instruct negF_reg(regF dst, regF src) %{
7787   match(Set dst (NegF src));
7788 
7789   size(4);
7790   format %{ "FNEGs  $src,$dst" %}
7791   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
7792   ins_encode(form3_opf_rs2F_rdF(src, dst));
7793   ins_pipe(faddF_reg);
7794 %}
7795 
7796 instruct negD_reg(regD dst, regD src) %{
7797   match(Set dst (NegD src));
7798 
7799   format %{ "FNEGd  $src,$dst" %}
7800   ins_encode(fnegd(dst, src));
7801   ins_pipe(faddD_reg);
7802 %}
7803 
7804 //  Sqrt float double precision
7805 instruct sqrtF_reg_reg(regF dst, regF src) %{
7806   match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
7807 
7808   size(4);
7809   format %{ "FSQRTS $src,$dst" %}
7810   ins_encode(fsqrts(dst, src));
7811   ins_pipe(fdivF_reg_reg);
7812 %}
7813 
7814 //  Sqrt float double precision
7815 instruct sqrtD_reg_reg(regD dst, regD src) %{
7816   match(Set dst (SqrtD src));
7817 
7818   size(4);
7819   format %{ "FSQRTD $src,$dst" %}
7820   ins_encode(fsqrtd(dst, src));
7821   ins_pipe(fdivD_reg_reg);
7822 %}
7823 
7824 //----------Logical Instructions-----------------------------------------------
7825 // And Instructions
7826 // Register And
7827 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7828   match(Set dst (AndI src1 src2));
7829 
7830   size(4);
7831   format %{ "AND    $src1,$src2,$dst" %}
7832   opcode(Assembler::and_op3, Assembler::arith_op);
7833   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7834   ins_pipe(ialu_reg_reg);
7835 %}
7836 
7837 // Immediate And
7838 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7839   match(Set dst (AndI src1 src2));
7840 
7841   size(4);
7842   format %{ "AND    $src1,$src2,$dst" %}
7843   opcode(Assembler::and_op3, Assembler::arith_op);
7844   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7845   ins_pipe(ialu_reg_imm);
7846 %}
7847 
7848 // Register And Long
7849 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7850   match(Set dst (AndL src1 src2));
7851 
7852   ins_cost(DEFAULT_COST);
7853   size(4);
7854   format %{ "AND    $src1,$src2,$dst\t! long" %}
7855   opcode(Assembler::and_op3, Assembler::arith_op);
7856   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7857   ins_pipe(ialu_reg_reg);
7858 %}
7859 
7860 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7861   match(Set dst (AndL src1 con));
7862 
7863   ins_cost(DEFAULT_COST);
7864   size(4);
7865   format %{ "AND    $src1,$con,$dst\t! long" %}
7866   opcode(Assembler::and_op3, Assembler::arith_op);
7867   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7868   ins_pipe(ialu_reg_imm);
7869 %}
7870 
7871 // Or Instructions
7872 // Register Or
7873 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7874   match(Set dst (OrI src1 src2));
7875 
7876   size(4);
7877   format %{ "OR     $src1,$src2,$dst" %}
7878   opcode(Assembler::or_op3, Assembler::arith_op);
7879   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7880   ins_pipe(ialu_reg_reg);
7881 %}
7882 
7883 // Immediate Or
7884 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7885   match(Set dst (OrI src1 src2));
7886 
7887   size(4);
7888   format %{ "OR     $src1,$src2,$dst" %}
7889   opcode(Assembler::or_op3, Assembler::arith_op);
7890   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7891   ins_pipe(ialu_reg_imm);
7892 %}
7893 
7894 // Register Or Long
7895 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7896   match(Set dst (OrL src1 src2));
7897 
7898   ins_cost(DEFAULT_COST);
7899   size(4);
7900   format %{ "OR     $src1,$src2,$dst\t! long" %}
7901   opcode(Assembler::or_op3, Assembler::arith_op);
7902   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7903   ins_pipe(ialu_reg_reg);
7904 %}
7905 
7906 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7907   match(Set dst (OrL src1 con));
7908   ins_cost(DEFAULT_COST*2);
7909 
7910   ins_cost(DEFAULT_COST);
7911   size(4);
7912   format %{ "OR     $src1,$con,$dst\t! long" %}
7913   opcode(Assembler::or_op3, Assembler::arith_op);
7914   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7915   ins_pipe(ialu_reg_imm);
7916 %}
7917 
7918 #ifndef _LP64
7919 
7920 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
7921 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
7922   match(Set dst (OrI src1 (CastP2X src2)));
7923 
7924   size(4);
7925   format %{ "OR     $src1,$src2,$dst" %}
7926   opcode(Assembler::or_op3, Assembler::arith_op);
7927   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7928   ins_pipe(ialu_reg_reg);
7929 %}
7930 
7931 #else
7932 
7933 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
7934   match(Set dst (OrL src1 (CastP2X src2)));
7935 
7936   ins_cost(DEFAULT_COST);
7937   size(4);
7938   format %{ "OR     $src1,$src2,$dst\t! long" %}
7939   opcode(Assembler::or_op3, Assembler::arith_op);
7940   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7941   ins_pipe(ialu_reg_reg);
7942 %}
7943 
7944 #endif
7945 
7946 // Xor Instructions
7947 // Register Xor
7948 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7949   match(Set dst (XorI src1 src2));
7950 
7951   size(4);
7952   format %{ "XOR    $src1,$src2,$dst" %}
7953   opcode(Assembler::xor_op3, Assembler::arith_op);
7954   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7955   ins_pipe(ialu_reg_reg);
7956 %}
7957 
7958 // Immediate Xor
7959 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7960   match(Set dst (XorI src1 src2));
7961 
7962   size(4);
7963   format %{ "XOR    $src1,$src2,$dst" %}
7964   opcode(Assembler::xor_op3, Assembler::arith_op);
7965   ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7966   ins_pipe(ialu_reg_imm);
7967 %}
7968 
7969 // Register Xor Long
7970 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7971   match(Set dst (XorL src1 src2));
7972 
7973   ins_cost(DEFAULT_COST);
7974   size(4);
7975   format %{ "XOR    $src1,$src2,$dst\t! long" %}
7976   opcode(Assembler::xor_op3, Assembler::arith_op);
7977   ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7978   ins_pipe(ialu_reg_reg);
7979 %}
7980 
7981 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7982   match(Set dst (XorL src1 con));
7983 
7984   ins_cost(DEFAULT_COST);
7985   size(4);
7986   format %{ "XOR    $src1,$con,$dst\t! long" %}
7987   opcode(Assembler::xor_op3, Assembler::arith_op);
7988   ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7989   ins_pipe(ialu_reg_imm);
7990 %}
7991 
7992 //----------Convert to Boolean-------------------------------------------------
7993 // Nice hack for 32-bit tests but doesn't work for
7994 // 64-bit pointers.
7995 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
7996   match(Set dst (Conv2B src));
7997   effect( KILL ccr );
7998   ins_cost(DEFAULT_COST*2);
7999   format %{ "CMP    R_G0,$src\n\t"
8000             "ADDX   R_G0,0,$dst" %}
8001   ins_encode( enc_to_bool( src, dst ) );
8002   ins_pipe(ialu_reg_ialu);
8003 %}
8004 
8005 #ifndef _LP64
8006 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8007   match(Set dst (Conv2B src));
8008   effect( KILL ccr );
8009   ins_cost(DEFAULT_COST*2);
8010   format %{ "CMP    R_G0,$src\n\t"
8011             "ADDX   R_G0,0,$dst" %}
8012   ins_encode( enc_to_bool( src, dst ) );
8013   ins_pipe(ialu_reg_ialu);
8014 %}
8015 #else
8016 instruct convP2B( iRegI dst, iRegP src ) %{
8017   match(Set dst (Conv2B src));
8018   ins_cost(DEFAULT_COST*2);
8019   format %{ "MOV    $src,$dst\n\t"
8020             "MOVRNZ $src,1,$dst" %}
8021   ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8022   ins_pipe(ialu_clr_and_mover);
8023 %}
8024 #endif
8025 
8026 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8027   match(Set dst (CmpLTMask src zero));
8028   effect(KILL ccr);
8029   size(4);
8030   format %{ "SRA    $src,#31,$dst\t# cmpLTMask0" %}
8031   ins_encode %{
8032     __ sra($src$$Register, 31, $dst$$Register);
8033   %}
8034   ins_pipe(ialu_reg_imm);
8035 %}
8036 
8037 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8038   match(Set dst (CmpLTMask p q));
8039   effect( KILL ccr );
8040   ins_cost(DEFAULT_COST*4);
8041   format %{ "CMP    $p,$q\n\t"
8042             "MOV    #0,$dst\n\t"
8043             "BLT,a  .+8\n\t"
8044             "MOV    #-1,$dst" %}
8045   ins_encode( enc_ltmask(p,q,dst) );
8046   ins_pipe(ialu_reg_reg_ialu);
8047 %}
8048 
8049 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8050   match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8051   effect(KILL ccr, TEMP tmp);
8052   ins_cost(DEFAULT_COST*3);
8053 
8054   format %{ "SUBcc  $p,$q,$p\t! p' = p-q\n\t"
8055             "ADD    $p,$y,$tmp\t! g3=p-q+y\n\t"
8056             "MOVlt  $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8057   ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8058   ins_pipe(cadd_cmpltmask);
8059 %}
8060 
8061 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8062   match(Set p (AndI (CmpLTMask p q) y));
8063   effect(KILL ccr);
8064   ins_cost(DEFAULT_COST*3);
8065 
8066   format %{ "CMP  $p,$q\n\t"
8067             "MOV  $y,$p\n\t"
8068             "MOVge G0,$p" %}
8069   ins_encode %{
8070     __ cmp($p$$Register, $q$$Register);
8071     __ mov($y$$Register, $p$$Register);
8072     __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8073   %}
8074   ins_pipe(ialu_reg_reg_ialu);
8075 %}
8076 
8077 //-----------------------------------------------------------------
8078 // Direct raw moves between float and general registers using VIS3.
8079 
8080 //  ins_pipe(faddF_reg);
8081 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8082   predicate(UseVIS >= 3);
8083   match(Set dst (MoveF2I src));
8084 
8085   format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8086   ins_encode %{
8087     __ movstouw($src$$FloatRegister, $dst$$Register);
8088   %}
8089   ins_pipe(ialu_reg_reg);
8090 %}
8091 
8092 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8093   predicate(UseVIS >= 3);
8094   match(Set dst (MoveI2F src));
8095 
8096   format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8097   ins_encode %{
8098     __ movwtos($src$$Register, $dst$$FloatRegister);
8099   %}
8100   ins_pipe(ialu_reg_reg);
8101 %}
8102 
8103 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8104   predicate(UseVIS >= 3);
8105   match(Set dst (MoveD2L src));
8106 
8107   format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8108   ins_encode %{
8109     __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8110   %}
8111   ins_pipe(ialu_reg_reg);
8112 %}
8113 
8114 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8115   predicate(UseVIS >= 3);
8116   match(Set dst (MoveL2D src));
8117 
8118   format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8119   ins_encode %{
8120     __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8121   %}
8122   ins_pipe(ialu_reg_reg);
8123 %}
8124 
8125 
8126 // Raw moves between float and general registers using stack.
8127 
8128 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8129   match(Set dst (MoveF2I src));
8130   effect(DEF dst, USE src);
8131   ins_cost(MEMORY_REF_COST);
8132 
8133   format %{ "LDUW   $src,$dst\t! MoveF2I" %}
8134   opcode(Assembler::lduw_op3);
8135   ins_encode(simple_form3_mem_reg( src, dst ) );
8136   ins_pipe(iload_mem);
8137 %}
8138 
8139 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8140   match(Set dst (MoveI2F src));
8141   effect(DEF dst, USE src);
8142   ins_cost(MEMORY_REF_COST);
8143 
8144   format %{ "LDF    $src,$dst\t! MoveI2F" %}
8145   opcode(Assembler::ldf_op3);
8146   ins_encode(simple_form3_mem_reg(src, dst));
8147   ins_pipe(floadF_stk);
8148 %}
8149 
8150 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8151   match(Set dst (MoveD2L src));
8152   effect(DEF dst, USE src);
8153   ins_cost(MEMORY_REF_COST);
8154 
8155   format %{ "LDX    $src,$dst\t! MoveD2L" %}
8156   opcode(Assembler::ldx_op3);
8157   ins_encode(simple_form3_mem_reg( src, dst ) );
8158   ins_pipe(iload_mem);
8159 %}
8160 
8161 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8162   match(Set dst (MoveL2D src));
8163   effect(DEF dst, USE src);
8164   ins_cost(MEMORY_REF_COST);
8165 
8166   format %{ "LDDF   $src,$dst\t! MoveL2D" %}
8167   opcode(Assembler::lddf_op3);
8168   ins_encode(simple_form3_mem_reg(src, dst));
8169   ins_pipe(floadD_stk);
8170 %}
8171 
8172 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8173   match(Set dst (MoveF2I src));
8174   effect(DEF dst, USE src);
8175   ins_cost(MEMORY_REF_COST);
8176 
8177   format %{ "STF   $src,$dst\t! MoveF2I" %}
8178   opcode(Assembler::stf_op3);
8179   ins_encode(simple_form3_mem_reg(dst, src));
8180   ins_pipe(fstoreF_stk_reg);
8181 %}
8182 
8183 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8184   match(Set dst (MoveI2F src));
8185   effect(DEF dst, USE src);
8186   ins_cost(MEMORY_REF_COST);
8187 
8188   format %{ "STW    $src,$dst\t! MoveI2F" %}
8189   opcode(Assembler::stw_op3);
8190   ins_encode(simple_form3_mem_reg( dst, src ) );
8191   ins_pipe(istore_mem_reg);
8192 %}
8193 
8194 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8195   match(Set dst (MoveD2L src));
8196   effect(DEF dst, USE src);
8197   ins_cost(MEMORY_REF_COST);
8198 
8199   format %{ "STDF   $src,$dst\t! MoveD2L" %}
8200   opcode(Assembler::stdf_op3);
8201   ins_encode(simple_form3_mem_reg(dst, src));
8202   ins_pipe(fstoreD_stk_reg);
8203 %}
8204 
8205 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8206   match(Set dst (MoveL2D src));
8207   effect(DEF dst, USE src);
8208   ins_cost(MEMORY_REF_COST);
8209 
8210   format %{ "STX    $src,$dst\t! MoveL2D" %}
8211   opcode(Assembler::stx_op3);
8212   ins_encode(simple_form3_mem_reg( dst, src ) );
8213   ins_pipe(istore_mem_reg);
8214 %}
8215 
8216 
8217 //----------Arithmetic Conversion Instructions---------------------------------
8218 // The conversions operations are all Alpha sorted.  Please keep it that way!
8219 
8220 instruct convD2F_reg(regF dst, regD src) %{
8221   match(Set dst (ConvD2F src));
8222   size(4);
8223   format %{ "FDTOS  $src,$dst" %}
8224   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8225   ins_encode(form3_opf_rs2D_rdF(src, dst));
8226   ins_pipe(fcvtD2F);
8227 %}
8228 
8229 
8230 // Convert a double to an int in a float register.
8231 // If the double is a NAN, stuff a zero in instead.
8232 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8233   effect(DEF dst, USE src, KILL fcc0);
8234   format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
8235             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8236             "FDTOI  $src,$dst\t! convert in delay slot\n\t"
8237             "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
8238             "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
8239       "skip:" %}
8240   ins_encode(form_d2i_helper(src,dst));
8241   ins_pipe(fcvtD2I);
8242 %}
8243 
8244 instruct convD2I_stk(stackSlotI dst, regD src) %{
8245   match(Set dst (ConvD2I src));
8246   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8247   expand %{
8248     regF tmp;
8249     convD2I_helper(tmp, src);
8250     regF_to_stkI(dst, tmp);
8251   %}
8252 %}
8253 
8254 instruct convD2I_reg(iRegI dst, regD src) %{
8255   predicate(UseVIS >= 3);
8256   match(Set dst (ConvD2I src));
8257   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8258   expand %{
8259     regF tmp;
8260     convD2I_helper(tmp, src);
8261     MoveF2I_reg_reg(dst, tmp);
8262   %}
8263 %}
8264 
8265 
8266 // Convert a double to a long in a double register.
8267 // If the double is a NAN, stuff a zero in instead.
8268 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8269   effect(DEF dst, USE src, KILL fcc0);
8270   format %{ "FCMPd  fcc0,$src,$src\t! check for NAN\n\t"
8271             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8272             "FDTOX  $src,$dst\t! convert in delay slot\n\t"
8273             "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
8274             "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
8275       "skip:" %}
8276   ins_encode(form_d2l_helper(src,dst));
8277   ins_pipe(fcvtD2L);
8278 %}
8279 
8280 instruct convD2L_stk(stackSlotL dst, regD src) %{
8281   match(Set dst (ConvD2L src));
8282   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8283   expand %{
8284     regD tmp;
8285     convD2L_helper(tmp, src);
8286     regD_to_stkL(dst, tmp);
8287   %}
8288 %}
8289 
8290 instruct convD2L_reg(iRegL dst, regD src) %{
8291   predicate(UseVIS >= 3);
8292   match(Set dst (ConvD2L src));
8293   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8294   expand %{
8295     regD tmp;
8296     convD2L_helper(tmp, src);
8297     MoveD2L_reg_reg(dst, tmp);
8298   %}
8299 %}
8300 
8301 
8302 instruct convF2D_reg(regD dst, regF src) %{
8303   match(Set dst (ConvF2D src));
8304   format %{ "FSTOD  $src,$dst" %}
8305   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8306   ins_encode(form3_opf_rs2F_rdD(src, dst));
8307   ins_pipe(fcvtF2D);
8308 %}
8309 
8310 
8311 // Convert a float to an int in a float register.
8312 // If the float is a NAN, stuff a zero in instead.
8313 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8314   effect(DEF dst, USE src, KILL fcc0);
8315   format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
8316             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8317             "FSTOI  $src,$dst\t! convert in delay slot\n\t"
8318             "FITOS  $dst,$dst\t! change NaN/max-int to valid float\n\t"
8319             "FSUBs  $dst,$dst,$dst\t! cleared only if nan\n"
8320       "skip:" %}
8321   ins_encode(form_f2i_helper(src,dst));
8322   ins_pipe(fcvtF2I);
8323 %}
8324 
8325 instruct convF2I_stk(stackSlotI dst, regF src) %{
8326   match(Set dst (ConvF2I src));
8327   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8328   expand %{
8329     regF tmp;
8330     convF2I_helper(tmp, src);
8331     regF_to_stkI(dst, tmp);
8332   %}
8333 %}
8334 
8335 instruct convF2I_reg(iRegI dst, regF src) %{
8336   predicate(UseVIS >= 3);
8337   match(Set dst (ConvF2I src));
8338   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8339   expand %{
8340     regF tmp;
8341     convF2I_helper(tmp, src);
8342     MoveF2I_reg_reg(dst, tmp);
8343   %}
8344 %}
8345 
8346 
8347 // Convert a float to a long in a float register.
8348 // If the float is a NAN, stuff a zero in instead.
8349 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8350   effect(DEF dst, USE src, KILL fcc0);
8351   format %{ "FCMPs  fcc0,$src,$src\t! check for NAN\n\t"
8352             "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8353             "FSTOX  $src,$dst\t! convert in delay slot\n\t"
8354             "FXTOD  $dst,$dst\t! change NaN/max-long to valid double\n\t"
8355             "FSUBd  $dst,$dst,$dst\t! cleared only if nan\n"
8356       "skip:" %}
8357   ins_encode(form_f2l_helper(src,dst));
8358   ins_pipe(fcvtF2L);
8359 %}
8360 
8361 instruct convF2L_stk(stackSlotL dst, regF src) %{
8362   match(Set dst (ConvF2L src));
8363   ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8364   expand %{
8365     regD tmp;
8366     convF2L_helper(tmp, src);
8367     regD_to_stkL(dst, tmp);
8368   %}
8369 %}
8370 
8371 instruct convF2L_reg(iRegL dst, regF src) %{
8372   predicate(UseVIS >= 3);
8373   match(Set dst (ConvF2L src));
8374   ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8375   expand %{
8376     regD tmp;
8377     convF2L_helper(tmp, src);
8378     MoveD2L_reg_reg(dst, tmp);
8379   %}
8380 %}
8381 
8382 
8383 instruct convI2D_helper(regD dst, regF tmp) %{
8384   effect(USE tmp, DEF dst);
8385   format %{ "FITOD  $tmp,$dst" %}
8386   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8387   ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8388   ins_pipe(fcvtI2D);
8389 %}
8390 
8391 instruct convI2D_stk(stackSlotI src, regD dst) %{
8392   match(Set dst (ConvI2D src));
8393   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8394   expand %{
8395     regF tmp;
8396     stkI_to_regF(tmp, src);
8397     convI2D_helper(dst, tmp);
8398   %}
8399 %}
8400 
8401 instruct convI2D_reg(regD_low dst, iRegI src) %{
8402   predicate(UseVIS >= 3);
8403   match(Set dst (ConvI2D src));
8404   expand %{
8405     regF tmp;
8406     MoveI2F_reg_reg(tmp, src);
8407     convI2D_helper(dst, tmp);
8408   %}
8409 %}
8410 
8411 instruct convI2D_mem(regD_low dst, memory mem) %{
8412   match(Set dst (ConvI2D (LoadI mem)));
8413   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8414   format %{ "LDF    $mem,$dst\n\t"
8415             "FITOD  $dst,$dst" %}
8416   opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8417   ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8418   ins_pipe(floadF_mem);
8419 %}
8420 
8421 
8422 instruct convI2F_helper(regF dst, regF tmp) %{
8423   effect(DEF dst, USE tmp);
8424   format %{ "FITOS  $tmp,$dst" %}
8425   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8426   ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8427   ins_pipe(fcvtI2F);
8428 %}
8429 
8430 instruct convI2F_stk(regF dst, stackSlotI src) %{
8431   match(Set dst (ConvI2F src));
8432   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8433   expand %{
8434     regF tmp;
8435     stkI_to_regF(tmp,src);
8436     convI2F_helper(dst, tmp);
8437   %}
8438 %}
8439 
8440 instruct convI2F_reg(regF dst, iRegI src) %{
8441   predicate(UseVIS >= 3);
8442   match(Set dst (ConvI2F src));
8443   ins_cost(DEFAULT_COST);
8444   expand %{
8445     regF tmp;
8446     MoveI2F_reg_reg(tmp, src);
8447     convI2F_helper(dst, tmp);
8448   %}
8449 %}
8450 
8451 instruct convI2F_mem( regF dst, memory mem ) %{
8452   match(Set dst (ConvI2F (LoadI mem)));
8453   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8454   format %{ "LDF    $mem,$dst\n\t"
8455             "FITOS  $dst,$dst" %}
8456   opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8457   ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8458   ins_pipe(floadF_mem);
8459 %}
8460 
8461 
8462 instruct convI2L_reg(iRegL dst, iRegI src) %{
8463   match(Set dst (ConvI2L src));
8464   size(4);
8465   format %{ "SRA    $src,0,$dst\t! int->long" %}
8466   opcode(Assembler::sra_op3, Assembler::arith_op);
8467   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8468   ins_pipe(ialu_reg_reg);
8469 %}
8470 
8471 // Zero-extend convert int to long
8472 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8473   match(Set dst (AndL (ConvI2L src) mask) );
8474   size(4);
8475   format %{ "SRL    $src,0,$dst\t! zero-extend int to long" %}
8476   opcode(Assembler::srl_op3, Assembler::arith_op);
8477   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8478   ins_pipe(ialu_reg_reg);
8479 %}
8480 
8481 // Zero-extend long
8482 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8483   match(Set dst (AndL src mask) );
8484   size(4);
8485   format %{ "SRL    $src,0,$dst\t! zero-extend long" %}
8486   opcode(Assembler::srl_op3, Assembler::arith_op);
8487   ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8488   ins_pipe(ialu_reg_reg);
8489 %}
8490 
8491 
8492 //-----------
8493 // Long to Double conversion using V8 opcodes.
8494 // Still useful because cheetah traps and becomes
8495 // amazingly slow for some common numbers.
8496 
8497 // Magic constant, 0x43300000
8498 instruct loadConI_x43300000(iRegI dst) %{
8499   effect(DEF dst);
8500   size(4);
8501   format %{ "SETHI  HI(0x43300000),$dst\t! 2^52" %}
8502   ins_encode(SetHi22(0x43300000, dst));
8503   ins_pipe(ialu_none);
8504 %}
8505 
8506 // Magic constant, 0x41f00000
8507 instruct loadConI_x41f00000(iRegI dst) %{
8508   effect(DEF dst);
8509   size(4);
8510   format %{ "SETHI  HI(0x41f00000),$dst\t! 2^32" %}
8511   ins_encode(SetHi22(0x41f00000, dst));
8512   ins_pipe(ialu_none);
8513 %}
8514 
8515 // Construct a double from two float halves
8516 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8517   effect(DEF dst, USE src1, USE src2);
8518   size(8);
8519   format %{ "FMOVS  $src1.hi,$dst.hi\n\t"
8520             "FMOVS  $src2.lo,$dst.lo" %}
8521   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8522   ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8523   ins_pipe(faddD_reg_reg);
8524 %}
8525 
8526 // Convert integer in high half of a double register (in the lower half of
8527 // the double register file) to double
8528 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8529   effect(DEF dst, USE src);
8530   size(4);
8531   format %{ "FITOD  $src,$dst" %}
8532   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8533   ins_encode(form3_opf_rs2D_rdD(src, dst));
8534   ins_pipe(fcvtLHi2D);
8535 %}
8536 
8537 // Add float double precision
8538 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8539   effect(DEF dst, USE src1, USE src2);
8540   size(4);
8541   format %{ "FADDD  $src1,$src2,$dst" %}
8542   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8543   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8544   ins_pipe(faddD_reg_reg);
8545 %}
8546 
8547 // Sub float double precision
8548 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8549   effect(DEF dst, USE src1, USE src2);
8550   size(4);
8551   format %{ "FSUBD  $src1,$src2,$dst" %}
8552   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8553   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8554   ins_pipe(faddD_reg_reg);
8555 %}
8556 
8557 // Mul float double precision
8558 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8559   effect(DEF dst, USE src1, USE src2);
8560   size(4);
8561   format %{ "FMULD  $src1,$src2,$dst" %}
8562   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8563   ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8564   ins_pipe(fmulD_reg_reg);
8565 %}
8566 
8567 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8568   match(Set dst (ConvL2D src));
8569   ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8570 
8571   expand %{
8572     regD_low   tmpsrc;
8573     iRegI      ix43300000;
8574     iRegI      ix41f00000;
8575     stackSlotL lx43300000;
8576     stackSlotL lx41f00000;
8577     regD_low   dx43300000;
8578     regD       dx41f00000;
8579     regD       tmp1;
8580     regD_low   tmp2;
8581     regD       tmp3;
8582     regD       tmp4;
8583 
8584     stkL_to_regD(tmpsrc, src);
8585 
8586     loadConI_x43300000(ix43300000);
8587     loadConI_x41f00000(ix41f00000);
8588     regI_to_stkLHi(lx43300000, ix43300000);
8589     regI_to_stkLHi(lx41f00000, ix41f00000);
8590     stkL_to_regD(dx43300000, lx43300000);
8591     stkL_to_regD(dx41f00000, lx41f00000);
8592 
8593     convI2D_regDHi_regD(tmp1, tmpsrc);
8594     regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8595     subD_regD_regD(tmp3, tmp2, dx43300000);
8596     mulD_regD_regD(tmp4, tmp1, dx41f00000);
8597     addD_regD_regD(dst, tmp3, tmp4);
8598   %}
8599 %}
8600 
8601 // Long to Double conversion using fast fxtof
8602 instruct convL2D_helper(regD dst, regD tmp) %{
8603   effect(DEF dst, USE tmp);
8604   size(4);
8605   format %{ "FXTOD  $tmp,$dst" %}
8606   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8607   ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8608   ins_pipe(fcvtL2D);
8609 %}
8610 
8611 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8612   predicate(VM_Version::has_fast_fxtof());
8613   match(Set dst (ConvL2D src));
8614   ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8615   expand %{
8616     regD tmp;
8617     stkL_to_regD(tmp, src);
8618     convL2D_helper(dst, tmp);
8619   %}
8620 %}
8621 
8622 instruct convL2D_reg(regD dst, iRegL src) %{
8623   predicate(UseVIS >= 3);
8624   match(Set dst (ConvL2D src));
8625   expand %{
8626     regD tmp;
8627     MoveL2D_reg_reg(tmp, src);
8628     convL2D_helper(dst, tmp);
8629   %}
8630 %}
8631 
8632 // Long to Float conversion using fast fxtof
8633 instruct convL2F_helper(regF dst, regD tmp) %{
8634   effect(DEF dst, USE tmp);
8635   size(4);
8636   format %{ "FXTOS  $tmp,$dst" %}
8637   opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8638   ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8639   ins_pipe(fcvtL2F);
8640 %}
8641 
8642 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8643   match(Set dst (ConvL2F src));
8644   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8645   expand %{
8646     regD tmp;
8647     stkL_to_regD(tmp, src);
8648     convL2F_helper(dst, tmp);
8649   %}
8650 %}
8651 
8652 instruct convL2F_reg(regF dst, iRegL src) %{
8653   predicate(UseVIS >= 3);
8654   match(Set dst (ConvL2F src));
8655   ins_cost(DEFAULT_COST);
8656   expand %{
8657     regD tmp;
8658     MoveL2D_reg_reg(tmp, src);
8659     convL2F_helper(dst, tmp);
8660   %}
8661 %}
8662 
8663 //-----------
8664 
8665 instruct convL2I_reg(iRegI dst, iRegL src) %{
8666   match(Set dst (ConvL2I src));
8667 #ifndef _LP64
8668   format %{ "MOV    $src.lo,$dst\t! long->int" %}
8669   ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8670   ins_pipe(ialu_move_reg_I_to_L);
8671 #else
8672   size(4);
8673   format %{ "SRA    $src,R_G0,$dst\t! long->int" %}
8674   ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8675   ins_pipe(ialu_reg);
8676 #endif
8677 %}
8678 
8679 // Register Shift Right Immediate
8680 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8681   match(Set dst (ConvL2I (RShiftL src cnt)));
8682 
8683   size(4);
8684   format %{ "SRAX   $src,$cnt,$dst" %}
8685   opcode(Assembler::srax_op3, Assembler::arith_op);
8686   ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8687   ins_pipe(ialu_reg_imm);
8688 %}
8689 
8690 //----------Control Flow Instructions------------------------------------------
8691 // Compare Instructions
8692 // Compare Integers
8693 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8694   match(Set icc (CmpI op1 op2));
8695   effect( DEF icc, USE op1, USE op2 );
8696 
8697   size(4);
8698   format %{ "CMP    $op1,$op2" %}
8699   opcode(Assembler::subcc_op3, Assembler::arith_op);
8700   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8701   ins_pipe(ialu_cconly_reg_reg);
8702 %}
8703 
8704 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8705   match(Set icc (CmpU op1 op2));
8706 
8707   size(4);
8708   format %{ "CMP    $op1,$op2\t! unsigned" %}
8709   opcode(Assembler::subcc_op3, Assembler::arith_op);
8710   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8711   ins_pipe(ialu_cconly_reg_reg);
8712 %}
8713 
8714 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8715   match(Set icc (CmpI op1 op2));
8716   effect( DEF icc, USE op1 );
8717 
8718   size(4);
8719   format %{ "CMP    $op1,$op2" %}
8720   opcode(Assembler::subcc_op3, Assembler::arith_op);
8721   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8722   ins_pipe(ialu_cconly_reg_imm);
8723 %}
8724 
8725 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8726   match(Set icc (CmpI (AndI op1 op2) zero));
8727 
8728   size(4);
8729   format %{ "BTST   $op2,$op1" %}
8730   opcode(Assembler::andcc_op3, Assembler::arith_op);
8731   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8732   ins_pipe(ialu_cconly_reg_reg_zero);
8733 %}
8734 
8735 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8736   match(Set icc (CmpI (AndI op1 op2) zero));
8737 
8738   size(4);
8739   format %{ "BTST   $op2,$op1" %}
8740   opcode(Assembler::andcc_op3, Assembler::arith_op);
8741   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8742   ins_pipe(ialu_cconly_reg_imm_zero);
8743 %}
8744 
8745 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8746   match(Set xcc (CmpL op1 op2));
8747   effect( DEF xcc, USE op1, USE op2 );
8748 
8749   size(4);
8750   format %{ "CMP    $op1,$op2\t\t! long" %}
8751   opcode(Assembler::subcc_op3, Assembler::arith_op);
8752   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8753   ins_pipe(ialu_cconly_reg_reg);
8754 %}
8755 
8756 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8757   match(Set xcc (CmpL op1 con));
8758   effect( DEF xcc, USE op1, USE con );
8759 
8760   size(4);
8761   format %{ "CMP    $op1,$con\t\t! long" %}
8762   opcode(Assembler::subcc_op3, Assembler::arith_op);
8763   ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8764   ins_pipe(ialu_cconly_reg_reg);
8765 %}
8766 
8767 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8768   match(Set xcc (CmpL (AndL op1 op2) zero));
8769   effect( DEF xcc, USE op1, USE op2 );
8770 
8771   size(4);
8772   format %{ "BTST   $op1,$op2\t\t! long" %}
8773   opcode(Assembler::andcc_op3, Assembler::arith_op);
8774   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8775   ins_pipe(ialu_cconly_reg_reg);
8776 %}
8777 
8778 // useful for checking the alignment of a pointer:
8779 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
8780   match(Set xcc (CmpL (AndL op1 con) zero));
8781   effect( DEF xcc, USE op1, USE con );
8782 
8783   size(4);
8784   format %{ "BTST   $op1,$con\t\t! long" %}
8785   opcode(Assembler::andcc_op3, Assembler::arith_op);
8786   ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8787   ins_pipe(ialu_cconly_reg_reg);
8788 %}
8789 
8790 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
8791   match(Set icc (CmpU op1 op2));
8792 
8793   size(4);
8794   format %{ "CMP    $op1,$op2\t! unsigned" %}
8795   opcode(Assembler::subcc_op3, Assembler::arith_op);
8796   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8797   ins_pipe(ialu_cconly_reg_imm);
8798 %}
8799 
8800 // Compare Pointers
8801 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
8802   match(Set pcc (CmpP op1 op2));
8803 
8804   size(4);
8805   format %{ "CMP    $op1,$op2\t! ptr" %}
8806   opcode(Assembler::subcc_op3, Assembler::arith_op);
8807   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8808   ins_pipe(ialu_cconly_reg_reg);
8809 %}
8810 
8811 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
8812   match(Set pcc (CmpP op1 op2));
8813 
8814   size(4);
8815   format %{ "CMP    $op1,$op2\t! ptr" %}
8816   opcode(Assembler::subcc_op3, Assembler::arith_op);
8817   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8818   ins_pipe(ialu_cconly_reg_imm);
8819 %}
8820 
8821 // Compare Narrow oops
8822 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
8823   match(Set icc (CmpN op1 op2));
8824 
8825   size(4);
8826   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
8827   opcode(Assembler::subcc_op3, Assembler::arith_op);
8828   ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8829   ins_pipe(ialu_cconly_reg_reg);
8830 %}
8831 
8832 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
8833   match(Set icc (CmpN op1 op2));
8834 
8835   size(4);
8836   format %{ "CMP    $op1,$op2\t! compressed ptr" %}
8837   opcode(Assembler::subcc_op3, Assembler::arith_op);
8838   ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8839   ins_pipe(ialu_cconly_reg_imm);
8840 %}
8841 
8842 //----------Max and Min--------------------------------------------------------
8843 // Min Instructions
8844 // Conditional move for min
8845 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
8846   effect( USE_DEF op2, USE op1, USE icc );
8847 
8848   size(4);
8849   format %{ "MOVlt  icc,$op1,$op2\t! min" %}
8850   opcode(Assembler::less);
8851   ins_encode( enc_cmov_reg_minmax(op2,op1) );
8852   ins_pipe(ialu_reg_flags);
8853 %}
8854 
8855 // Min Register with Register.
8856 instruct minI_eReg(iRegI op1, iRegI op2) %{
8857   match(Set op2 (MinI op1 op2));
8858   ins_cost(DEFAULT_COST*2);
8859   expand %{
8860     flagsReg icc;
8861     compI_iReg(icc,op1,op2);
8862     cmovI_reg_lt(op2,op1,icc);
8863   %}
8864 %}
8865 
8866 // Max Instructions
8867 // Conditional move for max
8868 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
8869   effect( USE_DEF op2, USE op1, USE icc );
8870   format %{ "MOVgt  icc,$op1,$op2\t! max" %}
8871   opcode(Assembler::greater);
8872   ins_encode( enc_cmov_reg_minmax(op2,op1) );
8873   ins_pipe(ialu_reg_flags);
8874 %}
8875 
8876 // Max Register with Register
8877 instruct maxI_eReg(iRegI op1, iRegI op2) %{
8878   match(Set op2 (MaxI op1 op2));
8879   ins_cost(DEFAULT_COST*2);
8880   expand %{
8881     flagsReg icc;
8882     compI_iReg(icc,op1,op2);
8883     cmovI_reg_gt(op2,op1,icc);
8884   %}
8885 %}
8886 
8887 
8888 //----------Float Compares----------------------------------------------------
8889 // Compare floating, generate condition code
8890 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
8891   match(Set fcc (CmpF src1 src2));
8892 
8893   size(4);
8894   format %{ "FCMPs  $fcc,$src1,$src2" %}
8895   opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
8896   ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
8897   ins_pipe(faddF_fcc_reg_reg_zero);
8898 %}
8899 
8900 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
8901   match(Set fcc (CmpD src1 src2));
8902 
8903   size(4);
8904   format %{ "FCMPd  $fcc,$src1,$src2" %}
8905   opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
8906   ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
8907   ins_pipe(faddD_fcc_reg_reg_zero);
8908 %}
8909 
8910 
8911 // Compare floating, generate -1,0,1
8912 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
8913   match(Set dst (CmpF3 src1 src2));
8914   effect(KILL fcc0);
8915   ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8916   format %{ "fcmpl  $dst,$src1,$src2" %}
8917   // Primary = float
8918   opcode( true );
8919   ins_encode( floating_cmp( dst, src1, src2 ) );
8920   ins_pipe( floating_cmp );
8921 %}
8922 
8923 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
8924   match(Set dst (CmpD3 src1 src2));
8925   effect(KILL fcc0);
8926   ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
8927   format %{ "dcmpl  $dst,$src1,$src2" %}
8928   // Primary = double (not float)
8929   opcode( false );
8930   ins_encode( floating_cmp( dst, src1, src2 ) );
8931   ins_pipe( floating_cmp );
8932 %}
8933 
8934 //----------Branches---------------------------------------------------------
8935 // Jump
8936 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
8937 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
8938   match(Jump switch_val);
8939   effect(TEMP table);
8940 
8941   ins_cost(350);
8942 
8943   format %{  "ADD    $constanttablebase, $constantoffset, O7\n\t"
8944              "LD     [O7 + $switch_val], O7\n\t"
8945              "JUMP   O7" %}
8946   ins_encode %{
8947     // Calculate table address into a register.
8948     Register table_reg;
8949     Register label_reg = O7;
8950     // If we are calculating the size of this instruction don't trust
8951     // zero offsets because they might change when
8952     // MachConstantBaseNode decides to optimize the constant table
8953     // base.
8954     if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
8955       table_reg = $constanttablebase;
8956     } else {
8957       table_reg = O7;
8958       RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
8959       __ add($constanttablebase, con_offset, table_reg);
8960     }
8961 
8962     // Jump to base address + switch value
8963     __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
8964     __ jmp(label_reg, G0);
8965     __ delayed()->nop();
8966   %}
8967   ins_pipe(ialu_reg_reg);
8968 %}
8969 
8970 // Direct Branch.  Use V8 version with longer range.
8971 instruct branch(label labl) %{
8972   match(Goto);
8973   effect(USE labl);
8974 
8975   size(8);
8976   ins_cost(BRANCH_COST);
8977   format %{ "BA     $labl" %}
8978   ins_encode %{
8979     Label* L = $labl$$label;
8980     __ ba(*L);
8981     __ delayed()->nop();
8982   %}
8983   ins_avoid_back_to_back(AVOID_BEFORE);
8984   ins_pipe(br);
8985 %}
8986 
8987 // Direct Branch, short with no delay slot
8988 instruct branch_short(label labl) %{
8989   match(Goto);
8990   predicate(UseCBCond);
8991   effect(USE labl);
8992 
8993   size(4);
8994   ins_cost(BRANCH_COST);
8995   format %{ "BA     $labl\t! short branch" %}
8996   ins_encode %{
8997     Label* L = $labl$$label;
8998     assert(__ use_cbcond(*L), "back to back cbcond");
8999     __ ba_short(*L);
9000   %}
9001   ins_short_branch(1);
9002   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9003   ins_pipe(cbcond_reg_imm);
9004 %}
9005 
9006 // Conditional Direct Branch
9007 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9008   match(If cmp icc);
9009   effect(USE labl);
9010 
9011   size(8);
9012   ins_cost(BRANCH_COST);
9013   format %{ "BP$cmp   $icc,$labl" %}
9014   // Prim = bits 24-22, Secnd = bits 31-30
9015   ins_encode( enc_bp( labl, cmp, icc ) );
9016   ins_avoid_back_to_back(AVOID_BEFORE);
9017   ins_pipe(br_cc);
9018 %}
9019 
9020 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9021   match(If cmp icc);
9022   effect(USE labl);
9023 
9024   ins_cost(BRANCH_COST);
9025   format %{ "BP$cmp  $icc,$labl" %}
9026   // Prim = bits 24-22, Secnd = bits 31-30
9027   ins_encode( enc_bp( labl, cmp, icc ) );
9028   ins_avoid_back_to_back(AVOID_BEFORE);
9029   ins_pipe(br_cc);
9030 %}
9031 
9032 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9033   match(If cmp pcc);
9034   effect(USE labl);
9035 
9036   size(8);
9037   ins_cost(BRANCH_COST);
9038   format %{ "BP$cmp  $pcc,$labl" %}
9039   ins_encode %{
9040     Label* L = $labl$$label;
9041     Assembler::Predict predict_taken =
9042       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9043 
9044     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9045     __ delayed()->nop();
9046   %}
9047   ins_avoid_back_to_back(AVOID_BEFORE);
9048   ins_pipe(br_cc);
9049 %}
9050 
9051 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9052   match(If cmp fcc);
9053   effect(USE labl);
9054 
9055   size(8);
9056   ins_cost(BRANCH_COST);
9057   format %{ "FBP$cmp $fcc,$labl" %}
9058   ins_encode %{
9059     Label* L = $labl$$label;
9060     Assembler::Predict predict_taken =
9061       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9062 
9063     __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9064     __ delayed()->nop();
9065   %}
9066   ins_avoid_back_to_back(AVOID_BEFORE);
9067   ins_pipe(br_fcc);
9068 %}
9069 
9070 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9071   match(CountedLoopEnd cmp icc);
9072   effect(USE labl);
9073 
9074   size(8);
9075   ins_cost(BRANCH_COST);
9076   format %{ "BP$cmp   $icc,$labl\t! Loop end" %}
9077   // Prim = bits 24-22, Secnd = bits 31-30
9078   ins_encode( enc_bp( labl, cmp, icc ) );
9079   ins_avoid_back_to_back(AVOID_BEFORE);
9080   ins_pipe(br_cc);
9081 %}
9082 
9083 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9084   match(CountedLoopEnd cmp icc);
9085   effect(USE labl);
9086 
9087   size(8);
9088   ins_cost(BRANCH_COST);
9089   format %{ "BP$cmp  $icc,$labl\t! Loop end" %}
9090   // Prim = bits 24-22, Secnd = bits 31-30
9091   ins_encode( enc_bp( labl, cmp, icc ) );
9092   ins_avoid_back_to_back(AVOID_BEFORE);
9093   ins_pipe(br_cc);
9094 %}
9095 
9096 // Compare and branch instructions
9097 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9098   match(If cmp (CmpI op1 op2));
9099   effect(USE labl, KILL icc);
9100 
9101   size(12);
9102   ins_cost(BRANCH_COST);
9103   format %{ "CMP    $op1,$op2\t! int\n\t"
9104             "BP$cmp   $labl" %}
9105   ins_encode %{
9106     Label* L = $labl$$label;
9107     Assembler::Predict predict_taken =
9108       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9109     __ cmp($op1$$Register, $op2$$Register);
9110     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9111     __ delayed()->nop();
9112   %}
9113   ins_pipe(cmp_br_reg_reg);
9114 %}
9115 
9116 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9117   match(If cmp (CmpI op1 op2));
9118   effect(USE labl, KILL icc);
9119 
9120   size(12);
9121   ins_cost(BRANCH_COST);
9122   format %{ "CMP    $op1,$op2\t! int\n\t"
9123             "BP$cmp   $labl" %}
9124   ins_encode %{
9125     Label* L = $labl$$label;
9126     Assembler::Predict predict_taken =
9127       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9128     __ cmp($op1$$Register, $op2$$constant);
9129     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9130     __ delayed()->nop();
9131   %}
9132   ins_pipe(cmp_br_reg_imm);
9133 %}
9134 
9135 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9136   match(If cmp (CmpU op1 op2));
9137   effect(USE labl, KILL icc);
9138 
9139   size(12);
9140   ins_cost(BRANCH_COST);
9141   format %{ "CMP    $op1,$op2\t! unsigned\n\t"
9142             "BP$cmp  $labl" %}
9143   ins_encode %{
9144     Label* L = $labl$$label;
9145     Assembler::Predict predict_taken =
9146       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9147     __ cmp($op1$$Register, $op2$$Register);
9148     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9149     __ delayed()->nop();
9150   %}
9151   ins_pipe(cmp_br_reg_reg);
9152 %}
9153 
9154 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9155   match(If cmp (CmpU op1 op2));
9156   effect(USE labl, KILL icc);
9157 
9158   size(12);
9159   ins_cost(BRANCH_COST);
9160   format %{ "CMP    $op1,$op2\t! unsigned\n\t"
9161             "BP$cmp  $labl" %}
9162   ins_encode %{
9163     Label* L = $labl$$label;
9164     Assembler::Predict predict_taken =
9165       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9166     __ cmp($op1$$Register, $op2$$constant);
9167     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9168     __ delayed()->nop();
9169   %}
9170   ins_pipe(cmp_br_reg_imm);
9171 %}
9172 
9173 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9174   match(If cmp (CmpL op1 op2));
9175   effect(USE labl, KILL xcc);
9176 
9177   size(12);
9178   ins_cost(BRANCH_COST);
9179   format %{ "CMP    $op1,$op2\t! long\n\t"
9180             "BP$cmp   $labl" %}
9181   ins_encode %{
9182     Label* L = $labl$$label;
9183     Assembler::Predict predict_taken =
9184       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9185     __ cmp($op1$$Register, $op2$$Register);
9186     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9187     __ delayed()->nop();
9188   %}
9189   ins_pipe(cmp_br_reg_reg);
9190 %}
9191 
9192 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9193   match(If cmp (CmpL op1 op2));
9194   effect(USE labl, KILL xcc);
9195 
9196   size(12);
9197   ins_cost(BRANCH_COST);
9198   format %{ "CMP    $op1,$op2\t! long\n\t"
9199             "BP$cmp   $labl" %}
9200   ins_encode %{
9201     Label* L = $labl$$label;
9202     Assembler::Predict predict_taken =
9203       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9204     __ cmp($op1$$Register, $op2$$constant);
9205     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9206     __ delayed()->nop();
9207   %}
9208   ins_pipe(cmp_br_reg_imm);
9209 %}
9210 
9211 // Compare Pointers and branch
9212 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9213   match(If cmp (CmpP op1 op2));
9214   effect(USE labl, KILL pcc);
9215 
9216   size(12);
9217   ins_cost(BRANCH_COST);
9218   format %{ "CMP    $op1,$op2\t! ptr\n\t"
9219             "B$cmp   $labl" %}
9220   ins_encode %{
9221     Label* L = $labl$$label;
9222     Assembler::Predict predict_taken =
9223       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9224     __ cmp($op1$$Register, $op2$$Register);
9225     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9226     __ delayed()->nop();
9227   %}
9228   ins_pipe(cmp_br_reg_reg);
9229 %}
9230 
9231 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9232   match(If cmp (CmpP op1 null));
9233   effect(USE labl, KILL pcc);
9234 
9235   size(12);
9236   ins_cost(BRANCH_COST);
9237   format %{ "CMP    $op1,0\t! ptr\n\t"
9238             "B$cmp   $labl" %}
9239   ins_encode %{
9240     Label* L = $labl$$label;
9241     Assembler::Predict predict_taken =
9242       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9243     __ cmp($op1$$Register, G0);
9244     // bpr() is not used here since it has shorter distance.
9245     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9246     __ delayed()->nop();
9247   %}
9248   ins_pipe(cmp_br_reg_reg);
9249 %}
9250 
9251 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9252   match(If cmp (CmpN op1 op2));
9253   effect(USE labl, KILL icc);
9254 
9255   size(12);
9256   ins_cost(BRANCH_COST);
9257   format %{ "CMP    $op1,$op2\t! compressed ptr\n\t"
9258             "BP$cmp   $labl" %}
9259   ins_encode %{
9260     Label* L = $labl$$label;
9261     Assembler::Predict predict_taken =
9262       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9263     __ cmp($op1$$Register, $op2$$Register);
9264     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9265     __ delayed()->nop();
9266   %}
9267   ins_pipe(cmp_br_reg_reg);
9268 %}
9269 
9270 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9271   match(If cmp (CmpN op1 null));
9272   effect(USE labl, KILL icc);
9273 
9274   size(12);
9275   ins_cost(BRANCH_COST);
9276   format %{ "CMP    $op1,0\t! compressed ptr\n\t"
9277             "BP$cmp   $labl" %}
9278   ins_encode %{
9279     Label* L = $labl$$label;
9280     Assembler::Predict predict_taken =
9281       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9282     __ cmp($op1$$Register, G0);
9283     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9284     __ delayed()->nop();
9285   %}
9286   ins_pipe(cmp_br_reg_reg);
9287 %}
9288 
9289 // Loop back branch
9290 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9291   match(CountedLoopEnd cmp (CmpI op1 op2));
9292   effect(USE labl, KILL icc);
9293 
9294   size(12);
9295   ins_cost(BRANCH_COST);
9296   format %{ "CMP    $op1,$op2\t! int\n\t"
9297             "BP$cmp   $labl\t! Loop end" %}
9298   ins_encode %{
9299     Label* L = $labl$$label;
9300     Assembler::Predict predict_taken =
9301       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9302     __ cmp($op1$$Register, $op2$$Register);
9303     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9304     __ delayed()->nop();
9305   %}
9306   ins_pipe(cmp_br_reg_reg);
9307 %}
9308 
9309 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9310   match(CountedLoopEnd cmp (CmpI op1 op2));
9311   effect(USE labl, KILL icc);
9312 
9313   size(12);
9314   ins_cost(BRANCH_COST);
9315   format %{ "CMP    $op1,$op2\t! int\n\t"
9316             "BP$cmp   $labl\t! Loop end" %}
9317   ins_encode %{
9318     Label* L = $labl$$label;
9319     Assembler::Predict predict_taken =
9320       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9321     __ cmp($op1$$Register, $op2$$constant);
9322     __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9323     __ delayed()->nop();
9324   %}
9325   ins_pipe(cmp_br_reg_imm);
9326 %}
9327 
9328 // Short compare and branch instructions
9329 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9330   match(If cmp (CmpI op1 op2));
9331   predicate(UseCBCond);
9332   effect(USE labl, KILL icc);
9333 
9334   size(4);
9335   ins_cost(BRANCH_COST);
9336   format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
9337   ins_encode %{
9338     Label* L = $labl$$label;
9339     assert(__ use_cbcond(*L), "back to back cbcond");
9340     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9341   %}
9342   ins_short_branch(1);
9343   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9344   ins_pipe(cbcond_reg_reg);
9345 %}
9346 
9347 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9348   match(If cmp (CmpI op1 op2));
9349   predicate(UseCBCond);
9350   effect(USE labl, KILL icc);
9351 
9352   size(4);
9353   ins_cost(BRANCH_COST);
9354   format %{ "CWB$cmp  $op1,$op2,$labl\t! int" %}
9355   ins_encode %{
9356     Label* L = $labl$$label;
9357     assert(__ use_cbcond(*L), "back to back cbcond");
9358     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9359   %}
9360   ins_short_branch(1);
9361   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9362   ins_pipe(cbcond_reg_imm);
9363 %}
9364 
9365 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9366   match(If cmp (CmpU op1 op2));
9367   predicate(UseCBCond);
9368   effect(USE labl, KILL icc);
9369 
9370   size(4);
9371   ins_cost(BRANCH_COST);
9372   format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9373   ins_encode %{
9374     Label* L = $labl$$label;
9375     assert(__ use_cbcond(*L), "back to back cbcond");
9376     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9377   %}
9378   ins_short_branch(1);
9379   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9380   ins_pipe(cbcond_reg_reg);
9381 %}
9382 
9383 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9384   match(If cmp (CmpU op1 op2));
9385   predicate(UseCBCond);
9386   effect(USE labl, KILL icc);
9387 
9388   size(4);
9389   ins_cost(BRANCH_COST);
9390   format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9391   ins_encode %{
9392     Label* L = $labl$$label;
9393     assert(__ use_cbcond(*L), "back to back cbcond");
9394     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9395   %}
9396   ins_short_branch(1);
9397   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9398   ins_pipe(cbcond_reg_imm);
9399 %}
9400 
9401 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9402   match(If cmp (CmpL op1 op2));
9403   predicate(UseCBCond);
9404   effect(USE labl, KILL xcc);
9405 
9406   size(4);
9407   ins_cost(BRANCH_COST);
9408   format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
9409   ins_encode %{
9410     Label* L = $labl$$label;
9411     assert(__ use_cbcond(*L), "back to back cbcond");
9412     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9413   %}
9414   ins_short_branch(1);
9415   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9416   ins_pipe(cbcond_reg_reg);
9417 %}
9418 
9419 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9420   match(If cmp (CmpL op1 op2));
9421   predicate(UseCBCond);
9422   effect(USE labl, KILL xcc);
9423 
9424   size(4);
9425   ins_cost(BRANCH_COST);
9426   format %{ "CXB$cmp  $op1,$op2,$labl\t! long" %}
9427   ins_encode %{
9428     Label* L = $labl$$label;
9429     assert(__ use_cbcond(*L), "back to back cbcond");
9430     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9431   %}
9432   ins_short_branch(1);
9433   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9434   ins_pipe(cbcond_reg_imm);
9435 %}
9436 
9437 // Compare Pointers and branch
9438 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9439   match(If cmp (CmpP op1 op2));
9440   predicate(UseCBCond);
9441   effect(USE labl, KILL pcc);
9442 
9443   size(4);
9444   ins_cost(BRANCH_COST);
9445 #ifdef _LP64
9446   format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9447 #else
9448   format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9449 #endif
9450   ins_encode %{
9451     Label* L = $labl$$label;
9452     assert(__ use_cbcond(*L), "back to back cbcond");
9453     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9454   %}
9455   ins_short_branch(1);
9456   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9457   ins_pipe(cbcond_reg_reg);
9458 %}
9459 
9460 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9461   match(If cmp (CmpP op1 null));
9462   predicate(UseCBCond);
9463   effect(USE labl, KILL pcc);
9464 
9465   size(4);
9466   ins_cost(BRANCH_COST);
9467 #ifdef _LP64
9468   format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9469 #else
9470   format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9471 #endif
9472   ins_encode %{
9473     Label* L = $labl$$label;
9474     assert(__ use_cbcond(*L), "back to back cbcond");
9475     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9476   %}
9477   ins_short_branch(1);
9478   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9479   ins_pipe(cbcond_reg_reg);
9480 %}
9481 
9482 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9483   match(If cmp (CmpN op1 op2));
9484   predicate(UseCBCond);
9485   effect(USE labl, KILL icc);
9486 
9487   size(4);
9488   ins_cost(BRANCH_COST);
9489   format %{ "CWB$cmp  $op1,$op2,$labl\t! compressed ptr" %}
9490   ins_encode %{
9491     Label* L = $labl$$label;
9492     assert(__ use_cbcond(*L), "back to back cbcond");
9493     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9494   %}
9495   ins_short_branch(1);
9496   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9497   ins_pipe(cbcond_reg_reg);
9498 %}
9499 
9500 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9501   match(If cmp (CmpN op1 null));
9502   predicate(UseCBCond);
9503   effect(USE labl, KILL icc);
9504 
9505   size(4);
9506   ins_cost(BRANCH_COST);
9507   format %{ "CWB$cmp  $op1,0,$labl\t! compressed ptr" %}
9508   ins_encode %{
9509     Label* L = $labl$$label;
9510     assert(__ use_cbcond(*L), "back to back cbcond");
9511     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9512   %}
9513   ins_short_branch(1);
9514   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9515   ins_pipe(cbcond_reg_reg);
9516 %}
9517 
9518 // Loop back branch
9519 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9520   match(CountedLoopEnd cmp (CmpI op1 op2));
9521   predicate(UseCBCond);
9522   effect(USE labl, KILL icc);
9523 
9524   size(4);
9525   ins_cost(BRANCH_COST);
9526   format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
9527   ins_encode %{
9528     Label* L = $labl$$label;
9529     assert(__ use_cbcond(*L), "back to back cbcond");
9530     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9531   %}
9532   ins_short_branch(1);
9533   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9534   ins_pipe(cbcond_reg_reg);
9535 %}
9536 
9537 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9538   match(CountedLoopEnd cmp (CmpI op1 op2));
9539   predicate(UseCBCond);
9540   effect(USE labl, KILL icc);
9541 
9542   size(4);
9543   ins_cost(BRANCH_COST);
9544   format %{ "CWB$cmp  $op1,$op2,$labl\t! Loop end" %}
9545   ins_encode %{
9546     Label* L = $labl$$label;
9547     assert(__ use_cbcond(*L), "back to back cbcond");
9548     __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9549   %}
9550   ins_short_branch(1);
9551   ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9552   ins_pipe(cbcond_reg_imm);
9553 %}
9554 
9555 // Branch-on-register tests all 64 bits.  We assume that values
9556 // in 64-bit registers always remains zero or sign extended
9557 // unless our code munges the high bits.  Interrupts can chop
9558 // the high order bits to zero or sign at any time.
9559 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9560   match(If cmp (CmpI op1 zero));
9561   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9562   effect(USE labl);
9563 
9564   size(8);
9565   ins_cost(BRANCH_COST);
9566   format %{ "BR$cmp   $op1,$labl" %}
9567   ins_encode( enc_bpr( labl, cmp, op1 ) );
9568   ins_avoid_back_to_back(AVOID_BEFORE);
9569   ins_pipe(br_reg);
9570 %}
9571 
9572 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9573   match(If cmp (CmpP op1 null));
9574   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9575   effect(USE labl);
9576 
9577   size(8);
9578   ins_cost(BRANCH_COST);
9579   format %{ "BR$cmp   $op1,$labl" %}
9580   ins_encode( enc_bpr( labl, cmp, op1 ) );
9581   ins_avoid_back_to_back(AVOID_BEFORE);
9582   ins_pipe(br_reg);
9583 %}
9584 
9585 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9586   match(If cmp (CmpL op1 zero));
9587   predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9588   effect(USE labl);
9589 
9590   size(8);
9591   ins_cost(BRANCH_COST);
9592   format %{ "BR$cmp   $op1,$labl" %}
9593   ins_encode( enc_bpr( labl, cmp, op1 ) );
9594   ins_avoid_back_to_back(AVOID_BEFORE);
9595   ins_pipe(br_reg);
9596 %}
9597 
9598 
9599 // ============================================================================
9600 // Long Compare
9601 //
9602 // Currently we hold longs in 2 registers.  Comparing such values efficiently
9603 // is tricky.  The flavor of compare used depends on whether we are testing
9604 // for LT, LE, or EQ.  For a simple LT test we can check just the sign bit.
9605 // The GE test is the negated LT test.  The LE test can be had by commuting
9606 // the operands (yielding a GE test) and then negating; negate again for the
9607 // GT test.  The EQ test is done by ORcc'ing the high and low halves, and the
9608 // NE test is negated from that.
9609 
9610 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9611 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)).  Note the
9612 // difference between 'Y' and '0L'.  The tree-matches for the CmpI sections
9613 // are collapsed internally in the ADLC's dfa-gen code.  The match for
9614 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9615 // foo match ends up with the wrong leaf.  One fix is to not match both
9616 // reg-reg and reg-zero forms of long-compare.  This is unfortunate because
9617 // both forms beat the trinary form of long-compare and both are very useful
9618 // on Intel which has so few registers.
9619 
9620 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9621   match(If cmp xcc);
9622   effect(USE labl);
9623 
9624   size(8);
9625   ins_cost(BRANCH_COST);
9626   format %{ "BP$cmp   $xcc,$labl" %}
9627   ins_encode %{
9628     Label* L = $labl$$label;
9629     Assembler::Predict predict_taken =
9630       cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9631 
9632     __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9633     __ delayed()->nop();
9634   %}
9635   ins_avoid_back_to_back(AVOID_BEFORE);
9636   ins_pipe(br_cc);
9637 %}
9638 
9639 // Manifest a CmpL3 result in an integer register.  Very painful.
9640 // This is the test to avoid.
9641 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9642   match(Set dst (CmpL3 src1 src2) );
9643   effect( KILL ccr );
9644   ins_cost(6*DEFAULT_COST);
9645   size(24);
9646   format %{ "CMP    $src1,$src2\t\t! long\n"
9647           "\tBLT,a,pn done\n"
9648           "\tMOV    -1,$dst\t! delay slot\n"
9649           "\tBGT,a,pn done\n"
9650           "\tMOV    1,$dst\t! delay slot\n"
9651           "\tCLR    $dst\n"
9652     "done:"     %}
9653   ins_encode( cmpl_flag(src1,src2,dst) );
9654   ins_pipe(cmpL_reg);
9655 %}
9656 
9657 // Conditional move
9658 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9659   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9660   ins_cost(150);
9661   format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
9662   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9663   ins_pipe(ialu_reg);
9664 %}
9665 
9666 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9667   match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9668   ins_cost(140);
9669   format %{ "MOV$cmp  $xcc,$src,$dst\t! long" %}
9670   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9671   ins_pipe(ialu_imm);
9672 %}
9673 
9674 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9675   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9676   ins_cost(150);
9677   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9678   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9679   ins_pipe(ialu_reg);
9680 %}
9681 
9682 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9683   match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9684   ins_cost(140);
9685   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9686   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9687   ins_pipe(ialu_imm);
9688 %}
9689 
9690 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9691   match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9692   ins_cost(150);
9693   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9694   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9695   ins_pipe(ialu_reg);
9696 %}
9697 
9698 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9699   match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9700   ins_cost(150);
9701   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9702   ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9703   ins_pipe(ialu_reg);
9704 %}
9705 
9706 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9707   match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9708   ins_cost(140);
9709   format %{ "MOV$cmp  $xcc,$src,$dst" %}
9710   ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9711   ins_pipe(ialu_imm);
9712 %}
9713 
9714 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9715   match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9716   ins_cost(150);
9717   opcode(0x101);
9718   format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9719   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9720   ins_pipe(int_conditional_float_move);
9721 %}
9722 
9723 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9724   match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9725   ins_cost(150);
9726   opcode(0x102);
9727   format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9728   ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9729   ins_pipe(int_conditional_float_move);
9730 %}
9731 
9732 // ============================================================================
9733 // Safepoint Instruction
9734 instruct safePoint_poll(iRegP poll) %{
9735   match(SafePoint poll);
9736   effect(USE poll);
9737 
9738   size(4);
9739 #ifdef _LP64
9740   format %{ "LDX    [$poll],R_G0\t! Safepoint: poll for GC" %}
9741 #else
9742   format %{ "LDUW   [$poll],R_G0\t! Safepoint: poll for GC" %}
9743 #endif
9744   ins_encode %{
9745     __ relocate(relocInfo::poll_type);
9746     __ ld_ptr($poll$$Register, 0, G0);
9747   %}
9748   ins_pipe(loadPollP);
9749 %}
9750 
9751 // ============================================================================
9752 // Call Instructions
9753 // Call Java Static Instruction
9754 instruct CallStaticJavaDirect( method meth ) %{
9755   match(CallStaticJava);
9756   predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9757   effect(USE meth);
9758 
9759   size(8);
9760   ins_cost(CALL_COST);
9761   format %{ "CALL,static  ; NOP ==> " %}
9762   ins_encode( Java_Static_Call( meth ), call_epilog );
9763   ins_avoid_back_to_back(AVOID_BEFORE);
9764   ins_pipe(simple_call);
9765 %}
9766 
9767 // Call Java Static Instruction (method handle version)
9768 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9769   match(CallStaticJava);
9770   predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9771   effect(USE meth, KILL l7_mh_SP_save);
9772 
9773   size(16);
9774   ins_cost(CALL_COST);
9775   format %{ "CALL,static/MethodHandle" %}
9776   ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9777   ins_pipe(simple_call);
9778 %}
9779 
9780 // Call Java Dynamic Instruction
9781 instruct CallDynamicJavaDirect( method meth ) %{
9782   match(CallDynamicJava);
9783   effect(USE meth);
9784 
9785   ins_cost(CALL_COST);
9786   format %{ "SET    (empty),R_G5\n\t"
9787             "CALL,dynamic  ; NOP ==> " %}
9788   ins_encode( Java_Dynamic_Call( meth ), call_epilog );
9789   ins_pipe(call);
9790 %}
9791 
9792 // Call Runtime Instruction
9793 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
9794   match(CallRuntime);
9795   effect(USE meth, KILL l7);
9796   ins_cost(CALL_COST);
9797   format %{ "CALL,runtime" %}
9798   ins_encode( Java_To_Runtime( meth ),
9799               call_epilog, adjust_long_from_native_call );
9800   ins_avoid_back_to_back(AVOID_BEFORE);
9801   ins_pipe(simple_call);
9802 %}
9803 
9804 // Call runtime without safepoint - same as CallRuntime
9805 instruct CallLeafDirect(method meth, l7RegP l7) %{
9806   match(CallLeaf);
9807   effect(USE meth, KILL l7);
9808   ins_cost(CALL_COST);
9809   format %{ "CALL,runtime leaf" %}
9810   ins_encode( Java_To_Runtime( meth ),
9811               call_epilog,
9812               adjust_long_from_native_call );
9813   ins_avoid_back_to_back(AVOID_BEFORE);
9814   ins_pipe(simple_call);
9815 %}
9816 
9817 // Call runtime without safepoint - same as CallLeaf
9818 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
9819   match(CallLeafNoFP);
9820   effect(USE meth, KILL l7);
9821   ins_cost(CALL_COST);
9822   format %{ "CALL,runtime leaf nofp" %}
9823   ins_encode( Java_To_Runtime( meth ),
9824               call_epilog,
9825               adjust_long_from_native_call );
9826   ins_avoid_back_to_back(AVOID_BEFORE);
9827   ins_pipe(simple_call);
9828 %}
9829 
9830 // Tail Call; Jump from runtime stub to Java code.
9831 // Also known as an 'interprocedural jump'.
9832 // Target of jump will eventually return to caller.
9833 // TailJump below removes the return address.
9834 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
9835   match(TailCall jump_target method_oop );
9836 
9837   ins_cost(CALL_COST);
9838   format %{ "Jmp     $jump_target  ; NOP \t! $method_oop holds method oop" %}
9839   ins_encode(form_jmpl(jump_target));
9840   ins_avoid_back_to_back(AVOID_BEFORE);
9841   ins_pipe(tail_call);
9842 %}
9843 
9844 
9845 // Return Instruction
9846 instruct Ret() %{
9847   match(Return);
9848 
9849   // The epilogue node did the ret already.
9850   size(0);
9851   format %{ "! return" %}
9852   ins_encode();
9853   ins_pipe(empty);
9854 %}
9855 
9856 
9857 // Tail Jump; remove the return address; jump to target.
9858 // TailCall above leaves the return address around.
9859 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
9860 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
9861 // "restore" before this instruction (in Epilogue), we need to materialize it
9862 // in %i0.
9863 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
9864   match( TailJump jump_target ex_oop );
9865   ins_cost(CALL_COST);
9866   format %{ "! discard R_O7\n\t"
9867             "Jmp     $jump_target  ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
9868   ins_encode(form_jmpl_set_exception_pc(jump_target));
9869   // opcode(Assembler::jmpl_op3, Assembler::arith_op);
9870   // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
9871   // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
9872   ins_avoid_back_to_back(AVOID_BEFORE);
9873   ins_pipe(tail_call);
9874 %}
9875 
9876 // Create exception oop: created by stack-crawling runtime code.
9877 // Created exception is now available to this handler, and is setup
9878 // just prior to jumping to this handler.  No code emitted.
9879 instruct CreateException( o0RegP ex_oop )
9880 %{
9881   match(Set ex_oop (CreateEx));
9882   ins_cost(0);
9883 
9884   size(0);
9885   // use the following format syntax
9886   format %{ "! exception oop is in R_O0; no code emitted" %}
9887   ins_encode();
9888   ins_pipe(empty);
9889 %}
9890 
9891 
9892 // Rethrow exception:
9893 // The exception oop will come in the first argument position.
9894 // Then JUMP (not call) to the rethrow stub code.
9895 instruct RethrowException()
9896 %{
9897   match(Rethrow);
9898   ins_cost(CALL_COST);
9899 
9900   // use the following format syntax
9901   format %{ "Jmp    rethrow_stub" %}
9902   ins_encode(enc_rethrow);
9903   ins_avoid_back_to_back(AVOID_BEFORE);
9904   ins_pipe(tail_call);
9905 %}
9906 
9907 
9908 // Die now
9909 instruct ShouldNotReachHere( )
9910 %{
9911   match(Halt);
9912   ins_cost(CALL_COST);
9913 
9914   size(4);
9915   // Use the following format syntax
9916   format %{ "ILLTRAP   ; ShouldNotReachHere" %}
9917   ins_encode( form2_illtrap() );
9918   ins_pipe(tail_call);
9919 %}
9920 
9921 // ============================================================================
9922 // The 2nd slow-half of a subtype check.  Scan the subklass's 2ndary superklass
9923 // array for an instance of the superklass.  Set a hidden internal cache on a
9924 // hit (cache is checked with exposed code in gen_subtype_check()).  Return
9925 // not zero for a miss or zero for a hit.  The encoding ALSO sets flags.
9926 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
9927   match(Set index (PartialSubtypeCheck sub super));
9928   effect( KILL pcc, KILL o7 );
9929   ins_cost(DEFAULT_COST*10);
9930   format %{ "CALL   PartialSubtypeCheck\n\tNOP" %}
9931   ins_encode( enc_PartialSubtypeCheck() );
9932   ins_avoid_back_to_back(AVOID_BEFORE);
9933   ins_pipe(partial_subtype_check_pipe);
9934 %}
9935 
9936 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
9937   match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
9938   effect( KILL idx, KILL o7 );
9939   ins_cost(DEFAULT_COST*10);
9940   format %{ "CALL   PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
9941   ins_encode( enc_PartialSubtypeCheck() );
9942   ins_avoid_back_to_back(AVOID_BEFORE);
9943   ins_pipe(partial_subtype_check_pipe);
9944 %}
9945 
9946 
9947 // ============================================================================
9948 // inlined locking and unlocking
9949 
9950 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9951   match(Set pcc (FastLock object box));
9952 
9953   effect(TEMP scratch2, USE_KILL box, KILL scratch);
9954   ins_cost(100);
9955 
9956   format %{ "FASTLOCK  $object,$box\t! kills $box,$scratch,$scratch2" %}
9957   ins_encode( Fast_Lock(object, box, scratch, scratch2) );
9958   ins_pipe(long_memory_op);
9959 %}
9960 
9961 
9962 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
9963   match(Set pcc (FastUnlock object box));
9964   effect(TEMP scratch2, USE_KILL box, KILL scratch);
9965   ins_cost(100);
9966 
9967   format %{ "FASTUNLOCK  $object,$box\t! kills $box,$scratch,$scratch2" %}
9968   ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
9969   ins_pipe(long_memory_op);
9970 %}
9971 
9972 // The encodings are generic.
9973 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
9974   predicate(!use_block_zeroing(n->in(2)) );
9975   match(Set dummy (ClearArray cnt base));
9976   effect(TEMP temp, KILL ccr);
9977   ins_cost(300);
9978   format %{ "MOV    $cnt,$temp\n"
9979     "loop:   SUBcc  $temp,8,$temp\t! Count down a dword of bytes\n"
9980     "        BRge   loop\t\t! Clearing loop\n"
9981     "        STX    G0,[$base+$temp]\t! delay slot" %}
9982 
9983   ins_encode %{
9984     // Compiler ensures base is doubleword aligned and cnt is count of doublewords
9985     Register nof_bytes_arg    = $cnt$$Register;
9986     Register nof_bytes_tmp    = $temp$$Register;
9987     Register base_pointer_arg = $base$$Register;
9988 
9989     Label loop;
9990     __ mov(nof_bytes_arg, nof_bytes_tmp);
9991 
9992     // Loop and clear, walking backwards through the array.
9993     // nof_bytes_tmp (if >0) is always the number of bytes to zero
9994     __ bind(loop);
9995     __ deccc(nof_bytes_tmp, 8);
9996     __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
9997     __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
9998     // %%%% this mini-loop must not cross a cache boundary!
9999   %}
10000   ins_pipe(long_memory_op);
10001 %}
10002 
10003 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10004   predicate(use_block_zeroing(n->in(2)));
10005   match(Set dummy (ClearArray cnt base));
10006   effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10007   ins_cost(300);
10008   format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
10009 
10010   ins_encode %{
10011 
10012     assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10013     Register to    = $base$$Register;
10014     Register count = $cnt$$Register;
10015 
10016     Label Ldone;
10017     __ nop(); // Separate short branches
10018     // Use BIS for zeroing (temp is not used).
10019     __ bis_zeroing(to, count, G0, Ldone);
10020     __ bind(Ldone);
10021 
10022   %}
10023   ins_pipe(long_memory_op);
10024 %}
10025 
10026 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10027   predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10028   match(Set dummy (ClearArray cnt base));
10029   effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10030   ins_cost(300);
10031   format %{ "CLEAR  [$base, $cnt]\t! ClearArray" %}
10032 
10033   ins_encode %{
10034 
10035     assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10036     Register to    = $base$$Register;
10037     Register count = $cnt$$Register;
10038     Register temp  = $tmp$$Register;
10039 
10040     Label Ldone;
10041     __ nop(); // Separate short branches
10042     // Use BIS for zeroing
10043     __ bis_zeroing(to, count, temp, Ldone);
10044     __ bind(Ldone);
10045 
10046   %}
10047   ins_pipe(long_memory_op);
10048 %}
10049 
10050 instruct string_compareL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10051                          o7RegI tmp, flagsReg ccr) %{
10052   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10053   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10054   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10055   ins_cost(300);
10056   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp" %}
10057   ins_encode %{
10058     __ string_compare($str1$$Register, $str2$$Register,
10059                       $cnt1$$Register, $cnt2$$Register,
10060                       $tmp$$Register, $tmp$$Register,
10061                       $result$$Register, StrIntrinsicNode::LL);
10062   %}
10063   ins_pipe(long_memory_op);
10064 %}
10065 
10066 instruct string_compareU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10067                          o7RegI tmp, flagsReg ccr) %{
10068   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10069   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10070   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10071   ins_cost(300);
10072   format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp" %}
10073   ins_encode %{
10074     __ string_compare($str1$$Register, $str2$$Register,
10075                       $cnt1$$Register, $cnt2$$Register,
10076                       $tmp$$Register, $tmp$$Register,
10077                       $result$$Register, StrIntrinsicNode::UU);
10078   %}
10079   ins_pipe(long_memory_op);
10080 %}
10081 
10082 instruct string_compareLU(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10083                           o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10084   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10085   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10086   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10087   ins_cost(300);
10088   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1,$tmp2" %}
10089   ins_encode %{
10090     __ string_compare($str1$$Register, $str2$$Register,
10091                       $cnt1$$Register, $cnt2$$Register,
10092                       $tmp1$$Register, $tmp2$$Register,
10093                       $result$$Register, StrIntrinsicNode::LU);
10094   %}
10095   ins_pipe(long_memory_op);
10096 %}
10097 
10098 instruct string_compareUL(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10099                           o7RegI tmp1, g1RegI tmp2, flagsReg ccr) %{
10100   predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10101   match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10102   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp1, KILL tmp2);
10103   ins_cost(300);
10104   format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result   // KILL $tmp1,$tmp2" %}
10105   ins_encode %{
10106     __ string_compare($str2$$Register, $str1$$Register,
10107                       $cnt2$$Register, $cnt1$$Register,
10108                       $tmp1$$Register, $tmp2$$Register,
10109                       $result$$Register, StrIntrinsicNode::UL);
10110   %}
10111   ins_pipe(long_memory_op);
10112 %}
10113 
10114 instruct string_equalsL(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10115                         o7RegI tmp, flagsReg ccr) %{
10116   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL);
10117   match(Set result (StrEquals (Binary str1 str2) cnt));
10118   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10119   ins_cost(300);
10120   format %{ "String Equals byte[] $str1,$str2,$cnt -> $result   // KILL $tmp" %}
10121   ins_encode %{
10122     __ array_equals(false, $str1$$Register, $str2$$Register,
10123                     $cnt$$Register, $tmp$$Register,
10124                     $result$$Register, true /* byte */);
10125   %}
10126   ins_pipe(long_memory_op);
10127 %}
10128 
10129 instruct string_equalsU(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10130                         o7RegI tmp, flagsReg ccr) %{
10131   predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU);
10132   match(Set result (StrEquals (Binary str1 str2) cnt));
10133   effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10134   ins_cost(300);
10135   format %{ "String Equals char[]  $str1,$str2,$cnt -> $result   // KILL $tmp" %}
10136   ins_encode %{
10137     __ array_equals(false, $str1$$Register, $str2$$Register,
10138                     $cnt$$Register, $tmp$$Register,
10139                     $result$$Register, false /* byte */);
10140   %}
10141   ins_pipe(long_memory_op);
10142 %}
10143 
10144 instruct array_equalsB(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10145                        o7RegI tmp2, flagsReg ccr) %{
10146   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10147   match(Set result (AryEq ary1 ary2));
10148   effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10149   ins_cost(300);
10150   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1,$tmp2" %}
10151   ins_encode %{
10152     __ array_equals(true, $ary1$$Register, $ary2$$Register,
10153                     $tmp1$$Register, $tmp2$$Register,
10154                     $result$$Register, true /* byte */);
10155   %}
10156   ins_pipe(long_memory_op);
10157 %}
10158 
10159 instruct array_equalsC(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10160                        o7RegI tmp2, flagsReg ccr) %{
10161   predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10162   match(Set result (AryEq ary1 ary2));
10163   effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10164   ins_cost(300);
10165   format %{ "Array Equals $ary1,$ary2 -> $result   // KILL $tmp1,$tmp2" %}
10166   ins_encode %{
10167     __ array_equals(true, $ary1$$Register, $ary2$$Register,
10168                     $tmp1$$Register, $tmp2$$Register,
10169                     $result$$Register, false /* byte */);
10170   %}
10171   ins_pipe(long_memory_op);
10172 %}
10173 
10174 // char[] to byte[] compression
10175 instruct string_compress(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result, iRegL tmp, flagsReg ccr) %{
10176   predicate(UseVIS < 3);
10177   match(Set result (StrCompressedCopy src (Binary dst len)));
10178   effect(TEMP result, TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10179   ins_cost(300);
10180   format %{ "String Compress $src,$dst,$len -> $result    // KILL $tmp" %}
10181   ins_encode %{
10182     Label Ldone;
10183     __ signx($len$$Register);
10184     __ cmp_zero_and_br(Assembler::zero, $len$$Register, Ldone, false, Assembler::pn);
10185     __ delayed()->mov($len$$Register, $result$$Register); // copy count
10186     __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp$$Register, Ldone);
10187     __ bind(Ldone);
10188   %}
10189   ins_pipe(long_memory_op);
10190 %}
10191 
10192 // fast char[] to byte[] compression using VIS instructions
10193 instruct string_compress_fast(o0RegP src, o1RegP dst, g3RegI len, notemp_iRegI result,
10194                               iRegL tmp1, iRegL tmp2, iRegL tmp3, iRegL tmp4,
10195                               regD ftmp1, regD ftmp2, regD ftmp3, flagsReg ccr) %{
10196   predicate(UseVIS >= 3);
10197   match(Set result (StrCompressedCopy src (Binary dst len)));
10198   effect(TEMP result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10199   ins_cost(300);
10200   format %{ "String Compress Fast $src,$dst,$len -> $result    // KILL $tmp1,$tmp2,$tmp3,$tmp4,$ftmp1,$ftmp2,$ftmp3" %}
10201   ins_encode %{
10202     Label Ldone;
10203     __ signx($len$$Register);
10204     __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $result$$Register,
10205                           $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register,
10206                           $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, Ldone);
10207     __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10208     __ string_compress($src$$Register, $dst$$Register, $len$$Register, $result$$Register, $tmp1$$Register, Ldone);
10209     __ bind(Ldone);
10210   %}
10211   ins_pipe(long_memory_op);
10212 %}
10213 
10214 // byte[] to char[] inflation
10215 instruct string_inflate(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10216                         iRegL tmp, flagsReg ccr) %{
10217   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10218   effect(TEMP tmp, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10219   ins_cost(300);
10220   format %{ "String Inflate $src,$dst,$len    // KILL $tmp" %}
10221   ins_encode %{
10222     Label Ldone;
10223     __ signx($len$$Register);
10224     __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10225     __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10226     __ bind(Ldone);
10227   %}
10228   ins_pipe(long_memory_op);
10229 %}
10230 
10231 // fast byte[] to char[] inflation using VIS instructions
10232 instruct string_inflate_fast(Universe dummy, o0RegP src, o1RegP dst, g3RegI len,
10233                              iRegL tmp, regD ftmp1, regD ftmp2, regD ftmp3, regD ftmp4, flagsReg ccr) %{
10234   predicate(UseVIS >= 3);
10235   match(Set dummy (StrInflatedCopy src (Binary dst len)));
10236   effect(TEMP tmp, TEMP ftmp1, TEMP ftmp2, TEMP ftmp3, TEMP ftmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL ccr);
10237   ins_cost(300);
10238   format %{ "String Inflate Fast $src,$dst,$len    // KILL $tmp,$ftmp1,$ftmp2,$ftmp3,$ftmp4" %}
10239   ins_encode %{
10240     Label Ldone;
10241     __ signx($len$$Register);
10242     __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register,
10243                          $ftmp1$$FloatRegister, $ftmp2$$FloatRegister, $ftmp3$$FloatRegister, $ftmp4$$FloatRegister, Ldone);
10244     __ cmp_and_brx_short($len$$Register, 0, Assembler::equal, Assembler::pn, Ldone);
10245     __ string_inflate($src$$Register, $dst$$Register, $len$$Register, $tmp$$Register, Ldone);
10246     __ bind(Ldone);
10247   %}
10248   ins_pipe(long_memory_op);
10249 %}
10250 
10251 
10252 //---------- Zeros Count Instructions ------------------------------------------
10253 
10254 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10255   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10256   match(Set dst (CountLeadingZerosI src));
10257   effect(TEMP dst, TEMP tmp, KILL cr);
10258 
10259   // x |= (x >> 1);
10260   // x |= (x >> 2);
10261   // x |= (x >> 4);
10262   // x |= (x >> 8);
10263   // x |= (x >> 16);
10264   // return (WORDBITS - popc(x));
10265   format %{ "SRL     $src,1,$tmp\t! count leading zeros (int)\n\t"
10266             "SRL     $src,0,$dst\t! 32-bit zero extend\n\t"
10267             "OR      $dst,$tmp,$dst\n\t"
10268             "SRL     $dst,2,$tmp\n\t"
10269             "OR      $dst,$tmp,$dst\n\t"
10270             "SRL     $dst,4,$tmp\n\t"
10271             "OR      $dst,$tmp,$dst\n\t"
10272             "SRL     $dst,8,$tmp\n\t"
10273             "OR      $dst,$tmp,$dst\n\t"
10274             "SRL     $dst,16,$tmp\n\t"
10275             "OR      $dst,$tmp,$dst\n\t"
10276             "POPC    $dst,$dst\n\t"
10277             "MOV     32,$tmp\n\t"
10278             "SUB     $tmp,$dst,$dst" %}
10279   ins_encode %{
10280     Register Rdst = $dst$$Register;
10281     Register Rsrc = $src$$Register;
10282     Register Rtmp = $tmp$$Register;
10283     __ srl(Rsrc, 1,    Rtmp);
10284     __ srl(Rsrc, 0,    Rdst);
10285     __ or3(Rdst, Rtmp, Rdst);
10286     __ srl(Rdst, 2,    Rtmp);
10287     __ or3(Rdst, Rtmp, Rdst);
10288     __ srl(Rdst, 4,    Rtmp);
10289     __ or3(Rdst, Rtmp, Rdst);
10290     __ srl(Rdst, 8,    Rtmp);
10291     __ or3(Rdst, Rtmp, Rdst);
10292     __ srl(Rdst, 16,   Rtmp);
10293     __ or3(Rdst, Rtmp, Rdst);
10294     __ popc(Rdst, Rdst);
10295     __ mov(BitsPerInt, Rtmp);
10296     __ sub(Rtmp, Rdst, Rdst);
10297   %}
10298   ins_pipe(ialu_reg);
10299 %}
10300 
10301 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10302   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10303   match(Set dst (CountLeadingZerosL src));
10304   effect(TEMP dst, TEMP tmp, KILL cr);
10305 
10306   // x |= (x >> 1);
10307   // x |= (x >> 2);
10308   // x |= (x >> 4);
10309   // x |= (x >> 8);
10310   // x |= (x >> 16);
10311   // x |= (x >> 32);
10312   // return (WORDBITS - popc(x));
10313   format %{ "SRLX    $src,1,$tmp\t! count leading zeros (long)\n\t"
10314             "OR      $src,$tmp,$dst\n\t"
10315             "SRLX    $dst,2,$tmp\n\t"
10316             "OR      $dst,$tmp,$dst\n\t"
10317             "SRLX    $dst,4,$tmp\n\t"
10318             "OR      $dst,$tmp,$dst\n\t"
10319             "SRLX    $dst,8,$tmp\n\t"
10320             "OR      $dst,$tmp,$dst\n\t"
10321             "SRLX    $dst,16,$tmp\n\t"
10322             "OR      $dst,$tmp,$dst\n\t"
10323             "SRLX    $dst,32,$tmp\n\t"
10324             "OR      $dst,$tmp,$dst\n\t"
10325             "POPC    $dst,$dst\n\t"
10326             "MOV     64,$tmp\n\t"
10327             "SUB     $tmp,$dst,$dst" %}
10328   ins_encode %{
10329     Register Rdst = $dst$$Register;
10330     Register Rsrc = $src$$Register;
10331     Register Rtmp = $tmp$$Register;
10332     __ srlx(Rsrc, 1,    Rtmp);
10333     __ or3( Rsrc, Rtmp, Rdst);
10334     __ srlx(Rdst, 2,    Rtmp);
10335     __ or3( Rdst, Rtmp, Rdst);
10336     __ srlx(Rdst, 4,    Rtmp);
10337     __ or3( Rdst, Rtmp, Rdst);
10338     __ srlx(Rdst, 8,    Rtmp);
10339     __ or3( Rdst, Rtmp, Rdst);
10340     __ srlx(Rdst, 16,   Rtmp);
10341     __ or3( Rdst, Rtmp, Rdst);
10342     __ srlx(Rdst, 32,   Rtmp);
10343     __ or3( Rdst, Rtmp, Rdst);
10344     __ popc(Rdst, Rdst);
10345     __ mov(BitsPerLong, Rtmp);
10346     __ sub(Rtmp, Rdst, Rdst);
10347   %}
10348   ins_pipe(ialu_reg);
10349 %}
10350 
10351 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10352   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10353   match(Set dst (CountTrailingZerosI src));
10354   effect(TEMP dst, KILL cr);
10355 
10356   // return popc(~x & (x - 1));
10357   format %{ "SUB     $src,1,$dst\t! count trailing zeros (int)\n\t"
10358             "ANDN    $dst,$src,$dst\n\t"
10359             "SRL     $dst,R_G0,$dst\n\t"
10360             "POPC    $dst,$dst" %}
10361   ins_encode %{
10362     Register Rdst = $dst$$Register;
10363     Register Rsrc = $src$$Register;
10364     __ sub(Rsrc, 1, Rdst);
10365     __ andn(Rdst, Rsrc, Rdst);
10366     __ srl(Rdst, G0, Rdst);
10367     __ popc(Rdst, Rdst);
10368   %}
10369   ins_pipe(ialu_reg);
10370 %}
10371 
10372 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10373   predicate(UsePopCountInstruction);  // See Matcher::match_rule_supported
10374   match(Set dst (CountTrailingZerosL src));
10375   effect(TEMP dst, KILL cr);
10376 
10377   // return popc(~x & (x - 1));
10378   format %{ "SUB     $src,1,$dst\t! count trailing zeros (long)\n\t"
10379             "ANDN    $dst,$src,$dst\n\t"
10380             "POPC    $dst,$dst" %}
10381   ins_encode %{
10382     Register Rdst = $dst$$Register;
10383     Register Rsrc = $src$$Register;
10384     __ sub(Rsrc, 1, Rdst);
10385     __ andn(Rdst, Rsrc, Rdst);
10386     __ popc(Rdst, Rdst);
10387   %}
10388   ins_pipe(ialu_reg);
10389 %}
10390 
10391 
10392 //---------- Population Count Instructions -------------------------------------
10393 
10394 instruct popCountI(iRegIsafe dst, iRegI src) %{
10395   predicate(UsePopCountInstruction);
10396   match(Set dst (PopCountI src));
10397 
10398   format %{ "SRL    $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10399             "POPC   $dst, $dst" %}
10400   ins_encode %{
10401     __ srl($src$$Register, G0, $dst$$Register);
10402     __ popc($dst$$Register, $dst$$Register);
10403   %}
10404   ins_pipe(ialu_reg);
10405 %}
10406 
10407 // Note: Long.bitCount(long) returns an int.
10408 instruct popCountL(iRegIsafe dst, iRegL src) %{
10409   predicate(UsePopCountInstruction);
10410   match(Set dst (PopCountL src));
10411 
10412   format %{ "POPC   $src, $dst" %}
10413   ins_encode %{
10414     __ popc($src$$Register, $dst$$Register);
10415   %}
10416   ins_pipe(ialu_reg);
10417 %}
10418 
10419 
10420 // ============================================================================
10421 //------------Bytes reverse--------------------------------------------------
10422 
10423 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10424   match(Set dst (ReverseBytesI src));
10425 
10426   // Op cost is artificially doubled to make sure that load or store
10427   // instructions are preferred over this one which requires a spill
10428   // onto a stack slot.
10429   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10430   format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
10431 
10432   ins_encode %{
10433     __ set($src$$disp + STACK_BIAS, O7);
10434     __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10435   %}
10436   ins_pipe( iload_mem );
10437 %}
10438 
10439 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10440   match(Set dst (ReverseBytesL src));
10441 
10442   // Op cost is artificially doubled to make sure that load or store
10443   // instructions are preferred over this one which requires a spill
10444   // onto a stack slot.
10445   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10446   format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
10447 
10448   ins_encode %{
10449     __ set($src$$disp + STACK_BIAS, O7);
10450     __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10451   %}
10452   ins_pipe( iload_mem );
10453 %}
10454 
10455 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10456   match(Set dst (ReverseBytesUS src));
10457 
10458   // Op cost is artificially doubled to make sure that load or store
10459   // instructions are preferred over this one which requires a spill
10460   // onto a stack slot.
10461   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10462   format %{ "LDUHA  $src, $dst\t!asi=primary_little\n\t" %}
10463 
10464   ins_encode %{
10465     // the value was spilled as an int so bias the load
10466     __ set($src$$disp + STACK_BIAS + 2, O7);
10467     __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10468   %}
10469   ins_pipe( iload_mem );
10470 %}
10471 
10472 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10473   match(Set dst (ReverseBytesS src));
10474 
10475   // Op cost is artificially doubled to make sure that load or store
10476   // instructions are preferred over this one which requires a spill
10477   // onto a stack slot.
10478   ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10479   format %{ "LDSHA  $src, $dst\t!asi=primary_little\n\t" %}
10480 
10481   ins_encode %{
10482     // the value was spilled as an int so bias the load
10483     __ set($src$$disp + STACK_BIAS + 2, O7);
10484     __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10485   %}
10486   ins_pipe( iload_mem );
10487 %}
10488 
10489 // Load Integer reversed byte order
10490 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10491   match(Set dst (ReverseBytesI (LoadI src)));
10492 
10493   ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10494   size(4);
10495   format %{ "LDUWA  $src, $dst\t!asi=primary_little" %}
10496 
10497   ins_encode %{
10498     __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10499   %}
10500   ins_pipe(iload_mem);
10501 %}
10502 
10503 // Load Long - aligned and reversed
10504 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10505   match(Set dst (ReverseBytesL (LoadL src)));
10506 
10507   ins_cost(MEMORY_REF_COST);
10508   size(4);
10509   format %{ "LDXA   $src, $dst\t!asi=primary_little" %}
10510 
10511   ins_encode %{
10512     __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10513   %}
10514   ins_pipe(iload_mem);
10515 %}
10516 
10517 // Load unsigned short / char reversed byte order
10518 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10519   match(Set dst (ReverseBytesUS (LoadUS src)));
10520 
10521   ins_cost(MEMORY_REF_COST);
10522   size(4);
10523   format %{ "LDUHA  $src, $dst\t!asi=primary_little" %}
10524 
10525   ins_encode %{
10526     __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10527   %}
10528   ins_pipe(iload_mem);
10529 %}
10530 
10531 // Load short reversed byte order
10532 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10533   match(Set dst (ReverseBytesS (LoadS src)));
10534 
10535   ins_cost(MEMORY_REF_COST);
10536   size(4);
10537   format %{ "LDSHA  $src, $dst\t!asi=primary_little" %}
10538 
10539   ins_encode %{
10540     __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10541   %}
10542   ins_pipe(iload_mem);
10543 %}
10544 
10545 // Store Integer reversed byte order
10546 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10547   match(Set dst (StoreI dst (ReverseBytesI src)));
10548 
10549   ins_cost(MEMORY_REF_COST);
10550   size(4);
10551   format %{ "STWA   $src, $dst\t!asi=primary_little" %}
10552 
10553   ins_encode %{
10554     __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10555   %}
10556   ins_pipe(istore_mem_reg);
10557 %}
10558 
10559 // Store Long reversed byte order
10560 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10561   match(Set dst (StoreL dst (ReverseBytesL src)));
10562 
10563   ins_cost(MEMORY_REF_COST);
10564   size(4);
10565   format %{ "STXA   $src, $dst\t!asi=primary_little" %}
10566 
10567   ins_encode %{
10568     __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10569   %}
10570   ins_pipe(istore_mem_reg);
10571 %}
10572 
10573 // Store unsighed short/char reversed byte order
10574 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10575   match(Set dst (StoreC dst (ReverseBytesUS src)));
10576 
10577   ins_cost(MEMORY_REF_COST);
10578   size(4);
10579   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
10580 
10581   ins_encode %{
10582     __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10583   %}
10584   ins_pipe(istore_mem_reg);
10585 %}
10586 
10587 // Store short reversed byte order
10588 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10589   match(Set dst (StoreC dst (ReverseBytesS src)));
10590 
10591   ins_cost(MEMORY_REF_COST);
10592   size(4);
10593   format %{ "STHA   $src, $dst\t!asi=primary_little" %}
10594 
10595   ins_encode %{
10596     __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10597   %}
10598   ins_pipe(istore_mem_reg);
10599 %}
10600 
10601 // ====================VECTOR INSTRUCTIONS=====================================
10602 
10603 // Load Aligned Packed values into a Double Register
10604 instruct loadV8(regD dst, memory mem) %{
10605   predicate(n->as_LoadVector()->memory_size() == 8);
10606   match(Set dst (LoadVector mem));
10607   ins_cost(MEMORY_REF_COST);
10608   size(4);
10609   format %{ "LDDF   $mem,$dst\t! load vector (8 bytes)" %}
10610   ins_encode %{
10611     __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10612   %}
10613   ins_pipe(floadD_mem);
10614 %}
10615 
10616 // Store Vector in Double register to memory
10617 instruct storeV8(memory mem, regD src) %{
10618   predicate(n->as_StoreVector()->memory_size() == 8);
10619   match(Set mem (StoreVector mem src));
10620   ins_cost(MEMORY_REF_COST);
10621   size(4);
10622   format %{ "STDF   $src,$mem\t! store vector (8 bytes)" %}
10623   ins_encode %{
10624     __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10625   %}
10626   ins_pipe(fstoreD_mem_reg);
10627 %}
10628 
10629 // Store Zero into vector in memory
10630 instruct storeV8B_zero(memory mem, immI0 zero) %{
10631   predicate(n->as_StoreVector()->memory_size() == 8);
10632   match(Set mem (StoreVector mem (ReplicateB zero)));
10633   ins_cost(MEMORY_REF_COST);
10634   size(4);
10635   format %{ "STX    $zero,$mem\t! store zero vector (8 bytes)" %}
10636   ins_encode %{
10637     __ stx(G0, $mem$$Address);
10638   %}
10639   ins_pipe(fstoreD_mem_zero);
10640 %}
10641 
10642 instruct storeV4S_zero(memory mem, immI0 zero) %{
10643   predicate(n->as_StoreVector()->memory_size() == 8);
10644   match(Set mem (StoreVector mem (ReplicateS zero)));
10645   ins_cost(MEMORY_REF_COST);
10646   size(4);
10647   format %{ "STX    $zero,$mem\t! store zero vector (4 shorts)" %}
10648   ins_encode %{
10649     __ stx(G0, $mem$$Address);
10650   %}
10651   ins_pipe(fstoreD_mem_zero);
10652 %}
10653 
10654 instruct storeV2I_zero(memory mem, immI0 zero) %{
10655   predicate(n->as_StoreVector()->memory_size() == 8);
10656   match(Set mem (StoreVector mem (ReplicateI zero)));
10657   ins_cost(MEMORY_REF_COST);
10658   size(4);
10659   format %{ "STX    $zero,$mem\t! store zero vector (2 ints)" %}
10660   ins_encode %{
10661     __ stx(G0, $mem$$Address);
10662   %}
10663   ins_pipe(fstoreD_mem_zero);
10664 %}
10665 
10666 instruct storeV2F_zero(memory mem, immF0 zero) %{
10667   predicate(n->as_StoreVector()->memory_size() == 8);
10668   match(Set mem (StoreVector mem (ReplicateF zero)));
10669   ins_cost(MEMORY_REF_COST);
10670   size(4);
10671   format %{ "STX    $zero,$mem\t! store zero vector (2 floats)" %}
10672   ins_encode %{
10673     __ stx(G0, $mem$$Address);
10674   %}
10675   ins_pipe(fstoreD_mem_zero);
10676 %}
10677 
10678 // Replicate scalar to packed byte values into Double register
10679 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10680   predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10681   match(Set dst (ReplicateB src));
10682   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10683   format %{ "SLLX  $src,56,$tmp\n\t"
10684             "SRLX  $tmp, 8,$tmp2\n\t"
10685             "OR    $tmp,$tmp2,$tmp\n\t"
10686             "SRLX  $tmp,16,$tmp2\n\t"
10687             "OR    $tmp,$tmp2,$tmp\n\t"
10688             "SRLX  $tmp,32,$tmp2\n\t"
10689             "OR    $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10690             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10691   ins_encode %{
10692     Register Rsrc = $src$$Register;
10693     Register Rtmp = $tmp$$Register;
10694     Register Rtmp2 = $tmp2$$Register;
10695     __ sllx(Rsrc,    56, Rtmp);
10696     __ srlx(Rtmp,     8, Rtmp2);
10697     __ or3 (Rtmp, Rtmp2, Rtmp);
10698     __ srlx(Rtmp,    16, Rtmp2);
10699     __ or3 (Rtmp, Rtmp2, Rtmp);
10700     __ srlx(Rtmp,    32, Rtmp2);
10701     __ or3 (Rtmp, Rtmp2, Rtmp);
10702     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10703   %}
10704   ins_pipe(ialu_reg);
10705 %}
10706 
10707 // Replicate scalar to packed byte values into Double stack
10708 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10709   predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10710   match(Set dst (ReplicateB src));
10711   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10712   format %{ "SLLX  $src,56,$tmp\n\t"
10713             "SRLX  $tmp, 8,$tmp2\n\t"
10714             "OR    $tmp,$tmp2,$tmp\n\t"
10715             "SRLX  $tmp,16,$tmp2\n\t"
10716             "OR    $tmp,$tmp2,$tmp\n\t"
10717             "SRLX  $tmp,32,$tmp2\n\t"
10718             "OR    $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10719             "STX   $tmp,$dst\t! regL to stkD" %}
10720   ins_encode %{
10721     Register Rsrc = $src$$Register;
10722     Register Rtmp = $tmp$$Register;
10723     Register Rtmp2 = $tmp2$$Register;
10724     __ sllx(Rsrc,    56, Rtmp);
10725     __ srlx(Rtmp,     8, Rtmp2);
10726     __ or3 (Rtmp, Rtmp2, Rtmp);
10727     __ srlx(Rtmp,    16, Rtmp2);
10728     __ or3 (Rtmp, Rtmp2, Rtmp);
10729     __ srlx(Rtmp,    32, Rtmp2);
10730     __ or3 (Rtmp, Rtmp2, Rtmp);
10731     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10732     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10733   %}
10734   ins_pipe(ialu_reg);
10735 %}
10736 
10737 // Replicate scalar constant to packed byte values in Double register
10738 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10739   predicate(n->as_Vector()->length() == 8);
10740   match(Set dst (ReplicateB con));
10741   effect(KILL tmp);
10742   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10743   ins_encode %{
10744     // XXX This is a quick fix for 6833573.
10745     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10746     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10747     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10748   %}
10749   ins_pipe(loadConFD);
10750 %}
10751 
10752 // Replicate scalar to packed char/short values into Double register
10753 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10754   predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10755   match(Set dst (ReplicateS src));
10756   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10757   format %{ "SLLX  $src,48,$tmp\n\t"
10758             "SRLX  $tmp,16,$tmp2\n\t"
10759             "OR    $tmp,$tmp2,$tmp\n\t"
10760             "SRLX  $tmp,32,$tmp2\n\t"
10761             "OR    $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10762             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10763   ins_encode %{
10764     Register Rsrc = $src$$Register;
10765     Register Rtmp = $tmp$$Register;
10766     Register Rtmp2 = $tmp2$$Register;
10767     __ sllx(Rsrc,    48, Rtmp);
10768     __ srlx(Rtmp,    16, Rtmp2);
10769     __ or3 (Rtmp, Rtmp2, Rtmp);
10770     __ srlx(Rtmp,    32, Rtmp2);
10771     __ or3 (Rtmp, Rtmp2, Rtmp);
10772     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10773   %}
10774   ins_pipe(ialu_reg);
10775 %}
10776 
10777 // Replicate scalar to packed char/short values into Double stack
10778 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10779   predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10780   match(Set dst (ReplicateS src));
10781   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10782   format %{ "SLLX  $src,48,$tmp\n\t"
10783             "SRLX  $tmp,16,$tmp2\n\t"
10784             "OR    $tmp,$tmp2,$tmp\n\t"
10785             "SRLX  $tmp,32,$tmp2\n\t"
10786             "OR    $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10787             "STX   $tmp,$dst\t! regL to stkD" %}
10788   ins_encode %{
10789     Register Rsrc = $src$$Register;
10790     Register Rtmp = $tmp$$Register;
10791     Register Rtmp2 = $tmp2$$Register;
10792     __ sllx(Rsrc,    48, Rtmp);
10793     __ srlx(Rtmp,    16, Rtmp2);
10794     __ or3 (Rtmp, Rtmp2, Rtmp);
10795     __ srlx(Rtmp,    32, Rtmp2);
10796     __ or3 (Rtmp, Rtmp2, Rtmp);
10797     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10798     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10799   %}
10800   ins_pipe(ialu_reg);
10801 %}
10802 
10803 // Replicate scalar constant to packed char/short values in Double register
10804 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10805   predicate(n->as_Vector()->length() == 4);
10806   match(Set dst (ReplicateS con));
10807   effect(KILL tmp);
10808   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10809   ins_encode %{
10810     // XXX This is a quick fix for 6833573.
10811     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10812     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10813     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10814   %}
10815   ins_pipe(loadConFD);
10816 %}
10817 
10818 // Replicate scalar to packed int values into Double register
10819 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10820   predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10821   match(Set dst (ReplicateI src));
10822   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10823   format %{ "SLLX  $src,32,$tmp\n\t"
10824             "SRLX  $tmp,32,$tmp2\n\t"
10825             "OR    $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10826             "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10827   ins_encode %{
10828     Register Rsrc = $src$$Register;
10829     Register Rtmp = $tmp$$Register;
10830     Register Rtmp2 = $tmp2$$Register;
10831     __ sllx(Rsrc,    32, Rtmp);
10832     __ srlx(Rtmp,    32, Rtmp2);
10833     __ or3 (Rtmp, Rtmp2, Rtmp);
10834     __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10835   %}
10836   ins_pipe(ialu_reg);
10837 %}
10838 
10839 // Replicate scalar to packed int values into Double stack
10840 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10841   predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10842   match(Set dst (ReplicateI src));
10843   effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10844   format %{ "SLLX  $src,32,$tmp\n\t"
10845             "SRLX  $tmp,32,$tmp2\n\t"
10846             "OR    $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10847             "STX   $tmp,$dst\t! regL to stkD" %}
10848   ins_encode %{
10849     Register Rsrc = $src$$Register;
10850     Register Rtmp = $tmp$$Register;
10851     Register Rtmp2 = $tmp2$$Register;
10852     __ sllx(Rsrc,    32, Rtmp);
10853     __ srlx(Rtmp,    32, Rtmp2);
10854     __ or3 (Rtmp, Rtmp2, Rtmp);
10855     __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10856     __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10857   %}
10858   ins_pipe(ialu_reg);
10859 %}
10860 
10861 // Replicate scalar zero constant to packed int values in Double register
10862 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10863   predicate(n->as_Vector()->length() == 2);
10864   match(Set dst (ReplicateI con));
10865   effect(KILL tmp);
10866   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10867   ins_encode %{
10868     // XXX This is a quick fix for 6833573.
10869     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10870     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10871     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10872   %}
10873   ins_pipe(loadConFD);
10874 %}
10875 
10876 // Replicate scalar to packed float values into Double stack
10877 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10878   predicate(n->as_Vector()->length() == 2);
10879   match(Set dst (ReplicateF src));
10880   ins_cost(MEMORY_REF_COST*2);
10881   format %{ "STF    $src,$dst.hi\t! packed2F\n\t"
10882             "STF    $src,$dst.lo" %}
10883   opcode(Assembler::stf_op3);
10884   ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10885   ins_pipe(fstoreF_stk_reg);
10886 %}
10887 
10888 // Replicate scalar zero constant to packed float values in Double register
10889 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10890   predicate(n->as_Vector()->length() == 2);
10891   match(Set dst (ReplicateF con));
10892   effect(KILL tmp);
10893   format %{ "LDDF   [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10894   ins_encode %{
10895     // XXX This is a quick fix for 6833573.
10896     //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10897     RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10898     __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10899   %}
10900   ins_pipe(loadConFD);
10901 %}
10902 
10903 //----------PEEPHOLE RULES-----------------------------------------------------
10904 // These must follow all instruction definitions as they use the names
10905 // defined in the instructions definitions.
10906 //
10907 // peepmatch ( root_instr_name [preceding_instruction]* );
10908 //
10909 // peepconstraint %{
10910 // (instruction_number.operand_name relational_op instruction_number.operand_name
10911 //  [, ...] );
10912 // // instruction numbers are zero-based using left to right order in peepmatch
10913 //
10914 // peepreplace ( instr_name  ( [instruction_number.operand_name]* ) );
10915 // // provide an instruction_number.operand_name for each operand that appears
10916 // // in the replacement instruction's match rule
10917 //
10918 // ---------VM FLAGS---------------------------------------------------------
10919 //
10920 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10921 //
10922 // Each peephole rule is given an identifying number starting with zero and
10923 // increasing by one in the order seen by the parser.  An individual peephole
10924 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10925 // on the command-line.
10926 //
10927 // ---------CURRENT LIMITATIONS----------------------------------------------
10928 //
10929 // Only match adjacent instructions in same basic block
10930 // Only equality constraints
10931 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10932 // Only one replacement instruction
10933 //
10934 // ---------EXAMPLE----------------------------------------------------------
10935 //
10936 // // pertinent parts of existing instructions in architecture description
10937 // instruct movI(eRegI dst, eRegI src) %{
10938 //   match(Set dst (CopyI src));
10939 // %}
10940 //
10941 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10942 //   match(Set dst (AddI dst src));
10943 //   effect(KILL cr);
10944 // %}
10945 //
10946 // // Change (inc mov) to lea
10947 // peephole %{
10948 //   // increment preceeded by register-register move
10949 //   peepmatch ( incI_eReg movI );
10950 //   // require that the destination register of the increment
10951 //   // match the destination register of the move
10952 //   peepconstraint ( 0.dst == 1.dst );
10953 //   // construct a replacement instruction that sets
10954 //   // the destination to ( move's source register + one )
10955 //   peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
10956 // %}
10957 //
10958 
10959 // // Change load of spilled value to only a spill
10960 // instruct storeI(memory mem, eRegI src) %{
10961 //   match(Set mem (StoreI mem src));
10962 // %}
10963 //
10964 // instruct loadI(eRegI dst, memory mem) %{
10965 //   match(Set dst (LoadI mem));
10966 // %}
10967 //
10968 // peephole %{
10969 //   peepmatch ( loadI storeI );
10970 //   peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
10971 //   peepreplace ( storeI( 1.mem 1.mem 1.src ) );
10972 // %}
10973 
10974 //----------SMARTSPILL RULES---------------------------------------------------
10975 // These must follow all instruction definitions as they use the names
10976 // defined in the instructions definitions.
10977 //
10978 // SPARC will probably not have any of these rules due to RISC instruction set.
10979 
10980 //----------PIPELINE-----------------------------------------------------------
10981 // Rules which define the behavior of the target architectures pipeline.
--- EOF ---