1 /* 2 * Copyright (c) 1997, 2016, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/assembler.hpp" 27 #include "asm/assembler.inline.hpp" 28 #include "compiler/disassembler.hpp" 29 #include "gc/shared/cardTableModRefBS.hpp" 30 #include "gc/shared/collectedHeap.inline.hpp" 31 #include "interpreter/interpreter.hpp" 32 #include "memory/resourceArea.hpp" 33 #include "memory/universe.hpp" 34 #include "oops/klass.inline.hpp" 35 #include "prims/methodHandles.hpp" 36 #include "runtime/biasedLocking.hpp" 37 #include "runtime/interfaceSupport.hpp" 38 #include "runtime/objectMonitor.hpp" 39 #include "runtime/os.hpp" 40 #include "runtime/sharedRuntime.hpp" 41 #include "runtime/stubRoutines.hpp" 42 #include "runtime/thread.hpp" 43 #include "utilities/macros.hpp" 44 #if INCLUDE_ALL_GCS 45 #include "gc/g1/g1CollectedHeap.inline.hpp" 46 #include "gc/g1/g1SATBCardTableModRefBS.hpp" 47 #include "gc/g1/heapRegion.hpp" 48 #endif // INCLUDE_ALL_GCS 49 #include "crc32c.h" 50 #ifdef COMPILER2 51 #include "opto/intrinsicnode.hpp" 52 #endif 53 54 #ifdef PRODUCT 55 #define BLOCK_COMMENT(str) /* nothing */ 56 #define STOP(error) stop(error) 57 #else 58 #define BLOCK_COMMENT(str) block_comment(str) 59 #define STOP(error) block_comment(error); stop(error) 60 #endif 61 62 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":") 63 64 #ifdef ASSERT 65 bool AbstractAssembler::pd_check_instruction_mark() { return true; } 66 #endif 67 68 static Assembler::Condition reverse[] = { 69 Assembler::noOverflow /* overflow = 0x0 */ , 70 Assembler::overflow /* noOverflow = 0x1 */ , 71 Assembler::aboveEqual /* carrySet = 0x2, below = 0x2 */ , 72 Assembler::below /* aboveEqual = 0x3, carryClear = 0x3 */ , 73 Assembler::notZero /* zero = 0x4, equal = 0x4 */ , 74 Assembler::zero /* notZero = 0x5, notEqual = 0x5 */ , 75 Assembler::above /* belowEqual = 0x6 */ , 76 Assembler::belowEqual /* above = 0x7 */ , 77 Assembler::positive /* negative = 0x8 */ , 78 Assembler::negative /* positive = 0x9 */ , 79 Assembler::noParity /* parity = 0xa */ , 80 Assembler::parity /* noParity = 0xb */ , 81 Assembler::greaterEqual /* less = 0xc */ , 82 Assembler::less /* greaterEqual = 0xd */ , 83 Assembler::greater /* lessEqual = 0xe */ , 84 Assembler::lessEqual /* greater = 0xf, */ 85 86 }; 87 88 89 // Implementation of MacroAssembler 90 91 // First all the versions that have distinct versions depending on 32/64 bit 92 // Unless the difference is trivial (1 line or so). 93 94 #ifndef _LP64 95 96 // 32bit versions 97 98 Address MacroAssembler::as_Address(AddressLiteral adr) { 99 return Address(adr.target(), adr.rspec()); 100 } 101 102 Address MacroAssembler::as_Address(ArrayAddress adr) { 103 return Address::make_array(adr); 104 } 105 106 void MacroAssembler::call_VM_leaf_base(address entry_point, 107 int number_of_arguments) { 108 call(RuntimeAddress(entry_point)); 109 increment(rsp, number_of_arguments * wordSize); 110 } 111 112 void MacroAssembler::cmpklass(Address src1, Metadata* obj) { 113 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 114 } 115 116 void MacroAssembler::cmpklass(Register src1, Metadata* obj) { 117 cmp_literal32(src1, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 118 } 119 120 void MacroAssembler::cmpoop(Address src1, jobject obj) { 121 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 122 } 123 124 void MacroAssembler::cmpoop(Register src1, jobject obj) { 125 cmp_literal32(src1, (int32_t)obj, oop_Relocation::spec_for_immediate()); 126 } 127 128 void MacroAssembler::extend_sign(Register hi, Register lo) { 129 // According to Intel Doc. AP-526, "Integer Divide", p.18. 130 if (VM_Version::is_P6() && hi == rdx && lo == rax) { 131 cdql(); 132 } else { 133 movl(hi, lo); 134 sarl(hi, 31); 135 } 136 } 137 138 void MacroAssembler::jC2(Register tmp, Label& L) { 139 // set parity bit if FPU flag C2 is set (via rax) 140 save_rax(tmp); 141 fwait(); fnstsw_ax(); 142 sahf(); 143 restore_rax(tmp); 144 // branch 145 jcc(Assembler::parity, L); 146 } 147 148 void MacroAssembler::jnC2(Register tmp, Label& L) { 149 // set parity bit if FPU flag C2 is set (via rax) 150 save_rax(tmp); 151 fwait(); fnstsw_ax(); 152 sahf(); 153 restore_rax(tmp); 154 // branch 155 jcc(Assembler::noParity, L); 156 } 157 158 // 32bit can do a case table jump in one instruction but we no longer allow the base 159 // to be installed in the Address class 160 void MacroAssembler::jump(ArrayAddress entry) { 161 jmp(as_Address(entry)); 162 } 163 164 // Note: y_lo will be destroyed 165 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 166 // Long compare for Java (semantics as described in JVM spec.) 167 Label high, low, done; 168 169 cmpl(x_hi, y_hi); 170 jcc(Assembler::less, low); 171 jcc(Assembler::greater, high); 172 // x_hi is the return register 173 xorl(x_hi, x_hi); 174 cmpl(x_lo, y_lo); 175 jcc(Assembler::below, low); 176 jcc(Assembler::equal, done); 177 178 bind(high); 179 xorl(x_hi, x_hi); 180 increment(x_hi); 181 jmp(done); 182 183 bind(low); 184 xorl(x_hi, x_hi); 185 decrementl(x_hi); 186 187 bind(done); 188 } 189 190 void MacroAssembler::lea(Register dst, AddressLiteral src) { 191 mov_literal32(dst, (int32_t)src.target(), src.rspec()); 192 } 193 194 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 195 // leal(dst, as_Address(adr)); 196 // see note in movl as to why we must use a move 197 mov_literal32(dst, (int32_t) adr.target(), adr.rspec()); 198 } 199 200 void MacroAssembler::leave() { 201 mov(rsp, rbp); 202 pop(rbp); 203 } 204 205 void MacroAssembler::lmul(int x_rsp_offset, int y_rsp_offset) { 206 // Multiplication of two Java long values stored on the stack 207 // as illustrated below. Result is in rdx:rax. 208 // 209 // rsp ---> [ ?? ] \ \ 210 // .... | y_rsp_offset | 211 // [ y_lo ] / (in bytes) | x_rsp_offset 212 // [ y_hi ] | (in bytes) 213 // .... | 214 // [ x_lo ] / 215 // [ x_hi ] 216 // .... 217 // 218 // Basic idea: lo(result) = lo(x_lo * y_lo) 219 // hi(result) = hi(x_lo * y_lo) + lo(x_hi * y_lo) + lo(x_lo * y_hi) 220 Address x_hi(rsp, x_rsp_offset + wordSize); Address x_lo(rsp, x_rsp_offset); 221 Address y_hi(rsp, y_rsp_offset + wordSize); Address y_lo(rsp, y_rsp_offset); 222 Label quick; 223 // load x_hi, y_hi and check if quick 224 // multiplication is possible 225 movl(rbx, x_hi); 226 movl(rcx, y_hi); 227 movl(rax, rbx); 228 orl(rbx, rcx); // rbx, = 0 <=> x_hi = 0 and y_hi = 0 229 jcc(Assembler::zero, quick); // if rbx, = 0 do quick multiply 230 // do full multiplication 231 // 1st step 232 mull(y_lo); // x_hi * y_lo 233 movl(rbx, rax); // save lo(x_hi * y_lo) in rbx, 234 // 2nd step 235 movl(rax, x_lo); 236 mull(rcx); // x_lo * y_hi 237 addl(rbx, rax); // add lo(x_lo * y_hi) to rbx, 238 // 3rd step 239 bind(quick); // note: rbx, = 0 if quick multiply! 240 movl(rax, x_lo); 241 mull(y_lo); // x_lo * y_lo 242 addl(rdx, rbx); // correct hi(x_lo * y_lo) 243 } 244 245 void MacroAssembler::lneg(Register hi, Register lo) { 246 negl(lo); 247 adcl(hi, 0); 248 negl(hi); 249 } 250 251 void MacroAssembler::lshl(Register hi, Register lo) { 252 // Java shift left long support (semantics as described in JVM spec., p.305) 253 // (basic idea for shift counts s >= n: x << s == (x << n) << (s - n)) 254 // shift value is in rcx ! 255 assert(hi != rcx, "must not use rcx"); 256 assert(lo != rcx, "must not use rcx"); 257 const Register s = rcx; // shift count 258 const int n = BitsPerWord; 259 Label L; 260 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 261 cmpl(s, n); // if (s < n) 262 jcc(Assembler::less, L); // else (s >= n) 263 movl(hi, lo); // x := x << n 264 xorl(lo, lo); 265 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 266 bind(L); // s (mod n) < n 267 shldl(hi, lo); // x := x << s 268 shll(lo); 269 } 270 271 272 void MacroAssembler::lshr(Register hi, Register lo, bool sign_extension) { 273 // Java shift right long support (semantics as described in JVM spec., p.306 & p.310) 274 // (basic idea for shift counts s >= n: x >> s == (x >> n) >> (s - n)) 275 assert(hi != rcx, "must not use rcx"); 276 assert(lo != rcx, "must not use rcx"); 277 const Register s = rcx; // shift count 278 const int n = BitsPerWord; 279 Label L; 280 andl(s, 0x3f); // s := s & 0x3f (s < 0x40) 281 cmpl(s, n); // if (s < n) 282 jcc(Assembler::less, L); // else (s >= n) 283 movl(lo, hi); // x := x >> n 284 if (sign_extension) sarl(hi, 31); 285 else xorl(hi, hi); 286 // Note: subl(s, n) is not needed since the Intel shift instructions work rcx mod n! 287 bind(L); // s (mod n) < n 288 shrdl(lo, hi); // x := x >> s 289 if (sign_extension) sarl(hi); 290 else shrl(hi); 291 } 292 293 void MacroAssembler::movoop(Register dst, jobject obj) { 294 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 295 } 296 297 void MacroAssembler::movoop(Address dst, jobject obj) { 298 mov_literal32(dst, (int32_t)obj, oop_Relocation::spec_for_immediate()); 299 } 300 301 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 302 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 303 } 304 305 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 306 mov_literal32(dst, (int32_t)obj, metadata_Relocation::spec_for_immediate()); 307 } 308 309 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 310 // scratch register is not used, 311 // it is defined to match parameters of 64-bit version of this method. 312 if (src.is_lval()) { 313 mov_literal32(dst, (intptr_t)src.target(), src.rspec()); 314 } else { 315 movl(dst, as_Address(src)); 316 } 317 } 318 319 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 320 movl(as_Address(dst), src); 321 } 322 323 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 324 movl(dst, as_Address(src)); 325 } 326 327 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 328 void MacroAssembler::movptr(Address dst, intptr_t src) { 329 movl(dst, src); 330 } 331 332 333 void MacroAssembler::pop_callee_saved_registers() { 334 pop(rcx); 335 pop(rdx); 336 pop(rdi); 337 pop(rsi); 338 } 339 340 void MacroAssembler::pop_fTOS() { 341 fld_d(Address(rsp, 0)); 342 addl(rsp, 2 * wordSize); 343 } 344 345 void MacroAssembler::push_callee_saved_registers() { 346 push(rsi); 347 push(rdi); 348 push(rdx); 349 push(rcx); 350 } 351 352 void MacroAssembler::push_fTOS() { 353 subl(rsp, 2 * wordSize); 354 fstp_d(Address(rsp, 0)); 355 } 356 357 358 void MacroAssembler::pushoop(jobject obj) { 359 push_literal32((int32_t)obj, oop_Relocation::spec_for_immediate()); 360 } 361 362 void MacroAssembler::pushklass(Metadata* obj) { 363 push_literal32((int32_t)obj, metadata_Relocation::spec_for_immediate()); 364 } 365 366 void MacroAssembler::pushptr(AddressLiteral src) { 367 if (src.is_lval()) { 368 push_literal32((int32_t)src.target(), src.rspec()); 369 } else { 370 pushl(as_Address(src)); 371 } 372 } 373 374 void MacroAssembler::set_word_if_not_zero(Register dst) { 375 xorl(dst, dst); 376 set_byte_if_not_zero(dst); 377 } 378 379 static void pass_arg0(MacroAssembler* masm, Register arg) { 380 masm->push(arg); 381 } 382 383 static void pass_arg1(MacroAssembler* masm, Register arg) { 384 masm->push(arg); 385 } 386 387 static void pass_arg2(MacroAssembler* masm, Register arg) { 388 masm->push(arg); 389 } 390 391 static void pass_arg3(MacroAssembler* masm, Register arg) { 392 masm->push(arg); 393 } 394 395 #ifndef PRODUCT 396 extern "C" void findpc(intptr_t x); 397 #endif 398 399 void MacroAssembler::debug32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip, char* msg) { 400 // In order to get locks to work, we need to fake a in_VM state 401 JavaThread* thread = JavaThread::current(); 402 JavaThreadState saved_state = thread->thread_state(); 403 thread->set_thread_state(_thread_in_vm); 404 if (ShowMessageBoxOnError) { 405 JavaThread* thread = JavaThread::current(); 406 JavaThreadState saved_state = thread->thread_state(); 407 thread->set_thread_state(_thread_in_vm); 408 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 409 ttyLocker ttyl; 410 BytecodeCounter::print(); 411 } 412 // To see where a verify_oop failed, get $ebx+40/X for this frame. 413 // This is the value of eip which points to where verify_oop will return. 414 if (os::message_box(msg, "Execution stopped, print registers?")) { 415 print_state32(rdi, rsi, rbp, rsp, rbx, rdx, rcx, rax, eip); 416 BREAKPOINT; 417 } 418 } else { 419 ttyLocker ttyl; 420 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", msg); 421 } 422 // Don't assert holding the ttyLock 423 assert(false, "DEBUG MESSAGE: %s", msg); 424 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 425 } 426 427 void MacroAssembler::print_state32(int rdi, int rsi, int rbp, int rsp, int rbx, int rdx, int rcx, int rax, int eip) { 428 ttyLocker ttyl; 429 FlagSetting fs(Debugging, true); 430 tty->print_cr("eip = 0x%08x", eip); 431 #ifndef PRODUCT 432 if ((WizardMode || Verbose) && PrintMiscellaneous) { 433 tty->cr(); 434 findpc(eip); 435 tty->cr(); 436 } 437 #endif 438 #define PRINT_REG(rax) \ 439 { tty->print("%s = ", #rax); os::print_location(tty, rax); } 440 PRINT_REG(rax); 441 PRINT_REG(rbx); 442 PRINT_REG(rcx); 443 PRINT_REG(rdx); 444 PRINT_REG(rdi); 445 PRINT_REG(rsi); 446 PRINT_REG(rbp); 447 PRINT_REG(rsp); 448 #undef PRINT_REG 449 // Print some words near top of staack. 450 int* dump_sp = (int*) rsp; 451 for (int col1 = 0; col1 < 8; col1++) { 452 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 453 os::print_location(tty, *dump_sp++); 454 } 455 for (int row = 0; row < 16; row++) { 456 tty->print("(rsp+0x%03x) 0x%08x: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (intptr_t)dump_sp); 457 for (int col = 0; col < 8; col++) { 458 tty->print(" 0x%08x", *dump_sp++); 459 } 460 tty->cr(); 461 } 462 // Print some instructions around pc: 463 Disassembler::decode((address)eip-64, (address)eip); 464 tty->print_cr("--------"); 465 Disassembler::decode((address)eip, (address)eip+32); 466 } 467 468 void MacroAssembler::stop(const char* msg) { 469 ExternalAddress message((address)msg); 470 // push address of message 471 pushptr(message.addr()); 472 { Label L; call(L, relocInfo::none); bind(L); } // push eip 473 pusha(); // push registers 474 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug32))); 475 hlt(); 476 } 477 478 void MacroAssembler::warn(const char* msg) { 479 push_CPU_state(); 480 481 ExternalAddress message((address) msg); 482 // push address of message 483 pushptr(message.addr()); 484 485 call(RuntimeAddress(CAST_FROM_FN_PTR(address, warning))); 486 addl(rsp, wordSize); // discard argument 487 pop_CPU_state(); 488 } 489 490 void MacroAssembler::print_state() { 491 { Label L; call(L, relocInfo::none); bind(L); } // push eip 492 pusha(); // push registers 493 494 push_CPU_state(); 495 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::print_state32))); 496 pop_CPU_state(); 497 498 popa(); 499 addl(rsp, wordSize); 500 } 501 502 #else // _LP64 503 504 // 64 bit versions 505 506 Address MacroAssembler::as_Address(AddressLiteral adr) { 507 // amd64 always does this as a pc-rel 508 // we can be absolute or disp based on the instruction type 509 // jmp/call are displacements others are absolute 510 assert(!adr.is_lval(), "must be rval"); 511 assert(reachable(adr), "must be"); 512 return Address((int32_t)(intptr_t)(adr.target() - pc()), adr.target(), adr.reloc()); 513 514 } 515 516 Address MacroAssembler::as_Address(ArrayAddress adr) { 517 AddressLiteral base = adr.base(); 518 lea(rscratch1, base); 519 Address index = adr.index(); 520 assert(index._disp == 0, "must not have disp"); // maybe it can? 521 Address array(rscratch1, index._index, index._scale, index._disp); 522 return array; 523 } 524 525 void MacroAssembler::call_VM_leaf_base(address entry_point, int num_args) { 526 Label L, E; 527 528 #ifdef _WIN64 529 // Windows always allocates space for it's register args 530 assert(num_args <= 4, "only register arguments supported"); 531 subq(rsp, frame::arg_reg_save_area_bytes); 532 #endif 533 534 // Align stack if necessary 535 testl(rsp, 15); 536 jcc(Assembler::zero, L); 537 538 subq(rsp, 8); 539 { 540 call(RuntimeAddress(entry_point)); 541 } 542 addq(rsp, 8); 543 jmp(E); 544 545 bind(L); 546 { 547 call(RuntimeAddress(entry_point)); 548 } 549 550 bind(E); 551 552 #ifdef _WIN64 553 // restore stack pointer 554 addq(rsp, frame::arg_reg_save_area_bytes); 555 #endif 556 557 } 558 559 void MacroAssembler::cmp64(Register src1, AddressLiteral src2) { 560 assert(!src2.is_lval(), "should use cmpptr"); 561 562 if (reachable(src2)) { 563 cmpq(src1, as_Address(src2)); 564 } else { 565 lea(rscratch1, src2); 566 Assembler::cmpq(src1, Address(rscratch1, 0)); 567 } 568 } 569 570 int MacroAssembler::corrected_idivq(Register reg) { 571 // Full implementation of Java ldiv and lrem; checks for special 572 // case as described in JVM spec., p.243 & p.271. The function 573 // returns the (pc) offset of the idivl instruction - may be needed 574 // for implicit exceptions. 575 // 576 // normal case special case 577 // 578 // input : rax: dividend min_long 579 // reg: divisor (may not be eax/edx) -1 580 // 581 // output: rax: quotient (= rax idiv reg) min_long 582 // rdx: remainder (= rax irem reg) 0 583 assert(reg != rax && reg != rdx, "reg cannot be rax or rdx register"); 584 static const int64_t min_long = 0x8000000000000000; 585 Label normal_case, special_case; 586 587 // check for special case 588 cmp64(rax, ExternalAddress((address) &min_long)); 589 jcc(Assembler::notEqual, normal_case); 590 xorl(rdx, rdx); // prepare rdx for possible special case (where 591 // remainder = 0) 592 cmpq(reg, -1); 593 jcc(Assembler::equal, special_case); 594 595 // handle normal case 596 bind(normal_case); 597 cdqq(); 598 int idivq_offset = offset(); 599 idivq(reg); 600 601 // normal and special case exit 602 bind(special_case); 603 604 return idivq_offset; 605 } 606 607 void MacroAssembler::decrementq(Register reg, int value) { 608 if (value == min_jint) { subq(reg, value); return; } 609 if (value < 0) { incrementq(reg, -value); return; } 610 if (value == 0) { ; return; } 611 if (value == 1 && UseIncDec) { decq(reg) ; return; } 612 /* else */ { subq(reg, value) ; return; } 613 } 614 615 void MacroAssembler::decrementq(Address dst, int value) { 616 if (value == min_jint) { subq(dst, value); return; } 617 if (value < 0) { incrementq(dst, -value); return; } 618 if (value == 0) { ; return; } 619 if (value == 1 && UseIncDec) { decq(dst) ; return; } 620 /* else */ { subq(dst, value) ; return; } 621 } 622 623 void MacroAssembler::incrementq(AddressLiteral dst) { 624 if (reachable(dst)) { 625 incrementq(as_Address(dst)); 626 } else { 627 lea(rscratch1, dst); 628 incrementq(Address(rscratch1, 0)); 629 } 630 } 631 632 void MacroAssembler::incrementq(Register reg, int value) { 633 if (value == min_jint) { addq(reg, value); return; } 634 if (value < 0) { decrementq(reg, -value); return; } 635 if (value == 0) { ; return; } 636 if (value == 1 && UseIncDec) { incq(reg) ; return; } 637 /* else */ { addq(reg, value) ; return; } 638 } 639 640 void MacroAssembler::incrementq(Address dst, int value) { 641 if (value == min_jint) { addq(dst, value); return; } 642 if (value < 0) { decrementq(dst, -value); return; } 643 if (value == 0) { ; return; } 644 if (value == 1 && UseIncDec) { incq(dst) ; return; } 645 /* else */ { addq(dst, value) ; return; } 646 } 647 648 // 32bit can do a case table jump in one instruction but we no longer allow the base 649 // to be installed in the Address class 650 void MacroAssembler::jump(ArrayAddress entry) { 651 lea(rscratch1, entry.base()); 652 Address dispatch = entry.index(); 653 assert(dispatch._base == noreg, "must be"); 654 dispatch._base = rscratch1; 655 jmp(dispatch); 656 } 657 658 void MacroAssembler::lcmp2int(Register x_hi, Register x_lo, Register y_hi, Register y_lo) { 659 ShouldNotReachHere(); // 64bit doesn't use two regs 660 cmpq(x_lo, y_lo); 661 } 662 663 void MacroAssembler::lea(Register dst, AddressLiteral src) { 664 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 665 } 666 667 void MacroAssembler::lea(Address dst, AddressLiteral adr) { 668 mov_literal64(rscratch1, (intptr_t)adr.target(), adr.rspec()); 669 movptr(dst, rscratch1); 670 } 671 672 void MacroAssembler::leave() { 673 // %%% is this really better? Why not on 32bit too? 674 emit_int8((unsigned char)0xC9); // LEAVE 675 } 676 677 void MacroAssembler::lneg(Register hi, Register lo) { 678 ShouldNotReachHere(); // 64bit doesn't use two regs 679 negq(lo); 680 } 681 682 void MacroAssembler::movoop(Register dst, jobject obj) { 683 mov_literal64(dst, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 684 } 685 686 void MacroAssembler::movoop(Address dst, jobject obj) { 687 mov_literal64(rscratch1, (intptr_t)obj, oop_Relocation::spec_for_immediate()); 688 movq(dst, rscratch1); 689 } 690 691 void MacroAssembler::mov_metadata(Register dst, Metadata* obj) { 692 mov_literal64(dst, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 693 } 694 695 void MacroAssembler::mov_metadata(Address dst, Metadata* obj) { 696 mov_literal64(rscratch1, (intptr_t)obj, metadata_Relocation::spec_for_immediate()); 697 movq(dst, rscratch1); 698 } 699 700 void MacroAssembler::movptr(Register dst, AddressLiteral src, Register scratch) { 701 if (src.is_lval()) { 702 mov_literal64(dst, (intptr_t)src.target(), src.rspec()); 703 } else { 704 if (reachable(src)) { 705 movq(dst, as_Address(src)); 706 } else { 707 lea(scratch, src); 708 movq(dst, Address(scratch, 0)); 709 } 710 } 711 } 712 713 void MacroAssembler::movptr(ArrayAddress dst, Register src) { 714 movq(as_Address(dst), src); 715 } 716 717 void MacroAssembler::movptr(Register dst, ArrayAddress src) { 718 movq(dst, as_Address(src)); 719 } 720 721 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 722 void MacroAssembler::movptr(Address dst, intptr_t src) { 723 mov64(rscratch1, src); 724 movq(dst, rscratch1); 725 } 726 727 // These are mostly for initializing NULL 728 void MacroAssembler::movptr(Address dst, int32_t src) { 729 movslq(dst, src); 730 } 731 732 void MacroAssembler::movptr(Register dst, int32_t src) { 733 mov64(dst, (intptr_t)src); 734 } 735 736 void MacroAssembler::pushoop(jobject obj) { 737 movoop(rscratch1, obj); 738 push(rscratch1); 739 } 740 741 void MacroAssembler::pushklass(Metadata* obj) { 742 mov_metadata(rscratch1, obj); 743 push(rscratch1); 744 } 745 746 void MacroAssembler::pushptr(AddressLiteral src) { 747 lea(rscratch1, src); 748 if (src.is_lval()) { 749 push(rscratch1); 750 } else { 751 pushq(Address(rscratch1, 0)); 752 } 753 } 754 755 void MacroAssembler::reset_last_Java_frame(bool clear_fp, 756 bool clear_pc) { 757 // we must set sp to zero to clear frame 758 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 759 // must clear fp, so that compiled frames are not confused; it is 760 // possible that we need it only for debugging 761 if (clear_fp) { 762 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 763 } 764 765 if (clear_pc) { 766 movptr(Address(r15_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 767 } 768 } 769 770 void MacroAssembler::set_last_Java_frame(Register last_java_sp, 771 Register last_java_fp, 772 address last_java_pc) { 773 // determine last_java_sp register 774 if (!last_java_sp->is_valid()) { 775 last_java_sp = rsp; 776 } 777 778 // last_java_fp is optional 779 if (last_java_fp->is_valid()) { 780 movptr(Address(r15_thread, JavaThread::last_Java_fp_offset()), 781 last_java_fp); 782 } 783 784 // last_java_pc is optional 785 if (last_java_pc != NULL) { 786 Address java_pc(r15_thread, 787 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()); 788 lea(rscratch1, InternalAddress(last_java_pc)); 789 movptr(java_pc, rscratch1); 790 } 791 792 movptr(Address(r15_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 793 } 794 795 static void pass_arg0(MacroAssembler* masm, Register arg) { 796 if (c_rarg0 != arg ) { 797 masm->mov(c_rarg0, arg); 798 } 799 } 800 801 static void pass_arg1(MacroAssembler* masm, Register arg) { 802 if (c_rarg1 != arg ) { 803 masm->mov(c_rarg1, arg); 804 } 805 } 806 807 static void pass_arg2(MacroAssembler* masm, Register arg) { 808 if (c_rarg2 != arg ) { 809 masm->mov(c_rarg2, arg); 810 } 811 } 812 813 static void pass_arg3(MacroAssembler* masm, Register arg) { 814 if (c_rarg3 != arg ) { 815 masm->mov(c_rarg3, arg); 816 } 817 } 818 819 void MacroAssembler::stop(const char* msg) { 820 address rip = pc(); 821 pusha(); // get regs on stack 822 lea(c_rarg0, ExternalAddress((address) msg)); 823 lea(c_rarg1, InternalAddress(rip)); 824 movq(c_rarg2, rsp); // pass pointer to regs array 825 andq(rsp, -16); // align stack as required by ABI 826 call(RuntimeAddress(CAST_FROM_FN_PTR(address, MacroAssembler::debug64))); 827 hlt(); 828 } 829 830 void MacroAssembler::warn(const char* msg) { 831 push(rbp); 832 movq(rbp, rsp); 833 andq(rsp, -16); // align stack as required by push_CPU_state and call 834 push_CPU_state(); // keeps alignment at 16 bytes 835 lea(c_rarg0, ExternalAddress((address) msg)); 836 call_VM_leaf(CAST_FROM_FN_PTR(address, warning), c_rarg0); 837 pop_CPU_state(); 838 mov(rsp, rbp); 839 pop(rbp); 840 } 841 842 void MacroAssembler::print_state() { 843 address rip = pc(); 844 pusha(); // get regs on stack 845 push(rbp); 846 movq(rbp, rsp); 847 andq(rsp, -16); // align stack as required by push_CPU_state and call 848 push_CPU_state(); // keeps alignment at 16 bytes 849 850 lea(c_rarg0, InternalAddress(rip)); 851 lea(c_rarg1, Address(rbp, wordSize)); // pass pointer to regs array 852 call_VM_leaf(CAST_FROM_FN_PTR(address, MacroAssembler::print_state64), c_rarg0, c_rarg1); 853 854 pop_CPU_state(); 855 mov(rsp, rbp); 856 pop(rbp); 857 popa(); 858 } 859 860 #ifndef PRODUCT 861 extern "C" void findpc(intptr_t x); 862 #endif 863 864 void MacroAssembler::debug64(char* msg, int64_t pc, int64_t regs[]) { 865 // In order to get locks to work, we need to fake a in_VM state 866 if (ShowMessageBoxOnError) { 867 JavaThread* thread = JavaThread::current(); 868 JavaThreadState saved_state = thread->thread_state(); 869 thread->set_thread_state(_thread_in_vm); 870 #ifndef PRODUCT 871 if (CountBytecodes || TraceBytecodes || StopInterpreterAt) { 872 ttyLocker ttyl; 873 BytecodeCounter::print(); 874 } 875 #endif 876 // To see where a verify_oop failed, get $ebx+40/X for this frame. 877 // XXX correct this offset for amd64 878 // This is the value of eip which points to where verify_oop will return. 879 if (os::message_box(msg, "Execution stopped, print registers?")) { 880 print_state64(pc, regs); 881 BREAKPOINT; 882 assert(false, "start up GDB"); 883 } 884 ThreadStateTransition::transition(thread, _thread_in_vm, saved_state); 885 } else { 886 ttyLocker ttyl; 887 ::tty->print_cr("=============== DEBUG MESSAGE: %s ================\n", 888 msg); 889 assert(false, "DEBUG MESSAGE: %s", msg); 890 } 891 } 892 893 void MacroAssembler::print_state64(int64_t pc, int64_t regs[]) { 894 ttyLocker ttyl; 895 FlagSetting fs(Debugging, true); 896 tty->print_cr("rip = 0x%016lx", pc); 897 #ifndef PRODUCT 898 tty->cr(); 899 findpc(pc); 900 tty->cr(); 901 #endif 902 #define PRINT_REG(rax, value) \ 903 { tty->print("%s = ", #rax); os::print_location(tty, value); } 904 PRINT_REG(rax, regs[15]); 905 PRINT_REG(rbx, regs[12]); 906 PRINT_REG(rcx, regs[14]); 907 PRINT_REG(rdx, regs[13]); 908 PRINT_REG(rdi, regs[8]); 909 PRINT_REG(rsi, regs[9]); 910 PRINT_REG(rbp, regs[10]); 911 PRINT_REG(rsp, regs[11]); 912 PRINT_REG(r8 , regs[7]); 913 PRINT_REG(r9 , regs[6]); 914 PRINT_REG(r10, regs[5]); 915 PRINT_REG(r11, regs[4]); 916 PRINT_REG(r12, regs[3]); 917 PRINT_REG(r13, regs[2]); 918 PRINT_REG(r14, regs[1]); 919 PRINT_REG(r15, regs[0]); 920 #undef PRINT_REG 921 // Print some words near top of staack. 922 int64_t* rsp = (int64_t*) regs[11]; 923 int64_t* dump_sp = rsp; 924 for (int col1 = 0; col1 < 8; col1++) { 925 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 926 os::print_location(tty, *dump_sp++); 927 } 928 for (int row = 0; row < 25; row++) { 929 tty->print("(rsp+0x%03x) 0x%016lx: ", (int)((intptr_t)dump_sp - (intptr_t)rsp), (int64_t)dump_sp); 930 for (int col = 0; col < 4; col++) { 931 tty->print(" 0x%016lx", *dump_sp++); 932 } 933 tty->cr(); 934 } 935 // Print some instructions around pc: 936 Disassembler::decode((address)pc-64, (address)pc); 937 tty->print_cr("--------"); 938 Disassembler::decode((address)pc, (address)pc+32); 939 } 940 941 #endif // _LP64 942 943 // Now versions that are common to 32/64 bit 944 945 void MacroAssembler::addptr(Register dst, int32_t imm32) { 946 LP64_ONLY(addq(dst, imm32)) NOT_LP64(addl(dst, imm32)); 947 } 948 949 void MacroAssembler::addptr(Register dst, Register src) { 950 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 951 } 952 953 void MacroAssembler::addptr(Address dst, Register src) { 954 LP64_ONLY(addq(dst, src)) NOT_LP64(addl(dst, src)); 955 } 956 957 void MacroAssembler::addsd(XMMRegister dst, AddressLiteral src) { 958 if (reachable(src)) { 959 Assembler::addsd(dst, as_Address(src)); 960 } else { 961 lea(rscratch1, src); 962 Assembler::addsd(dst, Address(rscratch1, 0)); 963 } 964 } 965 966 void MacroAssembler::addss(XMMRegister dst, AddressLiteral src) { 967 if (reachable(src)) { 968 addss(dst, as_Address(src)); 969 } else { 970 lea(rscratch1, src); 971 addss(dst, Address(rscratch1, 0)); 972 } 973 } 974 975 void MacroAssembler::addpd(XMMRegister dst, AddressLiteral src) { 976 if (reachable(src)) { 977 Assembler::addpd(dst, as_Address(src)); 978 } else { 979 lea(rscratch1, src); 980 Assembler::addpd(dst, Address(rscratch1, 0)); 981 } 982 } 983 984 void MacroAssembler::align(int modulus) { 985 align(modulus, offset()); 986 } 987 988 void MacroAssembler::align(int modulus, int target) { 989 if (target % modulus != 0) { 990 nop(modulus - (target % modulus)); 991 } 992 } 993 994 void MacroAssembler::andpd(XMMRegister dst, AddressLiteral src) { 995 // Used in sign-masking with aligned address. 996 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 997 if (reachable(src)) { 998 Assembler::andpd(dst, as_Address(src)); 999 } else { 1000 lea(rscratch1, src); 1001 Assembler::andpd(dst, Address(rscratch1, 0)); 1002 } 1003 } 1004 1005 void MacroAssembler::andps(XMMRegister dst, AddressLiteral src) { 1006 // Used in sign-masking with aligned address. 1007 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 1008 if (reachable(src)) { 1009 Assembler::andps(dst, as_Address(src)); 1010 } else { 1011 lea(rscratch1, src); 1012 Assembler::andps(dst, Address(rscratch1, 0)); 1013 } 1014 } 1015 1016 void MacroAssembler::andptr(Register dst, int32_t imm32) { 1017 LP64_ONLY(andq(dst, imm32)) NOT_LP64(andl(dst, imm32)); 1018 } 1019 1020 void MacroAssembler::atomic_incl(Address counter_addr) { 1021 if (os::is_MP()) 1022 lock(); 1023 incrementl(counter_addr); 1024 } 1025 1026 void MacroAssembler::atomic_incl(AddressLiteral counter_addr, Register scr) { 1027 if (reachable(counter_addr)) { 1028 atomic_incl(as_Address(counter_addr)); 1029 } else { 1030 lea(scr, counter_addr); 1031 atomic_incl(Address(scr, 0)); 1032 } 1033 } 1034 1035 #ifdef _LP64 1036 void MacroAssembler::atomic_incq(Address counter_addr) { 1037 if (os::is_MP()) 1038 lock(); 1039 incrementq(counter_addr); 1040 } 1041 1042 void MacroAssembler::atomic_incq(AddressLiteral counter_addr, Register scr) { 1043 if (reachable(counter_addr)) { 1044 atomic_incq(as_Address(counter_addr)); 1045 } else { 1046 lea(scr, counter_addr); 1047 atomic_incq(Address(scr, 0)); 1048 } 1049 } 1050 #endif 1051 1052 // Writes to stack successive pages until offset reached to check for 1053 // stack overflow + shadow pages. This clobbers tmp. 1054 void MacroAssembler::bang_stack_size(Register size, Register tmp) { 1055 movptr(tmp, rsp); 1056 // Bang stack for total size given plus shadow page size. 1057 // Bang one page at a time because large size can bang beyond yellow and 1058 // red zones. 1059 Label loop; 1060 bind(loop); 1061 movl(Address(tmp, (-os::vm_page_size())), size ); 1062 subptr(tmp, os::vm_page_size()); 1063 subl(size, os::vm_page_size()); 1064 jcc(Assembler::greater, loop); 1065 1066 // Bang down shadow pages too. 1067 // At this point, (tmp-0) is the last address touched, so don't 1068 // touch it again. (It was touched as (tmp-pagesize) but then tmp 1069 // was post-decremented.) Skip this address by starting at i=1, and 1070 // touch a few more pages below. N.B. It is important to touch all 1071 // the way down including all pages in the shadow zone. 1072 for (int i = 1; i < ((int)JavaThread::stack_shadow_zone_size() / os::vm_page_size()); i++) { 1073 // this could be any sized move but this is can be a debugging crumb 1074 // so the bigger the better. 1075 movptr(Address(tmp, (-i*os::vm_page_size())), size ); 1076 } 1077 } 1078 1079 void MacroAssembler::reserved_stack_check() { 1080 // testing if reserved zone needs to be enabled 1081 Label no_reserved_zone_enabling; 1082 Register thread = NOT_LP64(rsi) LP64_ONLY(r15_thread); 1083 NOT_LP64(get_thread(rsi);) 1084 1085 cmpptr(rsp, Address(thread, JavaThread::reserved_stack_activation_offset())); 1086 jcc(Assembler::below, no_reserved_zone_enabling); 1087 1088 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), thread); 1089 jump(RuntimeAddress(StubRoutines::throw_delayed_StackOverflowError_entry())); 1090 should_not_reach_here(); 1091 1092 bind(no_reserved_zone_enabling); 1093 } 1094 1095 int MacroAssembler::biased_locking_enter(Register lock_reg, 1096 Register obj_reg, 1097 Register swap_reg, 1098 Register tmp_reg, 1099 bool swap_reg_contains_mark, 1100 Label& done, 1101 Label* slow_case, 1102 BiasedLockingCounters* counters) { 1103 assert(UseBiasedLocking, "why call this otherwise?"); 1104 assert(swap_reg == rax, "swap_reg must be rax for cmpxchgq"); 1105 assert(tmp_reg != noreg, "tmp_reg must be supplied"); 1106 assert_different_registers(lock_reg, obj_reg, swap_reg, tmp_reg); 1107 assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits, "biased locking makes assumptions about bit layout"); 1108 Address mark_addr (obj_reg, oopDesc::mark_offset_in_bytes()); 1109 Address saved_mark_addr(lock_reg, 0); 1110 1111 if (PrintBiasedLockingStatistics && counters == NULL) { 1112 counters = BiasedLocking::counters(); 1113 } 1114 // Biased locking 1115 // See whether the lock is currently biased toward our thread and 1116 // whether the epoch is still valid 1117 // Note that the runtime guarantees sufficient alignment of JavaThread 1118 // pointers to allow age to be placed into low bits 1119 // First check to see whether biasing is even enabled for this object 1120 Label cas_label; 1121 int null_check_offset = -1; 1122 if (!swap_reg_contains_mark) { 1123 null_check_offset = offset(); 1124 movptr(swap_reg, mark_addr); 1125 } 1126 movptr(tmp_reg, swap_reg); 1127 andptr(tmp_reg, markOopDesc::biased_lock_mask_in_place); 1128 cmpptr(tmp_reg, markOopDesc::biased_lock_pattern); 1129 jcc(Assembler::notEqual, cas_label); 1130 // The bias pattern is present in the object's header. Need to check 1131 // whether the bias owner and the epoch are both still current. 1132 #ifndef _LP64 1133 // Note that because there is no current thread register on x86_32 we 1134 // need to store off the mark word we read out of the object to 1135 // avoid reloading it and needing to recheck invariants below. This 1136 // store is unfortunate but it makes the overall code shorter and 1137 // simpler. 1138 movptr(saved_mark_addr, swap_reg); 1139 #endif 1140 if (swap_reg_contains_mark) { 1141 null_check_offset = offset(); 1142 } 1143 load_prototype_header(tmp_reg, obj_reg); 1144 #ifdef _LP64 1145 orptr(tmp_reg, r15_thread); 1146 xorptr(tmp_reg, swap_reg); 1147 Register header_reg = tmp_reg; 1148 #else 1149 xorptr(tmp_reg, swap_reg); 1150 get_thread(swap_reg); 1151 xorptr(swap_reg, tmp_reg); 1152 Register header_reg = swap_reg; 1153 #endif 1154 andptr(header_reg, ~((int) markOopDesc::age_mask_in_place)); 1155 if (counters != NULL) { 1156 cond_inc32(Assembler::zero, 1157 ExternalAddress((address) counters->biased_lock_entry_count_addr())); 1158 } 1159 jcc(Assembler::equal, done); 1160 1161 Label try_revoke_bias; 1162 Label try_rebias; 1163 1164 // At this point we know that the header has the bias pattern and 1165 // that we are not the bias owner in the current epoch. We need to 1166 // figure out more details about the state of the header in order to 1167 // know what operations can be legally performed on the object's 1168 // header. 1169 1170 // If the low three bits in the xor result aren't clear, that means 1171 // the prototype header is no longer biased and we have to revoke 1172 // the bias on this object. 1173 testptr(header_reg, markOopDesc::biased_lock_mask_in_place); 1174 jccb(Assembler::notZero, try_revoke_bias); 1175 1176 // Biasing is still enabled for this data type. See whether the 1177 // epoch of the current bias is still valid, meaning that the epoch 1178 // bits of the mark word are equal to the epoch bits of the 1179 // prototype header. (Note that the prototype header's epoch bits 1180 // only change at a safepoint.) If not, attempt to rebias the object 1181 // toward the current thread. Note that we must be absolutely sure 1182 // that the current epoch is invalid in order to do this because 1183 // otherwise the manipulations it performs on the mark word are 1184 // illegal. 1185 testptr(header_reg, markOopDesc::epoch_mask_in_place); 1186 jccb(Assembler::notZero, try_rebias); 1187 1188 // The epoch of the current bias is still valid but we know nothing 1189 // about the owner; it might be set or it might be clear. Try to 1190 // acquire the bias of the object using an atomic operation. If this 1191 // fails we will go in to the runtime to revoke the object's bias. 1192 // Note that we first construct the presumed unbiased header so we 1193 // don't accidentally blow away another thread's valid bias. 1194 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1195 andptr(swap_reg, 1196 markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place); 1197 #ifdef _LP64 1198 movptr(tmp_reg, swap_reg); 1199 orptr(tmp_reg, r15_thread); 1200 #else 1201 get_thread(tmp_reg); 1202 orptr(tmp_reg, swap_reg); 1203 #endif 1204 if (os::is_MP()) { 1205 lock(); 1206 } 1207 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1208 // If the biasing toward our thread failed, this means that 1209 // another thread succeeded in biasing it toward itself and we 1210 // need to revoke that bias. The revocation will occur in the 1211 // interpreter runtime in the slow case. 1212 if (counters != NULL) { 1213 cond_inc32(Assembler::zero, 1214 ExternalAddress((address) counters->anonymously_biased_lock_entry_count_addr())); 1215 } 1216 if (slow_case != NULL) { 1217 jcc(Assembler::notZero, *slow_case); 1218 } 1219 jmp(done); 1220 1221 bind(try_rebias); 1222 // At this point we know the epoch has expired, meaning that the 1223 // current "bias owner", if any, is actually invalid. Under these 1224 // circumstances _only_, we are allowed to use the current header's 1225 // value as the comparison value when doing the cas to acquire the 1226 // bias in the current epoch. In other words, we allow transfer of 1227 // the bias from one thread to another directly in this situation. 1228 // 1229 // FIXME: due to a lack of registers we currently blow away the age 1230 // bits in this situation. Should attempt to preserve them. 1231 load_prototype_header(tmp_reg, obj_reg); 1232 #ifdef _LP64 1233 orptr(tmp_reg, r15_thread); 1234 #else 1235 get_thread(swap_reg); 1236 orptr(tmp_reg, swap_reg); 1237 movptr(swap_reg, saved_mark_addr); 1238 #endif 1239 if (os::is_MP()) { 1240 lock(); 1241 } 1242 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1243 // If the biasing toward our thread failed, then another thread 1244 // succeeded in biasing it toward itself and we need to revoke that 1245 // bias. The revocation will occur in the runtime in the slow case. 1246 if (counters != NULL) { 1247 cond_inc32(Assembler::zero, 1248 ExternalAddress((address) counters->rebiased_lock_entry_count_addr())); 1249 } 1250 if (slow_case != NULL) { 1251 jcc(Assembler::notZero, *slow_case); 1252 } 1253 jmp(done); 1254 1255 bind(try_revoke_bias); 1256 // The prototype mark in the klass doesn't have the bias bit set any 1257 // more, indicating that objects of this data type are not supposed 1258 // to be biased any more. We are going to try to reset the mark of 1259 // this object to the prototype value and fall through to the 1260 // CAS-based locking scheme. Note that if our CAS fails, it means 1261 // that another thread raced us for the privilege of revoking the 1262 // bias of this particular object, so it's okay to continue in the 1263 // normal locking code. 1264 // 1265 // FIXME: due to a lack of registers we currently blow away the age 1266 // bits in this situation. Should attempt to preserve them. 1267 NOT_LP64( movptr(swap_reg, saved_mark_addr); ) 1268 load_prototype_header(tmp_reg, obj_reg); 1269 if (os::is_MP()) { 1270 lock(); 1271 } 1272 cmpxchgptr(tmp_reg, mark_addr); // compare tmp_reg and swap_reg 1273 // Fall through to the normal CAS-based lock, because no matter what 1274 // the result of the above CAS, some thread must have succeeded in 1275 // removing the bias bit from the object's header. 1276 if (counters != NULL) { 1277 cond_inc32(Assembler::zero, 1278 ExternalAddress((address) counters->revoked_lock_entry_count_addr())); 1279 } 1280 1281 bind(cas_label); 1282 1283 return null_check_offset; 1284 } 1285 1286 void MacroAssembler::biased_locking_exit(Register obj_reg, Register temp_reg, Label& done) { 1287 assert(UseBiasedLocking, "why call this otherwise?"); 1288 1289 // Check for biased locking unlock case, which is a no-op 1290 // Note: we do not have to check the thread ID for two reasons. 1291 // First, the interpreter checks for IllegalMonitorStateException at 1292 // a higher level. Second, if the bias was revoked while we held the 1293 // lock, the object could not be rebiased toward another thread, so 1294 // the bias bit would be clear. 1295 movptr(temp_reg, Address(obj_reg, oopDesc::mark_offset_in_bytes())); 1296 andptr(temp_reg, markOopDesc::biased_lock_mask_in_place); 1297 cmpptr(temp_reg, markOopDesc::biased_lock_pattern); 1298 jcc(Assembler::equal, done); 1299 } 1300 1301 #ifdef COMPILER2 1302 1303 #if INCLUDE_RTM_OPT 1304 1305 // Update rtm_counters based on abort status 1306 // input: abort_status 1307 // rtm_counters (RTMLockingCounters*) 1308 // flags are killed 1309 void MacroAssembler::rtm_counters_update(Register abort_status, Register rtm_counters) { 1310 1311 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abort_count_offset())); 1312 if (PrintPreciseRTMLockingStatistics) { 1313 for (int i = 0; i < RTMLockingCounters::ABORT_STATUS_LIMIT; i++) { 1314 Label check_abort; 1315 testl(abort_status, (1<<i)); 1316 jccb(Assembler::equal, check_abort); 1317 atomic_incptr(Address(rtm_counters, RTMLockingCounters::abortX_count_offset() + (i * sizeof(uintx)))); 1318 bind(check_abort); 1319 } 1320 } 1321 } 1322 1323 // Branch if (random & (count-1) != 0), count is 2^n 1324 // tmp, scr and flags are killed 1325 void MacroAssembler::branch_on_random_using_rdtsc(Register tmp, Register scr, int count, Label& brLabel) { 1326 assert(tmp == rax, ""); 1327 assert(scr == rdx, ""); 1328 rdtsc(); // modifies EDX:EAX 1329 andptr(tmp, count-1); 1330 jccb(Assembler::notZero, brLabel); 1331 } 1332 1333 // Perform abort ratio calculation, set no_rtm bit if high ratio 1334 // input: rtm_counters_Reg (RTMLockingCounters* address) 1335 // tmpReg, rtm_counters_Reg and flags are killed 1336 void MacroAssembler::rtm_abort_ratio_calculation(Register tmpReg, 1337 Register rtm_counters_Reg, 1338 RTMLockingCounters* rtm_counters, 1339 Metadata* method_data) { 1340 Label L_done, L_check_always_rtm1, L_check_always_rtm2; 1341 1342 if (RTMLockingCalculationDelay > 0) { 1343 // Delay calculation 1344 movptr(tmpReg, ExternalAddress((address) RTMLockingCounters::rtm_calculation_flag_addr()), tmpReg); 1345 testptr(tmpReg, tmpReg); 1346 jccb(Assembler::equal, L_done); 1347 } 1348 // Abort ratio calculation only if abort_count > RTMAbortThreshold 1349 // Aborted transactions = abort_count * 100 1350 // All transactions = total_count * RTMTotalCountIncrRate 1351 // Set no_rtm bit if (Aborted transactions >= All transactions * RTMAbortRatio) 1352 1353 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::abort_count_offset())); 1354 cmpptr(tmpReg, RTMAbortThreshold); 1355 jccb(Assembler::below, L_check_always_rtm2); 1356 imulptr(tmpReg, tmpReg, 100); 1357 1358 Register scrReg = rtm_counters_Reg; 1359 movptr(scrReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1360 imulptr(scrReg, scrReg, RTMTotalCountIncrRate); 1361 imulptr(scrReg, scrReg, RTMAbortRatio); 1362 cmpptr(tmpReg, scrReg); 1363 jccb(Assembler::below, L_check_always_rtm1); 1364 if (method_data != NULL) { 1365 // set rtm_state to "no rtm" in MDO 1366 mov_metadata(tmpReg, method_data); 1367 if (os::is_MP()) { 1368 lock(); 1369 } 1370 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), NoRTM); 1371 } 1372 jmpb(L_done); 1373 bind(L_check_always_rtm1); 1374 // Reload RTMLockingCounters* address 1375 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1376 bind(L_check_always_rtm2); 1377 movptr(tmpReg, Address(rtm_counters_Reg, RTMLockingCounters::total_count_offset())); 1378 cmpptr(tmpReg, RTMLockingThreshold / RTMTotalCountIncrRate); 1379 jccb(Assembler::below, L_done); 1380 if (method_data != NULL) { 1381 // set rtm_state to "always rtm" in MDO 1382 mov_metadata(tmpReg, method_data); 1383 if (os::is_MP()) { 1384 lock(); 1385 } 1386 orl(Address(tmpReg, MethodData::rtm_state_offset_in_bytes()), UseRTM); 1387 } 1388 bind(L_done); 1389 } 1390 1391 // Update counters and perform abort ratio calculation 1392 // input: abort_status_Reg 1393 // rtm_counters_Reg, flags are killed 1394 void MacroAssembler::rtm_profiling(Register abort_status_Reg, 1395 Register rtm_counters_Reg, 1396 RTMLockingCounters* rtm_counters, 1397 Metadata* method_data, 1398 bool profile_rtm) { 1399 1400 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1401 // update rtm counters based on rax value at abort 1402 // reads abort_status_Reg, updates flags 1403 lea(rtm_counters_Reg, ExternalAddress((address)rtm_counters)); 1404 rtm_counters_update(abort_status_Reg, rtm_counters_Reg); 1405 if (profile_rtm) { 1406 // Save abort status because abort_status_Reg is used by following code. 1407 if (RTMRetryCount > 0) { 1408 push(abort_status_Reg); 1409 } 1410 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1411 rtm_abort_ratio_calculation(abort_status_Reg, rtm_counters_Reg, rtm_counters, method_data); 1412 // restore abort status 1413 if (RTMRetryCount > 0) { 1414 pop(abort_status_Reg); 1415 } 1416 } 1417 } 1418 1419 // Retry on abort if abort's status is 0x6: can retry (0x2) | memory conflict (0x4) 1420 // inputs: retry_count_Reg 1421 // : abort_status_Reg 1422 // output: retry_count_Reg decremented by 1 1423 // flags are killed 1424 void MacroAssembler::rtm_retry_lock_on_abort(Register retry_count_Reg, Register abort_status_Reg, Label& retryLabel) { 1425 Label doneRetry; 1426 assert(abort_status_Reg == rax, ""); 1427 // The abort reason bits are in eax (see all states in rtmLocking.hpp) 1428 // 0x6 = conflict on which we can retry (0x2) | memory conflict (0x4) 1429 // if reason is in 0x6 and retry count != 0 then retry 1430 andptr(abort_status_Reg, 0x6); 1431 jccb(Assembler::zero, doneRetry); 1432 testl(retry_count_Reg, retry_count_Reg); 1433 jccb(Assembler::zero, doneRetry); 1434 pause(); 1435 decrementl(retry_count_Reg); 1436 jmp(retryLabel); 1437 bind(doneRetry); 1438 } 1439 1440 // Spin and retry if lock is busy, 1441 // inputs: box_Reg (monitor address) 1442 // : retry_count_Reg 1443 // output: retry_count_Reg decremented by 1 1444 // : clear z flag if retry count exceeded 1445 // tmp_Reg, scr_Reg, flags are killed 1446 void MacroAssembler::rtm_retry_lock_on_busy(Register retry_count_Reg, Register box_Reg, 1447 Register tmp_Reg, Register scr_Reg, Label& retryLabel) { 1448 Label SpinLoop, SpinExit, doneRetry; 1449 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1450 1451 testl(retry_count_Reg, retry_count_Reg); 1452 jccb(Assembler::zero, doneRetry); 1453 decrementl(retry_count_Reg); 1454 movptr(scr_Reg, RTMSpinLoopCount); 1455 1456 bind(SpinLoop); 1457 pause(); 1458 decrementl(scr_Reg); 1459 jccb(Assembler::lessEqual, SpinExit); 1460 movptr(tmp_Reg, Address(box_Reg, owner_offset)); 1461 testptr(tmp_Reg, tmp_Reg); 1462 jccb(Assembler::notZero, SpinLoop); 1463 1464 bind(SpinExit); 1465 jmp(retryLabel); 1466 bind(doneRetry); 1467 incrementl(retry_count_Reg); // clear z flag 1468 } 1469 1470 // Use RTM for normal stack locks 1471 // Input: objReg (object to lock) 1472 void MacroAssembler::rtm_stack_locking(Register objReg, Register tmpReg, Register scrReg, 1473 Register retry_on_abort_count_Reg, 1474 RTMLockingCounters* stack_rtm_counters, 1475 Metadata* method_data, bool profile_rtm, 1476 Label& DONE_LABEL, Label& IsInflated) { 1477 assert(UseRTMForStackLocks, "why call this otherwise?"); 1478 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1479 assert(tmpReg == rax, ""); 1480 assert(scrReg == rdx, ""); 1481 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1482 1483 if (RTMRetryCount > 0) { 1484 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1485 bind(L_rtm_retry); 1486 } 1487 movptr(tmpReg, Address(objReg, 0)); 1488 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1489 jcc(Assembler::notZero, IsInflated); 1490 1491 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1492 Label L_noincrement; 1493 if (RTMTotalCountIncrRate > 1) { 1494 // tmpReg, scrReg and flags are killed 1495 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1496 } 1497 assert(stack_rtm_counters != NULL, "should not be NULL when profiling RTM"); 1498 atomic_incptr(ExternalAddress((address)stack_rtm_counters->total_count_addr()), scrReg); 1499 bind(L_noincrement); 1500 } 1501 xbegin(L_on_abort); 1502 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1503 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1504 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1505 jcc(Assembler::equal, DONE_LABEL); // all done if unlocked 1506 1507 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1508 if (UseRTMXendForLockBusy) { 1509 xend(); 1510 movptr(abort_status_Reg, 0x2); // Set the abort status to 2 (so we can retry) 1511 jmp(L_decrement_retry); 1512 } 1513 else { 1514 xabort(0); 1515 } 1516 bind(L_on_abort); 1517 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1518 rtm_profiling(abort_status_Reg, scrReg, stack_rtm_counters, method_data, profile_rtm); 1519 } 1520 bind(L_decrement_retry); 1521 if (RTMRetryCount > 0) { 1522 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1523 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1524 } 1525 } 1526 1527 // Use RTM for inflating locks 1528 // inputs: objReg (object to lock) 1529 // boxReg (on-stack box address (displaced header location) - KILLED) 1530 // tmpReg (ObjectMonitor address + markOopDesc::monitor_value) 1531 void MacroAssembler::rtm_inflated_locking(Register objReg, Register boxReg, Register tmpReg, 1532 Register scrReg, Register retry_on_busy_count_Reg, 1533 Register retry_on_abort_count_Reg, 1534 RTMLockingCounters* rtm_counters, 1535 Metadata* method_data, bool profile_rtm, 1536 Label& DONE_LABEL) { 1537 assert(UseRTMLocking, "why call this otherwise?"); 1538 assert(tmpReg == rax, ""); 1539 assert(scrReg == rdx, ""); 1540 Label L_rtm_retry, L_decrement_retry, L_on_abort; 1541 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 1542 1543 // Without cast to int32_t a movptr will destroy r10 which is typically obj 1544 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1545 movptr(boxReg, tmpReg); // Save ObjectMonitor address 1546 1547 if (RTMRetryCount > 0) { 1548 movl(retry_on_busy_count_Reg, RTMRetryCount); // Retry on lock busy 1549 movl(retry_on_abort_count_Reg, RTMRetryCount); // Retry on abort 1550 bind(L_rtm_retry); 1551 } 1552 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1553 Label L_noincrement; 1554 if (RTMTotalCountIncrRate > 1) { 1555 // tmpReg, scrReg and flags are killed 1556 branch_on_random_using_rdtsc(tmpReg, scrReg, (int)RTMTotalCountIncrRate, L_noincrement); 1557 } 1558 assert(rtm_counters != NULL, "should not be NULL when profiling RTM"); 1559 atomic_incptr(ExternalAddress((address)rtm_counters->total_count_addr()), scrReg); 1560 bind(L_noincrement); 1561 } 1562 xbegin(L_on_abort); 1563 movptr(tmpReg, Address(objReg, 0)); 1564 movptr(tmpReg, Address(tmpReg, owner_offset)); 1565 testptr(tmpReg, tmpReg); 1566 jcc(Assembler::zero, DONE_LABEL); 1567 if (UseRTMXendForLockBusy) { 1568 xend(); 1569 jmp(L_decrement_retry); 1570 } 1571 else { 1572 xabort(0); 1573 } 1574 bind(L_on_abort); 1575 Register abort_status_Reg = tmpReg; // status of abort is stored in RAX 1576 if (PrintPreciseRTMLockingStatistics || profile_rtm) { 1577 rtm_profiling(abort_status_Reg, scrReg, rtm_counters, method_data, profile_rtm); 1578 } 1579 if (RTMRetryCount > 0) { 1580 // retry on lock abort if abort status is 'can retry' (0x2) or 'memory conflict' (0x4) 1581 rtm_retry_lock_on_abort(retry_on_abort_count_Reg, abort_status_Reg, L_rtm_retry); 1582 } 1583 1584 movptr(tmpReg, Address(boxReg, owner_offset)) ; 1585 testptr(tmpReg, tmpReg) ; 1586 jccb(Assembler::notZero, L_decrement_retry) ; 1587 1588 // Appears unlocked - try to swing _owner from null to non-null. 1589 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1590 #ifdef _LP64 1591 Register threadReg = r15_thread; 1592 #else 1593 get_thread(scrReg); 1594 Register threadReg = scrReg; 1595 #endif 1596 if (os::is_MP()) { 1597 lock(); 1598 } 1599 cmpxchgptr(threadReg, Address(boxReg, owner_offset)); // Updates tmpReg 1600 1601 if (RTMRetryCount > 0) { 1602 // success done else retry 1603 jccb(Assembler::equal, DONE_LABEL) ; 1604 bind(L_decrement_retry); 1605 // Spin and retry if lock is busy. 1606 rtm_retry_lock_on_busy(retry_on_busy_count_Reg, boxReg, tmpReg, scrReg, L_rtm_retry); 1607 } 1608 else { 1609 bind(L_decrement_retry); 1610 } 1611 } 1612 1613 #endif // INCLUDE_RTM_OPT 1614 1615 // Fast_Lock and Fast_Unlock used by C2 1616 1617 // Because the transitions from emitted code to the runtime 1618 // monitorenter/exit helper stubs are so slow it's critical that 1619 // we inline both the stack-locking fast-path and the inflated fast path. 1620 // 1621 // See also: cmpFastLock and cmpFastUnlock. 1622 // 1623 // What follows is a specialized inline transliteration of the code 1624 // in slow_enter() and slow_exit(). If we're concerned about I$ bloat 1625 // another option would be to emit TrySlowEnter and TrySlowExit methods 1626 // at startup-time. These methods would accept arguments as 1627 // (rax,=Obj, rbx=Self, rcx=box, rdx=Scratch) and return success-failure 1628 // indications in the icc.ZFlag. Fast_Lock and Fast_Unlock would simply 1629 // marshal the arguments and emit calls to TrySlowEnter and TrySlowExit. 1630 // In practice, however, the # of lock sites is bounded and is usually small. 1631 // Besides the call overhead, TrySlowEnter and TrySlowExit might suffer 1632 // if the processor uses simple bimodal branch predictors keyed by EIP 1633 // Since the helper routines would be called from multiple synchronization 1634 // sites. 1635 // 1636 // An even better approach would be write "MonitorEnter()" and "MonitorExit()" 1637 // in java - using j.u.c and unsafe - and just bind the lock and unlock sites 1638 // to those specialized methods. That'd give us a mostly platform-independent 1639 // implementation that the JITs could optimize and inline at their pleasure. 1640 // Done correctly, the only time we'd need to cross to native could would be 1641 // to park() or unpark() threads. We'd also need a few more unsafe operators 1642 // to (a) prevent compiler-JIT reordering of non-volatile accesses, and 1643 // (b) explicit barriers or fence operations. 1644 // 1645 // TODO: 1646 // 1647 // * Arrange for C2 to pass "Self" into Fast_Lock and Fast_Unlock in one of the registers (scr). 1648 // This avoids manifesting the Self pointer in the Fast_Lock and Fast_Unlock terminals. 1649 // Given TLAB allocation, Self is usually manifested in a register, so passing it into 1650 // the lock operators would typically be faster than reifying Self. 1651 // 1652 // * Ideally I'd define the primitives as: 1653 // fast_lock (nax Obj, nax box, EAX tmp, nax scr) where box, tmp and scr are KILLED. 1654 // fast_unlock (nax Obj, EAX box, nax tmp) where box and tmp are KILLED 1655 // Unfortunately ADLC bugs prevent us from expressing the ideal form. 1656 // Instead, we're stuck with a rather awkward and brittle register assignments below. 1657 // Furthermore the register assignments are overconstrained, possibly resulting in 1658 // sub-optimal code near the synchronization site. 1659 // 1660 // * Eliminate the sp-proximity tests and just use "== Self" tests instead. 1661 // Alternately, use a better sp-proximity test. 1662 // 1663 // * Currently ObjectMonitor._Owner can hold either an sp value or a (THREAD *) value. 1664 // Either one is sufficient to uniquely identify a thread. 1665 // TODO: eliminate use of sp in _owner and use get_thread(tr) instead. 1666 // 1667 // * Intrinsify notify() and notifyAll() for the common cases where the 1668 // object is locked by the calling thread but the waitlist is empty. 1669 // avoid the expensive JNI call to JVM_Notify() and JVM_NotifyAll(). 1670 // 1671 // * use jccb and jmpb instead of jcc and jmp to improve code density. 1672 // But beware of excessive branch density on AMD Opterons. 1673 // 1674 // * Both Fast_Lock and Fast_Unlock set the ICC.ZF to indicate success 1675 // or failure of the fast-path. If the fast-path fails then we pass 1676 // control to the slow-path, typically in C. In Fast_Lock and 1677 // Fast_Unlock we often branch to DONE_LABEL, just to find that C2 1678 // will emit a conditional branch immediately after the node. 1679 // So we have branches to branches and lots of ICC.ZF games. 1680 // Instead, it might be better to have C2 pass a "FailureLabel" 1681 // into Fast_Lock and Fast_Unlock. In the case of success, control 1682 // will drop through the node. ICC.ZF is undefined at exit. 1683 // In the case of failure, the node will branch directly to the 1684 // FailureLabel 1685 1686 1687 // obj: object to lock 1688 // box: on-stack box address (displaced header location) - KILLED 1689 // rax,: tmp -- KILLED 1690 // scr: tmp -- KILLED 1691 void MacroAssembler::fast_lock(Register objReg, Register boxReg, Register tmpReg, 1692 Register scrReg, Register cx1Reg, Register cx2Reg, 1693 BiasedLockingCounters* counters, 1694 RTMLockingCounters* rtm_counters, 1695 RTMLockingCounters* stack_rtm_counters, 1696 Metadata* method_data, 1697 bool use_rtm, bool profile_rtm) { 1698 // Ensure the register assignents are disjoint 1699 assert(tmpReg == rax, ""); 1700 1701 if (use_rtm) { 1702 assert_different_registers(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg); 1703 } else { 1704 assert(cx1Reg == noreg, ""); 1705 assert(cx2Reg == noreg, ""); 1706 assert_different_registers(objReg, boxReg, tmpReg, scrReg); 1707 } 1708 1709 if (counters != NULL) { 1710 atomic_incl(ExternalAddress((address)counters->total_entry_count_addr()), scrReg); 1711 } 1712 if (EmitSync & 1) { 1713 // set box->dhw = markOopDesc::unused_mark() 1714 // Force all sync thru slow-path: slow_enter() and slow_exit() 1715 movptr (Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1716 cmpptr (rsp, (int32_t)NULL_WORD); 1717 } else { 1718 // Possible cases that we'll encounter in fast_lock 1719 // ------------------------------------------------ 1720 // * Inflated 1721 // -- unlocked 1722 // -- Locked 1723 // = by self 1724 // = by other 1725 // * biased 1726 // -- by Self 1727 // -- by other 1728 // * neutral 1729 // * stack-locked 1730 // -- by self 1731 // = sp-proximity test hits 1732 // = sp-proximity test generates false-negative 1733 // -- by other 1734 // 1735 1736 Label IsInflated, DONE_LABEL; 1737 1738 // it's stack-locked, biased or neutral 1739 // TODO: optimize away redundant LDs of obj->mark and improve the markword triage 1740 // order to reduce the number of conditional branches in the most common cases. 1741 // Beware -- there's a subtle invariant that fetch of the markword 1742 // at [FETCH], below, will never observe a biased encoding (*101b). 1743 // If this invariant is not held we risk exclusion (safety) failure. 1744 if (UseBiasedLocking && !UseOptoBiasInlining) { 1745 biased_locking_enter(boxReg, objReg, tmpReg, scrReg, false, DONE_LABEL, NULL, counters); 1746 } 1747 1748 #if INCLUDE_RTM_OPT 1749 if (UseRTMForStackLocks && use_rtm) { 1750 rtm_stack_locking(objReg, tmpReg, scrReg, cx2Reg, 1751 stack_rtm_counters, method_data, profile_rtm, 1752 DONE_LABEL, IsInflated); 1753 } 1754 #endif // INCLUDE_RTM_OPT 1755 1756 movptr(tmpReg, Address(objReg, 0)); // [FETCH] 1757 testptr(tmpReg, markOopDesc::monitor_value); // inflated vs stack-locked|neutral|biased 1758 jccb(Assembler::notZero, IsInflated); 1759 1760 // Attempt stack-locking ... 1761 orptr (tmpReg, markOopDesc::unlocked_value); 1762 movptr(Address(boxReg, 0), tmpReg); // Anticipate successful CAS 1763 if (os::is_MP()) { 1764 lock(); 1765 } 1766 cmpxchgptr(boxReg, Address(objReg, 0)); // Updates tmpReg 1767 if (counters != NULL) { 1768 cond_inc32(Assembler::equal, 1769 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1770 } 1771 jcc(Assembler::equal, DONE_LABEL); // Success 1772 1773 // Recursive locking. 1774 // The object is stack-locked: markword contains stack pointer to BasicLock. 1775 // Locked by current thread if difference with current SP is less than one page. 1776 subptr(tmpReg, rsp); 1777 // Next instruction set ZFlag == 1 (Success) if difference is less then one page. 1778 andptr(tmpReg, (int32_t) (NOT_LP64(0xFFFFF003) LP64_ONLY(7 - os::vm_page_size())) ); 1779 movptr(Address(boxReg, 0), tmpReg); 1780 if (counters != NULL) { 1781 cond_inc32(Assembler::equal, 1782 ExternalAddress((address)counters->fast_path_entry_count_addr())); 1783 } 1784 jmp(DONE_LABEL); 1785 1786 bind(IsInflated); 1787 // The object is inflated. tmpReg contains pointer to ObjectMonitor* + markOopDesc::monitor_value 1788 1789 #if INCLUDE_RTM_OPT 1790 // Use the same RTM locking code in 32- and 64-bit VM. 1791 if (use_rtm) { 1792 rtm_inflated_locking(objReg, boxReg, tmpReg, scrReg, cx1Reg, cx2Reg, 1793 rtm_counters, method_data, profile_rtm, DONE_LABEL); 1794 } else { 1795 #endif // INCLUDE_RTM_OPT 1796 1797 #ifndef _LP64 1798 // The object is inflated. 1799 1800 // boxReg refers to the on-stack BasicLock in the current frame. 1801 // We'd like to write: 1802 // set box->_displaced_header = markOopDesc::unused_mark(). Any non-0 value suffices. 1803 // This is convenient but results a ST-before-CAS penalty. The following CAS suffers 1804 // additional latency as we have another ST in the store buffer that must drain. 1805 1806 if (EmitSync & 8192) { 1807 movptr(Address(boxReg, 0), 3); // results in ST-before-CAS penalty 1808 get_thread (scrReg); 1809 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1810 movptr(tmpReg, NULL_WORD); // consider: xor vs mov 1811 if (os::is_MP()) { 1812 lock(); 1813 } 1814 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1815 } else 1816 if ((EmitSync & 128) == 0) { // avoid ST-before-CAS 1817 // register juggle because we need tmpReg for cmpxchgptr below 1818 movptr(scrReg, boxReg); 1819 movptr(boxReg, tmpReg); // consider: LEA box, [tmp-2] 1820 1821 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1822 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1823 // prefetchw [eax + Offset(_owner)-2] 1824 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1825 } 1826 1827 if ((EmitSync & 64) == 0) { 1828 // Optimistic form: consider XORL tmpReg,tmpReg 1829 movptr(tmpReg, NULL_WORD); 1830 } else { 1831 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1832 // Test-And-CAS instead of CAS 1833 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1834 testptr(tmpReg, tmpReg); // Locked ? 1835 jccb (Assembler::notZero, DONE_LABEL); 1836 } 1837 1838 // Appears unlocked - try to swing _owner from null to non-null. 1839 // Ideally, I'd manifest "Self" with get_thread and then attempt 1840 // to CAS the register containing Self into m->Owner. 1841 // But we don't have enough registers, so instead we can either try to CAS 1842 // rsp or the address of the box (in scr) into &m->owner. If the CAS succeeds 1843 // we later store "Self" into m->Owner. Transiently storing a stack address 1844 // (rsp or the address of the box) into m->owner is harmless. 1845 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1846 if (os::is_MP()) { 1847 lock(); 1848 } 1849 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1850 movptr(Address(scrReg, 0), 3); // box->_displaced_header = 3 1851 // If we weren't able to swing _owner from NULL to the BasicLock 1852 // then take the slow path. 1853 jccb (Assembler::notZero, DONE_LABEL); 1854 // update _owner from BasicLock to thread 1855 get_thread (scrReg); // beware: clobbers ICCs 1856 movptr(Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), scrReg); 1857 xorptr(boxReg, boxReg); // set icc.ZFlag = 1 to indicate success 1858 1859 // If the CAS fails we can either retry or pass control to the slow-path. 1860 // We use the latter tactic. 1861 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1862 // If the CAS was successful ... 1863 // Self has acquired the lock 1864 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1865 // Intentional fall-through into DONE_LABEL ... 1866 } else { 1867 movptr(Address(boxReg, 0), intptr_t(markOopDesc::unused_mark())); // results in ST-before-CAS penalty 1868 movptr(boxReg, tmpReg); 1869 1870 // Using a prefetchw helps avoid later RTS->RTO upgrades and cache probes 1871 if ((EmitSync & 2048) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 1872 // prefetchw [eax + Offset(_owner)-2] 1873 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1874 } 1875 1876 if ((EmitSync & 64) == 0) { 1877 // Optimistic form 1878 xorptr (tmpReg, tmpReg); 1879 } else { 1880 // Can suffer RTS->RTO upgrades on shared or cold $ lines 1881 movptr(tmpReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); // rax, = m->_owner 1882 testptr(tmpReg, tmpReg); // Locked ? 1883 jccb (Assembler::notZero, DONE_LABEL); 1884 } 1885 1886 // Appears unlocked - try to swing _owner from null to non-null. 1887 // Use either "Self" (in scr) or rsp as thread identity in _owner. 1888 // Invariant: tmpReg == 0. tmpReg is EAX which is the implicit cmpxchg comparand. 1889 get_thread (scrReg); 1890 if (os::is_MP()) { 1891 lock(); 1892 } 1893 cmpxchgptr(scrReg, Address(boxReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1894 1895 // If the CAS fails we can either retry or pass control to the slow-path. 1896 // We use the latter tactic. 1897 // Pass the CAS result in the icc.ZFlag into DONE_LABEL 1898 // If the CAS was successful ... 1899 // Self has acquired the lock 1900 // Invariant: m->_recursions should already be 0, so we don't need to explicitly set it. 1901 // Intentional fall-through into DONE_LABEL ... 1902 } 1903 #else // _LP64 1904 // It's inflated 1905 movq(scrReg, tmpReg); 1906 xorq(tmpReg, tmpReg); 1907 1908 if (os::is_MP()) { 1909 lock(); 1910 } 1911 cmpxchgptr(r15_thread, Address(scrReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 1912 // Unconditionally set box->_displaced_header = markOopDesc::unused_mark(). 1913 // Without cast to int32_t movptr will destroy r10 which is typically obj. 1914 movptr(Address(boxReg, 0), (int32_t)intptr_t(markOopDesc::unused_mark())); 1915 // Intentional fall-through into DONE_LABEL ... 1916 // Propagate ICC.ZF from CAS above into DONE_LABEL. 1917 #endif // _LP64 1918 #if INCLUDE_RTM_OPT 1919 } // use_rtm() 1920 #endif 1921 // DONE_LABEL is a hot target - we'd really like to place it at the 1922 // start of cache line by padding with NOPs. 1923 // See the AMD and Intel software optimization manuals for the 1924 // most efficient "long" NOP encodings. 1925 // Unfortunately none of our alignment mechanisms suffice. 1926 bind(DONE_LABEL); 1927 1928 // At DONE_LABEL the icc ZFlag is set as follows ... 1929 // Fast_Unlock uses the same protocol. 1930 // ZFlag == 1 -> Success 1931 // ZFlag == 0 -> Failure - force control through the slow-path 1932 } 1933 } 1934 1935 // obj: object to unlock 1936 // box: box address (displaced header location), killed. Must be EAX. 1937 // tmp: killed, cannot be obj nor box. 1938 // 1939 // Some commentary on balanced locking: 1940 // 1941 // Fast_Lock and Fast_Unlock are emitted only for provably balanced lock sites. 1942 // Methods that don't have provably balanced locking are forced to run in the 1943 // interpreter - such methods won't be compiled to use fast_lock and fast_unlock. 1944 // The interpreter provides two properties: 1945 // I1: At return-time the interpreter automatically and quietly unlocks any 1946 // objects acquired the current activation (frame). Recall that the 1947 // interpreter maintains an on-stack list of locks currently held by 1948 // a frame. 1949 // I2: If a method attempts to unlock an object that is not held by the 1950 // the frame the interpreter throws IMSX. 1951 // 1952 // Lets say A(), which has provably balanced locking, acquires O and then calls B(). 1953 // B() doesn't have provably balanced locking so it runs in the interpreter. 1954 // Control returns to A() and A() unlocks O. By I1 and I2, above, we know that O 1955 // is still locked by A(). 1956 // 1957 // The only other source of unbalanced locking would be JNI. The "Java Native Interface: 1958 // Programmer's Guide and Specification" claims that an object locked by jni_monitorenter 1959 // should not be unlocked by "normal" java-level locking and vice-versa. The specification 1960 // doesn't specify what will occur if a program engages in such mixed-mode locking, however. 1961 // Arguably given that the spec legislates the JNI case as undefined our implementation 1962 // could reasonably *avoid* checking owner in Fast_Unlock(). 1963 // In the interest of performance we elide m->Owner==Self check in unlock. 1964 // A perfectly viable alternative is to elide the owner check except when 1965 // Xcheck:jni is enabled. 1966 1967 void MacroAssembler::fast_unlock(Register objReg, Register boxReg, Register tmpReg, bool use_rtm) { 1968 assert(boxReg == rax, ""); 1969 assert_different_registers(objReg, boxReg, tmpReg); 1970 1971 if (EmitSync & 4) { 1972 // Disable - inhibit all inlining. Force control through the slow-path 1973 cmpptr (rsp, 0); 1974 } else { 1975 Label DONE_LABEL, Stacked, CheckSucc; 1976 1977 // Critically, the biased locking test must have precedence over 1978 // and appear before the (box->dhw == 0) recursive stack-lock test. 1979 if (UseBiasedLocking && !UseOptoBiasInlining) { 1980 biased_locking_exit(objReg, tmpReg, DONE_LABEL); 1981 } 1982 1983 #if INCLUDE_RTM_OPT 1984 if (UseRTMForStackLocks && use_rtm) { 1985 assert(!UseBiasedLocking, "Biased locking is not supported with RTM locking"); 1986 Label L_regular_unlock; 1987 movptr(tmpReg, Address(objReg, 0)); // fetch markword 1988 andptr(tmpReg, markOopDesc::biased_lock_mask_in_place); // look at 3 lock bits 1989 cmpptr(tmpReg, markOopDesc::unlocked_value); // bits = 001 unlocked 1990 jccb(Assembler::notEqual, L_regular_unlock); // if !HLE RegularLock 1991 xend(); // otherwise end... 1992 jmp(DONE_LABEL); // ... and we're done 1993 bind(L_regular_unlock); 1994 } 1995 #endif 1996 1997 cmpptr(Address(boxReg, 0), (int32_t)NULL_WORD); // Examine the displaced header 1998 jcc (Assembler::zero, DONE_LABEL); // 0 indicates recursive stack-lock 1999 movptr(tmpReg, Address(objReg, 0)); // Examine the object's markword 2000 testptr(tmpReg, markOopDesc::monitor_value); // Inflated? 2001 jccb (Assembler::zero, Stacked); 2002 2003 // It's inflated. 2004 #if INCLUDE_RTM_OPT 2005 if (use_rtm) { 2006 Label L_regular_inflated_unlock; 2007 int owner_offset = OM_OFFSET_NO_MONITOR_VALUE_TAG(owner); 2008 movptr(boxReg, Address(tmpReg, owner_offset)); 2009 testptr(boxReg, boxReg); 2010 jccb(Assembler::notZero, L_regular_inflated_unlock); 2011 xend(); 2012 jmpb(DONE_LABEL); 2013 bind(L_regular_inflated_unlock); 2014 } 2015 #endif 2016 2017 // Despite our balanced locking property we still check that m->_owner == Self 2018 // as java routines or native JNI code called by this thread might 2019 // have released the lock. 2020 // Refer to the comments in synchronizer.cpp for how we might encode extra 2021 // state in _succ so we can avoid fetching EntryList|cxq. 2022 // 2023 // I'd like to add more cases in fast_lock() and fast_unlock() -- 2024 // such as recursive enter and exit -- but we have to be wary of 2025 // I$ bloat, T$ effects and BP$ effects. 2026 // 2027 // If there's no contention try a 1-0 exit. That is, exit without 2028 // a costly MEMBAR or CAS. See synchronizer.cpp for details on how 2029 // we detect and recover from the race that the 1-0 exit admits. 2030 // 2031 // Conceptually Fast_Unlock() must execute a STST|LDST "release" barrier 2032 // before it STs null into _owner, releasing the lock. Updates 2033 // to data protected by the critical section must be visible before 2034 // we drop the lock (and thus before any other thread could acquire 2035 // the lock and observe the fields protected by the lock). 2036 // IA32's memory-model is SPO, so STs are ordered with respect to 2037 // each other and there's no need for an explicit barrier (fence). 2038 // See also http://gee.cs.oswego.edu/dl/jmm/cookbook.html. 2039 #ifndef _LP64 2040 get_thread (boxReg); 2041 if ((EmitSync & 4096) && VM_Version::supports_3dnow_prefetch() && os::is_MP()) { 2042 // prefetchw [ebx + Offset(_owner)-2] 2043 prefetchw(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2044 } 2045 2046 // Note that we could employ various encoding schemes to reduce 2047 // the number of loads below (currently 4) to just 2 or 3. 2048 // Refer to the comments in synchronizer.cpp. 2049 // In practice the chain of fetches doesn't seem to impact performance, however. 2050 xorptr(boxReg, boxReg); 2051 if ((EmitSync & 65536) == 0 && (EmitSync & 256)) { 2052 // Attempt to reduce branch density - AMD's branch predictor. 2053 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2054 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2055 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2056 jccb (Assembler::notZero, DONE_LABEL); 2057 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2058 jmpb (DONE_LABEL); 2059 } else { 2060 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2061 jccb (Assembler::notZero, DONE_LABEL); 2062 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2063 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2064 jccb (Assembler::notZero, CheckSucc); 2065 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2066 jmpb (DONE_LABEL); 2067 } 2068 2069 // The Following code fragment (EmitSync & 65536) improves the performance of 2070 // contended applications and contended synchronization microbenchmarks. 2071 // Unfortunately the emission of the code - even though not executed - causes regressions 2072 // in scimark and jetstream, evidently because of $ effects. Replacing the code 2073 // with an equal number of never-executed NOPs results in the same regression. 2074 // We leave it off by default. 2075 2076 if ((EmitSync & 65536) != 0) { 2077 Label LSuccess, LGoSlowPath ; 2078 2079 bind (CheckSucc); 2080 2081 // Optional pre-test ... it's safe to elide this 2082 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2083 jccb(Assembler::zero, LGoSlowPath); 2084 2085 // We have a classic Dekker-style idiom: 2086 // ST m->_owner = 0 ; MEMBAR; LD m->_succ 2087 // There are a number of ways to implement the barrier: 2088 // (1) lock:andl &m->_owner, 0 2089 // is fast, but mask doesn't currently support the "ANDL M,IMM32" form. 2090 // LOCK: ANDL [ebx+Offset(_Owner)-2], 0 2091 // Encodes as 81 31 OFF32 IMM32 or 83 63 OFF8 IMM8 2092 // (2) If supported, an explicit MFENCE is appealing. 2093 // In older IA32 processors MFENCE is slower than lock:add or xchg 2094 // particularly if the write-buffer is full as might be the case if 2095 // if stores closely precede the fence or fence-equivalent instruction. 2096 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2097 // as the situation has changed with Nehalem and Shanghai. 2098 // (3) In lieu of an explicit fence, use lock:addl to the top-of-stack 2099 // The $lines underlying the top-of-stack should be in M-state. 2100 // The locked add instruction is serializing, of course. 2101 // (4) Use xchg, which is serializing 2102 // mov boxReg, 0; xchgl boxReg, [tmpReg + Offset(_owner)-2] also works 2103 // (5) ST m->_owner = 0 and then execute lock:orl &m->_succ, 0. 2104 // The integer condition codes will tell us if succ was 0. 2105 // Since _succ and _owner should reside in the same $line and 2106 // we just stored into _owner, it's likely that the $line 2107 // remains in M-state for the lock:orl. 2108 // 2109 // We currently use (3), although it's likely that switching to (2) 2110 // is correct for the future. 2111 2112 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), NULL_WORD); 2113 if (os::is_MP()) { 2114 lock(); addptr(Address(rsp, 0), 0); 2115 } 2116 // Ratify _succ remains non-null 2117 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), 0); 2118 jccb (Assembler::notZero, LSuccess); 2119 2120 xorptr(boxReg, boxReg); // box is really EAX 2121 if (os::is_MP()) { lock(); } 2122 cmpxchgptr(rsp, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2123 // There's no successor so we tried to regrab the lock with the 2124 // placeholder value. If that didn't work, then another thread 2125 // grabbed the lock so we're done (and exit was a success). 2126 jccb (Assembler::notEqual, LSuccess); 2127 // Since we're low on registers we installed rsp as a placeholding in _owner. 2128 // Now install Self over rsp. This is safe as we're transitioning from 2129 // non-null to non=null 2130 get_thread (boxReg); 2131 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), boxReg); 2132 // Intentional fall-through into LGoSlowPath ... 2133 2134 bind (LGoSlowPath); 2135 orptr(boxReg, 1); // set ICC.ZF=0 to indicate failure 2136 jmpb (DONE_LABEL); 2137 2138 bind (LSuccess); 2139 xorptr(boxReg, boxReg); // set ICC.ZF=1 to indicate success 2140 jmpb (DONE_LABEL); 2141 } 2142 2143 bind (Stacked); 2144 // It's not inflated and it's not recursively stack-locked and it's not biased. 2145 // It must be stack-locked. 2146 // Try to reset the header to displaced header. 2147 // The "box" value on the stack is stable, so we can reload 2148 // and be assured we observe the same value as above. 2149 movptr(tmpReg, Address(boxReg, 0)); 2150 if (os::is_MP()) { 2151 lock(); 2152 } 2153 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2154 // Intention fall-thru into DONE_LABEL 2155 2156 // DONE_LABEL is a hot target - we'd really like to place it at the 2157 // start of cache line by padding with NOPs. 2158 // See the AMD and Intel software optimization manuals for the 2159 // most efficient "long" NOP encodings. 2160 // Unfortunately none of our alignment mechanisms suffice. 2161 if ((EmitSync & 65536) == 0) { 2162 bind (CheckSucc); 2163 } 2164 #else // _LP64 2165 // It's inflated 2166 if (EmitSync & 1024) { 2167 // Emit code to check that _owner == Self 2168 // We could fold the _owner test into subsequent code more efficiently 2169 // than using a stand-alone check, but since _owner checking is off by 2170 // default we don't bother. We also might consider predicating the 2171 // _owner==Self check on Xcheck:jni or running on a debug build. 2172 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2173 xorptr(boxReg, r15_thread); 2174 } else { 2175 xorptr(boxReg, boxReg); 2176 } 2177 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions))); 2178 jccb (Assembler::notZero, DONE_LABEL); 2179 movptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq))); 2180 orptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList))); 2181 jccb (Assembler::notZero, CheckSucc); 2182 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2183 jmpb (DONE_LABEL); 2184 2185 if ((EmitSync & 65536) == 0) { 2186 // Try to avoid passing control into the slow_path ... 2187 Label LSuccess, LGoSlowPath ; 2188 bind (CheckSucc); 2189 2190 // The following optional optimization can be elided if necessary 2191 // Effectively: if (succ == null) goto SlowPath 2192 // The code reduces the window for a race, however, 2193 // and thus benefits performance. 2194 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2195 jccb (Assembler::zero, LGoSlowPath); 2196 2197 if ((EmitSync & 16) && os::is_MP()) { 2198 orptr(boxReg, boxReg); 2199 xchgptr(boxReg, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2200 } else { 2201 movptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)), (int32_t)NULL_WORD); 2202 if (os::is_MP()) { 2203 // Memory barrier/fence 2204 // Dekker pivot point -- fulcrum : ST Owner; MEMBAR; LD Succ 2205 // Instead of MFENCE we use a dummy locked add of 0 to the top-of-stack. 2206 // This is faster on Nehalem and AMD Shanghai/Barcelona. 2207 // See https://blogs.oracle.com/dave/entry/instruction_selection_for_volatile_fences 2208 // We might also restructure (ST Owner=0;barrier;LD _Succ) to 2209 // (mov box,0; xchgq box, &m->Owner; LD _succ) . 2210 lock(); addl(Address(rsp, 0), 0); 2211 } 2212 } 2213 cmpptr(Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(succ)), (int32_t)NULL_WORD); 2214 jccb (Assembler::notZero, LSuccess); 2215 2216 // Rare inopportune interleaving - race. 2217 // The successor vanished in the small window above. 2218 // The lock is contended -- (cxq|EntryList) != null -- and there's no apparent successor. 2219 // We need to ensure progress and succession. 2220 // Try to reacquire the lock. 2221 // If that fails then the new owner is responsible for succession and this 2222 // thread needs to take no further action and can exit via the fast path (success). 2223 // If the re-acquire succeeds then pass control into the slow path. 2224 // As implemented, this latter mode is horrible because we generated more 2225 // coherence traffic on the lock *and* artifically extended the critical section 2226 // length while by virtue of passing control into the slow path. 2227 2228 // box is really RAX -- the following CMPXCHG depends on that binding 2229 // cmpxchg R,[M] is equivalent to rax = CAS(M,rax,R) 2230 movptr(boxReg, (int32_t)NULL_WORD); 2231 if (os::is_MP()) { lock(); } 2232 cmpxchgptr(r15_thread, Address(tmpReg, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner))); 2233 // There's no successor so we tried to regrab the lock. 2234 // If that didn't work, then another thread grabbed the 2235 // lock so we're done (and exit was a success). 2236 jccb (Assembler::notEqual, LSuccess); 2237 // Intentional fall-through into slow-path 2238 2239 bind (LGoSlowPath); 2240 orl (boxReg, 1); // set ICC.ZF=0 to indicate failure 2241 jmpb (DONE_LABEL); 2242 2243 bind (LSuccess); 2244 testl (boxReg, 0); // set ICC.ZF=1 to indicate success 2245 jmpb (DONE_LABEL); 2246 } 2247 2248 bind (Stacked); 2249 movptr(tmpReg, Address (boxReg, 0)); // re-fetch 2250 if (os::is_MP()) { lock(); } 2251 cmpxchgptr(tmpReg, Address(objReg, 0)); // Uses RAX which is box 2252 2253 if (EmitSync & 65536) { 2254 bind (CheckSucc); 2255 } 2256 #endif 2257 bind(DONE_LABEL); 2258 } 2259 } 2260 #endif // COMPILER2 2261 2262 void MacroAssembler::c2bool(Register x) { 2263 // implements x == 0 ? 0 : 1 2264 // note: must only look at least-significant byte of x 2265 // since C-style booleans are stored in one byte 2266 // only! (was bug) 2267 andl(x, 0xFF); 2268 setb(Assembler::notZero, x); 2269 } 2270 2271 // Wouldn't need if AddressLiteral version had new name 2272 void MacroAssembler::call(Label& L, relocInfo::relocType rtype) { 2273 Assembler::call(L, rtype); 2274 } 2275 2276 void MacroAssembler::call(Register entry) { 2277 Assembler::call(entry); 2278 } 2279 2280 void MacroAssembler::call(AddressLiteral entry) { 2281 if (reachable(entry)) { 2282 Assembler::call_literal(entry.target(), entry.rspec()); 2283 } else { 2284 lea(rscratch1, entry); 2285 Assembler::call(rscratch1); 2286 } 2287 } 2288 2289 void MacroAssembler::ic_call(address entry, jint method_index) { 2290 RelocationHolder rh = virtual_call_Relocation::spec(pc(), method_index); 2291 movptr(rax, (intptr_t)Universe::non_oop_word()); 2292 call(AddressLiteral(entry, rh)); 2293 } 2294 2295 // Implementation of call_VM versions 2296 2297 void MacroAssembler::call_VM(Register oop_result, 2298 address entry_point, 2299 bool check_exceptions) { 2300 Label C, E; 2301 call(C, relocInfo::none); 2302 jmp(E); 2303 2304 bind(C); 2305 call_VM_helper(oop_result, entry_point, 0, check_exceptions); 2306 ret(0); 2307 2308 bind(E); 2309 } 2310 2311 void MacroAssembler::call_VM(Register oop_result, 2312 address entry_point, 2313 Register arg_1, 2314 bool check_exceptions) { 2315 Label C, E; 2316 call(C, relocInfo::none); 2317 jmp(E); 2318 2319 bind(C); 2320 pass_arg1(this, arg_1); 2321 call_VM_helper(oop_result, entry_point, 1, check_exceptions); 2322 ret(0); 2323 2324 bind(E); 2325 } 2326 2327 void MacroAssembler::call_VM(Register oop_result, 2328 address entry_point, 2329 Register arg_1, 2330 Register arg_2, 2331 bool check_exceptions) { 2332 Label C, E; 2333 call(C, relocInfo::none); 2334 jmp(E); 2335 2336 bind(C); 2337 2338 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2339 2340 pass_arg2(this, arg_2); 2341 pass_arg1(this, arg_1); 2342 call_VM_helper(oop_result, entry_point, 2, check_exceptions); 2343 ret(0); 2344 2345 bind(E); 2346 } 2347 2348 void MacroAssembler::call_VM(Register oop_result, 2349 address entry_point, 2350 Register arg_1, 2351 Register arg_2, 2352 Register arg_3, 2353 bool check_exceptions) { 2354 Label C, E; 2355 call(C, relocInfo::none); 2356 jmp(E); 2357 2358 bind(C); 2359 2360 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2361 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2362 pass_arg3(this, arg_3); 2363 2364 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2365 pass_arg2(this, arg_2); 2366 2367 pass_arg1(this, arg_1); 2368 call_VM_helper(oop_result, entry_point, 3, check_exceptions); 2369 ret(0); 2370 2371 bind(E); 2372 } 2373 2374 void MacroAssembler::call_VM(Register oop_result, 2375 Register last_java_sp, 2376 address entry_point, 2377 int number_of_arguments, 2378 bool check_exceptions) { 2379 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2380 call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2381 } 2382 2383 void MacroAssembler::call_VM(Register oop_result, 2384 Register last_java_sp, 2385 address entry_point, 2386 Register arg_1, 2387 bool check_exceptions) { 2388 pass_arg1(this, arg_1); 2389 call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2390 } 2391 2392 void MacroAssembler::call_VM(Register oop_result, 2393 Register last_java_sp, 2394 address entry_point, 2395 Register arg_1, 2396 Register arg_2, 2397 bool check_exceptions) { 2398 2399 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2400 pass_arg2(this, arg_2); 2401 pass_arg1(this, arg_1); 2402 call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2403 } 2404 2405 void MacroAssembler::call_VM(Register oop_result, 2406 Register last_java_sp, 2407 address entry_point, 2408 Register arg_1, 2409 Register arg_2, 2410 Register arg_3, 2411 bool check_exceptions) { 2412 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2413 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2414 pass_arg3(this, arg_3); 2415 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2416 pass_arg2(this, arg_2); 2417 pass_arg1(this, arg_1); 2418 call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2419 } 2420 2421 void MacroAssembler::super_call_VM(Register oop_result, 2422 Register last_java_sp, 2423 address entry_point, 2424 int number_of_arguments, 2425 bool check_exceptions) { 2426 Register thread = LP64_ONLY(r15_thread) NOT_LP64(noreg); 2427 MacroAssembler::call_VM_base(oop_result, thread, last_java_sp, entry_point, number_of_arguments, check_exceptions); 2428 } 2429 2430 void MacroAssembler::super_call_VM(Register oop_result, 2431 Register last_java_sp, 2432 address entry_point, 2433 Register arg_1, 2434 bool check_exceptions) { 2435 pass_arg1(this, arg_1); 2436 super_call_VM(oop_result, last_java_sp, entry_point, 1, check_exceptions); 2437 } 2438 2439 void MacroAssembler::super_call_VM(Register oop_result, 2440 Register last_java_sp, 2441 address entry_point, 2442 Register arg_1, 2443 Register arg_2, 2444 bool check_exceptions) { 2445 2446 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2447 pass_arg2(this, arg_2); 2448 pass_arg1(this, arg_1); 2449 super_call_VM(oop_result, last_java_sp, entry_point, 2, check_exceptions); 2450 } 2451 2452 void MacroAssembler::super_call_VM(Register oop_result, 2453 Register last_java_sp, 2454 address entry_point, 2455 Register arg_1, 2456 Register arg_2, 2457 Register arg_3, 2458 bool check_exceptions) { 2459 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2460 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2461 pass_arg3(this, arg_3); 2462 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2463 pass_arg2(this, arg_2); 2464 pass_arg1(this, arg_1); 2465 super_call_VM(oop_result, last_java_sp, entry_point, 3, check_exceptions); 2466 } 2467 2468 void MacroAssembler::call_VM_base(Register oop_result, 2469 Register java_thread, 2470 Register last_java_sp, 2471 address entry_point, 2472 int number_of_arguments, 2473 bool check_exceptions) { 2474 // determine java_thread register 2475 if (!java_thread->is_valid()) { 2476 #ifdef _LP64 2477 java_thread = r15_thread; 2478 #else 2479 java_thread = rdi; 2480 get_thread(java_thread); 2481 #endif // LP64 2482 } 2483 // determine last_java_sp register 2484 if (!last_java_sp->is_valid()) { 2485 last_java_sp = rsp; 2486 } 2487 // debugging support 2488 assert(number_of_arguments >= 0 , "cannot have negative number of arguments"); 2489 LP64_ONLY(assert(java_thread == r15_thread, "unexpected register")); 2490 #ifdef ASSERT 2491 // TraceBytecodes does not use r12 but saves it over the call, so don't verify 2492 // r12 is the heapbase. 2493 LP64_ONLY(if ((UseCompressedOops || UseCompressedClassPointers) && !TraceBytecodes) verify_heapbase("call_VM_base: heap base corrupted?");) 2494 #endif // ASSERT 2495 2496 assert(java_thread != oop_result , "cannot use the same register for java_thread & oop_result"); 2497 assert(java_thread != last_java_sp, "cannot use the same register for java_thread & last_java_sp"); 2498 2499 // push java thread (becomes first argument of C function) 2500 2501 NOT_LP64(push(java_thread); number_of_arguments++); 2502 LP64_ONLY(mov(c_rarg0, r15_thread)); 2503 2504 // set last Java frame before call 2505 assert(last_java_sp != rbp, "can't use ebp/rbp"); 2506 2507 // Only interpreter should have to set fp 2508 set_last_Java_frame(java_thread, last_java_sp, rbp, NULL); 2509 2510 // do the call, remove parameters 2511 MacroAssembler::call_VM_leaf_base(entry_point, number_of_arguments); 2512 2513 // restore the thread (cannot use the pushed argument since arguments 2514 // may be overwritten by C code generated by an optimizing compiler); 2515 // however can use the register value directly if it is callee saved. 2516 if (LP64_ONLY(true ||) java_thread == rdi || java_thread == rsi) { 2517 // rdi & rsi (also r15) are callee saved -> nothing to do 2518 #ifdef ASSERT 2519 guarantee(java_thread != rax, "change this code"); 2520 push(rax); 2521 { Label L; 2522 get_thread(rax); 2523 cmpptr(java_thread, rax); 2524 jcc(Assembler::equal, L); 2525 STOP("MacroAssembler::call_VM_base: rdi not callee saved?"); 2526 bind(L); 2527 } 2528 pop(rax); 2529 #endif 2530 } else { 2531 get_thread(java_thread); 2532 } 2533 // reset last Java frame 2534 // Only interpreter should have to clear fp 2535 reset_last_Java_frame(java_thread, true, false); 2536 2537 // C++ interp handles this in the interpreter 2538 check_and_handle_popframe(java_thread); 2539 check_and_handle_earlyret(java_thread); 2540 2541 if (check_exceptions) { 2542 // check for pending exceptions (java_thread is set upon return) 2543 cmpptr(Address(java_thread, Thread::pending_exception_offset()), (int32_t) NULL_WORD); 2544 #ifndef _LP64 2545 jump_cc(Assembler::notEqual, 2546 RuntimeAddress(StubRoutines::forward_exception_entry())); 2547 #else 2548 // This used to conditionally jump to forward_exception however it is 2549 // possible if we relocate that the branch will not reach. So we must jump 2550 // around so we can always reach 2551 2552 Label ok; 2553 jcc(Assembler::equal, ok); 2554 jump(RuntimeAddress(StubRoutines::forward_exception_entry())); 2555 bind(ok); 2556 #endif // LP64 2557 } 2558 2559 // get oop result if there is one and reset the value in the thread 2560 if (oop_result->is_valid()) { 2561 get_vm_result(oop_result, java_thread); 2562 } 2563 } 2564 2565 void MacroAssembler::call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions) { 2566 2567 // Calculate the value for last_Java_sp 2568 // somewhat subtle. call_VM does an intermediate call 2569 // which places a return address on the stack just under the 2570 // stack pointer as the user finsihed with it. This allows 2571 // use to retrieve last_Java_pc from last_Java_sp[-1]. 2572 // On 32bit we then have to push additional args on the stack to accomplish 2573 // the actual requested call. On 64bit call_VM only can use register args 2574 // so the only extra space is the return address that call_VM created. 2575 // This hopefully explains the calculations here. 2576 2577 #ifdef _LP64 2578 // We've pushed one address, correct last_Java_sp 2579 lea(rax, Address(rsp, wordSize)); 2580 #else 2581 lea(rax, Address(rsp, (1 + number_of_arguments) * wordSize)); 2582 #endif // LP64 2583 2584 call_VM_base(oop_result, noreg, rax, entry_point, number_of_arguments, check_exceptions); 2585 2586 } 2587 2588 void MacroAssembler::call_VM_leaf(address entry_point, int number_of_arguments) { 2589 call_VM_leaf_base(entry_point, number_of_arguments); 2590 } 2591 2592 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0) { 2593 pass_arg0(this, arg_0); 2594 call_VM_leaf(entry_point, 1); 2595 } 2596 2597 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2598 2599 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2600 pass_arg1(this, arg_1); 2601 pass_arg0(this, arg_0); 2602 call_VM_leaf(entry_point, 2); 2603 } 2604 2605 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2606 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2607 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2608 pass_arg2(this, arg_2); 2609 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2610 pass_arg1(this, arg_1); 2611 pass_arg0(this, arg_0); 2612 call_VM_leaf(entry_point, 3); 2613 } 2614 2615 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0) { 2616 pass_arg0(this, arg_0); 2617 MacroAssembler::call_VM_leaf_base(entry_point, 1); 2618 } 2619 2620 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1) { 2621 2622 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2623 pass_arg1(this, arg_1); 2624 pass_arg0(this, arg_0); 2625 MacroAssembler::call_VM_leaf_base(entry_point, 2); 2626 } 2627 2628 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2) { 2629 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2630 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2631 pass_arg2(this, arg_2); 2632 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2633 pass_arg1(this, arg_1); 2634 pass_arg0(this, arg_0); 2635 MacroAssembler::call_VM_leaf_base(entry_point, 3); 2636 } 2637 2638 void MacroAssembler::super_call_VM_leaf(address entry_point, Register arg_0, Register arg_1, Register arg_2, Register arg_3) { 2639 LP64_ONLY(assert(arg_0 != c_rarg3, "smashed arg")); 2640 LP64_ONLY(assert(arg_1 != c_rarg3, "smashed arg")); 2641 LP64_ONLY(assert(arg_2 != c_rarg3, "smashed arg")); 2642 pass_arg3(this, arg_3); 2643 LP64_ONLY(assert(arg_0 != c_rarg2, "smashed arg")); 2644 LP64_ONLY(assert(arg_1 != c_rarg2, "smashed arg")); 2645 pass_arg2(this, arg_2); 2646 LP64_ONLY(assert(arg_0 != c_rarg1, "smashed arg")); 2647 pass_arg1(this, arg_1); 2648 pass_arg0(this, arg_0); 2649 MacroAssembler::call_VM_leaf_base(entry_point, 4); 2650 } 2651 2652 void MacroAssembler::get_vm_result(Register oop_result, Register java_thread) { 2653 movptr(oop_result, Address(java_thread, JavaThread::vm_result_offset())); 2654 movptr(Address(java_thread, JavaThread::vm_result_offset()), NULL_WORD); 2655 verify_oop(oop_result, "broken oop in call_VM_base"); 2656 } 2657 2658 void MacroAssembler::get_vm_result_2(Register metadata_result, Register java_thread) { 2659 movptr(metadata_result, Address(java_thread, JavaThread::vm_result_2_offset())); 2660 movptr(Address(java_thread, JavaThread::vm_result_2_offset()), NULL_WORD); 2661 } 2662 2663 void MacroAssembler::check_and_handle_earlyret(Register java_thread) { 2664 } 2665 2666 void MacroAssembler::check_and_handle_popframe(Register java_thread) { 2667 } 2668 2669 void MacroAssembler::cmp32(AddressLiteral src1, int32_t imm) { 2670 if (reachable(src1)) { 2671 cmpl(as_Address(src1), imm); 2672 } else { 2673 lea(rscratch1, src1); 2674 cmpl(Address(rscratch1, 0), imm); 2675 } 2676 } 2677 2678 void MacroAssembler::cmp32(Register src1, AddressLiteral src2) { 2679 assert(!src2.is_lval(), "use cmpptr"); 2680 if (reachable(src2)) { 2681 cmpl(src1, as_Address(src2)); 2682 } else { 2683 lea(rscratch1, src2); 2684 cmpl(src1, Address(rscratch1, 0)); 2685 } 2686 } 2687 2688 void MacroAssembler::cmp32(Register src1, int32_t imm) { 2689 Assembler::cmpl(src1, imm); 2690 } 2691 2692 void MacroAssembler::cmp32(Register src1, Address src2) { 2693 Assembler::cmpl(src1, src2); 2694 } 2695 2696 void MacroAssembler::cmpsd2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2697 ucomisd(opr1, opr2); 2698 2699 Label L; 2700 if (unordered_is_less) { 2701 movl(dst, -1); 2702 jcc(Assembler::parity, L); 2703 jcc(Assembler::below , L); 2704 movl(dst, 0); 2705 jcc(Assembler::equal , L); 2706 increment(dst); 2707 } else { // unordered is greater 2708 movl(dst, 1); 2709 jcc(Assembler::parity, L); 2710 jcc(Assembler::above , L); 2711 movl(dst, 0); 2712 jcc(Assembler::equal , L); 2713 decrementl(dst); 2714 } 2715 bind(L); 2716 } 2717 2718 void MacroAssembler::cmpss2int(XMMRegister opr1, XMMRegister opr2, Register dst, bool unordered_is_less) { 2719 ucomiss(opr1, opr2); 2720 2721 Label L; 2722 if (unordered_is_less) { 2723 movl(dst, -1); 2724 jcc(Assembler::parity, L); 2725 jcc(Assembler::below , L); 2726 movl(dst, 0); 2727 jcc(Assembler::equal , L); 2728 increment(dst); 2729 } else { // unordered is greater 2730 movl(dst, 1); 2731 jcc(Assembler::parity, L); 2732 jcc(Assembler::above , L); 2733 movl(dst, 0); 2734 jcc(Assembler::equal , L); 2735 decrementl(dst); 2736 } 2737 bind(L); 2738 } 2739 2740 2741 void MacroAssembler::cmp8(AddressLiteral src1, int imm) { 2742 if (reachable(src1)) { 2743 cmpb(as_Address(src1), imm); 2744 } else { 2745 lea(rscratch1, src1); 2746 cmpb(Address(rscratch1, 0), imm); 2747 } 2748 } 2749 2750 void MacroAssembler::cmpptr(Register src1, AddressLiteral src2) { 2751 #ifdef _LP64 2752 if (src2.is_lval()) { 2753 movptr(rscratch1, src2); 2754 Assembler::cmpq(src1, rscratch1); 2755 } else if (reachable(src2)) { 2756 cmpq(src1, as_Address(src2)); 2757 } else { 2758 lea(rscratch1, src2); 2759 Assembler::cmpq(src1, Address(rscratch1, 0)); 2760 } 2761 #else 2762 if (src2.is_lval()) { 2763 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2764 } else { 2765 cmpl(src1, as_Address(src2)); 2766 } 2767 #endif // _LP64 2768 } 2769 2770 void MacroAssembler::cmpptr(Address src1, AddressLiteral src2) { 2771 assert(src2.is_lval(), "not a mem-mem compare"); 2772 #ifdef _LP64 2773 // moves src2's literal address 2774 movptr(rscratch1, src2); 2775 Assembler::cmpq(src1, rscratch1); 2776 #else 2777 cmp_literal32(src1, (int32_t) src2.target(), src2.rspec()); 2778 #endif // _LP64 2779 } 2780 2781 void MacroAssembler::locked_cmpxchgptr(Register reg, AddressLiteral adr) { 2782 if (reachable(adr)) { 2783 if (os::is_MP()) 2784 lock(); 2785 cmpxchgptr(reg, as_Address(adr)); 2786 } else { 2787 lea(rscratch1, adr); 2788 if (os::is_MP()) 2789 lock(); 2790 cmpxchgptr(reg, Address(rscratch1, 0)); 2791 } 2792 } 2793 2794 void MacroAssembler::cmpxchgptr(Register reg, Address adr) { 2795 LP64_ONLY(cmpxchgq(reg, adr)) NOT_LP64(cmpxchgl(reg, adr)); 2796 } 2797 2798 void MacroAssembler::comisd(XMMRegister dst, AddressLiteral src) { 2799 if (reachable(src)) { 2800 Assembler::comisd(dst, as_Address(src)); 2801 } else { 2802 lea(rscratch1, src); 2803 Assembler::comisd(dst, Address(rscratch1, 0)); 2804 } 2805 } 2806 2807 void MacroAssembler::comiss(XMMRegister dst, AddressLiteral src) { 2808 if (reachable(src)) { 2809 Assembler::comiss(dst, as_Address(src)); 2810 } else { 2811 lea(rscratch1, src); 2812 Assembler::comiss(dst, Address(rscratch1, 0)); 2813 } 2814 } 2815 2816 2817 void MacroAssembler::cond_inc32(Condition cond, AddressLiteral counter_addr) { 2818 Condition negated_cond = negate_condition(cond); 2819 Label L; 2820 jcc(negated_cond, L); 2821 pushf(); // Preserve flags 2822 atomic_incl(counter_addr); 2823 popf(); 2824 bind(L); 2825 } 2826 2827 int MacroAssembler::corrected_idivl(Register reg) { 2828 // Full implementation of Java idiv and irem; checks for 2829 // special case as described in JVM spec., p.243 & p.271. 2830 // The function returns the (pc) offset of the idivl 2831 // instruction - may be needed for implicit exceptions. 2832 // 2833 // normal case special case 2834 // 2835 // input : rax,: dividend min_int 2836 // reg: divisor (may not be rax,/rdx) -1 2837 // 2838 // output: rax,: quotient (= rax, idiv reg) min_int 2839 // rdx: remainder (= rax, irem reg) 0 2840 assert(reg != rax && reg != rdx, "reg cannot be rax, or rdx register"); 2841 const int min_int = 0x80000000; 2842 Label normal_case, special_case; 2843 2844 // check for special case 2845 cmpl(rax, min_int); 2846 jcc(Assembler::notEqual, normal_case); 2847 xorl(rdx, rdx); // prepare rdx for possible special case (where remainder = 0) 2848 cmpl(reg, -1); 2849 jcc(Assembler::equal, special_case); 2850 2851 // handle normal case 2852 bind(normal_case); 2853 cdql(); 2854 int idivl_offset = offset(); 2855 idivl(reg); 2856 2857 // normal and special case exit 2858 bind(special_case); 2859 2860 return idivl_offset; 2861 } 2862 2863 2864 2865 void MacroAssembler::decrementl(Register reg, int value) { 2866 if (value == min_jint) {subl(reg, value) ; return; } 2867 if (value < 0) { incrementl(reg, -value); return; } 2868 if (value == 0) { ; return; } 2869 if (value == 1 && UseIncDec) { decl(reg) ; return; } 2870 /* else */ { subl(reg, value) ; return; } 2871 } 2872 2873 void MacroAssembler::decrementl(Address dst, int value) { 2874 if (value == min_jint) {subl(dst, value) ; return; } 2875 if (value < 0) { incrementl(dst, -value); return; } 2876 if (value == 0) { ; return; } 2877 if (value == 1 && UseIncDec) { decl(dst) ; return; } 2878 /* else */ { subl(dst, value) ; return; } 2879 } 2880 2881 void MacroAssembler::division_with_shift (Register reg, int shift_value) { 2882 assert (shift_value > 0, "illegal shift value"); 2883 Label _is_positive; 2884 testl (reg, reg); 2885 jcc (Assembler::positive, _is_positive); 2886 int offset = (1 << shift_value) - 1 ; 2887 2888 if (offset == 1) { 2889 incrementl(reg); 2890 } else { 2891 addl(reg, offset); 2892 } 2893 2894 bind (_is_positive); 2895 sarl(reg, shift_value); 2896 } 2897 2898 void MacroAssembler::divsd(XMMRegister dst, AddressLiteral src) { 2899 if (reachable(src)) { 2900 Assembler::divsd(dst, as_Address(src)); 2901 } else { 2902 lea(rscratch1, src); 2903 Assembler::divsd(dst, Address(rscratch1, 0)); 2904 } 2905 } 2906 2907 void MacroAssembler::divss(XMMRegister dst, AddressLiteral src) { 2908 if (reachable(src)) { 2909 Assembler::divss(dst, as_Address(src)); 2910 } else { 2911 lea(rscratch1, src); 2912 Assembler::divss(dst, Address(rscratch1, 0)); 2913 } 2914 } 2915 2916 // !defined(COMPILER2) is because of stupid core builds 2917 #if !defined(_LP64) || defined(COMPILER1) || !defined(COMPILER2) || INCLUDE_JVMCI 2918 void MacroAssembler::empty_FPU_stack() { 2919 if (VM_Version::supports_mmx()) { 2920 emms(); 2921 } else { 2922 for (int i = 8; i-- > 0; ) ffree(i); 2923 } 2924 } 2925 #endif // !LP64 || C1 || !C2 || INCLUDE_JVMCI 2926 2927 2928 // Defines obj, preserves var_size_in_bytes 2929 void MacroAssembler::eden_allocate(Register obj, 2930 Register var_size_in_bytes, 2931 int con_size_in_bytes, 2932 Register t1, 2933 Label& slow_case) { 2934 assert(obj == rax, "obj must be in rax, for cmpxchg"); 2935 assert_different_registers(obj, var_size_in_bytes, t1); 2936 if (!Universe::heap()->supports_inline_contig_alloc()) { 2937 jmp(slow_case); 2938 } else { 2939 Register end = t1; 2940 Label retry; 2941 bind(retry); 2942 ExternalAddress heap_top((address) Universe::heap()->top_addr()); 2943 movptr(obj, heap_top); 2944 if (var_size_in_bytes == noreg) { 2945 lea(end, Address(obj, con_size_in_bytes)); 2946 } else { 2947 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 2948 } 2949 // if end < obj then we wrapped around => object too long => slow case 2950 cmpptr(end, obj); 2951 jcc(Assembler::below, slow_case); 2952 cmpptr(end, ExternalAddress((address) Universe::heap()->end_addr())); 2953 jcc(Assembler::above, slow_case); 2954 // Compare obj with the top addr, and if still equal, store the new top addr in 2955 // end at the address of the top addr pointer. Sets ZF if was equal, and clears 2956 // it otherwise. Use lock prefix for atomicity on MPs. 2957 locked_cmpxchgptr(end, heap_top); 2958 jcc(Assembler::notEqual, retry); 2959 } 2960 } 2961 2962 void MacroAssembler::enter() { 2963 push(rbp); 2964 mov(rbp, rsp); 2965 } 2966 2967 // A 5 byte nop that is safe for patching (see patch_verified_entry) 2968 void MacroAssembler::fat_nop() { 2969 if (UseAddressNop) { 2970 addr_nop_5(); 2971 } else { 2972 emit_int8(0x26); // es: 2973 emit_int8(0x2e); // cs: 2974 emit_int8(0x64); // fs: 2975 emit_int8(0x65); // gs: 2976 emit_int8((unsigned char)0x90); 2977 } 2978 } 2979 2980 void MacroAssembler::fcmp(Register tmp) { 2981 fcmp(tmp, 1, true, true); 2982 } 2983 2984 void MacroAssembler::fcmp(Register tmp, int index, bool pop_left, bool pop_right) { 2985 assert(!pop_right || pop_left, "usage error"); 2986 if (VM_Version::supports_cmov()) { 2987 assert(tmp == noreg, "unneeded temp"); 2988 if (pop_left) { 2989 fucomip(index); 2990 } else { 2991 fucomi(index); 2992 } 2993 if (pop_right) { 2994 fpop(); 2995 } 2996 } else { 2997 assert(tmp != noreg, "need temp"); 2998 if (pop_left) { 2999 if (pop_right) { 3000 fcompp(); 3001 } else { 3002 fcomp(index); 3003 } 3004 } else { 3005 fcom(index); 3006 } 3007 // convert FPU condition into eflags condition via rax, 3008 save_rax(tmp); 3009 fwait(); fnstsw_ax(); 3010 sahf(); 3011 restore_rax(tmp); 3012 } 3013 // condition codes set as follows: 3014 // 3015 // CF (corresponds to C0) if x < y 3016 // PF (corresponds to C2) if unordered 3017 // ZF (corresponds to C3) if x = y 3018 } 3019 3020 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less) { 3021 fcmp2int(dst, unordered_is_less, 1, true, true); 3022 } 3023 3024 void MacroAssembler::fcmp2int(Register dst, bool unordered_is_less, int index, bool pop_left, bool pop_right) { 3025 fcmp(VM_Version::supports_cmov() ? noreg : dst, index, pop_left, pop_right); 3026 Label L; 3027 if (unordered_is_less) { 3028 movl(dst, -1); 3029 jcc(Assembler::parity, L); 3030 jcc(Assembler::below , L); 3031 movl(dst, 0); 3032 jcc(Assembler::equal , L); 3033 increment(dst); 3034 } else { // unordered is greater 3035 movl(dst, 1); 3036 jcc(Assembler::parity, L); 3037 jcc(Assembler::above , L); 3038 movl(dst, 0); 3039 jcc(Assembler::equal , L); 3040 decrementl(dst); 3041 } 3042 bind(L); 3043 } 3044 3045 void MacroAssembler::fld_d(AddressLiteral src) { 3046 fld_d(as_Address(src)); 3047 } 3048 3049 void MacroAssembler::fld_s(AddressLiteral src) { 3050 fld_s(as_Address(src)); 3051 } 3052 3053 void MacroAssembler::fld_x(AddressLiteral src) { 3054 Assembler::fld_x(as_Address(src)); 3055 } 3056 3057 void MacroAssembler::fldcw(AddressLiteral src) { 3058 Assembler::fldcw(as_Address(src)); 3059 } 3060 3061 void MacroAssembler::mulpd(XMMRegister dst, AddressLiteral src) { 3062 if (reachable(src)) { 3063 Assembler::mulpd(dst, as_Address(src)); 3064 } else { 3065 lea(rscratch1, src); 3066 Assembler::mulpd(dst, Address(rscratch1, 0)); 3067 } 3068 } 3069 3070 void MacroAssembler::increase_precision() { 3071 subptr(rsp, BytesPerWord); 3072 fnstcw(Address(rsp, 0)); 3073 movl(rax, Address(rsp, 0)); 3074 orl(rax, 0x300); 3075 push(rax); 3076 fldcw(Address(rsp, 0)); 3077 pop(rax); 3078 } 3079 3080 void MacroAssembler::restore_precision() { 3081 fldcw(Address(rsp, 0)); 3082 addptr(rsp, BytesPerWord); 3083 } 3084 3085 void MacroAssembler::fpop() { 3086 ffree(); 3087 fincstp(); 3088 } 3089 3090 void MacroAssembler::load_float(Address src) { 3091 if (UseSSE >= 1) { 3092 movflt(xmm0, src); 3093 } else { 3094 LP64_ONLY(ShouldNotReachHere()); 3095 NOT_LP64(fld_s(src)); 3096 } 3097 } 3098 3099 void MacroAssembler::store_float(Address dst) { 3100 if (UseSSE >= 1) { 3101 movflt(dst, xmm0); 3102 } else { 3103 LP64_ONLY(ShouldNotReachHere()); 3104 NOT_LP64(fstp_s(dst)); 3105 } 3106 } 3107 3108 void MacroAssembler::load_double(Address src) { 3109 if (UseSSE >= 2) { 3110 movdbl(xmm0, src); 3111 } else { 3112 LP64_ONLY(ShouldNotReachHere()); 3113 NOT_LP64(fld_d(src)); 3114 } 3115 } 3116 3117 void MacroAssembler::store_double(Address dst) { 3118 if (UseSSE >= 2) { 3119 movdbl(dst, xmm0); 3120 } else { 3121 LP64_ONLY(ShouldNotReachHere()); 3122 NOT_LP64(fstp_d(dst)); 3123 } 3124 } 3125 3126 void MacroAssembler::fremr(Register tmp) { 3127 save_rax(tmp); 3128 { Label L; 3129 bind(L); 3130 fprem(); 3131 fwait(); fnstsw_ax(); 3132 #ifdef _LP64 3133 testl(rax, 0x400); 3134 jcc(Assembler::notEqual, L); 3135 #else 3136 sahf(); 3137 jcc(Assembler::parity, L); 3138 #endif // _LP64 3139 } 3140 restore_rax(tmp); 3141 // Result is in ST0. 3142 // Note: fxch & fpop to get rid of ST1 3143 // (otherwise FPU stack could overflow eventually) 3144 fxch(1); 3145 fpop(); 3146 } 3147 3148 3149 void MacroAssembler::incrementl(AddressLiteral dst) { 3150 if (reachable(dst)) { 3151 incrementl(as_Address(dst)); 3152 } else { 3153 lea(rscratch1, dst); 3154 incrementl(Address(rscratch1, 0)); 3155 } 3156 } 3157 3158 void MacroAssembler::incrementl(ArrayAddress dst) { 3159 incrementl(as_Address(dst)); 3160 } 3161 3162 void MacroAssembler::incrementl(Register reg, int value) { 3163 if (value == min_jint) {addl(reg, value) ; return; } 3164 if (value < 0) { decrementl(reg, -value); return; } 3165 if (value == 0) { ; return; } 3166 if (value == 1 && UseIncDec) { incl(reg) ; return; } 3167 /* else */ { addl(reg, value) ; return; } 3168 } 3169 3170 void MacroAssembler::incrementl(Address dst, int value) { 3171 if (value == min_jint) {addl(dst, value) ; return; } 3172 if (value < 0) { decrementl(dst, -value); return; } 3173 if (value == 0) { ; return; } 3174 if (value == 1 && UseIncDec) { incl(dst) ; return; } 3175 /* else */ { addl(dst, value) ; return; } 3176 } 3177 3178 void MacroAssembler::jump(AddressLiteral dst) { 3179 if (reachable(dst)) { 3180 jmp_literal(dst.target(), dst.rspec()); 3181 } else { 3182 lea(rscratch1, dst); 3183 jmp(rscratch1); 3184 } 3185 } 3186 3187 void MacroAssembler::jump_cc(Condition cc, AddressLiteral dst) { 3188 if (reachable(dst)) { 3189 InstructionMark im(this); 3190 relocate(dst.reloc()); 3191 const int short_size = 2; 3192 const int long_size = 6; 3193 int offs = (intptr_t)dst.target() - ((intptr_t)pc()); 3194 if (dst.reloc() == relocInfo::none && is8bit(offs - short_size)) { 3195 // 0111 tttn #8-bit disp 3196 emit_int8(0x70 | cc); 3197 emit_int8((offs - short_size) & 0xFF); 3198 } else { 3199 // 0000 1111 1000 tttn #32-bit disp 3200 emit_int8(0x0F); 3201 emit_int8((unsigned char)(0x80 | cc)); 3202 emit_int32(offs - long_size); 3203 } 3204 } else { 3205 #ifdef ASSERT 3206 warning("reversing conditional branch"); 3207 #endif /* ASSERT */ 3208 Label skip; 3209 jccb(reverse[cc], skip); 3210 lea(rscratch1, dst); 3211 Assembler::jmp(rscratch1); 3212 bind(skip); 3213 } 3214 } 3215 3216 void MacroAssembler::ldmxcsr(AddressLiteral src) { 3217 if (reachable(src)) { 3218 Assembler::ldmxcsr(as_Address(src)); 3219 } else { 3220 lea(rscratch1, src); 3221 Assembler::ldmxcsr(Address(rscratch1, 0)); 3222 } 3223 } 3224 3225 int MacroAssembler::load_signed_byte(Register dst, Address src) { 3226 int off; 3227 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3228 off = offset(); 3229 movsbl(dst, src); // movsxb 3230 } else { 3231 off = load_unsigned_byte(dst, src); 3232 shll(dst, 24); 3233 sarl(dst, 24); 3234 } 3235 return off; 3236 } 3237 3238 // Note: load_signed_short used to be called load_signed_word. 3239 // Although the 'w' in x86 opcodes refers to the term "word" in the assembler 3240 // manual, which means 16 bits, that usage is found nowhere in HotSpot code. 3241 // The term "word" in HotSpot means a 32- or 64-bit machine word. 3242 int MacroAssembler::load_signed_short(Register dst, Address src) { 3243 int off; 3244 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3245 // This is dubious to me since it seems safe to do a signed 16 => 64 bit 3246 // version but this is what 64bit has always done. This seems to imply 3247 // that users are only using 32bits worth. 3248 off = offset(); 3249 movswl(dst, src); // movsxw 3250 } else { 3251 off = load_unsigned_short(dst, src); 3252 shll(dst, 16); 3253 sarl(dst, 16); 3254 } 3255 return off; 3256 } 3257 3258 int MacroAssembler::load_unsigned_byte(Register dst, Address src) { 3259 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3260 // and "3.9 Partial Register Penalties", p. 22). 3261 int off; 3262 if (LP64_ONLY(true || ) VM_Version::is_P6() || src.uses(dst)) { 3263 off = offset(); 3264 movzbl(dst, src); // movzxb 3265 } else { 3266 xorl(dst, dst); 3267 off = offset(); 3268 movb(dst, src); 3269 } 3270 return off; 3271 } 3272 3273 // Note: load_unsigned_short used to be called load_unsigned_word. 3274 int MacroAssembler::load_unsigned_short(Register dst, Address src) { 3275 // According to Intel Doc. AP-526, "Zero-Extension of Short", p.16, 3276 // and "3.9 Partial Register Penalties", p. 22). 3277 int off; 3278 if (LP64_ONLY(true ||) VM_Version::is_P6() || src.uses(dst)) { 3279 off = offset(); 3280 movzwl(dst, src); // movzxw 3281 } else { 3282 xorl(dst, dst); 3283 off = offset(); 3284 movw(dst, src); 3285 } 3286 return off; 3287 } 3288 3289 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2) { 3290 switch (size_in_bytes) { 3291 #ifndef _LP64 3292 case 8: 3293 assert(dst2 != noreg, "second dest register required"); 3294 movl(dst, src); 3295 movl(dst2, src.plus_disp(BytesPerInt)); 3296 break; 3297 #else 3298 case 8: movq(dst, src); break; 3299 #endif 3300 case 4: movl(dst, src); break; 3301 case 2: is_signed ? load_signed_short(dst, src) : load_unsigned_short(dst, src); break; 3302 case 1: is_signed ? load_signed_byte( dst, src) : load_unsigned_byte( dst, src); break; 3303 default: ShouldNotReachHere(); 3304 } 3305 } 3306 3307 void MacroAssembler::store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2) { 3308 switch (size_in_bytes) { 3309 #ifndef _LP64 3310 case 8: 3311 assert(src2 != noreg, "second source register required"); 3312 movl(dst, src); 3313 movl(dst.plus_disp(BytesPerInt), src2); 3314 break; 3315 #else 3316 case 8: movq(dst, src); break; 3317 #endif 3318 case 4: movl(dst, src); break; 3319 case 2: movw(dst, src); break; 3320 case 1: movb(dst, src); break; 3321 default: ShouldNotReachHere(); 3322 } 3323 } 3324 3325 void MacroAssembler::mov32(AddressLiteral dst, Register src) { 3326 if (reachable(dst)) { 3327 movl(as_Address(dst), src); 3328 } else { 3329 lea(rscratch1, dst); 3330 movl(Address(rscratch1, 0), src); 3331 } 3332 } 3333 3334 void MacroAssembler::mov32(Register dst, AddressLiteral src) { 3335 if (reachable(src)) { 3336 movl(dst, as_Address(src)); 3337 } else { 3338 lea(rscratch1, src); 3339 movl(dst, Address(rscratch1, 0)); 3340 } 3341 } 3342 3343 // C++ bool manipulation 3344 3345 void MacroAssembler::movbool(Register dst, Address src) { 3346 if(sizeof(bool) == 1) 3347 movb(dst, src); 3348 else if(sizeof(bool) == 2) 3349 movw(dst, src); 3350 else if(sizeof(bool) == 4) 3351 movl(dst, src); 3352 else 3353 // unsupported 3354 ShouldNotReachHere(); 3355 } 3356 3357 void MacroAssembler::movbool(Address dst, bool boolconst) { 3358 if(sizeof(bool) == 1) 3359 movb(dst, (int) boolconst); 3360 else if(sizeof(bool) == 2) 3361 movw(dst, (int) boolconst); 3362 else if(sizeof(bool) == 4) 3363 movl(dst, (int) boolconst); 3364 else 3365 // unsupported 3366 ShouldNotReachHere(); 3367 } 3368 3369 void MacroAssembler::movbool(Address dst, Register src) { 3370 if(sizeof(bool) == 1) 3371 movb(dst, src); 3372 else if(sizeof(bool) == 2) 3373 movw(dst, src); 3374 else if(sizeof(bool) == 4) 3375 movl(dst, src); 3376 else 3377 // unsupported 3378 ShouldNotReachHere(); 3379 } 3380 3381 void MacroAssembler::movbyte(ArrayAddress dst, int src) { 3382 movb(as_Address(dst), src); 3383 } 3384 3385 void MacroAssembler::movdl(XMMRegister dst, AddressLiteral src) { 3386 if (reachable(src)) { 3387 movdl(dst, as_Address(src)); 3388 } else { 3389 lea(rscratch1, src); 3390 movdl(dst, Address(rscratch1, 0)); 3391 } 3392 } 3393 3394 void MacroAssembler::movq(XMMRegister dst, AddressLiteral src) { 3395 if (reachable(src)) { 3396 movq(dst, as_Address(src)); 3397 } else { 3398 lea(rscratch1, src); 3399 movq(dst, Address(rscratch1, 0)); 3400 } 3401 } 3402 3403 void MacroAssembler::movdbl(XMMRegister dst, AddressLiteral src) { 3404 if (reachable(src)) { 3405 if (UseXmmLoadAndClearUpper) { 3406 movsd (dst, as_Address(src)); 3407 } else { 3408 movlpd(dst, as_Address(src)); 3409 } 3410 } else { 3411 lea(rscratch1, src); 3412 if (UseXmmLoadAndClearUpper) { 3413 movsd (dst, Address(rscratch1, 0)); 3414 } else { 3415 movlpd(dst, Address(rscratch1, 0)); 3416 } 3417 } 3418 } 3419 3420 void MacroAssembler::movflt(XMMRegister dst, AddressLiteral src) { 3421 if (reachable(src)) { 3422 movss(dst, as_Address(src)); 3423 } else { 3424 lea(rscratch1, src); 3425 movss(dst, Address(rscratch1, 0)); 3426 } 3427 } 3428 3429 void MacroAssembler::movptr(Register dst, Register src) { 3430 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3431 } 3432 3433 void MacroAssembler::movptr(Register dst, Address src) { 3434 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3435 } 3436 3437 // src should NEVER be a real pointer. Use AddressLiteral for true pointers 3438 void MacroAssembler::movptr(Register dst, intptr_t src) { 3439 LP64_ONLY(mov64(dst, src)) NOT_LP64(movl(dst, src)); 3440 } 3441 3442 void MacroAssembler::movptr(Address dst, Register src) { 3443 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src)); 3444 } 3445 3446 void MacroAssembler::movdqu(Address dst, XMMRegister src) { 3447 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3448 Assembler::vextractf32x4h(dst, src, 0); 3449 } else { 3450 Assembler::movdqu(dst, src); 3451 } 3452 } 3453 3454 void MacroAssembler::movdqu(XMMRegister dst, Address src) { 3455 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3456 Assembler::vinsertf32x4h(dst, src, 0); 3457 } else { 3458 Assembler::movdqu(dst, src); 3459 } 3460 } 3461 3462 void MacroAssembler::movdqu(XMMRegister dst, XMMRegister src) { 3463 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3464 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3465 } else { 3466 Assembler::movdqu(dst, src); 3467 } 3468 } 3469 3470 void MacroAssembler::movdqu(XMMRegister dst, AddressLiteral src) { 3471 if (reachable(src)) { 3472 movdqu(dst, as_Address(src)); 3473 } else { 3474 lea(rscratch1, src); 3475 movdqu(dst, Address(rscratch1, 0)); 3476 } 3477 } 3478 3479 void MacroAssembler::vmovdqu(Address dst, XMMRegister src) { 3480 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (src->encoding() > 15)) { 3481 Assembler::vextractf64x4h(dst, src, 0); 3482 } else { 3483 Assembler::vmovdqu(dst, src); 3484 } 3485 } 3486 3487 void MacroAssembler::vmovdqu(XMMRegister dst, Address src) { 3488 if (UseAVX > 2 && !VM_Version::supports_avx512vl() && (dst->encoding() > 15)) { 3489 Assembler::vinsertf64x4h(dst, src, 0); 3490 } else { 3491 Assembler::vmovdqu(dst, src); 3492 } 3493 } 3494 3495 void MacroAssembler::vmovdqu(XMMRegister dst, XMMRegister src) { 3496 if (UseAVX > 2 && !VM_Version::supports_avx512vl()) { 3497 Assembler::evmovdqul(dst, src, Assembler::AVX_512bit); 3498 } 3499 else { 3500 Assembler::vmovdqu(dst, src); 3501 } 3502 } 3503 3504 void MacroAssembler::vmovdqu(XMMRegister dst, AddressLiteral src) { 3505 if (reachable(src)) { 3506 vmovdqu(dst, as_Address(src)); 3507 } 3508 else { 3509 lea(rscratch1, src); 3510 vmovdqu(dst, Address(rscratch1, 0)); 3511 } 3512 } 3513 3514 void MacroAssembler::movdqa(XMMRegister dst, AddressLiteral src) { 3515 if (reachable(src)) { 3516 Assembler::movdqa(dst, as_Address(src)); 3517 } else { 3518 lea(rscratch1, src); 3519 Assembler::movdqa(dst, Address(rscratch1, 0)); 3520 } 3521 } 3522 3523 void MacroAssembler::movsd(XMMRegister dst, AddressLiteral src) { 3524 if (reachable(src)) { 3525 Assembler::movsd(dst, as_Address(src)); 3526 } else { 3527 lea(rscratch1, src); 3528 Assembler::movsd(dst, Address(rscratch1, 0)); 3529 } 3530 } 3531 3532 void MacroAssembler::movss(XMMRegister dst, AddressLiteral src) { 3533 if (reachable(src)) { 3534 Assembler::movss(dst, as_Address(src)); 3535 } else { 3536 lea(rscratch1, src); 3537 Assembler::movss(dst, Address(rscratch1, 0)); 3538 } 3539 } 3540 3541 void MacroAssembler::mulsd(XMMRegister dst, AddressLiteral src) { 3542 if (reachable(src)) { 3543 Assembler::mulsd(dst, as_Address(src)); 3544 } else { 3545 lea(rscratch1, src); 3546 Assembler::mulsd(dst, Address(rscratch1, 0)); 3547 } 3548 } 3549 3550 void MacroAssembler::mulss(XMMRegister dst, AddressLiteral src) { 3551 if (reachable(src)) { 3552 Assembler::mulss(dst, as_Address(src)); 3553 } else { 3554 lea(rscratch1, src); 3555 Assembler::mulss(dst, Address(rscratch1, 0)); 3556 } 3557 } 3558 3559 void MacroAssembler::null_check(Register reg, int offset) { 3560 if (needs_explicit_null_check(offset)) { 3561 // provoke OS NULL exception if reg = NULL by 3562 // accessing M[reg] w/o changing any (non-CC) registers 3563 // NOTE: cmpl is plenty here to provoke a segv 3564 cmpptr(rax, Address(reg, 0)); 3565 // Note: should probably use testl(rax, Address(reg, 0)); 3566 // may be shorter code (however, this version of 3567 // testl needs to be implemented first) 3568 } else { 3569 // nothing to do, (later) access of M[reg + offset] 3570 // will provoke OS NULL exception if reg = NULL 3571 } 3572 } 3573 3574 void MacroAssembler::os_breakpoint() { 3575 // instead of directly emitting a breakpoint, call os:breakpoint for better debugability 3576 // (e.g., MSVC can't call ps() otherwise) 3577 call(RuntimeAddress(CAST_FROM_FN_PTR(address, os::breakpoint))); 3578 } 3579 3580 #ifdef _LP64 3581 #define XSTATE_BV 0x200 3582 #endif 3583 3584 void MacroAssembler::pop_CPU_state() { 3585 pop_FPU_state(); 3586 pop_IU_state(); 3587 } 3588 3589 void MacroAssembler::pop_FPU_state() { 3590 #ifndef _LP64 3591 frstor(Address(rsp, 0)); 3592 #else 3593 fxrstor(Address(rsp, 0)); 3594 #endif 3595 addptr(rsp, FPUStateSizeInWords * wordSize); 3596 } 3597 3598 void MacroAssembler::pop_IU_state() { 3599 popa(); 3600 LP64_ONLY(addq(rsp, 8)); 3601 popf(); 3602 } 3603 3604 // Save Integer and Float state 3605 // Warning: Stack must be 16 byte aligned (64bit) 3606 void MacroAssembler::push_CPU_state() { 3607 push_IU_state(); 3608 push_FPU_state(); 3609 } 3610 3611 void MacroAssembler::push_FPU_state() { 3612 subptr(rsp, FPUStateSizeInWords * wordSize); 3613 #ifndef _LP64 3614 fnsave(Address(rsp, 0)); 3615 fwait(); 3616 #else 3617 fxsave(Address(rsp, 0)); 3618 #endif // LP64 3619 } 3620 3621 void MacroAssembler::push_IU_state() { 3622 // Push flags first because pusha kills them 3623 pushf(); 3624 // Make sure rsp stays 16-byte aligned 3625 LP64_ONLY(subq(rsp, 8)); 3626 pusha(); 3627 } 3628 3629 void MacroAssembler::reset_last_Java_frame(Register java_thread, bool clear_fp, bool clear_pc) { 3630 // determine java_thread register 3631 if (!java_thread->is_valid()) { 3632 java_thread = rdi; 3633 get_thread(java_thread); 3634 } 3635 // we must set sp to zero to clear frame 3636 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), NULL_WORD); 3637 if (clear_fp) { 3638 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), NULL_WORD); 3639 } 3640 3641 if (clear_pc) 3642 movptr(Address(java_thread, JavaThread::last_Java_pc_offset()), NULL_WORD); 3643 3644 } 3645 3646 void MacroAssembler::restore_rax(Register tmp) { 3647 if (tmp == noreg) pop(rax); 3648 else if (tmp != rax) mov(rax, tmp); 3649 } 3650 3651 void MacroAssembler::round_to(Register reg, int modulus) { 3652 addptr(reg, modulus - 1); 3653 andptr(reg, -modulus); 3654 } 3655 3656 void MacroAssembler::save_rax(Register tmp) { 3657 if (tmp == noreg) push(rax); 3658 else if (tmp != rax) mov(tmp, rax); 3659 } 3660 3661 // Write serialization page so VM thread can do a pseudo remote membar. 3662 // We use the current thread pointer to calculate a thread specific 3663 // offset to write to within the page. This minimizes bus traffic 3664 // due to cache line collision. 3665 void MacroAssembler::serialize_memory(Register thread, Register tmp) { 3666 movl(tmp, thread); 3667 shrl(tmp, os::get_serialize_page_shift_count()); 3668 andl(tmp, (os::vm_page_size() - sizeof(int))); 3669 3670 Address index(noreg, tmp, Address::times_1); 3671 ExternalAddress page(os::get_memory_serialize_page()); 3672 3673 // Size of store must match masking code above 3674 movl(as_Address(ArrayAddress(page, index)), tmp); 3675 } 3676 3677 // Calls to C land 3678 // 3679 // When entering C land, the rbp, & rsp of the last Java frame have to be recorded 3680 // in the (thread-local) JavaThread object. When leaving C land, the last Java fp 3681 // has to be reset to 0. This is required to allow proper stack traversal. 3682 void MacroAssembler::set_last_Java_frame(Register java_thread, 3683 Register last_java_sp, 3684 Register last_java_fp, 3685 address last_java_pc) { 3686 // determine java_thread register 3687 if (!java_thread->is_valid()) { 3688 java_thread = rdi; 3689 get_thread(java_thread); 3690 } 3691 // determine last_java_sp register 3692 if (!last_java_sp->is_valid()) { 3693 last_java_sp = rsp; 3694 } 3695 3696 // last_java_fp is optional 3697 3698 if (last_java_fp->is_valid()) { 3699 movptr(Address(java_thread, JavaThread::last_Java_fp_offset()), last_java_fp); 3700 } 3701 3702 // last_java_pc is optional 3703 3704 if (last_java_pc != NULL) { 3705 lea(Address(java_thread, 3706 JavaThread::frame_anchor_offset() + JavaFrameAnchor::last_Java_pc_offset()), 3707 InternalAddress(last_java_pc)); 3708 3709 } 3710 movptr(Address(java_thread, JavaThread::last_Java_sp_offset()), last_java_sp); 3711 } 3712 3713 void MacroAssembler::shlptr(Register dst, int imm8) { 3714 LP64_ONLY(shlq(dst, imm8)) NOT_LP64(shll(dst, imm8)); 3715 } 3716 3717 void MacroAssembler::shrptr(Register dst, int imm8) { 3718 LP64_ONLY(shrq(dst, imm8)) NOT_LP64(shrl(dst, imm8)); 3719 } 3720 3721 void MacroAssembler::sign_extend_byte(Register reg) { 3722 if (LP64_ONLY(true ||) (VM_Version::is_P6() && reg->has_byte_register())) { 3723 movsbl(reg, reg); // movsxb 3724 } else { 3725 shll(reg, 24); 3726 sarl(reg, 24); 3727 } 3728 } 3729 3730 void MacroAssembler::sign_extend_short(Register reg) { 3731 if (LP64_ONLY(true ||) VM_Version::is_P6()) { 3732 movswl(reg, reg); // movsxw 3733 } else { 3734 shll(reg, 16); 3735 sarl(reg, 16); 3736 } 3737 } 3738 3739 void MacroAssembler::testl(Register dst, AddressLiteral src) { 3740 assert(reachable(src), "Address should be reachable"); 3741 testl(dst, as_Address(src)); 3742 } 3743 3744 void MacroAssembler::pcmpeqb(XMMRegister dst, XMMRegister src) { 3745 int dst_enc = dst->encoding(); 3746 int src_enc = src->encoding(); 3747 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3748 Assembler::pcmpeqb(dst, src); 3749 } else if ((dst_enc < 16) && (src_enc < 16)) { 3750 Assembler::pcmpeqb(dst, src); 3751 } else if (src_enc < 16) { 3752 subptr(rsp, 64); 3753 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3754 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3755 Assembler::pcmpeqb(xmm0, src); 3756 movdqu(dst, xmm0); 3757 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3758 addptr(rsp, 64); 3759 } else if (dst_enc < 16) { 3760 subptr(rsp, 64); 3761 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3762 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3763 Assembler::pcmpeqb(dst, xmm0); 3764 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3765 addptr(rsp, 64); 3766 } else { 3767 subptr(rsp, 64); 3768 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3769 subptr(rsp, 64); 3770 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3771 movdqu(xmm0, src); 3772 movdqu(xmm1, dst); 3773 Assembler::pcmpeqb(xmm1, xmm0); 3774 movdqu(dst, xmm1); 3775 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3776 addptr(rsp, 64); 3777 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3778 addptr(rsp, 64); 3779 } 3780 } 3781 3782 void MacroAssembler::pcmpeqw(XMMRegister dst, XMMRegister src) { 3783 int dst_enc = dst->encoding(); 3784 int src_enc = src->encoding(); 3785 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3786 Assembler::pcmpeqw(dst, src); 3787 } else if ((dst_enc < 16) && (src_enc < 16)) { 3788 Assembler::pcmpeqw(dst, src); 3789 } else if (src_enc < 16) { 3790 subptr(rsp, 64); 3791 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3792 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3793 Assembler::pcmpeqw(xmm0, src); 3794 movdqu(dst, xmm0); 3795 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3796 addptr(rsp, 64); 3797 } else if (dst_enc < 16) { 3798 subptr(rsp, 64); 3799 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3800 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3801 Assembler::pcmpeqw(dst, xmm0); 3802 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3803 addptr(rsp, 64); 3804 } else { 3805 subptr(rsp, 64); 3806 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3807 subptr(rsp, 64); 3808 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3809 movdqu(xmm0, src); 3810 movdqu(xmm1, dst); 3811 Assembler::pcmpeqw(xmm1, xmm0); 3812 movdqu(dst, xmm1); 3813 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3814 addptr(rsp, 64); 3815 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3816 addptr(rsp, 64); 3817 } 3818 } 3819 3820 void MacroAssembler::pcmpestri(XMMRegister dst, Address src, int imm8) { 3821 int dst_enc = dst->encoding(); 3822 if (dst_enc < 16) { 3823 Assembler::pcmpestri(dst, src, imm8); 3824 } else { 3825 subptr(rsp, 64); 3826 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3827 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3828 Assembler::pcmpestri(xmm0, src, imm8); 3829 movdqu(dst, xmm0); 3830 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3831 addptr(rsp, 64); 3832 } 3833 } 3834 3835 void MacroAssembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) { 3836 int dst_enc = dst->encoding(); 3837 int src_enc = src->encoding(); 3838 if ((dst_enc < 16) && (src_enc < 16)) { 3839 Assembler::pcmpestri(dst, src, imm8); 3840 } else if (src_enc < 16) { 3841 subptr(rsp, 64); 3842 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3843 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3844 Assembler::pcmpestri(xmm0, src, imm8); 3845 movdqu(dst, xmm0); 3846 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3847 addptr(rsp, 64); 3848 } else if (dst_enc < 16) { 3849 subptr(rsp, 64); 3850 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3851 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3852 Assembler::pcmpestri(dst, xmm0, imm8); 3853 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3854 addptr(rsp, 64); 3855 } else { 3856 subptr(rsp, 64); 3857 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3858 subptr(rsp, 64); 3859 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3860 movdqu(xmm0, src); 3861 movdqu(xmm1, dst); 3862 Assembler::pcmpestri(xmm1, xmm0, imm8); 3863 movdqu(dst, xmm1); 3864 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3865 addptr(rsp, 64); 3866 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3867 addptr(rsp, 64); 3868 } 3869 } 3870 3871 void MacroAssembler::pmovzxbw(XMMRegister dst, XMMRegister src) { 3872 int dst_enc = dst->encoding(); 3873 int src_enc = src->encoding(); 3874 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3875 Assembler::pmovzxbw(dst, src); 3876 } else if ((dst_enc < 16) && (src_enc < 16)) { 3877 Assembler::pmovzxbw(dst, src); 3878 } else if (src_enc < 16) { 3879 subptr(rsp, 64); 3880 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3881 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3882 Assembler::pmovzxbw(xmm0, src); 3883 movdqu(dst, xmm0); 3884 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3885 addptr(rsp, 64); 3886 } else if (dst_enc < 16) { 3887 subptr(rsp, 64); 3888 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3889 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3890 Assembler::pmovzxbw(dst, xmm0); 3891 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3892 addptr(rsp, 64); 3893 } else { 3894 subptr(rsp, 64); 3895 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3896 subptr(rsp, 64); 3897 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3898 movdqu(xmm0, src); 3899 movdqu(xmm1, dst); 3900 Assembler::pmovzxbw(xmm1, xmm0); 3901 movdqu(dst, xmm1); 3902 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3903 addptr(rsp, 64); 3904 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3905 addptr(rsp, 64); 3906 } 3907 } 3908 3909 void MacroAssembler::pmovzxbw(XMMRegister dst, Address src) { 3910 int dst_enc = dst->encoding(); 3911 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 3912 Assembler::pmovzxbw(dst, src); 3913 } else if (dst_enc < 16) { 3914 Assembler::pmovzxbw(dst, src); 3915 } else { 3916 subptr(rsp, 64); 3917 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3918 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3919 Assembler::pmovzxbw(xmm0, src); 3920 movdqu(dst, xmm0); 3921 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3922 addptr(rsp, 64); 3923 } 3924 } 3925 3926 void MacroAssembler::pmovmskb(Register dst, XMMRegister src) { 3927 int src_enc = src->encoding(); 3928 if (src_enc < 16) { 3929 Assembler::pmovmskb(dst, src); 3930 } else { 3931 subptr(rsp, 64); 3932 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3933 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3934 Assembler::pmovmskb(dst, xmm0); 3935 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3936 addptr(rsp, 64); 3937 } 3938 } 3939 3940 void MacroAssembler::ptest(XMMRegister dst, XMMRegister src) { 3941 int dst_enc = dst->encoding(); 3942 int src_enc = src->encoding(); 3943 if ((dst_enc < 16) && (src_enc < 16)) { 3944 Assembler::ptest(dst, src); 3945 } else if (src_enc < 16) { 3946 subptr(rsp, 64); 3947 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3948 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 3949 Assembler::ptest(xmm0, src); 3950 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3951 addptr(rsp, 64); 3952 } else if (dst_enc < 16) { 3953 subptr(rsp, 64); 3954 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3955 evmovdqul(xmm0, src, Assembler::AVX_512bit); 3956 Assembler::ptest(dst, xmm0); 3957 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3958 addptr(rsp, 64); 3959 } else { 3960 subptr(rsp, 64); 3961 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 3962 subptr(rsp, 64); 3963 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 3964 movdqu(xmm0, src); 3965 movdqu(xmm1, dst); 3966 Assembler::ptest(xmm1, xmm0); 3967 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 3968 addptr(rsp, 64); 3969 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 3970 addptr(rsp, 64); 3971 } 3972 } 3973 3974 void MacroAssembler::sqrtsd(XMMRegister dst, AddressLiteral src) { 3975 if (reachable(src)) { 3976 Assembler::sqrtsd(dst, as_Address(src)); 3977 } else { 3978 lea(rscratch1, src); 3979 Assembler::sqrtsd(dst, Address(rscratch1, 0)); 3980 } 3981 } 3982 3983 void MacroAssembler::sqrtss(XMMRegister dst, AddressLiteral src) { 3984 if (reachable(src)) { 3985 Assembler::sqrtss(dst, as_Address(src)); 3986 } else { 3987 lea(rscratch1, src); 3988 Assembler::sqrtss(dst, Address(rscratch1, 0)); 3989 } 3990 } 3991 3992 void MacroAssembler::subsd(XMMRegister dst, AddressLiteral src) { 3993 if (reachable(src)) { 3994 Assembler::subsd(dst, as_Address(src)); 3995 } else { 3996 lea(rscratch1, src); 3997 Assembler::subsd(dst, Address(rscratch1, 0)); 3998 } 3999 } 4000 4001 void MacroAssembler::subss(XMMRegister dst, AddressLiteral src) { 4002 if (reachable(src)) { 4003 Assembler::subss(dst, as_Address(src)); 4004 } else { 4005 lea(rscratch1, src); 4006 Assembler::subss(dst, Address(rscratch1, 0)); 4007 } 4008 } 4009 4010 void MacroAssembler::ucomisd(XMMRegister dst, AddressLiteral src) { 4011 if (reachable(src)) { 4012 Assembler::ucomisd(dst, as_Address(src)); 4013 } else { 4014 lea(rscratch1, src); 4015 Assembler::ucomisd(dst, Address(rscratch1, 0)); 4016 } 4017 } 4018 4019 void MacroAssembler::ucomiss(XMMRegister dst, AddressLiteral src) { 4020 if (reachable(src)) { 4021 Assembler::ucomiss(dst, as_Address(src)); 4022 } else { 4023 lea(rscratch1, src); 4024 Assembler::ucomiss(dst, Address(rscratch1, 0)); 4025 } 4026 } 4027 4028 void MacroAssembler::xorpd(XMMRegister dst, AddressLiteral src) { 4029 // Used in sign-bit flipping with aligned address. 4030 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4031 if (reachable(src)) { 4032 Assembler::xorpd(dst, as_Address(src)); 4033 } else { 4034 lea(rscratch1, src); 4035 Assembler::xorpd(dst, Address(rscratch1, 0)); 4036 } 4037 } 4038 4039 void MacroAssembler::xorpd(XMMRegister dst, XMMRegister src) { 4040 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4041 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4042 } 4043 else { 4044 Assembler::xorpd(dst, src); 4045 } 4046 } 4047 4048 void MacroAssembler::xorps(XMMRegister dst, XMMRegister src) { 4049 if (UseAVX > 2 && !VM_Version::supports_avx512dq() && (dst->encoding() == src->encoding())) { 4050 Assembler::vpxor(dst, dst, src, Assembler::AVX_512bit); 4051 } else { 4052 Assembler::xorps(dst, src); 4053 } 4054 } 4055 4056 void MacroAssembler::xorps(XMMRegister dst, AddressLiteral src) { 4057 // Used in sign-bit flipping with aligned address. 4058 assert((UseAVX > 0) || (((intptr_t)src.target() & 15) == 0), "SSE mode requires address alignment 16 bytes"); 4059 if (reachable(src)) { 4060 Assembler::xorps(dst, as_Address(src)); 4061 } else { 4062 lea(rscratch1, src); 4063 Assembler::xorps(dst, Address(rscratch1, 0)); 4064 } 4065 } 4066 4067 void MacroAssembler::pshufb(XMMRegister dst, AddressLiteral src) { 4068 // Used in sign-bit flipping with aligned address. 4069 bool aligned_adr = (((intptr_t)src.target() & 15) == 0); 4070 assert((UseAVX > 0) || aligned_adr, "SSE mode requires address alignment 16 bytes"); 4071 if (reachable(src)) { 4072 Assembler::pshufb(dst, as_Address(src)); 4073 } else { 4074 lea(rscratch1, src); 4075 Assembler::pshufb(dst, Address(rscratch1, 0)); 4076 } 4077 } 4078 4079 // AVX 3-operands instructions 4080 4081 void MacroAssembler::vaddsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4082 if (reachable(src)) { 4083 vaddsd(dst, nds, as_Address(src)); 4084 } else { 4085 lea(rscratch1, src); 4086 vaddsd(dst, nds, Address(rscratch1, 0)); 4087 } 4088 } 4089 4090 void MacroAssembler::vaddss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4091 if (reachable(src)) { 4092 vaddss(dst, nds, as_Address(src)); 4093 } else { 4094 lea(rscratch1, src); 4095 vaddss(dst, nds, Address(rscratch1, 0)); 4096 } 4097 } 4098 4099 void MacroAssembler::vabsss(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4100 int dst_enc = dst->encoding(); 4101 int nds_enc = nds->encoding(); 4102 int src_enc = src->encoding(); 4103 if ((dst_enc < 16) && (nds_enc < 16)) { 4104 vandps(dst, nds, negate_field, vector_len); 4105 } else if ((src_enc < 16) && (dst_enc < 16)) { 4106 movss(src, nds); 4107 vandps(dst, src, negate_field, vector_len); 4108 } else if (src_enc < 16) { 4109 movss(src, nds); 4110 vandps(src, src, negate_field, vector_len); 4111 movss(dst, src); 4112 } else if (dst_enc < 16) { 4113 movdqu(src, xmm0); 4114 movss(xmm0, nds); 4115 vandps(dst, xmm0, negate_field, vector_len); 4116 movdqu(xmm0, src); 4117 } else if (nds_enc < 16) { 4118 movdqu(src, xmm0); 4119 vandps(xmm0, nds, negate_field, vector_len); 4120 movss(dst, xmm0); 4121 movdqu(xmm0, src); 4122 } else { 4123 movdqu(src, xmm0); 4124 movss(xmm0, nds); 4125 vandps(xmm0, xmm0, negate_field, vector_len); 4126 movss(dst, xmm0); 4127 movdqu(xmm0, src); 4128 } 4129 } 4130 4131 void MacroAssembler::vabssd(XMMRegister dst, XMMRegister nds, XMMRegister src, AddressLiteral negate_field, int vector_len) { 4132 int dst_enc = dst->encoding(); 4133 int nds_enc = nds->encoding(); 4134 int src_enc = src->encoding(); 4135 if ((dst_enc < 16) && (nds_enc < 16)) { 4136 vandpd(dst, nds, negate_field, vector_len); 4137 } else if ((src_enc < 16) && (dst_enc < 16)) { 4138 movsd(src, nds); 4139 vandpd(dst, src, negate_field, vector_len); 4140 } else if (src_enc < 16) { 4141 movsd(src, nds); 4142 vandpd(src, src, negate_field, vector_len); 4143 movsd(dst, src); 4144 } else if (dst_enc < 16) { 4145 movdqu(src, xmm0); 4146 movsd(xmm0, nds); 4147 vandpd(dst, xmm0, negate_field, vector_len); 4148 movdqu(xmm0, src); 4149 } else if (nds_enc < 16) { 4150 movdqu(src, xmm0); 4151 vandpd(xmm0, nds, negate_field, vector_len); 4152 movsd(dst, xmm0); 4153 movdqu(xmm0, src); 4154 } else { 4155 movdqu(src, xmm0); 4156 movsd(xmm0, nds); 4157 vandpd(xmm0, xmm0, negate_field, vector_len); 4158 movsd(dst, xmm0); 4159 movdqu(xmm0, src); 4160 } 4161 } 4162 4163 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4164 int dst_enc = dst->encoding(); 4165 int nds_enc = nds->encoding(); 4166 int src_enc = src->encoding(); 4167 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4168 Assembler::vpaddb(dst, nds, src, vector_len); 4169 } else if ((dst_enc < 16) && (src_enc < 16)) { 4170 Assembler::vpaddb(dst, dst, src, vector_len); 4171 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4172 // use nds as scratch for src 4173 evmovdqul(nds, src, Assembler::AVX_512bit); 4174 Assembler::vpaddb(dst, dst, nds, vector_len); 4175 } else if ((src_enc < 16) && (nds_enc < 16)) { 4176 // use nds as scratch for dst 4177 evmovdqul(nds, dst, Assembler::AVX_512bit); 4178 Assembler::vpaddb(nds, nds, src, vector_len); 4179 evmovdqul(dst, nds, Assembler::AVX_512bit); 4180 } else if (dst_enc < 16) { 4181 // use nds as scatch for xmm0 to hold src 4182 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4183 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4184 Assembler::vpaddb(dst, dst, xmm0, vector_len); 4185 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4186 } else { 4187 // worse case scenario, all regs are in the upper bank 4188 subptr(rsp, 64); 4189 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4190 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4191 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4192 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4193 Assembler::vpaddb(xmm0, xmm0, xmm1, vector_len); 4194 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4195 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4196 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4197 addptr(rsp, 64); 4198 } 4199 } 4200 4201 void MacroAssembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4202 int dst_enc = dst->encoding(); 4203 int nds_enc = nds->encoding(); 4204 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4205 Assembler::vpaddb(dst, nds, src, vector_len); 4206 } else if (dst_enc < 16) { 4207 Assembler::vpaddb(dst, dst, src, vector_len); 4208 } else if (nds_enc < 16) { 4209 // implies dst_enc in upper bank with src as scratch 4210 evmovdqul(nds, dst, Assembler::AVX_512bit); 4211 Assembler::vpaddb(nds, nds, src, vector_len); 4212 evmovdqul(dst, nds, Assembler::AVX_512bit); 4213 } else { 4214 // worse case scenario, all regs in upper bank 4215 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4216 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4217 Assembler::vpaddb(xmm0, xmm0, src, vector_len); 4218 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4219 } 4220 } 4221 4222 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4223 int dst_enc = dst->encoding(); 4224 int nds_enc = nds->encoding(); 4225 int src_enc = src->encoding(); 4226 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4227 Assembler::vpaddw(dst, nds, src, vector_len); 4228 } else if ((dst_enc < 16) && (src_enc < 16)) { 4229 Assembler::vpaddw(dst, dst, src, vector_len); 4230 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4231 // use nds as scratch for src 4232 evmovdqul(nds, src, Assembler::AVX_512bit); 4233 Assembler::vpaddw(dst, dst, nds, vector_len); 4234 } else if ((src_enc < 16) && (nds_enc < 16)) { 4235 // use nds as scratch for dst 4236 evmovdqul(nds, dst, Assembler::AVX_512bit); 4237 Assembler::vpaddw(nds, nds, src, vector_len); 4238 evmovdqul(dst, nds, Assembler::AVX_512bit); 4239 } else if (dst_enc < 16) { 4240 // use nds as scatch for xmm0 to hold src 4241 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4242 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4243 Assembler::vpaddw(dst, dst, xmm0, vector_len); 4244 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4245 } else { 4246 // worse case scenario, all regs are in the upper bank 4247 subptr(rsp, 64); 4248 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4249 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4250 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4251 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4252 Assembler::vpaddw(xmm0, xmm0, xmm1, vector_len); 4253 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4254 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4255 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4256 addptr(rsp, 64); 4257 } 4258 } 4259 4260 void MacroAssembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4261 int dst_enc = dst->encoding(); 4262 int nds_enc = nds->encoding(); 4263 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4264 Assembler::vpaddw(dst, nds, src, vector_len); 4265 } else if (dst_enc < 16) { 4266 Assembler::vpaddw(dst, dst, src, vector_len); 4267 } else if (nds_enc < 16) { 4268 // implies dst_enc in upper bank with src as scratch 4269 evmovdqul(nds, dst, Assembler::AVX_512bit); 4270 Assembler::vpaddw(nds, nds, src, vector_len); 4271 evmovdqul(dst, nds, Assembler::AVX_512bit); 4272 } else { 4273 // worse case scenario, all regs in upper bank 4274 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4275 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4276 Assembler::vpaddw(xmm0, xmm0, src, vector_len); 4277 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4278 } 4279 } 4280 4281 void MacroAssembler::vpbroadcastw(XMMRegister dst, XMMRegister src) { 4282 int dst_enc = dst->encoding(); 4283 int src_enc = src->encoding(); 4284 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4285 Assembler::vpbroadcastw(dst, src); 4286 } else if ((dst_enc < 16) && (src_enc < 16)) { 4287 Assembler::vpbroadcastw(dst, src); 4288 } else if (src_enc < 16) { 4289 subptr(rsp, 64); 4290 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4291 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4292 Assembler::vpbroadcastw(xmm0, src); 4293 movdqu(dst, xmm0); 4294 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4295 addptr(rsp, 64); 4296 } else if (dst_enc < 16) { 4297 subptr(rsp, 64); 4298 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4299 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4300 Assembler::vpbroadcastw(dst, xmm0); 4301 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4302 addptr(rsp, 64); 4303 } else { 4304 subptr(rsp, 64); 4305 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4306 subptr(rsp, 64); 4307 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4308 movdqu(xmm0, src); 4309 movdqu(xmm1, dst); 4310 Assembler::vpbroadcastw(xmm1, xmm0); 4311 movdqu(dst, xmm1); 4312 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4313 addptr(rsp, 64); 4314 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4315 addptr(rsp, 64); 4316 } 4317 } 4318 4319 void MacroAssembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4320 int dst_enc = dst->encoding(); 4321 int nds_enc = nds->encoding(); 4322 int src_enc = src->encoding(); 4323 assert(dst_enc == nds_enc, ""); 4324 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4325 Assembler::vpcmpeqb(dst, nds, src, vector_len); 4326 } else if ((dst_enc < 16) && (src_enc < 16)) { 4327 Assembler::vpcmpeqb(dst, nds, src, vector_len); 4328 } else if (src_enc < 16) { 4329 subptr(rsp, 64); 4330 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4331 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4332 Assembler::vpcmpeqb(xmm0, xmm0, src, vector_len); 4333 movdqu(dst, xmm0); 4334 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4335 addptr(rsp, 64); 4336 } else if (dst_enc < 16) { 4337 subptr(rsp, 64); 4338 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4339 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4340 Assembler::vpcmpeqb(dst, dst, xmm0, vector_len); 4341 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4342 addptr(rsp, 64); 4343 } else { 4344 subptr(rsp, 64); 4345 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4346 subptr(rsp, 64); 4347 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4348 movdqu(xmm0, src); 4349 movdqu(xmm1, dst); 4350 Assembler::vpcmpeqb(xmm1, xmm1, xmm0, vector_len); 4351 movdqu(dst, xmm1); 4352 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4353 addptr(rsp, 64); 4354 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4355 addptr(rsp, 64); 4356 } 4357 } 4358 4359 void MacroAssembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4360 int dst_enc = dst->encoding(); 4361 int nds_enc = nds->encoding(); 4362 int src_enc = src->encoding(); 4363 assert(dst_enc == nds_enc, ""); 4364 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4365 Assembler::vpcmpeqw(dst, nds, src, vector_len); 4366 } else if ((dst_enc < 16) && (src_enc < 16)) { 4367 Assembler::vpcmpeqw(dst, nds, src, vector_len); 4368 } else if (src_enc < 16) { 4369 subptr(rsp, 64); 4370 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4371 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4372 Assembler::vpcmpeqw(xmm0, xmm0, src, vector_len); 4373 movdqu(dst, xmm0); 4374 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4375 addptr(rsp, 64); 4376 } else if (dst_enc < 16) { 4377 subptr(rsp, 64); 4378 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4379 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4380 Assembler::vpcmpeqw(dst, dst, xmm0, vector_len); 4381 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4382 addptr(rsp, 64); 4383 } else { 4384 subptr(rsp, 64); 4385 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4386 subptr(rsp, 64); 4387 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4388 movdqu(xmm0, src); 4389 movdqu(xmm1, dst); 4390 Assembler::vpcmpeqw(xmm1, xmm1, xmm0, vector_len); 4391 movdqu(dst, xmm1); 4392 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4393 addptr(rsp, 64); 4394 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4395 addptr(rsp, 64); 4396 } 4397 } 4398 4399 void MacroAssembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) { 4400 int dst_enc = dst->encoding(); 4401 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4402 Assembler::vpmovzxbw(dst, src, vector_len); 4403 } else if (dst_enc < 16) { 4404 Assembler::vpmovzxbw(dst, src, vector_len); 4405 } else { 4406 subptr(rsp, 64); 4407 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4408 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4409 Assembler::vpmovzxbw(xmm0, src, vector_len); 4410 movdqu(dst, xmm0); 4411 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4412 addptr(rsp, 64); 4413 } 4414 } 4415 4416 void MacroAssembler::vpmovmskb(Register dst, XMMRegister src) { 4417 int src_enc = src->encoding(); 4418 if (src_enc < 16) { 4419 Assembler::vpmovmskb(dst, src); 4420 } else { 4421 subptr(rsp, 64); 4422 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4423 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4424 Assembler::vpmovmskb(dst, xmm0); 4425 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4426 addptr(rsp, 64); 4427 } 4428 } 4429 4430 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4431 int dst_enc = dst->encoding(); 4432 int nds_enc = nds->encoding(); 4433 int src_enc = src->encoding(); 4434 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4435 Assembler::vpmullw(dst, nds, src, vector_len); 4436 } else if ((dst_enc < 16) && (src_enc < 16)) { 4437 Assembler::vpmullw(dst, dst, src, vector_len); 4438 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4439 // use nds as scratch for src 4440 evmovdqul(nds, src, Assembler::AVX_512bit); 4441 Assembler::vpmullw(dst, dst, nds, vector_len); 4442 } else if ((src_enc < 16) && (nds_enc < 16)) { 4443 // use nds as scratch for dst 4444 evmovdqul(nds, dst, Assembler::AVX_512bit); 4445 Assembler::vpmullw(nds, nds, src, vector_len); 4446 evmovdqul(dst, nds, Assembler::AVX_512bit); 4447 } else if (dst_enc < 16) { 4448 // use nds as scatch for xmm0 to hold src 4449 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4450 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4451 Assembler::vpmullw(dst, dst, xmm0, vector_len); 4452 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4453 } else { 4454 // worse case scenario, all regs are in the upper bank 4455 subptr(rsp, 64); 4456 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4457 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4458 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4459 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4460 Assembler::vpmullw(xmm0, xmm0, xmm1, vector_len); 4461 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4462 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4463 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4464 addptr(rsp, 64); 4465 } 4466 } 4467 4468 void MacroAssembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4469 int dst_enc = dst->encoding(); 4470 int nds_enc = nds->encoding(); 4471 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4472 Assembler::vpmullw(dst, nds, src, vector_len); 4473 } else if (dst_enc < 16) { 4474 Assembler::vpmullw(dst, dst, src, vector_len); 4475 } else if (nds_enc < 16) { 4476 // implies dst_enc in upper bank with src as scratch 4477 evmovdqul(nds, dst, Assembler::AVX_512bit); 4478 Assembler::vpmullw(nds, nds, src, vector_len); 4479 evmovdqul(dst, nds, Assembler::AVX_512bit); 4480 } else { 4481 // worse case scenario, all regs in upper bank 4482 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4483 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4484 Assembler::vpmullw(xmm0, xmm0, src, vector_len); 4485 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4486 } 4487 } 4488 4489 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4490 int dst_enc = dst->encoding(); 4491 int nds_enc = nds->encoding(); 4492 int src_enc = src->encoding(); 4493 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4494 Assembler::vpsubb(dst, nds, src, vector_len); 4495 } else if ((dst_enc < 16) && (src_enc < 16)) { 4496 Assembler::vpsubb(dst, dst, src, vector_len); 4497 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4498 // use nds as scratch for src 4499 evmovdqul(nds, src, Assembler::AVX_512bit); 4500 Assembler::vpsubb(dst, dst, nds, vector_len); 4501 } else if ((src_enc < 16) && (nds_enc < 16)) { 4502 // use nds as scratch for dst 4503 evmovdqul(nds, dst, Assembler::AVX_512bit); 4504 Assembler::vpsubb(nds, nds, src, vector_len); 4505 evmovdqul(dst, nds, Assembler::AVX_512bit); 4506 } else if (dst_enc < 16) { 4507 // use nds as scatch for xmm0 to hold src 4508 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4509 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4510 Assembler::vpsubb(dst, dst, xmm0, vector_len); 4511 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4512 } else { 4513 // worse case scenario, all regs are in the upper bank 4514 subptr(rsp, 64); 4515 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4516 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4517 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4518 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4519 Assembler::vpsubb(xmm0, xmm0, xmm1, vector_len); 4520 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4521 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4522 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4523 addptr(rsp, 64); 4524 } 4525 } 4526 4527 void MacroAssembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4528 int dst_enc = dst->encoding(); 4529 int nds_enc = nds->encoding(); 4530 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4531 Assembler::vpsubb(dst, nds, src, vector_len); 4532 } else if (dst_enc < 16) { 4533 Assembler::vpsubb(dst, dst, src, vector_len); 4534 } else if (nds_enc < 16) { 4535 // implies dst_enc in upper bank with src as scratch 4536 evmovdqul(nds, dst, Assembler::AVX_512bit); 4537 Assembler::vpsubb(nds, nds, src, vector_len); 4538 evmovdqul(dst, nds, Assembler::AVX_512bit); 4539 } else { 4540 // worse case scenario, all regs in upper bank 4541 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4542 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4543 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4544 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4545 } 4546 } 4547 4548 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) { 4549 int dst_enc = dst->encoding(); 4550 int nds_enc = nds->encoding(); 4551 int src_enc = src->encoding(); 4552 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4553 Assembler::vpsubw(dst, nds, src, vector_len); 4554 } else if ((dst_enc < 16) && (src_enc < 16)) { 4555 Assembler::vpsubw(dst, dst, src, vector_len); 4556 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4557 // use nds as scratch for src 4558 evmovdqul(nds, src, Assembler::AVX_512bit); 4559 Assembler::vpsubw(dst, dst, nds, vector_len); 4560 } else if ((src_enc < 16) && (nds_enc < 16)) { 4561 // use nds as scratch for dst 4562 evmovdqul(nds, dst, Assembler::AVX_512bit); 4563 Assembler::vpsubw(nds, nds, src, vector_len); 4564 evmovdqul(dst, nds, Assembler::AVX_512bit); 4565 } else if (dst_enc < 16) { 4566 // use nds as scatch for xmm0 to hold src 4567 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4568 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4569 Assembler::vpsubw(dst, dst, xmm0, vector_len); 4570 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4571 } else { 4572 // worse case scenario, all regs are in the upper bank 4573 subptr(rsp, 64); 4574 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4575 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4576 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4577 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4578 Assembler::vpsubw(xmm0, xmm0, xmm1, vector_len); 4579 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4580 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4581 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4582 addptr(rsp, 64); 4583 } 4584 } 4585 4586 void MacroAssembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) { 4587 int dst_enc = dst->encoding(); 4588 int nds_enc = nds->encoding(); 4589 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4590 Assembler::vpsubw(dst, nds, src, vector_len); 4591 } else if (dst_enc < 16) { 4592 Assembler::vpsubw(dst, dst, src, vector_len); 4593 } else if (nds_enc < 16) { 4594 // implies dst_enc in upper bank with src as scratch 4595 evmovdqul(nds, dst, Assembler::AVX_512bit); 4596 Assembler::vpsubw(nds, nds, src, vector_len); 4597 evmovdqul(dst, nds, Assembler::AVX_512bit); 4598 } else { 4599 // worse case scenario, all regs in upper bank 4600 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4601 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4602 Assembler::vpsubw(xmm0, xmm0, src, vector_len); 4603 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4604 } 4605 } 4606 4607 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4608 int dst_enc = dst->encoding(); 4609 int nds_enc = nds->encoding(); 4610 int shift_enc = shift->encoding(); 4611 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4612 Assembler::vpsraw(dst, nds, shift, vector_len); 4613 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4614 Assembler::vpsraw(dst, dst, shift, vector_len); 4615 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4616 // use nds_enc as scratch with shift 4617 evmovdqul(nds, shift, Assembler::AVX_512bit); 4618 Assembler::vpsraw(dst, dst, nds, vector_len); 4619 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4620 // use nds as scratch with dst 4621 evmovdqul(nds, dst, Assembler::AVX_512bit); 4622 Assembler::vpsraw(nds, nds, shift, vector_len); 4623 evmovdqul(dst, nds, Assembler::AVX_512bit); 4624 } else if (dst_enc < 16) { 4625 // use nds to save a copy of xmm0 and hold shift 4626 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4627 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4628 Assembler::vpsraw(dst, dst, xmm0, vector_len); 4629 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4630 } else if (nds_enc < 16) { 4631 // use nds as dest as temps 4632 evmovdqul(nds, dst, Assembler::AVX_512bit); 4633 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4634 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4635 Assembler::vpsraw(nds, nds, xmm0, vector_len); 4636 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4637 evmovdqul(dst, nds, Assembler::AVX_512bit); 4638 } else { 4639 // worse case scenario, all regs are in the upper bank 4640 subptr(rsp, 64); 4641 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4642 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4643 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4644 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4645 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4646 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4647 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4648 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4649 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4650 addptr(rsp, 64); 4651 } 4652 } 4653 4654 void MacroAssembler::vpsraw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4655 int dst_enc = dst->encoding(); 4656 int nds_enc = nds->encoding(); 4657 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4658 Assembler::vpsraw(dst, nds, shift, vector_len); 4659 } else if (dst_enc < 16) { 4660 Assembler::vpsraw(dst, dst, shift, vector_len); 4661 } else if (nds_enc < 16) { 4662 // use nds as scratch 4663 evmovdqul(nds, dst, Assembler::AVX_512bit); 4664 Assembler::vpsraw(nds, nds, shift, vector_len); 4665 evmovdqul(dst, nds, Assembler::AVX_512bit); 4666 } else { 4667 // use nds as scratch for xmm0 4668 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4669 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4670 Assembler::vpsraw(xmm0, xmm0, shift, vector_len); 4671 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4672 } 4673 } 4674 4675 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4676 int dst_enc = dst->encoding(); 4677 int nds_enc = nds->encoding(); 4678 int shift_enc = shift->encoding(); 4679 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4680 Assembler::vpsrlw(dst, nds, shift, vector_len); 4681 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4682 Assembler::vpsrlw(dst, dst, shift, vector_len); 4683 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4684 // use nds_enc as scratch with shift 4685 evmovdqul(nds, shift, Assembler::AVX_512bit); 4686 Assembler::vpsrlw(dst, dst, nds, vector_len); 4687 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4688 // use nds as scratch with dst 4689 evmovdqul(nds, dst, Assembler::AVX_512bit); 4690 Assembler::vpsrlw(nds, nds, shift, vector_len); 4691 evmovdqul(dst, nds, Assembler::AVX_512bit); 4692 } else if (dst_enc < 16) { 4693 // use nds to save a copy of xmm0 and hold shift 4694 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4695 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4696 Assembler::vpsrlw(dst, dst, xmm0, vector_len); 4697 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4698 } else if (nds_enc < 16) { 4699 // use nds as dest as temps 4700 evmovdqul(nds, dst, Assembler::AVX_512bit); 4701 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4702 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4703 Assembler::vpsrlw(nds, nds, xmm0, vector_len); 4704 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4705 evmovdqul(dst, nds, Assembler::AVX_512bit); 4706 } else { 4707 // worse case scenario, all regs are in the upper bank 4708 subptr(rsp, 64); 4709 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4710 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4711 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4712 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4713 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4714 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4715 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4716 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4717 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4718 addptr(rsp, 64); 4719 } 4720 } 4721 4722 void MacroAssembler::vpsrlw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4723 int dst_enc = dst->encoding(); 4724 int nds_enc = nds->encoding(); 4725 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4726 Assembler::vpsrlw(dst, nds, shift, vector_len); 4727 } else if (dst_enc < 16) { 4728 Assembler::vpsrlw(dst, dst, shift, vector_len); 4729 } else if (nds_enc < 16) { 4730 // use nds as scratch 4731 evmovdqul(nds, dst, Assembler::AVX_512bit); 4732 Assembler::vpsrlw(nds, nds, shift, vector_len); 4733 evmovdqul(dst, nds, Assembler::AVX_512bit); 4734 } else { 4735 // use nds as scratch for xmm0 4736 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4737 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4738 Assembler::vpsrlw(xmm0, xmm0, shift, vector_len); 4739 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4740 } 4741 } 4742 4743 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, XMMRegister shift, int vector_len) { 4744 int dst_enc = dst->encoding(); 4745 int nds_enc = nds->encoding(); 4746 int shift_enc = shift->encoding(); 4747 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4748 Assembler::vpsllw(dst, nds, shift, vector_len); 4749 } else if ((dst_enc < 16) && (shift_enc < 16)) { 4750 Assembler::vpsllw(dst, dst, shift, vector_len); 4751 } else if ((dst_enc < 16) && (nds_enc < 16)) { 4752 // use nds_enc as scratch with shift 4753 evmovdqul(nds, shift, Assembler::AVX_512bit); 4754 Assembler::vpsllw(dst, dst, nds, vector_len); 4755 } else if ((shift_enc < 16) && (nds_enc < 16)) { 4756 // use nds as scratch with dst 4757 evmovdqul(nds, dst, Assembler::AVX_512bit); 4758 Assembler::vpsllw(nds, nds, shift, vector_len); 4759 evmovdqul(dst, nds, Assembler::AVX_512bit); 4760 } else if (dst_enc < 16) { 4761 // use nds to save a copy of xmm0 and hold shift 4762 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4763 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4764 Assembler::vpsllw(dst, dst, xmm0, vector_len); 4765 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4766 } else if (nds_enc < 16) { 4767 // use nds as dest as temps 4768 evmovdqul(nds, dst, Assembler::AVX_512bit); 4769 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4770 evmovdqul(xmm0, shift, Assembler::AVX_512bit); 4771 Assembler::vpsllw(nds, nds, xmm0, vector_len); 4772 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4773 evmovdqul(dst, nds, Assembler::AVX_512bit); 4774 } else { 4775 // worse case scenario, all regs are in the upper bank 4776 subptr(rsp, 64); 4777 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4778 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4779 evmovdqul(xmm1, shift, Assembler::AVX_512bit); 4780 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4781 Assembler::vpsllw(xmm0, xmm0, xmm1, vector_len); 4782 evmovdqul(xmm1, dst, Assembler::AVX_512bit); 4783 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4784 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4785 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4786 addptr(rsp, 64); 4787 } 4788 } 4789 4790 void MacroAssembler::vpsllw(XMMRegister dst, XMMRegister nds, int shift, int vector_len) { 4791 int dst_enc = dst->encoding(); 4792 int nds_enc = nds->encoding(); 4793 if (VM_Version::supports_avxonly() || VM_Version::supports_avx512bw()) { 4794 Assembler::vpsllw(dst, nds, shift, vector_len); 4795 } else if (dst_enc < 16) { 4796 Assembler::vpsllw(dst, dst, shift, vector_len); 4797 } else if (nds_enc < 16) { 4798 // use nds as scratch 4799 evmovdqul(nds, dst, Assembler::AVX_512bit); 4800 Assembler::vpsllw(nds, nds, shift, vector_len); 4801 evmovdqul(dst, nds, Assembler::AVX_512bit); 4802 } else { 4803 // use nds as scratch for xmm0 4804 evmovdqul(nds, xmm0, Assembler::AVX_512bit); 4805 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4806 Assembler::vpsllw(xmm0, xmm0, shift, vector_len); 4807 evmovdqul(xmm0, nds, Assembler::AVX_512bit); 4808 } 4809 } 4810 4811 void MacroAssembler::vptest(XMMRegister dst, XMMRegister src) { 4812 int dst_enc = dst->encoding(); 4813 int src_enc = src->encoding(); 4814 if ((dst_enc < 16) && (src_enc < 16)) { 4815 Assembler::vptest(dst, src); 4816 } else if (src_enc < 16) { 4817 subptr(rsp, 64); 4818 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4819 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4820 Assembler::vptest(xmm0, src); 4821 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4822 addptr(rsp, 64); 4823 } else if (dst_enc < 16) { 4824 subptr(rsp, 64); 4825 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4826 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4827 Assembler::vptest(dst, xmm0); 4828 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4829 addptr(rsp, 64); 4830 } else { 4831 subptr(rsp, 64); 4832 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4833 subptr(rsp, 64); 4834 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4835 movdqu(xmm0, src); 4836 movdqu(xmm1, dst); 4837 Assembler::vptest(xmm1, xmm0); 4838 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4839 addptr(rsp, 64); 4840 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4841 addptr(rsp, 64); 4842 } 4843 } 4844 4845 // This instruction exists within macros, ergo we cannot control its input 4846 // when emitted through those patterns. 4847 void MacroAssembler::punpcklbw(XMMRegister dst, XMMRegister src) { 4848 if (VM_Version::supports_avx512nobw()) { 4849 int dst_enc = dst->encoding(); 4850 int src_enc = src->encoding(); 4851 if (dst_enc == src_enc) { 4852 if (dst_enc < 16) { 4853 Assembler::punpcklbw(dst, src); 4854 } else { 4855 subptr(rsp, 64); 4856 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4857 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4858 Assembler::punpcklbw(xmm0, xmm0); 4859 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4860 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4861 addptr(rsp, 64); 4862 } 4863 } else { 4864 if ((src_enc < 16) && (dst_enc < 16)) { 4865 Assembler::punpcklbw(dst, src); 4866 } else if (src_enc < 16) { 4867 subptr(rsp, 64); 4868 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4869 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4870 Assembler::punpcklbw(xmm0, src); 4871 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4872 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4873 addptr(rsp, 64); 4874 } else if (dst_enc < 16) { 4875 subptr(rsp, 64); 4876 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4877 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4878 Assembler::punpcklbw(dst, xmm0); 4879 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4880 addptr(rsp, 64); 4881 } else { 4882 subptr(rsp, 64); 4883 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4884 subptr(rsp, 64); 4885 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4886 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4887 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4888 Assembler::punpcklbw(xmm0, xmm1); 4889 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4890 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4891 addptr(rsp, 64); 4892 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4893 addptr(rsp, 64); 4894 } 4895 } 4896 } else { 4897 Assembler::punpcklbw(dst, src); 4898 } 4899 } 4900 4901 // This instruction exists within macros, ergo we cannot control its input 4902 // when emitted through those patterns. 4903 void MacroAssembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) { 4904 if (VM_Version::supports_avx512nobw()) { 4905 int dst_enc = dst->encoding(); 4906 int src_enc = src->encoding(); 4907 if (dst_enc == src_enc) { 4908 if (dst_enc < 16) { 4909 Assembler::pshuflw(dst, src, mode); 4910 } else { 4911 subptr(rsp, 64); 4912 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4913 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4914 Assembler::pshuflw(xmm0, xmm0, mode); 4915 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4916 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4917 addptr(rsp, 64); 4918 } 4919 } else { 4920 if ((src_enc < 16) && (dst_enc < 16)) { 4921 Assembler::pshuflw(dst, src, mode); 4922 } else if (src_enc < 16) { 4923 subptr(rsp, 64); 4924 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4925 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4926 Assembler::pshuflw(xmm0, src, mode); 4927 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4928 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4929 addptr(rsp, 64); 4930 } else if (dst_enc < 16) { 4931 subptr(rsp, 64); 4932 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4933 evmovdqul(xmm0, src, Assembler::AVX_512bit); 4934 Assembler::pshuflw(dst, xmm0, mode); 4935 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4936 addptr(rsp, 64); 4937 } else { 4938 subptr(rsp, 64); 4939 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 4940 subptr(rsp, 64); 4941 evmovdqul(Address(rsp, 0), xmm1, Assembler::AVX_512bit); 4942 evmovdqul(xmm0, dst, Assembler::AVX_512bit); 4943 evmovdqul(xmm1, src, Assembler::AVX_512bit); 4944 Assembler::pshuflw(xmm0, xmm1, mode); 4945 evmovdqul(dst, xmm0, Assembler::AVX_512bit); 4946 evmovdqul(xmm1, Address(rsp, 0), Assembler::AVX_512bit); 4947 addptr(rsp, 64); 4948 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 4949 addptr(rsp, 64); 4950 } 4951 } 4952 } else { 4953 Assembler::pshuflw(dst, src, mode); 4954 } 4955 } 4956 4957 void MacroAssembler::vandpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4958 if (reachable(src)) { 4959 vandpd(dst, nds, as_Address(src), vector_len); 4960 } else { 4961 lea(rscratch1, src); 4962 vandpd(dst, nds, Address(rscratch1, 0), vector_len); 4963 } 4964 } 4965 4966 void MacroAssembler::vandps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 4967 if (reachable(src)) { 4968 vandps(dst, nds, as_Address(src), vector_len); 4969 } else { 4970 lea(rscratch1, src); 4971 vandps(dst, nds, Address(rscratch1, 0), vector_len); 4972 } 4973 } 4974 4975 void MacroAssembler::vdivsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4976 if (reachable(src)) { 4977 vdivsd(dst, nds, as_Address(src)); 4978 } else { 4979 lea(rscratch1, src); 4980 vdivsd(dst, nds, Address(rscratch1, 0)); 4981 } 4982 } 4983 4984 void MacroAssembler::vdivss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4985 if (reachable(src)) { 4986 vdivss(dst, nds, as_Address(src)); 4987 } else { 4988 lea(rscratch1, src); 4989 vdivss(dst, nds, Address(rscratch1, 0)); 4990 } 4991 } 4992 4993 void MacroAssembler::vmulsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 4994 if (reachable(src)) { 4995 vmulsd(dst, nds, as_Address(src)); 4996 } else { 4997 lea(rscratch1, src); 4998 vmulsd(dst, nds, Address(rscratch1, 0)); 4999 } 5000 } 5001 5002 void MacroAssembler::vmulss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5003 if (reachable(src)) { 5004 vmulss(dst, nds, as_Address(src)); 5005 } else { 5006 lea(rscratch1, src); 5007 vmulss(dst, nds, Address(rscratch1, 0)); 5008 } 5009 } 5010 5011 void MacroAssembler::vsubsd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5012 if (reachable(src)) { 5013 vsubsd(dst, nds, as_Address(src)); 5014 } else { 5015 lea(rscratch1, src); 5016 vsubsd(dst, nds, Address(rscratch1, 0)); 5017 } 5018 } 5019 5020 void MacroAssembler::vsubss(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5021 if (reachable(src)) { 5022 vsubss(dst, nds, as_Address(src)); 5023 } else { 5024 lea(rscratch1, src); 5025 vsubss(dst, nds, Address(rscratch1, 0)); 5026 } 5027 } 5028 5029 void MacroAssembler::vnegatess(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5030 int nds_enc = nds->encoding(); 5031 int dst_enc = dst->encoding(); 5032 bool dst_upper_bank = (dst_enc > 15); 5033 bool nds_upper_bank = (nds_enc > 15); 5034 if (VM_Version::supports_avx512novl() && 5035 (nds_upper_bank || dst_upper_bank)) { 5036 if (dst_upper_bank) { 5037 subptr(rsp, 64); 5038 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5039 movflt(xmm0, nds); 5040 vxorps(xmm0, xmm0, src, Assembler::AVX_128bit); 5041 movflt(dst, xmm0); 5042 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5043 addptr(rsp, 64); 5044 } else { 5045 movflt(dst, nds); 5046 vxorps(dst, dst, src, Assembler::AVX_128bit); 5047 } 5048 } else { 5049 vxorps(dst, nds, src, Assembler::AVX_128bit); 5050 } 5051 } 5052 5053 void MacroAssembler::vnegatesd(XMMRegister dst, XMMRegister nds, AddressLiteral src) { 5054 int nds_enc = nds->encoding(); 5055 int dst_enc = dst->encoding(); 5056 bool dst_upper_bank = (dst_enc > 15); 5057 bool nds_upper_bank = (nds_enc > 15); 5058 if (VM_Version::supports_avx512novl() && 5059 (nds_upper_bank || dst_upper_bank)) { 5060 if (dst_upper_bank) { 5061 subptr(rsp, 64); 5062 evmovdqul(Address(rsp, 0), xmm0, Assembler::AVX_512bit); 5063 movdbl(xmm0, nds); 5064 vxorpd(xmm0, xmm0, src, Assembler::AVX_128bit); 5065 movdbl(dst, xmm0); 5066 evmovdqul(xmm0, Address(rsp, 0), Assembler::AVX_512bit); 5067 addptr(rsp, 64); 5068 } else { 5069 movdbl(dst, nds); 5070 vxorpd(dst, dst, src, Assembler::AVX_128bit); 5071 } 5072 } else { 5073 vxorpd(dst, nds, src, Assembler::AVX_128bit); 5074 } 5075 } 5076 5077 void MacroAssembler::vxorpd(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5078 if (reachable(src)) { 5079 vxorpd(dst, nds, as_Address(src), vector_len); 5080 } else { 5081 lea(rscratch1, src); 5082 vxorpd(dst, nds, Address(rscratch1, 0), vector_len); 5083 } 5084 } 5085 5086 void MacroAssembler::vxorps(XMMRegister dst, XMMRegister nds, AddressLiteral src, int vector_len) { 5087 if (reachable(src)) { 5088 vxorps(dst, nds, as_Address(src), vector_len); 5089 } else { 5090 lea(rscratch1, src); 5091 vxorps(dst, nds, Address(rscratch1, 0), vector_len); 5092 } 5093 } 5094 5095 5096 ////////////////////////////////////////////////////////////////////////////////// 5097 #if INCLUDE_ALL_GCS 5098 5099 void MacroAssembler::g1_write_barrier_pre(Register obj, 5100 Register pre_val, 5101 Register thread, 5102 Register tmp, 5103 bool tosca_live, 5104 bool expand_call) { 5105 5106 // If expand_call is true then we expand the call_VM_leaf macro 5107 // directly to skip generating the check by 5108 // InterpreterMacroAssembler::call_VM_leaf_base that checks _last_sp. 5109 5110 #ifdef _LP64 5111 assert(thread == r15_thread, "must be"); 5112 #endif // _LP64 5113 5114 Label done; 5115 Label runtime; 5116 5117 assert(pre_val != noreg, "check this code"); 5118 5119 if (obj != noreg) { 5120 assert_different_registers(obj, pre_val, tmp); 5121 assert(pre_val != rax, "check this code"); 5122 } 5123 5124 Address in_progress(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5125 SATBMarkQueue::byte_offset_of_active())); 5126 Address index(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5127 SATBMarkQueue::byte_offset_of_index())); 5128 Address buffer(thread, in_bytes(JavaThread::satb_mark_queue_offset() + 5129 SATBMarkQueue::byte_offset_of_buf())); 5130 5131 5132 // Is marking active? 5133 if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) { 5134 cmpl(in_progress, 0); 5135 } else { 5136 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption"); 5137 cmpb(in_progress, 0); 5138 } 5139 jcc(Assembler::equal, done); 5140 5141 // Do we need to load the previous value? 5142 if (obj != noreg) { 5143 load_heap_oop(pre_val, Address(obj, 0)); 5144 } 5145 5146 // Is the previous value null? 5147 cmpptr(pre_val, (int32_t) NULL_WORD); 5148 jcc(Assembler::equal, done); 5149 5150 // Can we store original value in the thread's buffer? 5151 // Is index == 0? 5152 // (The index field is typed as size_t.) 5153 5154 movptr(tmp, index); // tmp := *index_adr 5155 cmpptr(tmp, 0); // tmp == 0? 5156 jcc(Assembler::equal, runtime); // If yes, goto runtime 5157 5158 subptr(tmp, wordSize); // tmp := tmp - wordSize 5159 movptr(index, tmp); // *index_adr := tmp 5160 addptr(tmp, buffer); // tmp := tmp + *buffer_adr 5161 5162 // Record the previous value 5163 movptr(Address(tmp, 0), pre_val); 5164 jmp(done); 5165 5166 bind(runtime); 5167 // save the live input values 5168 if(tosca_live) push(rax); 5169 5170 if (obj != noreg && obj != rax) 5171 push(obj); 5172 5173 if (pre_val != rax) 5174 push(pre_val); 5175 5176 // Calling the runtime using the regular call_VM_leaf mechanism generates 5177 // code (generated by InterpreterMacroAssember::call_VM_leaf_base) 5178 // that checks that the *(ebp+frame::interpreter_frame_last_sp) == NULL. 5179 // 5180 // If we care generating the pre-barrier without a frame (e.g. in the 5181 // intrinsified Reference.get() routine) then ebp might be pointing to 5182 // the caller frame and so this check will most likely fail at runtime. 5183 // 5184 // Expanding the call directly bypasses the generation of the check. 5185 // So when we do not have have a full interpreter frame on the stack 5186 // expand_call should be passed true. 5187 5188 NOT_LP64( push(thread); ) 5189 5190 if (expand_call) { 5191 LP64_ONLY( assert(pre_val != c_rarg1, "smashed arg"); ) 5192 pass_arg1(this, thread); 5193 pass_arg0(this, pre_val); 5194 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), 2); 5195 } else { 5196 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), pre_val, thread); 5197 } 5198 5199 NOT_LP64( pop(thread); ) 5200 5201 // save the live input values 5202 if (pre_val != rax) 5203 pop(pre_val); 5204 5205 if (obj != noreg && obj != rax) 5206 pop(obj); 5207 5208 if(tosca_live) pop(rax); 5209 5210 bind(done); 5211 } 5212 5213 void MacroAssembler::g1_write_barrier_post(Register store_addr, 5214 Register new_val, 5215 Register thread, 5216 Register tmp, 5217 Register tmp2) { 5218 #ifdef _LP64 5219 assert(thread == r15_thread, "must be"); 5220 #endif // _LP64 5221 5222 Address queue_index(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5223 DirtyCardQueue::byte_offset_of_index())); 5224 Address buffer(thread, in_bytes(JavaThread::dirty_card_queue_offset() + 5225 DirtyCardQueue::byte_offset_of_buf())); 5226 5227 CardTableModRefBS* ct = 5228 barrier_set_cast<CardTableModRefBS>(Universe::heap()->barrier_set()); 5229 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5230 5231 Label done; 5232 Label runtime; 5233 5234 // Does store cross heap regions? 5235 5236 movptr(tmp, store_addr); 5237 xorptr(tmp, new_val); 5238 shrptr(tmp, HeapRegion::LogOfHRGrainBytes); 5239 jcc(Assembler::equal, done); 5240 5241 // crosses regions, storing NULL? 5242 5243 cmpptr(new_val, (int32_t) NULL_WORD); 5244 jcc(Assembler::equal, done); 5245 5246 // storing region crossing non-NULL, is card already dirty? 5247 5248 const Register card_addr = tmp; 5249 const Register cardtable = tmp2; 5250 5251 movptr(card_addr, store_addr); 5252 shrptr(card_addr, CardTableModRefBS::card_shift); 5253 // Do not use ExternalAddress to load 'byte_map_base', since 'byte_map_base' is NOT 5254 // a valid address and therefore is not properly handled by the relocation code. 5255 movptr(cardtable, (intptr_t)ct->byte_map_base); 5256 addptr(card_addr, cardtable); 5257 5258 cmpb(Address(card_addr, 0), (int)G1SATBCardTableModRefBS::g1_young_card_val()); 5259 jcc(Assembler::equal, done); 5260 5261 membar(Assembler::Membar_mask_bits(Assembler::StoreLoad)); 5262 cmpb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5263 jcc(Assembler::equal, done); 5264 5265 5266 // storing a region crossing, non-NULL oop, card is clean. 5267 // dirty card and log. 5268 5269 movb(Address(card_addr, 0), (int)CardTableModRefBS::dirty_card_val()); 5270 5271 cmpl(queue_index, 0); 5272 jcc(Assembler::equal, runtime); 5273 subl(queue_index, wordSize); 5274 movptr(tmp2, buffer); 5275 #ifdef _LP64 5276 movslq(rscratch1, queue_index); 5277 addq(tmp2, rscratch1); 5278 movq(Address(tmp2, 0), card_addr); 5279 #else 5280 addl(tmp2, queue_index); 5281 movl(Address(tmp2, 0), card_addr); 5282 #endif 5283 jmp(done); 5284 5285 bind(runtime); 5286 // save the live input values 5287 push(store_addr); 5288 push(new_val); 5289 #ifdef _LP64 5290 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, r15_thread); 5291 #else 5292 push(thread); 5293 call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), card_addr, thread); 5294 pop(thread); 5295 #endif 5296 pop(new_val); 5297 pop(store_addr); 5298 5299 bind(done); 5300 } 5301 5302 #endif // INCLUDE_ALL_GCS 5303 ////////////////////////////////////////////////////////////////////////////////// 5304 5305 5306 void MacroAssembler::store_check(Register obj, Address dst) { 5307 store_check(obj); 5308 } 5309 5310 void MacroAssembler::store_check(Register obj) { 5311 // Does a store check for the oop in register obj. The content of 5312 // register obj is destroyed afterwards. 5313 BarrierSet* bs = Universe::heap()->barrier_set(); 5314 assert(bs->kind() == BarrierSet::CardTableForRS || 5315 bs->kind() == BarrierSet::CardTableExtension, 5316 "Wrong barrier set kind"); 5317 5318 CardTableModRefBS* ct = barrier_set_cast<CardTableModRefBS>(bs); 5319 assert(sizeof(*ct->byte_map_base) == sizeof(jbyte), "adjust this code"); 5320 5321 shrptr(obj, CardTableModRefBS::card_shift); 5322 5323 Address card_addr; 5324 5325 // The calculation for byte_map_base is as follows: 5326 // byte_map_base = _byte_map - (uintptr_t(low_bound) >> card_shift); 5327 // So this essentially converts an address to a displacement and it will 5328 // never need to be relocated. On 64bit however the value may be too 5329 // large for a 32bit displacement. 5330 intptr_t disp = (intptr_t) ct->byte_map_base; 5331 if (is_simm32(disp)) { 5332 card_addr = Address(noreg, obj, Address::times_1, disp); 5333 } else { 5334 // By doing it as an ExternalAddress 'disp' could be converted to a rip-relative 5335 // displacement and done in a single instruction given favorable mapping and a 5336 // smarter version of as_Address. However, 'ExternalAddress' generates a relocation 5337 // entry and that entry is not properly handled by the relocation code. 5338 AddressLiteral cardtable((address)ct->byte_map_base, relocInfo::none); 5339 Address index(noreg, obj, Address::times_1); 5340 card_addr = as_Address(ArrayAddress(cardtable, index)); 5341 } 5342 5343 int dirty = CardTableModRefBS::dirty_card_val(); 5344 if (UseCondCardMark) { 5345 Label L_already_dirty; 5346 if (UseConcMarkSweepGC) { 5347 membar(Assembler::StoreLoad); 5348 } 5349 cmpb(card_addr, dirty); 5350 jcc(Assembler::equal, L_already_dirty); 5351 movb(card_addr, dirty); 5352 bind(L_already_dirty); 5353 } else { 5354 movb(card_addr, dirty); 5355 } 5356 } 5357 5358 void MacroAssembler::subptr(Register dst, int32_t imm32) { 5359 LP64_ONLY(subq(dst, imm32)) NOT_LP64(subl(dst, imm32)); 5360 } 5361 5362 // Force generation of a 4 byte immediate value even if it fits into 8bit 5363 void MacroAssembler::subptr_imm32(Register dst, int32_t imm32) { 5364 LP64_ONLY(subq_imm32(dst, imm32)) NOT_LP64(subl_imm32(dst, imm32)); 5365 } 5366 5367 void MacroAssembler::subptr(Register dst, Register src) { 5368 LP64_ONLY(subq(dst, src)) NOT_LP64(subl(dst, src)); 5369 } 5370 5371 // C++ bool manipulation 5372 void MacroAssembler::testbool(Register dst) { 5373 if(sizeof(bool) == 1) 5374 testb(dst, 0xff); 5375 else if(sizeof(bool) == 2) { 5376 // testw implementation needed for two byte bools 5377 ShouldNotReachHere(); 5378 } else if(sizeof(bool) == 4) 5379 testl(dst, dst); 5380 else 5381 // unsupported 5382 ShouldNotReachHere(); 5383 } 5384 5385 void MacroAssembler::testptr(Register dst, Register src) { 5386 LP64_ONLY(testq(dst, src)) NOT_LP64(testl(dst, src)); 5387 } 5388 5389 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes. 5390 void MacroAssembler::tlab_allocate(Register obj, 5391 Register var_size_in_bytes, 5392 int con_size_in_bytes, 5393 Register t1, 5394 Register t2, 5395 Label& slow_case) { 5396 assert_different_registers(obj, t1, t2); 5397 assert_different_registers(obj, var_size_in_bytes, t1); 5398 Register end = t2; 5399 Register thread = NOT_LP64(t1) LP64_ONLY(r15_thread); 5400 5401 verify_tlab(); 5402 5403 NOT_LP64(get_thread(thread)); 5404 5405 movptr(obj, Address(thread, JavaThread::tlab_top_offset())); 5406 if (var_size_in_bytes == noreg) { 5407 lea(end, Address(obj, con_size_in_bytes)); 5408 } else { 5409 lea(end, Address(obj, var_size_in_bytes, Address::times_1)); 5410 } 5411 cmpptr(end, Address(thread, JavaThread::tlab_end_offset())); 5412 jcc(Assembler::above, slow_case); 5413 5414 // update the tlab top pointer 5415 movptr(Address(thread, JavaThread::tlab_top_offset()), end); 5416 5417 // recover var_size_in_bytes if necessary 5418 if (var_size_in_bytes == end) { 5419 subptr(var_size_in_bytes, obj); 5420 } 5421 verify_tlab(); 5422 } 5423 5424 // Preserves rbx, and rdx. 5425 Register MacroAssembler::tlab_refill(Label& retry, 5426 Label& try_eden, 5427 Label& slow_case) { 5428 Register top = rax; 5429 Register t1 = rcx; // object size 5430 Register t2 = rsi; 5431 Register thread_reg = NOT_LP64(rdi) LP64_ONLY(r15_thread); 5432 assert_different_registers(top, thread_reg, t1, t2, /* preserve: */ rbx, rdx); 5433 Label do_refill, discard_tlab; 5434 5435 if (!Universe::heap()->supports_inline_contig_alloc()) { 5436 // No allocation in the shared eden. 5437 jmp(slow_case); 5438 } 5439 5440 NOT_LP64(get_thread(thread_reg)); 5441 5442 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 5443 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 5444 5445 // calculate amount of free space 5446 subptr(t1, top); 5447 shrptr(t1, LogHeapWordSize); 5448 5449 // Retain tlab and allocate object in shared space if 5450 // the amount free in the tlab is too large to discard. 5451 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset()))); 5452 jcc(Assembler::lessEqual, discard_tlab); 5453 5454 // Retain 5455 // %%% yuck as movptr... 5456 movptr(t2, (int32_t) ThreadLocalAllocBuffer::refill_waste_limit_increment()); 5457 addptr(Address(thread_reg, in_bytes(JavaThread::tlab_refill_waste_limit_offset())), t2); 5458 if (TLABStats) { 5459 // increment number of slow_allocations 5460 addl(Address(thread_reg, in_bytes(JavaThread::tlab_slow_allocations_offset())), 1); 5461 } 5462 jmp(try_eden); 5463 5464 bind(discard_tlab); 5465 if (TLABStats) { 5466 // increment number of refills 5467 addl(Address(thread_reg, in_bytes(JavaThread::tlab_number_of_refills_offset())), 1); 5468 // accumulate wastage -- t1 is amount free in tlab 5469 addl(Address(thread_reg, in_bytes(JavaThread::tlab_fast_refill_waste_offset())), t1); 5470 } 5471 5472 // if tlab is currently allocated (top or end != null) then 5473 // fill [top, end + alignment_reserve) with array object 5474 testptr(top, top); 5475 jcc(Assembler::zero, do_refill); 5476 5477 // set up the mark word 5478 movptr(Address(top, oopDesc::mark_offset_in_bytes()), (intptr_t)markOopDesc::prototype()->copy_set_hash(0x2)); 5479 // set the length to the remaining space 5480 subptr(t1, typeArrayOopDesc::header_size(T_INT)); 5481 addptr(t1, (int32_t)ThreadLocalAllocBuffer::alignment_reserve()); 5482 shlptr(t1, log2_intptr(HeapWordSize/sizeof(jint))); 5483 movl(Address(top, arrayOopDesc::length_offset_in_bytes()), t1); 5484 // set klass to intArrayKlass 5485 // dubious reloc why not an oop reloc? 5486 movptr(t1, ExternalAddress((address)Universe::intArrayKlassObj_addr())); 5487 // store klass last. concurrent gcs assumes klass length is valid if 5488 // klass field is not null. 5489 store_klass(top, t1); 5490 5491 movptr(t1, top); 5492 subptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5493 incr_allocated_bytes(thread_reg, t1, 0); 5494 5495 // refill the tlab with an eden allocation 5496 bind(do_refill); 5497 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5498 shlptr(t1, LogHeapWordSize); 5499 // allocate new tlab, address returned in top 5500 eden_allocate(top, t1, 0, t2, slow_case); 5501 5502 // Check that t1 was preserved in eden_allocate. 5503 #ifdef ASSERT 5504 if (UseTLAB) { 5505 Label ok; 5506 Register tsize = rsi; 5507 assert_different_registers(tsize, thread_reg, t1); 5508 push(tsize); 5509 movptr(tsize, Address(thread_reg, in_bytes(JavaThread::tlab_size_offset()))); 5510 shlptr(tsize, LogHeapWordSize); 5511 cmpptr(t1, tsize); 5512 jcc(Assembler::equal, ok); 5513 STOP("assert(t1 != tlab size)"); 5514 should_not_reach_here(); 5515 5516 bind(ok); 5517 pop(tsize); 5518 } 5519 #endif 5520 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_start_offset())), top); 5521 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_top_offset())), top); 5522 addptr(top, t1); 5523 subptr(top, (int32_t)ThreadLocalAllocBuffer::alignment_reserve_in_bytes()); 5524 movptr(Address(thread_reg, in_bytes(JavaThread::tlab_end_offset())), top); 5525 5526 if (ZeroTLAB) { 5527 // This is a fast TLAB refill, therefore the GC is not notified of it. 5528 // So compiled code must fill the new TLAB with zeroes. 5529 movptr(top, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 5530 zero_memory(top, t1, 0, t2); 5531 } 5532 5533 verify_tlab(); 5534 jmp(retry); 5535 5536 return thread_reg; // for use by caller 5537 } 5538 5539 // Preserves the contents of address, destroys the contents length_in_bytes and temp. 5540 void MacroAssembler::zero_memory(Register address, Register length_in_bytes, int offset_in_bytes, Register temp) { 5541 assert(address != length_in_bytes && address != temp && temp != length_in_bytes, "registers must be different"); 5542 assert((offset_in_bytes & (BytesPerWord - 1)) == 0, "offset must be a multiple of BytesPerWord"); 5543 Label done; 5544 5545 testptr(length_in_bytes, length_in_bytes); 5546 jcc(Assembler::zero, done); 5547 5548 // initialize topmost word, divide index by 2, check if odd and test if zero 5549 // note: for the remaining code to work, index must be a multiple of BytesPerWord 5550 #ifdef ASSERT 5551 { 5552 Label L; 5553 testptr(length_in_bytes, BytesPerWord - 1); 5554 jcc(Assembler::zero, L); 5555 stop("length must be a multiple of BytesPerWord"); 5556 bind(L); 5557 } 5558 #endif 5559 Register index = length_in_bytes; 5560 xorptr(temp, temp); // use _zero reg to clear memory (shorter code) 5561 if (UseIncDec) { 5562 shrptr(index, 3); // divide by 8/16 and set carry flag if bit 2 was set 5563 } else { 5564 shrptr(index, 2); // use 2 instructions to avoid partial flag stall 5565 shrptr(index, 1); 5566 } 5567 #ifndef _LP64 5568 // index could have not been a multiple of 8 (i.e., bit 2 was set) 5569 { 5570 Label even; 5571 // note: if index was a multiple of 8, then it cannot 5572 // be 0 now otherwise it must have been 0 before 5573 // => if it is even, we don't need to check for 0 again 5574 jcc(Assembler::carryClear, even); 5575 // clear topmost word (no jump would be needed if conditional assignment worked here) 5576 movptr(Address(address, index, Address::times_8, offset_in_bytes - 0*BytesPerWord), temp); 5577 // index could be 0 now, must check again 5578 jcc(Assembler::zero, done); 5579 bind(even); 5580 } 5581 #endif // !_LP64 5582 // initialize remaining object fields: index is a multiple of 2 now 5583 { 5584 Label loop; 5585 bind(loop); 5586 movptr(Address(address, index, Address::times_8, offset_in_bytes - 1*BytesPerWord), temp); 5587 NOT_LP64(movptr(Address(address, index, Address::times_8, offset_in_bytes - 2*BytesPerWord), temp);) 5588 decrement(index); 5589 jcc(Assembler::notZero, loop); 5590 } 5591 5592 bind(done); 5593 } 5594 5595 void MacroAssembler::incr_allocated_bytes(Register thread, 5596 Register var_size_in_bytes, 5597 int con_size_in_bytes, 5598 Register t1) { 5599 if (!thread->is_valid()) { 5600 #ifdef _LP64 5601 thread = r15_thread; 5602 #else 5603 assert(t1->is_valid(), "need temp reg"); 5604 thread = t1; 5605 get_thread(thread); 5606 #endif 5607 } 5608 5609 #ifdef _LP64 5610 if (var_size_in_bytes->is_valid()) { 5611 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5612 } else { 5613 addq(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5614 } 5615 #else 5616 if (var_size_in_bytes->is_valid()) { 5617 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), var_size_in_bytes); 5618 } else { 5619 addl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())), con_size_in_bytes); 5620 } 5621 adcl(Address(thread, in_bytes(JavaThread::allocated_bytes_offset())+4), 0); 5622 #endif 5623 } 5624 5625 void MacroAssembler::fp_runtime_fallback(address runtime_entry, int nb_args, int num_fpu_regs_in_use) { 5626 pusha(); 5627 5628 // if we are coming from c1, xmm registers may be live 5629 int num_xmm_regs = LP64_ONLY(16) NOT_LP64(8); 5630 if (UseAVX > 2) { 5631 num_xmm_regs = LP64_ONLY(32) NOT_LP64(8); 5632 } 5633 5634 if (UseSSE == 1) { 5635 subptr(rsp, sizeof(jdouble)*8); 5636 for (int n = 0; n < 8; n++) { 5637 movflt(Address(rsp, n*sizeof(jdouble)), as_XMMRegister(n)); 5638 } 5639 } else if (UseSSE >= 2) { 5640 if (UseAVX > 2) { 5641 push(rbx); 5642 movl(rbx, 0xffff); 5643 kmovwl(k1, rbx); 5644 pop(rbx); 5645 } 5646 #ifdef COMPILER2 5647 if (MaxVectorSize > 16) { 5648 if(UseAVX > 2) { 5649 // Save upper half of ZMM registers 5650 subptr(rsp, 32*num_xmm_regs); 5651 for (int n = 0; n < num_xmm_regs; n++) { 5652 vextractf64x4h(Address(rsp, n*32), as_XMMRegister(n), 1); 5653 } 5654 } 5655 assert(UseAVX > 0, "256 bit vectors are supported only with AVX"); 5656 // Save upper half of YMM registers 5657 subptr(rsp, 16*num_xmm_regs); 5658 for (int n = 0; n < num_xmm_regs; n++) { 5659 vextractf128h(Address(rsp, n*16), as_XMMRegister(n)); 5660 } 5661 } 5662 #endif 5663 // Save whole 128bit (16 bytes) XMM registers 5664 subptr(rsp, 16*num_xmm_regs); 5665 #ifdef _LP64 5666 if (VM_Version::supports_evex()) { 5667 for (int n = 0; n < num_xmm_regs; n++) { 5668 vextractf32x4h(Address(rsp, n*16), as_XMMRegister(n), 0); 5669 } 5670 } else { 5671 for (int n = 0; n < num_xmm_regs; n++) { 5672 movdqu(Address(rsp, n*16), as_XMMRegister(n)); 5673 } 5674 } 5675 #else 5676 for (int n = 0; n < num_xmm_regs; n++) { 5677 movdqu(Address(rsp, n*16), as_XMMRegister(n)); 5678 } 5679 #endif 5680 } 5681 5682 // Preserve registers across runtime call 5683 int incoming_argument_and_return_value_offset = -1; 5684 if (num_fpu_regs_in_use > 1) { 5685 // Must preserve all other FPU regs (could alternatively convert 5686 // SharedRuntime::dsin, dcos etc. into assembly routines known not to trash 5687 // FPU state, but can not trust C compiler) 5688 NEEDS_CLEANUP; 5689 // NOTE that in this case we also push the incoming argument(s) to 5690 // the stack and restore it later; we also use this stack slot to 5691 // hold the return value from dsin, dcos etc. 5692 for (int i = 0; i < num_fpu_regs_in_use; i++) { 5693 subptr(rsp, sizeof(jdouble)); 5694 fstp_d(Address(rsp, 0)); 5695 } 5696 incoming_argument_and_return_value_offset = sizeof(jdouble)*(num_fpu_regs_in_use-1); 5697 for (int i = nb_args-1; i >= 0; i--) { 5698 fld_d(Address(rsp, incoming_argument_and_return_value_offset-i*sizeof(jdouble))); 5699 } 5700 } 5701 5702 subptr(rsp, nb_args*sizeof(jdouble)); 5703 for (int i = 0; i < nb_args; i++) { 5704 fstp_d(Address(rsp, i*sizeof(jdouble))); 5705 } 5706 5707 #ifdef _LP64 5708 if (nb_args > 0) { 5709 movdbl(xmm0, Address(rsp, 0)); 5710 } 5711 if (nb_args > 1) { 5712 movdbl(xmm1, Address(rsp, sizeof(jdouble))); 5713 } 5714 assert(nb_args <= 2, "unsupported number of args"); 5715 #endif // _LP64 5716 5717 // NOTE: we must not use call_VM_leaf here because that requires a 5718 // complete interpreter frame in debug mode -- same bug as 4387334 5719 // MacroAssembler::call_VM_leaf_base is perfectly safe and will 5720 // do proper 64bit abi 5721 5722 NEEDS_CLEANUP; 5723 // Need to add stack banging before this runtime call if it needs to 5724 // be taken; however, there is no generic stack banging routine at 5725 // the MacroAssembler level 5726 5727 MacroAssembler::call_VM_leaf_base(runtime_entry, 0); 5728 5729 #ifdef _LP64 5730 movsd(Address(rsp, 0), xmm0); 5731 fld_d(Address(rsp, 0)); 5732 #endif // _LP64 5733 addptr(rsp, sizeof(jdouble)*nb_args); 5734 if (num_fpu_regs_in_use > 1) { 5735 // Must save return value to stack and then restore entire FPU 5736 // stack except incoming arguments 5737 fstp_d(Address(rsp, incoming_argument_and_return_value_offset)); 5738 for (int i = 0; i < num_fpu_regs_in_use - nb_args; i++) { 5739 fld_d(Address(rsp, 0)); 5740 addptr(rsp, sizeof(jdouble)); 5741 } 5742 fld_d(Address(rsp, (nb_args-1)*sizeof(jdouble))); 5743 addptr(rsp, sizeof(jdouble)*nb_args); 5744 } 5745 5746 if (UseSSE == 1) { 5747 for (int n = 0; n < 8; n++) { 5748 movflt(as_XMMRegister(n), Address(rsp, n*sizeof(jdouble))); 5749 } 5750 addptr(rsp, sizeof(jdouble)*8); 5751 } else if (UseSSE >= 2) { 5752 // Restore whole 128bit (16 bytes) XMM registers 5753 #ifdef _LP64 5754 if (VM_Version::supports_evex()) { 5755 for (int n = 0; n < num_xmm_regs; n++) { 5756 vinsertf32x4h(as_XMMRegister(n), Address(rsp, n*16), 0); 5757 } 5758 } else { 5759 for (int n = 0; n < num_xmm_regs; n++) { 5760 movdqu(as_XMMRegister(n), Address(rsp, n*16)); 5761 } 5762 } 5763 #else 5764 for (int n = 0; n < num_xmm_regs; n++) { 5765 movdqu(as_XMMRegister(n), Address(rsp, n*16)); 5766 } 5767 #endif 5768 addptr(rsp, 16*num_xmm_regs); 5769 5770 #ifdef COMPILER2 5771 if (MaxVectorSize > 16) { 5772 // Restore upper half of YMM registers. 5773 for (int n = 0; n < num_xmm_regs; n++) { 5774 vinsertf128h(as_XMMRegister(n), Address(rsp, n*16)); 5775 } 5776 addptr(rsp, 16*num_xmm_regs); 5777 if(UseAVX > 2) { 5778 for (int n = 0; n < num_xmm_regs; n++) { 5779 vinsertf64x4h(as_XMMRegister(n), Address(rsp, n*32), 1); 5780 } 5781 addptr(rsp, 32*num_xmm_regs); 5782 } 5783 } 5784 #endif 5785 } 5786 popa(); 5787 } 5788 5789 static const double pi_4 = 0.7853981633974483; 5790 5791 void MacroAssembler::trigfunc(char trig, int num_fpu_regs_in_use) { 5792 // A hand-coded argument reduction for values in fabs(pi/4, pi/2) 5793 // was attempted in this code; unfortunately it appears that the 5794 // switch to 80-bit precision and back causes this to be 5795 // unprofitable compared with simply performing a runtime call if 5796 // the argument is out of the (-pi/4, pi/4) range. 5797 5798 Register tmp = noreg; 5799 if (!VM_Version::supports_cmov()) { 5800 // fcmp needs a temporary so preserve rbx, 5801 tmp = rbx; 5802 push(tmp); 5803 } 5804 5805 Label slow_case, done; 5806 if (trig == 't') { 5807 ExternalAddress pi4_adr = (address)&pi_4; 5808 if (reachable(pi4_adr)) { 5809 // x ?<= pi/4 5810 fld_d(pi4_adr); 5811 fld_s(1); // Stack: X PI/4 X 5812 fabs(); // Stack: |X| PI/4 X 5813 fcmp(tmp); 5814 jcc(Assembler::above, slow_case); 5815 5816 // fastest case: -pi/4 <= x <= pi/4 5817 ftan(); 5818 5819 jmp(done); 5820 } 5821 } 5822 // slow case: runtime call 5823 bind(slow_case); 5824 5825 switch(trig) { 5826 case 's': 5827 { 5828 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dsin), 1, num_fpu_regs_in_use); 5829 } 5830 break; 5831 case 'c': 5832 { 5833 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dcos), 1, num_fpu_regs_in_use); 5834 } 5835 break; 5836 case 't': 5837 { 5838 fp_runtime_fallback(CAST_FROM_FN_PTR(address, SharedRuntime::dtan), 1, num_fpu_regs_in_use); 5839 } 5840 break; 5841 default: 5842 assert(false, "bad intrinsic"); 5843 break; 5844 } 5845 5846 // Come here with result in F-TOS 5847 bind(done); 5848 5849 if (tmp != noreg) { 5850 pop(tmp); 5851 } 5852 } 5853 5854 // Look up the method for a megamorphic invokeinterface call. 5855 // The target method is determined by <intf_klass, itable_index>. 5856 // The receiver klass is in recv_klass. 5857 // On success, the result will be in method_result, and execution falls through. 5858 // On failure, execution transfers to the given label. 5859 void MacroAssembler::lookup_interface_method(Register recv_klass, 5860 Register intf_klass, 5861 RegisterOrConstant itable_index, 5862 Register method_result, 5863 Register scan_temp, 5864 Label& L_no_such_interface) { 5865 assert_different_registers(recv_klass, intf_klass, method_result, scan_temp); 5866 assert(itable_index.is_constant() || itable_index.as_register() == method_result, 5867 "caller must use same register for non-constant itable index as for method"); 5868 5869 // Compute start of first itableOffsetEntry (which is at the end of the vtable) 5870 int vtable_base = in_bytes(Klass::vtable_start_offset()); 5871 int itentry_off = itableMethodEntry::method_offset_in_bytes(); 5872 int scan_step = itableOffsetEntry::size() * wordSize; 5873 int vte_size = vtableEntry::size_in_bytes(); 5874 Address::ScaleFactor times_vte_scale = Address::times_ptr; 5875 assert(vte_size == wordSize, "else adjust times_vte_scale"); 5876 5877 movl(scan_temp, Address(recv_klass, Klass::vtable_length_offset())); 5878 5879 // %%% Could store the aligned, prescaled offset in the klassoop. 5880 lea(scan_temp, Address(recv_klass, scan_temp, times_vte_scale, vtable_base)); 5881 5882 // Adjust recv_klass by scaled itable_index, so we can free itable_index. 5883 assert(itableMethodEntry::size() * wordSize == wordSize, "adjust the scaling in the code below"); 5884 lea(recv_klass, Address(recv_klass, itable_index, Address::times_ptr, itentry_off)); 5885 5886 // for (scan = klass->itable(); scan->interface() != NULL; scan += scan_step) { 5887 // if (scan->interface() == intf) { 5888 // result = (klass + scan->offset() + itable_index); 5889 // } 5890 // } 5891 Label search, found_method; 5892 5893 for (int peel = 1; peel >= 0; peel--) { 5894 movptr(method_result, Address(scan_temp, itableOffsetEntry::interface_offset_in_bytes())); 5895 cmpptr(intf_klass, method_result); 5896 5897 if (peel) { 5898 jccb(Assembler::equal, found_method); 5899 } else { 5900 jccb(Assembler::notEqual, search); 5901 // (invert the test to fall through to found_method...) 5902 } 5903 5904 if (!peel) break; 5905 5906 bind(search); 5907 5908 // Check that the previous entry is non-null. A null entry means that 5909 // the receiver class doesn't implement the interface, and wasn't the 5910 // same as when the caller was compiled. 5911 testptr(method_result, method_result); 5912 jcc(Assembler::zero, L_no_such_interface); 5913 addptr(scan_temp, scan_step); 5914 } 5915 5916 bind(found_method); 5917 5918 // Got a hit. 5919 movl(scan_temp, Address(scan_temp, itableOffsetEntry::offset_offset_in_bytes())); 5920 movptr(method_result, Address(recv_klass, scan_temp, Address::times_1)); 5921 } 5922 5923 5924 // virtual method calling 5925 void MacroAssembler::lookup_virtual_method(Register recv_klass, 5926 RegisterOrConstant vtable_index, 5927 Register method_result) { 5928 const int base = in_bytes(Klass::vtable_start_offset()); 5929 assert(vtableEntry::size() * wordSize == wordSize, "else adjust the scaling in the code below"); 5930 Address vtable_entry_addr(recv_klass, 5931 vtable_index, Address::times_ptr, 5932 base + vtableEntry::method_offset_in_bytes()); 5933 movptr(method_result, vtable_entry_addr); 5934 } 5935 5936 5937 void MacroAssembler::check_klass_subtype(Register sub_klass, 5938 Register super_klass, 5939 Register temp_reg, 5940 Label& L_success) { 5941 Label L_failure; 5942 check_klass_subtype_fast_path(sub_klass, super_klass, temp_reg, &L_success, &L_failure, NULL); 5943 check_klass_subtype_slow_path(sub_klass, super_klass, temp_reg, noreg, &L_success, NULL); 5944 bind(L_failure); 5945 } 5946 5947 5948 void MacroAssembler::check_klass_subtype_fast_path(Register sub_klass, 5949 Register super_klass, 5950 Register temp_reg, 5951 Label* L_success, 5952 Label* L_failure, 5953 Label* L_slow_path, 5954 RegisterOrConstant super_check_offset) { 5955 assert_different_registers(sub_klass, super_klass, temp_reg); 5956 bool must_load_sco = (super_check_offset.constant_or_zero() == -1); 5957 if (super_check_offset.is_register()) { 5958 assert_different_registers(sub_klass, super_klass, 5959 super_check_offset.as_register()); 5960 } else if (must_load_sco) { 5961 assert(temp_reg != noreg, "supply either a temp or a register offset"); 5962 } 5963 5964 Label L_fallthrough; 5965 int label_nulls = 0; 5966 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 5967 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 5968 if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; } 5969 assert(label_nulls <= 1, "at most one NULL in the batch"); 5970 5971 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 5972 int sco_offset = in_bytes(Klass::super_check_offset_offset()); 5973 Address super_check_offset_addr(super_klass, sco_offset); 5974 5975 // Hacked jcc, which "knows" that L_fallthrough, at least, is in 5976 // range of a jccb. If this routine grows larger, reconsider at 5977 // least some of these. 5978 #define local_jcc(assembler_cond, label) \ 5979 if (&(label) == &L_fallthrough) jccb(assembler_cond, label); \ 5980 else jcc( assembler_cond, label) /*omit semi*/ 5981 5982 // Hacked jmp, which may only be used just before L_fallthrough. 5983 #define final_jmp(label) \ 5984 if (&(label) == &L_fallthrough) { /*do nothing*/ } \ 5985 else jmp(label) /*omit semi*/ 5986 5987 // If the pointers are equal, we are done (e.g., String[] elements). 5988 // This self-check enables sharing of secondary supertype arrays among 5989 // non-primary types such as array-of-interface. Otherwise, each such 5990 // type would need its own customized SSA. 5991 // We move this check to the front of the fast path because many 5992 // type checks are in fact trivially successful in this manner, 5993 // so we get a nicely predicted branch right at the start of the check. 5994 cmpptr(sub_klass, super_klass); 5995 local_jcc(Assembler::equal, *L_success); 5996 5997 // Check the supertype display: 5998 if (must_load_sco) { 5999 // Positive movl does right thing on LP64. 6000 movl(temp_reg, super_check_offset_addr); 6001 super_check_offset = RegisterOrConstant(temp_reg); 6002 } 6003 Address super_check_addr(sub_klass, super_check_offset, Address::times_1, 0); 6004 cmpptr(super_klass, super_check_addr); // load displayed supertype 6005 6006 // This check has worked decisively for primary supers. 6007 // Secondary supers are sought in the super_cache ('super_cache_addr'). 6008 // (Secondary supers are interfaces and very deeply nested subtypes.) 6009 // This works in the same check above because of a tricky aliasing 6010 // between the super_cache and the primary super display elements. 6011 // (The 'super_check_addr' can address either, as the case requires.) 6012 // Note that the cache is updated below if it does not help us find 6013 // what we need immediately. 6014 // So if it was a primary super, we can just fail immediately. 6015 // Otherwise, it's the slow path for us (no success at this point). 6016 6017 if (super_check_offset.is_register()) { 6018 local_jcc(Assembler::equal, *L_success); 6019 cmpl(super_check_offset.as_register(), sc_offset); 6020 if (L_failure == &L_fallthrough) { 6021 local_jcc(Assembler::equal, *L_slow_path); 6022 } else { 6023 local_jcc(Assembler::notEqual, *L_failure); 6024 final_jmp(*L_slow_path); 6025 } 6026 } else if (super_check_offset.as_constant() == sc_offset) { 6027 // Need a slow path; fast failure is impossible. 6028 if (L_slow_path == &L_fallthrough) { 6029 local_jcc(Assembler::equal, *L_success); 6030 } else { 6031 local_jcc(Assembler::notEqual, *L_slow_path); 6032 final_jmp(*L_success); 6033 } 6034 } else { 6035 // No slow path; it's a fast decision. 6036 if (L_failure == &L_fallthrough) { 6037 local_jcc(Assembler::equal, *L_success); 6038 } else { 6039 local_jcc(Assembler::notEqual, *L_failure); 6040 final_jmp(*L_success); 6041 } 6042 } 6043 6044 bind(L_fallthrough); 6045 6046 #undef local_jcc 6047 #undef final_jmp 6048 } 6049 6050 6051 void MacroAssembler::check_klass_subtype_slow_path(Register sub_klass, 6052 Register super_klass, 6053 Register temp_reg, 6054 Register temp2_reg, 6055 Label* L_success, 6056 Label* L_failure, 6057 bool set_cond_codes) { 6058 assert_different_registers(sub_klass, super_klass, temp_reg); 6059 if (temp2_reg != noreg) 6060 assert_different_registers(sub_klass, super_klass, temp_reg, temp2_reg); 6061 #define IS_A_TEMP(reg) ((reg) == temp_reg || (reg) == temp2_reg) 6062 6063 Label L_fallthrough; 6064 int label_nulls = 0; 6065 if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; } 6066 if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; } 6067 assert(label_nulls <= 1, "at most one NULL in the batch"); 6068 6069 // a couple of useful fields in sub_klass: 6070 int ss_offset = in_bytes(Klass::secondary_supers_offset()); 6071 int sc_offset = in_bytes(Klass::secondary_super_cache_offset()); 6072 Address secondary_supers_addr(sub_klass, ss_offset); 6073 Address super_cache_addr( sub_klass, sc_offset); 6074 6075 // Do a linear scan of the secondary super-klass chain. 6076 // This code is rarely used, so simplicity is a virtue here. 6077 // The repne_scan instruction uses fixed registers, which we must spill. 6078 // Don't worry too much about pre-existing connections with the input regs. 6079 6080 assert(sub_klass != rax, "killed reg"); // killed by mov(rax, super) 6081 assert(sub_klass != rcx, "killed reg"); // killed by lea(rcx, &pst_counter) 6082 6083 // Get super_klass value into rax (even if it was in rdi or rcx). 6084 bool pushed_rax = false, pushed_rcx = false, pushed_rdi = false; 6085 if (super_klass != rax || UseCompressedOops) { 6086 if (!IS_A_TEMP(rax)) { push(rax); pushed_rax = true; } 6087 mov(rax, super_klass); 6088 } 6089 if (!IS_A_TEMP(rcx)) { push(rcx); pushed_rcx = true; } 6090 if (!IS_A_TEMP(rdi)) { push(rdi); pushed_rdi = true; } 6091 6092 #ifndef PRODUCT 6093 int* pst_counter = &SharedRuntime::_partial_subtype_ctr; 6094 ExternalAddress pst_counter_addr((address) pst_counter); 6095 NOT_LP64( incrementl(pst_counter_addr) ); 6096 LP64_ONLY( lea(rcx, pst_counter_addr) ); 6097 LP64_ONLY( incrementl(Address(rcx, 0)) ); 6098 #endif //PRODUCT 6099 6100 // We will consult the secondary-super array. 6101 movptr(rdi, secondary_supers_addr); 6102 // Load the array length. (Positive movl does right thing on LP64.) 6103 movl(rcx, Address(rdi, Array<Klass*>::length_offset_in_bytes())); 6104 // Skip to start of data. 6105 addptr(rdi, Array<Klass*>::base_offset_in_bytes()); 6106 6107 // Scan RCX words at [RDI] for an occurrence of RAX. 6108 // Set NZ/Z based on last compare. 6109 // Z flag value will not be set by 'repne' if RCX == 0 since 'repne' does 6110 // not change flags (only scas instruction which is repeated sets flags). 6111 // Set Z = 0 (not equal) before 'repne' to indicate that class was not found. 6112 6113 testptr(rax,rax); // Set Z = 0 6114 repne_scan(); 6115 6116 // Unspill the temp. registers: 6117 if (pushed_rdi) pop(rdi); 6118 if (pushed_rcx) pop(rcx); 6119 if (pushed_rax) pop(rax); 6120 6121 if (set_cond_codes) { 6122 // Special hack for the AD files: rdi is guaranteed non-zero. 6123 assert(!pushed_rdi, "rdi must be left non-NULL"); 6124 // Also, the condition codes are properly set Z/NZ on succeed/failure. 6125 } 6126 6127 if (L_failure == &L_fallthrough) 6128 jccb(Assembler::notEqual, *L_failure); 6129 else jcc(Assembler::notEqual, *L_failure); 6130 6131 // Success. Cache the super we found and proceed in triumph. 6132 movptr(super_cache_addr, super_klass); 6133 6134 if (L_success != &L_fallthrough) { 6135 jmp(*L_success); 6136 } 6137 6138 #undef IS_A_TEMP 6139 6140 bind(L_fallthrough); 6141 } 6142 6143 6144 void MacroAssembler::cmov32(Condition cc, Register dst, Address src) { 6145 if (VM_Version::supports_cmov()) { 6146 cmovl(cc, dst, src); 6147 } else { 6148 Label L; 6149 jccb(negate_condition(cc), L); 6150 movl(dst, src); 6151 bind(L); 6152 } 6153 } 6154 6155 void MacroAssembler::cmov32(Condition cc, Register dst, Register src) { 6156 if (VM_Version::supports_cmov()) { 6157 cmovl(cc, dst, src); 6158 } else { 6159 Label L; 6160 jccb(negate_condition(cc), L); 6161 movl(dst, src); 6162 bind(L); 6163 } 6164 } 6165 6166 void MacroAssembler::verify_oop(Register reg, const char* s) { 6167 if (!VerifyOops) return; 6168 6169 // Pass register number to verify_oop_subroutine 6170 const char* b = NULL; 6171 { 6172 ResourceMark rm; 6173 stringStream ss; 6174 ss.print("verify_oop: %s: %s", reg->name(), s); 6175 b = code_string(ss.as_string()); 6176 } 6177 BLOCK_COMMENT("verify_oop {"); 6178 #ifdef _LP64 6179 push(rscratch1); // save r10, trashed by movptr() 6180 #endif 6181 push(rax); // save rax, 6182 push(reg); // pass register argument 6183 ExternalAddress buffer((address) b); 6184 // avoid using pushptr, as it modifies scratch registers 6185 // and our contract is not to modify anything 6186 movptr(rax, buffer.addr()); 6187 push(rax); 6188 // call indirectly to solve generation ordering problem 6189 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6190 call(rax); 6191 // Caller pops the arguments (oop, message) and restores rax, r10 6192 BLOCK_COMMENT("} verify_oop"); 6193 } 6194 6195 6196 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr, 6197 Register tmp, 6198 int offset) { 6199 intptr_t value = *delayed_value_addr; 6200 if (value != 0) 6201 return RegisterOrConstant(value + offset); 6202 6203 // load indirectly to solve generation ordering problem 6204 movptr(tmp, ExternalAddress((address) delayed_value_addr)); 6205 6206 #ifdef ASSERT 6207 { Label L; 6208 testptr(tmp, tmp); 6209 if (WizardMode) { 6210 const char* buf = NULL; 6211 { 6212 ResourceMark rm; 6213 stringStream ss; 6214 ss.print("DelayedValue=" INTPTR_FORMAT, delayed_value_addr[1]); 6215 buf = code_string(ss.as_string()); 6216 } 6217 jcc(Assembler::notZero, L); 6218 STOP(buf); 6219 } else { 6220 jccb(Assembler::notZero, L); 6221 hlt(); 6222 } 6223 bind(L); 6224 } 6225 #endif 6226 6227 if (offset != 0) 6228 addptr(tmp, offset); 6229 6230 return RegisterOrConstant(tmp); 6231 } 6232 6233 6234 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot, 6235 int extra_slot_offset) { 6236 // cf. TemplateTable::prepare_invoke(), if (load_receiver). 6237 int stackElementSize = Interpreter::stackElementSize; 6238 int offset = Interpreter::expr_offset_in_bytes(extra_slot_offset+0); 6239 #ifdef ASSERT 6240 int offset1 = Interpreter::expr_offset_in_bytes(extra_slot_offset+1); 6241 assert(offset1 - offset == stackElementSize, "correct arithmetic"); 6242 #endif 6243 Register scale_reg = noreg; 6244 Address::ScaleFactor scale_factor = Address::no_scale; 6245 if (arg_slot.is_constant()) { 6246 offset += arg_slot.as_constant() * stackElementSize; 6247 } else { 6248 scale_reg = arg_slot.as_register(); 6249 scale_factor = Address::times(stackElementSize); 6250 } 6251 offset += wordSize; // return PC is on stack 6252 return Address(rsp, scale_reg, scale_factor, offset); 6253 } 6254 6255 6256 void MacroAssembler::verify_oop_addr(Address addr, const char* s) { 6257 if (!VerifyOops) return; 6258 6259 // Address adjust(addr.base(), addr.index(), addr.scale(), addr.disp() + BytesPerWord); 6260 // Pass register number to verify_oop_subroutine 6261 const char* b = NULL; 6262 { 6263 ResourceMark rm; 6264 stringStream ss; 6265 ss.print("verify_oop_addr: %s", s); 6266 b = code_string(ss.as_string()); 6267 } 6268 #ifdef _LP64 6269 push(rscratch1); // save r10, trashed by movptr() 6270 #endif 6271 push(rax); // save rax, 6272 // addr may contain rsp so we will have to adjust it based on the push 6273 // we just did (and on 64 bit we do two pushes) 6274 // NOTE: 64bit seemed to have had a bug in that it did movq(addr, rax); which 6275 // stores rax into addr which is backwards of what was intended. 6276 if (addr.uses(rsp)) { 6277 lea(rax, addr); 6278 pushptr(Address(rax, LP64_ONLY(2 *) BytesPerWord)); 6279 } else { 6280 pushptr(addr); 6281 } 6282 6283 ExternalAddress buffer((address) b); 6284 // pass msg argument 6285 // avoid using pushptr, as it modifies scratch registers 6286 // and our contract is not to modify anything 6287 movptr(rax, buffer.addr()); 6288 push(rax); 6289 6290 // call indirectly to solve generation ordering problem 6291 movptr(rax, ExternalAddress(StubRoutines::verify_oop_subroutine_entry_address())); 6292 call(rax); 6293 // Caller pops the arguments (addr, message) and restores rax, r10. 6294 } 6295 6296 void MacroAssembler::verify_tlab() { 6297 #ifdef ASSERT 6298 if (UseTLAB && VerifyOops) { 6299 Label next, ok; 6300 Register t1 = rsi; 6301 Register thread_reg = NOT_LP64(rbx) LP64_ONLY(r15_thread); 6302 6303 push(t1); 6304 NOT_LP64(push(thread_reg)); 6305 NOT_LP64(get_thread(thread_reg)); 6306 6307 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6308 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_start_offset()))); 6309 jcc(Assembler::aboveEqual, next); 6310 STOP("assert(top >= start)"); 6311 should_not_reach_here(); 6312 6313 bind(next); 6314 movptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_end_offset()))); 6315 cmpptr(t1, Address(thread_reg, in_bytes(JavaThread::tlab_top_offset()))); 6316 jcc(Assembler::aboveEqual, ok); 6317 STOP("assert(top <= end)"); 6318 should_not_reach_here(); 6319 6320 bind(ok); 6321 NOT_LP64(pop(thread_reg)); 6322 pop(t1); 6323 } 6324 #endif 6325 } 6326 6327 class ControlWord { 6328 public: 6329 int32_t _value; 6330 6331 int rounding_control() const { return (_value >> 10) & 3 ; } 6332 int precision_control() const { return (_value >> 8) & 3 ; } 6333 bool precision() const { return ((_value >> 5) & 1) != 0; } 6334 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6335 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6336 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6337 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6338 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6339 6340 void print() const { 6341 // rounding control 6342 const char* rc; 6343 switch (rounding_control()) { 6344 case 0: rc = "round near"; break; 6345 case 1: rc = "round down"; break; 6346 case 2: rc = "round up "; break; 6347 case 3: rc = "chop "; break; 6348 }; 6349 // precision control 6350 const char* pc; 6351 switch (precision_control()) { 6352 case 0: pc = "24 bits "; break; 6353 case 1: pc = "reserved"; break; 6354 case 2: pc = "53 bits "; break; 6355 case 3: pc = "64 bits "; break; 6356 }; 6357 // flags 6358 char f[9]; 6359 f[0] = ' '; 6360 f[1] = ' '; 6361 f[2] = (precision ()) ? 'P' : 'p'; 6362 f[3] = (underflow ()) ? 'U' : 'u'; 6363 f[4] = (overflow ()) ? 'O' : 'o'; 6364 f[5] = (zero_divide ()) ? 'Z' : 'z'; 6365 f[6] = (denormalized()) ? 'D' : 'd'; 6366 f[7] = (invalid ()) ? 'I' : 'i'; 6367 f[8] = '\x0'; 6368 // output 6369 printf("%04x masks = %s, %s, %s", _value & 0xFFFF, f, rc, pc); 6370 } 6371 6372 }; 6373 6374 class StatusWord { 6375 public: 6376 int32_t _value; 6377 6378 bool busy() const { return ((_value >> 15) & 1) != 0; } 6379 bool C3() const { return ((_value >> 14) & 1) != 0; } 6380 bool C2() const { return ((_value >> 10) & 1) != 0; } 6381 bool C1() const { return ((_value >> 9) & 1) != 0; } 6382 bool C0() const { return ((_value >> 8) & 1) != 0; } 6383 int top() const { return (_value >> 11) & 7 ; } 6384 bool error_status() const { return ((_value >> 7) & 1) != 0; } 6385 bool stack_fault() const { return ((_value >> 6) & 1) != 0; } 6386 bool precision() const { return ((_value >> 5) & 1) != 0; } 6387 bool underflow() const { return ((_value >> 4) & 1) != 0; } 6388 bool overflow() const { return ((_value >> 3) & 1) != 0; } 6389 bool zero_divide() const { return ((_value >> 2) & 1) != 0; } 6390 bool denormalized() const { return ((_value >> 1) & 1) != 0; } 6391 bool invalid() const { return ((_value >> 0) & 1) != 0; } 6392 6393 void print() const { 6394 // condition codes 6395 char c[5]; 6396 c[0] = (C3()) ? '3' : '-'; 6397 c[1] = (C2()) ? '2' : '-'; 6398 c[2] = (C1()) ? '1' : '-'; 6399 c[3] = (C0()) ? '0' : '-'; 6400 c[4] = '\x0'; 6401 // flags 6402 char f[9]; 6403 f[0] = (error_status()) ? 'E' : '-'; 6404 f[1] = (stack_fault ()) ? 'S' : '-'; 6405 f[2] = (precision ()) ? 'P' : '-'; 6406 f[3] = (underflow ()) ? 'U' : '-'; 6407 f[4] = (overflow ()) ? 'O' : '-'; 6408 f[5] = (zero_divide ()) ? 'Z' : '-'; 6409 f[6] = (denormalized()) ? 'D' : '-'; 6410 f[7] = (invalid ()) ? 'I' : '-'; 6411 f[8] = '\x0'; 6412 // output 6413 printf("%04x flags = %s, cc = %s, top = %d", _value & 0xFFFF, f, c, top()); 6414 } 6415 6416 }; 6417 6418 class TagWord { 6419 public: 6420 int32_t _value; 6421 6422 int tag_at(int i) const { return (_value >> (i*2)) & 3; } 6423 6424 void print() const { 6425 printf("%04x", _value & 0xFFFF); 6426 } 6427 6428 }; 6429 6430 class FPU_Register { 6431 public: 6432 int32_t _m0; 6433 int32_t _m1; 6434 int16_t _ex; 6435 6436 bool is_indefinite() const { 6437 return _ex == -1 && _m1 == (int32_t)0xC0000000 && _m0 == 0; 6438 } 6439 6440 void print() const { 6441 char sign = (_ex < 0) ? '-' : '+'; 6442 const char* kind = (_ex == 0x7FFF || _ex == (int16_t)-1) ? "NaN" : " "; 6443 printf("%c%04hx.%08x%08x %s", sign, _ex, _m1, _m0, kind); 6444 }; 6445 6446 }; 6447 6448 class FPU_State { 6449 public: 6450 enum { 6451 register_size = 10, 6452 number_of_registers = 8, 6453 register_mask = 7 6454 }; 6455 6456 ControlWord _control_word; 6457 StatusWord _status_word; 6458 TagWord _tag_word; 6459 int32_t _error_offset; 6460 int32_t _error_selector; 6461 int32_t _data_offset; 6462 int32_t _data_selector; 6463 int8_t _register[register_size * number_of_registers]; 6464 6465 int tag_for_st(int i) const { return _tag_word.tag_at((_status_word.top() + i) & register_mask); } 6466 FPU_Register* st(int i) const { return (FPU_Register*)&_register[register_size * i]; } 6467 6468 const char* tag_as_string(int tag) const { 6469 switch (tag) { 6470 case 0: return "valid"; 6471 case 1: return "zero"; 6472 case 2: return "special"; 6473 case 3: return "empty"; 6474 } 6475 ShouldNotReachHere(); 6476 return NULL; 6477 } 6478 6479 void print() const { 6480 // print computation registers 6481 { int t = _status_word.top(); 6482 for (int i = 0; i < number_of_registers; i++) { 6483 int j = (i - t) & register_mask; 6484 printf("%c r%d = ST%d = ", (j == 0 ? '*' : ' '), i, j); 6485 st(j)->print(); 6486 printf(" %s\n", tag_as_string(_tag_word.tag_at(i))); 6487 } 6488 } 6489 printf("\n"); 6490 // print control registers 6491 printf("ctrl = "); _control_word.print(); printf("\n"); 6492 printf("stat = "); _status_word .print(); printf("\n"); 6493 printf("tags = "); _tag_word .print(); printf("\n"); 6494 } 6495 6496 }; 6497 6498 class Flag_Register { 6499 public: 6500 int32_t _value; 6501 6502 bool overflow() const { return ((_value >> 11) & 1) != 0; } 6503 bool direction() const { return ((_value >> 10) & 1) != 0; } 6504 bool sign() const { return ((_value >> 7) & 1) != 0; } 6505 bool zero() const { return ((_value >> 6) & 1) != 0; } 6506 bool auxiliary_carry() const { return ((_value >> 4) & 1) != 0; } 6507 bool parity() const { return ((_value >> 2) & 1) != 0; } 6508 bool carry() const { return ((_value >> 0) & 1) != 0; } 6509 6510 void print() const { 6511 // flags 6512 char f[8]; 6513 f[0] = (overflow ()) ? 'O' : '-'; 6514 f[1] = (direction ()) ? 'D' : '-'; 6515 f[2] = (sign ()) ? 'S' : '-'; 6516 f[3] = (zero ()) ? 'Z' : '-'; 6517 f[4] = (auxiliary_carry()) ? 'A' : '-'; 6518 f[5] = (parity ()) ? 'P' : '-'; 6519 f[6] = (carry ()) ? 'C' : '-'; 6520 f[7] = '\x0'; 6521 // output 6522 printf("%08x flags = %s", _value, f); 6523 } 6524 6525 }; 6526 6527 class IU_Register { 6528 public: 6529 int32_t _value; 6530 6531 void print() const { 6532 printf("%08x %11d", _value, _value); 6533 } 6534 6535 }; 6536 6537 class IU_State { 6538 public: 6539 Flag_Register _eflags; 6540 IU_Register _rdi; 6541 IU_Register _rsi; 6542 IU_Register _rbp; 6543 IU_Register _rsp; 6544 IU_Register _rbx; 6545 IU_Register _rdx; 6546 IU_Register _rcx; 6547 IU_Register _rax; 6548 6549 void print() const { 6550 // computation registers 6551 printf("rax, = "); _rax.print(); printf("\n"); 6552 printf("rbx, = "); _rbx.print(); printf("\n"); 6553 printf("rcx = "); _rcx.print(); printf("\n"); 6554 printf("rdx = "); _rdx.print(); printf("\n"); 6555 printf("rdi = "); _rdi.print(); printf("\n"); 6556 printf("rsi = "); _rsi.print(); printf("\n"); 6557 printf("rbp, = "); _rbp.print(); printf("\n"); 6558 printf("rsp = "); _rsp.print(); printf("\n"); 6559 printf("\n"); 6560 // control registers 6561 printf("flgs = "); _eflags.print(); printf("\n"); 6562 } 6563 }; 6564 6565 6566 class CPU_State { 6567 public: 6568 FPU_State _fpu_state; 6569 IU_State _iu_state; 6570 6571 void print() const { 6572 printf("--------------------------------------------------\n"); 6573 _iu_state .print(); 6574 printf("\n"); 6575 _fpu_state.print(); 6576 printf("--------------------------------------------------\n"); 6577 } 6578 6579 }; 6580 6581 6582 static void _print_CPU_state(CPU_State* state) { 6583 state->print(); 6584 }; 6585 6586 6587 void MacroAssembler::print_CPU_state() { 6588 push_CPU_state(); 6589 push(rsp); // pass CPU state 6590 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _print_CPU_state))); 6591 addptr(rsp, wordSize); // discard argument 6592 pop_CPU_state(); 6593 } 6594 6595 6596 static bool _verify_FPU(int stack_depth, char* s, CPU_State* state) { 6597 static int counter = 0; 6598 FPU_State* fs = &state->_fpu_state; 6599 counter++; 6600 // For leaf calls, only verify that the top few elements remain empty. 6601 // We only need 1 empty at the top for C2 code. 6602 if( stack_depth < 0 ) { 6603 if( fs->tag_for_st(7) != 3 ) { 6604 printf("FPR7 not empty\n"); 6605 state->print(); 6606 assert(false, "error"); 6607 return false; 6608 } 6609 return true; // All other stack states do not matter 6610 } 6611 6612 assert((fs->_control_word._value & 0xffff) == StubRoutines::_fpu_cntrl_wrd_std, 6613 "bad FPU control word"); 6614 6615 // compute stack depth 6616 int i = 0; 6617 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) < 3) i++; 6618 int d = i; 6619 while (i < FPU_State::number_of_registers && fs->tag_for_st(i) == 3) i++; 6620 // verify findings 6621 if (i != FPU_State::number_of_registers) { 6622 // stack not contiguous 6623 printf("%s: stack not contiguous at ST%d\n", s, i); 6624 state->print(); 6625 assert(false, "error"); 6626 return false; 6627 } 6628 // check if computed stack depth corresponds to expected stack depth 6629 if (stack_depth < 0) { 6630 // expected stack depth is -stack_depth or less 6631 if (d > -stack_depth) { 6632 // too many elements on the stack 6633 printf("%s: <= %d stack elements expected but found %d\n", s, -stack_depth, d); 6634 state->print(); 6635 assert(false, "error"); 6636 return false; 6637 } 6638 } else { 6639 // expected stack depth is stack_depth 6640 if (d != stack_depth) { 6641 // wrong stack depth 6642 printf("%s: %d stack elements expected but found %d\n", s, stack_depth, d); 6643 state->print(); 6644 assert(false, "error"); 6645 return false; 6646 } 6647 } 6648 // everything is cool 6649 return true; 6650 } 6651 6652 6653 void MacroAssembler::verify_FPU(int stack_depth, const char* s) { 6654 if (!VerifyFPU) return; 6655 push_CPU_state(); 6656 push(rsp); // pass CPU state 6657 ExternalAddress msg((address) s); 6658 // pass message string s 6659 pushptr(msg.addr()); 6660 push(stack_depth); // pass stack depth 6661 call(RuntimeAddress(CAST_FROM_FN_PTR(address, _verify_FPU))); 6662 addptr(rsp, 3 * wordSize); // discard arguments 6663 // check for error 6664 { Label L; 6665 testl(rax, rax); 6666 jcc(Assembler::notZero, L); 6667 int3(); // break if error condition 6668 bind(L); 6669 } 6670 pop_CPU_state(); 6671 } 6672 6673 void MacroAssembler::restore_cpu_control_state_after_jni() { 6674 // Either restore the MXCSR register after returning from the JNI Call 6675 // or verify that it wasn't changed (with -Xcheck:jni flag). 6676 if (VM_Version::supports_sse()) { 6677 if (RestoreMXCSROnJNICalls) { 6678 ldmxcsr(ExternalAddress(StubRoutines::addr_mxcsr_std())); 6679 } else if (CheckJNICalls) { 6680 call(RuntimeAddress(StubRoutines::x86::verify_mxcsr_entry())); 6681 } 6682 } 6683 if (VM_Version::supports_avx()) { 6684 // Clear upper bits of YMM registers to avoid SSE <-> AVX transition penalty. 6685 vzeroupper(); 6686 } 6687 6688 #ifndef _LP64 6689 // Either restore the x87 floating pointer control word after returning 6690 // from the JNI call or verify that it wasn't changed. 6691 if (CheckJNICalls) { 6692 call(RuntimeAddress(StubRoutines::x86::verify_fpu_cntrl_wrd_entry())); 6693 } 6694 #endif // _LP64 6695 } 6696 6697 6698 void MacroAssembler::load_klass(Register dst, Register src) { 6699 #ifdef _LP64 6700 if (UseCompressedClassPointers) { 6701 movl(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6702 decode_klass_not_null(dst); 6703 } else 6704 #endif 6705 movptr(dst, Address(src, oopDesc::klass_offset_in_bytes())); 6706 } 6707 6708 void MacroAssembler::load_prototype_header(Register dst, Register src) { 6709 load_klass(dst, src); 6710 movptr(dst, Address(dst, Klass::prototype_header_offset())); 6711 } 6712 6713 void MacroAssembler::store_klass(Register dst, Register src) { 6714 #ifdef _LP64 6715 if (UseCompressedClassPointers) { 6716 encode_klass_not_null(src); 6717 movl(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6718 } else 6719 #endif 6720 movptr(Address(dst, oopDesc::klass_offset_in_bytes()), src); 6721 } 6722 6723 void MacroAssembler::load_heap_oop(Register dst, Address src) { 6724 #ifdef _LP64 6725 // FIXME: Must change all places where we try to load the klass. 6726 if (UseCompressedOops) { 6727 movl(dst, src); 6728 decode_heap_oop(dst); 6729 } else 6730 #endif 6731 movptr(dst, src); 6732 } 6733 6734 // Doesn't do verfication, generates fixed size code 6735 void MacroAssembler::load_heap_oop_not_null(Register dst, Address src) { 6736 #ifdef _LP64 6737 if (UseCompressedOops) { 6738 movl(dst, src); 6739 decode_heap_oop_not_null(dst); 6740 } else 6741 #endif 6742 movptr(dst, src); 6743 } 6744 6745 void MacroAssembler::store_heap_oop(Address dst, Register src) { 6746 #ifdef _LP64 6747 if (UseCompressedOops) { 6748 assert(!dst.uses(src), "not enough registers"); 6749 encode_heap_oop(src); 6750 movl(dst, src); 6751 } else 6752 #endif 6753 movptr(dst, src); 6754 } 6755 6756 void MacroAssembler::cmp_heap_oop(Register src1, Address src2, Register tmp) { 6757 assert_different_registers(src1, tmp); 6758 #ifdef _LP64 6759 if (UseCompressedOops) { 6760 bool did_push = false; 6761 if (tmp == noreg) { 6762 tmp = rax; 6763 push(tmp); 6764 did_push = true; 6765 assert(!src2.uses(rsp), "can't push"); 6766 } 6767 load_heap_oop(tmp, src2); 6768 cmpptr(src1, tmp); 6769 if (did_push) pop(tmp); 6770 } else 6771 #endif 6772 cmpptr(src1, src2); 6773 } 6774 6775 // Used for storing NULLs. 6776 void MacroAssembler::store_heap_oop_null(Address dst) { 6777 #ifdef _LP64 6778 if (UseCompressedOops) { 6779 movl(dst, (int32_t)NULL_WORD); 6780 } else { 6781 movslq(dst, (int32_t)NULL_WORD); 6782 } 6783 #else 6784 movl(dst, (int32_t)NULL_WORD); 6785 #endif 6786 } 6787 6788 #ifdef _LP64 6789 void MacroAssembler::store_klass_gap(Register dst, Register src) { 6790 if (UseCompressedClassPointers) { 6791 // Store to klass gap in destination 6792 movl(Address(dst, oopDesc::klass_gap_offset_in_bytes()), src); 6793 } 6794 } 6795 6796 #ifdef ASSERT 6797 void MacroAssembler::verify_heapbase(const char* msg) { 6798 assert (UseCompressedOops, "should be compressed"); 6799 assert (Universe::heap() != NULL, "java heap should be initialized"); 6800 if (CheckCompressedOops) { 6801 Label ok; 6802 push(rscratch1); // cmpptr trashes rscratch1 6803 cmpptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 6804 jcc(Assembler::equal, ok); 6805 STOP(msg); 6806 bind(ok); 6807 pop(rscratch1); 6808 } 6809 } 6810 #endif 6811 6812 // Algorithm must match oop.inline.hpp encode_heap_oop. 6813 void MacroAssembler::encode_heap_oop(Register r) { 6814 #ifdef ASSERT 6815 verify_heapbase("MacroAssembler::encode_heap_oop: heap base corrupted?"); 6816 #endif 6817 verify_oop(r, "broken oop in encode_heap_oop"); 6818 if (Universe::narrow_oop_base() == NULL) { 6819 if (Universe::narrow_oop_shift() != 0) { 6820 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6821 shrq(r, LogMinObjAlignmentInBytes); 6822 } 6823 return; 6824 } 6825 testq(r, r); 6826 cmovq(Assembler::equal, r, r12_heapbase); 6827 subq(r, r12_heapbase); 6828 shrq(r, LogMinObjAlignmentInBytes); 6829 } 6830 6831 void MacroAssembler::encode_heap_oop_not_null(Register r) { 6832 #ifdef ASSERT 6833 verify_heapbase("MacroAssembler::encode_heap_oop_not_null: heap base corrupted?"); 6834 if (CheckCompressedOops) { 6835 Label ok; 6836 testq(r, r); 6837 jcc(Assembler::notEqual, ok); 6838 STOP("null oop passed to encode_heap_oop_not_null"); 6839 bind(ok); 6840 } 6841 #endif 6842 verify_oop(r, "broken oop in encode_heap_oop_not_null"); 6843 if (Universe::narrow_oop_base() != NULL) { 6844 subq(r, r12_heapbase); 6845 } 6846 if (Universe::narrow_oop_shift() != 0) { 6847 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6848 shrq(r, LogMinObjAlignmentInBytes); 6849 } 6850 } 6851 6852 void MacroAssembler::encode_heap_oop_not_null(Register dst, Register src) { 6853 #ifdef ASSERT 6854 verify_heapbase("MacroAssembler::encode_heap_oop_not_null2: heap base corrupted?"); 6855 if (CheckCompressedOops) { 6856 Label ok; 6857 testq(src, src); 6858 jcc(Assembler::notEqual, ok); 6859 STOP("null oop passed to encode_heap_oop_not_null2"); 6860 bind(ok); 6861 } 6862 #endif 6863 verify_oop(src, "broken oop in encode_heap_oop_not_null2"); 6864 if (dst != src) { 6865 movq(dst, src); 6866 } 6867 if (Universe::narrow_oop_base() != NULL) { 6868 subq(dst, r12_heapbase); 6869 } 6870 if (Universe::narrow_oop_shift() != 0) { 6871 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6872 shrq(dst, LogMinObjAlignmentInBytes); 6873 } 6874 } 6875 6876 void MacroAssembler::decode_heap_oop(Register r) { 6877 #ifdef ASSERT 6878 verify_heapbase("MacroAssembler::decode_heap_oop: heap base corrupted?"); 6879 #endif 6880 if (Universe::narrow_oop_base() == NULL) { 6881 if (Universe::narrow_oop_shift() != 0) { 6882 assert (LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6883 shlq(r, LogMinObjAlignmentInBytes); 6884 } 6885 } else { 6886 Label done; 6887 shlq(r, LogMinObjAlignmentInBytes); 6888 jccb(Assembler::equal, done); 6889 addq(r, r12_heapbase); 6890 bind(done); 6891 } 6892 verify_oop(r, "broken oop in decode_heap_oop"); 6893 } 6894 6895 void MacroAssembler::decode_heap_oop_not_null(Register r) { 6896 // Note: it will change flags 6897 assert (UseCompressedOops, "should only be used for compressed headers"); 6898 assert (Universe::heap() != NULL, "java heap should be initialized"); 6899 // Cannot assert, unverified entry point counts instructions (see .ad file) 6900 // vtableStubs also counts instructions in pd_code_size_limit. 6901 // Also do not verify_oop as this is called by verify_oop. 6902 if (Universe::narrow_oop_shift() != 0) { 6903 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6904 shlq(r, LogMinObjAlignmentInBytes); 6905 if (Universe::narrow_oop_base() != NULL) { 6906 addq(r, r12_heapbase); 6907 } 6908 } else { 6909 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6910 } 6911 } 6912 6913 void MacroAssembler::decode_heap_oop_not_null(Register dst, Register src) { 6914 // Note: it will change flags 6915 assert (UseCompressedOops, "should only be used for compressed headers"); 6916 assert (Universe::heap() != NULL, "java heap should be initialized"); 6917 // Cannot assert, unverified entry point counts instructions (see .ad file) 6918 // vtableStubs also counts instructions in pd_code_size_limit. 6919 // Also do not verify_oop as this is called by verify_oop. 6920 if (Universe::narrow_oop_shift() != 0) { 6921 assert(LogMinObjAlignmentInBytes == Universe::narrow_oop_shift(), "decode alg wrong"); 6922 if (LogMinObjAlignmentInBytes == Address::times_8) { 6923 leaq(dst, Address(r12_heapbase, src, Address::times_8, 0)); 6924 } else { 6925 if (dst != src) { 6926 movq(dst, src); 6927 } 6928 shlq(dst, LogMinObjAlignmentInBytes); 6929 if (Universe::narrow_oop_base() != NULL) { 6930 addq(dst, r12_heapbase); 6931 } 6932 } 6933 } else { 6934 assert (Universe::narrow_oop_base() == NULL, "sanity"); 6935 if (dst != src) { 6936 movq(dst, src); 6937 } 6938 } 6939 } 6940 6941 void MacroAssembler::encode_klass_not_null(Register r) { 6942 if (Universe::narrow_klass_base() != NULL) { 6943 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 6944 assert(r != r12_heapbase, "Encoding a klass in r12"); 6945 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 6946 subq(r, r12_heapbase); 6947 } 6948 if (Universe::narrow_klass_shift() != 0) { 6949 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6950 shrq(r, LogKlassAlignmentInBytes); 6951 } 6952 if (Universe::narrow_klass_base() != NULL) { 6953 reinit_heapbase(); 6954 } 6955 } 6956 6957 void MacroAssembler::encode_klass_not_null(Register dst, Register src) { 6958 if (dst == src) { 6959 encode_klass_not_null(src); 6960 } else { 6961 if (Universe::narrow_klass_base() != NULL) { 6962 mov64(dst, (int64_t)Universe::narrow_klass_base()); 6963 negq(dst); 6964 addq(dst, src); 6965 } else { 6966 movptr(dst, src); 6967 } 6968 if (Universe::narrow_klass_shift() != 0) { 6969 assert (LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 6970 shrq(dst, LogKlassAlignmentInBytes); 6971 } 6972 } 6973 } 6974 6975 // Function instr_size_for_decode_klass_not_null() counts the instructions 6976 // generated by decode_klass_not_null(register r) and reinit_heapbase(), 6977 // when (Universe::heap() != NULL). Hence, if the instructions they 6978 // generate change, then this method needs to be updated. 6979 int MacroAssembler::instr_size_for_decode_klass_not_null() { 6980 assert (UseCompressedClassPointers, "only for compressed klass ptrs"); 6981 if (Universe::narrow_klass_base() != NULL) { 6982 // mov64 + addq + shlq? + mov64 (for reinit_heapbase()). 6983 return (Universe::narrow_klass_shift() == 0 ? 20 : 24); 6984 } else { 6985 // longest load decode klass function, mov64, leaq 6986 return 16; 6987 } 6988 } 6989 6990 // !!! If the instructions that get generated here change then function 6991 // instr_size_for_decode_klass_not_null() needs to get updated. 6992 void MacroAssembler::decode_klass_not_null(Register r) { 6993 // Note: it will change flags 6994 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 6995 assert(r != r12_heapbase, "Decoding a klass in r12"); 6996 // Cannot assert, unverified entry point counts instructions (see .ad file) 6997 // vtableStubs also counts instructions in pd_code_size_limit. 6998 // Also do not verify_oop as this is called by verify_oop. 6999 if (Universe::narrow_klass_shift() != 0) { 7000 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 7001 shlq(r, LogKlassAlignmentInBytes); 7002 } 7003 // Use r12 as a scratch register in which to temporarily load the narrow_klass_base. 7004 if (Universe::narrow_klass_base() != NULL) { 7005 mov64(r12_heapbase, (int64_t)Universe::narrow_klass_base()); 7006 addq(r, r12_heapbase); 7007 reinit_heapbase(); 7008 } 7009 } 7010 7011 void MacroAssembler::decode_klass_not_null(Register dst, Register src) { 7012 // Note: it will change flags 7013 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7014 if (dst == src) { 7015 decode_klass_not_null(dst); 7016 } else { 7017 // Cannot assert, unverified entry point counts instructions (see .ad file) 7018 // vtableStubs also counts instructions in pd_code_size_limit. 7019 // Also do not verify_oop as this is called by verify_oop. 7020 mov64(dst, (int64_t)Universe::narrow_klass_base()); 7021 if (Universe::narrow_klass_shift() != 0) { 7022 assert(LogKlassAlignmentInBytes == Universe::narrow_klass_shift(), "decode alg wrong"); 7023 assert(LogKlassAlignmentInBytes == Address::times_8, "klass not aligned on 64bits?"); 7024 leaq(dst, Address(dst, src, Address::times_8, 0)); 7025 } else { 7026 addq(dst, src); 7027 } 7028 } 7029 } 7030 7031 void MacroAssembler::set_narrow_oop(Register dst, jobject obj) { 7032 assert (UseCompressedOops, "should only be used for compressed headers"); 7033 assert (Universe::heap() != NULL, "java heap should be initialized"); 7034 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7035 int oop_index = oop_recorder()->find_index(obj); 7036 RelocationHolder rspec = oop_Relocation::spec(oop_index); 7037 mov_narrow_oop(dst, oop_index, rspec); 7038 } 7039 7040 void MacroAssembler::set_narrow_oop(Address dst, jobject obj) { 7041 assert (UseCompressedOops, "should only be used for compressed headers"); 7042 assert (Universe::heap() != NULL, "java heap should be initialized"); 7043 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7044 int oop_index = oop_recorder()->find_index(obj); 7045 RelocationHolder rspec = oop_Relocation::spec(oop_index); 7046 mov_narrow_oop(dst, oop_index, rspec); 7047 } 7048 7049 void MacroAssembler::set_narrow_klass(Register dst, Klass* k) { 7050 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7051 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7052 int klass_index = oop_recorder()->find_index(k); 7053 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7054 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 7055 } 7056 7057 void MacroAssembler::set_narrow_klass(Address dst, Klass* k) { 7058 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7059 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7060 int klass_index = oop_recorder()->find_index(k); 7061 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7062 mov_narrow_oop(dst, Klass::encode_klass(k), rspec); 7063 } 7064 7065 void MacroAssembler::cmp_narrow_oop(Register dst, jobject obj) { 7066 assert (UseCompressedOops, "should only be used for compressed headers"); 7067 assert (Universe::heap() != NULL, "java heap should be initialized"); 7068 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7069 int oop_index = oop_recorder()->find_index(obj); 7070 RelocationHolder rspec = oop_Relocation::spec(oop_index); 7071 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 7072 } 7073 7074 void MacroAssembler::cmp_narrow_oop(Address dst, jobject obj) { 7075 assert (UseCompressedOops, "should only be used for compressed headers"); 7076 assert (Universe::heap() != NULL, "java heap should be initialized"); 7077 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7078 int oop_index = oop_recorder()->find_index(obj); 7079 RelocationHolder rspec = oop_Relocation::spec(oop_index); 7080 Assembler::cmp_narrow_oop(dst, oop_index, rspec); 7081 } 7082 7083 void MacroAssembler::cmp_narrow_klass(Register dst, Klass* k) { 7084 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7085 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7086 int klass_index = oop_recorder()->find_index(k); 7087 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7088 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 7089 } 7090 7091 void MacroAssembler::cmp_narrow_klass(Address dst, Klass* k) { 7092 assert (UseCompressedClassPointers, "should only be used for compressed headers"); 7093 assert (oop_recorder() != NULL, "this assembler needs an OopRecorder"); 7094 int klass_index = oop_recorder()->find_index(k); 7095 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 7096 Assembler::cmp_narrow_oop(dst, Klass::encode_klass(k), rspec); 7097 } 7098 7099 void MacroAssembler::reinit_heapbase() { 7100 if (UseCompressedOops || UseCompressedClassPointers) { 7101 if (Universe::heap() != NULL) { 7102 if (Universe::narrow_oop_base() == NULL) { 7103 MacroAssembler::xorptr(r12_heapbase, r12_heapbase); 7104 } else { 7105 mov64(r12_heapbase, (int64_t)Universe::narrow_ptrs_base()); 7106 } 7107 } else { 7108 movptr(r12_heapbase, ExternalAddress((address)Universe::narrow_ptrs_base_addr())); 7109 } 7110 } 7111 } 7112 7113 #endif // _LP64 7114 7115 7116 // C2 compiled method's prolog code. 7117 void MacroAssembler::verified_entry(int framesize, int stack_bang_size, bool fp_mode_24b) { 7118 7119 // WARNING: Initial instruction MUST be 5 bytes or longer so that 7120 // NativeJump::patch_verified_entry will be able to patch out the entry 7121 // code safely. The push to verify stack depth is ok at 5 bytes, 7122 // the frame allocation can be either 3 or 6 bytes. So if we don't do 7123 // stack bang then we must use the 6 byte frame allocation even if 7124 // we have no frame. :-( 7125 assert(stack_bang_size >= framesize || stack_bang_size <= 0, "stack bang size incorrect"); 7126 7127 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned"); 7128 // Remove word for return addr 7129 framesize -= wordSize; 7130 stack_bang_size -= wordSize; 7131 7132 // Calls to C2R adapters often do not accept exceptional returns. 7133 // We require that their callers must bang for them. But be careful, because 7134 // some VM calls (such as call site linkage) can use several kilobytes of 7135 // stack. But the stack safety zone should account for that. 7136 // See bugs 4446381, 4468289, 4497237. 7137 if (stack_bang_size > 0) { 7138 generate_stack_overflow_check(stack_bang_size); 7139 7140 // We always push rbp, so that on return to interpreter rbp, will be 7141 // restored correctly and we can correct the stack. 7142 push(rbp); 7143 // Save caller's stack pointer into RBP if the frame pointer is preserved. 7144 if (PreserveFramePointer) { 7145 mov(rbp, rsp); 7146 } 7147 // Remove word for ebp 7148 framesize -= wordSize; 7149 7150 // Create frame 7151 if (framesize) { 7152 subptr(rsp, framesize); 7153 } 7154 } else { 7155 // Create frame (force generation of a 4 byte immediate value) 7156 subptr_imm32(rsp, framesize); 7157 7158 // Save RBP register now. 7159 framesize -= wordSize; 7160 movptr(Address(rsp, framesize), rbp); 7161 // Save caller's stack pointer into RBP if the frame pointer is preserved. 7162 if (PreserveFramePointer) { 7163 movptr(rbp, rsp); 7164 if (framesize > 0) { 7165 addptr(rbp, framesize); 7166 } 7167 } 7168 } 7169 7170 if (VerifyStackAtCalls) { // Majik cookie to verify stack depth 7171 framesize -= wordSize; 7172 movptr(Address(rsp, framesize), (int32_t)0xbadb100d); 7173 } 7174 7175 #ifndef _LP64 7176 // If method sets FPU control word do it now 7177 if (fp_mode_24b) { 7178 fldcw(ExternalAddress(StubRoutines::addr_fpu_cntrl_wrd_24())); 7179 } 7180 if (UseSSE >= 2 && VerifyFPU) { 7181 verify_FPU(0, "FPU stack must be clean on entry"); 7182 } 7183 #endif 7184 7185 #ifdef ASSERT 7186 if (VerifyStackAtCalls) { 7187 Label L; 7188 push(rax); 7189 mov(rax, rsp); 7190 andptr(rax, StackAlignmentInBytes-1); 7191 cmpptr(rax, StackAlignmentInBytes-wordSize); 7192 pop(rax); 7193 jcc(Assembler::equal, L); 7194 STOP("Stack is not properly aligned!"); 7195 bind(L); 7196 } 7197 #endif 7198 7199 } 7200 7201 void MacroAssembler::clear_mem(Register base, Register cnt, Register tmp, bool is_large) { 7202 // cnt - number of qwords (8-byte words). 7203 // base - start address, qword aligned. 7204 // is_large - if optimizers know cnt is larger than InitArrayShortSize 7205 assert(base==rdi, "base register must be edi for rep stos"); 7206 assert(tmp==rax, "tmp register must be eax for rep stos"); 7207 assert(cnt==rcx, "cnt register must be ecx for rep stos"); 7208 assert(InitArrayShortSize % BytesPerLong == 0, 7209 "InitArrayShortSize should be the multiple of BytesPerLong"); 7210 7211 Label SHORT, LONG, DONE; 7212 7213 if (!is_large) { 7214 cmpptr(cnt, InitArrayShortSize/BytesPerLong); 7215 jcc(Assembler::greater, LONG); 7216 7217 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7218 7219 // Use individual pointer-sized stores for small counts: 7220 bind(SHORT); 7221 testptr(cnt, cnt); 7222 jcc(Assembler::equal, DONE); 7223 decrement(cnt); 7224 movptr(Address(base, cnt, Address::times_ptr), 0); 7225 jmp(SHORT); 7226 } 7227 7228 // Use longer rep-prefixed ops for non-small counts: 7229 bind(LONG); 7230 xorptr(tmp, tmp); 7231 if (UseFastStosb) { 7232 shlptr(cnt, 3); // convert to number of bytes 7233 rep_stosb(); 7234 } else { 7235 NOT_LP64(shlptr(cnt, 1);) // convert to number of 32-bit words for 32-bit VM 7236 rep_stos(); 7237 } 7238 7239 bind(DONE); 7240 } 7241 7242 #ifdef COMPILER2 7243 7244 // IndexOf for constant substrings with size >= 8 chars 7245 // which don't need to be loaded through stack. 7246 void MacroAssembler::string_indexofC8(Register str1, Register str2, 7247 Register cnt1, Register cnt2, 7248 int int_cnt2, Register result, 7249 XMMRegister vec, Register tmp, 7250 int ae) { 7251 ShortBranchVerifier sbv(this); 7252 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7253 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 7254 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7255 7256 // This method uses the pcmpestri instruction with bound registers 7257 // inputs: 7258 // xmm - substring 7259 // rax - substring length (elements count) 7260 // mem - scanned string 7261 // rdx - string length (elements count) 7262 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7263 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7264 // outputs: 7265 // rcx - matched index in string 7266 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7267 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7268 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7269 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7270 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7271 7272 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, 7273 RET_FOUND, RET_NOT_FOUND, EXIT, FOUND_SUBSTR, 7274 MATCH_SUBSTR_HEAD, RELOAD_STR, FOUND_CANDIDATE; 7275 7276 // Note, inline_string_indexOf() generates checks: 7277 // if (substr.count > string.count) return -1; 7278 // if (substr.count == 0) return 0; 7279 assert(int_cnt2 >= stride, "this code is used only for cnt2 >= 8 chars"); 7280 7281 // Load substring. 7282 if (ae == StrIntrinsicNode::UL) { 7283 pmovzxbw(vec, Address(str2, 0)); 7284 } else { 7285 movdqu(vec, Address(str2, 0)); 7286 } 7287 movl(cnt2, int_cnt2); 7288 movptr(result, str1); // string addr 7289 7290 if (int_cnt2 > stride) { 7291 jmpb(SCAN_TO_SUBSTR); 7292 7293 // Reload substr for rescan, this code 7294 // is executed only for large substrings (> 8 chars) 7295 bind(RELOAD_SUBSTR); 7296 if (ae == StrIntrinsicNode::UL) { 7297 pmovzxbw(vec, Address(str2, 0)); 7298 } else { 7299 movdqu(vec, Address(str2, 0)); 7300 } 7301 negptr(cnt2); // Jumped here with negative cnt2, convert to positive 7302 7303 bind(RELOAD_STR); 7304 // We came here after the beginning of the substring was 7305 // matched but the rest of it was not so we need to search 7306 // again. Start from the next element after the previous match. 7307 7308 // cnt2 is number of substring reminding elements and 7309 // cnt1 is number of string reminding elements when cmp failed. 7310 // Restored cnt1 = cnt1 - cnt2 + int_cnt2 7311 subl(cnt1, cnt2); 7312 addl(cnt1, int_cnt2); 7313 movl(cnt2, int_cnt2); // Now restore cnt2 7314 7315 decrementl(cnt1); // Shift to next element 7316 cmpl(cnt1, cnt2); 7317 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7318 7319 addptr(result, (1<<scale1)); 7320 7321 } // (int_cnt2 > 8) 7322 7323 // Scan string for start of substr in 16-byte vectors 7324 bind(SCAN_TO_SUBSTR); 7325 pcmpestri(vec, Address(result, 0), mode); 7326 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7327 subl(cnt1, stride); 7328 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7329 cmpl(cnt1, cnt2); 7330 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7331 addptr(result, 16); 7332 jmpb(SCAN_TO_SUBSTR); 7333 7334 // Found a potential substr 7335 bind(FOUND_CANDIDATE); 7336 // Matched whole vector if first element matched (tmp(rcx) == 0). 7337 if (int_cnt2 == stride) { 7338 jccb(Assembler::overflow, RET_FOUND); // OF == 1 7339 } else { // int_cnt2 > 8 7340 jccb(Assembler::overflow, FOUND_SUBSTR); 7341 } 7342 // After pcmpestri tmp(rcx) contains matched element index 7343 // Compute start addr of substr 7344 lea(result, Address(result, tmp, scale1)); 7345 7346 // Make sure string is still long enough 7347 subl(cnt1, tmp); 7348 cmpl(cnt1, cnt2); 7349 if (int_cnt2 == stride) { 7350 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7351 } else { // int_cnt2 > 8 7352 jccb(Assembler::greaterEqual, MATCH_SUBSTR_HEAD); 7353 } 7354 // Left less then substring. 7355 7356 bind(RET_NOT_FOUND); 7357 movl(result, -1); 7358 jmpb(EXIT); 7359 7360 if (int_cnt2 > stride) { 7361 // This code is optimized for the case when whole substring 7362 // is matched if its head is matched. 7363 bind(MATCH_SUBSTR_HEAD); 7364 pcmpestri(vec, Address(result, 0), mode); 7365 // Reload only string if does not match 7366 jccb(Assembler::noOverflow, RELOAD_STR); // OF == 0 7367 7368 Label CONT_SCAN_SUBSTR; 7369 // Compare the rest of substring (> 8 chars). 7370 bind(FOUND_SUBSTR); 7371 // First 8 chars are already matched. 7372 negptr(cnt2); 7373 addptr(cnt2, stride); 7374 7375 bind(SCAN_SUBSTR); 7376 subl(cnt1, stride); 7377 cmpl(cnt2, -stride); // Do not read beyond substring 7378 jccb(Assembler::lessEqual, CONT_SCAN_SUBSTR); 7379 // Back-up strings to avoid reading beyond substring: 7380 // cnt1 = cnt1 - cnt2 + 8 7381 addl(cnt1, cnt2); // cnt2 is negative 7382 addl(cnt1, stride); 7383 movl(cnt2, stride); negptr(cnt2); 7384 bind(CONT_SCAN_SUBSTR); 7385 if (int_cnt2 < (int)G) { 7386 int tail_off1 = int_cnt2<<scale1; 7387 int tail_off2 = int_cnt2<<scale2; 7388 if (ae == StrIntrinsicNode::UL) { 7389 pmovzxbw(vec, Address(str2, cnt2, scale2, tail_off2)); 7390 } else { 7391 movdqu(vec, Address(str2, cnt2, scale2, tail_off2)); 7392 } 7393 pcmpestri(vec, Address(result, cnt2, scale1, tail_off1), mode); 7394 } else { 7395 // calculate index in register to avoid integer overflow (int_cnt2*2) 7396 movl(tmp, int_cnt2); 7397 addptr(tmp, cnt2); 7398 if (ae == StrIntrinsicNode::UL) { 7399 pmovzxbw(vec, Address(str2, tmp, scale2, 0)); 7400 } else { 7401 movdqu(vec, Address(str2, tmp, scale2, 0)); 7402 } 7403 pcmpestri(vec, Address(result, tmp, scale1, 0), mode); 7404 } 7405 // Need to reload strings pointers if not matched whole vector 7406 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7407 addptr(cnt2, stride); 7408 jcc(Assembler::negative, SCAN_SUBSTR); 7409 // Fall through if found full substring 7410 7411 } // (int_cnt2 > 8) 7412 7413 bind(RET_FOUND); 7414 // Found result if we matched full small substring. 7415 // Compute substr offset 7416 subptr(result, str1); 7417 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7418 shrl(result, 1); // index 7419 } 7420 bind(EXIT); 7421 7422 } // string_indexofC8 7423 7424 // Small strings are loaded through stack if they cross page boundary. 7425 void MacroAssembler::string_indexof(Register str1, Register str2, 7426 Register cnt1, Register cnt2, 7427 int int_cnt2, Register result, 7428 XMMRegister vec, Register tmp, 7429 int ae) { 7430 ShortBranchVerifier sbv(this); 7431 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7432 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 7433 assert(ae != StrIntrinsicNode::LU, "Invalid encoding"); 7434 7435 // 7436 // int_cnt2 is length of small (< 8 chars) constant substring 7437 // or (-1) for non constant substring in which case its length 7438 // is in cnt2 register. 7439 // 7440 // Note, inline_string_indexOf() generates checks: 7441 // if (substr.count > string.count) return -1; 7442 // if (substr.count == 0) return 0; 7443 // 7444 int stride = (ae == StrIntrinsicNode::LL) ? 16 : 8; //UU, UL -> 8 7445 assert(int_cnt2 == -1 || (0 < int_cnt2 && int_cnt2 < stride), "should be != 0"); 7446 // This method uses the pcmpestri instruction with bound registers 7447 // inputs: 7448 // xmm - substring 7449 // rax - substring length (elements count) 7450 // mem - scanned string 7451 // rdx - string length (elements count) 7452 // 0xd - mode: 1100 (substring search) + 01 (unsigned shorts) 7453 // 0xc - mode: 1100 (substring search) + 00 (unsigned bytes) 7454 // outputs: 7455 // rcx - matched index in string 7456 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7457 int mode = (ae == StrIntrinsicNode::LL) ? 0x0c : 0x0d; // bytes or shorts 7458 Address::ScaleFactor scale1 = (ae == StrIntrinsicNode::LL) ? Address::times_1 : Address::times_2; 7459 Address::ScaleFactor scale2 = (ae == StrIntrinsicNode::UL) ? Address::times_1 : scale1; 7460 7461 Label RELOAD_SUBSTR, SCAN_TO_SUBSTR, SCAN_SUBSTR, ADJUST_STR, 7462 RET_FOUND, RET_NOT_FOUND, CLEANUP, FOUND_SUBSTR, 7463 FOUND_CANDIDATE; 7464 7465 { //======================================================== 7466 // We don't know where these strings are located 7467 // and we can't read beyond them. Load them through stack. 7468 Label BIG_STRINGS, CHECK_STR, COPY_SUBSTR, COPY_STR; 7469 7470 movptr(tmp, rsp); // save old SP 7471 7472 if (int_cnt2 > 0) { // small (< 8 chars) constant substring 7473 if (int_cnt2 == (1>>scale2)) { // One byte 7474 assert((ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL), "Only possible for latin1 encoding"); 7475 load_unsigned_byte(result, Address(str2, 0)); 7476 movdl(vec, result); // move 32 bits 7477 } else if (ae == StrIntrinsicNode::LL && int_cnt2 == 3) { // Three bytes 7478 // Not enough header space in 32-bit VM: 12+3 = 15. 7479 movl(result, Address(str2, -1)); 7480 shrl(result, 8); 7481 movdl(vec, result); // move 32 bits 7482 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (2>>scale2)) { // One char 7483 load_unsigned_short(result, Address(str2, 0)); 7484 movdl(vec, result); // move 32 bits 7485 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (4>>scale2)) { // Two chars 7486 movdl(vec, Address(str2, 0)); // move 32 bits 7487 } else if (ae != StrIntrinsicNode::UL && int_cnt2 == (8>>scale2)) { // Four chars 7488 movq(vec, Address(str2, 0)); // move 64 bits 7489 } else { // cnt2 = { 3, 5, 6, 7 } || (ae == StrIntrinsicNode::UL && cnt2 ={2, ..., 7}) 7490 // Array header size is 12 bytes in 32-bit VM 7491 // + 6 bytes for 3 chars == 18 bytes, 7492 // enough space to load vec and shift. 7493 assert(HeapWordSize*TypeArrayKlass::header_size() >= 12,"sanity"); 7494 if (ae == StrIntrinsicNode::UL) { 7495 int tail_off = int_cnt2-8; 7496 pmovzxbw(vec, Address(str2, tail_off)); 7497 psrldq(vec, -2*tail_off); 7498 } 7499 else { 7500 int tail_off = int_cnt2*(1<<scale2); 7501 movdqu(vec, Address(str2, tail_off-16)); 7502 psrldq(vec, 16-tail_off); 7503 } 7504 } 7505 } else { // not constant substring 7506 cmpl(cnt2, stride); 7507 jccb(Assembler::aboveEqual, BIG_STRINGS); // Both strings are big enough 7508 7509 // We can read beyond string if srt+16 does not cross page boundary 7510 // since heaps are aligned and mapped by pages. 7511 assert(os::vm_page_size() < (int)G, "default page should be small"); 7512 movl(result, str2); // We need only low 32 bits 7513 andl(result, (os::vm_page_size()-1)); 7514 cmpl(result, (os::vm_page_size()-16)); 7515 jccb(Assembler::belowEqual, CHECK_STR); 7516 7517 // Move small strings to stack to allow load 16 bytes into vec. 7518 subptr(rsp, 16); 7519 int stk_offset = wordSize-(1<<scale2); 7520 push(cnt2); 7521 7522 bind(COPY_SUBSTR); 7523 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UL) { 7524 load_unsigned_byte(result, Address(str2, cnt2, scale2, -1)); 7525 movb(Address(rsp, cnt2, scale2, stk_offset), result); 7526 } else if (ae == StrIntrinsicNode::UU) { 7527 load_unsigned_short(result, Address(str2, cnt2, scale2, -2)); 7528 movw(Address(rsp, cnt2, scale2, stk_offset), result); 7529 } 7530 decrement(cnt2); 7531 jccb(Assembler::notZero, COPY_SUBSTR); 7532 7533 pop(cnt2); 7534 movptr(str2, rsp); // New substring address 7535 } // non constant 7536 7537 bind(CHECK_STR); 7538 cmpl(cnt1, stride); 7539 jccb(Assembler::aboveEqual, BIG_STRINGS); 7540 7541 // Check cross page boundary. 7542 movl(result, str1); // We need only low 32 bits 7543 andl(result, (os::vm_page_size()-1)); 7544 cmpl(result, (os::vm_page_size()-16)); 7545 jccb(Assembler::belowEqual, BIG_STRINGS); 7546 7547 subptr(rsp, 16); 7548 int stk_offset = -(1<<scale1); 7549 if (int_cnt2 < 0) { // not constant 7550 push(cnt2); 7551 stk_offset += wordSize; 7552 } 7553 movl(cnt2, cnt1); 7554 7555 bind(COPY_STR); 7556 if (ae == StrIntrinsicNode::LL) { 7557 load_unsigned_byte(result, Address(str1, cnt2, scale1, -1)); 7558 movb(Address(rsp, cnt2, scale1, stk_offset), result); 7559 } else { 7560 load_unsigned_short(result, Address(str1, cnt2, scale1, -2)); 7561 movw(Address(rsp, cnt2, scale1, stk_offset), result); 7562 } 7563 decrement(cnt2); 7564 jccb(Assembler::notZero, COPY_STR); 7565 7566 if (int_cnt2 < 0) { // not constant 7567 pop(cnt2); 7568 } 7569 movptr(str1, rsp); // New string address 7570 7571 bind(BIG_STRINGS); 7572 // Load substring. 7573 if (int_cnt2 < 0) { // -1 7574 if (ae == StrIntrinsicNode::UL) { 7575 pmovzxbw(vec, Address(str2, 0)); 7576 } else { 7577 movdqu(vec, Address(str2, 0)); 7578 } 7579 push(cnt2); // substr count 7580 push(str2); // substr addr 7581 push(str1); // string addr 7582 } else { 7583 // Small (< 8 chars) constant substrings are loaded already. 7584 movl(cnt2, int_cnt2); 7585 } 7586 push(tmp); // original SP 7587 7588 } // Finished loading 7589 7590 //======================================================== 7591 // Start search 7592 // 7593 7594 movptr(result, str1); // string addr 7595 7596 if (int_cnt2 < 0) { // Only for non constant substring 7597 jmpb(SCAN_TO_SUBSTR); 7598 7599 // SP saved at sp+0 7600 // String saved at sp+1*wordSize 7601 // Substr saved at sp+2*wordSize 7602 // Substr count saved at sp+3*wordSize 7603 7604 // Reload substr for rescan, this code 7605 // is executed only for large substrings (> 8 chars) 7606 bind(RELOAD_SUBSTR); 7607 movptr(str2, Address(rsp, 2*wordSize)); 7608 movl(cnt2, Address(rsp, 3*wordSize)); 7609 if (ae == StrIntrinsicNode::UL) { 7610 pmovzxbw(vec, Address(str2, 0)); 7611 } else { 7612 movdqu(vec, Address(str2, 0)); 7613 } 7614 // We came here after the beginning of the substring was 7615 // matched but the rest of it was not so we need to search 7616 // again. Start from the next element after the previous match. 7617 subptr(str1, result); // Restore counter 7618 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7619 shrl(str1, 1); 7620 } 7621 addl(cnt1, str1); 7622 decrementl(cnt1); // Shift to next element 7623 cmpl(cnt1, cnt2); 7624 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7625 7626 addptr(result, (1<<scale1)); 7627 } // non constant 7628 7629 // Scan string for start of substr in 16-byte vectors 7630 bind(SCAN_TO_SUBSTR); 7631 assert(cnt1 == rdx && cnt2 == rax && tmp == rcx, "pcmpestri"); 7632 pcmpestri(vec, Address(result, 0), mode); 7633 jccb(Assembler::below, FOUND_CANDIDATE); // CF == 1 7634 subl(cnt1, stride); 7635 jccb(Assembler::lessEqual, RET_NOT_FOUND); // Scanned full string 7636 cmpl(cnt1, cnt2); 7637 jccb(Assembler::negative, RET_NOT_FOUND); // Left less then substring 7638 addptr(result, 16); 7639 7640 bind(ADJUST_STR); 7641 cmpl(cnt1, stride); // Do not read beyond string 7642 jccb(Assembler::greaterEqual, SCAN_TO_SUBSTR); 7643 // Back-up string to avoid reading beyond string. 7644 lea(result, Address(result, cnt1, scale1, -16)); 7645 movl(cnt1, stride); 7646 jmpb(SCAN_TO_SUBSTR); 7647 7648 // Found a potential substr 7649 bind(FOUND_CANDIDATE); 7650 // After pcmpestri tmp(rcx) contains matched element index 7651 7652 // Make sure string is still long enough 7653 subl(cnt1, tmp); 7654 cmpl(cnt1, cnt2); 7655 jccb(Assembler::greaterEqual, FOUND_SUBSTR); 7656 // Left less then substring. 7657 7658 bind(RET_NOT_FOUND); 7659 movl(result, -1); 7660 jmpb(CLEANUP); 7661 7662 bind(FOUND_SUBSTR); 7663 // Compute start addr of substr 7664 lea(result, Address(result, tmp, scale1)); 7665 if (int_cnt2 > 0) { // Constant substring 7666 // Repeat search for small substring (< 8 chars) 7667 // from new point without reloading substring. 7668 // Have to check that we don't read beyond string. 7669 cmpl(tmp, stride-int_cnt2); 7670 jccb(Assembler::greater, ADJUST_STR); 7671 // Fall through if matched whole substring. 7672 } else { // non constant 7673 assert(int_cnt2 == -1, "should be != 0"); 7674 7675 addl(tmp, cnt2); 7676 // Found result if we matched whole substring. 7677 cmpl(tmp, stride); 7678 jccb(Assembler::lessEqual, RET_FOUND); 7679 7680 // Repeat search for small substring (<= 8 chars) 7681 // from new point 'str1' without reloading substring. 7682 cmpl(cnt2, stride); 7683 // Have to check that we don't read beyond string. 7684 jccb(Assembler::lessEqual, ADJUST_STR); 7685 7686 Label CHECK_NEXT, CONT_SCAN_SUBSTR, RET_FOUND_LONG; 7687 // Compare the rest of substring (> 8 chars). 7688 movptr(str1, result); 7689 7690 cmpl(tmp, cnt2); 7691 // First 8 chars are already matched. 7692 jccb(Assembler::equal, CHECK_NEXT); 7693 7694 bind(SCAN_SUBSTR); 7695 pcmpestri(vec, Address(str1, 0), mode); 7696 // Need to reload strings pointers if not matched whole vector 7697 jcc(Assembler::noOverflow, RELOAD_SUBSTR); // OF == 0 7698 7699 bind(CHECK_NEXT); 7700 subl(cnt2, stride); 7701 jccb(Assembler::lessEqual, RET_FOUND_LONG); // Found full substring 7702 addptr(str1, 16); 7703 if (ae == StrIntrinsicNode::UL) { 7704 addptr(str2, 8); 7705 } else { 7706 addptr(str2, 16); 7707 } 7708 subl(cnt1, stride); 7709 cmpl(cnt2, stride); // Do not read beyond substring 7710 jccb(Assembler::greaterEqual, CONT_SCAN_SUBSTR); 7711 // Back-up strings to avoid reading beyond substring. 7712 7713 if (ae == StrIntrinsicNode::UL) { 7714 lea(str2, Address(str2, cnt2, scale2, -8)); 7715 lea(str1, Address(str1, cnt2, scale1, -16)); 7716 } else { 7717 lea(str2, Address(str2, cnt2, scale2, -16)); 7718 lea(str1, Address(str1, cnt2, scale1, -16)); 7719 } 7720 subl(cnt1, cnt2); 7721 movl(cnt2, stride); 7722 addl(cnt1, stride); 7723 bind(CONT_SCAN_SUBSTR); 7724 if (ae == StrIntrinsicNode::UL) { 7725 pmovzxbw(vec, Address(str2, 0)); 7726 } else { 7727 movdqu(vec, Address(str2, 0)); 7728 } 7729 jmpb(SCAN_SUBSTR); 7730 7731 bind(RET_FOUND_LONG); 7732 movptr(str1, Address(rsp, wordSize)); 7733 } // non constant 7734 7735 bind(RET_FOUND); 7736 // Compute substr offset 7737 subptr(result, str1); 7738 if (ae == StrIntrinsicNode::UU || ae == StrIntrinsicNode::UL) { 7739 shrl(result, 1); // index 7740 } 7741 bind(CLEANUP); 7742 pop(rsp); // restore SP 7743 7744 } // string_indexof 7745 7746 void MacroAssembler::string_indexof_char(Register str1, Register cnt1, Register ch, Register result, 7747 XMMRegister vec1, XMMRegister vec2, XMMRegister vec3, Register tmp) { 7748 ShortBranchVerifier sbv(this); 7749 assert(UseSSE42Intrinsics, "SSE4.2 intrinsics are required"); 7750 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 7751 7752 int stride = 8; 7753 7754 Label FOUND_CHAR, SCAN_TO_CHAR, SCAN_TO_CHAR_LOOP, 7755 SCAN_TO_8_CHAR, SCAN_TO_8_CHAR_LOOP, SCAN_TO_16_CHAR_LOOP, 7756 RET_NOT_FOUND, SCAN_TO_8_CHAR_INIT, 7757 FOUND_SEQ_CHAR, DONE_LABEL; 7758 7759 movptr(result, str1); 7760 if (UseAVX >= 2) { 7761 cmpl(cnt1, stride); 7762 jccb(Assembler::less, SCAN_TO_CHAR_LOOP); 7763 cmpl(cnt1, 2*stride); 7764 jccb(Assembler::less, SCAN_TO_8_CHAR_INIT); 7765 movdl(vec1, ch); 7766 vpbroadcastw(vec1, vec1); 7767 vpxor(vec2, vec2); 7768 movl(tmp, cnt1); 7769 andl(tmp, 0xFFFFFFF0); //vector count (in chars) 7770 andl(cnt1,0x0000000F); //tail count (in chars) 7771 7772 bind(SCAN_TO_16_CHAR_LOOP); 7773 vmovdqu(vec3, Address(result, 0)); 7774 vpcmpeqw(vec3, vec3, vec1, 1); 7775 vptest(vec2, vec3); 7776 jcc(Assembler::carryClear, FOUND_CHAR); 7777 addptr(result, 32); 7778 subl(tmp, 2*stride); 7779 jccb(Assembler::notZero, SCAN_TO_16_CHAR_LOOP); 7780 jmp(SCAN_TO_8_CHAR); 7781 bind(SCAN_TO_8_CHAR_INIT); 7782 movdl(vec1, ch); 7783 pshuflw(vec1, vec1, 0x00); 7784 pshufd(vec1, vec1, 0); 7785 pxor(vec2, vec2); 7786 } 7787 bind(SCAN_TO_8_CHAR); 7788 cmpl(cnt1, stride); 7789 if (UseAVX >= 2) { 7790 jccb(Assembler::less, SCAN_TO_CHAR); 7791 } else { 7792 jccb(Assembler::less, SCAN_TO_CHAR_LOOP); 7793 movdl(vec1, ch); 7794 pshuflw(vec1, vec1, 0x00); 7795 pshufd(vec1, vec1, 0); 7796 pxor(vec2, vec2); 7797 } 7798 movl(tmp, cnt1); 7799 andl(tmp, 0xFFFFFFF8); //vector count (in chars) 7800 andl(cnt1,0x00000007); //tail count (in chars) 7801 7802 bind(SCAN_TO_8_CHAR_LOOP); 7803 movdqu(vec3, Address(result, 0)); 7804 pcmpeqw(vec3, vec1); 7805 ptest(vec2, vec3); 7806 jcc(Assembler::carryClear, FOUND_CHAR); 7807 addptr(result, 16); 7808 subl(tmp, stride); 7809 jccb(Assembler::notZero, SCAN_TO_8_CHAR_LOOP); 7810 bind(SCAN_TO_CHAR); 7811 testl(cnt1, cnt1); 7812 jcc(Assembler::zero, RET_NOT_FOUND); 7813 bind(SCAN_TO_CHAR_LOOP); 7814 load_unsigned_short(tmp, Address(result, 0)); 7815 cmpl(ch, tmp); 7816 jccb(Assembler::equal, FOUND_SEQ_CHAR); 7817 addptr(result, 2); 7818 subl(cnt1, 1); 7819 jccb(Assembler::zero, RET_NOT_FOUND); 7820 jmp(SCAN_TO_CHAR_LOOP); 7821 7822 bind(RET_NOT_FOUND); 7823 movl(result, -1); 7824 jmpb(DONE_LABEL); 7825 7826 bind(FOUND_CHAR); 7827 if (UseAVX >= 2) { 7828 vpmovmskb(tmp, vec3); 7829 } else { 7830 pmovmskb(tmp, vec3); 7831 } 7832 bsfl(ch, tmp); 7833 addl(result, ch); 7834 7835 bind(FOUND_SEQ_CHAR); 7836 subptr(result, str1); 7837 shrl(result, 1); 7838 7839 bind(DONE_LABEL); 7840 } // string_indexof_char 7841 7842 // helper function for string_compare 7843 void MacroAssembler::load_next_elements(Register elem1, Register elem2, Register str1, Register str2, 7844 Address::ScaleFactor scale, Address::ScaleFactor scale1, 7845 Address::ScaleFactor scale2, Register index, int ae) { 7846 if (ae == StrIntrinsicNode::LL) { 7847 load_unsigned_byte(elem1, Address(str1, index, scale, 0)); 7848 load_unsigned_byte(elem2, Address(str2, index, scale, 0)); 7849 } else if (ae == StrIntrinsicNode::UU) { 7850 load_unsigned_short(elem1, Address(str1, index, scale, 0)); 7851 load_unsigned_short(elem2, Address(str2, index, scale, 0)); 7852 } else { 7853 load_unsigned_byte(elem1, Address(str1, index, scale1, 0)); 7854 load_unsigned_short(elem2, Address(str2, index, scale2, 0)); 7855 } 7856 } 7857 7858 // Compare strings, used for char[] and byte[]. 7859 void MacroAssembler::string_compare(Register str1, Register str2, 7860 Register cnt1, Register cnt2, Register result, 7861 XMMRegister vec1, int ae) { 7862 ShortBranchVerifier sbv(this); 7863 Label LENGTH_DIFF_LABEL, POP_LABEL, DONE_LABEL, WHILE_HEAD_LABEL; 7864 Label COMPARE_WIDE_VECTORS_LOOP_FAILED; // used only _LP64 && AVX3 7865 int stride, stride2, adr_stride, adr_stride1, adr_stride2; 7866 int stride2x2 = 0x40; 7867 Address::ScaleFactor scale = Address::no_scale; 7868 Address::ScaleFactor scale1 = Address::no_scale; 7869 Address::ScaleFactor scale2 = Address::no_scale; 7870 7871 if (ae != StrIntrinsicNode::LL) { 7872 stride2x2 = 0x20; 7873 } 7874 7875 if (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL) { 7876 shrl(cnt2, 1); 7877 } 7878 // Compute the minimum of the string lengths and the 7879 // difference of the string lengths (stack). 7880 // Do the conditional move stuff 7881 movl(result, cnt1); 7882 subl(cnt1, cnt2); 7883 push(cnt1); 7884 cmov32(Assembler::lessEqual, cnt2, result); // cnt2 = min(cnt1, cnt2) 7885 7886 // Is the minimum length zero? 7887 testl(cnt2, cnt2); 7888 jcc(Assembler::zero, LENGTH_DIFF_LABEL); 7889 if (ae == StrIntrinsicNode::LL) { 7890 // Load first bytes 7891 load_unsigned_byte(result, Address(str1, 0)); // result = str1[0] 7892 load_unsigned_byte(cnt1, Address(str2, 0)); // cnt1 = str2[0] 7893 } else if (ae == StrIntrinsicNode::UU) { 7894 // Load first characters 7895 load_unsigned_short(result, Address(str1, 0)); 7896 load_unsigned_short(cnt1, Address(str2, 0)); 7897 } else { 7898 load_unsigned_byte(result, Address(str1, 0)); 7899 load_unsigned_short(cnt1, Address(str2, 0)); 7900 } 7901 subl(result, cnt1); 7902 jcc(Assembler::notZero, POP_LABEL); 7903 7904 if (ae == StrIntrinsicNode::UU) { 7905 // Divide length by 2 to get number of chars 7906 shrl(cnt2, 1); 7907 } 7908 cmpl(cnt2, 1); 7909 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7910 7911 // Check if the strings start at the same location and setup scale and stride 7912 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7913 cmpptr(str1, str2); 7914 jcc(Assembler::equal, LENGTH_DIFF_LABEL); 7915 if (ae == StrIntrinsicNode::LL) { 7916 scale = Address::times_1; 7917 stride = 16; 7918 } else { 7919 scale = Address::times_2; 7920 stride = 8; 7921 } 7922 } else { 7923 scale1 = Address::times_1; 7924 scale2 = Address::times_2; 7925 // scale not used 7926 stride = 8; 7927 } 7928 7929 if (UseAVX >= 2 && UseSSE42Intrinsics) { 7930 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 7931 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_WIDE_TAIL, COMPARE_SMALL_STR; 7932 Label COMPARE_WIDE_VECTORS_LOOP, COMPARE_16_CHARS, COMPARE_INDEX_CHAR; 7933 Label COMPARE_WIDE_VECTORS_LOOP_AVX2; 7934 Label COMPARE_TAIL_LONG; 7935 Label COMPARE_WIDE_VECTORS_LOOP_AVX3; // used only _LP64 && AVX3 7936 7937 int pcmpmask = 0x19; 7938 if (ae == StrIntrinsicNode::LL) { 7939 pcmpmask &= ~0x01; 7940 } 7941 7942 // Setup to compare 16-chars (32-bytes) vectors, 7943 // start from first character again because it has aligned address. 7944 if (ae == StrIntrinsicNode::LL) { 7945 stride2 = 32; 7946 } else { 7947 stride2 = 16; 7948 } 7949 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7950 adr_stride = stride << scale; 7951 } else { 7952 adr_stride1 = 8; //stride << scale1; 7953 adr_stride2 = 16; //stride << scale2; 7954 } 7955 7956 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 7957 // rax and rdx are used by pcmpestri as elements counters 7958 movl(result, cnt2); 7959 andl(cnt2, ~(stride2-1)); // cnt2 holds the vector count 7960 jcc(Assembler::zero, COMPARE_TAIL_LONG); 7961 7962 // fast path : compare first 2 8-char vectors. 7963 bind(COMPARE_16_CHARS); 7964 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7965 movdqu(vec1, Address(str1, 0)); 7966 } else { 7967 pmovzxbw(vec1, Address(str1, 0)); 7968 } 7969 pcmpestri(vec1, Address(str2, 0), pcmpmask); 7970 jccb(Assembler::below, COMPARE_INDEX_CHAR); 7971 7972 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7973 movdqu(vec1, Address(str1, adr_stride)); 7974 pcmpestri(vec1, Address(str2, adr_stride), pcmpmask); 7975 } else { 7976 pmovzxbw(vec1, Address(str1, adr_stride1)); 7977 pcmpestri(vec1, Address(str2, adr_stride2), pcmpmask); 7978 } 7979 jccb(Assembler::aboveEqual, COMPARE_WIDE_VECTORS); 7980 addl(cnt1, stride); 7981 7982 // Compare the characters at index in cnt1 7983 bind(COMPARE_INDEX_CHAR); // cnt1 has the offset of the mismatching character 7984 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 7985 subl(result, cnt2); 7986 jmp(POP_LABEL); 7987 7988 // Setup the registers to start vector comparison loop 7989 bind(COMPARE_WIDE_VECTORS); 7990 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 7991 lea(str1, Address(str1, result, scale)); 7992 lea(str2, Address(str2, result, scale)); 7993 } else { 7994 lea(str1, Address(str1, result, scale1)); 7995 lea(str2, Address(str2, result, scale2)); 7996 } 7997 subl(result, stride2); 7998 subl(cnt2, stride2); 7999 jcc(Assembler::zero, COMPARE_WIDE_TAIL); 8000 negptr(result); 8001 8002 // In a loop, compare 16-chars (32-bytes) at once using (vpxor+vptest) 8003 bind(COMPARE_WIDE_VECTORS_LOOP); 8004 8005 #ifdef _LP64 8006 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 8007 cmpl(cnt2, stride2x2); 8008 jccb(Assembler::below, COMPARE_WIDE_VECTORS_LOOP_AVX2); 8009 testl(cnt2, stride2x2-1); // cnt2 holds the vector count 8010 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX2); // means we cannot subtract by 0x40 8011 8012 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 8013 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8014 evmovdquq(vec1, Address(str1, result, scale), Assembler::AVX_512bit); 8015 evpcmpeqb(k7, vec1, Address(str2, result, scale), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 8016 } else { 8017 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_512bit); 8018 evpcmpeqb(k7, vec1, Address(str2, result, scale2), Assembler::AVX_512bit); // k7 == 11..11, if operands equal, otherwise k7 has some 0 8019 } 8020 kortestql(k7, k7); 8021 jcc(Assembler::aboveEqual, COMPARE_WIDE_VECTORS_LOOP_FAILED); // miscompare 8022 addptr(result, stride2x2); // update since we already compared at this addr 8023 subl(cnt2, stride2x2); // and sub the size too 8024 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP_AVX3); 8025 8026 vpxor(vec1, vec1); 8027 jmpb(COMPARE_WIDE_TAIL); 8028 }//if (VM_Version::supports_avx512vlbw()) 8029 #endif // _LP64 8030 8031 8032 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8033 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8034 vmovdqu(vec1, Address(str1, result, scale)); 8035 vpxor(vec1, Address(str2, result, scale)); 8036 } else { 8037 vpmovzxbw(vec1, Address(str1, result, scale1), Assembler::AVX_256bit); 8038 vpxor(vec1, Address(str2, result, scale2)); 8039 } 8040 vptest(vec1, vec1); 8041 jcc(Assembler::notZero, VECTOR_NOT_EQUAL); 8042 addptr(result, stride2); 8043 subl(cnt2, stride2); 8044 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS_LOOP); 8045 // clean upper bits of YMM registers 8046 vpxor(vec1, vec1); 8047 8048 // compare wide vectors tail 8049 bind(COMPARE_WIDE_TAIL); 8050 testptr(result, result); 8051 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 8052 8053 movl(result, stride2); 8054 movl(cnt2, result); 8055 negptr(result); 8056 jmp(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8057 8058 // Identifies the mismatching (higher or lower)16-bytes in the 32-byte vectors. 8059 bind(VECTOR_NOT_EQUAL); 8060 // clean upper bits of YMM registers 8061 vpxor(vec1, vec1); 8062 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8063 lea(str1, Address(str1, result, scale)); 8064 lea(str2, Address(str2, result, scale)); 8065 } else { 8066 lea(str1, Address(str1, result, scale1)); 8067 lea(str2, Address(str2, result, scale2)); 8068 } 8069 jmp(COMPARE_16_CHARS); 8070 8071 // Compare tail chars, length between 1 to 15 chars 8072 bind(COMPARE_TAIL_LONG); 8073 movl(cnt2, result); 8074 cmpl(cnt2, stride); 8075 jccb(Assembler::less, COMPARE_SMALL_STR); 8076 8077 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8078 movdqu(vec1, Address(str1, 0)); 8079 } else { 8080 pmovzxbw(vec1, Address(str1, 0)); 8081 } 8082 pcmpestri(vec1, Address(str2, 0), pcmpmask); 8083 jcc(Assembler::below, COMPARE_INDEX_CHAR); 8084 subptr(cnt2, stride); 8085 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 8086 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8087 lea(str1, Address(str1, result, scale)); 8088 lea(str2, Address(str2, result, scale)); 8089 } else { 8090 lea(str1, Address(str1, result, scale1)); 8091 lea(str2, Address(str2, result, scale2)); 8092 } 8093 negptr(cnt2); 8094 jmpb(WHILE_HEAD_LABEL); 8095 8096 bind(COMPARE_SMALL_STR); 8097 } else if (UseSSE42Intrinsics) { 8098 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 8099 Label COMPARE_WIDE_VECTORS, VECTOR_NOT_EQUAL, COMPARE_TAIL; 8100 int pcmpmask = 0x19; 8101 // Setup to compare 8-char (16-byte) vectors, 8102 // start from first character again because it has aligned address. 8103 movl(result, cnt2); 8104 andl(cnt2, ~(stride - 1)); // cnt2 holds the vector count 8105 if (ae == StrIntrinsicNode::LL) { 8106 pcmpmask &= ~0x01; 8107 } 8108 jccb(Assembler::zero, COMPARE_TAIL); 8109 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8110 lea(str1, Address(str1, result, scale)); 8111 lea(str2, Address(str2, result, scale)); 8112 } else { 8113 lea(str1, Address(str1, result, scale1)); 8114 lea(str2, Address(str2, result, scale2)); 8115 } 8116 negptr(result); 8117 8118 // pcmpestri 8119 // inputs: 8120 // vec1- substring 8121 // rax - negative string length (elements count) 8122 // mem - scanned string 8123 // rdx - string length (elements count) 8124 // pcmpmask - cmp mode: 11000 (string compare with negated result) 8125 // + 00 (unsigned bytes) or + 01 (unsigned shorts) 8126 // outputs: 8127 // rcx - first mismatched element index 8128 assert(result == rax && cnt2 == rdx && cnt1 == rcx, "pcmpestri"); 8129 8130 bind(COMPARE_WIDE_VECTORS); 8131 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8132 movdqu(vec1, Address(str1, result, scale)); 8133 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 8134 } else { 8135 pmovzxbw(vec1, Address(str1, result, scale1)); 8136 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 8137 } 8138 // After pcmpestri cnt1(rcx) contains mismatched element index 8139 8140 jccb(Assembler::below, VECTOR_NOT_EQUAL); // CF==1 8141 addptr(result, stride); 8142 subptr(cnt2, stride); 8143 jccb(Assembler::notZero, COMPARE_WIDE_VECTORS); 8144 8145 // compare wide vectors tail 8146 testptr(result, result); 8147 jccb(Assembler::zero, LENGTH_DIFF_LABEL); 8148 8149 movl(cnt2, stride); 8150 movl(result, stride); 8151 negptr(result); 8152 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8153 movdqu(vec1, Address(str1, result, scale)); 8154 pcmpestri(vec1, Address(str2, result, scale), pcmpmask); 8155 } else { 8156 pmovzxbw(vec1, Address(str1, result, scale1)); 8157 pcmpestri(vec1, Address(str2, result, scale2), pcmpmask); 8158 } 8159 jccb(Assembler::aboveEqual, LENGTH_DIFF_LABEL); 8160 8161 // Mismatched characters in the vectors 8162 bind(VECTOR_NOT_EQUAL); 8163 addptr(cnt1, result); 8164 load_next_elements(result, cnt2, str1, str2, scale, scale1, scale2, cnt1, ae); 8165 subl(result, cnt2); 8166 jmpb(POP_LABEL); 8167 8168 bind(COMPARE_TAIL); // limit is zero 8169 movl(cnt2, result); 8170 // Fallthru to tail compare 8171 } 8172 // Shift str2 and str1 to the end of the arrays, negate min 8173 if (ae == StrIntrinsicNode::LL || ae == StrIntrinsicNode::UU) { 8174 lea(str1, Address(str1, cnt2, scale)); 8175 lea(str2, Address(str2, cnt2, scale)); 8176 } else { 8177 lea(str1, Address(str1, cnt2, scale1)); 8178 lea(str2, Address(str2, cnt2, scale2)); 8179 } 8180 decrementl(cnt2); // first character was compared already 8181 negptr(cnt2); 8182 8183 // Compare the rest of the elements 8184 bind(WHILE_HEAD_LABEL); 8185 load_next_elements(result, cnt1, str1, str2, scale, scale1, scale2, cnt2, ae); 8186 subl(result, cnt1); 8187 jccb(Assembler::notZero, POP_LABEL); 8188 increment(cnt2); 8189 jccb(Assembler::notZero, WHILE_HEAD_LABEL); 8190 8191 // Strings are equal up to min length. Return the length difference. 8192 bind(LENGTH_DIFF_LABEL); 8193 pop(result); 8194 if (ae == StrIntrinsicNode::UU) { 8195 // Divide diff by 2 to get number of chars 8196 sarl(result, 1); 8197 } 8198 jmpb(DONE_LABEL); 8199 8200 #ifdef _LP64 8201 if (VM_Version::supports_avx512vlbw()) { 8202 8203 bind(COMPARE_WIDE_VECTORS_LOOP_FAILED); 8204 8205 kmovql(cnt1, k7); 8206 notq(cnt1); 8207 bsfq(cnt2, cnt1); 8208 if (ae != StrIntrinsicNode::LL) { 8209 // Divide diff by 2 to get number of chars 8210 sarl(cnt2, 1); 8211 } 8212 addq(result, cnt2); 8213 if (ae == StrIntrinsicNode::LL) { 8214 load_unsigned_byte(cnt1, Address(str2, result)); 8215 load_unsigned_byte(result, Address(str1, result)); 8216 } else if (ae == StrIntrinsicNode::UU) { 8217 load_unsigned_short(cnt1, Address(str2, result, scale)); 8218 load_unsigned_short(result, Address(str1, result, scale)); 8219 } else { 8220 load_unsigned_short(cnt1, Address(str2, result, scale2)); 8221 load_unsigned_byte(result, Address(str1, result, scale1)); 8222 } 8223 subl(result, cnt1); 8224 jmpb(POP_LABEL); 8225 }//if (VM_Version::supports_avx512vlbw()) 8226 #endif // _LP64 8227 8228 // Discard the stored length difference 8229 bind(POP_LABEL); 8230 pop(cnt1); 8231 8232 // That's it 8233 bind(DONE_LABEL); 8234 if(ae == StrIntrinsicNode::UL) { 8235 negl(result); 8236 } 8237 8238 } 8239 8240 // Search for Non-ASCII character (Negative byte value) in a byte array, 8241 // return true if it has any and false otherwise. 8242 void MacroAssembler::has_negatives(Register ary1, Register len, 8243 Register result, Register tmp1, 8244 XMMRegister vec1, XMMRegister vec2) { 8245 8246 // rsi: byte array 8247 // rcx: len 8248 // rax: result 8249 ShortBranchVerifier sbv(this); 8250 assert_different_registers(ary1, len, result, tmp1); 8251 assert_different_registers(vec1, vec2); 8252 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_CHAR, COMPARE_VECTORS, COMPARE_BYTE; 8253 8254 // len == 0 8255 testl(len, len); 8256 jcc(Assembler::zero, FALSE_LABEL); 8257 8258 movl(result, len); // copy 8259 8260 if (UseAVX >= 2 && UseSSE >= 2) { 8261 // With AVX2, use 32-byte vector compare 8262 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8263 8264 // Compare 32-byte vectors 8265 andl(result, 0x0000001f); // tail count (in bytes) 8266 andl(len, 0xffffffe0); // vector count (in bytes) 8267 jccb(Assembler::zero, COMPARE_TAIL); 8268 8269 lea(ary1, Address(ary1, len, Address::times_1)); 8270 negptr(len); 8271 8272 movl(tmp1, 0x80808080); // create mask to test for Unicode chars in vector 8273 movdl(vec2, tmp1); 8274 vpbroadcastd(vec2, vec2); 8275 8276 bind(COMPARE_WIDE_VECTORS); 8277 vmovdqu(vec1, Address(ary1, len, Address::times_1)); 8278 vptest(vec1, vec2); 8279 jccb(Assembler::notZero, TRUE_LABEL); 8280 addptr(len, 32); 8281 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8282 8283 testl(result, result); 8284 jccb(Assembler::zero, FALSE_LABEL); 8285 8286 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8287 vptest(vec1, vec2); 8288 jccb(Assembler::notZero, TRUE_LABEL); 8289 jmpb(FALSE_LABEL); 8290 8291 bind(COMPARE_TAIL); // len is zero 8292 movl(len, result); 8293 // Fallthru to tail compare 8294 } else if (UseSSE42Intrinsics) { 8295 assert(UseSSE >= 4, "SSE4 must be for SSE4.2 intrinsics to be available"); 8296 // With SSE4.2, use double quad vector compare 8297 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8298 8299 // Compare 16-byte vectors 8300 andl(result, 0x0000000f); // tail count (in bytes) 8301 andl(len, 0xfffffff0); // vector count (in bytes) 8302 jccb(Assembler::zero, COMPARE_TAIL); 8303 8304 lea(ary1, Address(ary1, len, Address::times_1)); 8305 negptr(len); 8306 8307 movl(tmp1, 0x80808080); 8308 movdl(vec2, tmp1); 8309 pshufd(vec2, vec2, 0); 8310 8311 bind(COMPARE_WIDE_VECTORS); 8312 movdqu(vec1, Address(ary1, len, Address::times_1)); 8313 ptest(vec1, vec2); 8314 jccb(Assembler::notZero, TRUE_LABEL); 8315 addptr(len, 16); 8316 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8317 8318 testl(result, result); 8319 jccb(Assembler::zero, FALSE_LABEL); 8320 8321 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8322 ptest(vec1, vec2); 8323 jccb(Assembler::notZero, TRUE_LABEL); 8324 jmpb(FALSE_LABEL); 8325 8326 bind(COMPARE_TAIL); // len is zero 8327 movl(len, result); 8328 // Fallthru to tail compare 8329 } 8330 8331 // Compare 4-byte vectors 8332 andl(len, 0xfffffffc); // vector count (in bytes) 8333 jccb(Assembler::zero, COMPARE_CHAR); 8334 8335 lea(ary1, Address(ary1, len, Address::times_1)); 8336 negptr(len); 8337 8338 bind(COMPARE_VECTORS); 8339 movl(tmp1, Address(ary1, len, Address::times_1)); 8340 andl(tmp1, 0x80808080); 8341 jccb(Assembler::notZero, TRUE_LABEL); 8342 addptr(len, 4); 8343 jcc(Assembler::notZero, COMPARE_VECTORS); 8344 8345 // Compare trailing char (final 2 bytes), if any 8346 bind(COMPARE_CHAR); 8347 testl(result, 0x2); // tail char 8348 jccb(Assembler::zero, COMPARE_BYTE); 8349 load_unsigned_short(tmp1, Address(ary1, 0)); 8350 andl(tmp1, 0x00008080); 8351 jccb(Assembler::notZero, TRUE_LABEL); 8352 subptr(result, 2); 8353 lea(ary1, Address(ary1, 2)); 8354 8355 bind(COMPARE_BYTE); 8356 testl(result, 0x1); // tail byte 8357 jccb(Assembler::zero, FALSE_LABEL); 8358 load_unsigned_byte(tmp1, Address(ary1, 0)); 8359 andl(tmp1, 0x00000080); 8360 jccb(Assembler::notEqual, TRUE_LABEL); 8361 jmpb(FALSE_LABEL); 8362 8363 bind(TRUE_LABEL); 8364 movl(result, 1); // return true 8365 jmpb(DONE); 8366 8367 bind(FALSE_LABEL); 8368 xorl(result, result); // return false 8369 8370 // That's it 8371 bind(DONE); 8372 if (UseAVX >= 2 && UseSSE >= 2) { 8373 // clean upper bits of YMM registers 8374 vpxor(vec1, vec1); 8375 vpxor(vec2, vec2); 8376 } 8377 } 8378 8379 // Compare char[] or byte[] arrays aligned to 4 bytes or substrings. 8380 void MacroAssembler::arrays_equals(bool is_array_equ, Register ary1, Register ary2, 8381 Register limit, Register result, Register chr, 8382 XMMRegister vec1, XMMRegister vec2, bool is_char) { 8383 ShortBranchVerifier sbv(this); 8384 Label TRUE_LABEL, FALSE_LABEL, DONE, COMPARE_VECTORS, COMPARE_CHAR, COMPARE_BYTE; 8385 8386 int length_offset = arrayOopDesc::length_offset_in_bytes(); 8387 int base_offset = arrayOopDesc::base_offset_in_bytes(is_char ? T_CHAR : T_BYTE); 8388 8389 if (is_array_equ) { 8390 // Check the input args 8391 cmpptr(ary1, ary2); 8392 jcc(Assembler::equal, TRUE_LABEL); 8393 8394 // Need additional checks for arrays_equals. 8395 testptr(ary1, ary1); 8396 jcc(Assembler::zero, FALSE_LABEL); 8397 testptr(ary2, ary2); 8398 jcc(Assembler::zero, FALSE_LABEL); 8399 8400 // Check the lengths 8401 movl(limit, Address(ary1, length_offset)); 8402 cmpl(limit, Address(ary2, length_offset)); 8403 jcc(Assembler::notEqual, FALSE_LABEL); 8404 } 8405 8406 // count == 0 8407 testl(limit, limit); 8408 jcc(Assembler::zero, TRUE_LABEL); 8409 8410 if (is_array_equ) { 8411 // Load array address 8412 lea(ary1, Address(ary1, base_offset)); 8413 lea(ary2, Address(ary2, base_offset)); 8414 } 8415 8416 if (is_array_equ && is_char) { 8417 // arrays_equals when used for char[]. 8418 shll(limit, 1); // byte count != 0 8419 } 8420 movl(result, limit); // copy 8421 8422 if (UseAVX >= 2) { 8423 // With AVX2, use 32-byte vector compare 8424 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8425 8426 // Compare 32-byte vectors 8427 andl(result, 0x0000001f); // tail count (in bytes) 8428 andl(limit, 0xffffffe0); // vector count (in bytes) 8429 jcc(Assembler::zero, COMPARE_TAIL); 8430 8431 lea(ary1, Address(ary1, limit, Address::times_1)); 8432 lea(ary2, Address(ary2, limit, Address::times_1)); 8433 negptr(limit); 8434 8435 bind(COMPARE_WIDE_VECTORS); 8436 8437 #ifdef _LP64 8438 if (VM_Version::supports_avx512vlbw()) { // trying 64 bytes fast loop 8439 Label COMPARE_WIDE_VECTORS_LOOP_AVX2, COMPARE_WIDE_VECTORS_LOOP_AVX3; 8440 8441 cmpl(limit, -64); 8442 jccb(Assembler::greater, COMPARE_WIDE_VECTORS_LOOP_AVX2); 8443 8444 bind(COMPARE_WIDE_VECTORS_LOOP_AVX3); // the hottest loop 8445 8446 evmovdquq(vec1, Address(ary1, limit, Address::times_1), Assembler::AVX_512bit); 8447 evpcmpeqb(k7, vec1, Address(ary2, limit, Address::times_1), Assembler::AVX_512bit); 8448 kortestql(k7, k7); 8449 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8450 addptr(limit, 64); // update since we already compared at this addr 8451 cmpl(limit, -64); 8452 jccb(Assembler::lessEqual, COMPARE_WIDE_VECTORS_LOOP_AVX3); 8453 8454 // At this point we may still need to compare -limit+result bytes. 8455 // We could execute the next two instruction and just continue via non-wide path: 8456 // cmpl(limit, 0); 8457 // jcc(Assembler::equal, COMPARE_TAIL); // true 8458 // But since we stopped at the points ary{1,2}+limit which are 8459 // not farther than 64 bytes from the ends of arrays ary{1,2}+result 8460 // (|limit| <= 32 and result < 32), 8461 // we may just compare the last 64 bytes. 8462 // 8463 addptr(result, -64); // it is safe, bc we just came from this area 8464 evmovdquq(vec1, Address(ary1, result, Address::times_1), Assembler::AVX_512bit); 8465 evpcmpeqb(k7, vec1, Address(ary2, result, Address::times_1), Assembler::AVX_512bit); 8466 kortestql(k7, k7); 8467 jcc(Assembler::aboveEqual, FALSE_LABEL); // miscompare 8468 8469 jmp(TRUE_LABEL); 8470 8471 bind(COMPARE_WIDE_VECTORS_LOOP_AVX2); 8472 8473 }//if (VM_Version::supports_avx512vlbw()) 8474 #endif //_LP64 8475 8476 vmovdqu(vec1, Address(ary1, limit, Address::times_1)); 8477 vmovdqu(vec2, Address(ary2, limit, Address::times_1)); 8478 vpxor(vec1, vec2); 8479 8480 vptest(vec1, vec1); 8481 jccb(Assembler::notZero, FALSE_LABEL); 8482 addptr(limit, 32); 8483 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8484 8485 testl(result, result); 8486 jccb(Assembler::zero, TRUE_LABEL); 8487 8488 vmovdqu(vec1, Address(ary1, result, Address::times_1, -32)); 8489 vmovdqu(vec2, Address(ary2, result, Address::times_1, -32)); 8490 vpxor(vec1, vec2); 8491 8492 vptest(vec1, vec1); 8493 jccb(Assembler::notZero, FALSE_LABEL); 8494 jmpb(TRUE_LABEL); 8495 8496 bind(COMPARE_TAIL); // limit is zero 8497 movl(limit, result); 8498 // Fallthru to tail compare 8499 } else if (UseSSE42Intrinsics) { 8500 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 8501 // With SSE4.2, use double quad vector compare 8502 Label COMPARE_WIDE_VECTORS, COMPARE_TAIL; 8503 8504 // Compare 16-byte vectors 8505 andl(result, 0x0000000f); // tail count (in bytes) 8506 andl(limit, 0xfffffff0); // vector count (in bytes) 8507 jccb(Assembler::zero, COMPARE_TAIL); 8508 8509 lea(ary1, Address(ary1, limit, Address::times_1)); 8510 lea(ary2, Address(ary2, limit, Address::times_1)); 8511 negptr(limit); 8512 8513 bind(COMPARE_WIDE_VECTORS); 8514 movdqu(vec1, Address(ary1, limit, Address::times_1)); 8515 movdqu(vec2, Address(ary2, limit, Address::times_1)); 8516 pxor(vec1, vec2); 8517 8518 ptest(vec1, vec1); 8519 jccb(Assembler::notZero, FALSE_LABEL); 8520 addptr(limit, 16); 8521 jcc(Assembler::notZero, COMPARE_WIDE_VECTORS); 8522 8523 testl(result, result); 8524 jccb(Assembler::zero, TRUE_LABEL); 8525 8526 movdqu(vec1, Address(ary1, result, Address::times_1, -16)); 8527 movdqu(vec2, Address(ary2, result, Address::times_1, -16)); 8528 pxor(vec1, vec2); 8529 8530 ptest(vec1, vec1); 8531 jccb(Assembler::notZero, FALSE_LABEL); 8532 jmpb(TRUE_LABEL); 8533 8534 bind(COMPARE_TAIL); // limit is zero 8535 movl(limit, result); 8536 // Fallthru to tail compare 8537 } 8538 8539 // Compare 4-byte vectors 8540 andl(limit, 0xfffffffc); // vector count (in bytes) 8541 jccb(Assembler::zero, COMPARE_CHAR); 8542 8543 lea(ary1, Address(ary1, limit, Address::times_1)); 8544 lea(ary2, Address(ary2, limit, Address::times_1)); 8545 negptr(limit); 8546 8547 bind(COMPARE_VECTORS); 8548 movl(chr, Address(ary1, limit, Address::times_1)); 8549 cmpl(chr, Address(ary2, limit, Address::times_1)); 8550 jccb(Assembler::notEqual, FALSE_LABEL); 8551 addptr(limit, 4); 8552 jcc(Assembler::notZero, COMPARE_VECTORS); 8553 8554 // Compare trailing char (final 2 bytes), if any 8555 bind(COMPARE_CHAR); 8556 testl(result, 0x2); // tail char 8557 jccb(Assembler::zero, COMPARE_BYTE); 8558 load_unsigned_short(chr, Address(ary1, 0)); 8559 load_unsigned_short(limit, Address(ary2, 0)); 8560 cmpl(chr, limit); 8561 jccb(Assembler::notEqual, FALSE_LABEL); 8562 8563 if (is_array_equ && is_char) { 8564 bind(COMPARE_BYTE); 8565 } else { 8566 lea(ary1, Address(ary1, 2)); 8567 lea(ary2, Address(ary2, 2)); 8568 8569 bind(COMPARE_BYTE); 8570 testl(result, 0x1); // tail byte 8571 jccb(Assembler::zero, TRUE_LABEL); 8572 load_unsigned_byte(chr, Address(ary1, 0)); 8573 load_unsigned_byte(limit, Address(ary2, 0)); 8574 cmpl(chr, limit); 8575 jccb(Assembler::notEqual, FALSE_LABEL); 8576 } 8577 bind(TRUE_LABEL); 8578 movl(result, 1); // return true 8579 jmpb(DONE); 8580 8581 bind(FALSE_LABEL); 8582 xorl(result, result); // return false 8583 8584 // That's it 8585 bind(DONE); 8586 if (UseAVX >= 2) { 8587 // clean upper bits of YMM registers 8588 vpxor(vec1, vec1); 8589 vpxor(vec2, vec2); 8590 } 8591 } 8592 8593 #endif 8594 8595 void MacroAssembler::generate_fill(BasicType t, bool aligned, 8596 Register to, Register value, Register count, 8597 Register rtmp, XMMRegister xtmp) { 8598 ShortBranchVerifier sbv(this); 8599 assert_different_registers(to, value, count, rtmp); 8600 Label L_exit, L_skip_align1, L_skip_align2, L_fill_byte; 8601 Label L_fill_2_bytes, L_fill_4_bytes; 8602 8603 int shift = -1; 8604 switch (t) { 8605 case T_BYTE: 8606 shift = 2; 8607 break; 8608 case T_SHORT: 8609 shift = 1; 8610 break; 8611 case T_INT: 8612 shift = 0; 8613 break; 8614 default: ShouldNotReachHere(); 8615 } 8616 8617 if (t == T_BYTE) { 8618 andl(value, 0xff); 8619 movl(rtmp, value); 8620 shll(rtmp, 8); 8621 orl(value, rtmp); 8622 } 8623 if (t == T_SHORT) { 8624 andl(value, 0xffff); 8625 } 8626 if (t == T_BYTE || t == T_SHORT) { 8627 movl(rtmp, value); 8628 shll(rtmp, 16); 8629 orl(value, rtmp); 8630 } 8631 8632 cmpl(count, 2<<shift); // Short arrays (< 8 bytes) fill by element 8633 jcc(Assembler::below, L_fill_4_bytes); // use unsigned cmp 8634 if (!UseUnalignedLoadStores && !aligned && (t == T_BYTE || t == T_SHORT)) { 8635 // align source address at 4 bytes address boundary 8636 if (t == T_BYTE) { 8637 // One byte misalignment happens only for byte arrays 8638 testptr(to, 1); 8639 jccb(Assembler::zero, L_skip_align1); 8640 movb(Address(to, 0), value); 8641 increment(to); 8642 decrement(count); 8643 BIND(L_skip_align1); 8644 } 8645 // Two bytes misalignment happens only for byte and short (char) arrays 8646 testptr(to, 2); 8647 jccb(Assembler::zero, L_skip_align2); 8648 movw(Address(to, 0), value); 8649 addptr(to, 2); 8650 subl(count, 1<<(shift-1)); 8651 BIND(L_skip_align2); 8652 } 8653 if (UseSSE < 2) { 8654 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8655 // Fill 32-byte chunks 8656 subl(count, 8 << shift); 8657 jcc(Assembler::less, L_check_fill_8_bytes); 8658 align(16); 8659 8660 BIND(L_fill_32_bytes_loop); 8661 8662 for (int i = 0; i < 32; i += 4) { 8663 movl(Address(to, i), value); 8664 } 8665 8666 addptr(to, 32); 8667 subl(count, 8 << shift); 8668 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8669 BIND(L_check_fill_8_bytes); 8670 addl(count, 8 << shift); 8671 jccb(Assembler::zero, L_exit); 8672 jmpb(L_fill_8_bytes); 8673 8674 // 8675 // length is too short, just fill qwords 8676 // 8677 BIND(L_fill_8_bytes_loop); 8678 movl(Address(to, 0), value); 8679 movl(Address(to, 4), value); 8680 addptr(to, 8); 8681 BIND(L_fill_8_bytes); 8682 subl(count, 1 << (shift + 1)); 8683 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8684 // fall through to fill 4 bytes 8685 } else { 8686 Label L_fill_32_bytes; 8687 if (!UseUnalignedLoadStores) { 8688 // align to 8 bytes, we know we are 4 byte aligned to start 8689 testptr(to, 4); 8690 jccb(Assembler::zero, L_fill_32_bytes); 8691 movl(Address(to, 0), value); 8692 addptr(to, 4); 8693 subl(count, 1<<shift); 8694 } 8695 BIND(L_fill_32_bytes); 8696 { 8697 assert( UseSSE >= 2, "supported cpu only" ); 8698 Label L_fill_32_bytes_loop, L_check_fill_8_bytes, L_fill_8_bytes_loop, L_fill_8_bytes; 8699 if (UseAVX > 2) { 8700 movl(rtmp, 0xffff); 8701 kmovwl(k1, rtmp); 8702 } 8703 movdl(xtmp, value); 8704 if (UseAVX > 2 && UseUnalignedLoadStores) { 8705 // Fill 64-byte chunks 8706 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8707 evpbroadcastd(xtmp, xtmp, Assembler::AVX_512bit); 8708 8709 subl(count, 16 << shift); 8710 jcc(Assembler::less, L_check_fill_32_bytes); 8711 align(16); 8712 8713 BIND(L_fill_64_bytes_loop); 8714 evmovdqul(Address(to, 0), xtmp, Assembler::AVX_512bit); 8715 addptr(to, 64); 8716 subl(count, 16 << shift); 8717 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8718 8719 BIND(L_check_fill_32_bytes); 8720 addl(count, 8 << shift); 8721 jccb(Assembler::less, L_check_fill_8_bytes); 8722 vmovdqu(Address(to, 0), xtmp); 8723 addptr(to, 32); 8724 subl(count, 8 << shift); 8725 8726 BIND(L_check_fill_8_bytes); 8727 } else if (UseAVX == 2 && UseUnalignedLoadStores) { 8728 // Fill 64-byte chunks 8729 Label L_fill_64_bytes_loop, L_check_fill_32_bytes; 8730 vpbroadcastd(xtmp, xtmp); 8731 8732 subl(count, 16 << shift); 8733 jcc(Assembler::less, L_check_fill_32_bytes); 8734 align(16); 8735 8736 BIND(L_fill_64_bytes_loop); 8737 vmovdqu(Address(to, 0), xtmp); 8738 vmovdqu(Address(to, 32), xtmp); 8739 addptr(to, 64); 8740 subl(count, 16 << shift); 8741 jcc(Assembler::greaterEqual, L_fill_64_bytes_loop); 8742 8743 BIND(L_check_fill_32_bytes); 8744 addl(count, 8 << shift); 8745 jccb(Assembler::less, L_check_fill_8_bytes); 8746 vmovdqu(Address(to, 0), xtmp); 8747 addptr(to, 32); 8748 subl(count, 8 << shift); 8749 8750 BIND(L_check_fill_8_bytes); 8751 // clean upper bits of YMM registers 8752 movdl(xtmp, value); 8753 pshufd(xtmp, xtmp, 0); 8754 } else { 8755 // Fill 32-byte chunks 8756 pshufd(xtmp, xtmp, 0); 8757 8758 subl(count, 8 << shift); 8759 jcc(Assembler::less, L_check_fill_8_bytes); 8760 align(16); 8761 8762 BIND(L_fill_32_bytes_loop); 8763 8764 if (UseUnalignedLoadStores) { 8765 movdqu(Address(to, 0), xtmp); 8766 movdqu(Address(to, 16), xtmp); 8767 } else { 8768 movq(Address(to, 0), xtmp); 8769 movq(Address(to, 8), xtmp); 8770 movq(Address(to, 16), xtmp); 8771 movq(Address(to, 24), xtmp); 8772 } 8773 8774 addptr(to, 32); 8775 subl(count, 8 << shift); 8776 jcc(Assembler::greaterEqual, L_fill_32_bytes_loop); 8777 8778 BIND(L_check_fill_8_bytes); 8779 } 8780 addl(count, 8 << shift); 8781 jccb(Assembler::zero, L_exit); 8782 jmpb(L_fill_8_bytes); 8783 8784 // 8785 // length is too short, just fill qwords 8786 // 8787 BIND(L_fill_8_bytes_loop); 8788 movq(Address(to, 0), xtmp); 8789 addptr(to, 8); 8790 BIND(L_fill_8_bytes); 8791 subl(count, 1 << (shift + 1)); 8792 jcc(Assembler::greaterEqual, L_fill_8_bytes_loop); 8793 } 8794 } 8795 // fill trailing 4 bytes 8796 BIND(L_fill_4_bytes); 8797 testl(count, 1<<shift); 8798 jccb(Assembler::zero, L_fill_2_bytes); 8799 movl(Address(to, 0), value); 8800 if (t == T_BYTE || t == T_SHORT) { 8801 addptr(to, 4); 8802 BIND(L_fill_2_bytes); 8803 // fill trailing 2 bytes 8804 testl(count, 1<<(shift-1)); 8805 jccb(Assembler::zero, L_fill_byte); 8806 movw(Address(to, 0), value); 8807 if (t == T_BYTE) { 8808 addptr(to, 2); 8809 BIND(L_fill_byte); 8810 // fill trailing byte 8811 testl(count, 1); 8812 jccb(Assembler::zero, L_exit); 8813 movb(Address(to, 0), value); 8814 } else { 8815 BIND(L_fill_byte); 8816 } 8817 } else { 8818 BIND(L_fill_2_bytes); 8819 } 8820 BIND(L_exit); 8821 } 8822 8823 // encode char[] to byte[] in ISO_8859_1 8824 void MacroAssembler::encode_iso_array(Register src, Register dst, Register len, 8825 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 8826 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 8827 Register tmp5, Register result) { 8828 // rsi: src 8829 // rdi: dst 8830 // rdx: len 8831 // rcx: tmp5 8832 // rax: result 8833 ShortBranchVerifier sbv(this); 8834 assert_different_registers(src, dst, len, tmp5, result); 8835 Label L_done, L_copy_1_char, L_copy_1_char_exit; 8836 8837 // set result 8838 xorl(result, result); 8839 // check for zero length 8840 testl(len, len); 8841 jcc(Assembler::zero, L_done); 8842 movl(result, len); 8843 8844 // Setup pointers 8845 lea(src, Address(src, len, Address::times_2)); // char[] 8846 lea(dst, Address(dst, len, Address::times_1)); // byte[] 8847 negptr(len); 8848 8849 if (UseSSE42Intrinsics || UseAVX >= 2) { 8850 assert(UseSSE42Intrinsics ? UseSSE >= 4 : true, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 8851 Label L_chars_8_check, L_copy_8_chars, L_copy_8_chars_exit; 8852 Label L_chars_16_check, L_copy_16_chars, L_copy_16_chars_exit; 8853 8854 if (UseAVX >= 2) { 8855 Label L_chars_32_check, L_copy_32_chars, L_copy_32_chars_exit; 8856 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8857 movdl(tmp1Reg, tmp5); 8858 vpbroadcastd(tmp1Reg, tmp1Reg); 8859 jmpb(L_chars_32_check); 8860 8861 bind(L_copy_32_chars); 8862 vmovdqu(tmp3Reg, Address(src, len, Address::times_2, -64)); 8863 vmovdqu(tmp4Reg, Address(src, len, Address::times_2, -32)); 8864 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8865 vptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8866 jccb(Assembler::notZero, L_copy_32_chars_exit); 8867 vpackuswb(tmp3Reg, tmp3Reg, tmp4Reg, /* vector_len */ 1); 8868 vpermq(tmp4Reg, tmp3Reg, 0xD8, /* vector_len */ 1); 8869 vmovdqu(Address(dst, len, Address::times_1, -32), tmp4Reg); 8870 8871 bind(L_chars_32_check); 8872 addptr(len, 32); 8873 jccb(Assembler::lessEqual, L_copy_32_chars); 8874 8875 bind(L_copy_32_chars_exit); 8876 subptr(len, 16); 8877 jccb(Assembler::greater, L_copy_16_chars_exit); 8878 8879 } else if (UseSSE42Intrinsics) { 8880 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vector 8881 movdl(tmp1Reg, tmp5); 8882 pshufd(tmp1Reg, tmp1Reg, 0); 8883 jmpb(L_chars_16_check); 8884 } 8885 8886 bind(L_copy_16_chars); 8887 if (UseAVX >= 2) { 8888 vmovdqu(tmp2Reg, Address(src, len, Address::times_2, -32)); 8889 vptest(tmp2Reg, tmp1Reg); 8890 jccb(Assembler::notZero, L_copy_16_chars_exit); 8891 vpackuswb(tmp2Reg, tmp2Reg, tmp1Reg, /* vector_len */ 1); 8892 vpermq(tmp3Reg, tmp2Reg, 0xD8, /* vector_len */ 1); 8893 } else { 8894 if (UseAVX > 0) { 8895 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8896 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8897 vpor(tmp2Reg, tmp3Reg, tmp4Reg, /* vector_len */ 0); 8898 } else { 8899 movdqu(tmp3Reg, Address(src, len, Address::times_2, -32)); 8900 por(tmp2Reg, tmp3Reg); 8901 movdqu(tmp4Reg, Address(src, len, Address::times_2, -16)); 8902 por(tmp2Reg, tmp4Reg); 8903 } 8904 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 8905 jccb(Assembler::notZero, L_copy_16_chars_exit); 8906 packuswb(tmp3Reg, tmp4Reg); 8907 } 8908 movdqu(Address(dst, len, Address::times_1, -16), tmp3Reg); 8909 8910 bind(L_chars_16_check); 8911 addptr(len, 16); 8912 jccb(Assembler::lessEqual, L_copy_16_chars); 8913 8914 bind(L_copy_16_chars_exit); 8915 if (UseAVX >= 2) { 8916 // clean upper bits of YMM registers 8917 vpxor(tmp2Reg, tmp2Reg); 8918 vpxor(tmp3Reg, tmp3Reg); 8919 vpxor(tmp4Reg, tmp4Reg); 8920 movdl(tmp1Reg, tmp5); 8921 pshufd(tmp1Reg, tmp1Reg, 0); 8922 } 8923 subptr(len, 8); 8924 jccb(Assembler::greater, L_copy_8_chars_exit); 8925 8926 bind(L_copy_8_chars); 8927 movdqu(tmp3Reg, Address(src, len, Address::times_2, -16)); 8928 ptest(tmp3Reg, tmp1Reg); 8929 jccb(Assembler::notZero, L_copy_8_chars_exit); 8930 packuswb(tmp3Reg, tmp1Reg); 8931 movq(Address(dst, len, Address::times_1, -8), tmp3Reg); 8932 addptr(len, 8); 8933 jccb(Assembler::lessEqual, L_copy_8_chars); 8934 8935 bind(L_copy_8_chars_exit); 8936 subptr(len, 8); 8937 jccb(Assembler::zero, L_done); 8938 } 8939 8940 bind(L_copy_1_char); 8941 load_unsigned_short(tmp5, Address(src, len, Address::times_2, 0)); 8942 testl(tmp5, 0xff00); // check if Unicode char 8943 jccb(Assembler::notZero, L_copy_1_char_exit); 8944 movb(Address(dst, len, Address::times_1, 0), tmp5); 8945 addptr(len, 1); 8946 jccb(Assembler::less, L_copy_1_char); 8947 8948 bind(L_copy_1_char_exit); 8949 addptr(result, len); // len is negative count of not processed elements 8950 bind(L_done); 8951 } 8952 8953 #ifdef _LP64 8954 /** 8955 * Helper for multiply_to_len(). 8956 */ 8957 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) { 8958 addq(dest_lo, src1); 8959 adcq(dest_hi, 0); 8960 addq(dest_lo, src2); 8961 adcq(dest_hi, 0); 8962 } 8963 8964 /** 8965 * Multiply 64 bit by 64 bit first loop. 8966 */ 8967 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart, 8968 Register y, Register y_idx, Register z, 8969 Register carry, Register product, 8970 Register idx, Register kdx) { 8971 // 8972 // jlong carry, x[], y[], z[]; 8973 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 8974 // huge_128 product = y[idx] * x[xstart] + carry; 8975 // z[kdx] = (jlong)product; 8976 // carry = (jlong)(product >>> 64); 8977 // } 8978 // z[xstart] = carry; 8979 // 8980 8981 Label L_first_loop, L_first_loop_exit; 8982 Label L_one_x, L_one_y, L_multiply; 8983 8984 decrementl(xstart); 8985 jcc(Assembler::negative, L_one_x); 8986 8987 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 8988 rorq(x_xstart, 32); // convert big-endian to little-endian 8989 8990 bind(L_first_loop); 8991 decrementl(idx); 8992 jcc(Assembler::negative, L_first_loop_exit); 8993 decrementl(idx); 8994 jcc(Assembler::negative, L_one_y); 8995 movq(y_idx, Address(y, idx, Address::times_4, 0)); 8996 rorq(y_idx, 32); // convert big-endian to little-endian 8997 bind(L_multiply); 8998 movq(product, x_xstart); 8999 mulq(y_idx); // product(rax) * y_idx -> rdx:rax 9000 addq(product, carry); 9001 adcq(rdx, 0); 9002 subl(kdx, 2); 9003 movl(Address(z, kdx, Address::times_4, 4), product); 9004 shrq(product, 32); 9005 movl(Address(z, kdx, Address::times_4, 0), product); 9006 movq(carry, rdx); 9007 jmp(L_first_loop); 9008 9009 bind(L_one_y); 9010 movl(y_idx, Address(y, 0)); 9011 jmp(L_multiply); 9012 9013 bind(L_one_x); 9014 movl(x_xstart, Address(x, 0)); 9015 jmp(L_first_loop); 9016 9017 bind(L_first_loop_exit); 9018 } 9019 9020 /** 9021 * Multiply 64 bit by 64 bit and add 128 bit. 9022 */ 9023 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y, Register z, 9024 Register yz_idx, Register idx, 9025 Register carry, Register product, int offset) { 9026 // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry; 9027 // z[kdx] = (jlong)product; 9028 9029 movq(yz_idx, Address(y, idx, Address::times_4, offset)); 9030 rorq(yz_idx, 32); // convert big-endian to little-endian 9031 movq(product, x_xstart); 9032 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 9033 movq(yz_idx, Address(z, idx, Address::times_4, offset)); 9034 rorq(yz_idx, 32); // convert big-endian to little-endian 9035 9036 add2_with_carry(rdx, product, carry, yz_idx); 9037 9038 movl(Address(z, idx, Address::times_4, offset+4), product); 9039 shrq(product, 32); 9040 movl(Address(z, idx, Address::times_4, offset), product); 9041 9042 } 9043 9044 /** 9045 * Multiply 128 bit by 128 bit. Unrolled inner loop. 9046 */ 9047 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart, Register y, Register z, 9048 Register yz_idx, Register idx, Register jdx, 9049 Register carry, Register product, 9050 Register carry2) { 9051 // jlong carry, x[], y[], z[]; 9052 // int kdx = ystart+1; 9053 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 9054 // huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry; 9055 // z[kdx+idx+1] = (jlong)product; 9056 // jlong carry2 = (jlong)(product >>> 64); 9057 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry2; 9058 // z[kdx+idx] = (jlong)product; 9059 // carry = (jlong)(product >>> 64); 9060 // } 9061 // idx += 2; 9062 // if (idx > 0) { 9063 // product = (y[idx] * x_xstart) + z[kdx+idx] + carry; 9064 // z[kdx+idx] = (jlong)product; 9065 // carry = (jlong)(product >>> 64); 9066 // } 9067 // 9068 9069 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9070 9071 movl(jdx, idx); 9072 andl(jdx, 0xFFFFFFFC); 9073 shrl(jdx, 2); 9074 9075 bind(L_third_loop); 9076 subl(jdx, 1); 9077 jcc(Assembler::negative, L_third_loop_exit); 9078 subl(idx, 4); 9079 9080 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8); 9081 movq(carry2, rdx); 9082 9083 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0); 9084 movq(carry, rdx); 9085 jmp(L_third_loop); 9086 9087 bind (L_third_loop_exit); 9088 9089 andl (idx, 0x3); 9090 jcc(Assembler::zero, L_post_third_loop_done); 9091 9092 Label L_check_1; 9093 subl(idx, 2); 9094 jcc(Assembler::negative, L_check_1); 9095 9096 multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0); 9097 movq(carry, rdx); 9098 9099 bind (L_check_1); 9100 addl (idx, 0x2); 9101 andl (idx, 0x1); 9102 subl(idx, 1); 9103 jcc(Assembler::negative, L_post_third_loop_done); 9104 9105 movl(yz_idx, Address(y, idx, Address::times_4, 0)); 9106 movq(product, x_xstart); 9107 mulq(yz_idx); // product(rax) * yz_idx -> rdx:product(rax) 9108 movl(yz_idx, Address(z, idx, Address::times_4, 0)); 9109 9110 add2_with_carry(rdx, product, yz_idx, carry); 9111 9112 movl(Address(z, idx, Address::times_4, 0), product); 9113 shrq(product, 32); 9114 9115 shlq(rdx, 32); 9116 orq(product, rdx); 9117 movq(carry, product); 9118 9119 bind(L_post_third_loop_done); 9120 } 9121 9122 /** 9123 * Multiply 128 bit by 128 bit using BMI2. Unrolled inner loop. 9124 * 9125 */ 9126 void MacroAssembler::multiply_128_x_128_bmi2_loop(Register y, Register z, 9127 Register carry, Register carry2, 9128 Register idx, Register jdx, 9129 Register yz_idx1, Register yz_idx2, 9130 Register tmp, Register tmp3, Register tmp4) { 9131 assert(UseBMI2Instructions, "should be used only when BMI2 is available"); 9132 9133 // jlong carry, x[], y[], z[]; 9134 // int kdx = ystart+1; 9135 // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop 9136 // huge_128 tmp3 = (y[idx+1] * rdx) + z[kdx+idx+1] + carry; 9137 // jlong carry2 = (jlong)(tmp3 >>> 64); 9138 // huge_128 tmp4 = (y[idx] * rdx) + z[kdx+idx] + carry2; 9139 // carry = (jlong)(tmp4 >>> 64); 9140 // z[kdx+idx+1] = (jlong)tmp3; 9141 // z[kdx+idx] = (jlong)tmp4; 9142 // } 9143 // idx += 2; 9144 // if (idx > 0) { 9145 // yz_idx1 = (y[idx] * rdx) + z[kdx+idx] + carry; 9146 // z[kdx+idx] = (jlong)yz_idx1; 9147 // carry = (jlong)(yz_idx1 >>> 64); 9148 // } 9149 // 9150 9151 Label L_third_loop, L_third_loop_exit, L_post_third_loop_done; 9152 9153 movl(jdx, idx); 9154 andl(jdx, 0xFFFFFFFC); 9155 shrl(jdx, 2); 9156 9157 bind(L_third_loop); 9158 subl(jdx, 1); 9159 jcc(Assembler::negative, L_third_loop_exit); 9160 subl(idx, 4); 9161 9162 movq(yz_idx1, Address(y, idx, Address::times_4, 8)); 9163 rorxq(yz_idx1, yz_idx1, 32); // convert big-endian to little-endian 9164 movq(yz_idx2, Address(y, idx, Address::times_4, 0)); 9165 rorxq(yz_idx2, yz_idx2, 32); 9166 9167 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9168 mulxq(carry2, tmp, yz_idx2); // yz_idx2 * rdx -> carry2:tmp 9169 9170 movq(yz_idx1, Address(z, idx, Address::times_4, 8)); 9171 rorxq(yz_idx1, yz_idx1, 32); 9172 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9173 rorxq(yz_idx2, yz_idx2, 32); 9174 9175 if (VM_Version::supports_adx()) { 9176 adcxq(tmp3, carry); 9177 adoxq(tmp3, yz_idx1); 9178 9179 adcxq(tmp4, tmp); 9180 adoxq(tmp4, yz_idx2); 9181 9182 movl(carry, 0); // does not affect flags 9183 adcxq(carry2, carry); 9184 adoxq(carry2, carry); 9185 } else { 9186 add2_with_carry(tmp4, tmp3, carry, yz_idx1); 9187 add2_with_carry(carry2, tmp4, tmp, yz_idx2); 9188 } 9189 movq(carry, carry2); 9190 9191 movl(Address(z, idx, Address::times_4, 12), tmp3); 9192 shrq(tmp3, 32); 9193 movl(Address(z, idx, Address::times_4, 8), tmp3); 9194 9195 movl(Address(z, idx, Address::times_4, 4), tmp4); 9196 shrq(tmp4, 32); 9197 movl(Address(z, idx, Address::times_4, 0), tmp4); 9198 9199 jmp(L_third_loop); 9200 9201 bind (L_third_loop_exit); 9202 9203 andl (idx, 0x3); 9204 jcc(Assembler::zero, L_post_third_loop_done); 9205 9206 Label L_check_1; 9207 subl(idx, 2); 9208 jcc(Assembler::negative, L_check_1); 9209 9210 movq(yz_idx1, Address(y, idx, Address::times_4, 0)); 9211 rorxq(yz_idx1, yz_idx1, 32); 9212 mulxq(tmp4, tmp3, yz_idx1); // yz_idx1 * rdx -> tmp4:tmp3 9213 movq(yz_idx2, Address(z, idx, Address::times_4, 0)); 9214 rorxq(yz_idx2, yz_idx2, 32); 9215 9216 add2_with_carry(tmp4, tmp3, carry, yz_idx2); 9217 9218 movl(Address(z, idx, Address::times_4, 4), tmp3); 9219 shrq(tmp3, 32); 9220 movl(Address(z, idx, Address::times_4, 0), tmp3); 9221 movq(carry, tmp4); 9222 9223 bind (L_check_1); 9224 addl (idx, 0x2); 9225 andl (idx, 0x1); 9226 subl(idx, 1); 9227 jcc(Assembler::negative, L_post_third_loop_done); 9228 movl(tmp4, Address(y, idx, Address::times_4, 0)); 9229 mulxq(carry2, tmp3, tmp4); // tmp4 * rdx -> carry2:tmp3 9230 movl(tmp4, Address(z, idx, Address::times_4, 0)); 9231 9232 add2_with_carry(carry2, tmp3, tmp4, carry); 9233 9234 movl(Address(z, idx, Address::times_4, 0), tmp3); 9235 shrq(tmp3, 32); 9236 9237 shlq(carry2, 32); 9238 orq(tmp3, carry2); 9239 movq(carry, tmp3); 9240 9241 bind(L_post_third_loop_done); 9242 } 9243 9244 /** 9245 * Code for BigInteger::multiplyToLen() instrinsic. 9246 * 9247 * rdi: x 9248 * rax: xlen 9249 * rsi: y 9250 * rcx: ylen 9251 * r8: z 9252 * r11: zlen 9253 * r12: tmp1 9254 * r13: tmp2 9255 * r14: tmp3 9256 * r15: tmp4 9257 * rbx: tmp5 9258 * 9259 */ 9260 void MacroAssembler::multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z, Register zlen, 9261 Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5) { 9262 ShortBranchVerifier sbv(this); 9263 assert_different_registers(x, xlen, y, ylen, z, zlen, tmp1, tmp2, tmp3, tmp4, tmp5, rdx); 9264 9265 push(tmp1); 9266 push(tmp2); 9267 push(tmp3); 9268 push(tmp4); 9269 push(tmp5); 9270 9271 push(xlen); 9272 push(zlen); 9273 9274 const Register idx = tmp1; 9275 const Register kdx = tmp2; 9276 const Register xstart = tmp3; 9277 9278 const Register y_idx = tmp4; 9279 const Register carry = tmp5; 9280 const Register product = xlen; 9281 const Register x_xstart = zlen; // reuse register 9282 9283 // First Loop. 9284 // 9285 // final static long LONG_MASK = 0xffffffffL; 9286 // int xstart = xlen - 1; 9287 // int ystart = ylen - 1; 9288 // long carry = 0; 9289 // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) { 9290 // long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry; 9291 // z[kdx] = (int)product; 9292 // carry = product >>> 32; 9293 // } 9294 // z[xstart] = (int)carry; 9295 // 9296 9297 movl(idx, ylen); // idx = ylen; 9298 movl(kdx, zlen); // kdx = xlen+ylen; 9299 xorq(carry, carry); // carry = 0; 9300 9301 Label L_done; 9302 9303 movl(xstart, xlen); 9304 decrementl(xstart); 9305 jcc(Assembler::negative, L_done); 9306 9307 multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx); 9308 9309 Label L_second_loop; 9310 testl(kdx, kdx); 9311 jcc(Assembler::zero, L_second_loop); 9312 9313 Label L_carry; 9314 subl(kdx, 1); 9315 jcc(Assembler::zero, L_carry); 9316 9317 movl(Address(z, kdx, Address::times_4, 0), carry); 9318 shrq(carry, 32); 9319 subl(kdx, 1); 9320 9321 bind(L_carry); 9322 movl(Address(z, kdx, Address::times_4, 0), carry); 9323 9324 // Second and third (nested) loops. 9325 // 9326 // for (int i = xstart-1; i >= 0; i--) { // Second loop 9327 // carry = 0; 9328 // for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop 9329 // long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) + 9330 // (z[k] & LONG_MASK) + carry; 9331 // z[k] = (int)product; 9332 // carry = product >>> 32; 9333 // } 9334 // z[i] = (int)carry; 9335 // } 9336 // 9337 // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx 9338 9339 const Register jdx = tmp1; 9340 9341 bind(L_second_loop); 9342 xorl(carry, carry); // carry = 0; 9343 movl(jdx, ylen); // j = ystart+1 9344 9345 subl(xstart, 1); // i = xstart-1; 9346 jcc(Assembler::negative, L_done); 9347 9348 push (z); 9349 9350 Label L_last_x; 9351 lea(z, Address(z, xstart, Address::times_4, 4)); // z = z + k - j 9352 subl(xstart, 1); // i = xstart-1; 9353 jcc(Assembler::negative, L_last_x); 9354 9355 if (UseBMI2Instructions) { 9356 movq(rdx, Address(x, xstart, Address::times_4, 0)); 9357 rorxq(rdx, rdx, 32); // convert big-endian to little-endian 9358 } else { 9359 movq(x_xstart, Address(x, xstart, Address::times_4, 0)); 9360 rorq(x_xstart, 32); // convert big-endian to little-endian 9361 } 9362 9363 Label L_third_loop_prologue; 9364 bind(L_third_loop_prologue); 9365 9366 push (x); 9367 push (xstart); 9368 push (ylen); 9369 9370 9371 if (UseBMI2Instructions) { 9372 multiply_128_x_128_bmi2_loop(y, z, carry, x, jdx, ylen, product, tmp2, x_xstart, tmp3, tmp4); 9373 } else { // !UseBMI2Instructions 9374 multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x); 9375 } 9376 9377 pop(ylen); 9378 pop(xlen); 9379 pop(x); 9380 pop(z); 9381 9382 movl(tmp3, xlen); 9383 addl(tmp3, 1); 9384 movl(Address(z, tmp3, Address::times_4, 0), carry); 9385 subl(tmp3, 1); 9386 jccb(Assembler::negative, L_done); 9387 9388 shrq(carry, 32); 9389 movl(Address(z, tmp3, Address::times_4, 0), carry); 9390 jmp(L_second_loop); 9391 9392 // Next infrequent code is moved outside loops. 9393 bind(L_last_x); 9394 if (UseBMI2Instructions) { 9395 movl(rdx, Address(x, 0)); 9396 } else { 9397 movl(x_xstart, Address(x, 0)); 9398 } 9399 jmp(L_third_loop_prologue); 9400 9401 bind(L_done); 9402 9403 pop(zlen); 9404 pop(xlen); 9405 9406 pop(tmp5); 9407 pop(tmp4); 9408 pop(tmp3); 9409 pop(tmp2); 9410 pop(tmp1); 9411 } 9412 9413 void MacroAssembler::vectorized_mismatch(Register obja, Register objb, Register length, Register log2_array_indxscale, 9414 Register result, Register tmp1, Register tmp2, XMMRegister rymm0, XMMRegister rymm1, XMMRegister rymm2){ 9415 assert(UseSSE42Intrinsics, "SSE4.2 must be enabled."); 9416 Label VECTOR32_LOOP, VECTOR16_LOOP, VECTOR8_LOOP, VECTOR4_LOOP; 9417 Label VECTOR16_TAIL, VECTOR8_TAIL, VECTOR4_TAIL; 9418 Label VECTOR32_NOT_EQUAL, VECTOR16_NOT_EQUAL, VECTOR8_NOT_EQUAL, VECTOR4_NOT_EQUAL; 9419 Label SAME_TILL_END, DONE; 9420 Label BYTES_LOOP, BYTES_TAIL, BYTES_NOT_EQUAL; 9421 9422 //scale is in rcx in both Win64 and Unix 9423 ShortBranchVerifier sbv(this); 9424 9425 shlq(length); 9426 xorq(result, result); 9427 9428 cmpq(length, 8); 9429 jcc(Assembler::equal, VECTOR8_LOOP); 9430 jcc(Assembler::less, VECTOR4_TAIL); 9431 9432 if (UseAVX >= 2){ 9433 9434 cmpq(length, 16); 9435 jcc(Assembler::equal, VECTOR16_LOOP); 9436 jcc(Assembler::less, VECTOR8_LOOP); 9437 9438 cmpq(length, 32); 9439 jccb(Assembler::less, VECTOR16_TAIL); 9440 9441 subq(length, 32); 9442 bind(VECTOR32_LOOP); 9443 vmovdqu(rymm0, Address(obja, result)); 9444 vmovdqu(rymm1, Address(objb, result)); 9445 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_256bit); 9446 vptest(rymm2, rymm2); 9447 jcc(Assembler::notZero, VECTOR32_NOT_EQUAL);//mismatch found 9448 addq(result, 32); 9449 subq(length, 32); 9450 jccb(Assembler::greaterEqual, VECTOR32_LOOP); 9451 addq(length, 32); 9452 jcc(Assembler::equal, SAME_TILL_END); 9453 //falling through if less than 32 bytes left //close the branch here. 9454 9455 bind(VECTOR16_TAIL); 9456 cmpq(length, 16); 9457 jccb(Assembler::less, VECTOR8_TAIL); 9458 bind(VECTOR16_LOOP); 9459 movdqu(rymm0, Address(obja, result)); 9460 movdqu(rymm1, Address(objb, result)); 9461 vpxor(rymm2, rymm0, rymm1, Assembler::AVX_128bit); 9462 ptest(rymm2, rymm2); 9463 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9464 addq(result, 16); 9465 subq(length, 16); 9466 jcc(Assembler::equal, SAME_TILL_END); 9467 //falling through if less than 16 bytes left 9468 } else {//regular intrinsics 9469 9470 cmpq(length, 16); 9471 jccb(Assembler::less, VECTOR8_TAIL); 9472 9473 subq(length, 16); 9474 bind(VECTOR16_LOOP); 9475 movdqu(rymm0, Address(obja, result)); 9476 movdqu(rymm1, Address(objb, result)); 9477 pxor(rymm0, rymm1); 9478 ptest(rymm0, rymm0); 9479 jcc(Assembler::notZero, VECTOR16_NOT_EQUAL);//mismatch found 9480 addq(result, 16); 9481 subq(length, 16); 9482 jccb(Assembler::greaterEqual, VECTOR16_LOOP); 9483 addq(length, 16); 9484 jcc(Assembler::equal, SAME_TILL_END); 9485 //falling through if less than 16 bytes left 9486 } 9487 9488 bind(VECTOR8_TAIL); 9489 cmpq(length, 8); 9490 jccb(Assembler::less, VECTOR4_TAIL); 9491 bind(VECTOR8_LOOP); 9492 movq(tmp1, Address(obja, result)); 9493 movq(tmp2, Address(objb, result)); 9494 xorq(tmp1, tmp2); 9495 testq(tmp1, tmp1); 9496 jcc(Assembler::notZero, VECTOR8_NOT_EQUAL);//mismatch found 9497 addq(result, 8); 9498 subq(length, 8); 9499 jcc(Assembler::equal, SAME_TILL_END); 9500 //falling through if less than 8 bytes left 9501 9502 bind(VECTOR4_TAIL); 9503 cmpq(length, 4); 9504 jccb(Assembler::less, BYTES_TAIL); 9505 bind(VECTOR4_LOOP); 9506 movl(tmp1, Address(obja, result)); 9507 xorl(tmp1, Address(objb, result)); 9508 testl(tmp1, tmp1); 9509 jcc(Assembler::notZero, VECTOR4_NOT_EQUAL);//mismatch found 9510 addq(result, 4); 9511 subq(length, 4); 9512 jcc(Assembler::equal, SAME_TILL_END); 9513 //falling through if less than 4 bytes left 9514 9515 bind(BYTES_TAIL); 9516 bind(BYTES_LOOP); 9517 load_unsigned_byte(tmp1, Address(obja, result)); 9518 load_unsigned_byte(tmp2, Address(objb, result)); 9519 xorl(tmp1, tmp2); 9520 testl(tmp1, tmp1); 9521 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9522 decq(length); 9523 jccb(Assembler::zero, SAME_TILL_END); 9524 incq(result); 9525 load_unsigned_byte(tmp1, Address(obja, result)); 9526 load_unsigned_byte(tmp2, Address(objb, result)); 9527 xorl(tmp1, tmp2); 9528 testl(tmp1, tmp1); 9529 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9530 decq(length); 9531 jccb(Assembler::zero, SAME_TILL_END); 9532 incq(result); 9533 load_unsigned_byte(tmp1, Address(obja, result)); 9534 load_unsigned_byte(tmp2, Address(objb, result)); 9535 xorl(tmp1, tmp2); 9536 testl(tmp1, tmp1); 9537 jccb(Assembler::notZero, BYTES_NOT_EQUAL);//mismatch found 9538 jmpb(SAME_TILL_END); 9539 9540 if (UseAVX >= 2){ 9541 bind(VECTOR32_NOT_EQUAL); 9542 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_256bit); 9543 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_256bit); 9544 vpxor(rymm0, rymm0, rymm2, Assembler::AVX_256bit); 9545 vpmovmskb(tmp1, rymm0); 9546 bsfq(tmp1, tmp1); 9547 addq(result, tmp1); 9548 shrq(result); 9549 jmpb(DONE); 9550 } 9551 9552 bind(VECTOR16_NOT_EQUAL); 9553 if (UseAVX >= 2){ 9554 vpcmpeqb(rymm2, rymm2, rymm2, Assembler::AVX_128bit); 9555 vpcmpeqb(rymm0, rymm0, rymm1, Assembler::AVX_128bit); 9556 pxor(rymm0, rymm2); 9557 } else { 9558 pcmpeqb(rymm2, rymm2); 9559 pxor(rymm0, rymm1); 9560 pcmpeqb(rymm0, rymm1); 9561 pxor(rymm0, rymm2); 9562 } 9563 pmovmskb(tmp1, rymm0); 9564 bsfq(tmp1, tmp1); 9565 addq(result, tmp1); 9566 shrq(result); 9567 jmpb(DONE); 9568 9569 bind(VECTOR8_NOT_EQUAL); 9570 bind(VECTOR4_NOT_EQUAL); 9571 bsfq(tmp1, tmp1); 9572 shrq(tmp1, 3); 9573 addq(result, tmp1); 9574 bind(BYTES_NOT_EQUAL); 9575 shrq(result); 9576 jmpb(DONE); 9577 9578 bind(SAME_TILL_END); 9579 mov64(result, -1); 9580 9581 bind(DONE); 9582 } 9583 9584 9585 //Helper functions for square_to_len() 9586 9587 /** 9588 * Store the squares of x[], right shifted one bit (divided by 2) into z[] 9589 * Preserves x and z and modifies rest of the registers. 9590 */ 9591 void MacroAssembler::square_rshift(Register x, Register xlen, Register z, Register tmp1, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9592 // Perform square and right shift by 1 9593 // Handle odd xlen case first, then for even xlen do the following 9594 // jlong carry = 0; 9595 // for (int j=0, i=0; j < xlen; j+=2, i+=4) { 9596 // huge_128 product = x[j:j+1] * x[j:j+1]; 9597 // z[i:i+1] = (carry << 63) | (jlong)(product >>> 65); 9598 // z[i+2:i+3] = (jlong)(product >>> 1); 9599 // carry = (jlong)product; 9600 // } 9601 9602 xorq(tmp5, tmp5); // carry 9603 xorq(rdxReg, rdxReg); 9604 xorl(tmp1, tmp1); // index for x 9605 xorl(tmp4, tmp4); // index for z 9606 9607 Label L_first_loop, L_first_loop_exit; 9608 9609 testl(xlen, 1); 9610 jccb(Assembler::zero, L_first_loop); //jump if xlen is even 9611 9612 // Square and right shift by 1 the odd element using 32 bit multiply 9613 movl(raxReg, Address(x, tmp1, Address::times_4, 0)); 9614 imulq(raxReg, raxReg); 9615 shrq(raxReg, 1); 9616 adcq(tmp5, 0); 9617 movq(Address(z, tmp4, Address::times_4, 0), raxReg); 9618 incrementl(tmp1); 9619 addl(tmp4, 2); 9620 9621 // Square and right shift by 1 the rest using 64 bit multiply 9622 bind(L_first_loop); 9623 cmpptr(tmp1, xlen); 9624 jccb(Assembler::equal, L_first_loop_exit); 9625 9626 // Square 9627 movq(raxReg, Address(x, tmp1, Address::times_4, 0)); 9628 rorq(raxReg, 32); // convert big-endian to little-endian 9629 mulq(raxReg); // 64-bit multiply rax * rax -> rdx:rax 9630 9631 // Right shift by 1 and save carry 9632 shrq(tmp5, 1); // rdx:rax:tmp5 = (tmp5:rdx:rax) >>> 1 9633 rcrq(rdxReg, 1); 9634 rcrq(raxReg, 1); 9635 adcq(tmp5, 0); 9636 9637 // Store result in z 9638 movq(Address(z, tmp4, Address::times_4, 0), rdxReg); 9639 movq(Address(z, tmp4, Address::times_4, 8), raxReg); 9640 9641 // Update indices for x and z 9642 addl(tmp1, 2); 9643 addl(tmp4, 4); 9644 jmp(L_first_loop); 9645 9646 bind(L_first_loop_exit); 9647 } 9648 9649 9650 /** 9651 * Perform the following multiply add operation using BMI2 instructions 9652 * carry:sum = sum + op1*op2 + carry 9653 * op2 should be in rdx 9654 * op2 is preserved, all other registers are modified 9655 */ 9656 void MacroAssembler::multiply_add_64_bmi2(Register sum, Register op1, Register op2, Register carry, Register tmp2) { 9657 // assert op2 is rdx 9658 mulxq(tmp2, op1, op1); // op1 * op2 -> tmp2:op1 9659 addq(sum, carry); 9660 adcq(tmp2, 0); 9661 addq(sum, op1); 9662 adcq(tmp2, 0); 9663 movq(carry, tmp2); 9664 } 9665 9666 /** 9667 * Perform the following multiply add operation: 9668 * carry:sum = sum + op1*op2 + carry 9669 * Preserves op1, op2 and modifies rest of registers 9670 */ 9671 void MacroAssembler::multiply_add_64(Register sum, Register op1, Register op2, Register carry, Register rdxReg, Register raxReg) { 9672 // rdx:rax = op1 * op2 9673 movq(raxReg, op2); 9674 mulq(op1); 9675 9676 // rdx:rax = sum + carry + rdx:rax 9677 addq(sum, carry); 9678 adcq(rdxReg, 0); 9679 addq(sum, raxReg); 9680 adcq(rdxReg, 0); 9681 9682 // carry:sum = rdx:sum 9683 movq(carry, rdxReg); 9684 } 9685 9686 /** 9687 * Add 64 bit long carry into z[] with carry propogation. 9688 * Preserves z and carry register values and modifies rest of registers. 9689 * 9690 */ 9691 void MacroAssembler::add_one_64(Register z, Register zlen, Register carry, Register tmp1) { 9692 Label L_fourth_loop, L_fourth_loop_exit; 9693 9694 movl(tmp1, 1); 9695 subl(zlen, 2); 9696 addq(Address(z, zlen, Address::times_4, 0), carry); 9697 9698 bind(L_fourth_loop); 9699 jccb(Assembler::carryClear, L_fourth_loop_exit); 9700 subl(zlen, 2); 9701 jccb(Assembler::negative, L_fourth_loop_exit); 9702 addq(Address(z, zlen, Address::times_4, 0), tmp1); 9703 jmp(L_fourth_loop); 9704 bind(L_fourth_loop_exit); 9705 } 9706 9707 /** 9708 * Shift z[] left by 1 bit. 9709 * Preserves x, len, z and zlen registers and modifies rest of the registers. 9710 * 9711 */ 9712 void MacroAssembler::lshift_by_1(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4) { 9713 9714 Label L_fifth_loop, L_fifth_loop_exit; 9715 9716 // Fifth loop 9717 // Perform primitiveLeftShift(z, zlen, 1) 9718 9719 const Register prev_carry = tmp1; 9720 const Register new_carry = tmp4; 9721 const Register value = tmp2; 9722 const Register zidx = tmp3; 9723 9724 // int zidx, carry; 9725 // long value; 9726 // carry = 0; 9727 // for (zidx = zlen-2; zidx >=0; zidx -= 2) { 9728 // (carry:value) = (z[i] << 1) | carry ; 9729 // z[i] = value; 9730 // } 9731 9732 movl(zidx, zlen); 9733 xorl(prev_carry, prev_carry); // clear carry flag and prev_carry register 9734 9735 bind(L_fifth_loop); 9736 decl(zidx); // Use decl to preserve carry flag 9737 decl(zidx); 9738 jccb(Assembler::negative, L_fifth_loop_exit); 9739 9740 if (UseBMI2Instructions) { 9741 movq(value, Address(z, zidx, Address::times_4, 0)); 9742 rclq(value, 1); 9743 rorxq(value, value, 32); 9744 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9745 } 9746 else { 9747 // clear new_carry 9748 xorl(new_carry, new_carry); 9749 9750 // Shift z[i] by 1, or in previous carry and save new carry 9751 movq(value, Address(z, zidx, Address::times_4, 0)); 9752 shlq(value, 1); 9753 adcl(new_carry, 0); 9754 9755 orq(value, prev_carry); 9756 rorq(value, 0x20); 9757 movq(Address(z, zidx, Address::times_4, 0), value); // Store back in big endian form 9758 9759 // Set previous carry = new carry 9760 movl(prev_carry, new_carry); 9761 } 9762 jmp(L_fifth_loop); 9763 9764 bind(L_fifth_loop_exit); 9765 } 9766 9767 9768 /** 9769 * Code for BigInteger::squareToLen() intrinsic 9770 * 9771 * rdi: x 9772 * rsi: len 9773 * r8: z 9774 * rcx: zlen 9775 * r12: tmp1 9776 * r13: tmp2 9777 * r14: tmp3 9778 * r15: tmp4 9779 * rbx: tmp5 9780 * 9781 */ 9782 void MacroAssembler::square_to_len(Register x, Register len, Register z, Register zlen, Register tmp1, Register tmp2, Register tmp3, Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9783 9784 Label L_second_loop, L_second_loop_exit, L_third_loop, L_third_loop_exit, fifth_loop, fifth_loop_exit, L_last_x, L_multiply; 9785 push(tmp1); 9786 push(tmp2); 9787 push(tmp3); 9788 push(tmp4); 9789 push(tmp5); 9790 9791 // First loop 9792 // Store the squares, right shifted one bit (i.e., divided by 2). 9793 square_rshift(x, len, z, tmp1, tmp3, tmp4, tmp5, rdxReg, raxReg); 9794 9795 // Add in off-diagonal sums. 9796 // 9797 // Second, third (nested) and fourth loops. 9798 // zlen +=2; 9799 // for (int xidx=len-2,zidx=zlen-4; xidx > 0; xidx-=2,zidx-=4) { 9800 // carry = 0; 9801 // long op2 = x[xidx:xidx+1]; 9802 // for (int j=xidx-2,k=zidx; j >= 0; j-=2) { 9803 // k -= 2; 9804 // long op1 = x[j:j+1]; 9805 // long sum = z[k:k+1]; 9806 // carry:sum = multiply_add_64(sum, op1, op2, carry, tmp_regs); 9807 // z[k:k+1] = sum; 9808 // } 9809 // add_one_64(z, k, carry, tmp_regs); 9810 // } 9811 9812 const Register carry = tmp5; 9813 const Register sum = tmp3; 9814 const Register op1 = tmp4; 9815 Register op2 = tmp2; 9816 9817 push(zlen); 9818 push(len); 9819 addl(zlen,2); 9820 bind(L_second_loop); 9821 xorq(carry, carry); 9822 subl(zlen, 4); 9823 subl(len, 2); 9824 push(zlen); 9825 push(len); 9826 cmpl(len, 0); 9827 jccb(Assembler::lessEqual, L_second_loop_exit); 9828 9829 // Multiply an array by one 64 bit long. 9830 if (UseBMI2Instructions) { 9831 op2 = rdxReg; 9832 movq(op2, Address(x, len, Address::times_4, 0)); 9833 rorxq(op2, op2, 32); 9834 } 9835 else { 9836 movq(op2, Address(x, len, Address::times_4, 0)); 9837 rorq(op2, 32); 9838 } 9839 9840 bind(L_third_loop); 9841 decrementl(len); 9842 jccb(Assembler::negative, L_third_loop_exit); 9843 decrementl(len); 9844 jccb(Assembler::negative, L_last_x); 9845 9846 movq(op1, Address(x, len, Address::times_4, 0)); 9847 rorq(op1, 32); 9848 9849 bind(L_multiply); 9850 subl(zlen, 2); 9851 movq(sum, Address(z, zlen, Address::times_4, 0)); 9852 9853 // Multiply 64 bit by 64 bit and add 64 bits lower half and upper 64 bits as carry. 9854 if (UseBMI2Instructions) { 9855 multiply_add_64_bmi2(sum, op1, op2, carry, tmp2); 9856 } 9857 else { 9858 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9859 } 9860 9861 movq(Address(z, zlen, Address::times_4, 0), sum); 9862 9863 jmp(L_third_loop); 9864 bind(L_third_loop_exit); 9865 9866 // Fourth loop 9867 // Add 64 bit long carry into z with carry propogation. 9868 // Uses offsetted zlen. 9869 add_one_64(z, zlen, carry, tmp1); 9870 9871 pop(len); 9872 pop(zlen); 9873 jmp(L_second_loop); 9874 9875 // Next infrequent code is moved outside loops. 9876 bind(L_last_x); 9877 movl(op1, Address(x, 0)); 9878 jmp(L_multiply); 9879 9880 bind(L_second_loop_exit); 9881 pop(len); 9882 pop(zlen); 9883 pop(len); 9884 pop(zlen); 9885 9886 // Fifth loop 9887 // Shift z left 1 bit. 9888 lshift_by_1(x, len, z, zlen, tmp1, tmp2, tmp3, tmp4); 9889 9890 // z[zlen-1] |= x[len-1] & 1; 9891 movl(tmp3, Address(x, len, Address::times_4, -4)); 9892 andl(tmp3, 1); 9893 orl(Address(z, zlen, Address::times_4, -4), tmp3); 9894 9895 pop(tmp5); 9896 pop(tmp4); 9897 pop(tmp3); 9898 pop(tmp2); 9899 pop(tmp1); 9900 } 9901 9902 /** 9903 * Helper function for mul_add() 9904 * Multiply the in[] by int k and add to out[] starting at offset offs using 9905 * 128 bit by 32 bit multiply and return the carry in tmp5. 9906 * Only quad int aligned length of in[] is operated on in this function. 9907 * k is in rdxReg for BMI2Instructions, for others it is in tmp2. 9908 * This function preserves out, in and k registers. 9909 * len and offset point to the appropriate index in "in" & "out" correspondingly 9910 * tmp5 has the carry. 9911 * other registers are temporary and are modified. 9912 * 9913 */ 9914 void MacroAssembler::mul_add_128_x_32_loop(Register out, Register in, 9915 Register offset, Register len, Register tmp1, Register tmp2, Register tmp3, 9916 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9917 9918 Label L_first_loop, L_first_loop_exit; 9919 9920 movl(tmp1, len); 9921 shrl(tmp1, 2); 9922 9923 bind(L_first_loop); 9924 subl(tmp1, 1); 9925 jccb(Assembler::negative, L_first_loop_exit); 9926 9927 subl(len, 4); 9928 subl(offset, 4); 9929 9930 Register op2 = tmp2; 9931 const Register sum = tmp3; 9932 const Register op1 = tmp4; 9933 const Register carry = tmp5; 9934 9935 if (UseBMI2Instructions) { 9936 op2 = rdxReg; 9937 } 9938 9939 movq(op1, Address(in, len, Address::times_4, 8)); 9940 rorq(op1, 32); 9941 movq(sum, Address(out, offset, Address::times_4, 8)); 9942 rorq(sum, 32); 9943 if (UseBMI2Instructions) { 9944 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9945 } 9946 else { 9947 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9948 } 9949 // Store back in big endian from little endian 9950 rorq(sum, 0x20); 9951 movq(Address(out, offset, Address::times_4, 8), sum); 9952 9953 movq(op1, Address(in, len, Address::times_4, 0)); 9954 rorq(op1, 32); 9955 movq(sum, Address(out, offset, Address::times_4, 0)); 9956 rorq(sum, 32); 9957 if (UseBMI2Instructions) { 9958 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 9959 } 9960 else { 9961 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 9962 } 9963 // Store back in big endian from little endian 9964 rorq(sum, 0x20); 9965 movq(Address(out, offset, Address::times_4, 0), sum); 9966 9967 jmp(L_first_loop); 9968 bind(L_first_loop_exit); 9969 } 9970 9971 /** 9972 * Code for BigInteger::mulAdd() intrinsic 9973 * 9974 * rdi: out 9975 * rsi: in 9976 * r11: offs (out.length - offset) 9977 * rcx: len 9978 * r8: k 9979 * r12: tmp1 9980 * r13: tmp2 9981 * r14: tmp3 9982 * r15: tmp4 9983 * rbx: tmp5 9984 * Multiply the in[] by word k and add to out[], return the carry in rax 9985 */ 9986 void MacroAssembler::mul_add(Register out, Register in, Register offs, 9987 Register len, Register k, Register tmp1, Register tmp2, Register tmp3, 9988 Register tmp4, Register tmp5, Register rdxReg, Register raxReg) { 9989 9990 Label L_carry, L_last_in, L_done; 9991 9992 // carry = 0; 9993 // for (int j=len-1; j >= 0; j--) { 9994 // long product = (in[j] & LONG_MASK) * kLong + 9995 // (out[offs] & LONG_MASK) + carry; 9996 // out[offs--] = (int)product; 9997 // carry = product >>> 32; 9998 // } 9999 // 10000 push(tmp1); 10001 push(tmp2); 10002 push(tmp3); 10003 push(tmp4); 10004 push(tmp5); 10005 10006 Register op2 = tmp2; 10007 const Register sum = tmp3; 10008 const Register op1 = tmp4; 10009 const Register carry = tmp5; 10010 10011 if (UseBMI2Instructions) { 10012 op2 = rdxReg; 10013 movl(op2, k); 10014 } 10015 else { 10016 movl(op2, k); 10017 } 10018 10019 xorq(carry, carry); 10020 10021 //First loop 10022 10023 //Multiply in[] by k in a 4 way unrolled loop using 128 bit by 32 bit multiply 10024 //The carry is in tmp5 10025 mul_add_128_x_32_loop(out, in, offs, len, tmp1, tmp2, tmp3, tmp4, tmp5, rdxReg, raxReg); 10026 10027 //Multiply the trailing in[] entry using 64 bit by 32 bit, if any 10028 decrementl(len); 10029 jccb(Assembler::negative, L_carry); 10030 decrementl(len); 10031 jccb(Assembler::negative, L_last_in); 10032 10033 movq(op1, Address(in, len, Address::times_4, 0)); 10034 rorq(op1, 32); 10035 10036 subl(offs, 2); 10037 movq(sum, Address(out, offs, Address::times_4, 0)); 10038 rorq(sum, 32); 10039 10040 if (UseBMI2Instructions) { 10041 multiply_add_64_bmi2(sum, op1, op2, carry, raxReg); 10042 } 10043 else { 10044 multiply_add_64(sum, op1, op2, carry, rdxReg, raxReg); 10045 } 10046 10047 // Store back in big endian from little endian 10048 rorq(sum, 0x20); 10049 movq(Address(out, offs, Address::times_4, 0), sum); 10050 10051 testl(len, len); 10052 jccb(Assembler::zero, L_carry); 10053 10054 //Multiply the last in[] entry, if any 10055 bind(L_last_in); 10056 movl(op1, Address(in, 0)); 10057 movl(sum, Address(out, offs, Address::times_4, -4)); 10058 10059 movl(raxReg, k); 10060 mull(op1); //tmp4 * eax -> edx:eax 10061 addl(sum, carry); 10062 adcl(rdxReg, 0); 10063 addl(sum, raxReg); 10064 adcl(rdxReg, 0); 10065 movl(carry, rdxReg); 10066 10067 movl(Address(out, offs, Address::times_4, -4), sum); 10068 10069 bind(L_carry); 10070 //return tmp5/carry as carry in rax 10071 movl(rax, carry); 10072 10073 bind(L_done); 10074 pop(tmp5); 10075 pop(tmp4); 10076 pop(tmp3); 10077 pop(tmp2); 10078 pop(tmp1); 10079 } 10080 #endif 10081 10082 /** 10083 * Emits code to update CRC-32 with a byte value according to constants in table 10084 * 10085 * @param [in,out]crc Register containing the crc. 10086 * @param [in]val Register containing the byte to fold into the CRC. 10087 * @param [in]table Register containing the table of crc constants. 10088 * 10089 * uint32_t crc; 10090 * val = crc_table[(val ^ crc) & 0xFF]; 10091 * crc = val ^ (crc >> 8); 10092 * 10093 */ 10094 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) { 10095 xorl(val, crc); 10096 andl(val, 0xFF); 10097 shrl(crc, 8); // unsigned shift 10098 xorl(crc, Address(table, val, Address::times_4, 0)); 10099 } 10100 10101 /** 10102 * Fold 128-bit data chunk 10103 */ 10104 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, Register buf, int offset) { 10105 if (UseAVX > 0) { 10106 vpclmulhdq(xtmp, xK, xcrc); // [123:64] 10107 vpclmulldq(xcrc, xK, xcrc); // [63:0] 10108 vpxor(xcrc, xcrc, Address(buf, offset), 0 /* vector_len */); 10109 pxor(xcrc, xtmp); 10110 } else { 10111 movdqa(xtmp, xcrc); 10112 pclmulhdq(xtmp, xK); // [123:64] 10113 pclmulldq(xcrc, xK); // [63:0] 10114 pxor(xcrc, xtmp); 10115 movdqu(xtmp, Address(buf, offset)); 10116 pxor(xcrc, xtmp); 10117 } 10118 } 10119 10120 void MacroAssembler::fold_128bit_crc32(XMMRegister xcrc, XMMRegister xK, XMMRegister xtmp, XMMRegister xbuf) { 10121 if (UseAVX > 0) { 10122 vpclmulhdq(xtmp, xK, xcrc); 10123 vpclmulldq(xcrc, xK, xcrc); 10124 pxor(xcrc, xbuf); 10125 pxor(xcrc, xtmp); 10126 } else { 10127 movdqa(xtmp, xcrc); 10128 pclmulhdq(xtmp, xK); 10129 pclmulldq(xcrc, xK); 10130 pxor(xcrc, xbuf); 10131 pxor(xcrc, xtmp); 10132 } 10133 } 10134 10135 /** 10136 * 8-bit folds to compute 32-bit CRC 10137 * 10138 * uint64_t xcrc; 10139 * timesXtoThe32[xcrc & 0xFF] ^ (xcrc >> 8); 10140 */ 10141 void MacroAssembler::fold_8bit_crc32(XMMRegister xcrc, Register table, XMMRegister xtmp, Register tmp) { 10142 movdl(tmp, xcrc); 10143 andl(tmp, 0xFF); 10144 movdl(xtmp, Address(table, tmp, Address::times_4, 0)); 10145 psrldq(xcrc, 1); // unsigned shift one byte 10146 pxor(xcrc, xtmp); 10147 } 10148 10149 /** 10150 * uint32_t crc; 10151 * timesXtoThe32[crc & 0xFF] ^ (crc >> 8); 10152 */ 10153 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) { 10154 movl(tmp, crc); 10155 andl(tmp, 0xFF); 10156 shrl(crc, 8); 10157 xorl(crc, Address(table, tmp, Address::times_4, 0)); 10158 } 10159 10160 /** 10161 * @param crc register containing existing CRC (32-bit) 10162 * @param buf register pointing to input byte buffer (byte*) 10163 * @param len register containing number of bytes 10164 * @param table register that will contain address of CRC table 10165 * @param tmp scratch register 10166 */ 10167 void MacroAssembler::kernel_crc32(Register crc, Register buf, Register len, Register table, Register tmp) { 10168 assert_different_registers(crc, buf, len, table, tmp, rax); 10169 10170 Label L_tail, L_tail_restore, L_tail_loop, L_exit, L_align_loop, L_aligned; 10171 Label L_fold_tail, L_fold_128b, L_fold_512b, L_fold_512b_loop, L_fold_tail_loop; 10172 10173 // For EVEX with VL and BW, provide a standard mask, VL = 128 will guide the merge 10174 // context for the registers used, where all instructions below are using 128-bit mode 10175 // On EVEX without VL and BW, these instructions will all be AVX. 10176 if (VM_Version::supports_avx512vlbw()) { 10177 movl(tmp, 0xffff); 10178 kmovwl(k1, tmp); 10179 } 10180 10181 lea(table, ExternalAddress(StubRoutines::crc_table_addr())); 10182 notl(crc); // ~crc 10183 cmpl(len, 16); 10184 jcc(Assembler::less, L_tail); 10185 10186 // Align buffer to 16 bytes 10187 movl(tmp, buf); 10188 andl(tmp, 0xF); 10189 jccb(Assembler::zero, L_aligned); 10190 subl(tmp, 16); 10191 addl(len, tmp); 10192 10193 align(4); 10194 BIND(L_align_loop); 10195 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10196 update_byte_crc32(crc, rax, table); 10197 increment(buf); 10198 incrementl(tmp); 10199 jccb(Assembler::less, L_align_loop); 10200 10201 BIND(L_aligned); 10202 movl(tmp, len); // save 10203 shrl(len, 4); 10204 jcc(Assembler::zero, L_tail_restore); 10205 10206 // Fold crc into first bytes of vector 10207 movdqa(xmm1, Address(buf, 0)); 10208 movdl(rax, xmm1); 10209 xorl(crc, rax); 10210 pinsrd(xmm1, crc, 0); 10211 addptr(buf, 16); 10212 subl(len, 4); // len > 0 10213 jcc(Assembler::less, L_fold_tail); 10214 10215 movdqa(xmm2, Address(buf, 0)); 10216 movdqa(xmm3, Address(buf, 16)); 10217 movdqa(xmm4, Address(buf, 32)); 10218 addptr(buf, 48); 10219 subl(len, 3); 10220 jcc(Assembler::lessEqual, L_fold_512b); 10221 10222 // Fold total 512 bits of polynomial on each iteration, 10223 // 128 bits per each of 4 parallel streams. 10224 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 32)); 10225 10226 align(32); 10227 BIND(L_fold_512b_loop); 10228 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10229 fold_128bit_crc32(xmm2, xmm0, xmm5, buf, 16); 10230 fold_128bit_crc32(xmm3, xmm0, xmm5, buf, 32); 10231 fold_128bit_crc32(xmm4, xmm0, xmm5, buf, 48); 10232 addptr(buf, 64); 10233 subl(len, 4); 10234 jcc(Assembler::greater, L_fold_512b_loop); 10235 10236 // Fold 512 bits to 128 bits. 10237 BIND(L_fold_512b); 10238 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10239 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm2); 10240 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm3); 10241 fold_128bit_crc32(xmm1, xmm0, xmm5, xmm4); 10242 10243 // Fold the rest of 128 bits data chunks 10244 BIND(L_fold_tail); 10245 addl(len, 3); 10246 jccb(Assembler::lessEqual, L_fold_128b); 10247 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr() + 16)); 10248 10249 BIND(L_fold_tail_loop); 10250 fold_128bit_crc32(xmm1, xmm0, xmm5, buf, 0); 10251 addptr(buf, 16); 10252 decrementl(len); 10253 jccb(Assembler::greater, L_fold_tail_loop); 10254 10255 // Fold 128 bits in xmm1 down into 32 bits in crc register. 10256 BIND(L_fold_128b); 10257 movdqu(xmm0, ExternalAddress(StubRoutines::x86::crc_by128_masks_addr())); 10258 if (UseAVX > 0) { 10259 vpclmulqdq(xmm2, xmm0, xmm1, 0x1); 10260 vpand(xmm3, xmm0, xmm2, 0 /* vector_len */); 10261 vpclmulqdq(xmm0, xmm0, xmm3, 0x1); 10262 } else { 10263 movdqa(xmm2, xmm0); 10264 pclmulqdq(xmm2, xmm1, 0x1); 10265 movdqa(xmm3, xmm0); 10266 pand(xmm3, xmm2); 10267 pclmulqdq(xmm0, xmm3, 0x1); 10268 } 10269 psrldq(xmm1, 8); 10270 psrldq(xmm2, 4); 10271 pxor(xmm0, xmm1); 10272 pxor(xmm0, xmm2); 10273 10274 // 8 8-bit folds to compute 32-bit CRC. 10275 for (int j = 0; j < 4; j++) { 10276 fold_8bit_crc32(xmm0, table, xmm1, rax); 10277 } 10278 movdl(crc, xmm0); // mov 32 bits to general register 10279 for (int j = 0; j < 4; j++) { 10280 fold_8bit_crc32(crc, table, rax); 10281 } 10282 10283 BIND(L_tail_restore); 10284 movl(len, tmp); // restore 10285 BIND(L_tail); 10286 andl(len, 0xf); 10287 jccb(Assembler::zero, L_exit); 10288 10289 // Fold the rest of bytes 10290 align(4); 10291 BIND(L_tail_loop); 10292 movsbl(rax, Address(buf, 0)); // load byte with sign extension 10293 update_byte_crc32(crc, rax, table); 10294 increment(buf); 10295 decrementl(len); 10296 jccb(Assembler::greater, L_tail_loop); 10297 10298 BIND(L_exit); 10299 notl(crc); // ~c 10300 } 10301 10302 #ifdef _LP64 10303 // S. Gueron / Information Processing Letters 112 (2012) 184 10304 // Algorithm 4: Computing carry-less multiplication using a precomputed lookup table. 10305 // Input: A 32 bit value B = [byte3, byte2, byte1, byte0]. 10306 // Output: the 64-bit carry-less product of B * CONST 10307 void MacroAssembler::crc32c_ipl_alg4(Register in, uint32_t n, 10308 Register tmp1, Register tmp2, Register tmp3) { 10309 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10310 if (n > 0) { 10311 addq(tmp3, n * 256 * 8); 10312 } 10313 // Q1 = TABLEExt[n][B & 0xFF]; 10314 movl(tmp1, in); 10315 andl(tmp1, 0x000000FF); 10316 shll(tmp1, 3); 10317 addq(tmp1, tmp3); 10318 movq(tmp1, Address(tmp1, 0)); 10319 10320 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10321 movl(tmp2, in); 10322 shrl(tmp2, 8); 10323 andl(tmp2, 0x000000FF); 10324 shll(tmp2, 3); 10325 addq(tmp2, tmp3); 10326 movq(tmp2, Address(tmp2, 0)); 10327 10328 shlq(tmp2, 8); 10329 xorq(tmp1, tmp2); 10330 10331 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10332 movl(tmp2, in); 10333 shrl(tmp2, 16); 10334 andl(tmp2, 0x000000FF); 10335 shll(tmp2, 3); 10336 addq(tmp2, tmp3); 10337 movq(tmp2, Address(tmp2, 0)); 10338 10339 shlq(tmp2, 16); 10340 xorq(tmp1, tmp2); 10341 10342 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10343 shrl(in, 24); 10344 andl(in, 0x000000FF); 10345 shll(in, 3); 10346 addq(in, tmp3); 10347 movq(in, Address(in, 0)); 10348 10349 shlq(in, 24); 10350 xorq(in, tmp1); 10351 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10352 } 10353 10354 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10355 Register in_out, 10356 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10357 XMMRegister w_xtmp2, 10358 Register tmp1, 10359 Register n_tmp2, Register n_tmp3) { 10360 if (is_pclmulqdq_supported) { 10361 movdl(w_xtmp1, in_out); // modified blindly 10362 10363 movl(tmp1, const_or_pre_comp_const_index); 10364 movdl(w_xtmp2, tmp1); 10365 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10366 10367 movdq(in_out, w_xtmp1); 10368 } else { 10369 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3); 10370 } 10371 } 10372 10373 // Recombination Alternative 2: No bit-reflections 10374 // T1 = (CRC_A * U1) << 1 10375 // T2 = (CRC_B * U2) << 1 10376 // C1 = T1 >> 32 10377 // C2 = T2 >> 32 10378 // T1 = T1 & 0xFFFFFFFF 10379 // T2 = T2 & 0xFFFFFFFF 10380 // T1 = CRC32(0, T1) 10381 // T2 = CRC32(0, T2) 10382 // C1 = C1 ^ T1 10383 // C2 = C2 ^ T2 10384 // CRC = C1 ^ C2 ^ CRC_C 10385 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10386 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10387 Register tmp1, Register tmp2, 10388 Register n_tmp3) { 10389 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10390 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10391 shlq(in_out, 1); 10392 movl(tmp1, in_out); 10393 shrq(in_out, 32); 10394 xorl(tmp2, tmp2); 10395 crc32(tmp2, tmp1, 4); 10396 xorl(in_out, tmp2); // we don't care about upper 32 bit contents here 10397 shlq(in1, 1); 10398 movl(tmp1, in1); 10399 shrq(in1, 32); 10400 xorl(tmp2, tmp2); 10401 crc32(tmp2, tmp1, 4); 10402 xorl(in1, tmp2); 10403 xorl(in_out, in1); 10404 xorl(in_out, in2); 10405 } 10406 10407 // Set N to predefined value 10408 // Subtract from a lenght of a buffer 10409 // execute in a loop: 10410 // CRC_A = 0xFFFFFFFF, CRC_B = 0, CRC_C = 0 10411 // for i = 1 to N do 10412 // CRC_A = CRC32(CRC_A, A[i]) 10413 // CRC_B = CRC32(CRC_B, B[i]) 10414 // CRC_C = CRC32(CRC_C, C[i]) 10415 // end for 10416 // Recombine 10417 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10418 Register in_out1, Register in_out2, Register in_out3, 10419 Register tmp1, Register tmp2, Register tmp3, 10420 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10421 Register tmp4, Register tmp5, 10422 Register n_tmp6) { 10423 Label L_processPartitions; 10424 Label L_processPartition; 10425 Label L_exit; 10426 10427 bind(L_processPartitions); 10428 cmpl(in_out1, 3 * size); 10429 jcc(Assembler::less, L_exit); 10430 xorl(tmp1, tmp1); 10431 xorl(tmp2, tmp2); 10432 movq(tmp3, in_out2); 10433 addq(tmp3, size); 10434 10435 bind(L_processPartition); 10436 crc32(in_out3, Address(in_out2, 0), 8); 10437 crc32(tmp1, Address(in_out2, size), 8); 10438 crc32(tmp2, Address(in_out2, size * 2), 8); 10439 addq(in_out2, 8); 10440 cmpq(in_out2, tmp3); 10441 jcc(Assembler::less, L_processPartition); 10442 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10443 w_xtmp1, w_xtmp2, w_xtmp3, 10444 tmp4, tmp5, 10445 n_tmp6); 10446 addq(in_out2, 2 * size); 10447 subl(in_out1, 3 * size); 10448 jmp(L_processPartitions); 10449 10450 bind(L_exit); 10451 } 10452 #else 10453 void MacroAssembler::crc32c_ipl_alg4(Register in_out, uint32_t n, 10454 Register tmp1, Register tmp2, Register tmp3, 10455 XMMRegister xtmp1, XMMRegister xtmp2) { 10456 lea(tmp3, ExternalAddress(StubRoutines::crc32c_table_addr())); 10457 if (n > 0) { 10458 addl(tmp3, n * 256 * 8); 10459 } 10460 // Q1 = TABLEExt[n][B & 0xFF]; 10461 movl(tmp1, in_out); 10462 andl(tmp1, 0x000000FF); 10463 shll(tmp1, 3); 10464 addl(tmp1, tmp3); 10465 movq(xtmp1, Address(tmp1, 0)); 10466 10467 // Q2 = TABLEExt[n][B >> 8 & 0xFF]; 10468 movl(tmp2, in_out); 10469 shrl(tmp2, 8); 10470 andl(tmp2, 0x000000FF); 10471 shll(tmp2, 3); 10472 addl(tmp2, tmp3); 10473 movq(xtmp2, Address(tmp2, 0)); 10474 10475 psllq(xtmp2, 8); 10476 pxor(xtmp1, xtmp2); 10477 10478 // Q3 = TABLEExt[n][B >> 16 & 0xFF]; 10479 movl(tmp2, in_out); 10480 shrl(tmp2, 16); 10481 andl(tmp2, 0x000000FF); 10482 shll(tmp2, 3); 10483 addl(tmp2, tmp3); 10484 movq(xtmp2, Address(tmp2, 0)); 10485 10486 psllq(xtmp2, 16); 10487 pxor(xtmp1, xtmp2); 10488 10489 // Q4 = TABLEExt[n][B >> 24 & 0xFF]; 10490 shrl(in_out, 24); 10491 andl(in_out, 0x000000FF); 10492 shll(in_out, 3); 10493 addl(in_out, tmp3); 10494 movq(xtmp2, Address(in_out, 0)); 10495 10496 psllq(xtmp2, 24); 10497 pxor(xtmp1, xtmp2); // Result in CXMM 10498 // return Q1 ^ Q2 << 8 ^ Q3 << 16 ^ Q4 << 24; 10499 } 10500 10501 void MacroAssembler::crc32c_pclmulqdq(XMMRegister w_xtmp1, 10502 Register in_out, 10503 uint32_t const_or_pre_comp_const_index, bool is_pclmulqdq_supported, 10504 XMMRegister w_xtmp2, 10505 Register tmp1, 10506 Register n_tmp2, Register n_tmp3) { 10507 if (is_pclmulqdq_supported) { 10508 movdl(w_xtmp1, in_out); 10509 10510 movl(tmp1, const_or_pre_comp_const_index); 10511 movdl(w_xtmp2, tmp1); 10512 pclmulqdq(w_xtmp1, w_xtmp2, 0); 10513 // Keep result in XMM since GPR is 32 bit in length 10514 } else { 10515 crc32c_ipl_alg4(in_out, const_or_pre_comp_const_index, tmp1, n_tmp2, n_tmp3, w_xtmp1, w_xtmp2); 10516 } 10517 } 10518 10519 void MacroAssembler::crc32c_rec_alt2(uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, Register in_out, Register in1, Register in2, 10520 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10521 Register tmp1, Register tmp2, 10522 Register n_tmp3) { 10523 crc32c_pclmulqdq(w_xtmp1, in_out, const_or_pre_comp_const_index_u1, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10524 crc32c_pclmulqdq(w_xtmp2, in1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, w_xtmp3, tmp1, tmp2, n_tmp3); 10525 10526 psllq(w_xtmp1, 1); 10527 movdl(tmp1, w_xtmp1); 10528 psrlq(w_xtmp1, 32); 10529 movdl(in_out, w_xtmp1); 10530 10531 xorl(tmp2, tmp2); 10532 crc32(tmp2, tmp1, 4); 10533 xorl(in_out, tmp2); 10534 10535 psllq(w_xtmp2, 1); 10536 movdl(tmp1, w_xtmp2); 10537 psrlq(w_xtmp2, 32); 10538 movdl(in1, w_xtmp2); 10539 10540 xorl(tmp2, tmp2); 10541 crc32(tmp2, tmp1, 4); 10542 xorl(in1, tmp2); 10543 xorl(in_out, in1); 10544 xorl(in_out, in2); 10545 } 10546 10547 void MacroAssembler::crc32c_proc_chunk(uint32_t size, uint32_t const_or_pre_comp_const_index_u1, uint32_t const_or_pre_comp_const_index_u2, bool is_pclmulqdq_supported, 10548 Register in_out1, Register in_out2, Register in_out3, 10549 Register tmp1, Register tmp2, Register tmp3, 10550 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10551 Register tmp4, Register tmp5, 10552 Register n_tmp6) { 10553 Label L_processPartitions; 10554 Label L_processPartition; 10555 Label L_exit; 10556 10557 bind(L_processPartitions); 10558 cmpl(in_out1, 3 * size); 10559 jcc(Assembler::less, L_exit); 10560 xorl(tmp1, tmp1); 10561 xorl(tmp2, tmp2); 10562 movl(tmp3, in_out2); 10563 addl(tmp3, size); 10564 10565 bind(L_processPartition); 10566 crc32(in_out3, Address(in_out2, 0), 4); 10567 crc32(tmp1, Address(in_out2, size), 4); 10568 crc32(tmp2, Address(in_out2, size*2), 4); 10569 crc32(in_out3, Address(in_out2, 0+4), 4); 10570 crc32(tmp1, Address(in_out2, size+4), 4); 10571 crc32(tmp2, Address(in_out2, size*2+4), 4); 10572 addl(in_out2, 8); 10573 cmpl(in_out2, tmp3); 10574 jcc(Assembler::less, L_processPartition); 10575 10576 push(tmp3); 10577 push(in_out1); 10578 push(in_out2); 10579 tmp4 = tmp3; 10580 tmp5 = in_out1; 10581 n_tmp6 = in_out2; 10582 10583 crc32c_rec_alt2(const_or_pre_comp_const_index_u1, const_or_pre_comp_const_index_u2, is_pclmulqdq_supported, in_out3, tmp1, tmp2, 10584 w_xtmp1, w_xtmp2, w_xtmp3, 10585 tmp4, tmp5, 10586 n_tmp6); 10587 10588 pop(in_out2); 10589 pop(in_out1); 10590 pop(tmp3); 10591 10592 addl(in_out2, 2 * size); 10593 subl(in_out1, 3 * size); 10594 jmp(L_processPartitions); 10595 10596 bind(L_exit); 10597 } 10598 #endif //LP64 10599 10600 #ifdef _LP64 10601 // Algorithm 2: Pipelined usage of the CRC32 instruction. 10602 // Input: A buffer I of L bytes. 10603 // Output: the CRC32C value of the buffer. 10604 // Notations: 10605 // Write L = 24N + r, with N = floor (L/24). 10606 // r = L mod 24 (0 <= r < 24). 10607 // Consider I as the concatenation of A|B|C|R, where A, B, C, each, 10608 // N quadwords, and R consists of r bytes. 10609 // A[j] = I [8j+7:8j], j= 0, 1, ..., N-1 10610 // B[j] = I [N + 8j+7:N + 8j], j= 0, 1, ..., N-1 10611 // C[j] = I [2N + 8j+7:2N + 8j], j= 0, 1, ..., N-1 10612 // if r > 0 R[j] = I [3N +j], j= 0, 1, ...,r-1 10613 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10614 Register tmp1, Register tmp2, Register tmp3, 10615 Register tmp4, Register tmp5, Register tmp6, 10616 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10617 bool is_pclmulqdq_supported) { 10618 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10619 Label L_wordByWord; 10620 Label L_byteByByteProlog; 10621 Label L_byteByByte; 10622 Label L_exit; 10623 10624 if (is_pclmulqdq_supported ) { 10625 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10626 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr+1); 10627 10628 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10629 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10630 10631 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10632 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10633 assert((CRC32C_NUM_PRECOMPUTED_CONSTANTS - 1 ) == 5, "Checking whether you declared all of the constants based on the number of \"chunks\""); 10634 } else { 10635 const_or_pre_comp_const_index[0] = 1; 10636 const_or_pre_comp_const_index[1] = 0; 10637 10638 const_or_pre_comp_const_index[2] = 3; 10639 const_or_pre_comp_const_index[3] = 2; 10640 10641 const_or_pre_comp_const_index[4] = 5; 10642 const_or_pre_comp_const_index[5] = 4; 10643 } 10644 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10645 in2, in1, in_out, 10646 tmp1, tmp2, tmp3, 10647 w_xtmp1, w_xtmp2, w_xtmp3, 10648 tmp4, tmp5, 10649 tmp6); 10650 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10651 in2, in1, in_out, 10652 tmp1, tmp2, tmp3, 10653 w_xtmp1, w_xtmp2, w_xtmp3, 10654 tmp4, tmp5, 10655 tmp6); 10656 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10657 in2, in1, in_out, 10658 tmp1, tmp2, tmp3, 10659 w_xtmp1, w_xtmp2, w_xtmp3, 10660 tmp4, tmp5, 10661 tmp6); 10662 movl(tmp1, in2); 10663 andl(tmp1, 0x00000007); 10664 negl(tmp1); 10665 addl(tmp1, in2); 10666 addq(tmp1, in1); 10667 10668 BIND(L_wordByWord); 10669 cmpq(in1, tmp1); 10670 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10671 crc32(in_out, Address(in1, 0), 4); 10672 addq(in1, 4); 10673 jmp(L_wordByWord); 10674 10675 BIND(L_byteByByteProlog); 10676 andl(in2, 0x00000007); 10677 movl(tmp2, 1); 10678 10679 BIND(L_byteByByte); 10680 cmpl(tmp2, in2); 10681 jccb(Assembler::greater, L_exit); 10682 crc32(in_out, Address(in1, 0), 1); 10683 incq(in1); 10684 incl(tmp2); 10685 jmp(L_byteByByte); 10686 10687 BIND(L_exit); 10688 } 10689 #else 10690 void MacroAssembler::crc32c_ipl_alg2_alt2(Register in_out, Register in1, Register in2, 10691 Register tmp1, Register tmp2, Register tmp3, 10692 Register tmp4, Register tmp5, Register tmp6, 10693 XMMRegister w_xtmp1, XMMRegister w_xtmp2, XMMRegister w_xtmp3, 10694 bool is_pclmulqdq_supported) { 10695 uint32_t const_or_pre_comp_const_index[CRC32C_NUM_PRECOMPUTED_CONSTANTS]; 10696 Label L_wordByWord; 10697 Label L_byteByByteProlog; 10698 Label L_byteByByte; 10699 Label L_exit; 10700 10701 if (is_pclmulqdq_supported) { 10702 const_or_pre_comp_const_index[1] = *(uint32_t *)StubRoutines::_crc32c_table_addr; 10703 const_or_pre_comp_const_index[0] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 1); 10704 10705 const_or_pre_comp_const_index[3] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 2); 10706 const_or_pre_comp_const_index[2] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 3); 10707 10708 const_or_pre_comp_const_index[5] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 4); 10709 const_or_pre_comp_const_index[4] = *((uint32_t *)StubRoutines::_crc32c_table_addr + 5); 10710 } else { 10711 const_or_pre_comp_const_index[0] = 1; 10712 const_or_pre_comp_const_index[1] = 0; 10713 10714 const_or_pre_comp_const_index[2] = 3; 10715 const_or_pre_comp_const_index[3] = 2; 10716 10717 const_or_pre_comp_const_index[4] = 5; 10718 const_or_pre_comp_const_index[5] = 4; 10719 } 10720 crc32c_proc_chunk(CRC32C_HIGH, const_or_pre_comp_const_index[0], const_or_pre_comp_const_index[1], is_pclmulqdq_supported, 10721 in2, in1, in_out, 10722 tmp1, tmp2, tmp3, 10723 w_xtmp1, w_xtmp2, w_xtmp3, 10724 tmp4, tmp5, 10725 tmp6); 10726 crc32c_proc_chunk(CRC32C_MIDDLE, const_or_pre_comp_const_index[2], const_or_pre_comp_const_index[3], is_pclmulqdq_supported, 10727 in2, in1, in_out, 10728 tmp1, tmp2, tmp3, 10729 w_xtmp1, w_xtmp2, w_xtmp3, 10730 tmp4, tmp5, 10731 tmp6); 10732 crc32c_proc_chunk(CRC32C_LOW, const_or_pre_comp_const_index[4], const_or_pre_comp_const_index[5], is_pclmulqdq_supported, 10733 in2, in1, in_out, 10734 tmp1, tmp2, tmp3, 10735 w_xtmp1, w_xtmp2, w_xtmp3, 10736 tmp4, tmp5, 10737 tmp6); 10738 movl(tmp1, in2); 10739 andl(tmp1, 0x00000007); 10740 negl(tmp1); 10741 addl(tmp1, in2); 10742 addl(tmp1, in1); 10743 10744 BIND(L_wordByWord); 10745 cmpl(in1, tmp1); 10746 jcc(Assembler::greaterEqual, L_byteByByteProlog); 10747 crc32(in_out, Address(in1,0), 4); 10748 addl(in1, 4); 10749 jmp(L_wordByWord); 10750 10751 BIND(L_byteByByteProlog); 10752 andl(in2, 0x00000007); 10753 movl(tmp2, 1); 10754 10755 BIND(L_byteByByte); 10756 cmpl(tmp2, in2); 10757 jccb(Assembler::greater, L_exit); 10758 movb(tmp1, Address(in1, 0)); 10759 crc32(in_out, tmp1, 1); 10760 incl(in1); 10761 incl(tmp2); 10762 jmp(L_byteByByte); 10763 10764 BIND(L_exit); 10765 } 10766 #endif // LP64 10767 #undef BIND 10768 #undef BLOCK_COMMENT 10769 10770 10771 // Compress char[] array to byte[]. 10772 void MacroAssembler::char_array_compress(Register src, Register dst, Register len, 10773 XMMRegister tmp1Reg, XMMRegister tmp2Reg, 10774 XMMRegister tmp3Reg, XMMRegister tmp4Reg, 10775 Register tmp5, Register result) { 10776 Label copy_chars_loop, return_length, return_zero, done; 10777 10778 // rsi: src 10779 // rdi: dst 10780 // rdx: len 10781 // rcx: tmp5 10782 // rax: result 10783 10784 // rsi holds start addr of source char[] to be compressed 10785 // rdi holds start addr of destination byte[] 10786 // rdx holds length 10787 10788 assert(len != result, ""); 10789 10790 // save length for return 10791 push(len); 10792 10793 if (UseSSE42Intrinsics) { 10794 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 10795 Label copy_32_loop, copy_16, copy_tail; 10796 10797 movl(result, len); 10798 movl(tmp5, 0xff00ff00); // create mask to test for Unicode chars in vectors 10799 10800 // vectored compression 10801 andl(len, 0xfffffff0); // vector count (in chars) 10802 andl(result, 0x0000000f); // tail count (in chars) 10803 testl(len, len); 10804 jccb(Assembler::zero, copy_16); 10805 10806 // compress 16 chars per iter 10807 movdl(tmp1Reg, tmp5); 10808 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 10809 pxor(tmp4Reg, tmp4Reg); 10810 10811 lea(src, Address(src, len, Address::times_2)); 10812 lea(dst, Address(dst, len, Address::times_1)); 10813 negptr(len); 10814 10815 bind(copy_32_loop); 10816 movdqu(tmp2Reg, Address(src, len, Address::times_2)); // load 1st 8 characters 10817 por(tmp4Reg, tmp2Reg); 10818 movdqu(tmp3Reg, Address(src, len, Address::times_2, 16)); // load next 8 characters 10819 por(tmp4Reg, tmp3Reg); 10820 ptest(tmp4Reg, tmp1Reg); // check for Unicode chars in next vector 10821 jcc(Assembler::notZero, return_zero); 10822 packuswb(tmp2Reg, tmp3Reg); // only ASCII chars; compress each to 1 byte 10823 movdqu(Address(dst, len, Address::times_1), tmp2Reg); 10824 addptr(len, 16); 10825 jcc(Assembler::notZero, copy_32_loop); 10826 10827 // compress next vector of 8 chars (if any) 10828 bind(copy_16); 10829 movl(len, result); 10830 andl(len, 0xfffffff8); // vector count (in chars) 10831 andl(result, 0x00000007); // tail count (in chars) 10832 testl(len, len); 10833 jccb(Assembler::zero, copy_tail); 10834 10835 movdl(tmp1Reg, tmp5); 10836 pshufd(tmp1Reg, tmp1Reg, 0); // store Unicode mask in tmp1Reg 10837 pxor(tmp3Reg, tmp3Reg); 10838 10839 movdqu(tmp2Reg, Address(src, 0)); 10840 ptest(tmp2Reg, tmp1Reg); // check for Unicode chars in vector 10841 jccb(Assembler::notZero, return_zero); 10842 packuswb(tmp2Reg, tmp3Reg); // only LATIN1 chars; compress each to 1 byte 10843 movq(Address(dst, 0), tmp2Reg); 10844 addptr(src, 16); 10845 addptr(dst, 8); 10846 10847 bind(copy_tail); 10848 movl(len, result); 10849 } 10850 // compress 1 char per iter 10851 testl(len, len); 10852 jccb(Assembler::zero, return_length); 10853 lea(src, Address(src, len, Address::times_2)); 10854 lea(dst, Address(dst, len, Address::times_1)); 10855 negptr(len); 10856 10857 bind(copy_chars_loop); 10858 load_unsigned_short(result, Address(src, len, Address::times_2)); 10859 testl(result, 0xff00); // check if Unicode char 10860 jccb(Assembler::notZero, return_zero); 10861 movb(Address(dst, len, Address::times_1), result); // ASCII char; compress to 1 byte 10862 increment(len); 10863 jcc(Assembler::notZero, copy_chars_loop); 10864 10865 // if compression succeeded, return length 10866 bind(return_length); 10867 pop(result); 10868 jmpb(done); 10869 10870 // if compression failed, return 0 10871 bind(return_zero); 10872 xorl(result, result); 10873 addptr(rsp, wordSize); 10874 10875 bind(done); 10876 } 10877 10878 // Inflate byte[] array to char[]. 10879 void MacroAssembler::byte_array_inflate(Register src, Register dst, Register len, 10880 XMMRegister tmp1, Register tmp2) { 10881 Label copy_chars_loop, done; 10882 10883 // rsi: src 10884 // rdi: dst 10885 // rdx: len 10886 // rcx: tmp2 10887 10888 // rsi holds start addr of source byte[] to be inflated 10889 // rdi holds start addr of destination char[] 10890 // rdx holds length 10891 assert_different_registers(src, dst, len, tmp2); 10892 10893 if (UseSSE42Intrinsics) { 10894 assert(UseSSE >= 4, "SSE4 must be enabled for SSE4.2 intrinsics to be available"); 10895 Label copy_8_loop, copy_bytes, copy_tail; 10896 10897 movl(tmp2, len); 10898 andl(tmp2, 0x00000007); // tail count (in chars) 10899 andl(len, 0xfffffff8); // vector count (in chars) 10900 jccb(Assembler::zero, copy_tail); 10901 10902 // vectored inflation 10903 lea(src, Address(src, len, Address::times_1)); 10904 lea(dst, Address(dst, len, Address::times_2)); 10905 negptr(len); 10906 10907 // inflate 8 chars per iter 10908 bind(copy_8_loop); 10909 pmovzxbw(tmp1, Address(src, len, Address::times_1)); // unpack to 8 words 10910 movdqu(Address(dst, len, Address::times_2), tmp1); 10911 addptr(len, 8); 10912 jcc(Assembler::notZero, copy_8_loop); 10913 10914 bind(copy_tail); 10915 movl(len, tmp2); 10916 10917 cmpl(len, 4); 10918 jccb(Assembler::less, copy_bytes); 10919 10920 movdl(tmp1, Address(src, 0)); // load 4 byte chars 10921 pmovzxbw(tmp1, tmp1); 10922 movq(Address(dst, 0), tmp1); 10923 subptr(len, 4); 10924 addptr(src, 4); 10925 addptr(dst, 8); 10926 10927 bind(copy_bytes); 10928 } 10929 testl(len, len); 10930 jccb(Assembler::zero, done); 10931 lea(src, Address(src, len, Address::times_1)); 10932 lea(dst, Address(dst, len, Address::times_2)); 10933 negptr(len); 10934 10935 // inflate 1 char per iter 10936 bind(copy_chars_loop); 10937 load_unsigned_byte(tmp2, Address(src, len, Address::times_1)); // load byte char 10938 movw(Address(dst, len, Address::times_2), tmp2); // inflate byte char to word 10939 increment(len); 10940 jcc(Assembler::notZero, copy_chars_loop); 10941 10942 bind(done); 10943 } 10944 10945 10946 Assembler::Condition MacroAssembler::negate_condition(Assembler::Condition cond) { 10947 switch (cond) { 10948 // Note some conditions are synonyms for others 10949 case Assembler::zero: return Assembler::notZero; 10950 case Assembler::notZero: return Assembler::zero; 10951 case Assembler::less: return Assembler::greaterEqual; 10952 case Assembler::lessEqual: return Assembler::greater; 10953 case Assembler::greater: return Assembler::lessEqual; 10954 case Assembler::greaterEqual: return Assembler::less; 10955 case Assembler::below: return Assembler::aboveEqual; 10956 case Assembler::belowEqual: return Assembler::above; 10957 case Assembler::above: return Assembler::belowEqual; 10958 case Assembler::aboveEqual: return Assembler::below; 10959 case Assembler::overflow: return Assembler::noOverflow; 10960 case Assembler::noOverflow: return Assembler::overflow; 10961 case Assembler::negative: return Assembler::positive; 10962 case Assembler::positive: return Assembler::negative; 10963 case Assembler::parity: return Assembler::noParity; 10964 case Assembler::noParity: return Assembler::parity; 10965 } 10966 ShouldNotReachHere(); return Assembler::overflow; 10967 } 10968 10969 SkipIfEqual::SkipIfEqual( 10970 MacroAssembler* masm, const bool* flag_addr, bool value) { 10971 _masm = masm; 10972 _masm->cmp8(ExternalAddress((address)flag_addr), value); 10973 _masm->jcc(Assembler::equal, _label); 10974 } 10975 10976 SkipIfEqual::~SkipIfEqual() { 10977 _masm->bind(_label); 10978 } 10979 10980 // 32-bit Windows has its own fast-path implementation 10981 // of get_thread 10982 #if !defined(WIN32) || defined(_LP64) 10983 10984 // This is simply a call to Thread::current() 10985 void MacroAssembler::get_thread(Register thread) { 10986 if (thread != rax) { 10987 push(rax); 10988 } 10989 LP64_ONLY(push(rdi);) 10990 LP64_ONLY(push(rsi);) 10991 push(rdx); 10992 push(rcx); 10993 #ifdef _LP64 10994 push(r8); 10995 push(r9); 10996 push(r10); 10997 push(r11); 10998 #endif 10999 11000 MacroAssembler::call_VM_leaf_base(CAST_FROM_FN_PTR(address, Thread::current), 0); 11001 11002 #ifdef _LP64 11003 pop(r11); 11004 pop(r10); 11005 pop(r9); 11006 pop(r8); 11007 #endif 11008 pop(rcx); 11009 pop(rdx); 11010 LP64_ONLY(pop(rsi);) 11011 LP64_ONLY(pop(rdi);) 11012 if (thread != rax) { 11013 mov(thread, rax); 11014 pop(rax); 11015 } 11016 } 11017 11018 #endif