1 // 2 // Copyright (c) 2011, 2016, Oracle and/or its affiliates. All rights reserved. 3 // Copyright (c) 2012, 2016 SAP SE. All rights reserved. 4 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 5 // 6 // This code is free software; you can redistribute it and/or modify it 7 // under the terms of the GNU General Public License version 2 only, as 8 // published by the Free Software Foundation. 9 // 10 // This code is distributed in the hope that it will be useful, but WITHOUT 11 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 12 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 13 // version 2 for more details (a copy is included in the LICENSE file that 14 // accompanied this code). 15 // 16 // You should have received a copy of the GNU General Public License version 17 // 2 along with this work; if not, write to the Free Software Foundation, 18 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 19 // 20 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 21 // or visit www.oracle.com if you need additional information or have any 22 // questions. 23 // 24 // 25 26 // 27 // PPC64 Architecture Description File 28 // 29 30 //----------REGISTER DEFINITION BLOCK------------------------------------------ 31 // This information is used by the matcher and the register allocator to 32 // describe individual registers and classes of registers within the target 33 // architecture. 34 register %{ 35 //----------Architecture Description Register Definitions---------------------- 36 // General Registers 37 // "reg_def" name (register save type, C convention save type, 38 // ideal register type, encoding); 39 // 40 // Register Save Types: 41 // 42 // NS = No-Save: The register allocator assumes that these registers 43 // can be used without saving upon entry to the method, & 44 // that they do not need to be saved at call sites. 45 // 46 // SOC = Save-On-Call: The register allocator assumes that these registers 47 // can be used without saving upon entry to the method, 48 // but that they must be saved at call sites. 49 // These are called "volatiles" on ppc. 50 // 51 // SOE = Save-On-Entry: The register allocator assumes that these registers 52 // must be saved before using them upon entry to the 53 // method, but they do not need to be saved at call 54 // sites. 55 // These are called "nonvolatiles" on ppc. 56 // 57 // AS = Always-Save: The register allocator assumes that these registers 58 // must be saved before using them upon entry to the 59 // method, & that they must be saved at call sites. 60 // 61 // Ideal Register Type is used to determine how to save & restore a 62 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get 63 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI. 64 // 65 // The encoding number is the actual bit-pattern placed into the opcodes. 66 // 67 // PPC64 register definitions, based on the 64-bit PowerPC ELF ABI 68 // Supplement Version 1.7 as of 2003-10-29. 69 // 70 // For each 64-bit register we must define two registers: the register 71 // itself, e.g. R3, and a corresponding virtual other (32-bit-)'half', 72 // e.g. R3_H, which is needed by the allocator, but is not used 73 // for stores, loads, etc. 74 75 // ---------------------------- 76 // Integer/Long Registers 77 // ---------------------------- 78 79 // PPC64 has 32 64-bit integer registers. 80 81 // types: v = volatile, nv = non-volatile, s = system 82 reg_def R0 ( SOC, SOC, Op_RegI, 0, R0->as_VMReg() ); // v used in prologs 83 reg_def R0_H ( SOC, SOC, Op_RegI, 99, R0->as_VMReg()->next() ); 84 reg_def R1 ( NS, NS, Op_RegI, 1, R1->as_VMReg() ); // s SP 85 reg_def R1_H ( NS, NS, Op_RegI, 99, R1->as_VMReg()->next() ); 86 reg_def R2 ( SOC, SOC, Op_RegI, 2, R2->as_VMReg() ); // v TOC 87 reg_def R2_H ( SOC, SOC, Op_RegI, 99, R2->as_VMReg()->next() ); 88 reg_def R3 ( SOC, SOC, Op_RegI, 3, R3->as_VMReg() ); // v iarg1 & iret 89 reg_def R3_H ( SOC, SOC, Op_RegI, 99, R3->as_VMReg()->next() ); 90 reg_def R4 ( SOC, SOC, Op_RegI, 4, R4->as_VMReg() ); // iarg2 91 reg_def R4_H ( SOC, SOC, Op_RegI, 99, R4->as_VMReg()->next() ); 92 reg_def R5 ( SOC, SOC, Op_RegI, 5, R5->as_VMReg() ); // v iarg3 93 reg_def R5_H ( SOC, SOC, Op_RegI, 99, R5->as_VMReg()->next() ); 94 reg_def R6 ( SOC, SOC, Op_RegI, 6, R6->as_VMReg() ); // v iarg4 95 reg_def R6_H ( SOC, SOC, Op_RegI, 99, R6->as_VMReg()->next() ); 96 reg_def R7 ( SOC, SOC, Op_RegI, 7, R7->as_VMReg() ); // v iarg5 97 reg_def R7_H ( SOC, SOC, Op_RegI, 99, R7->as_VMReg()->next() ); 98 reg_def R8 ( SOC, SOC, Op_RegI, 8, R8->as_VMReg() ); // v iarg6 99 reg_def R8_H ( SOC, SOC, Op_RegI, 99, R8->as_VMReg()->next() ); 100 reg_def R9 ( SOC, SOC, Op_RegI, 9, R9->as_VMReg() ); // v iarg7 101 reg_def R9_H ( SOC, SOC, Op_RegI, 99, R9->as_VMReg()->next() ); 102 reg_def R10 ( SOC, SOC, Op_RegI, 10, R10->as_VMReg() ); // v iarg8 103 reg_def R10_H( SOC, SOC, Op_RegI, 99, R10->as_VMReg()->next()); 104 reg_def R11 ( SOC, SOC, Op_RegI, 11, R11->as_VMReg() ); // v ENV / scratch 105 reg_def R11_H( SOC, SOC, Op_RegI, 99, R11->as_VMReg()->next()); 106 reg_def R12 ( SOC, SOC, Op_RegI, 12, R12->as_VMReg() ); // v scratch 107 reg_def R12_H( SOC, SOC, Op_RegI, 99, R12->as_VMReg()->next()); 108 reg_def R13 ( NS, NS, Op_RegI, 13, R13->as_VMReg() ); // s system thread id 109 reg_def R13_H( NS, NS, Op_RegI, 99, R13->as_VMReg()->next()); 110 reg_def R14 ( SOC, SOE, Op_RegI, 14, R14->as_VMReg() ); // nv 111 reg_def R14_H( SOC, SOE, Op_RegI, 99, R14->as_VMReg()->next()); 112 reg_def R15 ( SOC, SOE, Op_RegI, 15, R15->as_VMReg() ); // nv 113 reg_def R15_H( SOC, SOE, Op_RegI, 99, R15->as_VMReg()->next()); 114 reg_def R16 ( SOC, SOE, Op_RegI, 16, R16->as_VMReg() ); // nv 115 reg_def R16_H( SOC, SOE, Op_RegI, 99, R16->as_VMReg()->next()); 116 reg_def R17 ( SOC, SOE, Op_RegI, 17, R17->as_VMReg() ); // nv 117 reg_def R17_H( SOC, SOE, Op_RegI, 99, R17->as_VMReg()->next()); 118 reg_def R18 ( SOC, SOE, Op_RegI, 18, R18->as_VMReg() ); // nv 119 reg_def R18_H( SOC, SOE, Op_RegI, 99, R18->as_VMReg()->next()); 120 reg_def R19 ( SOC, SOE, Op_RegI, 19, R19->as_VMReg() ); // nv 121 reg_def R19_H( SOC, SOE, Op_RegI, 99, R19->as_VMReg()->next()); 122 reg_def R20 ( SOC, SOE, Op_RegI, 20, R20->as_VMReg() ); // nv 123 reg_def R20_H( SOC, SOE, Op_RegI, 99, R20->as_VMReg()->next()); 124 reg_def R21 ( SOC, SOE, Op_RegI, 21, R21->as_VMReg() ); // nv 125 reg_def R21_H( SOC, SOE, Op_RegI, 99, R21->as_VMReg()->next()); 126 reg_def R22 ( SOC, SOE, Op_RegI, 22, R22->as_VMReg() ); // nv 127 reg_def R22_H( SOC, SOE, Op_RegI, 99, R22->as_VMReg()->next()); 128 reg_def R23 ( SOC, SOE, Op_RegI, 23, R23->as_VMReg() ); // nv 129 reg_def R23_H( SOC, SOE, Op_RegI, 99, R23->as_VMReg()->next()); 130 reg_def R24 ( SOC, SOE, Op_RegI, 24, R24->as_VMReg() ); // nv 131 reg_def R24_H( SOC, SOE, Op_RegI, 99, R24->as_VMReg()->next()); 132 reg_def R25 ( SOC, SOE, Op_RegI, 25, R25->as_VMReg() ); // nv 133 reg_def R25_H( SOC, SOE, Op_RegI, 99, R25->as_VMReg()->next()); 134 reg_def R26 ( SOC, SOE, Op_RegI, 26, R26->as_VMReg() ); // nv 135 reg_def R26_H( SOC, SOE, Op_RegI, 99, R26->as_VMReg()->next()); 136 reg_def R27 ( SOC, SOE, Op_RegI, 27, R27->as_VMReg() ); // nv 137 reg_def R27_H( SOC, SOE, Op_RegI, 99, R27->as_VMReg()->next()); 138 reg_def R28 ( SOC, SOE, Op_RegI, 28, R28->as_VMReg() ); // nv 139 reg_def R28_H( SOC, SOE, Op_RegI, 99, R28->as_VMReg()->next()); 140 reg_def R29 ( SOC, SOE, Op_RegI, 29, R29->as_VMReg() ); // nv 141 reg_def R29_H( SOC, SOE, Op_RegI, 99, R29->as_VMReg()->next()); 142 reg_def R30 ( SOC, SOE, Op_RegI, 30, R30->as_VMReg() ); // nv 143 reg_def R30_H( SOC, SOE, Op_RegI, 99, R30->as_VMReg()->next()); 144 reg_def R31 ( SOC, SOE, Op_RegI, 31, R31->as_VMReg() ); // nv 145 reg_def R31_H( SOC, SOE, Op_RegI, 99, R31->as_VMReg()->next()); 146 147 148 // ---------------------------- 149 // Float/Double Registers 150 // ---------------------------- 151 152 // Double Registers 153 // The rules of ADL require that double registers be defined in pairs. 154 // Each pair must be two 32-bit values, but not necessarily a pair of 155 // single float registers. In each pair, ADLC-assigned register numbers 156 // must be adjacent, with the lower number even. Finally, when the 157 // CPU stores such a register pair to memory, the word associated with 158 // the lower ADLC-assigned number must be stored to the lower address. 159 160 // PPC64 has 32 64-bit floating-point registers. Each can store a single 161 // or double precision floating-point value. 162 163 // types: v = volatile, nv = non-volatile, s = system 164 reg_def F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg() ); // v scratch 165 reg_def F0_H ( SOC, SOC, Op_RegF, 99, F0->as_VMReg()->next() ); 166 reg_def F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg() ); // v farg1 & fret 167 reg_def F1_H ( SOC, SOC, Op_RegF, 99, F1->as_VMReg()->next() ); 168 reg_def F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg() ); // v farg2 169 reg_def F2_H ( SOC, SOC, Op_RegF, 99, F2->as_VMReg()->next() ); 170 reg_def F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg() ); // v farg3 171 reg_def F3_H ( SOC, SOC, Op_RegF, 99, F3->as_VMReg()->next() ); 172 reg_def F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg() ); // v farg4 173 reg_def F4_H ( SOC, SOC, Op_RegF, 99, F4->as_VMReg()->next() ); 174 reg_def F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg() ); // v farg5 175 reg_def F5_H ( SOC, SOC, Op_RegF, 99, F5->as_VMReg()->next() ); 176 reg_def F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg() ); // v farg6 177 reg_def F6_H ( SOC, SOC, Op_RegF, 99, F6->as_VMReg()->next() ); 178 reg_def F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg() ); // v farg7 179 reg_def F7_H ( SOC, SOC, Op_RegF, 99, F7->as_VMReg()->next() ); 180 reg_def F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg() ); // v farg8 181 reg_def F8_H ( SOC, SOC, Op_RegF, 99, F8->as_VMReg()->next() ); 182 reg_def F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg() ); // v farg9 183 reg_def F9_H ( SOC, SOC, Op_RegF, 99, F9->as_VMReg()->next() ); 184 reg_def F10 ( SOC, SOC, Op_RegF, 10, F10->as_VMReg() ); // v farg10 185 reg_def F10_H( SOC, SOC, Op_RegF, 99, F10->as_VMReg()->next()); 186 reg_def F11 ( SOC, SOC, Op_RegF, 11, F11->as_VMReg() ); // v farg11 187 reg_def F11_H( SOC, SOC, Op_RegF, 99, F11->as_VMReg()->next()); 188 reg_def F12 ( SOC, SOC, Op_RegF, 12, F12->as_VMReg() ); // v farg12 189 reg_def F12_H( SOC, SOC, Op_RegF, 99, F12->as_VMReg()->next()); 190 reg_def F13 ( SOC, SOC, Op_RegF, 13, F13->as_VMReg() ); // v farg13 191 reg_def F13_H( SOC, SOC, Op_RegF, 99, F13->as_VMReg()->next()); 192 reg_def F14 ( SOC, SOE, Op_RegF, 14, F14->as_VMReg() ); // nv 193 reg_def F14_H( SOC, SOE, Op_RegF, 99, F14->as_VMReg()->next()); 194 reg_def F15 ( SOC, SOE, Op_RegF, 15, F15->as_VMReg() ); // nv 195 reg_def F15_H( SOC, SOE, Op_RegF, 99, F15->as_VMReg()->next()); 196 reg_def F16 ( SOC, SOE, Op_RegF, 16, F16->as_VMReg() ); // nv 197 reg_def F16_H( SOC, SOE, Op_RegF, 99, F16->as_VMReg()->next()); 198 reg_def F17 ( SOC, SOE, Op_RegF, 17, F17->as_VMReg() ); // nv 199 reg_def F17_H( SOC, SOE, Op_RegF, 99, F17->as_VMReg()->next()); 200 reg_def F18 ( SOC, SOE, Op_RegF, 18, F18->as_VMReg() ); // nv 201 reg_def F18_H( SOC, SOE, Op_RegF, 99, F18->as_VMReg()->next()); 202 reg_def F19 ( SOC, SOE, Op_RegF, 19, F19->as_VMReg() ); // nv 203 reg_def F19_H( SOC, SOE, Op_RegF, 99, F19->as_VMReg()->next()); 204 reg_def F20 ( SOC, SOE, Op_RegF, 20, F20->as_VMReg() ); // nv 205 reg_def F20_H( SOC, SOE, Op_RegF, 99, F20->as_VMReg()->next()); 206 reg_def F21 ( SOC, SOE, Op_RegF, 21, F21->as_VMReg() ); // nv 207 reg_def F21_H( SOC, SOE, Op_RegF, 99, F21->as_VMReg()->next()); 208 reg_def F22 ( SOC, SOE, Op_RegF, 22, F22->as_VMReg() ); // nv 209 reg_def F22_H( SOC, SOE, Op_RegF, 99, F22->as_VMReg()->next()); 210 reg_def F23 ( SOC, SOE, Op_RegF, 23, F23->as_VMReg() ); // nv 211 reg_def F23_H( SOC, SOE, Op_RegF, 99, F23->as_VMReg()->next()); 212 reg_def F24 ( SOC, SOE, Op_RegF, 24, F24->as_VMReg() ); // nv 213 reg_def F24_H( SOC, SOE, Op_RegF, 99, F24->as_VMReg()->next()); 214 reg_def F25 ( SOC, SOE, Op_RegF, 25, F25->as_VMReg() ); // nv 215 reg_def F25_H( SOC, SOE, Op_RegF, 99, F25->as_VMReg()->next()); 216 reg_def F26 ( SOC, SOE, Op_RegF, 26, F26->as_VMReg() ); // nv 217 reg_def F26_H( SOC, SOE, Op_RegF, 99, F26->as_VMReg()->next()); 218 reg_def F27 ( SOC, SOE, Op_RegF, 27, F27->as_VMReg() ); // nv 219 reg_def F27_H( SOC, SOE, Op_RegF, 99, F27->as_VMReg()->next()); 220 reg_def F28 ( SOC, SOE, Op_RegF, 28, F28->as_VMReg() ); // nv 221 reg_def F28_H( SOC, SOE, Op_RegF, 99, F28->as_VMReg()->next()); 222 reg_def F29 ( SOC, SOE, Op_RegF, 29, F29->as_VMReg() ); // nv 223 reg_def F29_H( SOC, SOE, Op_RegF, 99, F29->as_VMReg()->next()); 224 reg_def F30 ( SOC, SOE, Op_RegF, 30, F30->as_VMReg() ); // nv 225 reg_def F30_H( SOC, SOE, Op_RegF, 99, F30->as_VMReg()->next()); 226 reg_def F31 ( SOC, SOE, Op_RegF, 31, F31->as_VMReg() ); // nv 227 reg_def F31_H( SOC, SOE, Op_RegF, 99, F31->as_VMReg()->next()); 228 229 // ---------------------------- 230 // Special Registers 231 // ---------------------------- 232 233 // Condition Codes Flag Registers 234 235 // PPC64 has 8 condition code "registers" which are all contained 236 // in the CR register. 237 238 // types: v = volatile, nv = non-volatile, s = system 239 reg_def CCR0(SOC, SOC, Op_RegFlags, 0, CCR0->as_VMReg()); // v 240 reg_def CCR1(SOC, SOC, Op_RegFlags, 1, CCR1->as_VMReg()); // v 241 reg_def CCR2(SOC, SOC, Op_RegFlags, 2, CCR2->as_VMReg()); // nv 242 reg_def CCR3(SOC, SOC, Op_RegFlags, 3, CCR3->as_VMReg()); // nv 243 reg_def CCR4(SOC, SOC, Op_RegFlags, 4, CCR4->as_VMReg()); // nv 244 reg_def CCR5(SOC, SOC, Op_RegFlags, 5, CCR5->as_VMReg()); // v 245 reg_def CCR6(SOC, SOC, Op_RegFlags, 6, CCR6->as_VMReg()); // v 246 reg_def CCR7(SOC, SOC, Op_RegFlags, 7, CCR7->as_VMReg()); // v 247 248 // Special registers of PPC64 249 250 reg_def SR_XER( SOC, SOC, Op_RegP, 0, SR_XER->as_VMReg()); // v 251 reg_def SR_LR( SOC, SOC, Op_RegP, 1, SR_LR->as_VMReg()); // v 252 reg_def SR_CTR( SOC, SOC, Op_RegP, 2, SR_CTR->as_VMReg()); // v 253 reg_def SR_VRSAVE( SOC, SOC, Op_RegP, 3, SR_VRSAVE->as_VMReg()); // v 254 reg_def SR_SPEFSCR(SOC, SOC, Op_RegP, 4, SR_SPEFSCR->as_VMReg()); // v 255 reg_def SR_PPR( SOC, SOC, Op_RegP, 5, SR_PPR->as_VMReg()); // v 256 257 258 // ---------------------------- 259 // Specify priority of register selection within phases of register 260 // allocation. Highest priority is first. A useful heuristic is to 261 // give registers a low priority when they are required by machine 262 // instructions, like EAX and EDX on I486, and choose no-save registers 263 // before save-on-call, & save-on-call before save-on-entry. Registers 264 // which participate in fixed calling sequences should come last. 265 // Registers which are used as pairs must fall on an even boundary. 266 267 // It's worth about 1% on SPEC geomean to get this right. 268 269 // Chunk0, chunk1, and chunk2 form the MachRegisterNumbers enumeration 270 // in adGlobals_ppc.hpp which defines the <register>_num values, e.g. 271 // R3_num. Therefore, R3_num may not be (and in reality is not) 272 // the same as R3->encoding()! Furthermore, we cannot make any 273 // assumptions on ordering, e.g. R3_num may be less than R2_num. 274 // Additionally, the function 275 // static enum RC rc_class(OptoReg::Name reg ) 276 // maps a given <register>_num value to its chunk type (except for flags) 277 // and its current implementation relies on chunk0 and chunk1 having a 278 // size of 64 each. 279 280 // If you change this allocation class, please have a look at the 281 // default values for the parameters RoundRobinIntegerRegIntervalStart 282 // and RoundRobinFloatRegIntervalStart 283 284 alloc_class chunk0 ( 285 // Chunk0 contains *all* 64 integer registers halves. 286 287 // "non-volatile" registers 288 R14, R14_H, 289 R15, R15_H, 290 R17, R17_H, 291 R18, R18_H, 292 R19, R19_H, 293 R20, R20_H, 294 R21, R21_H, 295 R22, R22_H, 296 R23, R23_H, 297 R24, R24_H, 298 R25, R25_H, 299 R26, R26_H, 300 R27, R27_H, 301 R28, R28_H, 302 R29, R29_H, 303 R30, R30_H, 304 R31, R31_H, 305 306 // scratch/special registers 307 R11, R11_H, 308 R12, R12_H, 309 310 // argument registers 311 R10, R10_H, 312 R9, R9_H, 313 R8, R8_H, 314 R7, R7_H, 315 R6, R6_H, 316 R5, R5_H, 317 R4, R4_H, 318 R3, R3_H, 319 320 // special registers, not available for allocation 321 R16, R16_H, // R16_thread 322 R13, R13_H, // system thread id 323 R2, R2_H, // may be used for TOC 324 R1, R1_H, // SP 325 R0, R0_H // R0 (scratch) 326 ); 327 328 // If you change this allocation class, please have a look at the 329 // default values for the parameters RoundRobinIntegerRegIntervalStart 330 // and RoundRobinFloatRegIntervalStart 331 332 alloc_class chunk1 ( 333 // Chunk1 contains *all* 64 floating-point registers halves. 334 335 // scratch register 336 F0, F0_H, 337 338 // argument registers 339 F13, F13_H, 340 F12, F12_H, 341 F11, F11_H, 342 F10, F10_H, 343 F9, F9_H, 344 F8, F8_H, 345 F7, F7_H, 346 F6, F6_H, 347 F5, F5_H, 348 F4, F4_H, 349 F3, F3_H, 350 F2, F2_H, 351 F1, F1_H, 352 353 // non-volatile registers 354 F14, F14_H, 355 F15, F15_H, 356 F16, F16_H, 357 F17, F17_H, 358 F18, F18_H, 359 F19, F19_H, 360 F20, F20_H, 361 F21, F21_H, 362 F22, F22_H, 363 F23, F23_H, 364 F24, F24_H, 365 F25, F25_H, 366 F26, F26_H, 367 F27, F27_H, 368 F28, F28_H, 369 F29, F29_H, 370 F30, F30_H, 371 F31, F31_H 372 ); 373 374 alloc_class chunk2 ( 375 // Chunk2 contains *all* 8 condition code registers. 376 377 CCR0, 378 CCR1, 379 CCR2, 380 CCR3, 381 CCR4, 382 CCR5, 383 CCR6, 384 CCR7 385 ); 386 387 alloc_class chunk3 ( 388 // special registers 389 // These registers are not allocated, but used for nodes generated by postalloc expand. 390 SR_XER, 391 SR_LR, 392 SR_CTR, 393 SR_VRSAVE, 394 SR_SPEFSCR, 395 SR_PPR 396 ); 397 398 //-------Architecture Description Register Classes----------------------- 399 400 // Several register classes are automatically defined based upon 401 // information in this architecture description. 402 403 // 1) reg_class inline_cache_reg ( as defined in frame section ) 404 // 2) reg_class compiler_method_oop_reg ( as defined in frame section ) 405 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section ) 406 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ ) 407 // 408 409 // ---------------------------- 410 // 32 Bit Register Classes 411 // ---------------------------- 412 413 // We specify registers twice, once as read/write, and once read-only. 414 // We use the read-only registers for source operands. With this, we 415 // can include preset read only registers in this class, as a hard-coded 416 // '0'-register. (We used to simulate this on ppc.) 417 418 // 32 bit registers that can be read and written i.e. these registers 419 // can be dest (or src) of normal instructions. 420 reg_class bits32_reg_rw( 421 /*R0*/ // R0 422 /*R1*/ // SP 423 R2, // TOC 424 R3, 425 R4, 426 R5, 427 R6, 428 R7, 429 R8, 430 R9, 431 R10, 432 R11, 433 R12, 434 /*R13*/ // system thread id 435 R14, 436 R15, 437 /*R16*/ // R16_thread 438 R17, 439 R18, 440 R19, 441 R20, 442 R21, 443 R22, 444 R23, 445 R24, 446 R25, 447 R26, 448 R27, 449 R28, 450 /*R29,*/ // global TOC 451 R30, 452 R31 453 ); 454 455 // 32 bit registers that can only be read i.e. these registers can 456 // only be src of all instructions. 457 reg_class bits32_reg_ro( 458 /*R0*/ // R0 459 /*R1*/ // SP 460 R2 // TOC 461 R3, 462 R4, 463 R5, 464 R6, 465 R7, 466 R8, 467 R9, 468 R10, 469 R11, 470 R12, 471 /*R13*/ // system thread id 472 R14, 473 R15, 474 /*R16*/ // R16_thread 475 R17, 476 R18, 477 R19, 478 R20, 479 R21, 480 R22, 481 R23, 482 R24, 483 R25, 484 R26, 485 R27, 486 R28, 487 /*R29,*/ 488 R30, 489 R31 490 ); 491 492 reg_class rscratch1_bits32_reg(R11); 493 reg_class rscratch2_bits32_reg(R12); 494 reg_class rarg1_bits32_reg(R3); 495 reg_class rarg2_bits32_reg(R4); 496 reg_class rarg3_bits32_reg(R5); 497 reg_class rarg4_bits32_reg(R6); 498 499 // ---------------------------- 500 // 64 Bit Register Classes 501 // ---------------------------- 502 // 64-bit build means 64-bit pointers means hi/lo pairs 503 504 reg_class rscratch1_bits64_reg(R11_H, R11); 505 reg_class rscratch2_bits64_reg(R12_H, R12); 506 reg_class rarg1_bits64_reg(R3_H, R3); 507 reg_class rarg2_bits64_reg(R4_H, R4); 508 reg_class rarg3_bits64_reg(R5_H, R5); 509 reg_class rarg4_bits64_reg(R6_H, R6); 510 // Thread register, 'written' by tlsLoadP, see there. 511 reg_class thread_bits64_reg(R16_H, R16); 512 513 reg_class r19_bits64_reg(R19_H, R19); 514 515 // 64 bit registers that can be read and written i.e. these registers 516 // can be dest (or src) of normal instructions. 517 reg_class bits64_reg_rw( 518 /*R0_H, R0*/ // R0 519 /*R1_H, R1*/ // SP 520 R2_H, R2, // TOC 521 R3_H, R3, 522 R4_H, R4, 523 R5_H, R5, 524 R6_H, R6, 525 R7_H, R7, 526 R8_H, R8, 527 R9_H, R9, 528 R10_H, R10, 529 R11_H, R11, 530 R12_H, R12, 531 /*R13_H, R13*/ // system thread id 532 R14_H, R14, 533 R15_H, R15, 534 /*R16_H, R16*/ // R16_thread 535 R17_H, R17, 536 R18_H, R18, 537 R19_H, R19, 538 R20_H, R20, 539 R21_H, R21, 540 R22_H, R22, 541 R23_H, R23, 542 R24_H, R24, 543 R25_H, R25, 544 R26_H, R26, 545 R27_H, R27, 546 R28_H, R28, 547 /*R29_H, R29,*/ 548 R30_H, R30, 549 R31_H, R31 550 ); 551 552 // 64 bit registers used excluding r2, r11 and r12 553 // Used to hold the TOC to avoid collisions with expanded LeafCall which uses 554 // r2, r11 and r12 internally. 555 reg_class bits64_reg_leaf_call( 556 /*R0_H, R0*/ // R0 557 /*R1_H, R1*/ // SP 558 /*R2_H, R2*/ // TOC 559 R3_H, R3, 560 R4_H, R4, 561 R5_H, R5, 562 R6_H, R6, 563 R7_H, R7, 564 R8_H, R8, 565 R9_H, R9, 566 R10_H, R10, 567 /*R11_H, R11*/ 568 /*R12_H, R12*/ 569 /*R13_H, R13*/ // system thread id 570 R14_H, R14, 571 R15_H, R15, 572 /*R16_H, R16*/ // R16_thread 573 R17_H, R17, 574 R18_H, R18, 575 R19_H, R19, 576 R20_H, R20, 577 R21_H, R21, 578 R22_H, R22, 579 R23_H, R23, 580 R24_H, R24, 581 R25_H, R25, 582 R26_H, R26, 583 R27_H, R27, 584 R28_H, R28, 585 /*R29_H, R29,*/ 586 R30_H, R30, 587 R31_H, R31 588 ); 589 590 // Used to hold the TOC to avoid collisions with expanded DynamicCall 591 // which uses r19 as inline cache internally and expanded LeafCall which uses 592 // r2, r11 and r12 internally. 593 reg_class bits64_constant_table_base( 594 /*R0_H, R0*/ // R0 595 /*R1_H, R1*/ // SP 596 /*R2_H, R2*/ // TOC 597 R3_H, R3, 598 R4_H, R4, 599 R5_H, R5, 600 R6_H, R6, 601 R7_H, R7, 602 R8_H, R8, 603 R9_H, R9, 604 R10_H, R10, 605 /*R11_H, R11*/ 606 /*R12_H, R12*/ 607 /*R13_H, R13*/ // system thread id 608 R14_H, R14, 609 R15_H, R15, 610 /*R16_H, R16*/ // R16_thread 611 R17_H, R17, 612 R18_H, R18, 613 /*R19_H, R19*/ 614 R20_H, R20, 615 R21_H, R21, 616 R22_H, R22, 617 R23_H, R23, 618 R24_H, R24, 619 R25_H, R25, 620 R26_H, R26, 621 R27_H, R27, 622 R28_H, R28, 623 /*R29_H, R29,*/ 624 R30_H, R30, 625 R31_H, R31 626 ); 627 628 // 64 bit registers that can only be read i.e. these registers can 629 // only be src of all instructions. 630 reg_class bits64_reg_ro( 631 /*R0_H, R0*/ // R0 632 R1_H, R1, 633 R2_H, R2, // TOC 634 R3_H, R3, 635 R4_H, R4, 636 R5_H, R5, 637 R6_H, R6, 638 R7_H, R7, 639 R8_H, R8, 640 R9_H, R9, 641 R10_H, R10, 642 R11_H, R11, 643 R12_H, R12, 644 /*R13_H, R13*/ // system thread id 645 R14_H, R14, 646 R15_H, R15, 647 R16_H, R16, // R16_thread 648 R17_H, R17, 649 R18_H, R18, 650 R19_H, R19, 651 R20_H, R20, 652 R21_H, R21, 653 R22_H, R22, 654 R23_H, R23, 655 R24_H, R24, 656 R25_H, R25, 657 R26_H, R26, 658 R27_H, R27, 659 R28_H, R28, 660 /*R29_H, R29,*/ // TODO: let allocator handle TOC!! 661 R30_H, R30, 662 R31_H, R31 663 ); 664 665 666 // ---------------------------- 667 // Special Class for Condition Code Flags Register 668 669 reg_class int_flags( 670 /*CCR0*/ // scratch 671 /*CCR1*/ // scratch 672 /*CCR2*/ // nv! 673 /*CCR3*/ // nv! 674 /*CCR4*/ // nv! 675 CCR5, 676 CCR6, 677 CCR7 678 ); 679 680 reg_class int_flags_ro( 681 CCR0, 682 CCR1, 683 CCR2, 684 CCR3, 685 CCR4, 686 CCR5, 687 CCR6, 688 CCR7 689 ); 690 691 reg_class int_flags_CR0(CCR0); 692 reg_class int_flags_CR1(CCR1); 693 reg_class int_flags_CR6(CCR6); 694 reg_class ctr_reg(SR_CTR); 695 696 // ---------------------------- 697 // Float Register Classes 698 // ---------------------------- 699 700 reg_class flt_reg( 701 F0, 702 F1, 703 F2, 704 F3, 705 F4, 706 F5, 707 F6, 708 F7, 709 F8, 710 F9, 711 F10, 712 F11, 713 F12, 714 F13, 715 F14, // nv! 716 F15, // nv! 717 F16, // nv! 718 F17, // nv! 719 F18, // nv! 720 F19, // nv! 721 F20, // nv! 722 F21, // nv! 723 F22, // nv! 724 F23, // nv! 725 F24, // nv! 726 F25, // nv! 727 F26, // nv! 728 F27, // nv! 729 F28, // nv! 730 F29, // nv! 731 F30, // nv! 732 F31 // nv! 733 ); 734 735 // Double precision float registers have virtual `high halves' that 736 // are needed by the allocator. 737 reg_class dbl_reg( 738 F0, F0_H, 739 F1, F1_H, 740 F2, F2_H, 741 F3, F3_H, 742 F4, F4_H, 743 F5, F5_H, 744 F6, F6_H, 745 F7, F7_H, 746 F8, F8_H, 747 F9, F9_H, 748 F10, F10_H, 749 F11, F11_H, 750 F12, F12_H, 751 F13, F13_H, 752 F14, F14_H, // nv! 753 F15, F15_H, // nv! 754 F16, F16_H, // nv! 755 F17, F17_H, // nv! 756 F18, F18_H, // nv! 757 F19, F19_H, // nv! 758 F20, F20_H, // nv! 759 F21, F21_H, // nv! 760 F22, F22_H, // nv! 761 F23, F23_H, // nv! 762 F24, F24_H, // nv! 763 F25, F25_H, // nv! 764 F26, F26_H, // nv! 765 F27, F27_H, // nv! 766 F28, F28_H, // nv! 767 F29, F29_H, // nv! 768 F30, F30_H, // nv! 769 F31, F31_H // nv! 770 ); 771 772 %} 773 774 //----------DEFINITION BLOCK--------------------------------------------------- 775 // Define name --> value mappings to inform the ADLC of an integer valued name 776 // Current support includes integer values in the range [0, 0x7FFFFFFF] 777 // Format: 778 // int_def <name> ( <int_value>, <expression>); 779 // Generated Code in ad_<arch>.hpp 780 // #define <name> (<expression>) 781 // // value == <int_value> 782 // Generated code in ad_<arch>.cpp adlc_verification() 783 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>"); 784 // 785 definitions %{ 786 // The default cost (of an ALU instruction). 787 int_def DEFAULT_COST_LOW ( 30, 30); 788 int_def DEFAULT_COST ( 100, 100); 789 int_def HUGE_COST (1000000, 1000000); 790 791 // Memory refs 792 int_def MEMORY_REF_COST_LOW ( 200, DEFAULT_COST * 2); 793 int_def MEMORY_REF_COST ( 300, DEFAULT_COST * 3); 794 795 // Branches are even more expensive. 796 int_def BRANCH_COST ( 900, DEFAULT_COST * 9); 797 int_def CALL_COST ( 1300, DEFAULT_COST * 13); 798 %} 799 800 801 //----------SOURCE BLOCK------------------------------------------------------- 802 // This is a block of C++ code which provides values, functions, and 803 // definitions necessary in the rest of the architecture description. 804 source_hpp %{ 805 // Header information of the source block. 806 // Method declarations/definitions which are used outside 807 // the ad-scope can conveniently be defined here. 808 // 809 // To keep related declarations/definitions/uses close together, 810 // we switch between source %{ }% and source_hpp %{ }% freely as needed. 811 812 // Returns true if Node n is followed by a MemBar node that 813 // will do an acquire. If so, this node must not do the acquire 814 // operation. 815 bool followed_by_acquire(const Node *n); 816 %} 817 818 source %{ 819 820 // Optimize load-acquire. 821 // 822 // Check if acquire is unnecessary due to following operation that does 823 // acquire anyways. 824 // Walk the pattern: 825 // 826 // n: Load.acq 827 // | 828 // MemBarAcquire 829 // | | 830 // Proj(ctrl) Proj(mem) 831 // | | 832 // MemBarRelease/Volatile 833 // 834 bool followed_by_acquire(const Node *load) { 835 assert(load->is_Load(), "So far implemented only for loads."); 836 837 // Find MemBarAcquire. 838 const Node *mba = NULL; 839 for (DUIterator_Fast imax, i = load->fast_outs(imax); i < imax; i++) { 840 const Node *out = load->fast_out(i); 841 if (out->Opcode() == Op_MemBarAcquire) { 842 if (out->in(0) == load) continue; // Skip control edge, membar should be found via precedence edge. 843 mba = out; 844 break; 845 } 846 } 847 if (!mba) return false; 848 849 // Find following MemBar node. 850 // 851 // The following node must be reachable by control AND memory 852 // edge to assure no other operations are in between the two nodes. 853 // 854 // So first get the Proj node, mem_proj, to use it to iterate forward. 855 Node *mem_proj = NULL; 856 for (DUIterator_Fast imax, i = mba->fast_outs(imax); i < imax; i++) { 857 mem_proj = mba->fast_out(i); // Throw out-of-bounds if proj not found 858 assert(mem_proj->is_Proj(), "only projections here"); 859 ProjNode *proj = mem_proj->as_Proj(); 860 if (proj->_con == TypeFunc::Memory && 861 !Compile::current()->node_arena()->contains(mem_proj)) // Unmatched old-space only 862 break; 863 } 864 assert(mem_proj->as_Proj()->_con == TypeFunc::Memory, "Graph broken"); 865 866 // Search MemBar behind Proj. If there are other memory operations 867 // behind the Proj we lost. 868 for (DUIterator_Fast jmax, j = mem_proj->fast_outs(jmax); j < jmax; j++) { 869 Node *x = mem_proj->fast_out(j); 870 // Proj might have an edge to a store or load node which precedes the membar. 871 if (x->is_Mem()) return false; 872 873 // On PPC64 release and volatile are implemented by an instruction 874 // that also has acquire semantics. I.e. there is no need for an 875 // acquire before these. 876 int xop = x->Opcode(); 877 if (xop == Op_MemBarRelease || xop == Op_MemBarVolatile) { 878 // Make sure we're not missing Call/Phi/MergeMem by checking 879 // control edges. The control edge must directly lead back 880 // to the MemBarAcquire 881 Node *ctrl_proj = x->in(0); 882 if (ctrl_proj->is_Proj() && ctrl_proj->in(0) == mba) { 883 return true; 884 } 885 } 886 } 887 888 return false; 889 } 890 891 #define __ _masm. 892 893 // Tertiary op of a LoadP or StoreP encoding. 894 #define REGP_OP true 895 896 // **************************************************************************** 897 898 // REQUIRED FUNCTIONALITY 899 900 // !!!!! Special hack to get all type of calls to specify the byte offset 901 // from the start of the call to the point where the return address 902 // will point. 903 904 // PPC port: Removed use of lazy constant construct. 905 906 int MachCallStaticJavaNode::ret_addr_offset() { 907 // It's only a single branch-and-link instruction. 908 return 4; 909 } 910 911 int MachCallDynamicJavaNode::ret_addr_offset() { 912 // Offset is 4 with postalloc expanded calls (bl is one instruction). We use 913 // postalloc expanded calls if we use inline caches and do not update method data. 914 if (UseInlineCaches) 915 return 4; 916 917 int vtable_index = this->_vtable_index; 918 if (vtable_index < 0) { 919 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 920 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 921 return 12; 922 } else { 923 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 924 return 24; 925 } 926 } 927 928 int MachCallRuntimeNode::ret_addr_offset() { 929 #if defined(ABI_ELFv2) 930 return 28; 931 #else 932 return 40; 933 #endif 934 } 935 936 //============================================================================= 937 938 // condition code conversions 939 940 static int cc_to_boint(int cc) { 941 return Assembler::bcondCRbiIs0 | (cc & 8); 942 } 943 944 static int cc_to_inverse_boint(int cc) { 945 return Assembler::bcondCRbiIs0 | (8-(cc & 8)); 946 } 947 948 static int cc_to_biint(int cc, int flags_reg) { 949 return (flags_reg << 2) | (cc & 3); 950 } 951 952 //============================================================================= 953 954 // Compute padding required for nodes which need alignment. The padding 955 // is the number of bytes (not instructions) which will be inserted before 956 // the instruction. The padding must match the size of a NOP instruction. 957 958 int string_indexOf_imm1_charNode::compute_padding(int current_offset) const { 959 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof_1 960 } 961 962 int string_indexOf_imm1Node::compute_padding(int current_offset) const { 963 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof_1 964 } 965 966 int string_indexOfCharNode::compute_padding(int current_offset) const { 967 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof_1 968 } 969 970 int string_indexOf_immNode::compute_padding(int current_offset) const { 971 return (3*4-current_offset)&31; // see MacroAssembler::string_indexof(constant needlecount) 972 } 973 974 int string_indexOfNode::compute_padding(int current_offset) const { 975 return (1*4-current_offset)&31; // see MacroAssembler::string_indexof(variable needlecount) 976 } 977 978 int string_compareNode::compute_padding(int current_offset) const { 979 return (2*4-current_offset)&31; // see MacroAssembler::string_compare 980 } 981 982 int string_equals_immNode::compute_padding(int current_offset) const { 983 if (opnd_array(3)->constant() < 16) return 0; // For strlen < 16 no nops because loop completely unrolled 984 return (2*4-current_offset)&31; // Genral case - see MacroAssembler::char_arrays_equalsImm 985 } 986 987 int string_equalsNode::compute_padding(int current_offset) const { 988 return (7*4-current_offset)&31; // see MacroAssembler::char_arrays_equals 989 } 990 991 int inlineCallClearArrayNode::compute_padding(int current_offset) const { 992 return (2*4-current_offset)&31; // see MacroAssembler::clear_memory_doubleword 993 } 994 995 //============================================================================= 996 997 // Indicate if the safepoint node needs the polling page as an input. 998 bool SafePointNode::needs_polling_address_input() { 999 // The address is loaded from thread by a seperate node. 1000 return true; 1001 } 1002 1003 //============================================================================= 1004 1005 // Emit an interrupt that is caught by the debugger (for debugging compiler). 1006 void emit_break(CodeBuffer &cbuf) { 1007 MacroAssembler _masm(&cbuf); 1008 __ illtrap(); 1009 } 1010 1011 #ifndef PRODUCT 1012 void MachBreakpointNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1013 st->print("BREAKPOINT"); 1014 } 1015 #endif 1016 1017 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1018 emit_break(cbuf); 1019 } 1020 1021 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const { 1022 return MachNode::size(ra_); 1023 } 1024 1025 //============================================================================= 1026 1027 void emit_nop(CodeBuffer &cbuf) { 1028 MacroAssembler _masm(&cbuf); 1029 __ nop(); 1030 } 1031 1032 static inline void emit_long(CodeBuffer &cbuf, int value) { 1033 *((int*)(cbuf.insts_end())) = value; 1034 cbuf.set_insts_end(cbuf.insts_end() + BytesPerInstWord); 1035 } 1036 1037 //============================================================================= 1038 1039 %} // interrupt source 1040 1041 source_hpp %{ // Header information of the source block. 1042 1043 //-------------------------------------------------------------- 1044 //---< Used for optimization in Compile::Shorten_branches >--- 1045 //-------------------------------------------------------------- 1046 1047 class CallStubImpl { 1048 1049 public: 1050 1051 // Emit call stub, compiled java to interpreter. 1052 static void emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset); 1053 1054 // Size of call trampoline stub. 1055 // This doesn't need to be accurate to the byte, but it 1056 // must be larger than or equal to the real size of the stub. 1057 static uint size_call_trampoline() { 1058 return MacroAssembler::trampoline_stub_size; 1059 } 1060 1061 // number of relocations needed by a call trampoline stub 1062 static uint reloc_call_trampoline() { 1063 return 5; 1064 } 1065 1066 }; 1067 1068 %} // end source_hpp 1069 1070 source %{ 1071 1072 // Emit a trampoline stub for a call to a target which is too far away. 1073 // 1074 // code sequences: 1075 // 1076 // call-site: 1077 // branch-and-link to <destination> or <trampoline stub> 1078 // 1079 // Related trampoline stub for this call-site in the stub section: 1080 // load the call target from the constant pool 1081 // branch via CTR (LR/link still points to the call-site above) 1082 1083 void CallStubImpl::emit_trampoline_stub(MacroAssembler &_masm, int destination_toc_offset, int insts_call_instruction_offset) { 1084 address stub = __ emit_trampoline_stub(destination_toc_offset, insts_call_instruction_offset); 1085 if (stub == NULL) { 1086 ciEnv::current()->record_out_of_memory_failure(); 1087 } 1088 } 1089 1090 //============================================================================= 1091 1092 // Emit an inline branch-and-link call and a related trampoline stub. 1093 // 1094 // code sequences: 1095 // 1096 // call-site: 1097 // branch-and-link to <destination> or <trampoline stub> 1098 // 1099 // Related trampoline stub for this call-site in the stub section: 1100 // load the call target from the constant pool 1101 // branch via CTR (LR/link still points to the call-site above) 1102 // 1103 1104 typedef struct { 1105 int insts_call_instruction_offset; 1106 int ret_addr_offset; 1107 } EmitCallOffsets; 1108 1109 // Emit a branch-and-link instruction that branches to a trampoline. 1110 // - Remember the offset of the branch-and-link instruction. 1111 // - Add a relocation at the branch-and-link instruction. 1112 // - Emit a branch-and-link. 1113 // - Remember the return pc offset. 1114 EmitCallOffsets emit_call_with_trampoline_stub(MacroAssembler &_masm, address entry_point, relocInfo::relocType rtype) { 1115 EmitCallOffsets offsets = { -1, -1 }; 1116 const int start_offset = __ offset(); 1117 offsets.insts_call_instruction_offset = __ offset(); 1118 1119 // No entry point given, use the current pc. 1120 if (entry_point == NULL) entry_point = __ pc(); 1121 1122 if (!Compile::current()->in_scratch_emit_size()) { 1123 // Put the entry point as a constant into the constant pool. 1124 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 1125 if (entry_point_toc_addr == NULL) { 1126 ciEnv::current()->record_out_of_memory_failure(); 1127 return offsets; 1128 } 1129 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 1130 1131 // Emit the trampoline stub which will be related to the branch-and-link below. 1132 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, offsets.insts_call_instruction_offset); 1133 if (ciEnv::current()->failing()) { return offsets; } // Code cache may be full. 1134 __ relocate(rtype); 1135 } 1136 1137 // Note: At this point we do not have the address of the trampoline 1138 // stub, and the entry point might be too far away for bl, so __ pc() 1139 // serves as dummy and the bl will be patched later. 1140 __ bl((address) __ pc()); 1141 1142 offsets.ret_addr_offset = __ offset() - start_offset; 1143 1144 return offsets; 1145 } 1146 1147 //============================================================================= 1148 1149 // Factory for creating loadConL* nodes for large/small constant pool. 1150 1151 static inline jlong replicate_immF(float con) { 1152 // Replicate float con 2 times and pack into vector. 1153 int val = *((int*)&con); 1154 jlong lval = val; 1155 lval = (lval << 32) | (lval & 0xFFFFFFFFl); 1156 return lval; 1157 } 1158 1159 //============================================================================= 1160 1161 const RegMask& MachConstantBaseNode::_out_RegMask = BITS64_CONSTANT_TABLE_BASE_mask(); 1162 int Compile::ConstantTable::calculate_table_base_offset() const { 1163 return 0; // absolute addressing, no offset 1164 } 1165 1166 bool MachConstantBaseNode::requires_postalloc_expand() const { return true; } 1167 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) { 1168 iRegPdstOper *op_dst = new iRegPdstOper(); 1169 MachNode *m1 = new loadToc_hiNode(); 1170 MachNode *m2 = new loadToc_loNode(); 1171 1172 m1->add_req(NULL); 1173 m2->add_req(NULL, m1); 1174 m1->_opnds[0] = op_dst; 1175 m2->_opnds[0] = op_dst; 1176 m2->_opnds[1] = op_dst; 1177 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1178 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 1179 nodes->push(m1); 1180 nodes->push(m2); 1181 } 1182 1183 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1184 // Is postalloc expanded. 1185 ShouldNotReachHere(); 1186 } 1187 1188 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const { 1189 return 0; 1190 } 1191 1192 #ifndef PRODUCT 1193 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1194 st->print("-- \t// MachConstantBaseNode (empty encoding)"); 1195 } 1196 #endif 1197 1198 //============================================================================= 1199 1200 #ifndef PRODUCT 1201 void MachPrologNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1202 Compile* C = ra_->C; 1203 const long framesize = C->frame_slots() << LogBytesPerInt; 1204 1205 st->print("PROLOG\n\t"); 1206 if (C->need_stack_bang(framesize)) { 1207 st->print("stack_overflow_check\n\t"); 1208 } 1209 1210 if (!false /* TODO: PPC port C->is_frameless_method()*/) { 1211 st->print("save return pc\n\t"); 1212 st->print("push frame %ld\n\t", -framesize); 1213 } 1214 } 1215 #endif 1216 1217 // Macro used instead of the common __ to emulate the pipes of PPC. 1218 // Instead of e.g. __ ld(...) one hase to write ___(ld) ld(...) This enables the 1219 // micro scheduler to cope with "hand written" assembler like in the prolog. Though 1220 // still no scheduling of this code is possible, the micro scheduler is aware of the 1221 // code and can update its internal data. The following mechanism is used to achieve this: 1222 // The micro scheduler calls size() of each compound node during scheduling. size() does a 1223 // dummy emit and only during this dummy emit C->hb_scheduling() is not NULL. 1224 #if 0 // TODO: PPC port 1225 #define ___(op) if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1226 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(ppc64Opcode_##op); \ 1227 _masm. 1228 #define ___stop if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1229 C->hb_scheduling()->_pdScheduling->PdEmulatePipe(archOpcode_none) 1230 #define ___advance if (UsePower6SchedulerPPC64 && C->hb_scheduling()) \ 1231 C->hb_scheduling()->_pdScheduling->advance_offset 1232 #else 1233 #define ___(op) if (UsePower6SchedulerPPC64) \ 1234 Unimplemented(); \ 1235 _masm. 1236 #define ___stop if (UsePower6SchedulerPPC64) \ 1237 Unimplemented() 1238 #define ___advance if (UsePower6SchedulerPPC64) \ 1239 Unimplemented() 1240 #endif 1241 1242 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1243 Compile* C = ra_->C; 1244 MacroAssembler _masm(&cbuf); 1245 1246 const long framesize = C->frame_size_in_bytes(); 1247 assert(framesize % (2 * wordSize) == 0, "must preserve 2*wordSize alignment"); 1248 1249 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1250 1251 const Register return_pc = R20; // Must match return_addr() in frame section. 1252 const Register callers_sp = R21; 1253 const Register push_frame_temp = R22; 1254 const Register toc_temp = R23; 1255 assert_different_registers(R11, return_pc, callers_sp, push_frame_temp, toc_temp); 1256 1257 if (method_is_frameless) { 1258 // Add nop at beginning of all frameless methods to prevent any 1259 // oop instructions from getting overwritten by make_not_entrant 1260 // (patching attempt would fail). 1261 ___(nop) nop(); 1262 } else { 1263 // Get return pc. 1264 ___(mflr) mflr(return_pc); 1265 } 1266 1267 // Calls to C2R adapters often do not accept exceptional returns. 1268 // We require that their callers must bang for them. But be 1269 // careful, because some VM calls (such as call site linkage) can 1270 // use several kilobytes of stack. But the stack safety zone should 1271 // account for that. See bugs 4446381, 4468289, 4497237. 1272 1273 int bangsize = C->bang_size_in_bytes(); 1274 assert(bangsize >= framesize || bangsize <= 0, "stack bang size incorrect"); 1275 if (C->need_stack_bang(bangsize) && UseStackBanging) { 1276 // Unfortunately we cannot use the function provided in 1277 // assembler.cpp as we have to emulate the pipes. So I had to 1278 // insert the code of generate_stack_overflow_check(), see 1279 // assembler.cpp for some illuminative comments. 1280 const int page_size = os::vm_page_size(); 1281 int bang_end = JavaThread::stack_shadow_zone_size(); 1282 1283 // This is how far the previous frame's stack banging extended. 1284 const int bang_end_safe = bang_end; 1285 1286 if (bangsize > page_size) { 1287 bang_end += bangsize; 1288 } 1289 1290 int bang_offset = bang_end_safe; 1291 1292 while (bang_offset <= bang_end) { 1293 // Need at least one stack bang at end of shadow zone. 1294 1295 // Again I had to copy code, this time from assembler_ppc.cpp, 1296 // bang_stack_with_offset - see there for comments. 1297 1298 // Stack grows down, caller passes positive offset. 1299 assert(bang_offset > 0, "must bang with positive offset"); 1300 1301 long stdoffset = -bang_offset; 1302 1303 if (Assembler::is_simm(stdoffset, 16)) { 1304 // Signed 16 bit offset, a simple std is ok. 1305 if (UseLoadInstructionsForStackBangingPPC64) { 1306 ___(ld) ld(R0, (int)(signed short)stdoffset, R1_SP); 1307 } else { 1308 ___(std) std(R0, (int)(signed short)stdoffset, R1_SP); 1309 } 1310 } else if (Assembler::is_simm(stdoffset, 31)) { 1311 // Use largeoffset calculations for addis & ld/std. 1312 const int hi = MacroAssembler::largeoffset_si16_si16_hi(stdoffset); 1313 const int lo = MacroAssembler::largeoffset_si16_si16_lo(stdoffset); 1314 1315 Register tmp = R11; 1316 ___(addis) addis(tmp, R1_SP, hi); 1317 if (UseLoadInstructionsForStackBangingPPC64) { 1318 ___(ld) ld(R0, lo, tmp); 1319 } else { 1320 ___(std) std(R0, lo, tmp); 1321 } 1322 } else { 1323 ShouldNotReachHere(); 1324 } 1325 1326 bang_offset += page_size; 1327 } 1328 // R11 trashed 1329 } // C->need_stack_bang(framesize) && UseStackBanging 1330 1331 unsigned int bytes = (unsigned int)framesize; 1332 long offset = Assembler::align_addr(bytes, frame::alignment_in_bytes); 1333 ciMethod *currMethod = C->method(); 1334 1335 // Optimized version for most common case. 1336 if (UsePower6SchedulerPPC64 && 1337 !method_is_frameless && Assembler::is_simm((int)(-offset), 16) && 1338 !(false /* ConstantsALot TODO: PPC port*/)) { 1339 ___(or) mr(callers_sp, R1_SP); 1340 ___(std) std(return_pc, _abi(lr), R1_SP); 1341 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1342 return; 1343 } 1344 1345 if (!method_is_frameless) { 1346 // Get callers sp. 1347 ___(or) mr(callers_sp, R1_SP); 1348 1349 // Push method's frame, modifies SP. 1350 assert(Assembler::is_uimm(framesize, 32U), "wrong type"); 1351 // The ABI is already accounted for in 'framesize' via the 1352 // 'out_preserve' area. 1353 Register tmp = push_frame_temp; 1354 // Had to insert code of push_frame((unsigned int)framesize, push_frame_temp). 1355 if (Assembler::is_simm(-offset, 16)) { 1356 ___(stdu) stdu(R1_SP, -offset, R1_SP); 1357 } else { 1358 long x = -offset; 1359 // Had to insert load_const(tmp, -offset). 1360 ___(addis) lis( tmp, (int)((signed short)(((x >> 32) & 0xffff0000) >> 16))); 1361 ___(ori) ori( tmp, tmp, ((x >> 32) & 0x0000ffff)); 1362 ___(rldicr) sldi(tmp, tmp, 32); 1363 ___(oris) oris(tmp, tmp, (x & 0xffff0000) >> 16); 1364 ___(ori) ori( tmp, tmp, (x & 0x0000ffff)); 1365 1366 ___(stdux) stdux(R1_SP, R1_SP, tmp); 1367 } 1368 } 1369 #if 0 // TODO: PPC port 1370 // For testing large constant pools, emit a lot of constants to constant pool. 1371 // "Randomize" const_size. 1372 if (ConstantsALot) { 1373 const int num_consts = const_size(); 1374 for (int i = 0; i < num_consts; i++) { 1375 __ long_constant(0xB0B5B00BBABE); 1376 } 1377 } 1378 #endif 1379 if (!method_is_frameless) { 1380 // Save return pc. 1381 ___(std) std(return_pc, _abi(lr), callers_sp); 1382 } 1383 } 1384 #undef ___ 1385 #undef ___stop 1386 #undef ___advance 1387 1388 uint MachPrologNode::size(PhaseRegAlloc *ra_) const { 1389 // Variable size. determine dynamically. 1390 return MachNode::size(ra_); 1391 } 1392 1393 int MachPrologNode::reloc() const { 1394 // Return number of relocatable values contained in this instruction. 1395 return 1; // 1 reloc entry for load_const(toc). 1396 } 1397 1398 //============================================================================= 1399 1400 #ifndef PRODUCT 1401 void MachEpilogNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1402 Compile* C = ra_->C; 1403 1404 st->print("EPILOG\n\t"); 1405 st->print("restore return pc\n\t"); 1406 st->print("pop frame\n\t"); 1407 1408 if (do_polling() && C->is_method_compilation()) { 1409 st->print("touch polling page\n\t"); 1410 } 1411 } 1412 #endif 1413 1414 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1415 Compile* C = ra_->C; 1416 MacroAssembler _masm(&cbuf); 1417 1418 const long framesize = ((long)C->frame_slots()) << LogBytesPerInt; 1419 assert(framesize >= 0, "negative frame-size?"); 1420 1421 const bool method_needs_polling = do_polling() && C->is_method_compilation(); 1422 const bool method_is_frameless = false /* TODO: PPC port C->is_frameless_method()*/; 1423 const Register return_pc = R11; 1424 const Register polling_page = R12; 1425 1426 if (!method_is_frameless) { 1427 // Restore return pc relative to callers' sp. 1428 __ ld(return_pc, ((int)framesize) + _abi(lr), R1_SP); 1429 } 1430 1431 if (method_needs_polling) { 1432 if (LoadPollAddressFromThread) { 1433 // TODO: PPC port __ ld(polling_page, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1434 Unimplemented(); 1435 } else { 1436 __ load_const_optimized(polling_page, (long)(address) os::get_polling_page()); // TODO: PPC port: get_standard_polling_page() 1437 } 1438 } 1439 1440 if (!method_is_frameless) { 1441 // Move return pc to LR. 1442 __ mtlr(return_pc); 1443 // Pop frame (fixed frame-size). 1444 __ addi(R1_SP, R1_SP, (int)framesize); 1445 } 1446 1447 if (method_needs_polling) { 1448 // We need to mark the code position where the load from the safepoint 1449 // polling page was emitted as relocInfo::poll_return_type here. 1450 __ relocate(relocInfo::poll_return_type); 1451 __ load_from_polling_page(polling_page); 1452 } 1453 } 1454 1455 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const { 1456 // Variable size. Determine dynamically. 1457 return MachNode::size(ra_); 1458 } 1459 1460 int MachEpilogNode::reloc() const { 1461 // Return number of relocatable values contained in this instruction. 1462 return 1; // 1 for load_from_polling_page. 1463 } 1464 1465 const Pipeline * MachEpilogNode::pipeline() const { 1466 return MachNode::pipeline_class(); 1467 } 1468 1469 // This method seems to be obsolete. It is declared in machnode.hpp 1470 // and defined in all *.ad files, but it is never called. Should we 1471 // get rid of it? 1472 int MachEpilogNode::safepoint_offset() const { 1473 assert(do_polling(), "no return for this epilog node"); 1474 return 0; 1475 } 1476 1477 #if 0 // TODO: PPC port 1478 void MachLoadPollAddrLateNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const { 1479 MacroAssembler _masm(&cbuf); 1480 if (LoadPollAddressFromThread) { 1481 _masm.ld(R11, in_bytes(JavaThread::poll_address_offset()), R16_thread); 1482 } else { 1483 _masm.nop(); 1484 } 1485 } 1486 1487 uint MachLoadPollAddrLateNode::size(PhaseRegAlloc* ra_) const { 1488 if (LoadPollAddressFromThread) { 1489 return 4; 1490 } else { 1491 return 4; 1492 } 1493 } 1494 1495 #ifndef PRODUCT 1496 void MachLoadPollAddrLateNode::format(PhaseRegAlloc* ra_, outputStream* st) const { 1497 st->print_cr(" LD R11, PollAddressOffset, R16_thread \t// LoadPollAddressFromThread"); 1498 } 1499 #endif 1500 1501 const RegMask &MachLoadPollAddrLateNode::out_RegMask() const { 1502 return RSCRATCH1_BITS64_REG_mask(); 1503 } 1504 #endif // PPC port 1505 1506 // ============================================================================= 1507 1508 // Figure out which register class each belongs in: rc_int, rc_float or 1509 // rc_stack. 1510 enum RC { rc_bad, rc_int, rc_float, rc_stack }; 1511 1512 static enum RC rc_class(OptoReg::Name reg) { 1513 // Return the register class for the given register. The given register 1514 // reg is a <register>_num value, which is an index into the MachRegisterNumbers 1515 // enumeration in adGlobals_ppc.hpp. 1516 1517 if (reg == OptoReg::Bad) return rc_bad; 1518 1519 // We have 64 integer register halves, starting at index 0. 1520 if (reg < 64) return rc_int; 1521 1522 // We have 64 floating-point register halves, starting at index 64. 1523 if (reg < 64+64) return rc_float; 1524 1525 // Between float regs & stack are the flags regs. 1526 assert(OptoReg::is_stack(reg), "blow up if spilling flags"); 1527 1528 return rc_stack; 1529 } 1530 1531 static int ld_st_helper(CodeBuffer *cbuf, const char *op_str, uint opcode, int reg, int offset, 1532 bool do_print, Compile* C, outputStream *st) { 1533 1534 assert(opcode == Assembler::LD_OPCODE || 1535 opcode == Assembler::STD_OPCODE || 1536 opcode == Assembler::LWZ_OPCODE || 1537 opcode == Assembler::STW_OPCODE || 1538 opcode == Assembler::LFD_OPCODE || 1539 opcode == Assembler::STFD_OPCODE || 1540 opcode == Assembler::LFS_OPCODE || 1541 opcode == Assembler::STFS_OPCODE, 1542 "opcode not supported"); 1543 1544 if (cbuf) { 1545 int d = 1546 (Assembler::LD_OPCODE == opcode || Assembler::STD_OPCODE == opcode) ? 1547 Assembler::ds(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/) 1548 : Assembler::d1(offset+0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); // Makes no difference in opt build. 1549 emit_long(*cbuf, opcode | Assembler::rt(Matcher::_regEncode[reg]) | d | Assembler::ra(R1_SP)); 1550 } 1551 #ifndef PRODUCT 1552 else if (do_print) { 1553 st->print("%-7s %s, [R1_SP + #%d+%d] \t// spill copy", 1554 op_str, 1555 Matcher::regName[reg], 1556 offset, 0 /* TODO: PPC port C->frame_slots_sp_bias_in_bytes()*/); 1557 } 1558 #endif 1559 return 4; // size 1560 } 1561 1562 uint MachSpillCopyNode::implementation(CodeBuffer *cbuf, PhaseRegAlloc *ra_, bool do_size, outputStream *st) const { 1563 Compile* C = ra_->C; 1564 1565 // Get registers to move. 1566 OptoReg::Name src_hi = ra_->get_reg_second(in(1)); 1567 OptoReg::Name src_lo = ra_->get_reg_first(in(1)); 1568 OptoReg::Name dst_hi = ra_->get_reg_second(this); 1569 OptoReg::Name dst_lo = ra_->get_reg_first(this); 1570 1571 enum RC src_hi_rc = rc_class(src_hi); 1572 enum RC src_lo_rc = rc_class(src_lo); 1573 enum RC dst_hi_rc = rc_class(dst_hi); 1574 enum RC dst_lo_rc = rc_class(dst_lo); 1575 1576 assert(src_lo != OptoReg::Bad && dst_lo != OptoReg::Bad, "must move at least 1 register"); 1577 if (src_hi != OptoReg::Bad) 1578 assert((src_lo&1)==0 && src_lo+1==src_hi && 1579 (dst_lo&1)==0 && dst_lo+1==dst_hi, 1580 "expected aligned-adjacent pairs"); 1581 // Generate spill code! 1582 int size = 0; 1583 1584 if (src_lo == dst_lo && src_hi == dst_hi) 1585 return size; // Self copy, no move. 1586 1587 // -------------------------------------- 1588 // Memory->Memory Spill. Use R0 to hold the value. 1589 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1590 int src_offset = ra_->reg2offset(src_lo); 1591 int dst_offset = ra_->reg2offset(dst_lo); 1592 if (src_hi != OptoReg::Bad) { 1593 assert(src_hi_rc==rc_stack && dst_hi_rc==rc_stack, 1594 "expected same type of move for high parts"); 1595 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, R0_num, src_offset, !do_size, C, st); 1596 if (!cbuf && !do_size) st->print("\n\t"); 1597 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, R0_num, dst_offset, !do_size, C, st); 1598 } else { 1599 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, R0_num, src_offset, !do_size, C, st); 1600 if (!cbuf && !do_size) st->print("\n\t"); 1601 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, R0_num, dst_offset, !do_size, C, st); 1602 } 1603 return size; 1604 } 1605 1606 // -------------------------------------- 1607 // Check for float->int copy; requires a trip through memory. 1608 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1609 Unimplemented(); 1610 } 1611 1612 // -------------------------------------- 1613 // Check for integer reg-reg copy. 1614 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1615 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1616 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1617 size = (Rsrc != Rdst) ? 4 : 0; 1618 1619 if (cbuf) { 1620 MacroAssembler _masm(cbuf); 1621 if (size) { 1622 __ mr(Rdst, Rsrc); 1623 } 1624 } 1625 #ifndef PRODUCT 1626 else if (!do_size) { 1627 if (size) { 1628 st->print("%-7s %s, %s \t// spill copy", "MR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1629 } else { 1630 st->print("%-7s %s, %s \t// spill copy", "MR-NOP", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1631 } 1632 } 1633 #endif 1634 return size; 1635 } 1636 1637 // Check for integer store. 1638 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1639 int dst_offset = ra_->reg2offset(dst_lo); 1640 if (src_hi != OptoReg::Bad) { 1641 assert(src_hi_rc==rc_int && dst_hi_rc==rc_stack, 1642 "expected same type of move for high parts"); 1643 size += ld_st_helper(cbuf, "STD ", Assembler::STD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1644 } else { 1645 size += ld_st_helper(cbuf, "STW ", Assembler::STW_OPCODE, src_lo, dst_offset, !do_size, C, st); 1646 } 1647 return size; 1648 } 1649 1650 // Check for integer load. 1651 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1652 int src_offset = ra_->reg2offset(src_lo); 1653 if (src_hi != OptoReg::Bad) { 1654 assert(dst_hi_rc==rc_int && src_hi_rc==rc_stack, 1655 "expected same type of move for high parts"); 1656 size += ld_st_helper(cbuf, "LD ", Assembler::LD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1657 } else { 1658 size += ld_st_helper(cbuf, "LWZ ", Assembler::LWZ_OPCODE, dst_lo, src_offset, !do_size, C, st); 1659 } 1660 return size; 1661 } 1662 1663 // Check for float reg-reg copy. 1664 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1665 if (cbuf) { 1666 MacroAssembler _masm(cbuf); 1667 FloatRegister Rsrc = as_FloatRegister(Matcher::_regEncode[src_lo]); 1668 FloatRegister Rdst = as_FloatRegister(Matcher::_regEncode[dst_lo]); 1669 __ fmr(Rdst, Rsrc); 1670 } 1671 #ifndef PRODUCT 1672 else if (!do_size) { 1673 st->print("%-7s %s, %s \t// spill copy", "FMR", Matcher::regName[dst_lo], Matcher::regName[src_lo]); 1674 } 1675 #endif 1676 return 4; 1677 } 1678 1679 // Check for float store. 1680 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1681 int dst_offset = ra_->reg2offset(dst_lo); 1682 if (src_hi != OptoReg::Bad) { 1683 assert(src_hi_rc==rc_float && dst_hi_rc==rc_stack, 1684 "expected same type of move for high parts"); 1685 size += ld_st_helper(cbuf, "STFD", Assembler::STFD_OPCODE, src_lo, dst_offset, !do_size, C, st); 1686 } else { 1687 size += ld_st_helper(cbuf, "STFS", Assembler::STFS_OPCODE, src_lo, dst_offset, !do_size, C, st); 1688 } 1689 return size; 1690 } 1691 1692 // Check for float load. 1693 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1694 int src_offset = ra_->reg2offset(src_lo); 1695 if (src_hi != OptoReg::Bad) { 1696 assert(dst_hi_rc==rc_float && src_hi_rc==rc_stack, 1697 "expected same type of move for high parts"); 1698 size += ld_st_helper(cbuf, "LFD ", Assembler::LFD_OPCODE, dst_lo, src_offset, !do_size, C, st); 1699 } else { 1700 size += ld_st_helper(cbuf, "LFS ", Assembler::LFS_OPCODE, dst_lo, src_offset, !do_size, C, st); 1701 } 1702 return size; 1703 } 1704 1705 // -------------------------------------------------------------------- 1706 // Check for hi bits still needing moving. Only happens for misaligned 1707 // arguments to native calls. 1708 if (src_hi == dst_hi) 1709 return size; // Self copy; no move. 1710 1711 assert(src_hi_rc != rc_bad && dst_hi_rc != rc_bad, "src_hi & dst_hi cannot be Bad"); 1712 ShouldNotReachHere(); // Unimplemented 1713 return 0; 1714 } 1715 1716 #ifndef PRODUCT 1717 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1718 if (!ra_) 1719 st->print("N%d = SpillCopy(N%d)", _idx, in(1)->_idx); 1720 else 1721 implementation(NULL, ra_, false, st); 1722 } 1723 #endif 1724 1725 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1726 implementation(&cbuf, ra_, false, NULL); 1727 } 1728 1729 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const { 1730 return implementation(NULL, ra_, true, NULL); 1731 } 1732 1733 #if 0 // TODO: PPC port 1734 ArchOpcode MachSpillCopyNode_archOpcode(MachSpillCopyNode *n, PhaseRegAlloc *ra_) { 1735 #ifndef PRODUCT 1736 if (ra_->node_regs_max_index() == 0) return archOpcode_undefined; 1737 #endif 1738 assert(ra_->node_regs_max_index() != 0, ""); 1739 1740 // Get registers to move. 1741 OptoReg::Name src_hi = ra_->get_reg_second(n->in(1)); 1742 OptoReg::Name src_lo = ra_->get_reg_first(n->in(1)); 1743 OptoReg::Name dst_hi = ra_->get_reg_second(n); 1744 OptoReg::Name dst_lo = ra_->get_reg_first(n); 1745 1746 enum RC src_lo_rc = rc_class(src_lo); 1747 enum RC dst_lo_rc = rc_class(dst_lo); 1748 1749 if (src_lo == dst_lo && src_hi == dst_hi) 1750 return ppc64Opcode_none; // Self copy, no move. 1751 1752 // -------------------------------------- 1753 // Memory->Memory Spill. Use R0 to hold the value. 1754 if (src_lo_rc == rc_stack && dst_lo_rc == rc_stack) { 1755 return ppc64Opcode_compound; 1756 } 1757 1758 // -------------------------------------- 1759 // Check for float->int copy; requires a trip through memory. 1760 if (src_lo_rc == rc_float && dst_lo_rc == rc_int) { 1761 Unimplemented(); 1762 } 1763 1764 // -------------------------------------- 1765 // Check for integer reg-reg copy. 1766 if (src_lo_rc == rc_int && dst_lo_rc == rc_int) { 1767 Register Rsrc = as_Register(Matcher::_regEncode[src_lo]); 1768 Register Rdst = as_Register(Matcher::_regEncode[dst_lo]); 1769 if (Rsrc == Rdst) { 1770 return ppc64Opcode_none; 1771 } else { 1772 return ppc64Opcode_or; 1773 } 1774 } 1775 1776 // Check for integer store. 1777 if (src_lo_rc == rc_int && dst_lo_rc == rc_stack) { 1778 if (src_hi != OptoReg::Bad) { 1779 return ppc64Opcode_std; 1780 } else { 1781 return ppc64Opcode_stw; 1782 } 1783 } 1784 1785 // Check for integer load. 1786 if (dst_lo_rc == rc_int && src_lo_rc == rc_stack) { 1787 if (src_hi != OptoReg::Bad) { 1788 return ppc64Opcode_ld; 1789 } else { 1790 return ppc64Opcode_lwz; 1791 } 1792 } 1793 1794 // Check for float reg-reg copy. 1795 if (src_lo_rc == rc_float && dst_lo_rc == rc_float) { 1796 return ppc64Opcode_fmr; 1797 } 1798 1799 // Check for float store. 1800 if (src_lo_rc == rc_float && dst_lo_rc == rc_stack) { 1801 if (src_hi != OptoReg::Bad) { 1802 return ppc64Opcode_stfd; 1803 } else { 1804 return ppc64Opcode_stfs; 1805 } 1806 } 1807 1808 // Check for float load. 1809 if (dst_lo_rc == rc_float && src_lo_rc == rc_stack) { 1810 if (src_hi != OptoReg::Bad) { 1811 return ppc64Opcode_lfd; 1812 } else { 1813 return ppc64Opcode_lfs; 1814 } 1815 } 1816 1817 // -------------------------------------------------------------------- 1818 // Check for hi bits still needing moving. Only happens for misaligned 1819 // arguments to native calls. 1820 if (src_hi == dst_hi) { 1821 return ppc64Opcode_none; // Self copy; no move. 1822 } 1823 1824 ShouldNotReachHere(); 1825 return ppc64Opcode_undefined; 1826 } 1827 #endif // PPC port 1828 1829 #ifndef PRODUCT 1830 void MachNopNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1831 st->print("NOP \t// %d nops to pad for loops.", _count); 1832 } 1833 #endif 1834 1835 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *) const { 1836 MacroAssembler _masm(&cbuf); 1837 // _count contains the number of nops needed for padding. 1838 for (int i = 0; i < _count; i++) { 1839 __ nop(); 1840 } 1841 } 1842 1843 uint MachNopNode::size(PhaseRegAlloc *ra_) const { 1844 return _count * 4; 1845 } 1846 1847 #ifndef PRODUCT 1848 void BoxLockNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1849 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1850 char reg_str[128]; 1851 ra_->dump_register(this, reg_str); 1852 st->print("ADDI %s, SP, %d \t// box node", reg_str, offset); 1853 } 1854 #endif 1855 1856 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1857 MacroAssembler _masm(&cbuf); 1858 1859 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()); 1860 int reg = ra_->get_encode(this); 1861 1862 if (Assembler::is_simm(offset, 16)) { 1863 __ addi(as_Register(reg), R1, offset); 1864 } else { 1865 ShouldNotReachHere(); 1866 } 1867 } 1868 1869 uint BoxLockNode::size(PhaseRegAlloc *ra_) const { 1870 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_). 1871 return 4; 1872 } 1873 1874 #ifndef PRODUCT 1875 void MachUEPNode::format(PhaseRegAlloc *ra_, outputStream *st) const { 1876 st->print_cr("---- MachUEPNode ----"); 1877 st->print_cr("..."); 1878 } 1879 #endif 1880 1881 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const { 1882 // This is the unverified entry point. 1883 MacroAssembler _masm(&cbuf); 1884 1885 // Inline_cache contains a klass. 1886 Register ic_klass = as_Register(Matcher::inline_cache_reg_encode()); 1887 Register receiver_klass = R12_scratch2; // tmp 1888 1889 assert_different_registers(ic_klass, receiver_klass, R11_scratch1, R3_ARG1); 1890 assert(R11_scratch1 == R11, "need prologue scratch register"); 1891 1892 // Check for NULL argument if we don't have implicit null checks. 1893 if (!ImplicitNullChecks || !os::zero_page_read_protected()) { 1894 if (TrapBasedNullChecks) { 1895 __ trap_null_check(R3_ARG1); 1896 } else { 1897 Label valid; 1898 __ cmpdi(CCR0, R3_ARG1, 0); 1899 __ bne_predict_taken(CCR0, valid); 1900 // We have a null argument, branch to ic_miss_stub. 1901 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 1902 relocInfo::runtime_call_type); 1903 __ bind(valid); 1904 } 1905 } 1906 // Assume argument is not NULL, load klass from receiver. 1907 __ load_klass(receiver_klass, R3_ARG1); 1908 1909 if (TrapBasedICMissChecks) { 1910 __ trap_ic_miss_check(receiver_klass, ic_klass); 1911 } else { 1912 Label valid; 1913 __ cmpd(CCR0, receiver_klass, ic_klass); 1914 __ beq_predict_taken(CCR0, valid); 1915 // We have an unexpected klass, branch to ic_miss_stub. 1916 __ b64_patchable((address)SharedRuntime::get_ic_miss_stub(), 1917 relocInfo::runtime_call_type); 1918 __ bind(valid); 1919 } 1920 1921 // Argument is valid and klass is as expected, continue. 1922 } 1923 1924 #if 0 // TODO: PPC port 1925 // Optimize UEP code on z (save a load_const() call in main path). 1926 int MachUEPNode::ep_offset() { 1927 return 0; 1928 } 1929 #endif 1930 1931 uint MachUEPNode::size(PhaseRegAlloc *ra_) const { 1932 // Variable size. Determine dynamically. 1933 return MachNode::size(ra_); 1934 } 1935 1936 //============================================================================= 1937 1938 %} // interrupt source 1939 1940 source_hpp %{ // Header information of the source block. 1941 1942 class HandlerImpl { 1943 1944 public: 1945 1946 static int emit_exception_handler(CodeBuffer &cbuf); 1947 static int emit_deopt_handler(CodeBuffer& cbuf); 1948 1949 static uint size_exception_handler() { 1950 // The exception_handler is a b64_patchable. 1951 return MacroAssembler::b64_patchable_size; 1952 } 1953 1954 static uint size_deopt_handler() { 1955 // The deopt_handler is a bl64_patchable. 1956 return MacroAssembler::bl64_patchable_size; 1957 } 1958 1959 }; 1960 1961 %} // end source_hpp 1962 1963 source %{ 1964 1965 int HandlerImpl::emit_exception_handler(CodeBuffer &cbuf) { 1966 MacroAssembler _masm(&cbuf); 1967 1968 address base = __ start_a_stub(size_exception_handler()); 1969 if (base == NULL) return 0; // CodeBuffer::expand failed 1970 1971 int offset = __ offset(); 1972 __ b64_patchable((address)OptoRuntime::exception_blob()->content_begin(), 1973 relocInfo::runtime_call_type); 1974 assert(__ offset() - offset == (int)size_exception_handler(), "must be fixed size"); 1975 __ end_a_stub(); 1976 1977 return offset; 1978 } 1979 1980 // The deopt_handler is like the exception handler, but it calls to 1981 // the deoptimization blob instead of jumping to the exception blob. 1982 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) { 1983 MacroAssembler _masm(&cbuf); 1984 1985 address base = __ start_a_stub(size_deopt_handler()); 1986 if (base == NULL) return 0; // CodeBuffer::expand failed 1987 1988 int offset = __ offset(); 1989 __ bl64_patchable((address)SharedRuntime::deopt_blob()->unpack(), 1990 relocInfo::runtime_call_type); 1991 assert(__ offset() - offset == (int) size_deopt_handler(), "must be fixed size"); 1992 __ end_a_stub(); 1993 1994 return offset; 1995 } 1996 1997 //============================================================================= 1998 1999 // Use a frame slots bias for frameless methods if accessing the stack. 2000 static int frame_slots_bias(int reg_enc, PhaseRegAlloc* ra_) { 2001 if (as_Register(reg_enc) == R1_SP) { 2002 return 0; // TODO: PPC port ra_->C->frame_slots_sp_bias_in_bytes(); 2003 } 2004 return 0; 2005 } 2006 2007 const bool Matcher::match_rule_supported(int opcode) { 2008 if (!has_match_rule(opcode)) 2009 return false; 2010 2011 switch (opcode) { 2012 case Op_SqrtD: 2013 return VM_Version::has_fsqrt(); 2014 case Op_CountLeadingZerosI: 2015 case Op_CountLeadingZerosL: 2016 case Op_CountTrailingZerosI: 2017 case Op_CountTrailingZerosL: 2018 if (!UseCountLeadingZerosInstructionsPPC64) 2019 return false; 2020 break; 2021 2022 case Op_PopCountI: 2023 case Op_PopCountL: 2024 return (UsePopCountInstruction && VM_Version::has_popcntw()); 2025 2026 case Op_StrComp: 2027 return SpecialStringCompareTo; 2028 case Op_StrEquals: 2029 return SpecialStringEquals; 2030 case Op_StrIndexOf: 2031 return SpecialStringIndexOf; 2032 case Op_StrIndexOfChar: 2033 return SpecialStringIndexOf; 2034 } 2035 2036 return true; // Per default match rules are supported. 2037 } 2038 2039 const bool Matcher::match_rule_supported_vector(int opcode, int vlen) { 2040 2041 // TODO 2042 // identify extra cases that we might want to provide match rules for 2043 // e.g. Op_ vector nodes and other intrinsics while guarding with vlen 2044 bool ret_value = match_rule_supported(opcode); 2045 // Add rules here. 2046 2047 return ret_value; // Per default match rules are supported. 2048 } 2049 2050 const int Matcher::float_pressure(int default_pressure_threshold) { 2051 return default_pressure_threshold; 2052 } 2053 2054 int Matcher::regnum_to_fpu_offset(int regnum) { 2055 // No user for this method? 2056 Unimplemented(); 2057 return 999; 2058 } 2059 2060 const bool Matcher::convL2FSupported(void) { 2061 // fcfids can do the conversion (>= Power7). 2062 // fcfid + frsp showed rounding problem when result should be 0x3f800001. 2063 return VM_Version::has_fcfids(); // False means that conversion is done by runtime call. 2064 } 2065 2066 // Vector width in bytes. 2067 const int Matcher::vector_width_in_bytes(BasicType bt) { 2068 assert(MaxVectorSize == 8, ""); 2069 return 8; 2070 } 2071 2072 // Vector ideal reg. 2073 const int Matcher::vector_ideal_reg(int size) { 2074 assert(MaxVectorSize == 8 && size == 8, ""); 2075 return Op_RegL; 2076 } 2077 2078 const int Matcher::vector_shift_count_ideal_reg(int size) { 2079 fatal("vector shift is not supported"); 2080 return Node::NotAMachineReg; 2081 } 2082 2083 // Limits on vector size (number of elements) loaded into vector. 2084 const int Matcher::max_vector_size(const BasicType bt) { 2085 assert(is_java_primitive(bt), "only primitive type vectors"); 2086 return vector_width_in_bytes(bt)/type2aelembytes(bt); 2087 } 2088 2089 const int Matcher::min_vector_size(const BasicType bt) { 2090 return max_vector_size(bt); // Same as max. 2091 } 2092 2093 // PPC doesn't support misaligned vectors store/load. 2094 const bool Matcher::misaligned_vectors_ok() { 2095 return false; 2096 } 2097 2098 // PPC AES support not yet implemented 2099 const bool Matcher::pass_original_key_for_aes() { 2100 return false; 2101 } 2102 2103 // RETURNS: whether this branch offset is short enough that a short 2104 // branch can be used. 2105 // 2106 // If the platform does not provide any short branch variants, then 2107 // this method should return `false' for offset 0. 2108 // 2109 // `Compile::Fill_buffer' will decide on basis of this information 2110 // whether to do the pass `Compile::Shorten_branches' at all. 2111 // 2112 // And `Compile::Shorten_branches' will decide on basis of this 2113 // information whether to replace particular branch sites by short 2114 // ones. 2115 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) { 2116 // Is the offset within the range of a ppc64 pc relative branch? 2117 bool b; 2118 2119 const int safety_zone = 3 * BytesPerInstWord; 2120 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone), 2121 29 - 16 + 1 + 2); 2122 return b; 2123 } 2124 2125 const bool Matcher::isSimpleConstant64(jlong value) { 2126 // Probably always true, even if a temp register is required. 2127 return true; 2128 } 2129 /* TODO: PPC port 2130 // Make a new machine dependent decode node (with its operands). 2131 MachTypeNode *Matcher::make_decode_node() { 2132 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0, 2133 "This method is only implemented for unscaled cOops mode so far"); 2134 MachTypeNode *decode = new decodeN_unscaledNode(); 2135 decode->set_opnd_array(0, new iRegPdstOper()); 2136 decode->set_opnd_array(1, new iRegNsrcOper()); 2137 return decode; 2138 } 2139 */ 2140 2141 // false => size gets scaled to BytesPerLong, ok. 2142 const bool Matcher::init_array_count_is_in_bytes = false; 2143 2144 // Use conditional move (CMOVL) on Power7. 2145 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves 2146 2147 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet. 2148 // fsel doesn't accept a condition register as input, so this would be slightly different. 2149 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; } 2150 2151 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand). 2152 const bool Matcher::require_postalloc_expand = true; 2153 2154 // Should the Matcher clone shifts on addressing modes, expecting them to 2155 // be subsumed into complex addressing expressions or compute them into 2156 // registers? True for Intel but false for most RISCs. 2157 const bool Matcher::clone_shift_expressions = false; 2158 2159 // Do we need to mask the count passed to shift instructions or does 2160 // the cpu only look at the lower 5/6 bits anyway? 2161 // PowerPC requires masked shift counts. 2162 const bool Matcher::need_masked_shift_count = true; 2163 2164 // This affects two different things: 2165 // - how Decode nodes are matched 2166 // - how ImplicitNullCheck opportunities are recognized 2167 // If true, the matcher will try to remove all Decodes and match them 2168 // (as operands) into nodes. NullChecks are not prepared to deal with 2169 // Decodes by final_graph_reshaping(). 2170 // If false, final_graph_reshaping() forces the decode behind the Cmp 2171 // for a NullCheck. The matcher matches the Decode node into a register. 2172 // Implicit_null_check optimization moves the Decode along with the 2173 // memory operation back up before the NullCheck. 2174 bool Matcher::narrow_oop_use_complex_address() { 2175 // TODO: PPC port if (MatchDecodeNodes) return true; 2176 return false; 2177 } 2178 2179 bool Matcher::narrow_klass_use_complex_address() { 2180 NOT_LP64(ShouldNotCallThis()); 2181 assert(UseCompressedClassPointers, "only for compressed klass code"); 2182 // TODO: PPC port if (MatchDecodeNodes) return true; 2183 return false; 2184 } 2185 2186 // Is it better to copy float constants, or load them directly from memory? 2187 // Intel can load a float constant from a direct address, requiring no 2188 // extra registers. Most RISCs will have to materialize an address into a 2189 // register first, so they would do better to copy the constant from stack. 2190 const bool Matcher::rematerialize_float_constants = false; 2191 2192 // If CPU can load and store mis-aligned doubles directly then no fixup is 2193 // needed. Else we split the double into 2 integer pieces and move it 2194 // piece-by-piece. Only happens when passing doubles into C code as the 2195 // Java calling convention forces doubles to be aligned. 2196 const bool Matcher::misaligned_doubles_ok = true; 2197 2198 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) { 2199 Unimplemented(); 2200 } 2201 2202 // Advertise here if the CPU requires explicit rounding operations 2203 // to implement the UseStrictFP mode. 2204 const bool Matcher::strict_fp_requires_explicit_rounding = false; 2205 2206 // Do floats take an entire double register or just half? 2207 // 2208 // A float occupies a ppc64 double register. For the allocator, a 2209 // ppc64 double register appears as a pair of float registers. 2210 bool Matcher::float_in_double() { return true; } 2211 2212 // Do ints take an entire long register or just half? 2213 // The relevant question is how the int is callee-saved: 2214 // the whole long is written but de-opt'ing will have to extract 2215 // the relevant 32 bits. 2216 const bool Matcher::int_in_long = true; 2217 2218 // Constants for c2c and c calling conventions. 2219 2220 const MachRegisterNumbers iarg_reg[8] = { 2221 R3_num, R4_num, R5_num, R6_num, 2222 R7_num, R8_num, R9_num, R10_num 2223 }; 2224 2225 const MachRegisterNumbers farg_reg[13] = { 2226 F1_num, F2_num, F3_num, F4_num, 2227 F5_num, F6_num, F7_num, F8_num, 2228 F9_num, F10_num, F11_num, F12_num, 2229 F13_num 2230 }; 2231 2232 const int num_iarg_registers = sizeof(iarg_reg) / sizeof(iarg_reg[0]); 2233 2234 const int num_farg_registers = sizeof(farg_reg) / sizeof(farg_reg[0]); 2235 2236 // Return whether or not this register is ever used as an argument. This 2237 // function is used on startup to build the trampoline stubs in generateOptoStub. 2238 // Registers not mentioned will be killed by the VM call in the trampoline, and 2239 // arguments in those registers not be available to the callee. 2240 bool Matcher::can_be_java_arg(int reg) { 2241 // We return true for all registers contained in iarg_reg[] and 2242 // farg_reg[] and their virtual halves. 2243 // We must include the virtual halves in order to get STDs and LDs 2244 // instead of STWs and LWs in the trampoline stubs. 2245 2246 if ( reg == R3_num || reg == R3_H_num 2247 || reg == R4_num || reg == R4_H_num 2248 || reg == R5_num || reg == R5_H_num 2249 || reg == R6_num || reg == R6_H_num 2250 || reg == R7_num || reg == R7_H_num 2251 || reg == R8_num || reg == R8_H_num 2252 || reg == R9_num || reg == R9_H_num 2253 || reg == R10_num || reg == R10_H_num) 2254 return true; 2255 2256 if ( reg == F1_num || reg == F1_H_num 2257 || reg == F2_num || reg == F2_H_num 2258 || reg == F3_num || reg == F3_H_num 2259 || reg == F4_num || reg == F4_H_num 2260 || reg == F5_num || reg == F5_H_num 2261 || reg == F6_num || reg == F6_H_num 2262 || reg == F7_num || reg == F7_H_num 2263 || reg == F8_num || reg == F8_H_num 2264 || reg == F9_num || reg == F9_H_num 2265 || reg == F10_num || reg == F10_H_num 2266 || reg == F11_num || reg == F11_H_num 2267 || reg == F12_num || reg == F12_H_num 2268 || reg == F13_num || reg == F13_H_num) 2269 return true; 2270 2271 return false; 2272 } 2273 2274 bool Matcher::is_spillable_arg(int reg) { 2275 return can_be_java_arg(reg); 2276 } 2277 2278 bool Matcher::use_asm_for_ldiv_by_con(jlong divisor) { 2279 return false; 2280 } 2281 2282 // Register for DIVI projection of divmodI. 2283 RegMask Matcher::divI_proj_mask() { 2284 ShouldNotReachHere(); 2285 return RegMask(); 2286 } 2287 2288 // Register for MODI projection of divmodI. 2289 RegMask Matcher::modI_proj_mask() { 2290 ShouldNotReachHere(); 2291 return RegMask(); 2292 } 2293 2294 // Register for DIVL projection of divmodL. 2295 RegMask Matcher::divL_proj_mask() { 2296 ShouldNotReachHere(); 2297 return RegMask(); 2298 } 2299 2300 // Register for MODL projection of divmodL. 2301 RegMask Matcher::modL_proj_mask() { 2302 ShouldNotReachHere(); 2303 return RegMask(); 2304 } 2305 2306 const RegMask Matcher::method_handle_invoke_SP_save_mask() { 2307 return RegMask(); 2308 } 2309 2310 %} 2311 2312 //----------ENCODING BLOCK----------------------------------------------------- 2313 // This block specifies the encoding classes used by the compiler to output 2314 // byte streams. Encoding classes are parameterized macros used by 2315 // Machine Instruction Nodes in order to generate the bit encoding of the 2316 // instruction. Operands specify their base encoding interface with the 2317 // interface keyword. There are currently supported four interfaces, 2318 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an 2319 // operand to generate a function which returns its register number when 2320 // queried. CONST_INTER causes an operand to generate a function which 2321 // returns the value of the constant when queried. MEMORY_INTER causes an 2322 // operand to generate four functions which return the Base Register, the 2323 // Index Register, the Scale Value, and the Offset Value of the operand when 2324 // queried. COND_INTER causes an operand to generate six functions which 2325 // return the encoding code (ie - encoding bits for the instruction) 2326 // associated with each basic boolean condition for a conditional instruction. 2327 // 2328 // Instructions specify two basic values for encoding. Again, a function 2329 // is available to check if the constant displacement is an oop. They use the 2330 // ins_encode keyword to specify their encoding classes (which must be 2331 // a sequence of enc_class names, and their parameters, specified in 2332 // the encoding block), and they use the 2333 // opcode keyword to specify, in order, their primary, secondary, and 2334 // tertiary opcode. Only the opcode sections which a particular instruction 2335 // needs for encoding need to be specified. 2336 encode %{ 2337 enc_class enc_unimplemented %{ 2338 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2339 MacroAssembler _masm(&cbuf); 2340 __ unimplemented("Unimplemented mach node encoding in AD file.", 13); 2341 %} 2342 2343 enc_class enc_untested %{ 2344 #ifdef ASSERT 2345 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2346 MacroAssembler _masm(&cbuf); 2347 __ untested("Untested mach node encoding in AD file."); 2348 #else 2349 // TODO: PPC port $archOpcode(ppc64Opcode_none); 2350 #endif 2351 %} 2352 2353 enc_class enc_lbz(iRegIdst dst, memory mem) %{ 2354 // TODO: PPC port $archOpcode(ppc64Opcode_lbz); 2355 MacroAssembler _masm(&cbuf); 2356 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2357 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2358 %} 2359 2360 // Load acquire. 2361 enc_class enc_lbz_ac(iRegIdst dst, memory mem) %{ 2362 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2363 MacroAssembler _masm(&cbuf); 2364 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2365 __ lbz($dst$$Register, Idisp, $mem$$base$$Register); 2366 __ twi_0($dst$$Register); 2367 __ isync(); 2368 %} 2369 2370 enc_class enc_lhz(iRegIdst dst, memory mem) %{ 2371 // TODO: PPC port $archOpcode(ppc64Opcode_lhz); 2372 2373 MacroAssembler _masm(&cbuf); 2374 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2375 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2376 %} 2377 2378 // Load acquire. 2379 enc_class enc_lhz_ac(iRegIdst dst, memory mem) %{ 2380 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2381 2382 MacroAssembler _masm(&cbuf); 2383 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2384 __ lhz($dst$$Register, Idisp, $mem$$base$$Register); 2385 __ twi_0($dst$$Register); 2386 __ isync(); 2387 %} 2388 2389 enc_class enc_lwz(iRegIdst dst, memory mem) %{ 2390 // TODO: PPC port $archOpcode(ppc64Opcode_lwz); 2391 2392 MacroAssembler _masm(&cbuf); 2393 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2394 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2395 %} 2396 2397 // Load acquire. 2398 enc_class enc_lwz_ac(iRegIdst dst, memory mem) %{ 2399 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2400 2401 MacroAssembler _masm(&cbuf); 2402 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2403 __ lwz($dst$$Register, Idisp, $mem$$base$$Register); 2404 __ twi_0($dst$$Register); 2405 __ isync(); 2406 %} 2407 2408 enc_class enc_ld(iRegLdst dst, memoryAlg4 mem) %{ 2409 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2410 MacroAssembler _masm(&cbuf); 2411 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2412 // Operand 'ds' requires 4-alignment. 2413 assert((Idisp & 0x3) == 0, "unaligned offset"); 2414 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2415 %} 2416 2417 // Load acquire. 2418 enc_class enc_ld_ac(iRegLdst dst, memoryAlg4 mem) %{ 2419 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2420 MacroAssembler _masm(&cbuf); 2421 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2422 // Operand 'ds' requires 4-alignment. 2423 assert((Idisp & 0x3) == 0, "unaligned offset"); 2424 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 2425 __ twi_0($dst$$Register); 2426 __ isync(); 2427 %} 2428 2429 enc_class enc_lfd(RegF dst, memory mem) %{ 2430 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 2431 MacroAssembler _masm(&cbuf); 2432 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2433 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 2434 %} 2435 2436 enc_class enc_load_long_constL(iRegLdst dst, immL src, iRegLdst toc) %{ 2437 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2438 2439 MacroAssembler _masm(&cbuf); 2440 int toc_offset = 0; 2441 2442 if (!ra_->C->in_scratch_emit_size()) { 2443 address const_toc_addr; 2444 // Create a non-oop constant, no relocation needed. 2445 // If it is an IC, it has a virtual_call_Relocation. 2446 const_toc_addr = __ long_constant((jlong)$src$$constant); 2447 if (const_toc_addr == NULL) { 2448 ciEnv::current()->record_out_of_memory_failure(); 2449 return; 2450 } 2451 2452 // Get the constant's TOC offset. 2453 toc_offset = __ offset_to_method_toc(const_toc_addr); 2454 2455 // Keep the current instruction offset in mind. 2456 ((loadConLNode*)this)->_cbuf_insts_offset = __ offset(); 2457 } 2458 2459 __ ld($dst$$Register, toc_offset, $toc$$Register); 2460 %} 2461 2462 enc_class enc_load_long_constL_hi(iRegLdst dst, iRegLdst toc, immL src) %{ 2463 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2464 2465 MacroAssembler _masm(&cbuf); 2466 2467 if (!ra_->C->in_scratch_emit_size()) { 2468 address const_toc_addr; 2469 // Create a non-oop constant, no relocation needed. 2470 // If it is an IC, it has a virtual_call_Relocation. 2471 const_toc_addr = __ long_constant((jlong)$src$$constant); 2472 if (const_toc_addr == NULL) { 2473 ciEnv::current()->record_out_of_memory_failure(); 2474 return; 2475 } 2476 2477 // Get the constant's TOC offset. 2478 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2479 // Store the toc offset of the constant. 2480 ((loadConL_hiNode*)this)->_const_toc_offset = toc_offset; 2481 2482 // Also keep the current instruction offset in mind. 2483 ((loadConL_hiNode*)this)->_cbuf_insts_offset = __ offset(); 2484 } 2485 2486 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2487 %} 2488 2489 %} // encode 2490 2491 source %{ 2492 2493 typedef struct { 2494 loadConL_hiNode *_large_hi; 2495 loadConL_loNode *_large_lo; 2496 loadConLNode *_small; 2497 MachNode *_last; 2498 } loadConLNodesTuple; 2499 2500 loadConLNodesTuple loadConLNodesTuple_create(PhaseRegAlloc *ra_, Node *toc, immLOper *immSrc, 2501 OptoReg::Name reg_second, OptoReg::Name reg_first) { 2502 loadConLNodesTuple nodes; 2503 2504 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2505 if (large_constant_pool) { 2506 // Create new nodes. 2507 loadConL_hiNode *m1 = new loadConL_hiNode(); 2508 loadConL_loNode *m2 = new loadConL_loNode(); 2509 2510 // inputs for new nodes 2511 m1->add_req(NULL, toc); 2512 m2->add_req(NULL, m1); 2513 2514 // operands for new nodes 2515 m1->_opnds[0] = new iRegLdstOper(); // dst 2516 m1->_opnds[1] = immSrc; // src 2517 m1->_opnds[2] = new iRegPdstOper(); // toc 2518 m2->_opnds[0] = new iRegLdstOper(); // dst 2519 m2->_opnds[1] = immSrc; // src 2520 m2->_opnds[2] = new iRegLdstOper(); // base 2521 2522 // Initialize ins_attrib TOC fields. 2523 m1->_const_toc_offset = -1; 2524 m2->_const_toc_offset_hi_node = m1; 2525 2526 // Initialize ins_attrib instruction offset. 2527 m1->_cbuf_insts_offset = -1; 2528 2529 // register allocation for new nodes 2530 ra_->set_pair(m1->_idx, reg_second, reg_first); 2531 ra_->set_pair(m2->_idx, reg_second, reg_first); 2532 2533 // Create result. 2534 nodes._large_hi = m1; 2535 nodes._large_lo = m2; 2536 nodes._small = NULL; 2537 nodes._last = nodes._large_lo; 2538 assert(m2->bottom_type()->isa_long(), "must be long"); 2539 } else { 2540 loadConLNode *m2 = new loadConLNode(); 2541 2542 // inputs for new nodes 2543 m2->add_req(NULL, toc); 2544 2545 // operands for new nodes 2546 m2->_opnds[0] = new iRegLdstOper(); // dst 2547 m2->_opnds[1] = immSrc; // src 2548 m2->_opnds[2] = new iRegPdstOper(); // toc 2549 2550 // Initialize ins_attrib instruction offset. 2551 m2->_cbuf_insts_offset = -1; 2552 2553 // register allocation for new nodes 2554 ra_->set_pair(m2->_idx, reg_second, reg_first); 2555 2556 // Create result. 2557 nodes._large_hi = NULL; 2558 nodes._large_lo = NULL; 2559 nodes._small = m2; 2560 nodes._last = nodes._small; 2561 assert(m2->bottom_type()->isa_long(), "must be long"); 2562 } 2563 2564 return nodes; 2565 } 2566 2567 %} // source 2568 2569 encode %{ 2570 // Postalloc expand emitter for loading a long constant from the method's TOC. 2571 // Enc_class needed as consttanttablebase is not supported by postalloc 2572 // expand. 2573 enc_class postalloc_expand_load_long_constant(iRegLdst dst, immL src, iRegLdst toc) %{ 2574 // Create new nodes. 2575 loadConLNodesTuple loadConLNodes = 2576 loadConLNodesTuple_create(ra_, n_toc, op_src, 2577 ra_->get_reg_second(this), ra_->get_reg_first(this)); 2578 2579 // Push new nodes. 2580 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 2581 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 2582 2583 // some asserts 2584 assert(nodes->length() >= 1, "must have created at least 1 node"); 2585 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 2586 %} 2587 2588 enc_class enc_load_long_constP(iRegLdst dst, immP src, iRegLdst toc) %{ 2589 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 2590 2591 MacroAssembler _masm(&cbuf); 2592 int toc_offset = 0; 2593 2594 if (!ra_->C->in_scratch_emit_size()) { 2595 intptr_t val = $src$$constant; 2596 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2597 address const_toc_addr; 2598 if (constant_reloc == relocInfo::oop_type) { 2599 // Create an oop constant and a corresponding relocation. 2600 AddressLiteral a = __ allocate_oop_address((jobject)val); 2601 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2602 __ relocate(a.rspec()); 2603 } else if (constant_reloc == relocInfo::metadata_type) { 2604 AddressLiteral a = __ constant_metadata_address((Metadata *)val); 2605 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2606 __ relocate(a.rspec()); 2607 } else { 2608 // Create a non-oop constant, no relocation needed. 2609 const_toc_addr = __ long_constant((jlong)$src$$constant); 2610 } 2611 2612 if (const_toc_addr == NULL) { 2613 ciEnv::current()->record_out_of_memory_failure(); 2614 return; 2615 } 2616 // Get the constant's TOC offset. 2617 toc_offset = __ offset_to_method_toc(const_toc_addr); 2618 } 2619 2620 __ ld($dst$$Register, toc_offset, $toc$$Register); 2621 %} 2622 2623 enc_class enc_load_long_constP_hi(iRegLdst dst, immP src, iRegLdst toc) %{ 2624 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 2625 2626 MacroAssembler _masm(&cbuf); 2627 if (!ra_->C->in_scratch_emit_size()) { 2628 intptr_t val = $src$$constant; 2629 relocInfo::relocType constant_reloc = $src->constant_reloc(); // src 2630 address const_toc_addr; 2631 if (constant_reloc == relocInfo::oop_type) { 2632 // Create an oop constant and a corresponding relocation. 2633 AddressLiteral a = __ allocate_oop_address((jobject)val); 2634 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2635 __ relocate(a.rspec()); 2636 } else if (constant_reloc == relocInfo::metadata_type) { 2637 AddressLiteral a = __ constant_metadata_address((Metadata *)val); 2638 const_toc_addr = __ address_constant((address)a.value(), RelocationHolder::none); 2639 __ relocate(a.rspec()); 2640 } else { // non-oop pointers, e.g. card mark base, heap top 2641 // Create a non-oop constant, no relocation needed. 2642 const_toc_addr = __ long_constant((jlong)$src$$constant); 2643 } 2644 2645 if (const_toc_addr == NULL) { 2646 ciEnv::current()->record_out_of_memory_failure(); 2647 return; 2648 } 2649 // Get the constant's TOC offset. 2650 const int toc_offset = __ offset_to_method_toc(const_toc_addr); 2651 // Store the toc offset of the constant. 2652 ((loadConP_hiNode*)this)->_const_toc_offset = toc_offset; 2653 } 2654 2655 __ addis($dst$$Register, $toc$$Register, MacroAssembler::largeoffset_si16_si16_hi(_const_toc_offset)); 2656 %} 2657 2658 // Postalloc expand emitter for loading a ptr constant from the method's TOC. 2659 // Enc_class needed as consttanttablebase is not supported by postalloc 2660 // expand. 2661 enc_class postalloc_expand_load_ptr_constant(iRegPdst dst, immP src, iRegLdst toc) %{ 2662 const bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2663 if (large_constant_pool) { 2664 // Create new nodes. 2665 loadConP_hiNode *m1 = new loadConP_hiNode(); 2666 loadConP_loNode *m2 = new loadConP_loNode(); 2667 2668 // inputs for new nodes 2669 m1->add_req(NULL, n_toc); 2670 m2->add_req(NULL, m1); 2671 2672 // operands for new nodes 2673 m1->_opnds[0] = new iRegPdstOper(); // dst 2674 m1->_opnds[1] = op_src; // src 2675 m1->_opnds[2] = new iRegPdstOper(); // toc 2676 m2->_opnds[0] = new iRegPdstOper(); // dst 2677 m2->_opnds[1] = op_src; // src 2678 m2->_opnds[2] = new iRegLdstOper(); // base 2679 2680 // Initialize ins_attrib TOC fields. 2681 m1->_const_toc_offset = -1; 2682 m2->_const_toc_offset_hi_node = m1; 2683 2684 // Register allocation for new nodes. 2685 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2686 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2687 2688 nodes->push(m1); 2689 nodes->push(m2); 2690 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2691 } else { 2692 loadConPNode *m2 = new loadConPNode(); 2693 2694 // inputs for new nodes 2695 m2->add_req(NULL, n_toc); 2696 2697 // operands for new nodes 2698 m2->_opnds[0] = new iRegPdstOper(); // dst 2699 m2->_opnds[1] = op_src; // src 2700 m2->_opnds[2] = new iRegPdstOper(); // toc 2701 2702 // Register allocation for new nodes. 2703 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2704 2705 nodes->push(m2); 2706 assert(m2->bottom_type()->isa_ptr(), "must be ptr"); 2707 } 2708 %} 2709 2710 // Enc_class needed as consttanttablebase is not supported by postalloc 2711 // expand. 2712 enc_class postalloc_expand_load_float_constant(regF dst, immF src, iRegLdst toc) %{ 2713 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2714 2715 MachNode *m2; 2716 if (large_constant_pool) { 2717 m2 = new loadConFCompNode(); 2718 } else { 2719 m2 = new loadConFNode(); 2720 } 2721 // inputs for new nodes 2722 m2->add_req(NULL, n_toc); 2723 2724 // operands for new nodes 2725 m2->_opnds[0] = op_dst; 2726 m2->_opnds[1] = op_src; 2727 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase 2728 2729 // register allocation for new nodes 2730 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2731 nodes->push(m2); 2732 %} 2733 2734 // Enc_class needed as consttanttablebase is not supported by postalloc 2735 // expand. 2736 enc_class postalloc_expand_load_double_constant(regD dst, immD src, iRegLdst toc) %{ 2737 bool large_constant_pool = true; // TODO: PPC port C->cfg()->_consts_size > 4000; 2738 2739 MachNode *m2; 2740 if (large_constant_pool) { 2741 m2 = new loadConDCompNode(); 2742 } else { 2743 m2 = new loadConDNode(); 2744 } 2745 // inputs for new nodes 2746 m2->add_req(NULL, n_toc); 2747 2748 // operands for new nodes 2749 m2->_opnds[0] = op_dst; 2750 m2->_opnds[1] = op_src; 2751 m2->_opnds[2] = new iRegPdstOper(); // constanttablebase 2752 2753 // register allocation for new nodes 2754 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2755 nodes->push(m2); 2756 %} 2757 2758 enc_class enc_stw(iRegIsrc src, memory mem) %{ 2759 // TODO: PPC port $archOpcode(ppc64Opcode_stw); 2760 MacroAssembler _masm(&cbuf); 2761 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2762 __ stw($src$$Register, Idisp, $mem$$base$$Register); 2763 %} 2764 2765 enc_class enc_std(iRegIsrc src, memoryAlg4 mem) %{ 2766 // TODO: PPC port $archOpcode(ppc64Opcode_std); 2767 MacroAssembler _masm(&cbuf); 2768 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2769 // Operand 'ds' requires 4-alignment. 2770 assert((Idisp & 0x3) == 0, "unaligned offset"); 2771 __ std($src$$Register, Idisp, $mem$$base$$Register); 2772 %} 2773 2774 enc_class enc_stfs(RegF src, memory mem) %{ 2775 // TODO: PPC port $archOpcode(ppc64Opcode_stfs); 2776 MacroAssembler _masm(&cbuf); 2777 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2778 __ stfs($src$$FloatRegister, Idisp, $mem$$base$$Register); 2779 %} 2780 2781 enc_class enc_stfd(RegF src, memory mem) %{ 2782 // TODO: PPC port $archOpcode(ppc64Opcode_stfd); 2783 MacroAssembler _masm(&cbuf); 2784 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 2785 __ stfd($src$$FloatRegister, Idisp, $mem$$base$$Register); 2786 %} 2787 2788 // Use release_store for card-marking to ensure that previous 2789 // oop-stores are visible before the card-mark change. 2790 enc_class enc_cms_card_mark(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{ 2791 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 2792 // FIXME: Implement this as a cmove and use a fixed condition code 2793 // register which is written on every transition to compiled code, 2794 // e.g. in call-stub and when returning from runtime stubs. 2795 // 2796 // Proposed code sequence for the cmove implementation: 2797 // 2798 // Label skip_release; 2799 // __ beq(CCRfixed, skip_release); 2800 // __ release(); 2801 // __ bind(skip_release); 2802 // __ stb(card mark); 2803 2804 MacroAssembler _masm(&cbuf); 2805 Label skip_storestore; 2806 2807 #if 0 // TODO: PPC port 2808 // Check CMSCollectorCardTableModRefBSExt::_requires_release and do the 2809 // StoreStore barrier conditionally. 2810 __ lwz(R0, 0, $releaseFieldAddr$$Register); 2811 __ cmpwi($crx$$CondRegister, R0, 0); 2812 __ beq_predict_taken($crx$$CondRegister, skip_storestore); 2813 #endif 2814 __ li(R0, 0); 2815 __ membar(Assembler::StoreStore); 2816 #if 0 // TODO: PPC port 2817 __ bind(skip_storestore); 2818 #endif 2819 2820 // Do the store. 2821 if ($mem$$index == 0) { 2822 __ stb(R0, $mem$$disp, $mem$$base$$Register); 2823 } else { 2824 assert(0 == $mem$$disp, "no displacement possible with indexed load/stores on ppc"); 2825 __ stbx(R0, $mem$$base$$Register, $mem$$index$$Register); 2826 } 2827 %} 2828 2829 enc_class postalloc_expand_encode_oop(iRegNdst dst, iRegPdst src, flagsReg crx) %{ 2830 2831 if (VM_Version::has_isel()) { 2832 // use isel instruction with Power 7 2833 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node(); 2834 encodeP_subNode *n_sub_base = new encodeP_subNode(); 2835 encodeP_shiftNode *n_shift = new encodeP_shiftNode(); 2836 cond_set_0_oopNode *n_cond_set = new cond_set_0_oopNode(); 2837 2838 n_compare->add_req(n_region, n_src); 2839 n_compare->_opnds[0] = op_crx; 2840 n_compare->_opnds[1] = op_src; 2841 n_compare->_opnds[2] = new immL16Oper(0); 2842 2843 n_sub_base->add_req(n_region, n_src); 2844 n_sub_base->_opnds[0] = op_dst; 2845 n_sub_base->_opnds[1] = op_src; 2846 n_sub_base->_bottom_type = _bottom_type; 2847 2848 n_shift->add_req(n_region, n_sub_base); 2849 n_shift->_opnds[0] = op_dst; 2850 n_shift->_opnds[1] = op_dst; 2851 n_shift->_bottom_type = _bottom_type; 2852 2853 n_cond_set->add_req(n_region, n_compare, n_shift); 2854 n_cond_set->_opnds[0] = op_dst; 2855 n_cond_set->_opnds[1] = op_crx; 2856 n_cond_set->_opnds[2] = op_dst; 2857 n_cond_set->_bottom_type = _bottom_type; 2858 2859 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2860 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2861 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2862 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2863 2864 nodes->push(n_compare); 2865 nodes->push(n_sub_base); 2866 nodes->push(n_shift); 2867 nodes->push(n_cond_set); 2868 2869 } else { 2870 // before Power 7 2871 moveRegNode *n_move = new moveRegNode(); 2872 cmpP_reg_imm16Node *n_compare = new cmpP_reg_imm16Node(); 2873 encodeP_shiftNode *n_shift = new encodeP_shiftNode(); 2874 cond_sub_baseNode *n_sub_base = new cond_sub_baseNode(); 2875 2876 n_move->add_req(n_region, n_src); 2877 n_move->_opnds[0] = op_dst; 2878 n_move->_opnds[1] = op_src; 2879 ra_->set_oop(n_move, true); // Until here, 'n_move' still produces an oop. 2880 2881 n_compare->add_req(n_region, n_src); 2882 n_compare->add_prec(n_move); 2883 2884 n_compare->_opnds[0] = op_crx; 2885 n_compare->_opnds[1] = op_src; 2886 n_compare->_opnds[2] = new immL16Oper(0); 2887 2888 n_sub_base->add_req(n_region, n_compare, n_src); 2889 n_sub_base->_opnds[0] = op_dst; 2890 n_sub_base->_opnds[1] = op_crx; 2891 n_sub_base->_opnds[2] = op_src; 2892 n_sub_base->_bottom_type = _bottom_type; 2893 2894 n_shift->add_req(n_region, n_sub_base); 2895 n_shift->_opnds[0] = op_dst; 2896 n_shift->_opnds[1] = op_dst; 2897 n_shift->_bottom_type = _bottom_type; 2898 2899 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2900 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2901 ra_->set_pair(n_sub_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2902 ra_->set_pair(n_move->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2903 2904 nodes->push(n_move); 2905 nodes->push(n_compare); 2906 nodes->push(n_sub_base); 2907 nodes->push(n_shift); 2908 } 2909 2910 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 2911 %} 2912 2913 enc_class postalloc_expand_encode_oop_not_null(iRegNdst dst, iRegPdst src) %{ 2914 2915 encodeP_subNode *n1 = new encodeP_subNode(); 2916 n1->add_req(n_region, n_src); 2917 n1->_opnds[0] = op_dst; 2918 n1->_opnds[1] = op_src; 2919 n1->_bottom_type = _bottom_type; 2920 2921 encodeP_shiftNode *n2 = new encodeP_shiftNode(); 2922 n2->add_req(n_region, n1); 2923 n2->_opnds[0] = op_dst; 2924 n2->_opnds[1] = op_dst; 2925 n2->_bottom_type = _bottom_type; 2926 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2927 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2928 2929 nodes->push(n1); 2930 nodes->push(n2); 2931 assert(!(ra_->is_oop(this)), "sanity"); // This is not supposed to be GC'ed. 2932 %} 2933 2934 enc_class postalloc_expand_decode_oop(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 2935 decodeN_shiftNode *n_shift = new decodeN_shiftNode(); 2936 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node(); 2937 2938 n_compare->add_req(n_region, n_src); 2939 n_compare->_opnds[0] = op_crx; 2940 n_compare->_opnds[1] = op_src; 2941 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR); 2942 2943 n_shift->add_req(n_region, n_src); 2944 n_shift->_opnds[0] = op_dst; 2945 n_shift->_opnds[1] = op_src; 2946 n_shift->_bottom_type = _bottom_type; 2947 2948 if (VM_Version::has_isel()) { 2949 // use isel instruction with Power 7 2950 2951 decodeN_addNode *n_add_base = new decodeN_addNode(); 2952 n_add_base->add_req(n_region, n_shift); 2953 n_add_base->_opnds[0] = op_dst; 2954 n_add_base->_opnds[1] = op_dst; 2955 n_add_base->_bottom_type = _bottom_type; 2956 2957 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode(); 2958 n_cond_set->add_req(n_region, n_compare, n_add_base); 2959 n_cond_set->_opnds[0] = op_dst; 2960 n_cond_set->_opnds[1] = op_crx; 2961 n_cond_set->_opnds[2] = op_dst; 2962 n_cond_set->_bottom_type = _bottom_type; 2963 2964 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 2965 ra_->set_oop(n_cond_set, true); 2966 2967 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2968 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2969 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2970 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2971 2972 nodes->push(n_compare); 2973 nodes->push(n_shift); 2974 nodes->push(n_add_base); 2975 nodes->push(n_cond_set); 2976 2977 } else { 2978 // before Power 7 2979 cond_add_baseNode *n_add_base = new cond_add_baseNode(); 2980 2981 n_add_base->add_req(n_region, n_compare, n_shift); 2982 n_add_base->_opnds[0] = op_dst; 2983 n_add_base->_opnds[1] = op_crx; 2984 n_add_base->_opnds[2] = op_dst; 2985 n_add_base->_bottom_type = _bottom_type; 2986 2987 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 2988 ra_->set_oop(n_add_base, true); 2989 2990 ra_->set_pair(n_shift->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2991 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 2992 ra_->set_pair(n_add_base->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 2993 2994 nodes->push(n_compare); 2995 nodes->push(n_shift); 2996 nodes->push(n_add_base); 2997 } 2998 %} 2999 3000 enc_class postalloc_expand_decode_oop_not_null(iRegPdst dst, iRegNsrc src) %{ 3001 decodeN_shiftNode *n1 = new decodeN_shiftNode(); 3002 n1->add_req(n_region, n_src); 3003 n1->_opnds[0] = op_dst; 3004 n1->_opnds[1] = op_src; 3005 n1->_bottom_type = _bottom_type; 3006 3007 decodeN_addNode *n2 = new decodeN_addNode(); 3008 n2->add_req(n_region, n1); 3009 n2->_opnds[0] = op_dst; 3010 n2->_opnds[1] = op_dst; 3011 n2->_bottom_type = _bottom_type; 3012 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3013 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 3014 3015 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 3016 ra_->set_oop(n2, true); 3017 3018 nodes->push(n1); 3019 nodes->push(n2); 3020 %} 3021 3022 enc_class enc_cmove_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src, cmpOp cmp) %{ 3023 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3024 3025 MacroAssembler _masm(&cbuf); 3026 int cc = $cmp$$cmpcode; 3027 int flags_reg = $crx$$reg; 3028 Label done; 3029 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3030 // Branch if not (cmp crx). 3031 __ bc(cc_to_inverse_boint(cc), cc_to_biint(cc, flags_reg), done); 3032 __ mr($dst$$Register, $src$$Register); 3033 // TODO PPC port __ endgroup_if_needed(_size == 12); 3034 __ bind(done); 3035 %} 3036 3037 enc_class enc_cmove_imm(iRegIdst dst, flagsRegSrc crx, immI16 src, cmpOp cmp) %{ 3038 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3039 3040 MacroAssembler _masm(&cbuf); 3041 Label done; 3042 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3043 // Branch if not (cmp crx). 3044 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 3045 __ li($dst$$Register, $src$$constant); 3046 // TODO PPC port __ endgroup_if_needed(_size == 12); 3047 __ bind(done); 3048 %} 3049 3050 // New atomics. 3051 enc_class enc_GetAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3052 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3053 3054 MacroAssembler _masm(&cbuf); 3055 Register Rtmp = R0; 3056 Register Rres = $res$$Register; 3057 Register Rsrc = $src$$Register; 3058 Register Rptr = $mem_ptr$$Register; 3059 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3060 Register Rold = RegCollision ? Rtmp : Rres; 3061 3062 Label Lretry; 3063 __ bind(Lretry); 3064 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3065 __ add(Rtmp, Rsrc, Rold); 3066 __ stwcx_(Rtmp, Rptr); 3067 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3068 __ bne_predict_not_taken(CCR0, Lretry); 3069 } else { 3070 __ bne( CCR0, Lretry); 3071 } 3072 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3073 __ fence(); 3074 %} 3075 3076 enc_class enc_GetAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3077 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3078 3079 MacroAssembler _masm(&cbuf); 3080 Register Rtmp = R0; 3081 Register Rres = $res$$Register; 3082 Register Rsrc = $src$$Register; 3083 Register Rptr = $mem_ptr$$Register; 3084 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3085 Register Rold = RegCollision ? Rtmp : Rres; 3086 3087 Label Lretry; 3088 __ bind(Lretry); 3089 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3090 __ add(Rtmp, Rsrc, Rold); 3091 __ stdcx_(Rtmp, Rptr); 3092 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3093 __ bne_predict_not_taken(CCR0, Lretry); 3094 } else { 3095 __ bne( CCR0, Lretry); 3096 } 3097 if (RegCollision) __ subf(Rres, Rsrc, Rtmp); 3098 __ fence(); 3099 %} 3100 3101 enc_class enc_GetAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src) %{ 3102 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3103 3104 MacroAssembler _masm(&cbuf); 3105 Register Rtmp = R0; 3106 Register Rres = $res$$Register; 3107 Register Rsrc = $src$$Register; 3108 Register Rptr = $mem_ptr$$Register; 3109 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3110 Register Rold = RegCollision ? Rtmp : Rres; 3111 3112 Label Lretry; 3113 __ bind(Lretry); 3114 __ lwarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3115 __ stwcx_(Rsrc, Rptr); 3116 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3117 __ bne_predict_not_taken(CCR0, Lretry); 3118 } else { 3119 __ bne( CCR0, Lretry); 3120 } 3121 if (RegCollision) __ mr(Rres, Rtmp); 3122 __ fence(); 3123 %} 3124 3125 enc_class enc_GetAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src) %{ 3126 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3127 3128 MacroAssembler _masm(&cbuf); 3129 Register Rtmp = R0; 3130 Register Rres = $res$$Register; 3131 Register Rsrc = $src$$Register; 3132 Register Rptr = $mem_ptr$$Register; 3133 bool RegCollision = (Rres == Rsrc) || (Rres == Rptr); 3134 Register Rold = RegCollision ? Rtmp : Rres; 3135 3136 Label Lretry; 3137 __ bind(Lretry); 3138 __ ldarx(Rold, Rptr, MacroAssembler::cmpxchgx_hint_atomic_update()); 3139 __ stdcx_(Rsrc, Rptr); 3140 if (UseStaticBranchPredictionInCompareAndSwapPPC64) { 3141 __ bne_predict_not_taken(CCR0, Lretry); 3142 } else { 3143 __ bne( CCR0, Lretry); 3144 } 3145 if (RegCollision) __ mr(Rres, Rtmp); 3146 __ fence(); 3147 %} 3148 3149 // This enc_class is needed so that scheduler gets proper 3150 // input mapping for latency computation. 3151 enc_class enc_andc(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 3152 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 3153 MacroAssembler _masm(&cbuf); 3154 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 3155 %} 3156 3157 enc_class enc_convI2B_regI__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3158 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3159 3160 MacroAssembler _masm(&cbuf); 3161 3162 Label done; 3163 __ cmpwi($crx$$CondRegister, $src$$Register, 0); 3164 __ li($dst$$Register, $zero$$constant); 3165 __ beq($crx$$CondRegister, done); 3166 __ li($dst$$Register, $notzero$$constant); 3167 __ bind(done); 3168 %} 3169 3170 enc_class enc_convP2B_regP__cmove(iRegIdst dst, iRegPsrc src, flagsReg crx, immI16 zero, immI16 notzero) %{ 3171 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3172 3173 MacroAssembler _masm(&cbuf); 3174 3175 Label done; 3176 __ cmpdi($crx$$CondRegister, $src$$Register, 0); 3177 __ li($dst$$Register, $zero$$constant); 3178 __ beq($crx$$CondRegister, done); 3179 __ li($dst$$Register, $notzero$$constant); 3180 __ bind(done); 3181 %} 3182 3183 enc_class enc_cmove_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL mem ) %{ 3184 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 3185 3186 MacroAssembler _masm(&cbuf); 3187 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 3188 Label done; 3189 __ bso($crx$$CondRegister, done); 3190 __ ld($dst$$Register, Idisp, $mem$$base$$Register); 3191 // TODO PPC port __ endgroup_if_needed(_size == 12); 3192 __ bind(done); 3193 %} 3194 3195 enc_class enc_bc(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3196 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3197 3198 MacroAssembler _masm(&cbuf); 3199 Label d; // dummy 3200 __ bind(d); 3201 Label* p = ($lbl$$label); 3202 // `p' is `NULL' when this encoding class is used only to 3203 // determine the size of the encoded instruction. 3204 Label& l = (NULL == p)? d : *(p); 3205 int cc = $cmp$$cmpcode; 3206 int flags_reg = $crx$$reg; 3207 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 3208 int bhint = Assembler::bhintNoHint; 3209 3210 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3211 if (_prob <= PROB_NEVER) { 3212 bhint = Assembler::bhintIsNotTaken; 3213 } else if (_prob >= PROB_ALWAYS) { 3214 bhint = Assembler::bhintIsTaken; 3215 } 3216 } 3217 3218 __ bc(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3219 cc_to_biint(cc, flags_reg), 3220 l); 3221 %} 3222 3223 enc_class enc_bc_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3224 // The scheduler doesn't know about branch shortening, so we set the opcode 3225 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3226 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3227 3228 MacroAssembler _masm(&cbuf); 3229 Label d; // dummy 3230 __ bind(d); 3231 Label* p = ($lbl$$label); 3232 // `p' is `NULL' when this encoding class is used only to 3233 // determine the size of the encoded instruction. 3234 Label& l = (NULL == p)? d : *(p); 3235 int cc = $cmp$$cmpcode; 3236 int flags_reg = $crx$$reg; 3237 int bhint = Assembler::bhintNoHint; 3238 3239 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3240 if (_prob <= PROB_NEVER) { 3241 bhint = Assembler::bhintIsNotTaken; 3242 } else if (_prob >= PROB_ALWAYS) { 3243 bhint = Assembler::bhintIsTaken; 3244 } 3245 } 3246 3247 // Tell the conditional far branch to optimize itself when being relocated. 3248 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3249 cc_to_biint(cc, flags_reg), 3250 l, 3251 MacroAssembler::bc_far_optimize_on_relocate); 3252 %} 3253 3254 // Branch used with Power6 scheduling (can be shortened without changing the node). 3255 enc_class enc_bc_short_far(flagsRegSrc crx, cmpOp cmp, Label lbl) %{ 3256 // The scheduler doesn't know about branch shortening, so we set the opcode 3257 // to ppc64Opcode_bc in order to hide this detail from the scheduler. 3258 // TODO: PPC port $archOpcode(ppc64Opcode_bc); 3259 3260 MacroAssembler _masm(&cbuf); 3261 Label d; // dummy 3262 __ bind(d); 3263 Label* p = ($lbl$$label); 3264 // `p' is `NULL' when this encoding class is used only to 3265 // determine the size of the encoded instruction. 3266 Label& l = (NULL == p)? d : *(p); 3267 int cc = $cmp$$cmpcode; 3268 int flags_reg = $crx$$reg; 3269 int bhint = Assembler::bhintNoHint; 3270 3271 if (UseStaticBranchPredictionForUncommonPathsPPC64) { 3272 if (_prob <= PROB_NEVER) { 3273 bhint = Assembler::bhintIsNotTaken; 3274 } else if (_prob >= PROB_ALWAYS) { 3275 bhint = Assembler::bhintIsTaken; 3276 } 3277 } 3278 3279 #if 0 // TODO: PPC port 3280 if (_size == 8) { 3281 // Tell the conditional far branch to optimize itself when being relocated. 3282 __ bc_far(Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3283 cc_to_biint(cc, flags_reg), 3284 l, 3285 MacroAssembler::bc_far_optimize_on_relocate); 3286 } else { 3287 __ bc (Assembler::add_bhint_to_boint(bhint, cc_to_boint(cc)), 3288 cc_to_biint(cc, flags_reg), 3289 l); 3290 } 3291 #endif 3292 Unimplemented(); 3293 %} 3294 3295 // Postalloc expand emitter for loading a replicatef float constant from 3296 // the method's TOC. 3297 // Enc_class needed as consttanttablebase is not supported by postalloc 3298 // expand. 3299 enc_class postalloc_expand_load_replF_constant(iRegLdst dst, immF src, iRegLdst toc) %{ 3300 // Create new nodes. 3301 3302 // Make an operand with the bit pattern to load as float. 3303 immLOper *op_repl = new immLOper((jlong)replicate_immF(op_src->constantF())); 3304 3305 loadConLNodesTuple loadConLNodes = 3306 loadConLNodesTuple_create(ra_, n_toc, op_repl, 3307 ra_->get_reg_second(this), ra_->get_reg_first(this)); 3308 3309 // Push new nodes. 3310 if (loadConLNodes._large_hi) nodes->push(loadConLNodes._large_hi); 3311 if (loadConLNodes._last) nodes->push(loadConLNodes._last); 3312 3313 assert(nodes->length() >= 1, "must have created at least 1 node"); 3314 assert(loadConLNodes._last->bottom_type()->isa_long(), "must be long"); 3315 %} 3316 3317 // This enc_class is needed so that scheduler gets proper 3318 // input mapping for latency computation. 3319 enc_class enc_poll(immI dst, iRegLdst poll) %{ 3320 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 3321 // Fake operand dst needed for PPC scheduler. 3322 assert($dst$$constant == 0x0, "dst must be 0x0"); 3323 3324 MacroAssembler _masm(&cbuf); 3325 // Mark the code position where the load from the safepoint 3326 // polling page was emitted as relocInfo::poll_type. 3327 __ relocate(relocInfo::poll_type); 3328 __ load_from_polling_page($poll$$Register); 3329 %} 3330 3331 // A Java static call or a runtime call. 3332 // 3333 // Branch-and-link relative to a trampoline. 3334 // The trampoline loads the target address and does a long branch to there. 3335 // In case we call java, the trampoline branches to a interpreter_stub 3336 // which loads the inline cache and the real call target from the constant pool. 3337 // 3338 // This basically looks like this: 3339 // 3340 // >>>> consts -+ -+ 3341 // | |- offset1 3342 // [call target1] | <-+ 3343 // [IC cache] |- offset2 3344 // [call target2] <--+ 3345 // 3346 // <<<< consts 3347 // >>>> insts 3348 // 3349 // bl offset16 -+ -+ ??? // How many bits available? 3350 // | | 3351 // <<<< insts | | 3352 // >>>> stubs | | 3353 // | |- trampoline_stub_Reloc 3354 // trampoline stub: | <-+ 3355 // r2 = toc | 3356 // r2 = [r2 + offset1] | // Load call target1 from const section 3357 // mtctr r2 | 3358 // bctr |- static_stub_Reloc 3359 // comp_to_interp_stub: <---+ 3360 // r1 = toc 3361 // ICreg = [r1 + IC_offset] // Load IC from const section 3362 // r1 = [r1 + offset2] // Load call target2 from const section 3363 // mtctr r1 3364 // bctr 3365 // 3366 // <<<< stubs 3367 // 3368 // The call instruction in the code either 3369 // - Branches directly to a compiled method if the offset is encodable in instruction. 3370 // - Branches to the trampoline stub if the offset to the compiled method is not encodable. 3371 // - Branches to the compiled_to_interp stub if the target is interpreted. 3372 // 3373 // Further there are three relocations from the loads to the constants in 3374 // the constant section. 3375 // 3376 // Usage of r1 and r2 in the stubs allows to distinguish them. 3377 enc_class enc_java_static_call(method meth) %{ 3378 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3379 3380 MacroAssembler _masm(&cbuf); 3381 address entry_point = (address)$meth$$method; 3382 3383 if (!_method) { 3384 // A call to a runtime wrapper, e.g. new, new_typeArray_Java, uncommon_trap. 3385 emit_call_with_trampoline_stub(_masm, entry_point, relocInfo::runtime_call_type); 3386 } else { 3387 // Remember the offset not the address. 3388 const int start_offset = __ offset(); 3389 // The trampoline stub. 3390 if (!Compile::current()->in_scratch_emit_size()) { 3391 // No entry point given, use the current pc. 3392 // Make sure branch fits into 3393 if (entry_point == 0) entry_point = __ pc(); 3394 3395 // Put the entry point as a constant into the constant pool. 3396 const address entry_point_toc_addr = __ address_constant(entry_point, RelocationHolder::none); 3397 if (entry_point_toc_addr == NULL) { 3398 ciEnv::current()->record_out_of_memory_failure(); 3399 return; 3400 } 3401 const int entry_point_toc_offset = __ offset_to_method_toc(entry_point_toc_addr); 3402 3403 3404 // Emit the trampoline stub which will be related to the branch-and-link below. 3405 CallStubImpl::emit_trampoline_stub(_masm, entry_point_toc_offset, start_offset); 3406 if (ciEnv::current()->failing()) { return; } // Code cache may be full. 3407 int method_index = resolved_method_index(cbuf); 3408 __ relocate(_optimized_virtual ? opt_virtual_call_Relocation::spec(method_index) 3409 : static_call_Relocation::spec(method_index)); 3410 } 3411 3412 // The real call. 3413 // Note: At this point we do not have the address of the trampoline 3414 // stub, and the entry point might be too far away for bl, so __ pc() 3415 // serves as dummy and the bl will be patched later. 3416 cbuf.set_insts_mark(); 3417 __ bl(__ pc()); // Emits a relocation. 3418 3419 // The stub for call to interpreter. 3420 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf); 3421 if (stub == NULL) { 3422 ciEnv::current()->record_failure("CodeCache is full"); 3423 return; 3424 } 3425 } 3426 %} 3427 3428 // Second node of expanded dynamic call - the call. 3429 enc_class enc_java_dynamic_call_sched(method meth) %{ 3430 // TODO: PPC port $archOpcode(ppc64Opcode_bl); 3431 3432 MacroAssembler _masm(&cbuf); 3433 3434 if (!ra_->C->in_scratch_emit_size()) { 3435 // Create a call trampoline stub for the given method. 3436 const address entry_point = !($meth$$method) ? 0 : (address)$meth$$method; 3437 const address entry_point_const = __ address_constant(entry_point, RelocationHolder::none); 3438 if (entry_point_const == NULL) { 3439 ciEnv::current()->record_out_of_memory_failure(); 3440 return; 3441 } 3442 const int entry_point_const_toc_offset = __ offset_to_method_toc(entry_point_const); 3443 CallStubImpl::emit_trampoline_stub(_masm, entry_point_const_toc_offset, __ offset()); 3444 if (ra_->C->env()->failing()) { return; } // Code cache may be full. 3445 3446 // Build relocation at call site with ic position as data. 3447 assert((_load_ic_hi_node != NULL && _load_ic_node == NULL) || 3448 (_load_ic_hi_node == NULL && _load_ic_node != NULL), 3449 "must have one, but can't have both"); 3450 assert((_load_ic_hi_node != NULL && _load_ic_hi_node->_cbuf_insts_offset != -1) || 3451 (_load_ic_node != NULL && _load_ic_node->_cbuf_insts_offset != -1), 3452 "must contain instruction offset"); 3453 const int virtual_call_oop_addr_offset = _load_ic_hi_node != NULL 3454 ? _load_ic_hi_node->_cbuf_insts_offset 3455 : _load_ic_node->_cbuf_insts_offset; 3456 const address virtual_call_oop_addr = __ addr_at(virtual_call_oop_addr_offset); 3457 assert(MacroAssembler::is_load_const_from_method_toc_at(virtual_call_oop_addr), 3458 "should be load from TOC"); 3459 int method_index = resolved_method_index(cbuf); 3460 __ relocate(virtual_call_Relocation::spec(virtual_call_oop_addr, method_index)); 3461 } 3462 3463 // At this point I do not have the address of the trampoline stub, 3464 // and the entry point might be too far away for bl. Pc() serves 3465 // as dummy and bl will be patched later. 3466 __ bl((address) __ pc()); 3467 %} 3468 3469 // postalloc expand emitter for virtual calls. 3470 enc_class postalloc_expand_java_dynamic_call_sched(method meth, iRegLdst toc) %{ 3471 3472 // Create the nodes for loading the IC from the TOC. 3473 loadConLNodesTuple loadConLNodes_IC = 3474 loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong)Universe::non_oop_word()), 3475 OptoReg::Name(R19_H_num), OptoReg::Name(R19_num)); 3476 3477 // Create the call node. 3478 CallDynamicJavaDirectSchedNode *call = new CallDynamicJavaDirectSchedNode(); 3479 call->_method_handle_invoke = _method_handle_invoke; 3480 call->_vtable_index = _vtable_index; 3481 call->_method = _method; 3482 call->_bci = _bci; 3483 call->_optimized_virtual = _optimized_virtual; 3484 call->_tf = _tf; 3485 call->_entry_point = _entry_point; 3486 call->_cnt = _cnt; 3487 call->_argsize = _argsize; 3488 call->_oop_map = _oop_map; 3489 call->_jvms = _jvms; 3490 call->_jvmadj = _jvmadj; 3491 call->_in_rms = _in_rms; 3492 call->_nesting = _nesting; 3493 call->_override_symbolic_info = _override_symbolic_info; 3494 3495 // New call needs all inputs of old call. 3496 // Req... 3497 for (uint i = 0; i < req(); ++i) { 3498 // The expanded node does not need toc any more. 3499 // Add the inline cache constant here instead. This expresses the 3500 // register of the inline cache must be live at the call. 3501 // Else we would have to adapt JVMState by -1. 3502 if (i == mach_constant_base_node_input()) { 3503 call->add_req(loadConLNodes_IC._last); 3504 } else { 3505 call->add_req(in(i)); 3506 } 3507 } 3508 // ...as well as prec 3509 for (uint i = req(); i < len(); ++i) { 3510 call->add_prec(in(i)); 3511 } 3512 3513 // Remember nodes loading the inline cache into r19. 3514 call->_load_ic_hi_node = loadConLNodes_IC._large_hi; 3515 call->_load_ic_node = loadConLNodes_IC._small; 3516 3517 // Operands for new nodes. 3518 call->_opnds[0] = _opnds[0]; 3519 call->_opnds[1] = _opnds[1]; 3520 3521 // Only the inline cache is associated with a register. 3522 assert(Matcher::inline_cache_reg() == OptoReg::Name(R19_num), "ic reg should be R19"); 3523 3524 // Push new nodes. 3525 if (loadConLNodes_IC._large_hi) nodes->push(loadConLNodes_IC._large_hi); 3526 if (loadConLNodes_IC._last) nodes->push(loadConLNodes_IC._last); 3527 nodes->push(call); 3528 %} 3529 3530 // Compound version of call dynamic 3531 // Toc is only passed so that it can be used in ins_encode statement. 3532 // In the code we have to use $constanttablebase. 3533 enc_class enc_java_dynamic_call(method meth, iRegLdst toc) %{ 3534 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3535 MacroAssembler _masm(&cbuf); 3536 int start_offset = __ offset(); 3537 3538 Register Rtoc = (ra_) ? $constanttablebase : R2_TOC; 3539 #if 0 3540 int vtable_index = this->_vtable_index; 3541 if (_vtable_index < 0) { 3542 // Must be invalid_vtable_index, not nonvirtual_vtable_index. 3543 assert(_vtable_index == Method::invalid_vtable_index, "correct sentinel value"); 3544 Register ic_reg = as_Register(Matcher::inline_cache_reg_encode()); 3545 3546 // Virtual call relocation will point to ic load. 3547 address virtual_call_meta_addr = __ pc(); 3548 // Load a clear inline cache. 3549 AddressLiteral empty_ic((address) Universe::non_oop_word()); 3550 bool success = __ load_const_from_method_toc(ic_reg, empty_ic, Rtoc, /*fixed_size*/ true); 3551 if (!success) { 3552 ciEnv::current()->record_out_of_memory_failure(); 3553 return; 3554 } 3555 // CALL to fixup routine. Fixup routine uses ScopeDesc info 3556 // to determine who we intended to call. 3557 __ relocate(virtual_call_Relocation::spec(virtual_call_meta_addr)); 3558 emit_call_with_trampoline_stub(_masm, (address)$meth$$method, relocInfo::none); 3559 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3560 "Fix constant in ret_addr_offset()"); 3561 } else { 3562 assert(!UseInlineCaches, "expect vtable calls only if not using ICs"); 3563 // Go thru the vtable. Get receiver klass. Receiver already 3564 // checked for non-null. If we'll go thru a C2I adapter, the 3565 // interpreter expects method in R19_method. 3566 3567 __ load_klass(R11_scratch1, R3); 3568 3569 int entry_offset = in_bytes(Klass::vtable_start_offset()) + _vtable_index * vtableEntry::size_in_bytes(); 3570 int v_off = entry_offset + vtableEntry::method_offset_in_bytes(); 3571 __ li(R19_method, v_off); 3572 __ ldx(R19_method/*method oop*/, R19_method/*method offset*/, R11_scratch1/*class*/); 3573 // NOTE: for vtable dispatches, the vtable entry will never be 3574 // null. However it may very well end up in handle_wrong_method 3575 // if the method is abstract for the particular class. 3576 __ ld(R11_scratch1, in_bytes(Method::from_compiled_offset()), R19_method); 3577 // Call target. Either compiled code or C2I adapter. 3578 __ mtctr(R11_scratch1); 3579 __ bctrl(); 3580 if (((MachCallDynamicJavaNode*)this)->ret_addr_offset() != __ offset() - start_offset) { 3581 tty->print(" %d, %d\n", ((MachCallDynamicJavaNode*)this)->ret_addr_offset(),__ offset() - start_offset); 3582 } 3583 assert(((MachCallDynamicJavaNode*)this)->ret_addr_offset() == __ offset() - start_offset, 3584 "Fix constant in ret_addr_offset()"); 3585 } 3586 #endif 3587 Unimplemented(); // ret_addr_offset not yet fixed. Depends on compressed oops (load klass!). 3588 %} 3589 3590 // a runtime call 3591 enc_class enc_java_to_runtime_call (method meth) %{ 3592 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 3593 3594 MacroAssembler _masm(&cbuf); 3595 const address start_pc = __ pc(); 3596 3597 #if defined(ABI_ELFv2) 3598 address entry= !($meth$$method) ? NULL : (address)$meth$$method; 3599 __ call_c(entry, relocInfo::runtime_call_type); 3600 #else 3601 // The function we're going to call. 3602 FunctionDescriptor fdtemp; 3603 const FunctionDescriptor* fd = !($meth$$method) ? &fdtemp : (FunctionDescriptor*)$meth$$method; 3604 3605 Register Rtoc = R12_scratch2; 3606 // Calculate the method's TOC. 3607 __ calculate_address_from_global_toc(Rtoc, __ method_toc()); 3608 // Put entry, env, toc into the constant pool, this needs up to 3 constant 3609 // pool entries; call_c_using_toc will optimize the call. 3610 bool success = __ call_c_using_toc(fd, relocInfo::runtime_call_type, Rtoc); 3611 if (!success) { 3612 ciEnv::current()->record_out_of_memory_failure(); 3613 return; 3614 } 3615 #endif 3616 3617 // Check the ret_addr_offset. 3618 assert(((MachCallRuntimeNode*)this)->ret_addr_offset() == __ last_calls_return_pc() - start_pc, 3619 "Fix constant in ret_addr_offset()"); 3620 %} 3621 3622 // Move to ctr for leaf call. 3623 // This enc_class is needed so that scheduler gets proper 3624 // input mapping for latency computation. 3625 enc_class enc_leaf_call_mtctr(iRegLsrc src) %{ 3626 // TODO: PPC port $archOpcode(ppc64Opcode_mtctr); 3627 MacroAssembler _masm(&cbuf); 3628 __ mtctr($src$$Register); 3629 %} 3630 3631 // Postalloc expand emitter for runtime leaf calls. 3632 enc_class postalloc_expand_java_to_runtime_call(method meth, iRegLdst toc) %{ 3633 loadConLNodesTuple loadConLNodes_Entry; 3634 #if defined(ABI_ELFv2) 3635 jlong entry_address = (jlong) this->entry_point(); 3636 assert(entry_address, "need address here"); 3637 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address), 3638 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3639 #else 3640 // Get the struct that describes the function we are about to call. 3641 FunctionDescriptor* fd = (FunctionDescriptor*) this->entry_point(); 3642 assert(fd, "need fd here"); 3643 jlong entry_address = (jlong) fd->entry(); 3644 // new nodes 3645 loadConLNodesTuple loadConLNodes_Env; 3646 loadConLNodesTuple loadConLNodes_Toc; 3647 3648 // Create nodes and operands for loading the entry point. 3649 loadConLNodes_Entry = loadConLNodesTuple_create(ra_, n_toc, new immLOper(entry_address), 3650 OptoReg::Name(R12_H_num), OptoReg::Name(R12_num)); 3651 3652 3653 // Create nodes and operands for loading the env pointer. 3654 if (fd->env() != NULL) { 3655 loadConLNodes_Env = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->env()), 3656 OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3657 } else { 3658 loadConLNodes_Env._large_hi = NULL; 3659 loadConLNodes_Env._large_lo = NULL; 3660 loadConLNodes_Env._small = NULL; 3661 loadConLNodes_Env._last = new loadConL16Node(); 3662 loadConLNodes_Env._last->_opnds[0] = new iRegLdstOper(); 3663 loadConLNodes_Env._last->_opnds[1] = new immL16Oper(0); 3664 ra_->set_pair(loadConLNodes_Env._last->_idx, OptoReg::Name(R11_H_num), OptoReg::Name(R11_num)); 3665 } 3666 3667 // Create nodes and operands for loading the Toc point. 3668 loadConLNodes_Toc = loadConLNodesTuple_create(ra_, n_toc, new immLOper((jlong) fd->toc()), 3669 OptoReg::Name(R2_H_num), OptoReg::Name(R2_num)); 3670 #endif // ABI_ELFv2 3671 // mtctr node 3672 MachNode *mtctr = new CallLeafDirect_mtctrNode(); 3673 3674 assert(loadConLNodes_Entry._last != NULL, "entry must exist"); 3675 mtctr->add_req(0, loadConLNodes_Entry._last); 3676 3677 mtctr->_opnds[0] = new iRegLdstOper(); 3678 mtctr->_opnds[1] = new iRegLdstOper(); 3679 3680 // call node 3681 MachCallLeafNode *call = new CallLeafDirectNode(); 3682 3683 call->_opnds[0] = _opnds[0]; 3684 call->_opnds[1] = new methodOper((intptr_t) entry_address); // May get set later. 3685 3686 // Make the new call node look like the old one. 3687 call->_name = _name; 3688 call->_tf = _tf; 3689 call->_entry_point = _entry_point; 3690 call->_cnt = _cnt; 3691 call->_argsize = _argsize; 3692 call->_oop_map = _oop_map; 3693 guarantee(!_jvms, "You must clone the jvms and adapt the offsets by fix_jvms()."); 3694 call->_jvms = NULL; 3695 call->_jvmadj = _jvmadj; 3696 call->_in_rms = _in_rms; 3697 call->_nesting = _nesting; 3698 3699 3700 // New call needs all inputs of old call. 3701 // Req... 3702 for (uint i = 0; i < req(); ++i) { 3703 if (i != mach_constant_base_node_input()) { 3704 call->add_req(in(i)); 3705 } 3706 } 3707 3708 // These must be reqired edges, as the registers are live up to 3709 // the call. Else the constants are handled as kills. 3710 call->add_req(mtctr); 3711 #if !defined(ABI_ELFv2) 3712 call->add_req(loadConLNodes_Env._last); 3713 call->add_req(loadConLNodes_Toc._last); 3714 #endif 3715 3716 // ...as well as prec 3717 for (uint i = req(); i < len(); ++i) { 3718 call->add_prec(in(i)); 3719 } 3720 3721 // registers 3722 ra_->set1(mtctr->_idx, OptoReg::Name(SR_CTR_num)); 3723 3724 // Insert the new nodes. 3725 if (loadConLNodes_Entry._large_hi) nodes->push(loadConLNodes_Entry._large_hi); 3726 if (loadConLNodes_Entry._last) nodes->push(loadConLNodes_Entry._last); 3727 #if !defined(ABI_ELFv2) 3728 if (loadConLNodes_Env._large_hi) nodes->push(loadConLNodes_Env._large_hi); 3729 if (loadConLNodes_Env._last) nodes->push(loadConLNodes_Env._last); 3730 if (loadConLNodes_Toc._large_hi) nodes->push(loadConLNodes_Toc._large_hi); 3731 if (loadConLNodes_Toc._last) nodes->push(loadConLNodes_Toc._last); 3732 #endif 3733 nodes->push(mtctr); 3734 nodes->push(call); 3735 %} 3736 %} 3737 3738 //----------FRAME-------------------------------------------------------------- 3739 // Definition of frame structure and management information. 3740 3741 frame %{ 3742 // What direction does stack grow in (assumed to be same for native & Java). 3743 stack_direction(TOWARDS_LOW); 3744 3745 // These two registers define part of the calling convention between 3746 // compiled code and the interpreter. 3747 3748 // Inline Cache Register or method for I2C. 3749 inline_cache_reg(R19); // R19_method 3750 3751 // Method Oop Register when calling interpreter. 3752 interpreter_method_oop_reg(R19); // R19_method 3753 3754 // Optional: name the operand used by cisc-spilling to access 3755 // [stack_pointer + offset]. 3756 cisc_spilling_operand_name(indOffset); 3757 3758 // Number of stack slots consumed by a Monitor enter. 3759 sync_stack_slots((frame::jit_monitor_size / VMRegImpl::stack_slot_size)); 3760 3761 // Compiled code's Frame Pointer. 3762 frame_pointer(R1); // R1_SP 3763 3764 // Interpreter stores its frame pointer in a register which is 3765 // stored to the stack by I2CAdaptors. I2CAdaptors convert from 3766 // interpreted java to compiled java. 3767 // 3768 // R14_state holds pointer to caller's cInterpreter. 3769 interpreter_frame_pointer(R14); // R14_state 3770 3771 stack_alignment(frame::alignment_in_bytes); 3772 3773 in_preserve_stack_slots((frame::jit_in_preserve_size / VMRegImpl::stack_slot_size)); 3774 3775 // Number of outgoing stack slots killed above the 3776 // out_preserve_stack_slots for calls to C. Supports the var-args 3777 // backing area for register parms. 3778 // 3779 varargs_C_out_slots_killed(((frame::abi_reg_args_size - frame::jit_out_preserve_size) / VMRegImpl::stack_slot_size)); 3780 3781 // The after-PROLOG location of the return address. Location of 3782 // return address specifies a type (REG or STACK) and a number 3783 // representing the register number (i.e. - use a register name) or 3784 // stack slot. 3785 // 3786 // A: Link register is stored in stack slot ... 3787 // M: ... but it's in the caller's frame according to PPC-64 ABI. 3788 // J: Therefore, we make sure that the link register is also in R11_scratch1 3789 // at the end of the prolog. 3790 // B: We use R20, now. 3791 //return_addr(REG R20); 3792 3793 // G: After reading the comments made by all the luminaries on their 3794 // failure to tell the compiler where the return address really is, 3795 // I hardly dare to try myself. However, I'm convinced it's in slot 3796 // 4 what apparently works and saves us some spills. 3797 return_addr(STACK 4); 3798 3799 // This is the body of the function 3800 // 3801 // void Matcher::calling_convention(OptoRegPair* sig, // array of ideal regs 3802 // uint length, // length of array 3803 // bool is_outgoing) 3804 // 3805 // The `sig' array is to be updated. sig[j] represents the location 3806 // of the j-th argument, either a register or a stack slot. 3807 3808 // Comment taken from i486.ad: 3809 // Body of function which returns an integer array locating 3810 // arguments either in registers or in stack slots. Passed an array 3811 // of ideal registers called "sig" and a "length" count. Stack-slot 3812 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3813 // arguments for a CALLEE. Incoming stack arguments are 3814 // automatically biased by the preserve_stack_slots field above. 3815 calling_convention %{ 3816 // No difference between ingoing/outgoing. Just pass false. 3817 SharedRuntime::java_calling_convention(sig_bt, regs, length, false); 3818 %} 3819 3820 // Comment taken from i486.ad: 3821 // Body of function which returns an integer array locating 3822 // arguments either in registers or in stack slots. Passed an array 3823 // of ideal registers called "sig" and a "length" count. Stack-slot 3824 // offsets are based on outgoing arguments, i.e. a CALLER setting up 3825 // arguments for a CALLEE. Incoming stack arguments are 3826 // automatically biased by the preserve_stack_slots field above. 3827 c_calling_convention %{ 3828 // This is obviously always outgoing. 3829 // C argument in register AND stack slot. 3830 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length); 3831 %} 3832 3833 // Location of native (C/C++) and interpreter return values. This 3834 // is specified to be the same as Java. In the 32-bit VM, long 3835 // values are actually returned from native calls in O0:O1 and 3836 // returned to the interpreter in I0:I1. The copying to and from 3837 // the register pairs is done by the appropriate call and epilog 3838 // opcodes. This simplifies the register allocator. 3839 c_return_value %{ 3840 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3841 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3842 "only return normal values"); 3843 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3844 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3845 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3846 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3847 %} 3848 3849 // Location of compiled Java return values. Same as C 3850 return_value %{ 3851 assert((ideal_reg >= Op_RegI && ideal_reg <= Op_RegL) || 3852 (ideal_reg == Op_RegN && Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0), 3853 "only return normal values"); 3854 // enum names from opcodes.hpp: Op_Node Op_Set Op_RegN Op_RegI Op_RegP Op_RegF Op_RegD Op_RegL 3855 static int typeToRegLo[Op_RegL+1] = { 0, 0, R3_num, R3_num, R3_num, F1_num, F1_num, R3_num }; 3856 static int typeToRegHi[Op_RegL+1] = { 0, 0, OptoReg::Bad, R3_H_num, R3_H_num, OptoReg::Bad, F1_H_num, R3_H_num }; 3857 return OptoRegPair(typeToRegHi[ideal_reg], typeToRegLo[ideal_reg]); 3858 %} 3859 %} 3860 3861 3862 //----------ATTRIBUTES--------------------------------------------------------- 3863 3864 //----------Operand Attributes------------------------------------------------- 3865 op_attrib op_cost(1); // Required cost attribute. 3866 3867 //----------Instruction Attributes--------------------------------------------- 3868 3869 // Cost attribute. required. 3870 ins_attrib ins_cost(DEFAULT_COST); 3871 3872 // Is this instruction a non-matching short branch variant of some 3873 // long branch? Not required. 3874 ins_attrib ins_short_branch(0); 3875 3876 ins_attrib ins_is_TrapBasedCheckNode(true); 3877 3878 // Number of constants. 3879 // This instruction uses the given number of constants 3880 // (optional attribute). 3881 // This is needed to determine in time whether the constant pool will 3882 // exceed 4000 entries. Before postalloc_expand the overall number of constants 3883 // is determined. It's also used to compute the constant pool size 3884 // in Output(). 3885 ins_attrib ins_num_consts(0); 3886 3887 // Required alignment attribute (must be a power of 2) specifies the 3888 // alignment that some part of the instruction (not necessarily the 3889 // start) requires. If > 1, a compute_padding() function must be 3890 // provided for the instruction. 3891 ins_attrib ins_alignment(1); 3892 3893 // Enforce/prohibit rematerializations. 3894 // - If an instruction is attributed with 'ins_cannot_rematerialize(true)' 3895 // then rematerialization of that instruction is prohibited and the 3896 // instruction's value will be spilled if necessary. 3897 // Causes that MachNode::rematerialize() returns false. 3898 // - If an instruction is attributed with 'ins_should_rematerialize(true)' 3899 // then rematerialization should be enforced and a copy of the instruction 3900 // should be inserted if possible; rematerialization is not guaranteed. 3901 // Note: this may result in rematerializations in front of every use. 3902 // Causes that MachNode::rematerialize() can return true. 3903 // (optional attribute) 3904 ins_attrib ins_cannot_rematerialize(false); 3905 ins_attrib ins_should_rematerialize(false); 3906 3907 // Instruction has variable size depending on alignment. 3908 ins_attrib ins_variable_size_depending_on_alignment(false); 3909 3910 // Instruction is a nop. 3911 ins_attrib ins_is_nop(false); 3912 3913 // Instruction is mapped to a MachIfFastLock node (instead of MachFastLock). 3914 ins_attrib ins_use_mach_if_fast_lock_node(false); 3915 3916 // Field for the toc offset of a constant. 3917 // 3918 // This is needed if the toc offset is not encodable as an immediate in 3919 // the PPC load instruction. If so, the upper (hi) bits of the offset are 3920 // added to the toc, and from this a load with immediate is performed. 3921 // With postalloc expand, we get two nodes that require the same offset 3922 // but which don't know about each other. The offset is only known 3923 // when the constant is added to the constant pool during emitting. 3924 // It is generated in the 'hi'-node adding the upper bits, and saved 3925 // in this node. The 'lo'-node has a link to the 'hi'-node and reads 3926 // the offset from there when it gets encoded. 3927 ins_attrib ins_field_const_toc_offset(0); 3928 ins_attrib ins_field_const_toc_offset_hi_node(0); 3929 3930 // A field that can hold the instructions offset in the code buffer. 3931 // Set in the nodes emitter. 3932 ins_attrib ins_field_cbuf_insts_offset(-1); 3933 3934 // Fields for referencing a call's load-IC-node. 3935 // If the toc offset can not be encoded as an immediate in a load, we 3936 // use two nodes. 3937 ins_attrib ins_field_load_ic_hi_node(0); 3938 ins_attrib ins_field_load_ic_node(0); 3939 3940 //----------OPERANDS----------------------------------------------------------- 3941 // Operand definitions must precede instruction definitions for correct 3942 // parsing in the ADLC because operands constitute user defined types 3943 // which are used in instruction definitions. 3944 // 3945 // Formats are generated automatically for constants and base registers. 3946 3947 //----------Simple Operands---------------------------------------------------- 3948 // Immediate Operands 3949 3950 // Integer Immediate: 32-bit 3951 operand immI() %{ 3952 match(ConI); 3953 op_cost(40); 3954 format %{ %} 3955 interface(CONST_INTER); 3956 %} 3957 3958 operand immI8() %{ 3959 predicate(Assembler::is_simm(n->get_int(), 8)); 3960 op_cost(0); 3961 match(ConI); 3962 format %{ %} 3963 interface(CONST_INTER); 3964 %} 3965 3966 // Integer Immediate: 16-bit 3967 operand immI16() %{ 3968 predicate(Assembler::is_simm(n->get_int(), 16)); 3969 op_cost(0); 3970 match(ConI); 3971 format %{ %} 3972 interface(CONST_INTER); 3973 %} 3974 3975 // Integer Immediate: 32-bit, where lowest 16 bits are 0x0000. 3976 operand immIhi16() %{ 3977 predicate(((n->get_int() & 0xffff0000) != 0) && ((n->get_int() & 0xffff) == 0)); 3978 match(ConI); 3979 op_cost(0); 3980 format %{ %} 3981 interface(CONST_INTER); 3982 %} 3983 3984 operand immInegpow2() %{ 3985 predicate(is_power_of_2_long((jlong) (julong) (juint) (-(n->get_int())))); 3986 match(ConI); 3987 op_cost(0); 3988 format %{ %} 3989 interface(CONST_INTER); 3990 %} 3991 3992 operand immIpow2minus1() %{ 3993 predicate(is_power_of_2_long((((jlong) (n->get_int()))+1))); 3994 match(ConI); 3995 op_cost(0); 3996 format %{ %} 3997 interface(CONST_INTER); 3998 %} 3999 4000 operand immIpowerOf2() %{ 4001 predicate(is_power_of_2_long((((jlong) (julong) (juint) (n->get_int()))))); 4002 match(ConI); 4003 op_cost(0); 4004 format %{ %} 4005 interface(CONST_INTER); 4006 %} 4007 4008 // Unsigned Integer Immediate: the values 0-31 4009 operand uimmI5() %{ 4010 predicate(Assembler::is_uimm(n->get_int(), 5)); 4011 match(ConI); 4012 op_cost(0); 4013 format %{ %} 4014 interface(CONST_INTER); 4015 %} 4016 4017 // Unsigned Integer Immediate: 6-bit 4018 operand uimmI6() %{ 4019 predicate(Assembler::is_uimm(n->get_int(), 6)); 4020 match(ConI); 4021 op_cost(0); 4022 format %{ %} 4023 interface(CONST_INTER); 4024 %} 4025 4026 // Unsigned Integer Immediate: 6-bit int, greater than 32 4027 operand uimmI6_ge32() %{ 4028 predicate(Assembler::is_uimm(n->get_int(), 6) && n->get_int() >= 32); 4029 match(ConI); 4030 op_cost(0); 4031 format %{ %} 4032 interface(CONST_INTER); 4033 %} 4034 4035 // Unsigned Integer Immediate: 15-bit 4036 operand uimmI15() %{ 4037 predicate(Assembler::is_uimm(n->get_int(), 15)); 4038 match(ConI); 4039 op_cost(0); 4040 format %{ %} 4041 interface(CONST_INTER); 4042 %} 4043 4044 // Unsigned Integer Immediate: 16-bit 4045 operand uimmI16() %{ 4046 predicate(Assembler::is_uimm(n->get_int(), 16)); 4047 match(ConI); 4048 op_cost(0); 4049 format %{ %} 4050 interface(CONST_INTER); 4051 %} 4052 4053 // constant 'int 0'. 4054 operand immI_0() %{ 4055 predicate(n->get_int() == 0); 4056 match(ConI); 4057 op_cost(0); 4058 format %{ %} 4059 interface(CONST_INTER); 4060 %} 4061 4062 // constant 'int 1'. 4063 operand immI_1() %{ 4064 predicate(n->get_int() == 1); 4065 match(ConI); 4066 op_cost(0); 4067 format %{ %} 4068 interface(CONST_INTER); 4069 %} 4070 4071 // constant 'int -1'. 4072 operand immI_minus1() %{ 4073 predicate(n->get_int() == -1); 4074 match(ConI); 4075 op_cost(0); 4076 format %{ %} 4077 interface(CONST_INTER); 4078 %} 4079 4080 // int value 16. 4081 operand immI_16() %{ 4082 predicate(n->get_int() == 16); 4083 match(ConI); 4084 op_cost(0); 4085 format %{ %} 4086 interface(CONST_INTER); 4087 %} 4088 4089 // int value 24. 4090 operand immI_24() %{ 4091 predicate(n->get_int() == 24); 4092 match(ConI); 4093 op_cost(0); 4094 format %{ %} 4095 interface(CONST_INTER); 4096 %} 4097 4098 // Compressed oops constants 4099 // Pointer Immediate 4100 operand immN() %{ 4101 match(ConN); 4102 4103 op_cost(10); 4104 format %{ %} 4105 interface(CONST_INTER); 4106 %} 4107 4108 // NULL Pointer Immediate 4109 operand immN_0() %{ 4110 predicate(n->get_narrowcon() == 0); 4111 match(ConN); 4112 4113 op_cost(0); 4114 format %{ %} 4115 interface(CONST_INTER); 4116 %} 4117 4118 // Compressed klass constants 4119 operand immNKlass() %{ 4120 match(ConNKlass); 4121 4122 op_cost(0); 4123 format %{ %} 4124 interface(CONST_INTER); 4125 %} 4126 4127 // This operand can be used to avoid matching of an instruct 4128 // with chain rule. 4129 operand immNKlass_NM() %{ 4130 match(ConNKlass); 4131 predicate(false); 4132 op_cost(0); 4133 format %{ %} 4134 interface(CONST_INTER); 4135 %} 4136 4137 // Pointer Immediate: 64-bit 4138 operand immP() %{ 4139 match(ConP); 4140 op_cost(0); 4141 format %{ %} 4142 interface(CONST_INTER); 4143 %} 4144 4145 // Operand to avoid match of loadConP. 4146 // This operand can be used to avoid matching of an instruct 4147 // with chain rule. 4148 operand immP_NM() %{ 4149 match(ConP); 4150 predicate(false); 4151 op_cost(0); 4152 format %{ %} 4153 interface(CONST_INTER); 4154 %} 4155 4156 // costant 'pointer 0'. 4157 operand immP_0() %{ 4158 predicate(n->get_ptr() == 0); 4159 match(ConP); 4160 op_cost(0); 4161 format %{ %} 4162 interface(CONST_INTER); 4163 %} 4164 4165 // pointer 0x0 or 0x1 4166 operand immP_0or1() %{ 4167 predicate((n->get_ptr() == 0) || (n->get_ptr() == 1)); 4168 match(ConP); 4169 op_cost(0); 4170 format %{ %} 4171 interface(CONST_INTER); 4172 %} 4173 4174 operand immL() %{ 4175 match(ConL); 4176 op_cost(40); 4177 format %{ %} 4178 interface(CONST_INTER); 4179 %} 4180 4181 // Long Immediate: 16-bit 4182 operand immL16() %{ 4183 predicate(Assembler::is_simm(n->get_long(), 16)); 4184 match(ConL); 4185 op_cost(0); 4186 format %{ %} 4187 interface(CONST_INTER); 4188 %} 4189 4190 // Long Immediate: 16-bit, 4-aligned 4191 operand immL16Alg4() %{ 4192 predicate(Assembler::is_simm(n->get_long(), 16) && ((n->get_long() & 0x3) == 0)); 4193 match(ConL); 4194 op_cost(0); 4195 format %{ %} 4196 interface(CONST_INTER); 4197 %} 4198 4199 // Long Immediate: 32-bit, where lowest 16 bits are 0x0000. 4200 operand immL32hi16() %{ 4201 predicate(Assembler::is_simm(n->get_long(), 32) && ((n->get_long() & 0xffffL) == 0L)); 4202 match(ConL); 4203 op_cost(0); 4204 format %{ %} 4205 interface(CONST_INTER); 4206 %} 4207 4208 // Long Immediate: 32-bit 4209 operand immL32() %{ 4210 predicate(Assembler::is_simm(n->get_long(), 32)); 4211 match(ConL); 4212 op_cost(0); 4213 format %{ %} 4214 interface(CONST_INTER); 4215 %} 4216 4217 // Long Immediate: 64-bit, where highest 16 bits are not 0x0000. 4218 operand immLhighest16() %{ 4219 predicate((n->get_long() & 0xffff000000000000L) != 0L && (n->get_long() & 0x0000ffffffffffffL) == 0L); 4220 match(ConL); 4221 op_cost(0); 4222 format %{ %} 4223 interface(CONST_INTER); 4224 %} 4225 4226 operand immLnegpow2() %{ 4227 predicate(is_power_of_2_long((jlong)-(n->get_long()))); 4228 match(ConL); 4229 op_cost(0); 4230 format %{ %} 4231 interface(CONST_INTER); 4232 %} 4233 4234 operand immLpow2minus1() %{ 4235 predicate(is_power_of_2_long((((jlong) (n->get_long()))+1)) && 4236 (n->get_long() != (jlong)0xffffffffffffffffL)); 4237 match(ConL); 4238 op_cost(0); 4239 format %{ %} 4240 interface(CONST_INTER); 4241 %} 4242 4243 // constant 'long 0'. 4244 operand immL_0() %{ 4245 predicate(n->get_long() == 0L); 4246 match(ConL); 4247 op_cost(0); 4248 format %{ %} 4249 interface(CONST_INTER); 4250 %} 4251 4252 // constat ' long -1'. 4253 operand immL_minus1() %{ 4254 predicate(n->get_long() == -1L); 4255 match(ConL); 4256 op_cost(0); 4257 format %{ %} 4258 interface(CONST_INTER); 4259 %} 4260 4261 // Long Immediate: low 32-bit mask 4262 operand immL_32bits() %{ 4263 predicate(n->get_long() == 0xFFFFFFFFL); 4264 match(ConL); 4265 op_cost(0); 4266 format %{ %} 4267 interface(CONST_INTER); 4268 %} 4269 4270 // Unsigned Long Immediate: 16-bit 4271 operand uimmL16() %{ 4272 predicate(Assembler::is_uimm(n->get_long(), 16)); 4273 match(ConL); 4274 op_cost(0); 4275 format %{ %} 4276 interface(CONST_INTER); 4277 %} 4278 4279 // Float Immediate 4280 operand immF() %{ 4281 match(ConF); 4282 op_cost(40); 4283 format %{ %} 4284 interface(CONST_INTER); 4285 %} 4286 4287 // Float Immediate: +0.0f. 4288 operand immF_0() %{ 4289 predicate(jint_cast(n->getf()) == 0); 4290 match(ConF); 4291 4292 op_cost(0); 4293 format %{ %} 4294 interface(CONST_INTER); 4295 %} 4296 4297 // Double Immediate 4298 operand immD() %{ 4299 match(ConD); 4300 op_cost(40); 4301 format %{ %} 4302 interface(CONST_INTER); 4303 %} 4304 4305 // Integer Register Operands 4306 // Integer Destination Register 4307 // See definition of reg_class bits32_reg_rw. 4308 operand iRegIdst() %{ 4309 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4310 match(RegI); 4311 match(rscratch1RegI); 4312 match(rscratch2RegI); 4313 match(rarg1RegI); 4314 match(rarg2RegI); 4315 match(rarg3RegI); 4316 match(rarg4RegI); 4317 format %{ %} 4318 interface(REG_INTER); 4319 %} 4320 4321 // Integer Source Register 4322 // See definition of reg_class bits32_reg_ro. 4323 operand iRegIsrc() %{ 4324 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4325 match(RegI); 4326 match(rscratch1RegI); 4327 match(rscratch2RegI); 4328 match(rarg1RegI); 4329 match(rarg2RegI); 4330 match(rarg3RegI); 4331 match(rarg4RegI); 4332 format %{ %} 4333 interface(REG_INTER); 4334 %} 4335 4336 operand rscratch1RegI() %{ 4337 constraint(ALLOC_IN_RC(rscratch1_bits32_reg)); 4338 match(iRegIdst); 4339 format %{ %} 4340 interface(REG_INTER); 4341 %} 4342 4343 operand rscratch2RegI() %{ 4344 constraint(ALLOC_IN_RC(rscratch2_bits32_reg)); 4345 match(iRegIdst); 4346 format %{ %} 4347 interface(REG_INTER); 4348 %} 4349 4350 operand rarg1RegI() %{ 4351 constraint(ALLOC_IN_RC(rarg1_bits32_reg)); 4352 match(iRegIdst); 4353 format %{ %} 4354 interface(REG_INTER); 4355 %} 4356 4357 operand rarg2RegI() %{ 4358 constraint(ALLOC_IN_RC(rarg2_bits32_reg)); 4359 match(iRegIdst); 4360 format %{ %} 4361 interface(REG_INTER); 4362 %} 4363 4364 operand rarg3RegI() %{ 4365 constraint(ALLOC_IN_RC(rarg3_bits32_reg)); 4366 match(iRegIdst); 4367 format %{ %} 4368 interface(REG_INTER); 4369 %} 4370 4371 operand rarg4RegI() %{ 4372 constraint(ALLOC_IN_RC(rarg4_bits32_reg)); 4373 match(iRegIdst); 4374 format %{ %} 4375 interface(REG_INTER); 4376 %} 4377 4378 operand rarg1RegL() %{ 4379 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4380 match(iRegLdst); 4381 format %{ %} 4382 interface(REG_INTER); 4383 %} 4384 4385 operand rarg2RegL() %{ 4386 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4387 match(iRegLdst); 4388 format %{ %} 4389 interface(REG_INTER); 4390 %} 4391 4392 operand rarg3RegL() %{ 4393 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4394 match(iRegLdst); 4395 format %{ %} 4396 interface(REG_INTER); 4397 %} 4398 4399 operand rarg4RegL() %{ 4400 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4401 match(iRegLdst); 4402 format %{ %} 4403 interface(REG_INTER); 4404 %} 4405 4406 // Pointer Destination Register 4407 // See definition of reg_class bits64_reg_rw. 4408 operand iRegPdst() %{ 4409 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4410 match(RegP); 4411 match(rscratch1RegP); 4412 match(rscratch2RegP); 4413 match(rarg1RegP); 4414 match(rarg2RegP); 4415 match(rarg3RegP); 4416 match(rarg4RegP); 4417 format %{ %} 4418 interface(REG_INTER); 4419 %} 4420 4421 // Pointer Destination Register 4422 // Operand not using r11 and r12 (killed in epilog). 4423 operand iRegPdstNoScratch() %{ 4424 constraint(ALLOC_IN_RC(bits64_reg_leaf_call)); 4425 match(RegP); 4426 match(rarg1RegP); 4427 match(rarg2RegP); 4428 match(rarg3RegP); 4429 match(rarg4RegP); 4430 format %{ %} 4431 interface(REG_INTER); 4432 %} 4433 4434 // Pointer Source Register 4435 // See definition of reg_class bits64_reg_ro. 4436 operand iRegPsrc() %{ 4437 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4438 match(RegP); 4439 match(iRegPdst); 4440 match(rscratch1RegP); 4441 match(rscratch2RegP); 4442 match(rarg1RegP); 4443 match(rarg2RegP); 4444 match(rarg3RegP); 4445 match(rarg4RegP); 4446 match(threadRegP); 4447 format %{ %} 4448 interface(REG_INTER); 4449 %} 4450 4451 // Thread operand. 4452 operand threadRegP() %{ 4453 constraint(ALLOC_IN_RC(thread_bits64_reg)); 4454 match(iRegPdst); 4455 format %{ "R16" %} 4456 interface(REG_INTER); 4457 %} 4458 4459 operand rscratch1RegP() %{ 4460 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4461 match(iRegPdst); 4462 format %{ "R11" %} 4463 interface(REG_INTER); 4464 %} 4465 4466 operand rscratch2RegP() %{ 4467 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4468 match(iRegPdst); 4469 format %{ %} 4470 interface(REG_INTER); 4471 %} 4472 4473 operand rarg1RegP() %{ 4474 constraint(ALLOC_IN_RC(rarg1_bits64_reg)); 4475 match(iRegPdst); 4476 format %{ %} 4477 interface(REG_INTER); 4478 %} 4479 4480 operand rarg2RegP() %{ 4481 constraint(ALLOC_IN_RC(rarg2_bits64_reg)); 4482 match(iRegPdst); 4483 format %{ %} 4484 interface(REG_INTER); 4485 %} 4486 4487 operand rarg3RegP() %{ 4488 constraint(ALLOC_IN_RC(rarg3_bits64_reg)); 4489 match(iRegPdst); 4490 format %{ %} 4491 interface(REG_INTER); 4492 %} 4493 4494 operand rarg4RegP() %{ 4495 constraint(ALLOC_IN_RC(rarg4_bits64_reg)); 4496 match(iRegPdst); 4497 format %{ %} 4498 interface(REG_INTER); 4499 %} 4500 4501 operand iRegNsrc() %{ 4502 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4503 match(RegN); 4504 match(iRegNdst); 4505 4506 format %{ %} 4507 interface(REG_INTER); 4508 %} 4509 4510 operand iRegNdst() %{ 4511 constraint(ALLOC_IN_RC(bits32_reg_rw)); 4512 match(RegN); 4513 4514 format %{ %} 4515 interface(REG_INTER); 4516 %} 4517 4518 // Long Destination Register 4519 // See definition of reg_class bits64_reg_rw. 4520 operand iRegLdst() %{ 4521 constraint(ALLOC_IN_RC(bits64_reg_rw)); 4522 match(RegL); 4523 match(rscratch1RegL); 4524 match(rscratch2RegL); 4525 format %{ %} 4526 interface(REG_INTER); 4527 %} 4528 4529 // Long Source Register 4530 // See definition of reg_class bits64_reg_ro. 4531 operand iRegLsrc() %{ 4532 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4533 match(RegL); 4534 match(iRegLdst); 4535 match(rscratch1RegL); 4536 match(rscratch2RegL); 4537 format %{ %} 4538 interface(REG_INTER); 4539 %} 4540 4541 // Special operand for ConvL2I. 4542 operand iRegL2Isrc(iRegLsrc reg) %{ 4543 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4544 match(ConvL2I reg); 4545 format %{ "ConvL2I($reg)" %} 4546 interface(REG_INTER) 4547 %} 4548 4549 operand rscratch1RegL() %{ 4550 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); 4551 match(RegL); 4552 format %{ %} 4553 interface(REG_INTER); 4554 %} 4555 4556 operand rscratch2RegL() %{ 4557 constraint(ALLOC_IN_RC(rscratch2_bits64_reg)); 4558 match(RegL); 4559 format %{ %} 4560 interface(REG_INTER); 4561 %} 4562 4563 // Condition Code Flag Registers 4564 operand flagsReg() %{ 4565 constraint(ALLOC_IN_RC(int_flags)); 4566 match(RegFlags); 4567 format %{ %} 4568 interface(REG_INTER); 4569 %} 4570 4571 operand flagsRegSrc() %{ 4572 constraint(ALLOC_IN_RC(int_flags_ro)); 4573 match(RegFlags); 4574 match(flagsReg); 4575 match(flagsRegCR0); 4576 format %{ %} 4577 interface(REG_INTER); 4578 %} 4579 4580 // Condition Code Flag Register CR0 4581 operand flagsRegCR0() %{ 4582 constraint(ALLOC_IN_RC(int_flags_CR0)); 4583 match(RegFlags); 4584 format %{ "CR0" %} 4585 interface(REG_INTER); 4586 %} 4587 4588 operand flagsRegCR1() %{ 4589 constraint(ALLOC_IN_RC(int_flags_CR1)); 4590 match(RegFlags); 4591 format %{ "CR1" %} 4592 interface(REG_INTER); 4593 %} 4594 4595 operand flagsRegCR6() %{ 4596 constraint(ALLOC_IN_RC(int_flags_CR6)); 4597 match(RegFlags); 4598 format %{ "CR6" %} 4599 interface(REG_INTER); 4600 %} 4601 4602 operand regCTR() %{ 4603 constraint(ALLOC_IN_RC(ctr_reg)); 4604 // RegFlags should work. Introducing a RegSpecial type would cause a 4605 // lot of changes. 4606 match(RegFlags); 4607 format %{"SR_CTR" %} 4608 interface(REG_INTER); 4609 %} 4610 4611 operand regD() %{ 4612 constraint(ALLOC_IN_RC(dbl_reg)); 4613 match(RegD); 4614 format %{ %} 4615 interface(REG_INTER); 4616 %} 4617 4618 operand regF() %{ 4619 constraint(ALLOC_IN_RC(flt_reg)); 4620 match(RegF); 4621 format %{ %} 4622 interface(REG_INTER); 4623 %} 4624 4625 // Special Registers 4626 4627 // Method Register 4628 operand inline_cache_regP(iRegPdst reg) %{ 4629 constraint(ALLOC_IN_RC(r19_bits64_reg)); // inline_cache_reg 4630 match(reg); 4631 format %{ %} 4632 interface(REG_INTER); 4633 %} 4634 4635 operand compiler_method_oop_regP(iRegPdst reg) %{ 4636 constraint(ALLOC_IN_RC(rscratch1_bits64_reg)); // compiler_method_oop_reg 4637 match(reg); 4638 format %{ %} 4639 interface(REG_INTER); 4640 %} 4641 4642 operand interpreter_method_oop_regP(iRegPdst reg) %{ 4643 constraint(ALLOC_IN_RC(r19_bits64_reg)); // interpreter_method_oop_reg 4644 match(reg); 4645 format %{ %} 4646 interface(REG_INTER); 4647 %} 4648 4649 // Operands to remove register moves in unscaled mode. 4650 // Match read/write registers with an EncodeP node if neither shift nor add are required. 4651 operand iRegP2N(iRegPsrc reg) %{ 4652 predicate(false /* TODO: PPC port MatchDecodeNodes*/&& Universe::narrow_oop_shift() == 0); 4653 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4654 match(EncodeP reg); 4655 format %{ "$reg" %} 4656 interface(REG_INTER) 4657 %} 4658 4659 operand iRegN2P(iRegNsrc reg) %{ 4660 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4661 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4662 match(DecodeN reg); 4663 format %{ "$reg" %} 4664 interface(REG_INTER) 4665 %} 4666 4667 operand iRegN2P_klass(iRegNsrc reg) %{ 4668 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4669 constraint(ALLOC_IN_RC(bits32_reg_ro)); 4670 match(DecodeNKlass reg); 4671 format %{ "$reg" %} 4672 interface(REG_INTER) 4673 %} 4674 4675 //----------Complex Operands--------------------------------------------------- 4676 // Indirect Memory Reference 4677 operand indirect(iRegPsrc reg) %{ 4678 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4679 match(reg); 4680 op_cost(100); 4681 format %{ "[$reg]" %} 4682 interface(MEMORY_INTER) %{ 4683 base($reg); 4684 index(0x0); 4685 scale(0x0); 4686 disp(0x0); 4687 %} 4688 %} 4689 4690 // Indirect with Offset 4691 operand indOffset16(iRegPsrc reg, immL16 offset) %{ 4692 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4693 match(AddP reg offset); 4694 op_cost(100); 4695 format %{ "[$reg + $offset]" %} 4696 interface(MEMORY_INTER) %{ 4697 base($reg); 4698 index(0x0); 4699 scale(0x0); 4700 disp($offset); 4701 %} 4702 %} 4703 4704 // Indirect with 4-aligned Offset 4705 operand indOffset16Alg4(iRegPsrc reg, immL16Alg4 offset) %{ 4706 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4707 match(AddP reg offset); 4708 op_cost(100); 4709 format %{ "[$reg + $offset]" %} 4710 interface(MEMORY_INTER) %{ 4711 base($reg); 4712 index(0x0); 4713 scale(0x0); 4714 disp($offset); 4715 %} 4716 %} 4717 4718 //----------Complex Operands for Compressed OOPs------------------------------- 4719 // Compressed OOPs with narrow_oop_shift == 0. 4720 4721 // Indirect Memory Reference, compressed OOP 4722 operand indirectNarrow(iRegNsrc reg) %{ 4723 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4724 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4725 match(DecodeN reg); 4726 op_cost(100); 4727 format %{ "[$reg]" %} 4728 interface(MEMORY_INTER) %{ 4729 base($reg); 4730 index(0x0); 4731 scale(0x0); 4732 disp(0x0); 4733 %} 4734 %} 4735 4736 operand indirectNarrow_klass(iRegNsrc reg) %{ 4737 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4738 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4739 match(DecodeNKlass reg); 4740 op_cost(100); 4741 format %{ "[$reg]" %} 4742 interface(MEMORY_INTER) %{ 4743 base($reg); 4744 index(0x0); 4745 scale(0x0); 4746 disp(0x0); 4747 %} 4748 %} 4749 4750 // Indirect with Offset, compressed OOP 4751 operand indOffset16Narrow(iRegNsrc reg, immL16 offset) %{ 4752 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4753 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4754 match(AddP (DecodeN reg) offset); 4755 op_cost(100); 4756 format %{ "[$reg + $offset]" %} 4757 interface(MEMORY_INTER) %{ 4758 base($reg); 4759 index(0x0); 4760 scale(0x0); 4761 disp($offset); 4762 %} 4763 %} 4764 4765 operand indOffset16Narrow_klass(iRegNsrc reg, immL16 offset) %{ 4766 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4767 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4768 match(AddP (DecodeNKlass reg) offset); 4769 op_cost(100); 4770 format %{ "[$reg + $offset]" %} 4771 interface(MEMORY_INTER) %{ 4772 base($reg); 4773 index(0x0); 4774 scale(0x0); 4775 disp($offset); 4776 %} 4777 %} 4778 4779 // Indirect with 4-aligned Offset, compressed OOP 4780 operand indOffset16NarrowAlg4(iRegNsrc reg, immL16Alg4 offset) %{ 4781 predicate(false /* TODO: PPC port MatchDecodeNodes*/); 4782 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4783 match(AddP (DecodeN reg) offset); 4784 op_cost(100); 4785 format %{ "[$reg + $offset]" %} 4786 interface(MEMORY_INTER) %{ 4787 base($reg); 4788 index(0x0); 4789 scale(0x0); 4790 disp($offset); 4791 %} 4792 %} 4793 4794 operand indOffset16NarrowAlg4_klass(iRegNsrc reg, immL16Alg4 offset) %{ 4795 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0); 4796 constraint(ALLOC_IN_RC(bits64_reg_ro)); 4797 match(AddP (DecodeNKlass reg) offset); 4798 op_cost(100); 4799 format %{ "[$reg + $offset]" %} 4800 interface(MEMORY_INTER) %{ 4801 base($reg); 4802 index(0x0); 4803 scale(0x0); 4804 disp($offset); 4805 %} 4806 %} 4807 4808 //----------Special Memory Operands-------------------------------------------- 4809 // Stack Slot Operand 4810 // 4811 // This operand is used for loading and storing temporary values on 4812 // the stack where a match requires a value to flow through memory. 4813 operand stackSlotI(sRegI reg) %{ 4814 constraint(ALLOC_IN_RC(stack_slots)); 4815 op_cost(100); 4816 //match(RegI); 4817 format %{ "[sp+$reg]" %} 4818 interface(MEMORY_INTER) %{ 4819 base(0x1); // R1_SP 4820 index(0x0); 4821 scale(0x0); 4822 disp($reg); // Stack Offset 4823 %} 4824 %} 4825 4826 operand stackSlotL(sRegL reg) %{ 4827 constraint(ALLOC_IN_RC(stack_slots)); 4828 op_cost(100); 4829 //match(RegL); 4830 format %{ "[sp+$reg]" %} 4831 interface(MEMORY_INTER) %{ 4832 base(0x1); // R1_SP 4833 index(0x0); 4834 scale(0x0); 4835 disp($reg); // Stack Offset 4836 %} 4837 %} 4838 4839 operand stackSlotP(sRegP reg) %{ 4840 constraint(ALLOC_IN_RC(stack_slots)); 4841 op_cost(100); 4842 //match(RegP); 4843 format %{ "[sp+$reg]" %} 4844 interface(MEMORY_INTER) %{ 4845 base(0x1); // R1_SP 4846 index(0x0); 4847 scale(0x0); 4848 disp($reg); // Stack Offset 4849 %} 4850 %} 4851 4852 operand stackSlotF(sRegF reg) %{ 4853 constraint(ALLOC_IN_RC(stack_slots)); 4854 op_cost(100); 4855 //match(RegF); 4856 format %{ "[sp+$reg]" %} 4857 interface(MEMORY_INTER) %{ 4858 base(0x1); // R1_SP 4859 index(0x0); 4860 scale(0x0); 4861 disp($reg); // Stack Offset 4862 %} 4863 %} 4864 4865 operand stackSlotD(sRegD reg) %{ 4866 constraint(ALLOC_IN_RC(stack_slots)); 4867 op_cost(100); 4868 //match(RegD); 4869 format %{ "[sp+$reg]" %} 4870 interface(MEMORY_INTER) %{ 4871 base(0x1); // R1_SP 4872 index(0x0); 4873 scale(0x0); 4874 disp($reg); // Stack Offset 4875 %} 4876 %} 4877 4878 // Operands for expressing Control Flow 4879 // NOTE: Label is a predefined operand which should not be redefined in 4880 // the AD file. It is generically handled within the ADLC. 4881 4882 //----------Conditional Branch Operands---------------------------------------- 4883 // Comparison Op 4884 // 4885 // This is the operation of the comparison, and is limited to the 4886 // following set of codes: L (<), LE (<=), G (>), GE (>=), E (==), NE 4887 // (!=). 4888 // 4889 // Other attributes of the comparison, such as unsignedness, are specified 4890 // by the comparison instruction that sets a condition code flags register. 4891 // That result is represented by a flags operand whose subtype is appropriate 4892 // to the unsignedness (etc.) of the comparison. 4893 // 4894 // Later, the instruction which matches both the Comparison Op (a Bool) and 4895 // the flags (produced by the Cmp) specifies the coding of the comparison op 4896 // by matching a specific subtype of Bool operand below. 4897 4898 // When used for floating point comparisons: unordered same as less. 4899 operand cmpOp() %{ 4900 match(Bool); 4901 format %{ "" %} 4902 interface(COND_INTER) %{ 4903 // BO only encodes bit 4 of bcondCRbiIsX, as bits 1-3 are always '100'. 4904 // BO & BI 4905 equal(0xA); // 10 10: bcondCRbiIs1 & Condition::equal 4906 not_equal(0x2); // 00 10: bcondCRbiIs0 & Condition::equal 4907 less(0x8); // 10 00: bcondCRbiIs1 & Condition::less 4908 greater_equal(0x0); // 00 00: bcondCRbiIs0 & Condition::less 4909 less_equal(0x1); // 00 01: bcondCRbiIs0 & Condition::greater 4910 greater(0x9); // 10 01: bcondCRbiIs1 & Condition::greater 4911 overflow(0xB); // 10 11: bcondCRbiIs1 & Condition::summary_overflow 4912 no_overflow(0x3); // 00 11: bcondCRbiIs0 & Condition::summary_overflow 4913 %} 4914 %} 4915 4916 //----------OPERAND CLASSES---------------------------------------------------- 4917 // Operand Classes are groups of operands that are used to simplify 4918 // instruction definitions by not requiring the AD writer to specify 4919 // seperate instructions for every form of operand when the 4920 // instruction accepts multiple operand types with the same basic 4921 // encoding and format. The classic case of this is memory operands. 4922 // Indirect is not included since its use is limited to Compare & Swap. 4923 4924 opclass memory(indirect, indOffset16 /*, indIndex, tlsReference*/, indirectNarrow, indirectNarrow_klass, indOffset16Narrow, indOffset16Narrow_klass); 4925 // Memory operand where offsets are 4-aligned. Required for ld, std. 4926 opclass memoryAlg4(indirect, indOffset16Alg4, indirectNarrow, indOffset16NarrowAlg4, indOffset16NarrowAlg4_klass); 4927 opclass indirectMemory(indirect, indirectNarrow); 4928 4929 // Special opclass for I and ConvL2I. 4930 opclass iRegIsrc_iRegL2Isrc(iRegIsrc, iRegL2Isrc); 4931 4932 // Operand classes to match encode and decode. iRegN_P2N is only used 4933 // for storeN. I have never seen an encode node elsewhere. 4934 opclass iRegN_P2N(iRegNsrc, iRegP2N); 4935 opclass iRegP_N2P(iRegPsrc, iRegN2P, iRegN2P_klass); 4936 4937 //----------PIPELINE----------------------------------------------------------- 4938 4939 pipeline %{ 4940 4941 // See J.M.Tendler et al. "Power4 system microarchitecture", IBM 4942 // J. Res. & Dev., No. 1, Jan. 2002. 4943 4944 //----------ATTRIBUTES--------------------------------------------------------- 4945 attributes %{ 4946 4947 // Power4 instructions are of fixed length. 4948 fixed_size_instructions; 4949 4950 // TODO: if `bundle' means number of instructions fetched 4951 // per cycle, this is 8. If `bundle' means Power4 `group', that is 4952 // max instructions issued per cycle, this is 5. 4953 max_instructions_per_bundle = 8; 4954 4955 // A Power4 instruction is 4 bytes long. 4956 instruction_unit_size = 4; 4957 4958 // The Power4 processor fetches 64 bytes... 4959 instruction_fetch_unit_size = 64; 4960 4961 // ...in one line 4962 instruction_fetch_units = 1 4963 4964 // Unused, list one so that array generated by adlc is not empty. 4965 // Aix compiler chokes if _nop_count = 0. 4966 nops(fxNop); 4967 %} 4968 4969 //----------RESOURCES---------------------------------------------------------- 4970 // Resources are the functional units available to the machine 4971 resources( 4972 PPC_BR, // branch unit 4973 PPC_CR, // condition unit 4974 PPC_FX1, // integer arithmetic unit 1 4975 PPC_FX2, // integer arithmetic unit 2 4976 PPC_LDST1, // load/store unit 1 4977 PPC_LDST2, // load/store unit 2 4978 PPC_FP1, // float arithmetic unit 1 4979 PPC_FP2, // float arithmetic unit 2 4980 PPC_LDST = PPC_LDST1 | PPC_LDST2, 4981 PPC_FX = PPC_FX1 | PPC_FX2, 4982 PPC_FP = PPC_FP1 | PPC_FP2 4983 ); 4984 4985 //----------PIPELINE DESCRIPTION----------------------------------------------- 4986 // Pipeline Description specifies the stages in the machine's pipeline 4987 pipe_desc( 4988 // Power4 longest pipeline path 4989 PPC_IF, // instruction fetch 4990 PPC_IC, 4991 //PPC_BP, // branch prediction 4992 PPC_D0, // decode 4993 PPC_D1, // decode 4994 PPC_D2, // decode 4995 PPC_D3, // decode 4996 PPC_Xfer1, 4997 PPC_GD, // group definition 4998 PPC_MP, // map 4999 PPC_ISS, // issue 5000 PPC_RF, // resource fetch 5001 PPC_EX1, // execute (all units) 5002 PPC_EX2, // execute (FP, LDST) 5003 PPC_EX3, // execute (FP, LDST) 5004 PPC_EX4, // execute (FP) 5005 PPC_EX5, // execute (FP) 5006 PPC_EX6, // execute (FP) 5007 PPC_WB, // write back 5008 PPC_Xfer2, 5009 PPC_CP 5010 ); 5011 5012 //----------PIPELINE CLASSES--------------------------------------------------- 5013 // Pipeline Classes describe the stages in which input and output are 5014 // referenced by the hardware pipeline. 5015 5016 // Simple pipeline classes. 5017 5018 // Default pipeline class. 5019 pipe_class pipe_class_default() %{ 5020 single_instruction; 5021 fixed_latency(2); 5022 %} 5023 5024 // Pipeline class for empty instructions. 5025 pipe_class pipe_class_empty() %{ 5026 single_instruction; 5027 fixed_latency(0); 5028 %} 5029 5030 // Pipeline class for compares. 5031 pipe_class pipe_class_compare() %{ 5032 single_instruction; 5033 fixed_latency(16); 5034 %} 5035 5036 // Pipeline class for traps. 5037 pipe_class pipe_class_trap() %{ 5038 single_instruction; 5039 fixed_latency(100); 5040 %} 5041 5042 // Pipeline class for memory operations. 5043 pipe_class pipe_class_memory() %{ 5044 single_instruction; 5045 fixed_latency(16); 5046 %} 5047 5048 // Pipeline class for call. 5049 pipe_class pipe_class_call() %{ 5050 single_instruction; 5051 fixed_latency(100); 5052 %} 5053 5054 // Define the class for the Nop node. 5055 define %{ 5056 MachNop = pipe_class_default; 5057 %} 5058 5059 %} 5060 5061 //----------INSTRUCTIONS------------------------------------------------------- 5062 5063 // Naming of instructions: 5064 // opA_operB / opA_operB_operC: 5065 // Operation 'op' with one or two source operands 'oper'. Result 5066 // type is A, source operand types are B and C. 5067 // Iff A == B == C, B and C are left out. 5068 // 5069 // The instructions are ordered according to the following scheme: 5070 // - loads 5071 // - load constants 5072 // - prefetch 5073 // - store 5074 // - encode/decode 5075 // - membar 5076 // - conditional moves 5077 // - compare & swap 5078 // - arithmetic and logic operations 5079 // * int: Add, Sub, Mul, Div, Mod 5080 // * int: lShift, arShift, urShift, rot 5081 // * float: Add, Sub, Mul, Div 5082 // * and, or, xor ... 5083 // - register moves: float <-> int, reg <-> stack, repl 5084 // - cast (high level type cast, XtoP, castPP, castII, not_null etc. 5085 // - conv (low level type cast requiring bit changes (sign extend etc) 5086 // - compares, range & zero checks. 5087 // - branches 5088 // - complex operations, intrinsics, min, max, replicate 5089 // - lock 5090 // - Calls 5091 // 5092 // If there are similar instructions with different types they are sorted: 5093 // int before float 5094 // small before big 5095 // signed before unsigned 5096 // e.g., loadS before loadUS before loadI before loadF. 5097 5098 5099 //----------Load/Store Instructions-------------------------------------------- 5100 5101 //----------Load Instructions-------------------------------------------------- 5102 5103 // Converts byte to int. 5104 // As convB2I_reg, but without match rule. The match rule of convB2I_reg 5105 // reuses the 'amount' operand, but adlc expects that operand specification 5106 // and operands in match rule are equivalent. 5107 instruct convB2I_reg_2(iRegIdst dst, iRegIsrc src) %{ 5108 effect(DEF dst, USE src); 5109 format %{ "EXTSB $dst, $src \t// byte->int" %} 5110 size(4); 5111 ins_encode %{ 5112 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 5113 __ extsb($dst$$Register, $src$$Register); 5114 %} 5115 ins_pipe(pipe_class_default); 5116 %} 5117 5118 instruct loadUB_indirect(iRegIdst dst, indirectMemory mem) %{ 5119 // match-rule, false predicate 5120 match(Set dst (LoadB mem)); 5121 predicate(false); 5122 5123 format %{ "LBZ $dst, $mem" %} 5124 size(4); 5125 ins_encode( enc_lbz(dst, mem) ); 5126 ins_pipe(pipe_class_memory); 5127 %} 5128 5129 instruct loadUB_indirect_ac(iRegIdst dst, indirectMemory mem) %{ 5130 // match-rule, false predicate 5131 match(Set dst (LoadB mem)); 5132 predicate(false); 5133 5134 format %{ "LBZ $dst, $mem\n\t" 5135 "TWI $dst\n\t" 5136 "ISYNC" %} 5137 size(12); 5138 ins_encode( enc_lbz_ac(dst, mem) ); 5139 ins_pipe(pipe_class_memory); 5140 %} 5141 5142 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5143 instruct loadB_indirect_Ex(iRegIdst dst, indirectMemory mem) %{ 5144 match(Set dst (LoadB mem)); 5145 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5146 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5147 expand %{ 5148 iRegIdst tmp; 5149 loadUB_indirect(tmp, mem); 5150 convB2I_reg_2(dst, tmp); 5151 %} 5152 %} 5153 5154 instruct loadB_indirect_ac_Ex(iRegIdst dst, indirectMemory mem) %{ 5155 match(Set dst (LoadB mem)); 5156 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5157 expand %{ 5158 iRegIdst tmp; 5159 loadUB_indirect_ac(tmp, mem); 5160 convB2I_reg_2(dst, tmp); 5161 %} 5162 %} 5163 5164 instruct loadUB_indOffset16(iRegIdst dst, indOffset16 mem) %{ 5165 // match-rule, false predicate 5166 match(Set dst (LoadB mem)); 5167 predicate(false); 5168 5169 format %{ "LBZ $dst, $mem" %} 5170 size(4); 5171 ins_encode( enc_lbz(dst, mem) ); 5172 ins_pipe(pipe_class_memory); 5173 %} 5174 5175 instruct loadUB_indOffset16_ac(iRegIdst dst, indOffset16 mem) %{ 5176 // match-rule, false predicate 5177 match(Set dst (LoadB mem)); 5178 predicate(false); 5179 5180 format %{ "LBZ $dst, $mem\n\t" 5181 "TWI $dst\n\t" 5182 "ISYNC" %} 5183 size(12); 5184 ins_encode( enc_lbz_ac(dst, mem) ); 5185 ins_pipe(pipe_class_memory); 5186 %} 5187 5188 // Load Byte (8bit signed). LoadB = LoadUB + ConvUB2B. 5189 instruct loadB_indOffset16_Ex(iRegIdst dst, indOffset16 mem) %{ 5190 match(Set dst (LoadB mem)); 5191 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5192 ins_cost(MEMORY_REF_COST + DEFAULT_COST); 5193 5194 expand %{ 5195 iRegIdst tmp; 5196 loadUB_indOffset16(tmp, mem); 5197 convB2I_reg_2(dst, tmp); 5198 %} 5199 %} 5200 5201 instruct loadB_indOffset16_ac_Ex(iRegIdst dst, indOffset16 mem) %{ 5202 match(Set dst (LoadB mem)); 5203 ins_cost(3*MEMORY_REF_COST + DEFAULT_COST); 5204 5205 expand %{ 5206 iRegIdst tmp; 5207 loadUB_indOffset16_ac(tmp, mem); 5208 convB2I_reg_2(dst, tmp); 5209 %} 5210 %} 5211 5212 // Load Unsigned Byte (8bit UNsigned) into an int reg. 5213 instruct loadUB(iRegIdst dst, memory mem) %{ 5214 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5215 match(Set dst (LoadUB mem)); 5216 ins_cost(MEMORY_REF_COST); 5217 5218 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int" %} 5219 size(4); 5220 ins_encode( enc_lbz(dst, mem) ); 5221 ins_pipe(pipe_class_memory); 5222 %} 5223 5224 // Load Unsigned Byte (8bit UNsigned) acquire. 5225 instruct loadUB_ac(iRegIdst dst, memory mem) %{ 5226 match(Set dst (LoadUB mem)); 5227 ins_cost(3*MEMORY_REF_COST); 5228 5229 format %{ "LBZ $dst, $mem \t// byte, zero-extend to int, acquire\n\t" 5230 "TWI $dst\n\t" 5231 "ISYNC" %} 5232 size(12); 5233 ins_encode( enc_lbz_ac(dst, mem) ); 5234 ins_pipe(pipe_class_memory); 5235 %} 5236 5237 // Load Unsigned Byte (8bit UNsigned) into a Long Register. 5238 instruct loadUB2L(iRegLdst dst, memory mem) %{ 5239 match(Set dst (ConvI2L (LoadUB mem))); 5240 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5241 ins_cost(MEMORY_REF_COST); 5242 5243 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long" %} 5244 size(4); 5245 ins_encode( enc_lbz(dst, mem) ); 5246 ins_pipe(pipe_class_memory); 5247 %} 5248 5249 instruct loadUB2L_ac(iRegLdst dst, memory mem) %{ 5250 match(Set dst (ConvI2L (LoadUB mem))); 5251 ins_cost(3*MEMORY_REF_COST); 5252 5253 format %{ "LBZ $dst, $mem \t// byte, zero-extend to long, acquire\n\t" 5254 "TWI $dst\n\t" 5255 "ISYNC" %} 5256 size(12); 5257 ins_encode( enc_lbz_ac(dst, mem) ); 5258 ins_pipe(pipe_class_memory); 5259 %} 5260 5261 // Load Short (16bit signed) 5262 instruct loadS(iRegIdst dst, memory mem) %{ 5263 match(Set dst (LoadS mem)); 5264 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5265 ins_cost(MEMORY_REF_COST); 5266 5267 format %{ "LHA $dst, $mem" %} 5268 size(4); 5269 ins_encode %{ 5270 // TODO: PPC port $archOpcode(ppc64Opcode_lha); 5271 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5272 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5273 %} 5274 ins_pipe(pipe_class_memory); 5275 %} 5276 5277 // Load Short (16bit signed) acquire. 5278 instruct loadS_ac(iRegIdst dst, memory mem) %{ 5279 match(Set dst (LoadS mem)); 5280 ins_cost(3*MEMORY_REF_COST); 5281 5282 format %{ "LHA $dst, $mem\t acquire\n\t" 5283 "TWI $dst\n\t" 5284 "ISYNC" %} 5285 size(12); 5286 ins_encode %{ 5287 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5288 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5289 __ lha($dst$$Register, Idisp, $mem$$base$$Register); 5290 __ twi_0($dst$$Register); 5291 __ isync(); 5292 %} 5293 ins_pipe(pipe_class_memory); 5294 %} 5295 5296 // Load Char (16bit unsigned) 5297 instruct loadUS(iRegIdst dst, memory mem) %{ 5298 match(Set dst (LoadUS mem)); 5299 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5300 ins_cost(MEMORY_REF_COST); 5301 5302 format %{ "LHZ $dst, $mem" %} 5303 size(4); 5304 ins_encode( enc_lhz(dst, mem) ); 5305 ins_pipe(pipe_class_memory); 5306 %} 5307 5308 // Load Char (16bit unsigned) acquire. 5309 instruct loadUS_ac(iRegIdst dst, memory mem) %{ 5310 match(Set dst (LoadUS mem)); 5311 ins_cost(3*MEMORY_REF_COST); 5312 5313 format %{ "LHZ $dst, $mem \t// acquire\n\t" 5314 "TWI $dst\n\t" 5315 "ISYNC" %} 5316 size(12); 5317 ins_encode( enc_lhz_ac(dst, mem) ); 5318 ins_pipe(pipe_class_memory); 5319 %} 5320 5321 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register. 5322 instruct loadUS2L(iRegLdst dst, memory mem) %{ 5323 match(Set dst (ConvI2L (LoadUS mem))); 5324 predicate(_kids[0]->_leaf->as_Load()->is_unordered() || followed_by_acquire(_kids[0]->_leaf)); 5325 ins_cost(MEMORY_REF_COST); 5326 5327 format %{ "LHZ $dst, $mem \t// short, zero-extend to long" %} 5328 size(4); 5329 ins_encode( enc_lhz(dst, mem) ); 5330 ins_pipe(pipe_class_memory); 5331 %} 5332 5333 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register acquire. 5334 instruct loadUS2L_ac(iRegLdst dst, memory mem) %{ 5335 match(Set dst (ConvI2L (LoadUS mem))); 5336 ins_cost(3*MEMORY_REF_COST); 5337 5338 format %{ "LHZ $dst, $mem \t// short, zero-extend to long, acquire\n\t" 5339 "TWI $dst\n\t" 5340 "ISYNC" %} 5341 size(12); 5342 ins_encode( enc_lhz_ac(dst, mem) ); 5343 ins_pipe(pipe_class_memory); 5344 %} 5345 5346 // Load Integer. 5347 instruct loadI(iRegIdst dst, memory mem) %{ 5348 match(Set dst (LoadI mem)); 5349 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5350 ins_cost(MEMORY_REF_COST); 5351 5352 format %{ "LWZ $dst, $mem" %} 5353 size(4); 5354 ins_encode( enc_lwz(dst, mem) ); 5355 ins_pipe(pipe_class_memory); 5356 %} 5357 5358 // Load Integer acquire. 5359 instruct loadI_ac(iRegIdst dst, memory mem) %{ 5360 match(Set dst (LoadI mem)); 5361 ins_cost(3*MEMORY_REF_COST); 5362 5363 format %{ "LWZ $dst, $mem \t// load acquire\n\t" 5364 "TWI $dst\n\t" 5365 "ISYNC" %} 5366 size(12); 5367 ins_encode( enc_lwz_ac(dst, mem) ); 5368 ins_pipe(pipe_class_memory); 5369 %} 5370 5371 // Match loading integer and casting it to unsigned int in 5372 // long register. 5373 // LoadI + ConvI2L + AndL 0xffffffff. 5374 instruct loadUI2L(iRegLdst dst, memory mem, immL_32bits mask) %{ 5375 match(Set dst (AndL (ConvI2L (LoadI mem)) mask)); 5376 predicate(_kids[0]->_kids[0]->_leaf->as_Load()->is_unordered()); 5377 ins_cost(MEMORY_REF_COST); 5378 5379 format %{ "LWZ $dst, $mem \t// zero-extend to long" %} 5380 size(4); 5381 ins_encode( enc_lwz(dst, mem) ); 5382 ins_pipe(pipe_class_memory); 5383 %} 5384 5385 // Match loading integer and casting it to long. 5386 instruct loadI2L(iRegLdst dst, memory mem) %{ 5387 match(Set dst (ConvI2L (LoadI mem))); 5388 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5389 ins_cost(MEMORY_REF_COST); 5390 5391 format %{ "LWA $dst, $mem \t// loadI2L" %} 5392 size(4); 5393 ins_encode %{ 5394 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5395 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5396 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5397 %} 5398 ins_pipe(pipe_class_memory); 5399 %} 5400 5401 // Match loading integer and casting it to long - acquire. 5402 instruct loadI2L_ac(iRegLdst dst, memory mem) %{ 5403 match(Set dst (ConvI2L (LoadI mem))); 5404 ins_cost(3*MEMORY_REF_COST); 5405 5406 format %{ "LWA $dst, $mem \t// loadI2L acquire" 5407 "TWI $dst\n\t" 5408 "ISYNC" %} 5409 size(12); 5410 ins_encode %{ 5411 // TODO: PPC port $archOpcode(ppc64Opcode_lwa); 5412 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5413 __ lwa($dst$$Register, Idisp, $mem$$base$$Register); 5414 __ twi_0($dst$$Register); 5415 __ isync(); 5416 %} 5417 ins_pipe(pipe_class_memory); 5418 %} 5419 5420 // Load Long - aligned 5421 instruct loadL(iRegLdst dst, memoryAlg4 mem) %{ 5422 match(Set dst (LoadL mem)); 5423 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5424 ins_cost(MEMORY_REF_COST); 5425 5426 format %{ "LD $dst, $mem \t// long" %} 5427 size(4); 5428 ins_encode( enc_ld(dst, mem) ); 5429 ins_pipe(pipe_class_memory); 5430 %} 5431 5432 // Load Long - aligned acquire. 5433 instruct loadL_ac(iRegLdst dst, memoryAlg4 mem) %{ 5434 match(Set dst (LoadL mem)); 5435 ins_cost(3*MEMORY_REF_COST); 5436 5437 format %{ "LD $dst, $mem \t// long acquire\n\t" 5438 "TWI $dst\n\t" 5439 "ISYNC" %} 5440 size(12); 5441 ins_encode( enc_ld_ac(dst, mem) ); 5442 ins_pipe(pipe_class_memory); 5443 %} 5444 5445 // Load Long - UNaligned 5446 instruct loadL_unaligned(iRegLdst dst, memoryAlg4 mem) %{ 5447 match(Set dst (LoadL_unaligned mem)); 5448 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5449 ins_cost(MEMORY_REF_COST); 5450 5451 format %{ "LD $dst, $mem \t// unaligned long" %} 5452 size(4); 5453 ins_encode( enc_ld(dst, mem) ); 5454 ins_pipe(pipe_class_memory); 5455 %} 5456 5457 // Load nodes for superwords 5458 5459 // Load Aligned Packed Byte 5460 instruct loadV8(iRegLdst dst, memoryAlg4 mem) %{ 5461 predicate(n->as_LoadVector()->memory_size() == 8); 5462 match(Set dst (LoadVector mem)); 5463 ins_cost(MEMORY_REF_COST); 5464 5465 format %{ "LD $dst, $mem \t// load 8-byte Vector" %} 5466 size(4); 5467 ins_encode( enc_ld(dst, mem) ); 5468 ins_pipe(pipe_class_memory); 5469 %} 5470 5471 // Load Range, range = array length (=jint) 5472 instruct loadRange(iRegIdst dst, memory mem) %{ 5473 match(Set dst (LoadRange mem)); 5474 ins_cost(MEMORY_REF_COST); 5475 5476 format %{ "LWZ $dst, $mem \t// range" %} 5477 size(4); 5478 ins_encode( enc_lwz(dst, mem) ); 5479 ins_pipe(pipe_class_memory); 5480 %} 5481 5482 // Load Compressed Pointer 5483 instruct loadN(iRegNdst dst, memory mem) %{ 5484 match(Set dst (LoadN mem)); 5485 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5486 ins_cost(MEMORY_REF_COST); 5487 5488 format %{ "LWZ $dst, $mem \t// load compressed ptr" %} 5489 size(4); 5490 ins_encode( enc_lwz(dst, mem) ); 5491 ins_pipe(pipe_class_memory); 5492 %} 5493 5494 // Load Compressed Pointer acquire. 5495 instruct loadN_ac(iRegNdst dst, memory mem) %{ 5496 match(Set dst (LoadN mem)); 5497 ins_cost(3*MEMORY_REF_COST); 5498 5499 format %{ "LWZ $dst, $mem \t// load acquire compressed ptr\n\t" 5500 "TWI $dst\n\t" 5501 "ISYNC" %} 5502 size(12); 5503 ins_encode( enc_lwz_ac(dst, mem) ); 5504 ins_pipe(pipe_class_memory); 5505 %} 5506 5507 // Load Compressed Pointer and decode it if narrow_oop_shift == 0. 5508 instruct loadN2P_unscaled(iRegPdst dst, memory mem) %{ 5509 match(Set dst (DecodeN (LoadN mem))); 5510 predicate(_kids[0]->_leaf->as_Load()->is_unordered() && Universe::narrow_oop_shift() == 0); 5511 ins_cost(MEMORY_REF_COST); 5512 5513 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} 5514 size(4); 5515 ins_encode( enc_lwz(dst, mem) ); 5516 ins_pipe(pipe_class_memory); 5517 %} 5518 5519 instruct loadN2P_klass_unscaled(iRegPdst dst, memory mem) %{ 5520 match(Set dst (DecodeNKlass (LoadNKlass mem))); 5521 predicate(Universe::narrow_klass_base() == NULL && Universe::narrow_klass_shift() == 0 && 5522 _kids[0]->_leaf->as_Load()->is_unordered()); 5523 ins_cost(MEMORY_REF_COST); 5524 5525 format %{ "LWZ $dst, $mem \t// DecodeN (unscaled)" %} 5526 size(4); 5527 ins_encode( enc_lwz(dst, mem) ); 5528 ins_pipe(pipe_class_memory); 5529 %} 5530 5531 // Load Pointer 5532 instruct loadP(iRegPdst dst, memoryAlg4 mem) %{ 5533 match(Set dst (LoadP mem)); 5534 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5535 ins_cost(MEMORY_REF_COST); 5536 5537 format %{ "LD $dst, $mem \t// ptr" %} 5538 size(4); 5539 ins_encode( enc_ld(dst, mem) ); 5540 ins_pipe(pipe_class_memory); 5541 %} 5542 5543 // Load Pointer acquire. 5544 instruct loadP_ac(iRegPdst dst, memoryAlg4 mem) %{ 5545 match(Set dst (LoadP mem)); 5546 ins_cost(3*MEMORY_REF_COST); 5547 5548 format %{ "LD $dst, $mem \t// ptr acquire\n\t" 5549 "TWI $dst\n\t" 5550 "ISYNC" %} 5551 size(12); 5552 ins_encode( enc_ld_ac(dst, mem) ); 5553 ins_pipe(pipe_class_memory); 5554 %} 5555 5556 // LoadP + CastP2L 5557 instruct loadP2X(iRegLdst dst, memoryAlg4 mem) %{ 5558 match(Set dst (CastP2X (LoadP mem))); 5559 predicate(_kids[0]->_leaf->as_Load()->is_unordered()); 5560 ins_cost(MEMORY_REF_COST); 5561 5562 format %{ "LD $dst, $mem \t// ptr + p2x" %} 5563 size(4); 5564 ins_encode( enc_ld(dst, mem) ); 5565 ins_pipe(pipe_class_memory); 5566 %} 5567 5568 // Load compressed klass pointer. 5569 instruct loadNKlass(iRegNdst dst, memory mem) %{ 5570 match(Set dst (LoadNKlass mem)); 5571 ins_cost(MEMORY_REF_COST); 5572 5573 format %{ "LWZ $dst, $mem \t// compressed klass ptr" %} 5574 size(4); 5575 ins_encode( enc_lwz(dst, mem) ); 5576 ins_pipe(pipe_class_memory); 5577 %} 5578 5579 // Load Klass Pointer 5580 instruct loadKlass(iRegPdst dst, memoryAlg4 mem) %{ 5581 match(Set dst (LoadKlass mem)); 5582 ins_cost(MEMORY_REF_COST); 5583 5584 format %{ "LD $dst, $mem \t// klass ptr" %} 5585 size(4); 5586 ins_encode( enc_ld(dst, mem) ); 5587 ins_pipe(pipe_class_memory); 5588 %} 5589 5590 // Load Float 5591 instruct loadF(regF dst, memory mem) %{ 5592 match(Set dst (LoadF mem)); 5593 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5594 ins_cost(MEMORY_REF_COST); 5595 5596 format %{ "LFS $dst, $mem" %} 5597 size(4); 5598 ins_encode %{ 5599 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 5600 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5601 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5602 %} 5603 ins_pipe(pipe_class_memory); 5604 %} 5605 5606 // Load Float acquire. 5607 instruct loadF_ac(regF dst, memory mem, flagsRegCR0 cr0) %{ 5608 match(Set dst (LoadF mem)); 5609 effect(TEMP cr0); 5610 ins_cost(3*MEMORY_REF_COST); 5611 5612 format %{ "LFS $dst, $mem \t// acquire\n\t" 5613 "FCMPU cr0, $dst, $dst\n\t" 5614 "BNE cr0, next\n" 5615 "next:\n\t" 5616 "ISYNC" %} 5617 size(16); 5618 ins_encode %{ 5619 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5620 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5621 Label next; 5622 __ lfs($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5623 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5624 __ bne(CCR0, next); 5625 __ bind(next); 5626 __ isync(); 5627 %} 5628 ins_pipe(pipe_class_memory); 5629 %} 5630 5631 // Load Double - aligned 5632 instruct loadD(regD dst, memory mem) %{ 5633 match(Set dst (LoadD mem)); 5634 predicate(n->as_Load()->is_unordered() || followed_by_acquire(n)); 5635 ins_cost(MEMORY_REF_COST); 5636 5637 format %{ "LFD $dst, $mem" %} 5638 size(4); 5639 ins_encode( enc_lfd(dst, mem) ); 5640 ins_pipe(pipe_class_memory); 5641 %} 5642 5643 // Load Double - aligned acquire. 5644 instruct loadD_ac(regD dst, memory mem, flagsRegCR0 cr0) %{ 5645 match(Set dst (LoadD mem)); 5646 effect(TEMP cr0); 5647 ins_cost(3*MEMORY_REF_COST); 5648 5649 format %{ "LFD $dst, $mem \t// acquire\n\t" 5650 "FCMPU cr0, $dst, $dst\n\t" 5651 "BNE cr0, next\n" 5652 "next:\n\t" 5653 "ISYNC" %} 5654 size(16); 5655 ins_encode %{ 5656 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5657 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 5658 Label next; 5659 __ lfd($dst$$FloatRegister, Idisp, $mem$$base$$Register); 5660 __ fcmpu(CCR0, $dst$$FloatRegister, $dst$$FloatRegister); 5661 __ bne(CCR0, next); 5662 __ bind(next); 5663 __ isync(); 5664 %} 5665 ins_pipe(pipe_class_memory); 5666 %} 5667 5668 // Load Double - UNaligned 5669 instruct loadD_unaligned(regD dst, memory mem) %{ 5670 match(Set dst (LoadD_unaligned mem)); 5671 // predicate(...) // Unaligned_ac is not needed (and wouldn't make sense). 5672 ins_cost(MEMORY_REF_COST); 5673 5674 format %{ "LFD $dst, $mem" %} 5675 size(4); 5676 ins_encode( enc_lfd(dst, mem) ); 5677 ins_pipe(pipe_class_memory); 5678 %} 5679 5680 //----------Constants-------------------------------------------------------- 5681 5682 // Load MachConstantTableBase: add hi offset to global toc. 5683 // TODO: Handle hidden register r29 in bundler! 5684 instruct loadToc_hi(iRegLdst dst) %{ 5685 effect(DEF dst); 5686 ins_cost(DEFAULT_COST); 5687 5688 format %{ "ADDIS $dst, R29, DISP.hi \t// load TOC hi" %} 5689 size(4); 5690 ins_encode %{ 5691 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5692 __ calculate_address_from_global_toc_hi16only($dst$$Register, __ method_toc()); 5693 %} 5694 ins_pipe(pipe_class_default); 5695 %} 5696 5697 // Load MachConstantTableBase: add lo offset to global toc. 5698 instruct loadToc_lo(iRegLdst dst, iRegLdst src) %{ 5699 effect(DEF dst, USE src); 5700 ins_cost(DEFAULT_COST); 5701 5702 format %{ "ADDI $dst, $src, DISP.lo \t// load TOC lo" %} 5703 size(4); 5704 ins_encode %{ 5705 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5706 __ calculate_address_from_global_toc_lo16only($dst$$Register, __ method_toc()); 5707 %} 5708 ins_pipe(pipe_class_default); 5709 %} 5710 5711 // Load 16-bit integer constant 0xssss???? 5712 instruct loadConI16(iRegIdst dst, immI16 src) %{ 5713 match(Set dst src); 5714 5715 format %{ "LI $dst, $src" %} 5716 size(4); 5717 ins_encode %{ 5718 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5719 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 5720 %} 5721 ins_pipe(pipe_class_default); 5722 %} 5723 5724 // Load integer constant 0x????0000 5725 instruct loadConIhi16(iRegIdst dst, immIhi16 src) %{ 5726 match(Set dst src); 5727 ins_cost(DEFAULT_COST); 5728 5729 format %{ "LIS $dst, $src.hi" %} 5730 size(4); 5731 ins_encode %{ 5732 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5733 // Lis sign extends 16-bit src then shifts it 16 bit to the left. 5734 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5735 %} 5736 ins_pipe(pipe_class_default); 5737 %} 5738 5739 // Part 2 of loading 32 bit constant: hi16 is is src1 (properly shifted 5740 // and sign extended), this adds the low 16 bits. 5741 instruct loadConI32_lo16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 5742 // no match-rule, false predicate 5743 effect(DEF dst, USE src1, USE src2); 5744 predicate(false); 5745 5746 format %{ "ORI $dst, $src1.hi, $src2.lo" %} 5747 size(4); 5748 ins_encode %{ 5749 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5750 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5751 %} 5752 ins_pipe(pipe_class_default); 5753 %} 5754 5755 instruct loadConI_Ex(iRegIdst dst, immI src) %{ 5756 match(Set dst src); 5757 ins_cost(DEFAULT_COST*2); 5758 5759 expand %{ 5760 // Would like to use $src$$constant. 5761 immI16 srcLo %{ _opnds[1]->constant() %} 5762 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5763 immIhi16 srcHi %{ _opnds[1]->constant() %} 5764 iRegIdst tmpI; 5765 loadConIhi16(tmpI, srcHi); 5766 loadConI32_lo16(dst, tmpI, srcLo); 5767 %} 5768 %} 5769 5770 // No constant pool entries required. 5771 instruct loadConL16(iRegLdst dst, immL16 src) %{ 5772 match(Set dst src); 5773 5774 format %{ "LI $dst, $src \t// long" %} 5775 size(4); 5776 ins_encode %{ 5777 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5778 __ li($dst$$Register, (int)((short) ($src$$constant & 0xFFFF))); 5779 %} 5780 ins_pipe(pipe_class_default); 5781 %} 5782 5783 // Load long constant 0xssssssss????0000 5784 instruct loadConL32hi16(iRegLdst dst, immL32hi16 src) %{ 5785 match(Set dst src); 5786 ins_cost(DEFAULT_COST); 5787 5788 format %{ "LIS $dst, $src.hi \t// long" %} 5789 size(4); 5790 ins_encode %{ 5791 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5792 __ lis($dst$$Register, (int)((short)(($src$$constant & 0xFFFF0000) >> 16))); 5793 %} 5794 ins_pipe(pipe_class_default); 5795 %} 5796 5797 // To load a 32 bit constant: merge lower 16 bits into already loaded 5798 // high 16 bits. 5799 instruct loadConL32_lo16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 5800 // no match-rule, false predicate 5801 effect(DEF dst, USE src1, USE src2); 5802 predicate(false); 5803 5804 format %{ "ORI $dst, $src1, $src2.lo" %} 5805 size(4); 5806 ins_encode %{ 5807 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 5808 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 5809 %} 5810 ins_pipe(pipe_class_default); 5811 %} 5812 5813 // Load 32-bit long constant 5814 instruct loadConL32_Ex(iRegLdst dst, immL32 src) %{ 5815 match(Set dst src); 5816 ins_cost(DEFAULT_COST*2); 5817 5818 expand %{ 5819 // Would like to use $src$$constant. 5820 immL16 srcLo %{ _opnds[1]->constant() /*& 0x0000FFFFL */%} 5821 // srcHi can be 0000 if srcLo sign-extends to a negative number. 5822 immL32hi16 srcHi %{ _opnds[1]->constant() /*& 0xFFFF0000L */%} 5823 iRegLdst tmpL; 5824 loadConL32hi16(tmpL, srcHi); 5825 loadConL32_lo16(dst, tmpL, srcLo); 5826 %} 5827 %} 5828 5829 // Load long constant 0x????000000000000. 5830 instruct loadConLhighest16_Ex(iRegLdst dst, immLhighest16 src) %{ 5831 match(Set dst src); 5832 ins_cost(DEFAULT_COST); 5833 5834 expand %{ 5835 immL32hi16 srcHi %{ _opnds[1]->constant() >> 32 /*& 0xFFFF0000L */%} 5836 immI shift32 %{ 32 %} 5837 iRegLdst tmpL; 5838 loadConL32hi16(tmpL, srcHi); 5839 lshiftL_regL_immI(dst, tmpL, shift32); 5840 %} 5841 %} 5842 5843 // Expand node for constant pool load: small offset. 5844 instruct loadConL(iRegLdst dst, immL src, iRegLdst toc) %{ 5845 effect(DEF dst, USE src, USE toc); 5846 ins_cost(MEMORY_REF_COST); 5847 5848 ins_num_consts(1); 5849 // Needed so that CallDynamicJavaDirect can compute the address of this 5850 // instruction for relocation. 5851 ins_field_cbuf_insts_offset(int); 5852 5853 format %{ "LD $dst, offset, $toc \t// load long $src from TOC" %} 5854 size(4); 5855 ins_encode( enc_load_long_constL(dst, src, toc) ); 5856 ins_pipe(pipe_class_memory); 5857 %} 5858 5859 // Expand node for constant pool load: large offset. 5860 instruct loadConL_hi(iRegLdst dst, immL src, iRegLdst toc) %{ 5861 effect(DEF dst, USE src, USE toc); 5862 predicate(false); 5863 5864 ins_num_consts(1); 5865 ins_field_const_toc_offset(int); 5866 // Needed so that CallDynamicJavaDirect can compute the address of this 5867 // instruction for relocation. 5868 ins_field_cbuf_insts_offset(int); 5869 5870 format %{ "ADDIS $dst, $toc, offset \t// load long $src from TOC (hi)" %} 5871 size(4); 5872 ins_encode( enc_load_long_constL_hi(dst, toc, src) ); 5873 ins_pipe(pipe_class_default); 5874 %} 5875 5876 // Expand node for constant pool load: large offset. 5877 // No constant pool entries required. 5878 instruct loadConL_lo(iRegLdst dst, immL src, iRegLdst base) %{ 5879 effect(DEF dst, USE src, USE base); 5880 predicate(false); 5881 5882 ins_field_const_toc_offset_hi_node(loadConL_hiNode*); 5883 5884 format %{ "LD $dst, offset, $base \t// load long $src from TOC (lo)" %} 5885 size(4); 5886 ins_encode %{ 5887 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 5888 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 5889 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 5890 %} 5891 ins_pipe(pipe_class_memory); 5892 %} 5893 5894 // Load long constant from constant table. Expand in case of 5895 // offset > 16 bit is needed. 5896 // Adlc adds toc node MachConstantTableBase. 5897 instruct loadConL_Ex(iRegLdst dst, immL src) %{ 5898 match(Set dst src); 5899 ins_cost(MEMORY_REF_COST); 5900 5901 format %{ "LD $dst, offset, $constanttablebase\t// load long $src from table, postalloc expanded" %} 5902 // We can not inline the enc_class for the expand as that does not support constanttablebase. 5903 postalloc_expand( postalloc_expand_load_long_constant(dst, src, constanttablebase) ); 5904 %} 5905 5906 // Load NULL as compressed oop. 5907 instruct loadConN0(iRegNdst dst, immN_0 src) %{ 5908 match(Set dst src); 5909 ins_cost(DEFAULT_COST); 5910 5911 format %{ "LI $dst, $src \t// compressed ptr" %} 5912 size(4); 5913 ins_encode %{ 5914 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5915 __ li($dst$$Register, 0); 5916 %} 5917 ins_pipe(pipe_class_default); 5918 %} 5919 5920 // Load hi part of compressed oop constant. 5921 instruct loadConN_hi(iRegNdst dst, immN src) %{ 5922 effect(DEF dst, USE src); 5923 ins_cost(DEFAULT_COST); 5924 5925 format %{ "LIS $dst, $src \t// narrow oop hi" %} 5926 size(4); 5927 ins_encode %{ 5928 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 5929 __ lis($dst$$Register, (int)(short)(($src$$constant >> 16) & 0xffff)); 5930 %} 5931 ins_pipe(pipe_class_default); 5932 %} 5933 5934 // Add lo part of compressed oop constant to already loaded hi part. 5935 instruct loadConN_lo(iRegNdst dst, iRegNsrc src1, immN src2) %{ 5936 effect(DEF dst, USE src1, USE src2); 5937 ins_cost(DEFAULT_COST); 5938 5939 format %{ "ORI $dst, $src1, $src2 \t// narrow oop lo" %} 5940 size(4); 5941 ins_encode %{ 5942 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 5943 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 5944 int oop_index = __ oop_recorder()->find_index((jobject)$src2$$constant); 5945 RelocationHolder rspec = oop_Relocation::spec(oop_index); 5946 __ relocate(rspec, 1); 5947 __ ori($dst$$Register, $src1$$Register, $src2$$constant & 0xffff); 5948 %} 5949 ins_pipe(pipe_class_default); 5950 %} 5951 5952 // Needed to postalloc expand loadConN: ConN is loaded as ConI 5953 // leaving the upper 32 bits with sign-extension bits. 5954 // This clears these bits: dst = src & 0xFFFFFFFF. 5955 // TODO: Eventually call this maskN_regN_FFFFFFFF. 5956 instruct clearMs32b(iRegNdst dst, iRegNsrc src) %{ 5957 effect(DEF dst, USE src); 5958 predicate(false); 5959 5960 format %{ "MASK $dst, $src, 0xFFFFFFFF" %} // mask 5961 size(4); 5962 ins_encode %{ 5963 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 5964 __ clrldi($dst$$Register, $src$$Register, 0x20); 5965 %} 5966 ins_pipe(pipe_class_default); 5967 %} 5968 5969 // Optimize DecodeN for disjoint base. 5970 // Load base of compressed oops into a register 5971 instruct loadBase(iRegLdst dst) %{ 5972 effect(DEF dst); 5973 5974 format %{ "LoadConst $dst, heapbase" %} 5975 ins_encode %{ 5976 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 5977 __ load_const_optimized($dst$$Register, Universe::narrow_oop_base(), R0); 5978 %} 5979 ins_pipe(pipe_class_default); 5980 %} 5981 5982 // Loading ConN must be postalloc expanded so that edges between 5983 // the nodes are safe. They may not interfere with a safepoint. 5984 // GL TODO: This needs three instructions: better put this into the constant pool. 5985 instruct loadConN_Ex(iRegNdst dst, immN src) %{ 5986 match(Set dst src); 5987 ins_cost(DEFAULT_COST*2); 5988 5989 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 5990 postalloc_expand %{ 5991 MachNode *m1 = new loadConN_hiNode(); 5992 MachNode *m2 = new loadConN_loNode(); 5993 MachNode *m3 = new clearMs32bNode(); 5994 m1->add_req(NULL); 5995 m2->add_req(NULL, m1); 5996 m3->add_req(NULL, m2); 5997 m1->_opnds[0] = op_dst; 5998 m1->_opnds[1] = op_src; 5999 m2->_opnds[0] = op_dst; 6000 m2->_opnds[1] = op_dst; 6001 m2->_opnds[2] = op_src; 6002 m3->_opnds[0] = op_dst; 6003 m3->_opnds[1] = op_dst; 6004 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6005 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6006 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6007 nodes->push(m1); 6008 nodes->push(m2); 6009 nodes->push(m3); 6010 %} 6011 %} 6012 6013 // We have seen a safepoint between the hi and lo parts, and this node was handled 6014 // as an oop. Therefore this needs a match rule so that build_oop_map knows this is 6015 // not a narrow oop. 6016 instruct loadConNKlass_hi(iRegNdst dst, immNKlass_NM src) %{ 6017 match(Set dst src); 6018 effect(DEF dst, USE src); 6019 ins_cost(DEFAULT_COST); 6020 6021 format %{ "LIS $dst, $src \t// narrow klass hi" %} 6022 size(4); 6023 ins_encode %{ 6024 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 6025 intptr_t Csrc = Klass::encode_klass((Klass *)$src$$constant); 6026 __ lis($dst$$Register, (int)(short)((Csrc >> 16) & 0xffff)); 6027 %} 6028 ins_pipe(pipe_class_default); 6029 %} 6030 6031 // As loadConNKlass_hi this must be recognized as narrow klass, not oop! 6032 instruct loadConNKlass_mask(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6033 match(Set dst src1); 6034 effect(TEMP src2); 6035 ins_cost(DEFAULT_COST); 6036 6037 format %{ "MASK $dst, $src2, 0xFFFFFFFF" %} // mask 6038 size(4); 6039 ins_encode %{ 6040 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6041 __ clrldi($dst$$Register, $src2$$Register, 0x20); 6042 %} 6043 ins_pipe(pipe_class_default); 6044 %} 6045 6046 // This needs a match rule so that build_oop_map knows this is 6047 // not a narrow oop. 6048 instruct loadConNKlass_lo(iRegNdst dst, immNKlass_NM src1, iRegNsrc src2) %{ 6049 match(Set dst src1); 6050 effect(TEMP src2); 6051 ins_cost(DEFAULT_COST); 6052 6053 format %{ "ORI $dst, $src1, $src2 \t// narrow klass lo" %} 6054 size(4); 6055 ins_encode %{ 6056 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 6057 intptr_t Csrc = Klass::encode_klass((Klass *)$src1$$constant); 6058 assert(__ oop_recorder() != NULL, "this assembler needs an OopRecorder"); 6059 int klass_index = __ oop_recorder()->find_index((Klass *)$src1$$constant); 6060 RelocationHolder rspec = metadata_Relocation::spec(klass_index); 6061 6062 __ relocate(rspec, 1); 6063 __ ori($dst$$Register, $src2$$Register, Csrc & 0xffff); 6064 %} 6065 ins_pipe(pipe_class_default); 6066 %} 6067 6068 // Loading ConNKlass must be postalloc expanded so that edges between 6069 // the nodes are safe. They may not interfere with a safepoint. 6070 instruct loadConNKlass_Ex(iRegNdst dst, immNKlass src) %{ 6071 match(Set dst src); 6072 ins_cost(DEFAULT_COST*2); 6073 6074 format %{ "LoadN $dst, $src \t// postalloc expanded" %} // mask 6075 postalloc_expand %{ 6076 // Load high bits into register. Sign extended. 6077 MachNode *m1 = new loadConNKlass_hiNode(); 6078 m1->add_req(NULL); 6079 m1->_opnds[0] = op_dst; 6080 m1->_opnds[1] = op_src; 6081 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6082 nodes->push(m1); 6083 6084 MachNode *m2 = m1; 6085 if (!Assembler::is_uimm((jlong)Klass::encode_klass((Klass *)op_src->constant()), 31)) { 6086 // Value might be 1-extended. Mask out these bits. 6087 m2 = new loadConNKlass_maskNode(); 6088 m2->add_req(NULL, m1); 6089 m2->_opnds[0] = op_dst; 6090 m2->_opnds[1] = op_src; 6091 m2->_opnds[2] = op_dst; 6092 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6093 nodes->push(m2); 6094 } 6095 6096 MachNode *m3 = new loadConNKlass_loNode(); 6097 m3->add_req(NULL, m2); 6098 m3->_opnds[0] = op_dst; 6099 m3->_opnds[1] = op_src; 6100 m3->_opnds[2] = op_dst; 6101 ra_->set_pair(m3->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6102 nodes->push(m3); 6103 %} 6104 %} 6105 6106 // 0x1 is used in object initialization (initial object header). 6107 // No constant pool entries required. 6108 instruct loadConP0or1(iRegPdst dst, immP_0or1 src) %{ 6109 match(Set dst src); 6110 6111 format %{ "LI $dst, $src \t// ptr" %} 6112 size(4); 6113 ins_encode %{ 6114 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 6115 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 6116 %} 6117 ins_pipe(pipe_class_default); 6118 %} 6119 6120 // Expand node for constant pool load: small offset. 6121 // The match rule is needed to generate the correct bottom_type(), 6122 // however this node should never match. The use of predicate is not 6123 // possible since ADLC forbids predicates for chain rules. The higher 6124 // costs do not prevent matching in this case. For that reason the 6125 // operand immP_NM with predicate(false) is used. 6126 instruct loadConP(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6127 match(Set dst src); 6128 effect(TEMP toc); 6129 6130 ins_num_consts(1); 6131 6132 format %{ "LD $dst, offset, $toc \t// load ptr $src from TOC" %} 6133 size(4); 6134 ins_encode( enc_load_long_constP(dst, src, toc) ); 6135 ins_pipe(pipe_class_memory); 6136 %} 6137 6138 // Expand node for constant pool load: large offset. 6139 instruct loadConP_hi(iRegPdst dst, immP_NM src, iRegLdst toc) %{ 6140 effect(DEF dst, USE src, USE toc); 6141 predicate(false); 6142 6143 ins_num_consts(1); 6144 ins_field_const_toc_offset(int); 6145 6146 format %{ "ADDIS $dst, $toc, offset \t// load ptr $src from TOC (hi)" %} 6147 size(4); 6148 ins_encode( enc_load_long_constP_hi(dst, src, toc) ); 6149 ins_pipe(pipe_class_default); 6150 %} 6151 6152 // Expand node for constant pool load: large offset. 6153 instruct loadConP_lo(iRegPdst dst, immP_NM src, iRegLdst base) %{ 6154 match(Set dst src); 6155 effect(TEMP base); 6156 6157 ins_field_const_toc_offset_hi_node(loadConP_hiNode*); 6158 6159 format %{ "LD $dst, offset, $base \t// load ptr $src from TOC (lo)" %} 6160 size(4); 6161 ins_encode %{ 6162 // TODO: PPC port $archOpcode(ppc64Opcode_ld); 6163 int offset = ra_->C->in_scratch_emit_size() ? 0 : _const_toc_offset_hi_node->_const_toc_offset; 6164 __ ld($dst$$Register, MacroAssembler::largeoffset_si16_si16_lo(offset), $base$$Register); 6165 %} 6166 ins_pipe(pipe_class_memory); 6167 %} 6168 6169 // Load pointer constant from constant table. Expand in case an 6170 // offset > 16 bit is needed. 6171 // Adlc adds toc node MachConstantTableBase. 6172 instruct loadConP_Ex(iRegPdst dst, immP src) %{ 6173 match(Set dst src); 6174 ins_cost(MEMORY_REF_COST); 6175 6176 // This rule does not use "expand" because then 6177 // the result type is not known to be an Oop. An ADLC 6178 // enhancement will be needed to make that work - not worth it! 6179 6180 // If this instruction rematerializes, it prolongs the live range 6181 // of the toc node, causing illegal graphs. 6182 // assert(edge_from_to(_reg_node[reg_lo],def)) fails in verify_good_schedule(). 6183 ins_cannot_rematerialize(true); 6184 6185 format %{ "LD $dst, offset, $constanttablebase \t// load ptr $src from table, postalloc expanded" %} 6186 postalloc_expand( postalloc_expand_load_ptr_constant(dst, src, constanttablebase) ); 6187 %} 6188 6189 // Expand node for constant pool load: small offset. 6190 instruct loadConF(regF dst, immF src, iRegLdst toc) %{ 6191 effect(DEF dst, USE src, USE toc); 6192 ins_cost(MEMORY_REF_COST); 6193 6194 ins_num_consts(1); 6195 6196 format %{ "LFS $dst, offset, $toc \t// load float $src from TOC" %} 6197 size(4); 6198 ins_encode %{ 6199 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 6200 address float_address = __ float_constant($src$$constant); 6201 if (float_address == NULL) { 6202 ciEnv::current()->record_out_of_memory_failure(); 6203 return; 6204 } 6205 __ lfs($dst$$FloatRegister, __ offset_to_method_toc(float_address), $toc$$Register); 6206 %} 6207 ins_pipe(pipe_class_memory); 6208 %} 6209 6210 // Expand node for constant pool load: large offset. 6211 instruct loadConFComp(regF dst, immF src, iRegLdst toc) %{ 6212 effect(DEF dst, USE src, USE toc); 6213 ins_cost(MEMORY_REF_COST); 6214 6215 ins_num_consts(1); 6216 6217 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6218 "LFS $dst, offset_lo, $toc \t// load float $src from TOC (hi/lo)\n\t" 6219 "ADDIS $toc, $toc, -offset_hi"%} 6220 size(12); 6221 ins_encode %{ 6222 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6223 FloatRegister Rdst = $dst$$FloatRegister; 6224 Register Rtoc = $toc$$Register; 6225 address float_address = __ float_constant($src$$constant); 6226 if (float_address == NULL) { 6227 ciEnv::current()->record_out_of_memory_failure(); 6228 return; 6229 } 6230 int offset = __ offset_to_method_toc(float_address); 6231 int hi = (offset + (1<<15))>>16; 6232 int lo = offset - hi * (1<<16); 6233 6234 __ addis(Rtoc, Rtoc, hi); 6235 __ lfs(Rdst, lo, Rtoc); 6236 __ addis(Rtoc, Rtoc, -hi); 6237 %} 6238 ins_pipe(pipe_class_memory); 6239 %} 6240 6241 // Adlc adds toc node MachConstantTableBase. 6242 instruct loadConF_Ex(regF dst, immF src) %{ 6243 match(Set dst src); 6244 ins_cost(MEMORY_REF_COST); 6245 6246 // See loadConP. 6247 ins_cannot_rematerialize(true); 6248 6249 format %{ "LFS $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6250 postalloc_expand( postalloc_expand_load_float_constant(dst, src, constanttablebase) ); 6251 %} 6252 6253 // Expand node for constant pool load: small offset. 6254 instruct loadConD(regD dst, immD src, iRegLdst toc) %{ 6255 effect(DEF dst, USE src, USE toc); 6256 ins_cost(MEMORY_REF_COST); 6257 6258 ins_num_consts(1); 6259 6260 format %{ "LFD $dst, offset, $toc \t// load double $src from TOC" %} 6261 size(4); 6262 ins_encode %{ 6263 // TODO: PPC port $archOpcode(ppc64Opcode_lfd); 6264 address float_address = __ double_constant($src$$constant); 6265 if (float_address == NULL) { 6266 ciEnv::current()->record_out_of_memory_failure(); 6267 return; 6268 } 6269 int offset = __ offset_to_method_toc(float_address); 6270 __ lfd($dst$$FloatRegister, offset, $toc$$Register); 6271 %} 6272 ins_pipe(pipe_class_memory); 6273 %} 6274 6275 // Expand node for constant pool load: large offset. 6276 instruct loadConDComp(regD dst, immD src, iRegLdst toc) %{ 6277 effect(DEF dst, USE src, USE toc); 6278 ins_cost(MEMORY_REF_COST); 6279 6280 ins_num_consts(1); 6281 6282 format %{ "ADDIS $toc, $toc, offset_hi\n\t" 6283 "LFD $dst, offset_lo, $toc \t// load double $src from TOC (hi/lo)\n\t" 6284 "ADDIS $toc, $toc, -offset_hi" %} 6285 size(12); 6286 ins_encode %{ 6287 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6288 FloatRegister Rdst = $dst$$FloatRegister; 6289 Register Rtoc = $toc$$Register; 6290 address float_address = __ double_constant($src$$constant); 6291 if (float_address == NULL) { 6292 ciEnv::current()->record_out_of_memory_failure(); 6293 return; 6294 } 6295 int offset = __ offset_to_method_toc(float_address); 6296 int hi = (offset + (1<<15))>>16; 6297 int lo = offset - hi * (1<<16); 6298 6299 __ addis(Rtoc, Rtoc, hi); 6300 __ lfd(Rdst, lo, Rtoc); 6301 __ addis(Rtoc, Rtoc, -hi); 6302 %} 6303 ins_pipe(pipe_class_memory); 6304 %} 6305 6306 // Adlc adds toc node MachConstantTableBase. 6307 instruct loadConD_Ex(regD dst, immD src) %{ 6308 match(Set dst src); 6309 ins_cost(MEMORY_REF_COST); 6310 6311 // See loadConP. 6312 ins_cannot_rematerialize(true); 6313 6314 format %{ "ConD $dst, offset, $constanttablebase \t// load $src from table, postalloc expanded" %} 6315 postalloc_expand( postalloc_expand_load_double_constant(dst, src, constanttablebase) ); 6316 %} 6317 6318 // Prefetch instructions. 6319 // Must be safe to execute with invalid address (cannot fault). 6320 6321 // Special prefetch versions which use the dcbz instruction. 6322 instruct prefetch_alloc_zero(indirectMemory mem, iRegLsrc src) %{ 6323 match(PrefetchAllocation (AddP mem src)); 6324 predicate(AllocatePrefetchStyle == 3); 6325 ins_cost(MEMORY_REF_COST); 6326 6327 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many with zero" %} 6328 size(4); 6329 ins_encode %{ 6330 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6331 __ dcbz($src$$Register, $mem$$base$$Register); 6332 %} 6333 ins_pipe(pipe_class_memory); 6334 %} 6335 6336 instruct prefetch_alloc_zero_no_offset(indirectMemory mem) %{ 6337 match(PrefetchAllocation mem); 6338 predicate(AllocatePrefetchStyle == 3); 6339 ins_cost(MEMORY_REF_COST); 6340 6341 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many with zero" %} 6342 size(4); 6343 ins_encode %{ 6344 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6345 __ dcbz($mem$$base$$Register); 6346 %} 6347 ins_pipe(pipe_class_memory); 6348 %} 6349 6350 instruct prefetch_alloc(indirectMemory mem, iRegLsrc src) %{ 6351 match(PrefetchAllocation (AddP mem src)); 6352 predicate(AllocatePrefetchStyle != 3); 6353 ins_cost(MEMORY_REF_COST); 6354 6355 format %{ "PREFETCH $mem, 2, $src \t// Prefetch write-many" %} 6356 size(4); 6357 ins_encode %{ 6358 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6359 __ dcbtst($src$$Register, $mem$$base$$Register); 6360 %} 6361 ins_pipe(pipe_class_memory); 6362 %} 6363 6364 instruct prefetch_alloc_no_offset(indirectMemory mem) %{ 6365 match(PrefetchAllocation mem); 6366 predicate(AllocatePrefetchStyle != 3); 6367 ins_cost(MEMORY_REF_COST); 6368 6369 format %{ "PREFETCH $mem, 2 \t// Prefetch write-many" %} 6370 size(4); 6371 ins_encode %{ 6372 // TODO: PPC port $archOpcode(ppc64Opcode_dcbtst); 6373 __ dcbtst($mem$$base$$Register); 6374 %} 6375 ins_pipe(pipe_class_memory); 6376 %} 6377 6378 //----------Store Instructions------------------------------------------------- 6379 6380 // Store Byte 6381 instruct storeB(memory mem, iRegIsrc src) %{ 6382 match(Set mem (StoreB mem src)); 6383 ins_cost(MEMORY_REF_COST); 6384 6385 format %{ "STB $src, $mem \t// byte" %} 6386 size(4); 6387 ins_encode %{ 6388 // TODO: PPC port $archOpcode(ppc64Opcode_stb); 6389 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6390 __ stb($src$$Register, Idisp, $mem$$base$$Register); 6391 %} 6392 ins_pipe(pipe_class_memory); 6393 %} 6394 6395 // Store Char/Short 6396 instruct storeC(memory mem, iRegIsrc src) %{ 6397 match(Set mem (StoreC mem src)); 6398 ins_cost(MEMORY_REF_COST); 6399 6400 format %{ "STH $src, $mem \t// short" %} 6401 size(4); 6402 ins_encode %{ 6403 // TODO: PPC port $archOpcode(ppc64Opcode_sth); 6404 int Idisp = $mem$$disp + frame_slots_bias($mem$$base, ra_); 6405 __ sth($src$$Register, Idisp, $mem$$base$$Register); 6406 %} 6407 ins_pipe(pipe_class_memory); 6408 %} 6409 6410 // Store Integer 6411 instruct storeI(memory mem, iRegIsrc src) %{ 6412 match(Set mem (StoreI mem src)); 6413 ins_cost(MEMORY_REF_COST); 6414 6415 format %{ "STW $src, $mem" %} 6416 size(4); 6417 ins_encode( enc_stw(src, mem) ); 6418 ins_pipe(pipe_class_memory); 6419 %} 6420 6421 // ConvL2I + StoreI. 6422 instruct storeI_convL2I(memory mem, iRegLsrc src) %{ 6423 match(Set mem (StoreI mem (ConvL2I src))); 6424 ins_cost(MEMORY_REF_COST); 6425 6426 format %{ "STW l2i($src), $mem" %} 6427 size(4); 6428 ins_encode( enc_stw(src, mem) ); 6429 ins_pipe(pipe_class_memory); 6430 %} 6431 6432 // Store Long 6433 instruct storeL(memoryAlg4 mem, iRegLsrc src) %{ 6434 match(Set mem (StoreL mem src)); 6435 ins_cost(MEMORY_REF_COST); 6436 6437 format %{ "STD $src, $mem \t// long" %} 6438 size(4); 6439 ins_encode( enc_std(src, mem) ); 6440 ins_pipe(pipe_class_memory); 6441 %} 6442 6443 // Store super word nodes. 6444 6445 // Store Aligned Packed Byte long register to memory 6446 instruct storeA8B(memoryAlg4 mem, iRegLsrc src) %{ 6447 predicate(n->as_StoreVector()->memory_size() == 8); 6448 match(Set mem (StoreVector mem src)); 6449 ins_cost(MEMORY_REF_COST); 6450 6451 format %{ "STD $mem, $src \t// packed8B" %} 6452 size(4); 6453 ins_encode( enc_std(src, mem) ); 6454 ins_pipe(pipe_class_memory); 6455 %} 6456 6457 // Store Compressed Oop 6458 instruct storeN(memory dst, iRegN_P2N src) %{ 6459 match(Set dst (StoreN dst src)); 6460 ins_cost(MEMORY_REF_COST); 6461 6462 format %{ "STW $src, $dst \t// compressed oop" %} 6463 size(4); 6464 ins_encode( enc_stw(src, dst) ); 6465 ins_pipe(pipe_class_memory); 6466 %} 6467 6468 // Store Compressed KLass 6469 instruct storeNKlass(memory dst, iRegN_P2N src) %{ 6470 match(Set dst (StoreNKlass dst src)); 6471 ins_cost(MEMORY_REF_COST); 6472 6473 format %{ "STW $src, $dst \t// compressed klass" %} 6474 size(4); 6475 ins_encode( enc_stw(src, dst) ); 6476 ins_pipe(pipe_class_memory); 6477 %} 6478 6479 // Store Pointer 6480 instruct storeP(memoryAlg4 dst, iRegPsrc src) %{ 6481 match(Set dst (StoreP dst src)); 6482 ins_cost(MEMORY_REF_COST); 6483 6484 format %{ "STD $src, $dst \t// ptr" %} 6485 size(4); 6486 ins_encode( enc_std(src, dst) ); 6487 ins_pipe(pipe_class_memory); 6488 %} 6489 6490 // Store Float 6491 instruct storeF(memory mem, regF src) %{ 6492 match(Set mem (StoreF mem src)); 6493 ins_cost(MEMORY_REF_COST); 6494 6495 format %{ "STFS $src, $mem" %} 6496 size(4); 6497 ins_encode( enc_stfs(src, mem) ); 6498 ins_pipe(pipe_class_memory); 6499 %} 6500 6501 // Store Double 6502 instruct storeD(memory mem, regD src) %{ 6503 match(Set mem (StoreD mem src)); 6504 ins_cost(MEMORY_REF_COST); 6505 6506 format %{ "STFD $src, $mem" %} 6507 size(4); 6508 ins_encode( enc_stfd(src, mem) ); 6509 ins_pipe(pipe_class_memory); 6510 %} 6511 6512 //----------Store Instructions With Zeros-------------------------------------- 6513 6514 // Card-mark for CMS garbage collection. 6515 // This cardmark does an optimization so that it must not always 6516 // do a releasing store. For this, it gets the address of 6517 // CMSCollectorCardTableModRefBSExt::_requires_release as input. 6518 // (Using releaseFieldAddr in the match rule is a hack.) 6519 instruct storeCM_CMS(memory mem, iRegLdst releaseFieldAddr, flagsReg crx) %{ 6520 match(Set mem (StoreCM mem releaseFieldAddr)); 6521 effect(TEMP crx); 6522 predicate(false); 6523 ins_cost(MEMORY_REF_COST); 6524 6525 // See loadConP. 6526 ins_cannot_rematerialize(true); 6527 6528 format %{ "STB #0, $mem \t// CMS card-mark byte (must be 0!), checking requires_release in [$releaseFieldAddr]" %} 6529 ins_encode( enc_cms_card_mark(mem, releaseFieldAddr, crx) ); 6530 ins_pipe(pipe_class_memory); 6531 %} 6532 6533 // Card-mark for CMS garbage collection. 6534 // This cardmark does an optimization so that it must not always 6535 // do a releasing store. For this, it needs the constant address of 6536 // CMSCollectorCardTableModRefBSExt::_requires_release. 6537 // This constant address is split off here by expand so we can use 6538 // adlc / matcher functionality to load it from the constant section. 6539 instruct storeCM_CMS_ExEx(memory mem, immI_0 zero) %{ 6540 match(Set mem (StoreCM mem zero)); 6541 predicate(UseConcMarkSweepGC); 6542 6543 expand %{ 6544 immL baseImm %{ 0 /* TODO: PPC port (jlong)CMSCollectorCardTableModRefBSExt::requires_release_address() */ %} 6545 iRegLdst releaseFieldAddress; 6546 flagsReg crx; 6547 loadConL_Ex(releaseFieldAddress, baseImm); 6548 storeCM_CMS(mem, releaseFieldAddress, crx); 6549 %} 6550 %} 6551 6552 instruct storeCM_G1(memory mem, immI_0 zero) %{ 6553 match(Set mem (StoreCM mem zero)); 6554 predicate(UseG1GC); 6555 ins_cost(MEMORY_REF_COST); 6556 6557 ins_cannot_rematerialize(true); 6558 6559 format %{ "STB #0, $mem \t// CMS card-mark byte store (G1)" %} 6560 size(8); 6561 ins_encode %{ 6562 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6563 __ li(R0, 0); 6564 //__ release(); // G1: oops are allowed to get visible after dirty marking 6565 guarantee($mem$$base$$Register != R1_SP, "use frame_slots_bias"); 6566 __ stb(R0, $mem$$disp, $mem$$base$$Register); 6567 %} 6568 ins_pipe(pipe_class_memory); 6569 %} 6570 6571 // Convert oop pointer into compressed form. 6572 6573 // Nodes for postalloc expand. 6574 6575 // Shift node for expand. 6576 instruct encodeP_shift(iRegNdst dst, iRegNsrc src) %{ 6577 // The match rule is needed to make it a 'MachTypeNode'! 6578 match(Set dst (EncodeP src)); 6579 predicate(false); 6580 6581 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6582 size(4); 6583 ins_encode %{ 6584 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6585 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6586 %} 6587 ins_pipe(pipe_class_default); 6588 %} 6589 6590 // Add node for expand. 6591 instruct encodeP_sub(iRegPdst dst, iRegPdst src) %{ 6592 // The match rule is needed to make it a 'MachTypeNode'! 6593 match(Set dst (EncodeP src)); 6594 predicate(false); 6595 6596 format %{ "SUB $dst, $src, oop_base \t// encode" %} 6597 ins_encode %{ 6598 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6599 __ sub_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6600 %} 6601 ins_pipe(pipe_class_default); 6602 %} 6603 6604 // Conditional sub base. 6605 instruct cond_sub_base(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6606 // The match rule is needed to make it a 'MachTypeNode'! 6607 match(Set dst (EncodeP (Binary crx src1))); 6608 predicate(false); 6609 6610 format %{ "BEQ $crx, done\n\t" 6611 "SUB $dst, $src1, heapbase \t// encode: subtract base if != NULL\n" 6612 "done:" %} 6613 ins_encode %{ 6614 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6615 Label done; 6616 __ beq($crx$$CondRegister, done); 6617 __ sub_const_optimized($dst$$Register, $src1$$Register, Universe::narrow_oop_base(), R0); 6618 __ bind(done); 6619 %} 6620 ins_pipe(pipe_class_default); 6621 %} 6622 6623 // Power 7 can use isel instruction 6624 instruct cond_set_0_oop(iRegNdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6625 // The match rule is needed to make it a 'MachTypeNode'! 6626 match(Set dst (EncodeP (Binary crx src1))); 6627 predicate(false); 6628 6629 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// encode: preserve 0" %} 6630 size(4); 6631 ins_encode %{ 6632 // This is a Power7 instruction for which no machine description exists. 6633 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6634 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6635 %} 6636 ins_pipe(pipe_class_default); 6637 %} 6638 6639 // Disjoint narrow oop base. 6640 instruct encodeP_Disjoint(iRegNdst dst, iRegPsrc src) %{ 6641 match(Set dst (EncodeP src)); 6642 predicate(Universe::narrow_oop_base_disjoint()); 6643 6644 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %} 6645 size(4); 6646 ins_encode %{ 6647 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6648 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_oop_shift(), 32); 6649 %} 6650 ins_pipe(pipe_class_default); 6651 %} 6652 6653 // shift != 0, base != 0 6654 instruct encodeP_Ex(iRegNdst dst, flagsReg crx, iRegPsrc src) %{ 6655 match(Set dst (EncodeP src)); 6656 effect(TEMP crx); 6657 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull && 6658 Universe::narrow_oop_shift() != 0 && 6659 Universe::narrow_oop_base_overlaps()); 6660 6661 format %{ "EncodeP $dst, $crx, $src \t// postalloc expanded" %} 6662 postalloc_expand( postalloc_expand_encode_oop(dst, src, crx)); 6663 %} 6664 6665 // shift != 0, base != 0 6666 instruct encodeP_not_null_Ex(iRegNdst dst, iRegPsrc src) %{ 6667 match(Set dst (EncodeP src)); 6668 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull && 6669 Universe::narrow_oop_shift() != 0 && 6670 Universe::narrow_oop_base_overlaps()); 6671 6672 format %{ "EncodeP $dst, $src\t// $src != Null, postalloc expanded" %} 6673 postalloc_expand( postalloc_expand_encode_oop_not_null(dst, src) ); 6674 %} 6675 6676 // shift != 0, base == 0 6677 // TODO: This is the same as encodeP_shift. Merge! 6678 instruct encodeP_not_null_base_null(iRegNdst dst, iRegPsrc src) %{ 6679 match(Set dst (EncodeP src)); 6680 predicate(Universe::narrow_oop_shift() != 0 && 6681 Universe::narrow_oop_base() ==0); 6682 6683 format %{ "SRDI $dst, $src, #3 \t// encodeP, $src != NULL" %} 6684 size(4); 6685 ins_encode %{ 6686 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6687 __ srdi($dst$$Register, $src$$Register, Universe::narrow_oop_shift() & 0x3f); 6688 %} 6689 ins_pipe(pipe_class_default); 6690 %} 6691 6692 // Compressed OOPs with narrow_oop_shift == 0. 6693 // shift == 0, base == 0 6694 instruct encodeP_narrow_oop_shift_0(iRegNdst dst, iRegPsrc src) %{ 6695 match(Set dst (EncodeP src)); 6696 predicate(Universe::narrow_oop_shift() == 0); 6697 6698 format %{ "MR $dst, $src \t// Ptr->Narrow" %} 6699 // variable size, 0 or 4. 6700 ins_encode %{ 6701 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6702 __ mr_if_needed($dst$$Register, $src$$Register); 6703 %} 6704 ins_pipe(pipe_class_default); 6705 %} 6706 6707 // Decode nodes. 6708 6709 // Shift node for expand. 6710 instruct decodeN_shift(iRegPdst dst, iRegPsrc src) %{ 6711 // The match rule is needed to make it a 'MachTypeNode'! 6712 match(Set dst (DecodeN src)); 6713 predicate(false); 6714 6715 format %{ "SLDI $dst, $src, #3 \t// DecodeN" %} 6716 size(4); 6717 ins_encode %{ 6718 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6719 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6720 %} 6721 ins_pipe(pipe_class_default); 6722 %} 6723 6724 // Add node for expand. 6725 instruct decodeN_add(iRegPdst dst, iRegPdst src) %{ 6726 // The match rule is needed to make it a 'MachTypeNode'! 6727 match(Set dst (DecodeN src)); 6728 predicate(false); 6729 6730 format %{ "ADD $dst, $src, heapbase \t// DecodeN, add oop base" %} 6731 ins_encode %{ 6732 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6733 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6734 %} 6735 ins_pipe(pipe_class_default); 6736 %} 6737 6738 // conditianal add base for expand 6739 instruct cond_add_base(iRegPdst dst, flagsRegSrc crx, iRegPsrc src) %{ 6740 // The match rule is needed to make it a 'MachTypeNode'! 6741 // NOTICE that the rule is nonsense - we just have to make sure that: 6742 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6743 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6744 match(Set dst (DecodeN (Binary crx src))); 6745 predicate(false); 6746 6747 format %{ "BEQ $crx, done\n\t" 6748 "ADD $dst, $src, heapbase \t// DecodeN: add oop base if $src != NULL\n" 6749 "done:" %} 6750 ins_encode %{ 6751 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6752 Label done; 6753 __ beq($crx$$CondRegister, done); 6754 __ add_const_optimized($dst$$Register, $src$$Register, Universe::narrow_oop_base(), R0); 6755 __ bind(done); 6756 %} 6757 ins_pipe(pipe_class_default); 6758 %} 6759 6760 instruct cond_set_0_ptr(iRegPdst dst, flagsRegSrc crx, iRegPsrc src1) %{ 6761 // The match rule is needed to make it a 'MachTypeNode'! 6762 // NOTICE that the rule is nonsense - we just have to make sure that: 6763 // - _matrule->_rChild->_opType == "DecodeN" (see InstructForm::captures_bottom_type() in formssel.cpp) 6764 // - we have to match 'crx' to avoid an "illegal USE of non-input: flagsReg crx" error in ADLC. 6765 match(Set dst (DecodeN (Binary crx src1))); 6766 predicate(false); 6767 6768 format %{ "CMOVE $dst, $crx eq, 0, $src1 \t// decode: preserve 0" %} 6769 size(4); 6770 ins_encode %{ 6771 // This is a Power7 instruction for which no machine description exists. 6772 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 6773 __ isel_0($dst$$Register, $crx$$CondRegister, Assembler::equal, $src1$$Register); 6774 %} 6775 ins_pipe(pipe_class_default); 6776 %} 6777 6778 // shift != 0, base != 0 6779 instruct decodeN_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6780 match(Set dst (DecodeN src)); 6781 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6782 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6783 Universe::narrow_oop_shift() != 0 && 6784 Universe::narrow_oop_base() != 0); 6785 ins_cost(4 * DEFAULT_COST); // Should be more expensive than decodeN_Disjoint_isel_Ex. 6786 effect(TEMP crx); 6787 6788 format %{ "DecodeN $dst, $src \t// Kills $crx, postalloc expanded" %} 6789 postalloc_expand( postalloc_expand_decode_oop(dst, src, crx) ); 6790 %} 6791 6792 // shift != 0, base == 0 6793 instruct decodeN_nullBase(iRegPdst dst, iRegNsrc src) %{ 6794 match(Set dst (DecodeN src)); 6795 predicate(Universe::narrow_oop_shift() != 0 && 6796 Universe::narrow_oop_base() == 0); 6797 6798 format %{ "SLDI $dst, $src, #3 \t// DecodeN (zerobased)" %} 6799 size(4); 6800 ins_encode %{ 6801 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 6802 __ sldi($dst$$Register, $src$$Register, Universe::narrow_oop_shift()); 6803 %} 6804 ins_pipe(pipe_class_default); 6805 %} 6806 6807 // Optimize DecodeN for disjoint base. 6808 // Shift narrow oop and or it into register that already contains the heap base. 6809 // Base == dst must hold, and is assured by construction in postaloc_expand. 6810 instruct decodeN_mergeDisjoint(iRegPdst dst, iRegNsrc src, iRegLsrc base) %{ 6811 match(Set dst (DecodeN src)); 6812 effect(TEMP base); 6813 predicate(false); 6814 6815 format %{ "RLDIMI $dst, $src, shift, 32-shift \t// DecodeN (disjoint base)" %} 6816 size(4); 6817 ins_encode %{ 6818 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 6819 __ rldimi($dst$$Register, $src$$Register, Universe::narrow_oop_shift(), 32-Universe::narrow_oop_shift()); 6820 %} 6821 ins_pipe(pipe_class_default); 6822 %} 6823 6824 // Optimize DecodeN for disjoint base. 6825 // This node requires only one cycle on the critical path. 6826 // We must postalloc_expand as we can not express use_def effects where 6827 // the used register is L and the def'ed register P. 6828 instruct decodeN_Disjoint_notNull_Ex(iRegPdst dst, iRegNsrc src) %{ 6829 match(Set dst (DecodeN src)); 6830 effect(TEMP_DEF dst); 6831 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6832 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 6833 Universe::narrow_oop_base_disjoint()); 6834 ins_cost(DEFAULT_COST); 6835 6836 format %{ "MOV $dst, heapbase \t\n" 6837 "RLDIMI $dst, $src, shift, 32-shift \t// decode with disjoint base" %} 6838 postalloc_expand %{ 6839 loadBaseNode *n1 = new loadBaseNode(); 6840 n1->add_req(NULL); 6841 n1->_opnds[0] = op_dst; 6842 6843 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode(); 6844 n2->add_req(n_region, n_src, n1); 6845 n2->_opnds[0] = op_dst; 6846 n2->_opnds[1] = op_src; 6847 n2->_opnds[2] = op_dst; 6848 n2->_bottom_type = _bottom_type; 6849 6850 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6851 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6852 6853 nodes->push(n1); 6854 nodes->push(n2); 6855 %} 6856 %} 6857 6858 instruct decodeN_Disjoint_isel_Ex(iRegPdst dst, iRegNsrc src, flagsReg crx) %{ 6859 match(Set dst (DecodeN src)); 6860 effect(TEMP_DEF dst, TEMP crx); 6861 predicate((n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull && 6862 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant) && 6863 Universe::narrow_oop_base_disjoint() && VM_Version::has_isel()); 6864 ins_cost(3 * DEFAULT_COST); 6865 6866 format %{ "DecodeN $dst, $src \t// decode with disjoint base using isel" %} 6867 postalloc_expand %{ 6868 loadBaseNode *n1 = new loadBaseNode(); 6869 n1->add_req(NULL); 6870 n1->_opnds[0] = op_dst; 6871 6872 cmpN_reg_imm0Node *n_compare = new cmpN_reg_imm0Node(); 6873 n_compare->add_req(n_region, n_src); 6874 n_compare->_opnds[0] = op_crx; 6875 n_compare->_opnds[1] = op_src; 6876 n_compare->_opnds[2] = new immN_0Oper(TypeNarrowOop::NULL_PTR); 6877 6878 decodeN_mergeDisjointNode *n2 = new decodeN_mergeDisjointNode(); 6879 n2->add_req(n_region, n_src, n1); 6880 n2->_opnds[0] = op_dst; 6881 n2->_opnds[1] = op_src; 6882 n2->_opnds[2] = op_dst; 6883 n2->_bottom_type = _bottom_type; 6884 6885 cond_set_0_ptrNode *n_cond_set = new cond_set_0_ptrNode(); 6886 n_cond_set->add_req(n_region, n_compare, n2); 6887 n_cond_set->_opnds[0] = op_dst; 6888 n_cond_set->_opnds[1] = op_crx; 6889 n_cond_set->_opnds[2] = op_dst; 6890 n_cond_set->_bottom_type = _bottom_type; 6891 6892 assert(ra_->is_oop(this) == true, "A decodeN node must produce an oop!"); 6893 ra_->set_oop(n_cond_set, true); 6894 6895 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6896 ra_->set_pair(n_compare->_idx, ra_->get_reg_second(n_crx), ra_->get_reg_first(n_crx)); 6897 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6898 ra_->set_pair(n_cond_set->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 6899 6900 nodes->push(n1); 6901 nodes->push(n_compare); 6902 nodes->push(n2); 6903 nodes->push(n_cond_set); 6904 %} 6905 %} 6906 6907 // src != 0, shift != 0, base != 0 6908 instruct decodeN_notNull_addBase_Ex(iRegPdst dst, iRegNsrc src) %{ 6909 match(Set dst (DecodeN src)); 6910 predicate((n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull || 6911 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant) && 6912 Universe::narrow_oop_shift() != 0 && 6913 Universe::narrow_oop_base() != 0); 6914 ins_cost(2 * DEFAULT_COST); 6915 6916 format %{ "DecodeN $dst, $src \t// $src != NULL, postalloc expanded" %} 6917 postalloc_expand( postalloc_expand_decode_oop_not_null(dst, src)); 6918 %} 6919 6920 // Compressed OOPs with narrow_oop_shift == 0. 6921 instruct decodeN_unscaled(iRegPdst dst, iRegNsrc src) %{ 6922 match(Set dst (DecodeN src)); 6923 predicate(Universe::narrow_oop_shift() == 0); 6924 ins_cost(DEFAULT_COST); 6925 6926 format %{ "MR $dst, $src \t// DecodeN (unscaled)" %} 6927 // variable size, 0 or 4. 6928 ins_encode %{ 6929 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6930 __ mr_if_needed($dst$$Register, $src$$Register); 6931 %} 6932 ins_pipe(pipe_class_default); 6933 %} 6934 6935 // Convert compressed oop into int for vectors alignment masking. 6936 instruct decodeN2I_unscaled(iRegIdst dst, iRegNsrc src) %{ 6937 match(Set dst (ConvL2I (CastP2X (DecodeN src)))); 6938 predicate(Universe::narrow_oop_shift() == 0); 6939 ins_cost(DEFAULT_COST); 6940 6941 format %{ "MR $dst, $src \t// (int)DecodeN (unscaled)" %} 6942 // variable size, 0 or 4. 6943 ins_encode %{ 6944 // TODO: PPC port $archOpcode(ppc64Opcode_or); 6945 __ mr_if_needed($dst$$Register, $src$$Register); 6946 %} 6947 ins_pipe(pipe_class_default); 6948 %} 6949 6950 // Convert klass pointer into compressed form. 6951 6952 // Nodes for postalloc expand. 6953 6954 // Shift node for expand. 6955 instruct encodePKlass_shift(iRegNdst dst, iRegNsrc src) %{ 6956 // The match rule is needed to make it a 'MachTypeNode'! 6957 match(Set dst (EncodePKlass src)); 6958 predicate(false); 6959 6960 format %{ "SRDI $dst, $src, 3 \t// encode" %} 6961 size(4); 6962 ins_encode %{ 6963 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6964 __ srdi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 6965 %} 6966 ins_pipe(pipe_class_default); 6967 %} 6968 6969 // Add node for expand. 6970 instruct encodePKlass_sub_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 6971 // The match rule is needed to make it a 'MachTypeNode'! 6972 match(Set dst (EncodePKlass (Binary base src))); 6973 predicate(false); 6974 6975 format %{ "SUB $dst, $base, $src \t// encode" %} 6976 size(4); 6977 ins_encode %{ 6978 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 6979 __ subf($dst$$Register, $base$$Register, $src$$Register); 6980 %} 6981 ins_pipe(pipe_class_default); 6982 %} 6983 6984 // Disjoint narrow oop base. 6985 instruct encodePKlass_Disjoint(iRegNdst dst, iRegPsrc src) %{ 6986 match(Set dst (EncodePKlass src)); 6987 predicate(false /* TODO: PPC port Universe::narrow_klass_base_disjoint()*/); 6988 6989 format %{ "EXTRDI $dst, $src, #32, #3 \t// encode with disjoint base" %} 6990 size(4); 6991 ins_encode %{ 6992 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 6993 __ rldicl($dst$$Register, $src$$Register, 64-Universe::narrow_klass_shift(), 32); 6994 %} 6995 ins_pipe(pipe_class_default); 6996 %} 6997 6998 // shift != 0, base != 0 6999 instruct encodePKlass_not_null_Ex(iRegNdst dst, iRegLsrc base, iRegPsrc src) %{ 7000 match(Set dst (EncodePKlass (Binary base src))); 7001 predicate(false); 7002 7003 format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7004 postalloc_expand %{ 7005 encodePKlass_sub_baseNode *n1 = new encodePKlass_sub_baseNode(); 7006 n1->add_req(n_region, n_base, n_src); 7007 n1->_opnds[0] = op_dst; 7008 n1->_opnds[1] = op_base; 7009 n1->_opnds[2] = op_src; 7010 n1->_bottom_type = _bottom_type; 7011 7012 encodePKlass_shiftNode *n2 = new encodePKlass_shiftNode(); 7013 n2->add_req(n_region, n1); 7014 n2->_opnds[0] = op_dst; 7015 n2->_opnds[1] = op_dst; 7016 n2->_bottom_type = _bottom_type; 7017 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7018 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7019 7020 nodes->push(n1); 7021 nodes->push(n2); 7022 %} 7023 %} 7024 7025 // shift != 0, base != 0 7026 instruct encodePKlass_not_null_ExEx(iRegNdst dst, iRegPsrc src) %{ 7027 match(Set dst (EncodePKlass src)); 7028 //predicate(Universe::narrow_klass_shift() != 0 && 7029 // true /* TODO: PPC port Universe::narrow_klass_base_overlaps()*/); 7030 7031 //format %{ "EncodePKlass $dst, $src\t// $src != Null, postalloc expanded" %} 7032 ins_cost(DEFAULT_COST*2); // Don't count constant. 7033 expand %{ 7034 immL baseImm %{ (jlong)(intptr_t)Universe::narrow_klass_base() %} 7035 iRegLdst base; 7036 loadConL_Ex(base, baseImm); 7037 encodePKlass_not_null_Ex(dst, base, src); 7038 %} 7039 %} 7040 7041 // Decode nodes. 7042 7043 // Shift node for expand. 7044 instruct decodeNKlass_shift(iRegPdst dst, iRegPsrc src) %{ 7045 // The match rule is needed to make it a 'MachTypeNode'! 7046 match(Set dst (DecodeNKlass src)); 7047 predicate(false); 7048 7049 format %{ "SLDI $dst, $src, #3 \t// DecodeNKlass" %} 7050 size(4); 7051 ins_encode %{ 7052 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 7053 __ sldi($dst$$Register, $src$$Register, Universe::narrow_klass_shift()); 7054 %} 7055 ins_pipe(pipe_class_default); 7056 %} 7057 7058 // Add node for expand. 7059 7060 instruct decodeNKlass_add_base(iRegPdst dst, iRegLsrc base, iRegPdst src) %{ 7061 // The match rule is needed to make it a 'MachTypeNode'! 7062 match(Set dst (DecodeNKlass (Binary base src))); 7063 predicate(false); 7064 7065 format %{ "ADD $dst, $base, $src \t// DecodeNKlass, add klass base" %} 7066 size(4); 7067 ins_encode %{ 7068 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7069 __ add($dst$$Register, $base$$Register, $src$$Register); 7070 %} 7071 ins_pipe(pipe_class_default); 7072 %} 7073 7074 // src != 0, shift != 0, base != 0 7075 instruct decodeNKlass_notNull_addBase_Ex(iRegPdst dst, iRegLsrc base, iRegNsrc src) %{ 7076 match(Set dst (DecodeNKlass (Binary base src))); 7077 //effect(kill src); // We need a register for the immediate result after shifting. 7078 predicate(false); 7079 7080 format %{ "DecodeNKlass $dst = $base + ($src << 3) \t// $src != NULL, postalloc expanded" %} 7081 postalloc_expand %{ 7082 decodeNKlass_add_baseNode *n1 = new decodeNKlass_add_baseNode(); 7083 n1->add_req(n_region, n_base, n_src); 7084 n1->_opnds[0] = op_dst; 7085 n1->_opnds[1] = op_base; 7086 n1->_opnds[2] = op_src; 7087 n1->_bottom_type = _bottom_type; 7088 7089 decodeNKlass_shiftNode *n2 = new decodeNKlass_shiftNode(); 7090 n2->add_req(n_region, n1); 7091 n2->_opnds[0] = op_dst; 7092 n2->_opnds[1] = op_dst; 7093 n2->_bottom_type = _bottom_type; 7094 7095 ra_->set_pair(n1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7096 ra_->set_pair(n2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); 7097 7098 nodes->push(n1); 7099 nodes->push(n2); 7100 %} 7101 %} 7102 7103 // src != 0, shift != 0, base != 0 7104 instruct decodeNKlass_notNull_addBase_ExEx(iRegPdst dst, iRegNsrc src) %{ 7105 match(Set dst (DecodeNKlass src)); 7106 // predicate(Universe::narrow_klass_shift() != 0 && 7107 // Universe::narrow_klass_base() != 0); 7108 7109 //format %{ "DecodeNKlass $dst, $src \t// $src != NULL, expanded" %} 7110 7111 ins_cost(DEFAULT_COST*2); // Don't count constant. 7112 expand %{ 7113 // We add first, then we shift. Like this, we can get along with one register less. 7114 // But we have to load the base pre-shifted. 7115 immL baseImm %{ (jlong)((intptr_t)Universe::narrow_klass_base() >> Universe::narrow_klass_shift()) %} 7116 iRegLdst base; 7117 loadConL_Ex(base, baseImm); 7118 decodeNKlass_notNull_addBase_Ex(dst, base, src); 7119 %} 7120 %} 7121 7122 //----------MemBar Instructions----------------------------------------------- 7123 // Memory barrier flavors 7124 7125 instruct membar_acquire() %{ 7126 match(LoadFence); 7127 ins_cost(4*MEMORY_REF_COST); 7128 7129 format %{ "MEMBAR-acquire" %} 7130 size(4); 7131 ins_encode %{ 7132 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7133 __ acquire(); 7134 %} 7135 ins_pipe(pipe_class_default); 7136 %} 7137 7138 instruct unnecessary_membar_acquire() %{ 7139 match(MemBarAcquire); 7140 ins_cost(0); 7141 7142 format %{ " -- \t// redundant MEMBAR-acquire - empty" %} 7143 size(0); 7144 ins_encode( /*empty*/ ); 7145 ins_pipe(pipe_class_default); 7146 %} 7147 7148 instruct membar_acquire_lock() %{ 7149 match(MemBarAcquireLock); 7150 ins_cost(0); 7151 7152 format %{ " -- \t// redundant MEMBAR-acquire - empty (acquire as part of CAS in prior FastLock)" %} 7153 size(0); 7154 ins_encode( /*empty*/ ); 7155 ins_pipe(pipe_class_default); 7156 %} 7157 7158 instruct membar_release() %{ 7159 match(MemBarRelease); 7160 match(StoreFence); 7161 ins_cost(4*MEMORY_REF_COST); 7162 7163 format %{ "MEMBAR-release" %} 7164 size(4); 7165 ins_encode %{ 7166 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7167 __ release(); 7168 %} 7169 ins_pipe(pipe_class_default); 7170 %} 7171 7172 instruct membar_storestore() %{ 7173 match(MemBarStoreStore); 7174 ins_cost(4*MEMORY_REF_COST); 7175 7176 format %{ "MEMBAR-store-store" %} 7177 size(4); 7178 ins_encode %{ 7179 // TODO: PPC port $archOpcode(ppc64Opcode_lwsync); 7180 __ membar(Assembler::StoreStore); 7181 %} 7182 ins_pipe(pipe_class_default); 7183 %} 7184 7185 instruct membar_release_lock() %{ 7186 match(MemBarReleaseLock); 7187 ins_cost(0); 7188 7189 format %{ " -- \t// redundant MEMBAR-release - empty (release in FastUnlock)" %} 7190 size(0); 7191 ins_encode( /*empty*/ ); 7192 ins_pipe(pipe_class_default); 7193 %} 7194 7195 instruct membar_volatile() %{ 7196 match(MemBarVolatile); 7197 ins_cost(4*MEMORY_REF_COST); 7198 7199 format %{ "MEMBAR-volatile" %} 7200 size(4); 7201 ins_encode %{ 7202 // TODO: PPC port $archOpcode(ppc64Opcode_sync); 7203 __ fence(); 7204 %} 7205 ins_pipe(pipe_class_default); 7206 %} 7207 7208 // This optimization is wrong on PPC. The following pattern is not supported: 7209 // MemBarVolatile 7210 // ^ ^ 7211 // | | 7212 // CtrlProj MemProj 7213 // ^ ^ 7214 // | | 7215 // | Load 7216 // | 7217 // MemBarVolatile 7218 // 7219 // The first MemBarVolatile could get optimized out! According to 7220 // Vladimir, this pattern can not occur on Oracle platforms. 7221 // However, it does occur on PPC64 (because of membars in 7222 // inline_unsafe_load_store). 7223 // 7224 // Add this node again if we found a good solution for inline_unsafe_load_store(). 7225 // Don't forget to look at the implementation of post_store_load_barrier again, 7226 // we did other fixes in that method. 7227 //instruct unnecessary_membar_volatile() %{ 7228 // match(MemBarVolatile); 7229 // predicate(Matcher::post_store_load_barrier(n)); 7230 // ins_cost(0); 7231 // 7232 // format %{ " -- \t// redundant MEMBAR-volatile - empty" %} 7233 // size(0); 7234 // ins_encode( /*empty*/ ); 7235 // ins_pipe(pipe_class_default); 7236 //%} 7237 7238 instruct membar_CPUOrder() %{ 7239 match(MemBarCPUOrder); 7240 ins_cost(0); 7241 7242 format %{ " -- \t// MEMBAR-CPUOrder - empty: PPC64 processors are self-consistent." %} 7243 size(0); 7244 ins_encode( /*empty*/ ); 7245 ins_pipe(pipe_class_default); 7246 %} 7247 7248 //----------Conditional Move--------------------------------------------------- 7249 7250 // Cmove using isel. 7251 instruct cmovI_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{ 7252 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7253 predicate(VM_Version::has_isel()); 7254 ins_cost(DEFAULT_COST); 7255 7256 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7257 size(4); 7258 ins_encode %{ 7259 // This is a Power7 instruction for which no machine description 7260 // exists. Anyways, the scheduler should be off on Power7. 7261 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7262 int cc = $cmp$$cmpcode; 7263 __ isel($dst$$Register, $crx$$CondRegister, 7264 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7265 %} 7266 ins_pipe(pipe_class_default); 7267 %} 7268 7269 instruct cmovI_reg(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, iRegIsrc src) %{ 7270 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7271 predicate(!VM_Version::has_isel()); 7272 ins_cost(DEFAULT_COST+BRANCH_COST); 7273 7274 ins_variable_size_depending_on_alignment(true); 7275 7276 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7277 // Worst case is branch + move + stop, no stop without scheduler 7278 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7279 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7280 ins_pipe(pipe_class_default); 7281 %} 7282 7283 instruct cmovI_imm(cmpOp cmp, flagsRegSrc crx, iRegIdst dst, immI16 src) %{ 7284 match(Set dst (CMoveI (Binary cmp crx) (Binary dst src))); 7285 ins_cost(DEFAULT_COST+BRANCH_COST); 7286 7287 ins_variable_size_depending_on_alignment(true); 7288 7289 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7290 // Worst case is branch + move + stop, no stop without scheduler 7291 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7292 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7293 ins_pipe(pipe_class_default); 7294 %} 7295 7296 // Cmove using isel. 7297 instruct cmovL_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{ 7298 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7299 predicate(VM_Version::has_isel()); 7300 ins_cost(DEFAULT_COST); 7301 7302 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7303 size(4); 7304 ins_encode %{ 7305 // This is a Power7 instruction for which no machine description 7306 // exists. Anyways, the scheduler should be off on Power7. 7307 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7308 int cc = $cmp$$cmpcode; 7309 __ isel($dst$$Register, $crx$$CondRegister, 7310 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7311 %} 7312 ins_pipe(pipe_class_default); 7313 %} 7314 7315 instruct cmovL_reg(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, iRegLsrc src) %{ 7316 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7317 predicate(!VM_Version::has_isel()); 7318 ins_cost(DEFAULT_COST+BRANCH_COST); 7319 7320 ins_variable_size_depending_on_alignment(true); 7321 7322 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7323 // Worst case is branch + move + stop, no stop without scheduler. 7324 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7325 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7326 ins_pipe(pipe_class_default); 7327 %} 7328 7329 instruct cmovL_imm(cmpOp cmp, flagsRegSrc crx, iRegLdst dst, immL16 src) %{ 7330 match(Set dst (CMoveL (Binary cmp crx) (Binary dst src))); 7331 ins_cost(DEFAULT_COST+BRANCH_COST); 7332 7333 ins_variable_size_depending_on_alignment(true); 7334 7335 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7336 // Worst case is branch + move + stop, no stop without scheduler. 7337 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7338 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7339 ins_pipe(pipe_class_default); 7340 %} 7341 7342 // Cmove using isel. 7343 instruct cmovN_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{ 7344 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7345 predicate(VM_Version::has_isel()); 7346 ins_cost(DEFAULT_COST); 7347 7348 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7349 size(4); 7350 ins_encode %{ 7351 // This is a Power7 instruction for which no machine description 7352 // exists. Anyways, the scheduler should be off on Power7. 7353 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7354 int cc = $cmp$$cmpcode; 7355 __ isel($dst$$Register, $crx$$CondRegister, 7356 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7357 %} 7358 ins_pipe(pipe_class_default); 7359 %} 7360 7361 // Conditional move for RegN. Only cmov(reg, reg). 7362 instruct cmovN_reg(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, iRegNsrc src) %{ 7363 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7364 predicate(!VM_Version::has_isel()); 7365 ins_cost(DEFAULT_COST+BRANCH_COST); 7366 7367 ins_variable_size_depending_on_alignment(true); 7368 7369 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7370 // Worst case is branch + move + stop, no stop without scheduler. 7371 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7372 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7373 ins_pipe(pipe_class_default); 7374 %} 7375 7376 instruct cmovN_imm(cmpOp cmp, flagsRegSrc crx, iRegNdst dst, immN_0 src) %{ 7377 match(Set dst (CMoveN (Binary cmp crx) (Binary dst src))); 7378 ins_cost(DEFAULT_COST+BRANCH_COST); 7379 7380 ins_variable_size_depending_on_alignment(true); 7381 7382 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7383 // Worst case is branch + move + stop, no stop without scheduler. 7384 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7385 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7386 ins_pipe(pipe_class_default); 7387 %} 7388 7389 // Cmove using isel. 7390 instruct cmovP_reg_isel(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegPsrc src) %{ 7391 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7392 predicate(VM_Version::has_isel()); 7393 ins_cost(DEFAULT_COST); 7394 7395 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7396 size(4); 7397 ins_encode %{ 7398 // This is a Power7 instruction for which no machine description 7399 // exists. Anyways, the scheduler should be off on Power7. 7400 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7401 int cc = $cmp$$cmpcode; 7402 __ isel($dst$$Register, $crx$$CondRegister, 7403 (Assembler::Condition)(cc & 3), /*invert*/((~cc) & 8), $src$$Register); 7404 %} 7405 ins_pipe(pipe_class_default); 7406 %} 7407 7408 instruct cmovP_reg(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, iRegP_N2P src) %{ 7409 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7410 predicate(!VM_Version::has_isel()); 7411 ins_cost(DEFAULT_COST+BRANCH_COST); 7412 7413 ins_variable_size_depending_on_alignment(true); 7414 7415 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7416 // Worst case is branch + move + stop, no stop without scheduler. 7417 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7418 ins_encode( enc_cmove_reg(dst, crx, src, cmp) ); 7419 ins_pipe(pipe_class_default); 7420 %} 7421 7422 instruct cmovP_imm(cmpOp cmp, flagsRegSrc crx, iRegPdst dst, immP_0 src) %{ 7423 match(Set dst (CMoveP (Binary cmp crx) (Binary dst src))); 7424 ins_cost(DEFAULT_COST+BRANCH_COST); 7425 7426 ins_variable_size_depending_on_alignment(true); 7427 7428 format %{ "CMOVE $cmp, $crx, $dst, $src\n\t" %} 7429 // Worst case is branch + move + stop, no stop without scheduler. 7430 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 7431 ins_encode( enc_cmove_imm(dst, crx, src, cmp) ); 7432 ins_pipe(pipe_class_default); 7433 %} 7434 7435 instruct cmovF_reg(cmpOp cmp, flagsRegSrc crx, regF dst, regF src) %{ 7436 match(Set dst (CMoveF (Binary cmp crx) (Binary dst src))); 7437 ins_cost(DEFAULT_COST+BRANCH_COST); 7438 7439 ins_variable_size_depending_on_alignment(true); 7440 7441 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7442 // Worst case is branch + move + stop, no stop without scheduler. 7443 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7444 ins_encode %{ 7445 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7446 Label done; 7447 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7448 // Branch if not (cmp crx). 7449 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7450 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7451 // TODO PPC port __ endgroup_if_needed(_size == 12); 7452 __ bind(done); 7453 %} 7454 ins_pipe(pipe_class_default); 7455 %} 7456 7457 instruct cmovD_reg(cmpOp cmp, flagsRegSrc crx, regD dst, regD src) %{ 7458 match(Set dst (CMoveD (Binary cmp crx) (Binary dst src))); 7459 ins_cost(DEFAULT_COST+BRANCH_COST); 7460 7461 ins_variable_size_depending_on_alignment(true); 7462 7463 format %{ "CMOVEF $cmp, $crx, $dst, $src\n\t" %} 7464 // Worst case is branch + move + stop, no stop without scheduler. 7465 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 7466 ins_encode %{ 7467 // TODO: PPC port $archOpcode(ppc64Opcode_cmovef); 7468 Label done; 7469 assert((Assembler::bcondCRbiIs1 & ~Assembler::bcondCRbiIs0) == 8, "check encoding"); 7470 // Branch if not (cmp crx). 7471 __ bc(cc_to_inverse_boint($cmp$$cmpcode), cc_to_biint($cmp$$cmpcode, $crx$$reg), done); 7472 __ fmr($dst$$FloatRegister, $src$$FloatRegister); 7473 // TODO PPC port __ endgroup_if_needed(_size == 12); 7474 __ bind(done); 7475 %} 7476 ins_pipe(pipe_class_default); 7477 %} 7478 7479 //----------Conditional_store-------------------------------------------------- 7480 // Conditional-store of the updated heap-top. 7481 // Used during allocation of the shared heap. 7482 // Sets flags (EQ) on success. Implemented with a CASA on Sparc. 7483 7484 // As compareAndSwapL, but return flag register instead of boolean value in 7485 // int register. 7486 // Used by sun/misc/AtomicLongCSImpl.java. 7487 // Mem_ptr must be a memory operand, else this node does not get 7488 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7489 // can be rematerialized which leads to errors. 7490 instruct storeLConditional_regP_regL_regL(flagsReg crx, indirect mem_ptr, iRegLsrc oldVal, iRegLsrc newVal, flagsRegCR0 cr0) %{ 7491 match(Set crx (StoreLConditional mem_ptr (Binary oldVal newVal))); 7492 effect(TEMP cr0); 7493 format %{ "CMPXCHGD if ($crx = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7494 ins_encode %{ 7495 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7496 __ cmpxchgd($crx$$CondRegister, R0, $oldVal$$Register, $newVal$$Register, $mem_ptr$$Register, 7497 MacroAssembler::MemBarAcq, MacroAssembler::cmpxchgx_hint_atomic_update(), 7498 noreg, NULL, true); 7499 %} 7500 ins_pipe(pipe_class_default); 7501 %} 7502 7503 // As compareAndSwapP, but return flag register instead of boolean value in 7504 // int register. 7505 // This instruction is matched if UseTLAB is off. 7506 // Mem_ptr must be a memory operand, else this node does not get 7507 // Flag_needs_anti_dependence_check set by adlc. If this is not set this node 7508 // can be rematerialized which leads to errors. 7509 instruct storePConditional_regP_regP_regP(flagsRegCR0 cr0, indirect mem_ptr, iRegPsrc oldVal, iRegPsrc newVal) %{ 7510 match(Set cr0 (StorePConditional mem_ptr (Binary oldVal newVal))); 7511 ins_cost(2*MEMORY_REF_COST); 7512 7513 format %{ "STDCX_ if ($cr0 = ($oldVal == *$mem_ptr)) *mem_ptr = $newVal; as bool" %} 7514 ins_encode %{ 7515 // TODO: PPC port $archOpcode(ppc64Opcode_stdcx_); 7516 __ stdcx_($newVal$$Register, $mem_ptr$$Register); 7517 %} 7518 ins_pipe(pipe_class_memory); 7519 %} 7520 7521 // Implement LoadPLocked. Must be ordered against changes of the memory location 7522 // by storePConditional. 7523 // Don't know whether this is ever used. 7524 instruct loadPLocked(iRegPdst dst, memory mem) %{ 7525 match(Set dst (LoadPLocked mem)); 7526 ins_cost(2*MEMORY_REF_COST); 7527 7528 format %{ "LDARX $dst, $mem \t// loadPLocked\n\t" %} 7529 size(4); 7530 ins_encode %{ 7531 // TODO: PPC port $archOpcode(ppc64Opcode_ldarx); 7532 __ ldarx($dst$$Register, $mem$$Register, MacroAssembler::cmpxchgx_hint_atomic_update()); 7533 %} 7534 ins_pipe(pipe_class_memory); 7535 %} 7536 7537 //----------Compare-And-Swap--------------------------------------------------- 7538 7539 // CompareAndSwap{P,I,L} have more than one output, therefore "CmpI 7540 // (CompareAndSwap ...)" or "If (CmpI (CompareAndSwap ..))" cannot be 7541 // matched. 7542 7543 instruct compareAndSwapI_regP_regI_regI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{ 7544 match(Set res (CompareAndSwapI mem_ptr (Binary src1 src2))); 7545 effect(TEMP cr0); 7546 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7547 // Variable size: instruction count smaller if regs are disjoint. 7548 ins_encode %{ 7549 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7550 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7551 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7552 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7553 $res$$Register, true); 7554 %} 7555 ins_pipe(pipe_class_default); 7556 %} 7557 7558 instruct compareAndSwapN_regP_regN_regN(iRegIdst res, iRegPdst mem_ptr, iRegNsrc src1, iRegNsrc src2, flagsRegCR0 cr0) %{ 7559 match(Set res (CompareAndSwapN mem_ptr (Binary src1 src2))); 7560 effect(TEMP cr0); 7561 format %{ "CMPXCHGW $res, $mem_ptr, $src1, $src2; as bool" %} 7562 // Variable size: instruction count smaller if regs are disjoint. 7563 ins_encode %{ 7564 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7565 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7566 __ cmpxchgw(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7567 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7568 $res$$Register, true); 7569 %} 7570 ins_pipe(pipe_class_default); 7571 %} 7572 7573 instruct compareAndSwapL_regP_regL_regL(iRegIdst res, iRegPdst mem_ptr, iRegLsrc src1, iRegLsrc src2, flagsRegCR0 cr0) %{ 7574 match(Set res (CompareAndSwapL mem_ptr (Binary src1 src2))); 7575 effect(TEMP cr0); 7576 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool" %} 7577 // Variable size: instruction count smaller if regs are disjoint. 7578 ins_encode %{ 7579 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7580 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7581 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7582 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7583 $res$$Register, NULL, true); 7584 %} 7585 ins_pipe(pipe_class_default); 7586 %} 7587 7588 instruct compareAndSwapP_regP_regP_regP(iRegIdst res, iRegPdst mem_ptr, iRegPsrc src1, iRegPsrc src2, flagsRegCR0 cr0) %{ 7589 match(Set res (CompareAndSwapP mem_ptr (Binary src1 src2))); 7590 effect(TEMP cr0); 7591 format %{ "CMPXCHGD $res, $mem_ptr, $src1, $src2; as bool; ptr" %} 7592 // Variable size: instruction count smaller if regs are disjoint. 7593 ins_encode %{ 7594 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 7595 // CmpxchgX sets CCR0 to cmpX(src1, src2) and Rres to 'true'/'false'. 7596 __ cmpxchgd(CCR0, R0, $src1$$Register, $src2$$Register, $mem_ptr$$Register, 7597 MacroAssembler::MemBarFenceAfter, MacroAssembler::cmpxchgx_hint_atomic_update(), 7598 $res$$Register, NULL, true); 7599 %} 7600 ins_pipe(pipe_class_default); 7601 %} 7602 7603 instruct getAndAddI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{ 7604 match(Set res (GetAndAddI mem_ptr src)); 7605 effect(TEMP cr0); 7606 format %{ "GetAndAddI $res, $mem_ptr, $src" %} 7607 // Variable size: instruction count smaller if regs are disjoint. 7608 ins_encode( enc_GetAndAddI(res, mem_ptr, src) ); 7609 ins_pipe(pipe_class_default); 7610 %} 7611 7612 instruct getAndAddL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{ 7613 match(Set res (GetAndAddL mem_ptr src)); 7614 effect(TEMP cr0); 7615 format %{ "GetAndAddL $res, $mem_ptr, $src" %} 7616 // Variable size: instruction count smaller if regs are disjoint. 7617 ins_encode( enc_GetAndAddL(res, mem_ptr, src) ); 7618 ins_pipe(pipe_class_default); 7619 %} 7620 7621 instruct getAndSetI(iRegIdst res, iRegPdst mem_ptr, iRegIsrc src, flagsRegCR0 cr0) %{ 7622 match(Set res (GetAndSetI mem_ptr src)); 7623 effect(TEMP cr0); 7624 format %{ "GetAndSetI $res, $mem_ptr, $src" %} 7625 // Variable size: instruction count smaller if regs are disjoint. 7626 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7627 ins_pipe(pipe_class_default); 7628 %} 7629 7630 instruct getAndSetL(iRegLdst res, iRegPdst mem_ptr, iRegLsrc src, flagsRegCR0 cr0) %{ 7631 match(Set res (GetAndSetL mem_ptr src)); 7632 effect(TEMP cr0); 7633 format %{ "GetAndSetL $res, $mem_ptr, $src" %} 7634 // Variable size: instruction count smaller if regs are disjoint. 7635 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7636 ins_pipe(pipe_class_default); 7637 %} 7638 7639 instruct getAndSetP(iRegPdst res, iRegPdst mem_ptr, iRegPsrc src, flagsRegCR0 cr0) %{ 7640 match(Set res (GetAndSetP mem_ptr src)); 7641 effect(TEMP cr0); 7642 format %{ "GetAndSetP $res, $mem_ptr, $src" %} 7643 // Variable size: instruction count smaller if regs are disjoint. 7644 ins_encode( enc_GetAndSetL(res, mem_ptr, src) ); 7645 ins_pipe(pipe_class_default); 7646 %} 7647 7648 instruct getAndSetN(iRegNdst res, iRegPdst mem_ptr, iRegNsrc src, flagsRegCR0 cr0) %{ 7649 match(Set res (GetAndSetN mem_ptr src)); 7650 effect(TEMP cr0); 7651 format %{ "GetAndSetN $res, $mem_ptr, $src" %} 7652 // Variable size: instruction count smaller if regs are disjoint. 7653 ins_encode( enc_GetAndSetI(res, mem_ptr, src) ); 7654 ins_pipe(pipe_class_default); 7655 %} 7656 7657 //----------Arithmetic Instructions-------------------------------------------- 7658 // Addition Instructions 7659 7660 // Register Addition 7661 instruct addI_reg_reg(iRegIdst dst, iRegIsrc_iRegL2Isrc src1, iRegIsrc_iRegL2Isrc src2) %{ 7662 match(Set dst (AddI src1 src2)); 7663 format %{ "ADD $dst, $src1, $src2" %} 7664 size(4); 7665 ins_encode %{ 7666 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7667 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7668 %} 7669 ins_pipe(pipe_class_default); 7670 %} 7671 7672 // Expand does not work with above instruct. (??) 7673 instruct addI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7674 // no match-rule 7675 effect(DEF dst, USE src1, USE src2); 7676 format %{ "ADD $dst, $src1, $src2" %} 7677 size(4); 7678 ins_encode %{ 7679 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7680 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7681 %} 7682 ins_pipe(pipe_class_default); 7683 %} 7684 7685 instruct tree_addI_addI_addI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 7686 match(Set dst (AddI (AddI (AddI src1 src2) src3) src4)); 7687 ins_cost(DEFAULT_COST*3); 7688 7689 expand %{ 7690 // FIXME: we should do this in the ideal world. 7691 iRegIdst tmp1; 7692 iRegIdst tmp2; 7693 addI_reg_reg(tmp1, src1, src2); 7694 addI_reg_reg_2(tmp2, src3, src4); // Adlc complains about addI_reg_reg. 7695 addI_reg_reg(dst, tmp1, tmp2); 7696 %} 7697 %} 7698 7699 // Immediate Addition 7700 instruct addI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 7701 match(Set dst (AddI src1 src2)); 7702 format %{ "ADDI $dst, $src1, $src2" %} 7703 size(4); 7704 ins_encode %{ 7705 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7706 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7707 %} 7708 ins_pipe(pipe_class_default); 7709 %} 7710 7711 // Immediate Addition with 16-bit shifted operand 7712 instruct addI_reg_immhi16(iRegIdst dst, iRegIsrc src1, immIhi16 src2) %{ 7713 match(Set dst (AddI src1 src2)); 7714 format %{ "ADDIS $dst, $src1, $src2" %} 7715 size(4); 7716 ins_encode %{ 7717 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7718 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7719 %} 7720 ins_pipe(pipe_class_default); 7721 %} 7722 7723 // Long Addition 7724 instruct addL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7725 match(Set dst (AddL src1 src2)); 7726 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7727 size(4); 7728 ins_encode %{ 7729 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7730 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7731 %} 7732 ins_pipe(pipe_class_default); 7733 %} 7734 7735 // Expand does not work with above instruct. (??) 7736 instruct addL_reg_reg_2(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7737 // no match-rule 7738 effect(DEF dst, USE src1, USE src2); 7739 format %{ "ADD $dst, $src1, $src2 \t// long" %} 7740 size(4); 7741 ins_encode %{ 7742 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7743 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7744 %} 7745 ins_pipe(pipe_class_default); 7746 %} 7747 7748 instruct tree_addL_addL_addL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2, iRegLsrc src3, iRegLsrc src4) %{ 7749 match(Set dst (AddL (AddL (AddL src1 src2) src3) src4)); 7750 ins_cost(DEFAULT_COST*3); 7751 7752 expand %{ 7753 // FIXME: we should do this in the ideal world. 7754 iRegLdst tmp1; 7755 iRegLdst tmp2; 7756 addL_reg_reg(tmp1, src1, src2); 7757 addL_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 7758 addL_reg_reg(dst, tmp1, tmp2); 7759 %} 7760 %} 7761 7762 // AddL + ConvL2I. 7763 instruct addI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7764 match(Set dst (ConvL2I (AddL src1 src2))); 7765 7766 format %{ "ADD $dst, $src1, $src2 \t// long + l2i" %} 7767 size(4); 7768 ins_encode %{ 7769 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7770 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7771 %} 7772 ins_pipe(pipe_class_default); 7773 %} 7774 7775 // No constant pool entries required. 7776 instruct addL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 7777 match(Set dst (AddL src1 src2)); 7778 7779 format %{ "ADDI $dst, $src1, $src2" %} 7780 size(4); 7781 ins_encode %{ 7782 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7783 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7784 %} 7785 ins_pipe(pipe_class_default); 7786 %} 7787 7788 // Long Immediate Addition with 16-bit shifted operand. 7789 // No constant pool entries required. 7790 instruct addL_reg_immhi16(iRegLdst dst, iRegLsrc src1, immL32hi16 src2) %{ 7791 match(Set dst (AddL src1 src2)); 7792 7793 format %{ "ADDIS $dst, $src1, $src2" %} 7794 size(4); 7795 ins_encode %{ 7796 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7797 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7798 %} 7799 ins_pipe(pipe_class_default); 7800 %} 7801 7802 // Pointer Register Addition 7803 instruct addP_reg_reg(iRegPdst dst, iRegP_N2P src1, iRegLsrc src2) %{ 7804 match(Set dst (AddP src1 src2)); 7805 format %{ "ADD $dst, $src1, $src2" %} 7806 size(4); 7807 ins_encode %{ 7808 // TODO: PPC port $archOpcode(ppc64Opcode_add); 7809 __ add($dst$$Register, $src1$$Register, $src2$$Register); 7810 %} 7811 ins_pipe(pipe_class_default); 7812 %} 7813 7814 // Pointer Immediate Addition 7815 // No constant pool entries required. 7816 instruct addP_reg_imm16(iRegPdst dst, iRegP_N2P src1, immL16 src2) %{ 7817 match(Set dst (AddP src1 src2)); 7818 7819 format %{ "ADDI $dst, $src1, $src2" %} 7820 size(4); 7821 ins_encode %{ 7822 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 7823 __ addi($dst$$Register, $src1$$Register, $src2$$constant); 7824 %} 7825 ins_pipe(pipe_class_default); 7826 %} 7827 7828 // Pointer Immediate Addition with 16-bit shifted operand. 7829 // No constant pool entries required. 7830 instruct addP_reg_immhi16(iRegPdst dst, iRegP_N2P src1, immL32hi16 src2) %{ 7831 match(Set dst (AddP src1 src2)); 7832 7833 format %{ "ADDIS $dst, $src1, $src2" %} 7834 size(4); 7835 ins_encode %{ 7836 // TODO: PPC port $archOpcode(ppc64Opcode_addis); 7837 __ addis($dst$$Register, $src1$$Register, ($src2$$constant)>>16); 7838 %} 7839 ins_pipe(pipe_class_default); 7840 %} 7841 7842 //--------------------- 7843 // Subtraction Instructions 7844 7845 // Register Subtraction 7846 instruct subI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 7847 match(Set dst (SubI src1 src2)); 7848 format %{ "SUBF $dst, $src2, $src1" %} 7849 size(4); 7850 ins_encode %{ 7851 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7852 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7853 %} 7854 ins_pipe(pipe_class_default); 7855 %} 7856 7857 // Immediate Subtraction 7858 // Immediate Subtraction: The compiler converts "x-c0" into "x+ -c0" (see SubLNode::Ideal), 7859 // Don't try to use addi with - $src2$$constant since it can overflow when $src2$$constant == minI16. 7860 7861 // SubI from constant (using subfic). 7862 instruct subI_imm16_reg(iRegIdst dst, immI16 src1, iRegIsrc src2) %{ 7863 match(Set dst (SubI src1 src2)); 7864 format %{ "SUBI $dst, $src1, $src2" %} 7865 7866 size(4); 7867 ins_encode %{ 7868 // TODO: PPC port $archOpcode(ppc64Opcode_subfic); 7869 __ subfic($dst$$Register, $src2$$Register, $src1$$constant); 7870 %} 7871 ins_pipe(pipe_class_default); 7872 %} 7873 7874 // Turn the sign-bit of an integer into a 32-bit mask, 0x0...0 for 7875 // positive integers and 0xF...F for negative ones. 7876 instruct signmask32I_regI(iRegIdst dst, iRegIsrc src) %{ 7877 // no match-rule, false predicate 7878 effect(DEF dst, USE src); 7879 predicate(false); 7880 7881 format %{ "SRAWI $dst, $src, #31" %} 7882 size(4); 7883 ins_encode %{ 7884 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 7885 __ srawi($dst$$Register, $src$$Register, 0x1f); 7886 %} 7887 ins_pipe(pipe_class_default); 7888 %} 7889 7890 instruct absI_reg_Ex(iRegIdst dst, iRegIsrc src) %{ 7891 match(Set dst (AbsI src)); 7892 ins_cost(DEFAULT_COST*3); 7893 7894 expand %{ 7895 iRegIdst tmp1; 7896 iRegIdst tmp2; 7897 signmask32I_regI(tmp1, src); 7898 xorI_reg_reg(tmp2, tmp1, src); 7899 subI_reg_reg(dst, tmp2, tmp1); 7900 %} 7901 %} 7902 7903 instruct negI_regI(iRegIdst dst, immI_0 zero, iRegIsrc src2) %{ 7904 match(Set dst (SubI zero src2)); 7905 format %{ "NEG $dst, $src2" %} 7906 size(4); 7907 ins_encode %{ 7908 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7909 __ neg($dst$$Register, $src2$$Register); 7910 %} 7911 ins_pipe(pipe_class_default); 7912 %} 7913 7914 // Long subtraction 7915 instruct subL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7916 match(Set dst (SubL src1 src2)); 7917 format %{ "SUBF $dst, $src2, $src1 \t// long" %} 7918 size(4); 7919 ins_encode %{ 7920 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7921 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7922 %} 7923 ins_pipe(pipe_class_default); 7924 %} 7925 7926 // SubL + convL2I. 7927 instruct subI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 7928 match(Set dst (ConvL2I (SubL src1 src2))); 7929 7930 format %{ "SUBF $dst, $src2, $src1 \t// long + l2i" %} 7931 size(4); 7932 ins_encode %{ 7933 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 7934 __ subf($dst$$Register, $src2$$Register, $src1$$Register); 7935 %} 7936 ins_pipe(pipe_class_default); 7937 %} 7938 7939 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7940 // positive longs and 0xF...F for negative ones. 7941 instruct signmask64I_regL(iRegIdst dst, iRegLsrc src) %{ 7942 // no match-rule, false predicate 7943 effect(DEF dst, USE src); 7944 predicate(false); 7945 7946 format %{ "SRADI $dst, $src, #63" %} 7947 size(4); 7948 ins_encode %{ 7949 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7950 __ sradi($dst$$Register, $src$$Register, 0x3f); 7951 %} 7952 ins_pipe(pipe_class_default); 7953 %} 7954 7955 // Turn the sign-bit of a long into a 64-bit mask, 0x0...0 for 7956 // positive longs and 0xF...F for negative ones. 7957 instruct signmask64L_regL(iRegLdst dst, iRegLsrc src) %{ 7958 // no match-rule, false predicate 7959 effect(DEF dst, USE src); 7960 predicate(false); 7961 7962 format %{ "SRADI $dst, $src, #63" %} 7963 size(4); 7964 ins_encode %{ 7965 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 7966 __ sradi($dst$$Register, $src$$Register, 0x3f); 7967 %} 7968 ins_pipe(pipe_class_default); 7969 %} 7970 7971 // Long negation 7972 instruct negL_reg_reg(iRegLdst dst, immL_0 zero, iRegLsrc src2) %{ 7973 match(Set dst (SubL zero src2)); 7974 format %{ "NEG $dst, $src2 \t// long" %} 7975 size(4); 7976 ins_encode %{ 7977 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7978 __ neg($dst$$Register, $src2$$Register); 7979 %} 7980 ins_pipe(pipe_class_default); 7981 %} 7982 7983 // NegL + ConvL2I. 7984 instruct negI_con0_regL(iRegIdst dst, immL_0 zero, iRegLsrc src2) %{ 7985 match(Set dst (ConvL2I (SubL zero src2))); 7986 7987 format %{ "NEG $dst, $src2 \t// long + l2i" %} 7988 size(4); 7989 ins_encode %{ 7990 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 7991 __ neg($dst$$Register, $src2$$Register); 7992 %} 7993 ins_pipe(pipe_class_default); 7994 %} 7995 7996 // Multiplication Instructions 7997 // Integer Multiplication 7998 7999 // Register Multiplication 8000 instruct mulI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8001 match(Set dst (MulI src1 src2)); 8002 ins_cost(DEFAULT_COST); 8003 8004 format %{ "MULLW $dst, $src1, $src2" %} 8005 size(4); 8006 ins_encode %{ 8007 // TODO: PPC port $archOpcode(ppc64Opcode_mullw); 8008 __ mullw($dst$$Register, $src1$$Register, $src2$$Register); 8009 %} 8010 ins_pipe(pipe_class_default); 8011 %} 8012 8013 // Immediate Multiplication 8014 instruct mulI_reg_imm16(iRegIdst dst, iRegIsrc src1, immI16 src2) %{ 8015 match(Set dst (MulI src1 src2)); 8016 ins_cost(DEFAULT_COST); 8017 8018 format %{ "MULLI $dst, $src1, $src2" %} 8019 size(4); 8020 ins_encode %{ 8021 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8022 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8023 %} 8024 ins_pipe(pipe_class_default); 8025 %} 8026 8027 instruct mulL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8028 match(Set dst (MulL src1 src2)); 8029 ins_cost(DEFAULT_COST); 8030 8031 format %{ "MULLD $dst $src1, $src2 \t// long" %} 8032 size(4); 8033 ins_encode %{ 8034 // TODO: PPC port $archOpcode(ppc64Opcode_mulld); 8035 __ mulld($dst$$Register, $src1$$Register, $src2$$Register); 8036 %} 8037 ins_pipe(pipe_class_default); 8038 %} 8039 8040 // Multiply high for optimized long division by constant. 8041 instruct mulHighL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8042 match(Set dst (MulHiL src1 src2)); 8043 ins_cost(DEFAULT_COST); 8044 8045 format %{ "MULHD $dst $src1, $src2 \t// long" %} 8046 size(4); 8047 ins_encode %{ 8048 // TODO: PPC port $archOpcode(ppc64Opcode_mulhd); 8049 __ mulhd($dst$$Register, $src1$$Register, $src2$$Register); 8050 %} 8051 ins_pipe(pipe_class_default); 8052 %} 8053 8054 // Immediate Multiplication 8055 instruct mulL_reg_imm16(iRegLdst dst, iRegLsrc src1, immL16 src2) %{ 8056 match(Set dst (MulL src1 src2)); 8057 ins_cost(DEFAULT_COST); 8058 8059 format %{ "MULLI $dst, $src1, $src2" %} 8060 size(4); 8061 ins_encode %{ 8062 // TODO: PPC port $archOpcode(ppc64Opcode_mulli); 8063 __ mulli($dst$$Register, $src1$$Register, $src2$$constant); 8064 %} 8065 ins_pipe(pipe_class_default); 8066 %} 8067 8068 // Integer Division with Immediate -1: Negate. 8069 instruct divI_reg_immIvalueMinus1(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 8070 match(Set dst (DivI src1 src2)); 8071 ins_cost(DEFAULT_COST); 8072 8073 format %{ "NEG $dst, $src1 \t// /-1" %} 8074 size(4); 8075 ins_encode %{ 8076 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8077 __ neg($dst$$Register, $src1$$Register); 8078 %} 8079 ins_pipe(pipe_class_default); 8080 %} 8081 8082 // Integer Division with constant, but not -1. 8083 // We should be able to improve this by checking the type of src2. 8084 // It might well be that src2 is known to be positive. 8085 instruct divI_reg_regnotMinus1(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8086 match(Set dst (DivI src1 src2)); 8087 predicate(n->in(2)->find_int_con(-1) != -1); // src2 is a constant, but not -1 8088 ins_cost(2*DEFAULT_COST); 8089 8090 format %{ "DIVW $dst, $src1, $src2 \t// /not-1" %} 8091 size(4); 8092 ins_encode %{ 8093 // TODO: PPC port $archOpcode(ppc64Opcode_divw); 8094 __ divw($dst$$Register, $src1$$Register, $src2$$Register); 8095 %} 8096 ins_pipe(pipe_class_default); 8097 %} 8098 8099 instruct cmovI_bne_negI_reg(iRegIdst dst, flagsRegSrc crx, iRegIsrc src1) %{ 8100 effect(USE_DEF dst, USE src1, USE crx); 8101 predicate(false); 8102 8103 ins_variable_size_depending_on_alignment(true); 8104 8105 format %{ "CMOVE $dst, neg($src1), $crx" %} 8106 // Worst case is branch + move + stop, no stop without scheduler. 8107 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8108 ins_encode %{ 8109 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8110 Label done; 8111 __ bne($crx$$CondRegister, done); 8112 __ neg($dst$$Register, $src1$$Register); 8113 // TODO PPC port __ endgroup_if_needed(_size == 12); 8114 __ bind(done); 8115 %} 8116 ins_pipe(pipe_class_default); 8117 %} 8118 8119 // Integer Division with Registers not containing constants. 8120 instruct divI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8121 match(Set dst (DivI src1 src2)); 8122 ins_cost(10*DEFAULT_COST); 8123 8124 expand %{ 8125 immI16 imm %{ (int)-1 %} 8126 flagsReg tmp1; 8127 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8128 divI_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8129 cmovI_bne_negI_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8130 %} 8131 %} 8132 8133 // Long Division with Immediate -1: Negate. 8134 instruct divL_reg_immLvalueMinus1(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 8135 match(Set dst (DivL src1 src2)); 8136 ins_cost(DEFAULT_COST); 8137 8138 format %{ "NEG $dst, $src1 \t// /-1, long" %} 8139 size(4); 8140 ins_encode %{ 8141 // TODO: PPC port $archOpcode(ppc64Opcode_neg); 8142 __ neg($dst$$Register, $src1$$Register); 8143 %} 8144 ins_pipe(pipe_class_default); 8145 %} 8146 8147 // Long Division with constant, but not -1. 8148 instruct divL_reg_regnotMinus1(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8149 match(Set dst (DivL src1 src2)); 8150 predicate(n->in(2)->find_long_con(-1L) != -1L); // Src2 is a constant, but not -1. 8151 ins_cost(2*DEFAULT_COST); 8152 8153 format %{ "DIVD $dst, $src1, $src2 \t// /not-1, long" %} 8154 size(4); 8155 ins_encode %{ 8156 // TODO: PPC port $archOpcode(ppc64Opcode_divd); 8157 __ divd($dst$$Register, $src1$$Register, $src2$$Register); 8158 %} 8159 ins_pipe(pipe_class_default); 8160 %} 8161 8162 instruct cmovL_bne_negL_reg(iRegLdst dst, flagsRegSrc crx, iRegLsrc src1) %{ 8163 effect(USE_DEF dst, USE src1, USE crx); 8164 predicate(false); 8165 8166 ins_variable_size_depending_on_alignment(true); 8167 8168 format %{ "CMOVE $dst, neg($src1), $crx" %} 8169 // Worst case is branch + move + stop, no stop without scheduler. 8170 size(false /* TODO: PPC PORT (InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 8171 ins_encode %{ 8172 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 8173 Label done; 8174 __ bne($crx$$CondRegister, done); 8175 __ neg($dst$$Register, $src1$$Register); 8176 // TODO PPC port __ endgroup_if_needed(_size == 12); 8177 __ bind(done); 8178 %} 8179 ins_pipe(pipe_class_default); 8180 %} 8181 8182 // Long Division with Registers not containing constants. 8183 instruct divL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8184 match(Set dst (DivL src1 src2)); 8185 ins_cost(10*DEFAULT_COST); 8186 8187 expand %{ 8188 immL16 imm %{ (int)-1 %} 8189 flagsReg tmp1; 8190 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8191 divL_reg_regnotMinus1(dst, src1, src2); // dst = src1 / src2 8192 cmovL_bne_negL_reg(dst, tmp1, src1); // cmove dst = neg(src1) if src2 == -1 8193 %} 8194 %} 8195 8196 // Integer Remainder with registers. 8197 instruct modI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8198 match(Set dst (ModI src1 src2)); 8199 ins_cost(10*DEFAULT_COST); 8200 8201 expand %{ 8202 immI16 imm %{ (int)-1 %} 8203 flagsReg tmp1; 8204 iRegIdst tmp2; 8205 iRegIdst tmp3; 8206 cmpI_reg_imm16(tmp1, src2, imm); // check src2 == -1 8207 divI_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8208 cmovI_bne_negI_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8209 mulI_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8210 subI_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8211 %} 8212 %} 8213 8214 // Long Remainder with registers 8215 instruct modL_reg_reg_Ex(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8216 match(Set dst (ModL src1 src2)); 8217 ins_cost(10*DEFAULT_COST); 8218 8219 expand %{ 8220 immL16 imm %{ (int)-1 %} 8221 flagsReg tmp1; 8222 iRegLdst tmp2; 8223 iRegLdst tmp3; 8224 cmpL_reg_imm16(tmp1, src2, imm); // check src2 == -1 8225 divL_reg_regnotMinus1(tmp2, src1, src2); // tmp2 = src1 / src2 8226 cmovL_bne_negL_reg(tmp2, tmp1, src1); // cmove tmp2 = neg(src1) if src2 == -1 8227 mulL_reg_reg(tmp3, src2, tmp2); // tmp3 = src2 * tmp2 8228 subL_reg_reg(dst, src1, tmp3); // dst = src1 - tmp3 8229 %} 8230 %} 8231 8232 // Integer Shift Instructions 8233 8234 // Register Shift Left 8235 8236 // Clear all but the lowest #mask bits. 8237 // Used to normalize shift amounts in registers. 8238 instruct maskI_reg_imm(iRegIdst dst, iRegIsrc src, uimmI6 mask) %{ 8239 // no match-rule, false predicate 8240 effect(DEF dst, USE src, USE mask); 8241 predicate(false); 8242 8243 format %{ "MASK $dst, $src, $mask \t// clear $mask upper bits" %} 8244 size(4); 8245 ins_encode %{ 8246 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8247 __ clrldi($dst$$Register, $src$$Register, $mask$$constant); 8248 %} 8249 ins_pipe(pipe_class_default); 8250 %} 8251 8252 instruct lShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8253 // no match-rule, false predicate 8254 effect(DEF dst, USE src1, USE src2); 8255 predicate(false); 8256 8257 format %{ "SLW $dst, $src1, $src2" %} 8258 size(4); 8259 ins_encode %{ 8260 // TODO: PPC port $archOpcode(ppc64Opcode_slw); 8261 __ slw($dst$$Register, $src1$$Register, $src2$$Register); 8262 %} 8263 ins_pipe(pipe_class_default); 8264 %} 8265 8266 instruct lShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8267 match(Set dst (LShiftI src1 src2)); 8268 ins_cost(DEFAULT_COST*2); 8269 expand %{ 8270 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8271 iRegIdst tmpI; 8272 maskI_reg_imm(tmpI, src2, mask); 8273 lShiftI_reg_reg(dst, src1, tmpI); 8274 %} 8275 %} 8276 8277 // Register Shift Left Immediate 8278 instruct lShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8279 match(Set dst (LShiftI src1 src2)); 8280 8281 format %{ "SLWI $dst, $src1, ($src2 & 0x1f)" %} 8282 size(4); 8283 ins_encode %{ 8284 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8285 __ slwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8286 %} 8287 ins_pipe(pipe_class_default); 8288 %} 8289 8290 // AndI with negpow2-constant + LShiftI 8291 instruct lShiftI_andI_immInegpow2_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8292 match(Set dst (LShiftI (AndI src1 src2) src3)); 8293 predicate(UseRotateAndMaskInstructionsPPC64); 8294 8295 format %{ "RLWINM $dst, lShiftI(AndI($src1, $src2), $src3)" %} 8296 size(4); 8297 ins_encode %{ 8298 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8299 long src2 = $src2$$constant; 8300 long src3 = $src3$$constant; 8301 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8302 if (maskbits >= 32) { 8303 __ li($dst$$Register, 0); // addi 8304 } else { 8305 __ rlwinm($dst$$Register, $src1$$Register, src3 & 0x1f, 0, (31-maskbits) & 0x1f); 8306 } 8307 %} 8308 ins_pipe(pipe_class_default); 8309 %} 8310 8311 // RShiftI + AndI with negpow2-constant + LShiftI 8312 instruct lShiftI_andI_immInegpow2_rShiftI_imm5(iRegIdst dst, iRegIsrc src1, immInegpow2 src2, uimmI5 src3) %{ 8313 match(Set dst (LShiftI (AndI (RShiftI src1 src3) src2) src3)); 8314 predicate(UseRotateAndMaskInstructionsPPC64); 8315 8316 format %{ "RLWINM $dst, lShiftI(AndI(RShiftI($src1, $src3), $src2), $src3)" %} 8317 size(4); 8318 ins_encode %{ 8319 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); // FIXME: assert that rlwinm is equal to addi 8320 long src2 = $src2$$constant; 8321 long src3 = $src3$$constant; 8322 long maskbits = src3 + log2_long((jlong) (julong) (juint) -src2); 8323 if (maskbits >= 32) { 8324 __ li($dst$$Register, 0); // addi 8325 } else { 8326 __ rlwinm($dst$$Register, $src1$$Register, 0, 0, (31-maskbits) & 0x1f); 8327 } 8328 %} 8329 ins_pipe(pipe_class_default); 8330 %} 8331 8332 instruct lShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8333 // no match-rule, false predicate 8334 effect(DEF dst, USE src1, USE src2); 8335 predicate(false); 8336 8337 format %{ "SLD $dst, $src1, $src2" %} 8338 size(4); 8339 ins_encode %{ 8340 // TODO: PPC port $archOpcode(ppc64Opcode_sld); 8341 __ sld($dst$$Register, $src1$$Register, $src2$$Register); 8342 %} 8343 ins_pipe(pipe_class_default); 8344 %} 8345 8346 // Register Shift Left 8347 instruct lShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8348 match(Set dst (LShiftL src1 src2)); 8349 ins_cost(DEFAULT_COST*2); 8350 expand %{ 8351 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8352 iRegIdst tmpI; 8353 maskI_reg_imm(tmpI, src2, mask); 8354 lShiftL_regL_regI(dst, src1, tmpI); 8355 %} 8356 %} 8357 8358 // Register Shift Left Immediate 8359 instruct lshiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8360 match(Set dst (LShiftL src1 src2)); 8361 format %{ "SLDI $dst, $src1, ($src2 & 0x3f)" %} 8362 size(4); 8363 ins_encode %{ 8364 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8365 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8366 %} 8367 ins_pipe(pipe_class_default); 8368 %} 8369 8370 // If we shift more than 32 bits, we need not convert I2L. 8371 instruct lShiftL_regI_immGE32(iRegLdst dst, iRegIsrc src1, uimmI6_ge32 src2) %{ 8372 match(Set dst (LShiftL (ConvI2L src1) src2)); 8373 ins_cost(DEFAULT_COST); 8374 8375 size(4); 8376 format %{ "SLDI $dst, i2l($src1), $src2" %} 8377 ins_encode %{ 8378 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8379 __ sldi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8380 %} 8381 ins_pipe(pipe_class_default); 8382 %} 8383 8384 // Shift a postivie int to the left. 8385 // Clrlsldi clears the upper 32 bits and shifts. 8386 instruct scaledPositiveI2L_lShiftL_convI2L_reg_imm6(iRegLdst dst, iRegIsrc src1, uimmI6 src2) %{ 8387 match(Set dst (LShiftL (ConvI2L src1) src2)); 8388 predicate(((ConvI2LNode*)(_kids[0]->_leaf))->type()->is_long()->is_positive_int()); 8389 8390 format %{ "SLDI $dst, i2l(positive_int($src1)), $src2" %} 8391 size(4); 8392 ins_encode %{ 8393 // TODO: PPC port $archOpcode(ppc64Opcode_rldic); 8394 __ clrlsldi($dst$$Register, $src1$$Register, 0x20, $src2$$constant); 8395 %} 8396 ins_pipe(pipe_class_default); 8397 %} 8398 8399 instruct arShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8400 // no match-rule, false predicate 8401 effect(DEF dst, USE src1, USE src2); 8402 predicate(false); 8403 8404 format %{ "SRAW $dst, $src1, $src2" %} 8405 size(4); 8406 ins_encode %{ 8407 // TODO: PPC port $archOpcode(ppc64Opcode_sraw); 8408 __ sraw($dst$$Register, $src1$$Register, $src2$$Register); 8409 %} 8410 ins_pipe(pipe_class_default); 8411 %} 8412 8413 // Register Arithmetic Shift Right 8414 instruct arShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8415 match(Set dst (RShiftI src1 src2)); 8416 ins_cost(DEFAULT_COST*2); 8417 expand %{ 8418 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8419 iRegIdst tmpI; 8420 maskI_reg_imm(tmpI, src2, mask); 8421 arShiftI_reg_reg(dst, src1, tmpI); 8422 %} 8423 %} 8424 8425 // Register Arithmetic Shift Right Immediate 8426 instruct arShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8427 match(Set dst (RShiftI src1 src2)); 8428 8429 format %{ "SRAWI $dst, $src1, ($src2 & 0x1f)" %} 8430 size(4); 8431 ins_encode %{ 8432 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 8433 __ srawi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8434 %} 8435 ins_pipe(pipe_class_default); 8436 %} 8437 8438 instruct arShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8439 // no match-rule, false predicate 8440 effect(DEF dst, USE src1, USE src2); 8441 predicate(false); 8442 8443 format %{ "SRAD $dst, $src1, $src2" %} 8444 size(4); 8445 ins_encode %{ 8446 // TODO: PPC port $archOpcode(ppc64Opcode_srad); 8447 __ srad($dst$$Register, $src1$$Register, $src2$$Register); 8448 %} 8449 ins_pipe(pipe_class_default); 8450 %} 8451 8452 // Register Shift Right Arithmetic Long 8453 instruct arShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8454 match(Set dst (RShiftL src1 src2)); 8455 ins_cost(DEFAULT_COST*2); 8456 8457 expand %{ 8458 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8459 iRegIdst tmpI; 8460 maskI_reg_imm(tmpI, src2, mask); 8461 arShiftL_regL_regI(dst, src1, tmpI); 8462 %} 8463 %} 8464 8465 // Register Shift Right Immediate 8466 instruct arShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8467 match(Set dst (RShiftL src1 src2)); 8468 8469 format %{ "SRADI $dst, $src1, ($src2 & 0x3f)" %} 8470 size(4); 8471 ins_encode %{ 8472 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8473 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8474 %} 8475 ins_pipe(pipe_class_default); 8476 %} 8477 8478 // RShiftL + ConvL2I 8479 instruct convL2I_arShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8480 match(Set dst (ConvL2I (RShiftL src1 src2))); 8481 8482 format %{ "SRADI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8483 size(4); 8484 ins_encode %{ 8485 // TODO: PPC port $archOpcode(ppc64Opcode_sradi); 8486 __ sradi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8487 %} 8488 ins_pipe(pipe_class_default); 8489 %} 8490 8491 instruct urShiftI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8492 // no match-rule, false predicate 8493 effect(DEF dst, USE src1, USE src2); 8494 predicate(false); 8495 8496 format %{ "SRW $dst, $src1, $src2" %} 8497 size(4); 8498 ins_encode %{ 8499 // TODO: PPC port $archOpcode(ppc64Opcode_srw); 8500 __ srw($dst$$Register, $src1$$Register, $src2$$Register); 8501 %} 8502 ins_pipe(pipe_class_default); 8503 %} 8504 8505 // Register Shift Right 8506 instruct urShiftI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8507 match(Set dst (URShiftI src1 src2)); 8508 ins_cost(DEFAULT_COST*2); 8509 8510 expand %{ 8511 uimmI6 mask %{ 0x3b /* clear 59 bits, keep 5 */ %} 8512 iRegIdst tmpI; 8513 maskI_reg_imm(tmpI, src2, mask); 8514 urShiftI_reg_reg(dst, src1, tmpI); 8515 %} 8516 %} 8517 8518 // Register Shift Right Immediate 8519 instruct urShiftI_reg_imm(iRegIdst dst, iRegIsrc src1, immI src2) %{ 8520 match(Set dst (URShiftI src1 src2)); 8521 8522 format %{ "SRWI $dst, $src1, ($src2 & 0x1f)" %} 8523 size(4); 8524 ins_encode %{ 8525 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8526 __ srwi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x1f); 8527 %} 8528 ins_pipe(pipe_class_default); 8529 %} 8530 8531 instruct urShiftL_regL_regI(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8532 // no match-rule, false predicate 8533 effect(DEF dst, USE src1, USE src2); 8534 predicate(false); 8535 8536 format %{ "SRD $dst, $src1, $src2" %} 8537 size(4); 8538 ins_encode %{ 8539 // TODO: PPC port $archOpcode(ppc64Opcode_srd); 8540 __ srd($dst$$Register, $src1$$Register, $src2$$Register); 8541 %} 8542 ins_pipe(pipe_class_default); 8543 %} 8544 8545 // Register Shift Right 8546 instruct urShiftL_regL_regI_Ex(iRegLdst dst, iRegLsrc src1, iRegIsrc src2) %{ 8547 match(Set dst (URShiftL src1 src2)); 8548 ins_cost(DEFAULT_COST*2); 8549 8550 expand %{ 8551 uimmI6 mask %{ 0x3a /* clear 58 bits, keep 6 */ %} 8552 iRegIdst tmpI; 8553 maskI_reg_imm(tmpI, src2, mask); 8554 urShiftL_regL_regI(dst, src1, tmpI); 8555 %} 8556 %} 8557 8558 // Register Shift Right Immediate 8559 instruct urShiftL_regL_immI(iRegLdst dst, iRegLsrc src1, immI src2) %{ 8560 match(Set dst (URShiftL src1 src2)); 8561 8562 format %{ "SRDI $dst, $src1, ($src2 & 0x3f)" %} 8563 size(4); 8564 ins_encode %{ 8565 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8566 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8567 %} 8568 ins_pipe(pipe_class_default); 8569 %} 8570 8571 // URShiftL + ConvL2I. 8572 instruct convL2I_urShiftL_regL_immI(iRegIdst dst, iRegLsrc src1, immI src2) %{ 8573 match(Set dst (ConvL2I (URShiftL src1 src2))); 8574 8575 format %{ "SRDI $dst, $src1, ($src2 & 0x3f) \t// long + l2i" %} 8576 size(4); 8577 ins_encode %{ 8578 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8579 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8580 %} 8581 ins_pipe(pipe_class_default); 8582 %} 8583 8584 // Register Shift Right Immediate with a CastP2X 8585 instruct shrP_convP2X_reg_imm6(iRegLdst dst, iRegP_N2P src1, uimmI6 src2) %{ 8586 match(Set dst (URShiftL (CastP2X src1) src2)); 8587 8588 format %{ "SRDI $dst, $src1, $src2 \t// Cast ptr $src1 to long and shift" %} 8589 size(4); 8590 ins_encode %{ 8591 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8592 __ srdi($dst$$Register, $src1$$Register, ($src2$$constant) & 0x3f); 8593 %} 8594 ins_pipe(pipe_class_default); 8595 %} 8596 8597 instruct sxtI_reg(iRegIdst dst, iRegIsrc src) %{ 8598 match(Set dst (ConvL2I (ConvI2L src))); 8599 8600 format %{ "EXTSW $dst, $src \t// int->int" %} 8601 size(4); 8602 ins_encode %{ 8603 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 8604 __ extsw($dst$$Register, $src$$Register); 8605 %} 8606 ins_pipe(pipe_class_default); 8607 %} 8608 8609 //----------Rotate Instructions------------------------------------------------ 8610 8611 // Rotate Left by 8-bit immediate 8612 instruct rotlI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 lshift, immI8 rshift) %{ 8613 match(Set dst (OrI (LShiftI src lshift) (URShiftI src rshift))); 8614 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8615 8616 format %{ "ROTLWI $dst, $src, $lshift" %} 8617 size(4); 8618 ins_encode %{ 8619 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8620 __ rotlwi($dst$$Register, $src$$Register, $lshift$$constant); 8621 %} 8622 ins_pipe(pipe_class_default); 8623 %} 8624 8625 // Rotate Right by 8-bit immediate 8626 instruct rotrI_reg_immi8(iRegIdst dst, iRegIsrc src, immI8 rshift, immI8 lshift) %{ 8627 match(Set dst (OrI (URShiftI src rshift) (LShiftI src lshift))); 8628 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f)); 8629 8630 format %{ "ROTRWI $dst, $rshift" %} 8631 size(4); 8632 ins_encode %{ 8633 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8634 __ rotrwi($dst$$Register, $src$$Register, $rshift$$constant); 8635 %} 8636 ins_pipe(pipe_class_default); 8637 %} 8638 8639 //----------Floating Point Arithmetic Instructions----------------------------- 8640 8641 // Add float single precision 8642 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{ 8643 match(Set dst (AddF src1 src2)); 8644 8645 format %{ "FADDS $dst, $src1, $src2" %} 8646 size(4); 8647 ins_encode %{ 8648 // TODO: PPC port $archOpcode(ppc64Opcode_fadds); 8649 __ fadds($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8650 %} 8651 ins_pipe(pipe_class_default); 8652 %} 8653 8654 // Add float double precision 8655 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{ 8656 match(Set dst (AddD src1 src2)); 8657 8658 format %{ "FADD $dst, $src1, $src2" %} 8659 size(4); 8660 ins_encode %{ 8661 // TODO: PPC port $archOpcode(ppc64Opcode_fadd); 8662 __ fadd($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8663 %} 8664 ins_pipe(pipe_class_default); 8665 %} 8666 8667 // Sub float single precision 8668 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{ 8669 match(Set dst (SubF src1 src2)); 8670 8671 format %{ "FSUBS $dst, $src1, $src2" %} 8672 size(4); 8673 ins_encode %{ 8674 // TODO: PPC port $archOpcode(ppc64Opcode_fsubs); 8675 __ fsubs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8676 %} 8677 ins_pipe(pipe_class_default); 8678 %} 8679 8680 // Sub float double precision 8681 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{ 8682 match(Set dst (SubD src1 src2)); 8683 format %{ "FSUB $dst, $src1, $src2" %} 8684 size(4); 8685 ins_encode %{ 8686 // TODO: PPC port $archOpcode(ppc64Opcode_fsub); 8687 __ fsub($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8688 %} 8689 ins_pipe(pipe_class_default); 8690 %} 8691 8692 // Mul float single precision 8693 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{ 8694 match(Set dst (MulF src1 src2)); 8695 format %{ "FMULS $dst, $src1, $src2" %} 8696 size(4); 8697 ins_encode %{ 8698 // TODO: PPC port $archOpcode(ppc64Opcode_fmuls); 8699 __ fmuls($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8700 %} 8701 ins_pipe(pipe_class_default); 8702 %} 8703 8704 // Mul float double precision 8705 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{ 8706 match(Set dst (MulD src1 src2)); 8707 format %{ "FMUL $dst, $src1, $src2" %} 8708 size(4); 8709 ins_encode %{ 8710 // TODO: PPC port $archOpcode(ppc64Opcode_fmul); 8711 __ fmul($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8712 %} 8713 ins_pipe(pipe_class_default); 8714 %} 8715 8716 // Div float single precision 8717 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{ 8718 match(Set dst (DivF src1 src2)); 8719 format %{ "FDIVS $dst, $src1, $src2" %} 8720 size(4); 8721 ins_encode %{ 8722 // TODO: PPC port $archOpcode(ppc64Opcode_fdivs); 8723 __ fdivs($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8724 %} 8725 ins_pipe(pipe_class_default); 8726 %} 8727 8728 // Div float double precision 8729 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{ 8730 match(Set dst (DivD src1 src2)); 8731 format %{ "FDIV $dst, $src1, $src2" %} 8732 size(4); 8733 ins_encode %{ 8734 // TODO: PPC port $archOpcode(ppc64Opcode_fdiv); 8735 __ fdiv($dst$$FloatRegister, $src1$$FloatRegister, $src2$$FloatRegister); 8736 %} 8737 ins_pipe(pipe_class_default); 8738 %} 8739 8740 // Absolute float single precision 8741 instruct absF_reg(regF dst, regF src) %{ 8742 match(Set dst (AbsF src)); 8743 format %{ "FABS $dst, $src \t// float" %} 8744 size(4); 8745 ins_encode %{ 8746 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8747 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8748 %} 8749 ins_pipe(pipe_class_default); 8750 %} 8751 8752 // Absolute float double precision 8753 instruct absD_reg(regD dst, regD src) %{ 8754 match(Set dst (AbsD src)); 8755 format %{ "FABS $dst, $src \t// double" %} 8756 size(4); 8757 ins_encode %{ 8758 // TODO: PPC port $archOpcode(ppc64Opcode_fabs); 8759 __ fabs($dst$$FloatRegister, $src$$FloatRegister); 8760 %} 8761 ins_pipe(pipe_class_default); 8762 %} 8763 8764 instruct negF_reg(regF dst, regF src) %{ 8765 match(Set dst (NegF src)); 8766 format %{ "FNEG $dst, $src \t// float" %} 8767 size(4); 8768 ins_encode %{ 8769 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8770 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8771 %} 8772 ins_pipe(pipe_class_default); 8773 %} 8774 8775 instruct negD_reg(regD dst, regD src) %{ 8776 match(Set dst (NegD src)); 8777 format %{ "FNEG $dst, $src \t// double" %} 8778 size(4); 8779 ins_encode %{ 8780 // TODO: PPC port $archOpcode(ppc64Opcode_fneg); 8781 __ fneg($dst$$FloatRegister, $src$$FloatRegister); 8782 %} 8783 ins_pipe(pipe_class_default); 8784 %} 8785 8786 // AbsF + NegF. 8787 instruct negF_absF_reg(regF dst, regF src) %{ 8788 match(Set dst (NegF (AbsF src))); 8789 format %{ "FNABS $dst, $src \t// float" %} 8790 size(4); 8791 ins_encode %{ 8792 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8793 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8794 %} 8795 ins_pipe(pipe_class_default); 8796 %} 8797 8798 // AbsD + NegD. 8799 instruct negD_absD_reg(regD dst, regD src) %{ 8800 match(Set dst (NegD (AbsD src))); 8801 format %{ "FNABS $dst, $src \t// double" %} 8802 size(4); 8803 ins_encode %{ 8804 // TODO: PPC port $archOpcode(ppc64Opcode_fnabs); 8805 __ fnabs($dst$$FloatRegister, $src$$FloatRegister); 8806 %} 8807 ins_pipe(pipe_class_default); 8808 %} 8809 8810 // VM_Version::has_fsqrt() decides if this node will be used. 8811 // Sqrt float double precision 8812 instruct sqrtD_reg(regD dst, regD src) %{ 8813 match(Set dst (SqrtD src)); 8814 format %{ "FSQRT $dst, $src" %} 8815 size(4); 8816 ins_encode %{ 8817 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrt); 8818 __ fsqrt($dst$$FloatRegister, $src$$FloatRegister); 8819 %} 8820 ins_pipe(pipe_class_default); 8821 %} 8822 8823 // Single-precision sqrt. 8824 instruct sqrtF_reg(regF dst, regF src) %{ 8825 match(Set dst (ConvD2F (SqrtD (ConvF2D src)))); 8826 predicate(VM_Version::has_fsqrts()); 8827 ins_cost(DEFAULT_COST); 8828 8829 format %{ "FSQRTS $dst, $src" %} 8830 size(4); 8831 ins_encode %{ 8832 // TODO: PPC port $archOpcode(ppc64Opcode_fsqrts); 8833 __ fsqrts($dst$$FloatRegister, $src$$FloatRegister); 8834 %} 8835 ins_pipe(pipe_class_default); 8836 %} 8837 8838 instruct roundDouble_nop(regD dst) %{ 8839 match(Set dst (RoundDouble dst)); 8840 ins_cost(0); 8841 8842 format %{ " -- \t// RoundDouble not needed - empty" %} 8843 size(0); 8844 // PPC results are already "rounded" (i.e., normal-format IEEE). 8845 ins_encode( /*empty*/ ); 8846 ins_pipe(pipe_class_default); 8847 %} 8848 8849 instruct roundFloat_nop(regF dst) %{ 8850 match(Set dst (RoundFloat dst)); 8851 ins_cost(0); 8852 8853 format %{ " -- \t// RoundFloat not needed - empty" %} 8854 size(0); 8855 // PPC results are already "rounded" (i.e., normal-format IEEE). 8856 ins_encode( /*empty*/ ); 8857 ins_pipe(pipe_class_default); 8858 %} 8859 8860 //----------Logical Instructions----------------------------------------------- 8861 8862 // And Instructions 8863 8864 // Register And 8865 instruct andI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8866 match(Set dst (AndI src1 src2)); 8867 format %{ "AND $dst, $src1, $src2" %} 8868 size(4); 8869 ins_encode %{ 8870 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8871 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8872 %} 8873 ins_pipe(pipe_class_default); 8874 %} 8875 8876 // Immediate And 8877 instruct andI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2, flagsRegCR0 cr0) %{ 8878 match(Set dst (AndI src1 src2)); 8879 effect(KILL cr0); 8880 8881 format %{ "ANDI $dst, $src1, $src2" %} 8882 size(4); 8883 ins_encode %{ 8884 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8885 // FIXME: avoid andi_ ? 8886 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8887 %} 8888 ins_pipe(pipe_class_default); 8889 %} 8890 8891 // Immediate And where the immediate is a negative power of 2. 8892 instruct andI_reg_immInegpow2(iRegIdst dst, iRegIsrc src1, immInegpow2 src2) %{ 8893 match(Set dst (AndI src1 src2)); 8894 format %{ "ANDWI $dst, $src1, $src2" %} 8895 size(4); 8896 ins_encode %{ 8897 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8898 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)(julong)(juint)-($src2$$constant))); 8899 %} 8900 ins_pipe(pipe_class_default); 8901 %} 8902 8903 instruct andI_reg_immIpow2minus1(iRegIdst dst, iRegIsrc src1, immIpow2minus1 src2) %{ 8904 match(Set dst (AndI src1 src2)); 8905 format %{ "ANDWI $dst, $src1, $src2" %} 8906 size(4); 8907 ins_encode %{ 8908 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8909 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8910 %} 8911 ins_pipe(pipe_class_default); 8912 %} 8913 8914 instruct andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src1, immIpowerOf2 src2) %{ 8915 match(Set dst (AndI src1 src2)); 8916 predicate(UseRotateAndMaskInstructionsPPC64); 8917 format %{ "ANDWI $dst, $src1, $src2" %} 8918 size(4); 8919 ins_encode %{ 8920 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 8921 __ rlwinm($dst$$Register, $src1$$Register, 0, 8922 (31-log2_long((jlong) $src2$$constant)) & 0x1f, (31-log2_long((jlong) $src2$$constant)) & 0x1f); 8923 %} 8924 ins_pipe(pipe_class_default); 8925 %} 8926 8927 // Register And Long 8928 instruct andL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 8929 match(Set dst (AndL src1 src2)); 8930 ins_cost(DEFAULT_COST); 8931 8932 format %{ "AND $dst, $src1, $src2 \t// long" %} 8933 size(4); 8934 ins_encode %{ 8935 // TODO: PPC port $archOpcode(ppc64Opcode_and); 8936 __ andr($dst$$Register, $src1$$Register, $src2$$Register); 8937 %} 8938 ins_pipe(pipe_class_default); 8939 %} 8940 8941 // Immediate And long 8942 instruct andL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2, flagsRegCR0 cr0) %{ 8943 match(Set dst (AndL src1 src2)); 8944 effect(KILL cr0); 8945 8946 format %{ "ANDI $dst, $src1, $src2 \t// long" %} 8947 size(4); 8948 ins_encode %{ 8949 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 8950 // FIXME: avoid andi_ ? 8951 __ andi_($dst$$Register, $src1$$Register, $src2$$constant); 8952 %} 8953 ins_pipe(pipe_class_default); 8954 %} 8955 8956 // Immediate And Long where the immediate is a negative power of 2. 8957 instruct andL_reg_immLnegpow2(iRegLdst dst, iRegLsrc src1, immLnegpow2 src2) %{ 8958 match(Set dst (AndL src1 src2)); 8959 format %{ "ANDDI $dst, $src1, $src2" %} 8960 size(4); 8961 ins_encode %{ 8962 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 8963 __ clrrdi($dst$$Register, $src1$$Register, log2_long((jlong)-$src2$$constant)); 8964 %} 8965 ins_pipe(pipe_class_default); 8966 %} 8967 8968 instruct andL_reg_immLpow2minus1(iRegLdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 8969 match(Set dst (AndL src1 src2)); 8970 format %{ "ANDDI $dst, $src1, $src2" %} 8971 size(4); 8972 ins_encode %{ 8973 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8974 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8975 %} 8976 ins_pipe(pipe_class_default); 8977 %} 8978 8979 // AndL + ConvL2I. 8980 instruct convL2I_andL_reg_immLpow2minus1(iRegIdst dst, iRegLsrc src1, immLpow2minus1 src2) %{ 8981 match(Set dst (ConvL2I (AndL src1 src2))); 8982 ins_cost(DEFAULT_COST); 8983 8984 format %{ "ANDDI $dst, $src1, $src2 \t// long + l2i" %} 8985 size(4); 8986 ins_encode %{ 8987 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 8988 __ clrldi($dst$$Register, $src1$$Register, 64-log2_long((((jlong) $src2$$constant)+1))); 8989 %} 8990 ins_pipe(pipe_class_default); 8991 %} 8992 8993 // Or Instructions 8994 8995 // Register Or 8996 instruct orI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 8997 match(Set dst (OrI src1 src2)); 8998 format %{ "OR $dst, $src1, $src2" %} 8999 size(4); 9000 ins_encode %{ 9001 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9002 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9003 %} 9004 ins_pipe(pipe_class_default); 9005 %} 9006 9007 // Expand does not work with above instruct. (??) 9008 instruct orI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9009 // no match-rule 9010 effect(DEF dst, USE src1, USE src2); 9011 format %{ "OR $dst, $src1, $src2" %} 9012 size(4); 9013 ins_encode %{ 9014 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9015 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9016 %} 9017 ins_pipe(pipe_class_default); 9018 %} 9019 9020 instruct tree_orI_orI_orI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9021 match(Set dst (OrI (OrI (OrI src1 src2) src3) src4)); 9022 ins_cost(DEFAULT_COST*3); 9023 9024 expand %{ 9025 // FIXME: we should do this in the ideal world. 9026 iRegIdst tmp1; 9027 iRegIdst tmp2; 9028 orI_reg_reg(tmp1, src1, src2); 9029 orI_reg_reg_2(tmp2, src3, src4); // Adlc complains about orI_reg_reg. 9030 orI_reg_reg(dst, tmp1, tmp2); 9031 %} 9032 %} 9033 9034 // Immediate Or 9035 instruct orI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9036 match(Set dst (OrI src1 src2)); 9037 format %{ "ORI $dst, $src1, $src2" %} 9038 size(4); 9039 ins_encode %{ 9040 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9041 __ ori($dst$$Register, $src1$$Register, ($src2$$constant) & 0xFFFF); 9042 %} 9043 ins_pipe(pipe_class_default); 9044 %} 9045 9046 // Register Or Long 9047 instruct orL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9048 match(Set dst (OrL src1 src2)); 9049 ins_cost(DEFAULT_COST); 9050 9051 size(4); 9052 format %{ "OR $dst, $src1, $src2 \t// long" %} 9053 ins_encode %{ 9054 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9055 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9056 %} 9057 ins_pipe(pipe_class_default); 9058 %} 9059 9060 // OrL + ConvL2I. 9061 instruct orI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9062 match(Set dst (ConvL2I (OrL src1 src2))); 9063 ins_cost(DEFAULT_COST); 9064 9065 format %{ "OR $dst, $src1, $src2 \t// long + l2i" %} 9066 size(4); 9067 ins_encode %{ 9068 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9069 __ or_unchecked($dst$$Register, $src1$$Register, $src2$$Register); 9070 %} 9071 ins_pipe(pipe_class_default); 9072 %} 9073 9074 // Immediate Or long 9075 instruct orL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 con) %{ 9076 match(Set dst (OrL src1 con)); 9077 ins_cost(DEFAULT_COST); 9078 9079 format %{ "ORI $dst, $src1, $con \t// long" %} 9080 size(4); 9081 ins_encode %{ 9082 // TODO: PPC port $archOpcode(ppc64Opcode_ori); 9083 __ ori($dst$$Register, $src1$$Register, ($con$$constant) & 0xFFFF); 9084 %} 9085 ins_pipe(pipe_class_default); 9086 %} 9087 9088 // Xor Instructions 9089 9090 // Register Xor 9091 instruct xorI_reg_reg(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9092 match(Set dst (XorI src1 src2)); 9093 format %{ "XOR $dst, $src1, $src2" %} 9094 size(4); 9095 ins_encode %{ 9096 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9097 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9098 %} 9099 ins_pipe(pipe_class_default); 9100 %} 9101 9102 // Expand does not work with above instruct. (??) 9103 instruct xorI_reg_reg_2(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9104 // no match-rule 9105 effect(DEF dst, USE src1, USE src2); 9106 format %{ "XOR $dst, $src1, $src2" %} 9107 size(4); 9108 ins_encode %{ 9109 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9110 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9111 %} 9112 ins_pipe(pipe_class_default); 9113 %} 9114 9115 instruct tree_xorI_xorI_xorI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, iRegIsrc src3, iRegIsrc src4) %{ 9116 match(Set dst (XorI (XorI (XorI src1 src2) src3) src4)); 9117 ins_cost(DEFAULT_COST*3); 9118 9119 expand %{ 9120 // FIXME: we should do this in the ideal world. 9121 iRegIdst tmp1; 9122 iRegIdst tmp2; 9123 xorI_reg_reg(tmp1, src1, src2); 9124 xorI_reg_reg_2(tmp2, src3, src4); // Adlc complains about xorI_reg_reg. 9125 xorI_reg_reg(dst, tmp1, tmp2); 9126 %} 9127 %} 9128 9129 // Immediate Xor 9130 instruct xorI_reg_uimm16(iRegIdst dst, iRegIsrc src1, uimmI16 src2) %{ 9131 match(Set dst (XorI src1 src2)); 9132 format %{ "XORI $dst, $src1, $src2" %} 9133 size(4); 9134 ins_encode %{ 9135 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9136 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9137 %} 9138 ins_pipe(pipe_class_default); 9139 %} 9140 9141 // Register Xor Long 9142 instruct xorL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9143 match(Set dst (XorL src1 src2)); 9144 ins_cost(DEFAULT_COST); 9145 9146 format %{ "XOR $dst, $src1, $src2 \t// long" %} 9147 size(4); 9148 ins_encode %{ 9149 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9150 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9151 %} 9152 ins_pipe(pipe_class_default); 9153 %} 9154 9155 // XorL + ConvL2I. 9156 instruct xorI_regL_regL(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9157 match(Set dst (ConvL2I (XorL src1 src2))); 9158 ins_cost(DEFAULT_COST); 9159 9160 format %{ "XOR $dst, $src1, $src2 \t// long + l2i" %} 9161 size(4); 9162 ins_encode %{ 9163 // TODO: PPC port $archOpcode(ppc64Opcode_xor); 9164 __ xorr($dst$$Register, $src1$$Register, $src2$$Register); 9165 %} 9166 ins_pipe(pipe_class_default); 9167 %} 9168 9169 // Immediate Xor Long 9170 instruct xorL_reg_uimm16(iRegLdst dst, iRegLsrc src1, uimmL16 src2) %{ 9171 match(Set dst (XorL src1 src2)); 9172 ins_cost(DEFAULT_COST); 9173 9174 format %{ "XORI $dst, $src1, $src2 \t// long" %} 9175 size(4); 9176 ins_encode %{ 9177 // TODO: PPC port $archOpcode(ppc64Opcode_xori); 9178 __ xori($dst$$Register, $src1$$Register, $src2$$constant); 9179 %} 9180 ins_pipe(pipe_class_default); 9181 %} 9182 9183 instruct notI_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2) %{ 9184 match(Set dst (XorI src1 src2)); 9185 ins_cost(DEFAULT_COST); 9186 9187 format %{ "NOT $dst, $src1 ($src2)" %} 9188 size(4); 9189 ins_encode %{ 9190 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9191 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9192 %} 9193 ins_pipe(pipe_class_default); 9194 %} 9195 9196 instruct notL_reg(iRegLdst dst, iRegLsrc src1, immL_minus1 src2) %{ 9197 match(Set dst (XorL src1 src2)); 9198 ins_cost(DEFAULT_COST); 9199 9200 format %{ "NOT $dst, $src1 ($src2) \t// long" %} 9201 size(4); 9202 ins_encode %{ 9203 // TODO: PPC port $archOpcode(ppc64Opcode_nor); 9204 __ nor($dst$$Register, $src1$$Register, $src1$$Register); 9205 %} 9206 ins_pipe(pipe_class_default); 9207 %} 9208 9209 // And-complement 9210 instruct andcI_reg_reg(iRegIdst dst, iRegIsrc src1, immI_minus1 src2, iRegIsrc src3) %{ 9211 match(Set dst (AndI (XorI src1 src2) src3)); 9212 ins_cost(DEFAULT_COST); 9213 9214 format %{ "ANDW $dst, xori($src1, $src2), $src3" %} 9215 size(4); 9216 ins_encode( enc_andc(dst, src3, src1) ); 9217 ins_pipe(pipe_class_default); 9218 %} 9219 9220 // And-complement 9221 instruct andcL_reg_reg(iRegLdst dst, iRegLsrc src1, iRegLsrc src2) %{ 9222 // no match-rule, false predicate 9223 effect(DEF dst, USE src1, USE src2); 9224 predicate(false); 9225 9226 format %{ "ANDC $dst, $src1, $src2" %} 9227 size(4); 9228 ins_encode %{ 9229 // TODO: PPC port $archOpcode(ppc64Opcode_andc); 9230 __ andc($dst$$Register, $src1$$Register, $src2$$Register); 9231 %} 9232 ins_pipe(pipe_class_default); 9233 %} 9234 9235 //----------Moves between int/long and float/double---------------------------- 9236 // 9237 // The following rules move values from int/long registers/stack-locations 9238 // to float/double registers/stack-locations and vice versa, without doing any 9239 // conversions. These rules are used to implement the bit-conversion methods 9240 // of java.lang.Float etc., e.g. 9241 // int floatToIntBits(float value) 9242 // float intBitsToFloat(int bits) 9243 // 9244 // Notes on the implementation on ppc64: 9245 // We only provide rules which move between a register and a stack-location, 9246 // because we always have to go through memory when moving between a float 9247 // register and an integer register. 9248 9249 //---------- Chain stack slots between similar types -------- 9250 9251 // These are needed so that the rules below can match. 9252 9253 // Load integer from stack slot 9254 instruct stkI_to_regI(iRegIdst dst, stackSlotI src) %{ 9255 match(Set dst src); 9256 ins_cost(MEMORY_REF_COST); 9257 9258 format %{ "LWZ $dst, $src" %} 9259 size(4); 9260 ins_encode( enc_lwz(dst, src) ); 9261 ins_pipe(pipe_class_memory); 9262 %} 9263 9264 // Store integer to stack slot 9265 instruct regI_to_stkI(stackSlotI dst, iRegIsrc src) %{ 9266 match(Set dst src); 9267 ins_cost(MEMORY_REF_COST); 9268 9269 format %{ "STW $src, $dst \t// stk" %} 9270 size(4); 9271 ins_encode( enc_stw(src, dst) ); // rs=rt 9272 ins_pipe(pipe_class_memory); 9273 %} 9274 9275 // Load long from stack slot 9276 instruct stkL_to_regL(iRegLdst dst, stackSlotL src) %{ 9277 match(Set dst src); 9278 ins_cost(MEMORY_REF_COST); 9279 9280 format %{ "LD $dst, $src \t// long" %} 9281 size(4); 9282 ins_encode( enc_ld(dst, src) ); 9283 ins_pipe(pipe_class_memory); 9284 %} 9285 9286 // Store long to stack slot 9287 instruct regL_to_stkL(stackSlotL dst, iRegLsrc src) %{ 9288 match(Set dst src); 9289 ins_cost(MEMORY_REF_COST); 9290 9291 format %{ "STD $src, $dst \t// long" %} 9292 size(4); 9293 ins_encode( enc_std(src, dst) ); // rs=rt 9294 ins_pipe(pipe_class_memory); 9295 %} 9296 9297 //----------Moves between int and float 9298 9299 // Move float value from float stack-location to integer register. 9300 instruct moveF2I_stack_reg(iRegIdst dst, stackSlotF src) %{ 9301 match(Set dst (MoveF2I src)); 9302 ins_cost(MEMORY_REF_COST); 9303 9304 format %{ "LWZ $dst, $src \t// MoveF2I" %} 9305 size(4); 9306 ins_encode( enc_lwz(dst, src) ); 9307 ins_pipe(pipe_class_memory); 9308 %} 9309 9310 // Move float value from float register to integer stack-location. 9311 instruct moveF2I_reg_stack(stackSlotI dst, regF src) %{ 9312 match(Set dst (MoveF2I src)); 9313 ins_cost(MEMORY_REF_COST); 9314 9315 format %{ "STFS $src, $dst \t// MoveF2I" %} 9316 size(4); 9317 ins_encode( enc_stfs(src, dst) ); 9318 ins_pipe(pipe_class_memory); 9319 %} 9320 9321 // Move integer value from integer stack-location to float register. 9322 instruct moveI2F_stack_reg(regF dst, stackSlotI src) %{ 9323 match(Set dst (MoveI2F src)); 9324 ins_cost(MEMORY_REF_COST); 9325 9326 format %{ "LFS $dst, $src \t// MoveI2F" %} 9327 size(4); 9328 ins_encode %{ 9329 // TODO: PPC port $archOpcode(ppc64Opcode_lfs); 9330 int Idisp = $src$$disp + frame_slots_bias($src$$base, ra_); 9331 __ lfs($dst$$FloatRegister, Idisp, $src$$base$$Register); 9332 %} 9333 ins_pipe(pipe_class_memory); 9334 %} 9335 9336 // Move integer value from integer register to float stack-location. 9337 instruct moveI2F_reg_stack(stackSlotF dst, iRegIsrc src) %{ 9338 match(Set dst (MoveI2F src)); 9339 ins_cost(MEMORY_REF_COST); 9340 9341 format %{ "STW $src, $dst \t// MoveI2F" %} 9342 size(4); 9343 ins_encode( enc_stw(src, dst) ); 9344 ins_pipe(pipe_class_memory); 9345 %} 9346 9347 //----------Moves between long and float 9348 9349 instruct moveF2L_reg_stack(stackSlotL dst, regF src) %{ 9350 // no match-rule, false predicate 9351 effect(DEF dst, USE src); 9352 predicate(false); 9353 9354 format %{ "storeD $src, $dst \t// STACK" %} 9355 size(4); 9356 ins_encode( enc_stfd(src, dst) ); 9357 ins_pipe(pipe_class_default); 9358 %} 9359 9360 //----------Moves between long and double 9361 9362 // Move double value from double stack-location to long register. 9363 instruct moveD2L_stack_reg(iRegLdst dst, stackSlotD src) %{ 9364 match(Set dst (MoveD2L src)); 9365 ins_cost(MEMORY_REF_COST); 9366 size(4); 9367 format %{ "LD $dst, $src \t// MoveD2L" %} 9368 ins_encode( enc_ld(dst, src) ); 9369 ins_pipe(pipe_class_memory); 9370 %} 9371 9372 // Move double value from double register to long stack-location. 9373 instruct moveD2L_reg_stack(stackSlotL dst, regD src) %{ 9374 match(Set dst (MoveD2L src)); 9375 effect(DEF dst, USE src); 9376 ins_cost(MEMORY_REF_COST); 9377 9378 format %{ "STFD $src, $dst \t// MoveD2L" %} 9379 size(4); 9380 ins_encode( enc_stfd(src, dst) ); 9381 ins_pipe(pipe_class_memory); 9382 %} 9383 9384 // Move long value from long stack-location to double register. 9385 instruct moveL2D_stack_reg(regD dst, stackSlotL src) %{ 9386 match(Set dst (MoveL2D src)); 9387 ins_cost(MEMORY_REF_COST); 9388 9389 format %{ "LFD $dst, $src \t// MoveL2D" %} 9390 size(4); 9391 ins_encode( enc_lfd(dst, src) ); 9392 ins_pipe(pipe_class_memory); 9393 %} 9394 9395 // Move long value from long register to double stack-location. 9396 instruct moveL2D_reg_stack(stackSlotD dst, iRegLsrc src) %{ 9397 match(Set dst (MoveL2D src)); 9398 ins_cost(MEMORY_REF_COST); 9399 9400 format %{ "STD $src, $dst \t// MoveL2D" %} 9401 size(4); 9402 ins_encode( enc_std(src, dst) ); 9403 ins_pipe(pipe_class_memory); 9404 %} 9405 9406 //----------Register Move Instructions----------------------------------------- 9407 9408 // Replicate for Superword 9409 9410 instruct moveReg(iRegLdst dst, iRegIsrc src) %{ 9411 predicate(false); 9412 effect(DEF dst, USE src); 9413 9414 format %{ "MR $dst, $src \t// replicate " %} 9415 // variable size, 0 or 4. 9416 ins_encode %{ 9417 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9418 __ mr_if_needed($dst$$Register, $src$$Register); 9419 %} 9420 ins_pipe(pipe_class_default); 9421 %} 9422 9423 //----------Cast instructions (Java-level type cast)--------------------------- 9424 9425 // Cast Long to Pointer for unsafe natives. 9426 instruct castX2P(iRegPdst dst, iRegLsrc src) %{ 9427 match(Set dst (CastX2P src)); 9428 9429 format %{ "MR $dst, $src \t// Long->Ptr" %} 9430 // variable size, 0 or 4. 9431 ins_encode %{ 9432 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9433 __ mr_if_needed($dst$$Register, $src$$Register); 9434 %} 9435 ins_pipe(pipe_class_default); 9436 %} 9437 9438 // Cast Pointer to Long for unsafe natives. 9439 instruct castP2X(iRegLdst dst, iRegP_N2P src) %{ 9440 match(Set dst (CastP2X src)); 9441 9442 format %{ "MR $dst, $src \t// Ptr->Long" %} 9443 // variable size, 0 or 4. 9444 ins_encode %{ 9445 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9446 __ mr_if_needed($dst$$Register, $src$$Register); 9447 %} 9448 ins_pipe(pipe_class_default); 9449 %} 9450 9451 instruct castPP(iRegPdst dst) %{ 9452 match(Set dst (CastPP dst)); 9453 format %{ " -- \t// castPP of $dst" %} 9454 size(0); 9455 ins_encode( /*empty*/ ); 9456 ins_pipe(pipe_class_default); 9457 %} 9458 9459 instruct castII(iRegIdst dst) %{ 9460 match(Set dst (CastII dst)); 9461 format %{ " -- \t// castII of $dst" %} 9462 size(0); 9463 ins_encode( /*empty*/ ); 9464 ins_pipe(pipe_class_default); 9465 %} 9466 9467 instruct checkCastPP(iRegPdst dst) %{ 9468 match(Set dst (CheckCastPP dst)); 9469 format %{ " -- \t// checkcastPP of $dst" %} 9470 size(0); 9471 ins_encode( /*empty*/ ); 9472 ins_pipe(pipe_class_default); 9473 %} 9474 9475 //----------Convert instructions----------------------------------------------- 9476 9477 // Convert to boolean. 9478 9479 // int_to_bool(src) : { 1 if src != 0 9480 // { 0 else 9481 // 9482 // strategy: 9483 // 1) Count leading zeros of 32 bit-value src, 9484 // this returns 32 (0b10.0000) iff src == 0 and <32 otherwise. 9485 // 2) Shift 5 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9486 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9487 9488 // convI2Bool 9489 instruct convI2Bool_reg__cntlz_Ex(iRegIdst dst, iRegIsrc src) %{ 9490 match(Set dst (Conv2B src)); 9491 predicate(UseCountLeadingZerosInstructionsPPC64); 9492 ins_cost(DEFAULT_COST); 9493 9494 expand %{ 9495 immI shiftAmount %{ 0x5 %} 9496 uimmI16 mask %{ 0x1 %} 9497 iRegIdst tmp1; 9498 iRegIdst tmp2; 9499 countLeadingZerosI(tmp1, src); 9500 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9501 xorI_reg_uimm16(dst, tmp2, mask); 9502 %} 9503 %} 9504 9505 instruct convI2Bool_reg__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx) %{ 9506 match(Set dst (Conv2B src)); 9507 effect(TEMP crx); 9508 predicate(!UseCountLeadingZerosInstructionsPPC64); 9509 ins_cost(DEFAULT_COST); 9510 9511 format %{ "CMPWI $crx, $src, #0 \t// convI2B" 9512 "LI $dst, #0\n\t" 9513 "BEQ $crx, done\n\t" 9514 "LI $dst, #1\n" 9515 "done:" %} 9516 size(16); 9517 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x0, 0x1) ); 9518 ins_pipe(pipe_class_compare); 9519 %} 9520 9521 // ConvI2B + XorI 9522 instruct xorI_convI2Bool_reg_immIvalue1__cntlz_Ex(iRegIdst dst, iRegIsrc src, immI_1 mask) %{ 9523 match(Set dst (XorI (Conv2B src) mask)); 9524 predicate(UseCountLeadingZerosInstructionsPPC64); 9525 ins_cost(DEFAULT_COST); 9526 9527 expand %{ 9528 immI shiftAmount %{ 0x5 %} 9529 iRegIdst tmp1; 9530 countLeadingZerosI(tmp1, src); 9531 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9532 %} 9533 %} 9534 9535 instruct xorI_convI2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegIsrc src, flagsReg crx, immI_1 mask) %{ 9536 match(Set dst (XorI (Conv2B src) mask)); 9537 effect(TEMP crx); 9538 predicate(!UseCountLeadingZerosInstructionsPPC64); 9539 ins_cost(DEFAULT_COST); 9540 9541 format %{ "CMPWI $crx, $src, #0 \t// Xor(convI2B($src), $mask)" 9542 "LI $dst, #1\n\t" 9543 "BEQ $crx, done\n\t" 9544 "LI $dst, #0\n" 9545 "done:" %} 9546 size(16); 9547 ins_encode( enc_convI2B_regI__cmove(dst, src, crx, 0x1, 0x0) ); 9548 ins_pipe(pipe_class_compare); 9549 %} 9550 9551 // AndI 0b0..010..0 + ConvI2B 9552 instruct convI2Bool_andI_reg_immIpowerOf2(iRegIdst dst, iRegIsrc src, immIpowerOf2 mask) %{ 9553 match(Set dst (Conv2B (AndI src mask))); 9554 predicate(UseRotateAndMaskInstructionsPPC64); 9555 ins_cost(DEFAULT_COST); 9556 9557 format %{ "RLWINM $dst, $src, $mask \t// convI2B(AndI($src, $mask))" %} 9558 size(4); 9559 ins_encode %{ 9560 // TODO: PPC port $archOpcode(ppc64Opcode_rlwinm); 9561 __ rlwinm($dst$$Register, $src$$Register, (32-log2_long((jlong)$mask$$constant)) & 0x1f, 31, 31); 9562 %} 9563 ins_pipe(pipe_class_default); 9564 %} 9565 9566 // Convert pointer to boolean. 9567 // 9568 // ptr_to_bool(src) : { 1 if src != 0 9569 // { 0 else 9570 // 9571 // strategy: 9572 // 1) Count leading zeros of 64 bit-value src, 9573 // this returns 64 (0b100.0000) iff src == 0 and <64 otherwise. 9574 // 2) Shift 6 bits to the right, result is 0b1 iff src == 0, 0b0 otherwise. 9575 // 3) Xori the result to get 0b1 if src != 0 and 0b0 if src == 0. 9576 9577 // ConvP2B 9578 instruct convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src) %{ 9579 match(Set dst (Conv2B src)); 9580 predicate(UseCountLeadingZerosInstructionsPPC64); 9581 ins_cost(DEFAULT_COST); 9582 9583 expand %{ 9584 immI shiftAmount %{ 0x6 %} 9585 uimmI16 mask %{ 0x1 %} 9586 iRegIdst tmp1; 9587 iRegIdst tmp2; 9588 countLeadingZerosP(tmp1, src); 9589 urShiftI_reg_imm(tmp2, tmp1, shiftAmount); 9590 xorI_reg_uimm16(dst, tmp2, mask); 9591 %} 9592 %} 9593 9594 instruct convP2Bool_reg__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx) %{ 9595 match(Set dst (Conv2B src)); 9596 effect(TEMP crx); 9597 predicate(!UseCountLeadingZerosInstructionsPPC64); 9598 ins_cost(DEFAULT_COST); 9599 9600 format %{ "CMPDI $crx, $src, #0 \t// convP2B" 9601 "LI $dst, #0\n\t" 9602 "BEQ $crx, done\n\t" 9603 "LI $dst, #1\n" 9604 "done:" %} 9605 size(16); 9606 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x0, 0x1) ); 9607 ins_pipe(pipe_class_compare); 9608 %} 9609 9610 // ConvP2B + XorI 9611 instruct xorI_convP2Bool_reg__cntlz_Ex(iRegIdst dst, iRegP_N2P src, immI_1 mask) %{ 9612 match(Set dst (XorI (Conv2B src) mask)); 9613 predicate(UseCountLeadingZerosInstructionsPPC64); 9614 ins_cost(DEFAULT_COST); 9615 9616 expand %{ 9617 immI shiftAmount %{ 0x6 %} 9618 iRegIdst tmp1; 9619 countLeadingZerosP(tmp1, src); 9620 urShiftI_reg_imm(dst, tmp1, shiftAmount); 9621 %} 9622 %} 9623 9624 instruct xorI_convP2Bool_reg_immIvalue1__cmove(iRegIdst dst, iRegP_N2P src, flagsReg crx, immI_1 mask) %{ 9625 match(Set dst (XorI (Conv2B src) mask)); 9626 effect(TEMP crx); 9627 predicate(!UseCountLeadingZerosInstructionsPPC64); 9628 ins_cost(DEFAULT_COST); 9629 9630 format %{ "CMPDI $crx, $src, #0 \t// XorI(convP2B($src), $mask)" 9631 "LI $dst, #1\n\t" 9632 "BEQ $crx, done\n\t" 9633 "LI $dst, #0\n" 9634 "done:" %} 9635 size(16); 9636 ins_encode( enc_convP2B_regP__cmove(dst, src, crx, 0x1, 0x0) ); 9637 ins_pipe(pipe_class_compare); 9638 %} 9639 9640 // if src1 < src2, return -1 else return 0 9641 instruct cmpLTMask_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 9642 match(Set dst (CmpLTMask src1 src2)); 9643 ins_cost(DEFAULT_COST*4); 9644 9645 expand %{ 9646 iRegLdst src1s; 9647 iRegLdst src2s; 9648 iRegLdst diff; 9649 convI2L_reg(src1s, src1); // Ensure proper sign extension. 9650 convI2L_reg(src2s, src2); // Ensure proper sign extension. 9651 subL_reg_reg(diff, src1s, src2s); 9652 // Need to consider >=33 bit result, therefore we need signmaskL. 9653 signmask64I_regL(dst, diff); 9654 %} 9655 %} 9656 9657 instruct cmpLTMask_reg_immI0(iRegIdst dst, iRegIsrc src1, immI_0 src2) %{ 9658 match(Set dst (CmpLTMask src1 src2)); // if src1 < src2, return -1 else return 0 9659 format %{ "SRAWI $dst, $src1, $src2 \t// CmpLTMask" %} 9660 size(4); 9661 ins_encode %{ 9662 // TODO: PPC port $archOpcode(ppc64Opcode_srawi); 9663 __ srawi($dst$$Register, $src1$$Register, 0x1f); 9664 %} 9665 ins_pipe(pipe_class_default); 9666 %} 9667 9668 //----------Arithmetic Conversion Instructions--------------------------------- 9669 9670 // Convert to Byte -- nop 9671 // Convert to Short -- nop 9672 9673 // Convert to Int 9674 9675 instruct convB2I_reg(iRegIdst dst, iRegIsrc src, immI_24 amount) %{ 9676 match(Set dst (RShiftI (LShiftI src amount) amount)); 9677 format %{ "EXTSB $dst, $src \t// byte->int" %} 9678 size(4); 9679 ins_encode %{ 9680 // TODO: PPC port $archOpcode(ppc64Opcode_extsb); 9681 __ extsb($dst$$Register, $src$$Register); 9682 %} 9683 ins_pipe(pipe_class_default); 9684 %} 9685 9686 // LShiftI 16 + RShiftI 16 converts short to int. 9687 instruct convS2I_reg(iRegIdst dst, iRegIsrc src, immI_16 amount) %{ 9688 match(Set dst (RShiftI (LShiftI src amount) amount)); 9689 format %{ "EXTSH $dst, $src \t// short->int" %} 9690 size(4); 9691 ins_encode %{ 9692 // TODO: PPC port $archOpcode(ppc64Opcode_extsh); 9693 __ extsh($dst$$Register, $src$$Register); 9694 %} 9695 ins_pipe(pipe_class_default); 9696 %} 9697 9698 // ConvL2I + ConvI2L: Sign extend int in long register. 9699 instruct sxtI_L2L_reg(iRegLdst dst, iRegLsrc src) %{ 9700 match(Set dst (ConvI2L (ConvL2I src))); 9701 9702 format %{ "EXTSW $dst, $src \t// long->long" %} 9703 size(4); 9704 ins_encode %{ 9705 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9706 __ extsw($dst$$Register, $src$$Register); 9707 %} 9708 ins_pipe(pipe_class_default); 9709 %} 9710 9711 instruct convL2I_reg(iRegIdst dst, iRegLsrc src) %{ 9712 match(Set dst (ConvL2I src)); 9713 format %{ "MR $dst, $src \t// long->int" %} 9714 // variable size, 0 or 4 9715 ins_encode %{ 9716 // TODO: PPC port $archOpcode(ppc64Opcode_or); 9717 __ mr_if_needed($dst$$Register, $src$$Register); 9718 %} 9719 ins_pipe(pipe_class_default); 9720 %} 9721 9722 instruct convD2IRaw_regD(regD dst, regD src) %{ 9723 // no match-rule, false predicate 9724 effect(DEF dst, USE src); 9725 predicate(false); 9726 9727 format %{ "FCTIWZ $dst, $src \t// convD2I, $src != NaN" %} 9728 size(4); 9729 ins_encode %{ 9730 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz);; 9731 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9732 %} 9733 ins_pipe(pipe_class_default); 9734 %} 9735 9736 instruct cmovI_bso_stackSlotL(iRegIdst dst, flagsRegSrc crx, stackSlotL src) %{ 9737 // no match-rule, false predicate 9738 effect(DEF dst, USE crx, USE src); 9739 predicate(false); 9740 9741 ins_variable_size_depending_on_alignment(true); 9742 9743 format %{ "cmovI $crx, $dst, $src" %} 9744 // Worst case is branch + move + stop, no stop without scheduler. 9745 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 12 : 8); 9746 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9747 ins_pipe(pipe_class_default); 9748 %} 9749 9750 instruct cmovI_bso_stackSlotL_conLvalue0_Ex(iRegIdst dst, flagsRegSrc crx, stackSlotL mem) %{ 9751 // no match-rule, false predicate 9752 effect(DEF dst, USE crx, USE mem); 9753 predicate(false); 9754 9755 format %{ "CmovI $dst, $crx, $mem \t// postalloc expanded" %} 9756 postalloc_expand %{ 9757 // 9758 // replaces 9759 // 9760 // region dst crx mem 9761 // \ | | / 9762 // dst=cmovI_bso_stackSlotL_conLvalue0 9763 // 9764 // with 9765 // 9766 // region dst 9767 // \ / 9768 // dst=loadConI16(0) 9769 // | 9770 // ^ region dst crx mem 9771 // | \ | | / 9772 // dst=cmovI_bso_stackSlotL 9773 // 9774 9775 // Create new nodes. 9776 MachNode *m1 = new loadConI16Node(); 9777 MachNode *m2 = new cmovI_bso_stackSlotLNode(); 9778 9779 // inputs for new nodes 9780 m1->add_req(n_region); 9781 m2->add_req(n_region, n_crx, n_mem); 9782 9783 // precedences for new nodes 9784 m2->add_prec(m1); 9785 9786 // operands for new nodes 9787 m1->_opnds[0] = op_dst; 9788 m1->_opnds[1] = new immI16Oper(0); 9789 9790 m2->_opnds[0] = op_dst; 9791 m2->_opnds[1] = op_crx; 9792 m2->_opnds[2] = op_mem; 9793 9794 // registers for new nodes 9795 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9796 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9797 9798 // Insert new nodes. 9799 nodes->push(m1); 9800 nodes->push(m2); 9801 %} 9802 %} 9803 9804 // Double to Int conversion, NaN is mapped to 0. 9805 instruct convD2I_reg_ExEx(iRegIdst dst, regD src) %{ 9806 match(Set dst (ConvD2I src)); 9807 ins_cost(DEFAULT_COST); 9808 9809 expand %{ 9810 regD tmpD; 9811 stackSlotL tmpS; 9812 flagsReg crx; 9813 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9814 convD2IRaw_regD(tmpD, src); // Convert float to int (speculated). 9815 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 9816 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9817 %} 9818 %} 9819 9820 instruct convF2IRaw_regF(regF dst, regF src) %{ 9821 // no match-rule, false predicate 9822 effect(DEF dst, USE src); 9823 predicate(false); 9824 9825 format %{ "FCTIWZ $dst, $src \t// convF2I, $src != NaN" %} 9826 size(4); 9827 ins_encode %{ 9828 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9829 __ fctiwz($dst$$FloatRegister, $src$$FloatRegister); 9830 %} 9831 ins_pipe(pipe_class_default); 9832 %} 9833 9834 // Float to Int conversion, NaN is mapped to 0. 9835 instruct convF2I_regF_ExEx(iRegIdst dst, regF src) %{ 9836 match(Set dst (ConvF2I src)); 9837 ins_cost(DEFAULT_COST); 9838 9839 expand %{ 9840 regF tmpF; 9841 stackSlotL tmpS; 9842 flagsReg crx; 9843 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9844 convF2IRaw_regF(tmpF, src); // Convert float to int (speculated). 9845 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9846 cmovI_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9847 %} 9848 %} 9849 9850 // Convert to Long 9851 9852 instruct convI2L_reg(iRegLdst dst, iRegIsrc src) %{ 9853 match(Set dst (ConvI2L src)); 9854 format %{ "EXTSW $dst, $src \t// int->long" %} 9855 size(4); 9856 ins_encode %{ 9857 // TODO: PPC port $archOpcode(ppc64Opcode_extsw); 9858 __ extsw($dst$$Register, $src$$Register); 9859 %} 9860 ins_pipe(pipe_class_default); 9861 %} 9862 9863 // Zero-extend: convert unsigned int to long (convUI2L). 9864 instruct zeroExtendL_regI(iRegLdst dst, iRegIsrc src, immL_32bits mask) %{ 9865 match(Set dst (AndL (ConvI2L src) mask)); 9866 ins_cost(DEFAULT_COST); 9867 9868 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9869 size(4); 9870 ins_encode %{ 9871 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9872 __ clrldi($dst$$Register, $src$$Register, 32); 9873 %} 9874 ins_pipe(pipe_class_default); 9875 %} 9876 9877 // Zero-extend: convert unsigned int to long in long register. 9878 instruct zeroExtendL_regL(iRegLdst dst, iRegLsrc src, immL_32bits mask) %{ 9879 match(Set dst (AndL src mask)); 9880 ins_cost(DEFAULT_COST); 9881 9882 format %{ "CLRLDI $dst, $src, #32 \t// zero-extend int to long" %} 9883 size(4); 9884 ins_encode %{ 9885 // TODO: PPC port $archOpcode(ppc64Opcode_rldicl); 9886 __ clrldi($dst$$Register, $src$$Register, 32); 9887 %} 9888 ins_pipe(pipe_class_default); 9889 %} 9890 9891 instruct convF2LRaw_regF(regF dst, regF src) %{ 9892 // no match-rule, false predicate 9893 effect(DEF dst, USE src); 9894 predicate(false); 9895 9896 format %{ "FCTIDZ $dst, $src \t// convF2L, $src != NaN" %} 9897 size(4); 9898 ins_encode %{ 9899 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9900 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 9901 %} 9902 ins_pipe(pipe_class_default); 9903 %} 9904 9905 instruct cmovL_bso_stackSlotL(iRegLdst dst, flagsRegSrc crx, stackSlotL src) %{ 9906 // no match-rule, false predicate 9907 effect(DEF dst, USE crx, USE src); 9908 predicate(false); 9909 9910 ins_variable_size_depending_on_alignment(true); 9911 9912 format %{ "cmovL $crx, $dst, $src" %} 9913 // Worst case is branch + move + stop, no stop without scheduler. 9914 size(false /* TODO: PPC PORT Compile::current()->do_hb_scheduling()*/ ? 12 : 8); 9915 ins_encode( enc_cmove_bso_stackSlotL(dst, crx, src) ); 9916 ins_pipe(pipe_class_default); 9917 %} 9918 9919 instruct cmovL_bso_stackSlotL_conLvalue0_Ex(iRegLdst dst, flagsRegSrc crx, stackSlotL mem) %{ 9920 // no match-rule, false predicate 9921 effect(DEF dst, USE crx, USE mem); 9922 predicate(false); 9923 9924 format %{ "CmovL $dst, $crx, $mem \t// postalloc expanded" %} 9925 postalloc_expand %{ 9926 // 9927 // replaces 9928 // 9929 // region dst crx mem 9930 // \ | | / 9931 // dst=cmovL_bso_stackSlotL_conLvalue0 9932 // 9933 // with 9934 // 9935 // region dst 9936 // \ / 9937 // dst=loadConL16(0) 9938 // | 9939 // ^ region dst crx mem 9940 // | \ | | / 9941 // dst=cmovL_bso_stackSlotL 9942 // 9943 9944 // Create new nodes. 9945 MachNode *m1 = new loadConL16Node(); 9946 MachNode *m2 = new cmovL_bso_stackSlotLNode(); 9947 9948 // inputs for new nodes 9949 m1->add_req(n_region); 9950 m2->add_req(n_region, n_crx, n_mem); 9951 m2->add_prec(m1); 9952 9953 // operands for new nodes 9954 m1->_opnds[0] = op_dst; 9955 m1->_opnds[1] = new immL16Oper(0); 9956 m2->_opnds[0] = op_dst; 9957 m2->_opnds[1] = op_crx; 9958 m2->_opnds[2] = op_mem; 9959 9960 // registers for new nodes 9961 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9962 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 9963 9964 // Insert new nodes. 9965 nodes->push(m1); 9966 nodes->push(m2); 9967 %} 9968 %} 9969 9970 // Float to Long conversion, NaN is mapped to 0. 9971 instruct convF2L_reg_ExEx(iRegLdst dst, regF src) %{ 9972 match(Set dst (ConvF2L src)); 9973 ins_cost(DEFAULT_COST); 9974 9975 expand %{ 9976 regF tmpF; 9977 stackSlotL tmpS; 9978 flagsReg crx; 9979 cmpFUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 9980 convF2LRaw_regF(tmpF, src); // Convert float to long (speculated). 9981 moveF2L_reg_stack(tmpS, tmpF); // Store float to stack (speculated). 9982 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 9983 %} 9984 %} 9985 9986 instruct convD2LRaw_regD(regD dst, regD src) %{ 9987 // no match-rule, false predicate 9988 effect(DEF dst, USE src); 9989 predicate(false); 9990 9991 format %{ "FCTIDZ $dst, $src \t// convD2L $src != NaN" %} 9992 size(4); 9993 ins_encode %{ 9994 // TODO: PPC port $archOpcode(ppc64Opcode_fctiwz); 9995 __ fctidz($dst$$FloatRegister, $src$$FloatRegister); 9996 %} 9997 ins_pipe(pipe_class_default); 9998 %} 9999 10000 // Double to Long conversion, NaN is mapped to 0. 10001 instruct convD2L_reg_ExEx(iRegLdst dst, regD src) %{ 10002 match(Set dst (ConvD2L src)); 10003 ins_cost(DEFAULT_COST); 10004 10005 expand %{ 10006 regD tmpD; 10007 stackSlotL tmpS; 10008 flagsReg crx; 10009 cmpDUnordered_reg_reg(crx, src, src); // Check whether src is NaN. 10010 convD2LRaw_regD(tmpD, src); // Convert float to long (speculated). 10011 moveD2L_reg_stack(tmpS, tmpD); // Store float to stack (speculated). 10012 cmovL_bso_stackSlotL_conLvalue0_Ex(dst, crx, tmpS); // Cmove based on NaN check. 10013 %} 10014 %} 10015 10016 // Convert to Float 10017 10018 // Placed here as needed in expand. 10019 instruct convL2DRaw_regD(regD dst, regD src) %{ 10020 // no match-rule, false predicate 10021 effect(DEF dst, USE src); 10022 predicate(false); 10023 10024 format %{ "FCFID $dst, $src \t// convL2D" %} 10025 size(4); 10026 ins_encode %{ 10027 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10028 __ fcfid($dst$$FloatRegister, $src$$FloatRegister); 10029 %} 10030 ins_pipe(pipe_class_default); 10031 %} 10032 10033 // Placed here as needed in expand. 10034 instruct convD2F_reg(regF dst, regD src) %{ 10035 match(Set dst (ConvD2F src)); 10036 format %{ "FRSP $dst, $src \t// convD2F" %} 10037 size(4); 10038 ins_encode %{ 10039 // TODO: PPC port $archOpcode(ppc64Opcode_frsp); 10040 __ frsp($dst$$FloatRegister, $src$$FloatRegister); 10041 %} 10042 ins_pipe(pipe_class_default); 10043 %} 10044 10045 // Integer to Float conversion. 10046 instruct convI2F_ireg_Ex(regF dst, iRegIsrc src) %{ 10047 match(Set dst (ConvI2F src)); 10048 predicate(!VM_Version::has_fcfids()); 10049 ins_cost(DEFAULT_COST); 10050 10051 expand %{ 10052 iRegLdst tmpL; 10053 stackSlotL tmpS; 10054 regD tmpD; 10055 regD tmpD2; 10056 convI2L_reg(tmpL, src); // Sign-extension int to long. 10057 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10058 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10059 convL2DRaw_regD(tmpD2, tmpD); // Convert to double. 10060 convD2F_reg(dst, tmpD2); // Convert double to float. 10061 %} 10062 %} 10063 10064 instruct convL2FRaw_regF(regF dst, regD src) %{ 10065 // no match-rule, false predicate 10066 effect(DEF dst, USE src); 10067 predicate(false); 10068 10069 format %{ "FCFIDS $dst, $src \t// convL2F" %} 10070 size(4); 10071 ins_encode %{ 10072 // TODO: PPC port $archOpcode(ppc64Opcode_fcfid); 10073 __ fcfids($dst$$FloatRegister, $src$$FloatRegister); 10074 %} 10075 ins_pipe(pipe_class_default); 10076 %} 10077 10078 // Integer to Float conversion. Special version for Power7. 10079 instruct convI2F_ireg_fcfids_Ex(regF dst, iRegIsrc src) %{ 10080 match(Set dst (ConvI2F src)); 10081 predicate(VM_Version::has_fcfids()); 10082 ins_cost(DEFAULT_COST); 10083 10084 expand %{ 10085 iRegLdst tmpL; 10086 stackSlotL tmpS; 10087 regD tmpD; 10088 convI2L_reg(tmpL, src); // Sign-extension int to long. 10089 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10090 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10091 convL2FRaw_regF(dst, tmpD); // Convert to float. 10092 %} 10093 %} 10094 10095 // L2F to avoid runtime call. 10096 instruct convL2F_ireg_fcfids_Ex(regF dst, iRegLsrc src) %{ 10097 match(Set dst (ConvL2F src)); 10098 predicate(VM_Version::has_fcfids()); 10099 ins_cost(DEFAULT_COST); 10100 10101 expand %{ 10102 stackSlotL tmpS; 10103 regD tmpD; 10104 regL_to_stkL(tmpS, src); // Store long to stack. 10105 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10106 convL2FRaw_regF(dst, tmpD); // Convert to float. 10107 %} 10108 %} 10109 10110 // Moved up as used in expand. 10111 //instruct convD2F_reg(regF dst, regD src) %{%} 10112 10113 // Convert to Double 10114 10115 // Integer to Double conversion. 10116 instruct convI2D_reg_Ex(regD dst, iRegIsrc src) %{ 10117 match(Set dst (ConvI2D src)); 10118 ins_cost(DEFAULT_COST); 10119 10120 expand %{ 10121 iRegLdst tmpL; 10122 stackSlotL tmpS; 10123 regD tmpD; 10124 convI2L_reg(tmpL, src); // Sign-extension int to long. 10125 regL_to_stkL(tmpS, tmpL); // Store long to stack. 10126 moveL2D_stack_reg(tmpD, tmpS); // Load long into double register. 10127 convL2DRaw_regD(dst, tmpD); // Convert to double. 10128 %} 10129 %} 10130 10131 // Long to Double conversion 10132 instruct convL2D_reg_Ex(regD dst, stackSlotL src) %{ 10133 match(Set dst (ConvL2D src)); 10134 ins_cost(DEFAULT_COST + MEMORY_REF_COST); 10135 10136 expand %{ 10137 regD tmpD; 10138 moveL2D_stack_reg(tmpD, src); 10139 convL2DRaw_regD(dst, tmpD); 10140 %} 10141 %} 10142 10143 instruct convF2D_reg(regD dst, regF src) %{ 10144 match(Set dst (ConvF2D src)); 10145 format %{ "FMR $dst, $src \t// float->double" %} 10146 // variable size, 0 or 4 10147 ins_encode %{ 10148 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 10149 __ fmr_if_needed($dst$$FloatRegister, $src$$FloatRegister); 10150 %} 10151 ins_pipe(pipe_class_default); 10152 %} 10153 10154 //----------Control Flow Instructions------------------------------------------ 10155 // Compare Instructions 10156 10157 // Compare Integers 10158 instruct cmpI_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10159 match(Set crx (CmpI src1 src2)); 10160 size(4); 10161 format %{ "CMPW $crx, $src1, $src2" %} 10162 ins_encode %{ 10163 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10164 __ cmpw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10165 %} 10166 ins_pipe(pipe_class_compare); 10167 %} 10168 10169 instruct cmpI_reg_imm16(flagsReg crx, iRegIsrc src1, immI16 src2) %{ 10170 match(Set crx (CmpI src1 src2)); 10171 format %{ "CMPWI $crx, $src1, $src2" %} 10172 size(4); 10173 ins_encode %{ 10174 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10175 __ cmpwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10176 %} 10177 ins_pipe(pipe_class_compare); 10178 %} 10179 10180 // (src1 & src2) == 0? 10181 instruct testI_reg_imm(flagsRegCR0 cr0, iRegIsrc src1, uimmI16 src2, immI_0 zero) %{ 10182 match(Set cr0 (CmpI (AndI src1 src2) zero)); 10183 // r0 is killed 10184 format %{ "ANDI R0, $src1, $src2 \t// BTST int" %} 10185 size(4); 10186 ins_encode %{ 10187 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10188 __ andi_(R0, $src1$$Register, $src2$$constant); 10189 %} 10190 ins_pipe(pipe_class_compare); 10191 %} 10192 10193 instruct cmpL_reg_reg(flagsReg crx, iRegLsrc src1, iRegLsrc src2) %{ 10194 match(Set crx (CmpL src1 src2)); 10195 format %{ "CMPD $crx, $src1, $src2" %} 10196 size(4); 10197 ins_encode %{ 10198 // TODO: PPC port $archOpcode(ppc64Opcode_cmp); 10199 __ cmpd($crx$$CondRegister, $src1$$Register, $src2$$Register); 10200 %} 10201 ins_pipe(pipe_class_compare); 10202 %} 10203 10204 instruct cmpL_reg_imm16(flagsReg crx, iRegLsrc src1, immL16 src2) %{ 10205 match(Set crx (CmpL src1 src2)); 10206 format %{ "CMPDI $crx, $src1, $src2" %} 10207 size(4); 10208 ins_encode %{ 10209 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10210 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10211 %} 10212 ins_pipe(pipe_class_compare); 10213 %} 10214 10215 instruct testL_reg_reg(flagsRegCR0 cr0, iRegLsrc src1, iRegLsrc src2, immL_0 zero) %{ 10216 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10217 // r0 is killed 10218 format %{ "AND R0, $src1, $src2 \t// BTST long" %} 10219 size(4); 10220 ins_encode %{ 10221 // TODO: PPC port $archOpcode(ppc64Opcode_and_); 10222 __ and_(R0, $src1$$Register, $src2$$Register); 10223 %} 10224 ins_pipe(pipe_class_compare); 10225 %} 10226 10227 instruct testL_reg_imm(flagsRegCR0 cr0, iRegLsrc src1, uimmL16 src2, immL_0 zero) %{ 10228 match(Set cr0 (CmpL (AndL src1 src2) zero)); 10229 // r0 is killed 10230 format %{ "ANDI R0, $src1, $src2 \t// BTST long" %} 10231 size(4); 10232 ins_encode %{ 10233 // TODO: PPC port $archOpcode(ppc64Opcode_andi_); 10234 __ andi_(R0, $src1$$Register, $src2$$constant); 10235 %} 10236 ins_pipe(pipe_class_compare); 10237 %} 10238 10239 instruct cmovI_conIvalueMinus1_conIvalue1(iRegIdst dst, flagsRegSrc crx) %{ 10240 // no match-rule, false predicate 10241 effect(DEF dst, USE crx); 10242 predicate(false); 10243 10244 ins_variable_size_depending_on_alignment(true); 10245 10246 format %{ "cmovI $crx, $dst, -1, 0, +1" %} 10247 // Worst case is branch + move + branch + move + stop, no stop without scheduler. 10248 size(false /* TODO: PPC PORTInsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 20 : 16); 10249 ins_encode %{ 10250 // TODO: PPC port $archOpcode(ppc64Opcode_cmove); 10251 Label done; 10252 // li(Rdst, 0); // equal -> 0 10253 __ beq($crx$$CondRegister, done); 10254 __ li($dst$$Register, 1); // greater -> +1 10255 __ bgt($crx$$CondRegister, done); 10256 __ li($dst$$Register, -1); // unordered or less -> -1 10257 // TODO: PPC port__ endgroup_if_needed(_size == 20); 10258 __ bind(done); 10259 %} 10260 ins_pipe(pipe_class_compare); 10261 %} 10262 10263 instruct cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(iRegIdst dst, flagsRegSrc crx) %{ 10264 // no match-rule, false predicate 10265 effect(DEF dst, USE crx); 10266 predicate(false); 10267 10268 format %{ "CmovI $crx, $dst, -1, 0, +1 \t// postalloc expanded" %} 10269 postalloc_expand %{ 10270 // 10271 // replaces 10272 // 10273 // region crx 10274 // \ | 10275 // dst=cmovI_conIvalueMinus1_conIvalue0_conIvalue1 10276 // 10277 // with 10278 // 10279 // region 10280 // \ 10281 // dst=loadConI16(0) 10282 // | 10283 // ^ region crx 10284 // | \ | 10285 // dst=cmovI_conIvalueMinus1_conIvalue1 10286 // 10287 10288 // Create new nodes. 10289 MachNode *m1 = new loadConI16Node(); 10290 MachNode *m2 = new cmovI_conIvalueMinus1_conIvalue1Node(); 10291 10292 // inputs for new nodes 10293 m1->add_req(n_region); 10294 m2->add_req(n_region, n_crx); 10295 m2->add_prec(m1); 10296 10297 // operands for new nodes 10298 m1->_opnds[0] = op_dst; 10299 m1->_opnds[1] = new immI16Oper(0); 10300 m2->_opnds[0] = op_dst; 10301 m2->_opnds[1] = op_crx; 10302 10303 // registers for new nodes 10304 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10305 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // dst 10306 10307 // Insert new nodes. 10308 nodes->push(m1); 10309 nodes->push(m2); 10310 %} 10311 %} 10312 10313 // Manifest a CmpL3 result in an integer register. Very painful. 10314 // This is the test to avoid. 10315 // (src1 < src2) ? -1 : ((src1 > src2) ? 1 : 0) 10316 instruct cmpL3_reg_reg_ExEx(iRegIdst dst, iRegLsrc src1, iRegLsrc src2) %{ 10317 match(Set dst (CmpL3 src1 src2)); 10318 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10319 10320 expand %{ 10321 flagsReg tmp1; 10322 cmpL_reg_reg(tmp1, src1, src2); 10323 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10324 %} 10325 %} 10326 10327 // Implicit range checks. 10328 // A range check in the ideal world has one of the following shapes: 10329 // - (If le (CmpU length index)), (IfTrue throw exception) 10330 // - (If lt (CmpU index length)), (IfFalse throw exception) 10331 // 10332 // Match range check 'If le (CmpU length index)'. 10333 instruct rangeCheck_iReg_uimm15(cmpOp cmp, iRegIsrc src_length, uimmI15 index, label labl) %{ 10334 match(If cmp (CmpU src_length index)); 10335 effect(USE labl); 10336 predicate(TrapBasedRangeChecks && 10337 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::le && 10338 PROB_UNLIKELY(_leaf->as_If()->_prob) >= PROB_ALWAYS && 10339 (Matcher::branches_to_uncommon_trap(_leaf))); 10340 10341 ins_is_TrapBasedCheckNode(true); 10342 10343 format %{ "TWI $index $cmp $src_length \t// RangeCheck => trap $labl" %} 10344 size(4); 10345 ins_encode %{ 10346 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10347 if ($cmp$$cmpcode == 0x1 /* less_equal */) { 10348 __ trap_range_check_le($src_length$$Register, $index$$constant); 10349 } else { 10350 // Both successors are uncommon traps, probability is 0. 10351 // Node got flipped during fixup flow. 10352 assert($cmp$$cmpcode == 0x9, "must be greater"); 10353 __ trap_range_check_g($src_length$$Register, $index$$constant); 10354 } 10355 %} 10356 ins_pipe(pipe_class_trap); 10357 %} 10358 10359 // Match range check 'If lt (CmpU index length)'. 10360 instruct rangeCheck_iReg_iReg(cmpOp cmp, iRegIsrc src_index, iRegIsrc src_length, label labl) %{ 10361 match(If cmp (CmpU src_index src_length)); 10362 effect(USE labl); 10363 predicate(TrapBasedRangeChecks && 10364 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10365 _leaf->as_If()->_prob >= PROB_ALWAYS && 10366 (Matcher::branches_to_uncommon_trap(_leaf))); 10367 10368 ins_is_TrapBasedCheckNode(true); 10369 10370 format %{ "TW $src_index $cmp $src_length \t// RangeCheck => trap $labl" %} 10371 size(4); 10372 ins_encode %{ 10373 // TODO: PPC port $archOpcode(ppc64Opcode_tw); 10374 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10375 __ trap_range_check_ge($src_index$$Register, $src_length$$Register); 10376 } else { 10377 // Both successors are uncommon traps, probability is 0. 10378 // Node got flipped during fixup flow. 10379 assert($cmp$$cmpcode == 0x8, "must be less"); 10380 __ trap_range_check_l($src_index$$Register, $src_length$$Register); 10381 } 10382 %} 10383 ins_pipe(pipe_class_trap); 10384 %} 10385 10386 // Match range check 'If lt (CmpU index length)'. 10387 instruct rangeCheck_uimm15_iReg(cmpOp cmp, iRegIsrc src_index, uimmI15 length, label labl) %{ 10388 match(If cmp (CmpU src_index length)); 10389 effect(USE labl); 10390 predicate(TrapBasedRangeChecks && 10391 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::lt && 10392 _leaf->as_If()->_prob >= PROB_ALWAYS && 10393 (Matcher::branches_to_uncommon_trap(_leaf))); 10394 10395 ins_is_TrapBasedCheckNode(true); 10396 10397 format %{ "TWI $src_index $cmp $length \t// RangeCheck => trap $labl" %} 10398 size(4); 10399 ins_encode %{ 10400 // TODO: PPC port $archOpcode(ppc64Opcode_twi); 10401 if ($cmp$$cmpcode == 0x0 /* greater_equal */) { 10402 __ trap_range_check_ge($src_index$$Register, $length$$constant); 10403 } else { 10404 // Both successors are uncommon traps, probability is 0. 10405 // Node got flipped during fixup flow. 10406 assert($cmp$$cmpcode == 0x8, "must be less"); 10407 __ trap_range_check_l($src_index$$Register, $length$$constant); 10408 } 10409 %} 10410 ins_pipe(pipe_class_trap); 10411 %} 10412 10413 instruct compU_reg_reg(flagsReg crx, iRegIsrc src1, iRegIsrc src2) %{ 10414 match(Set crx (CmpU src1 src2)); 10415 format %{ "CMPLW $crx, $src1, $src2 \t// unsigned" %} 10416 size(4); 10417 ins_encode %{ 10418 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10419 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10420 %} 10421 ins_pipe(pipe_class_compare); 10422 %} 10423 10424 instruct compU_reg_uimm16(flagsReg crx, iRegIsrc src1, uimmI16 src2) %{ 10425 match(Set crx (CmpU src1 src2)); 10426 size(4); 10427 format %{ "CMPLWI $crx, $src1, $src2" %} 10428 ins_encode %{ 10429 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10430 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10431 %} 10432 ins_pipe(pipe_class_compare); 10433 %} 10434 10435 // Implicit zero checks (more implicit null checks). 10436 // No constant pool entries required. 10437 instruct zeroCheckN_iReg_imm0(cmpOp cmp, iRegNsrc value, immN_0 zero, label labl) %{ 10438 match(If cmp (CmpN value zero)); 10439 effect(USE labl); 10440 predicate(TrapBasedNullChecks && 10441 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10442 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10443 Matcher::branches_to_uncommon_trap(_leaf)); 10444 ins_cost(1); 10445 10446 ins_is_TrapBasedCheckNode(true); 10447 10448 format %{ "TDI $value $cmp $zero \t// ZeroCheckN => trap $labl" %} 10449 size(4); 10450 ins_encode %{ 10451 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10452 if ($cmp$$cmpcode == 0xA) { 10453 __ trap_null_check($value$$Register); 10454 } else { 10455 // Both successors are uncommon traps, probability is 0. 10456 // Node got flipped during fixup flow. 10457 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10458 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10459 } 10460 %} 10461 ins_pipe(pipe_class_trap); 10462 %} 10463 10464 // Compare narrow oops. 10465 instruct cmpN_reg_reg(flagsReg crx, iRegNsrc src1, iRegNsrc src2) %{ 10466 match(Set crx (CmpN src1 src2)); 10467 10468 size(4); 10469 ins_cost(2); 10470 format %{ "CMPLW $crx, $src1, $src2 \t// compressed ptr" %} 10471 ins_encode %{ 10472 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10473 __ cmplw($crx$$CondRegister, $src1$$Register, $src2$$Register); 10474 %} 10475 ins_pipe(pipe_class_compare); 10476 %} 10477 10478 instruct cmpN_reg_imm0(flagsReg crx, iRegNsrc src1, immN_0 src2) %{ 10479 match(Set crx (CmpN src1 src2)); 10480 // Make this more expensive than zeroCheckN_iReg_imm0. 10481 ins_cost(2); 10482 10483 format %{ "CMPLWI $crx, $src1, $src2 \t// compressed ptr" %} 10484 size(4); 10485 ins_encode %{ 10486 // TODO: PPC port $archOpcode(ppc64Opcode_cmpli); 10487 __ cmplwi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10488 %} 10489 ins_pipe(pipe_class_compare); 10490 %} 10491 10492 // Implicit zero checks (more implicit null checks). 10493 // No constant pool entries required. 10494 instruct zeroCheckP_reg_imm0(cmpOp cmp, iRegP_N2P value, immP_0 zero, label labl) %{ 10495 match(If cmp (CmpP value zero)); 10496 effect(USE labl); 10497 predicate(TrapBasedNullChecks && 10498 _kids[0]->_leaf->as_Bool()->_test._test == BoolTest::ne && 10499 _leaf->as_If()->_prob >= PROB_LIKELY_MAG(4) && 10500 Matcher::branches_to_uncommon_trap(_leaf)); 10501 ins_cost(1); // Should not be cheaper than zeroCheckN. 10502 10503 ins_is_TrapBasedCheckNode(true); 10504 10505 format %{ "TDI $value $cmp $zero \t// ZeroCheckP => trap $labl" %} 10506 size(4); 10507 ins_encode %{ 10508 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 10509 if ($cmp$$cmpcode == 0xA) { 10510 __ trap_null_check($value$$Register); 10511 } else { 10512 // Both successors are uncommon traps, probability is 0. 10513 // Node got flipped during fixup flow. 10514 assert($cmp$$cmpcode == 0x2 , "must be equal(0xA) or notEqual(0x2)"); 10515 __ trap_null_check($value$$Register, Assembler::traptoGreaterThanUnsigned); 10516 } 10517 %} 10518 ins_pipe(pipe_class_trap); 10519 %} 10520 10521 // Compare Pointers 10522 instruct cmpP_reg_reg(flagsReg crx, iRegP_N2P src1, iRegP_N2P src2) %{ 10523 match(Set crx (CmpP src1 src2)); 10524 format %{ "CMPLD $crx, $src1, $src2 \t// ptr" %} 10525 size(4); 10526 ins_encode %{ 10527 // TODO: PPC port $archOpcode(ppc64Opcode_cmpl); 10528 __ cmpld($crx$$CondRegister, $src1$$Register, $src2$$Register); 10529 %} 10530 ins_pipe(pipe_class_compare); 10531 %} 10532 10533 // Used in postalloc expand. 10534 instruct cmpP_reg_imm16(flagsReg crx, iRegPsrc src1, immL16 src2) %{ 10535 // This match rule prevents reordering of node before a safepoint. 10536 // This only makes sense if this instructions is used exclusively 10537 // for the expansion of EncodeP! 10538 match(Set crx (CmpP src1 src2)); 10539 predicate(false); 10540 10541 format %{ "CMPDI $crx, $src1, $src2" %} 10542 size(4); 10543 ins_encode %{ 10544 // TODO: PPC port $archOpcode(ppc64Opcode_cmpi); 10545 __ cmpdi($crx$$CondRegister, $src1$$Register, $src2$$constant); 10546 %} 10547 ins_pipe(pipe_class_compare); 10548 %} 10549 10550 //----------Float Compares---------------------------------------------------- 10551 10552 instruct cmpFUnordered_reg_reg(flagsReg crx, regF src1, regF src2) %{ 10553 // Needs matchrule, see cmpDUnordered. 10554 match(Set crx (CmpF src1 src2)); 10555 // no match-rule, false predicate 10556 predicate(false); 10557 10558 format %{ "cmpFUrd $crx, $src1, $src2" %} 10559 size(4); 10560 ins_encode %{ 10561 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10562 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10563 %} 10564 ins_pipe(pipe_class_default); 10565 %} 10566 10567 instruct cmov_bns_less(flagsReg crx) %{ 10568 // no match-rule, false predicate 10569 effect(DEF crx); 10570 predicate(false); 10571 10572 ins_variable_size_depending_on_alignment(true); 10573 10574 format %{ "cmov $crx" %} 10575 // Worst case is branch + move + stop, no stop without scheduler. 10576 size(false /* TODO: PPC PORT(InsertEndGroupPPC64 && Compile::current()->do_hb_scheduling())*/ ? 16 : 12); 10577 ins_encode %{ 10578 // TODO: PPC port $archOpcode(ppc64Opcode_cmovecr); 10579 Label done; 10580 __ bns($crx$$CondRegister, done); // not unordered -> keep crx 10581 __ li(R0, 0); 10582 __ cmpwi($crx$$CondRegister, R0, 1); // unordered -> set crx to 'less' 10583 // TODO PPC port __ endgroup_if_needed(_size == 16); 10584 __ bind(done); 10585 %} 10586 ins_pipe(pipe_class_default); 10587 %} 10588 10589 // Compare floating, generate condition code. 10590 instruct cmpF_reg_reg_Ex(flagsReg crx, regF src1, regF src2) %{ 10591 // FIXME: should we match 'If cmp (CmpF src1 src2))' ?? 10592 // 10593 // The following code sequence occurs a lot in mpegaudio: 10594 // 10595 // block BXX: 10596 // 0: instruct cmpFUnordered_reg_reg (cmpF_reg_reg-0): 10597 // cmpFUrd CCR6, F11, F9 10598 // 4: instruct cmov_bns_less (cmpF_reg_reg-1): 10599 // cmov CCR6 10600 // 8: instruct branchConSched: 10601 // B_FARle CCR6, B56 P=0.500000 C=-1.000000 10602 match(Set crx (CmpF src1 src2)); 10603 ins_cost(DEFAULT_COST+BRANCH_COST); 10604 10605 format %{ "CmpF $crx, $src1, $src2 \t// postalloc expanded" %} 10606 postalloc_expand %{ 10607 // 10608 // replaces 10609 // 10610 // region src1 src2 10611 // \ | | 10612 // crx=cmpF_reg_reg 10613 // 10614 // with 10615 // 10616 // region src1 src2 10617 // \ | | 10618 // crx=cmpFUnordered_reg_reg 10619 // | 10620 // ^ region 10621 // | \ 10622 // crx=cmov_bns_less 10623 // 10624 10625 // Create new nodes. 10626 MachNode *m1 = new cmpFUnordered_reg_regNode(); 10627 MachNode *m2 = new cmov_bns_lessNode(); 10628 10629 // inputs for new nodes 10630 m1->add_req(n_region, n_src1, n_src2); 10631 m2->add_req(n_region); 10632 m2->add_prec(m1); 10633 10634 // operands for new nodes 10635 m1->_opnds[0] = op_crx; 10636 m1->_opnds[1] = op_src1; 10637 m1->_opnds[2] = op_src2; 10638 m2->_opnds[0] = op_crx; 10639 10640 // registers for new nodes 10641 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10642 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10643 10644 // Insert new nodes. 10645 nodes->push(m1); 10646 nodes->push(m2); 10647 %} 10648 %} 10649 10650 // Compare float, generate -1,0,1 10651 instruct cmpF3_reg_reg_ExEx(iRegIdst dst, regF src1, regF src2) %{ 10652 match(Set dst (CmpF3 src1 src2)); 10653 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10654 10655 expand %{ 10656 flagsReg tmp1; 10657 cmpFUnordered_reg_reg(tmp1, src1, src2); 10658 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10659 %} 10660 %} 10661 10662 instruct cmpDUnordered_reg_reg(flagsReg crx, regD src1, regD src2) %{ 10663 // Needs matchrule so that ideal opcode is Cmp. This causes that gcm places the 10664 // node right before the conditional move using it. 10665 // In jck test api/java_awt/geom/QuadCurve2DFloat/index.html#SetCurveTesttestCase7, 10666 // compilation of java.awt.geom.RectangularShape::getBounds()Ljava/awt/Rectangle 10667 // crashed in register allocation where the flags Reg between cmpDUnoredered and a 10668 // conditional move was supposed to be spilled. 10669 match(Set crx (CmpD src1 src2)); 10670 // False predicate, shall not be matched. 10671 predicate(false); 10672 10673 format %{ "cmpFUrd $crx, $src1, $src2" %} 10674 size(4); 10675 ins_encode %{ 10676 // TODO: PPC port $archOpcode(ppc64Opcode_fcmpu); 10677 __ fcmpu($crx$$CondRegister, $src1$$FloatRegister, $src2$$FloatRegister); 10678 %} 10679 ins_pipe(pipe_class_default); 10680 %} 10681 10682 instruct cmpD_reg_reg_Ex(flagsReg crx, regD src1, regD src2) %{ 10683 match(Set crx (CmpD src1 src2)); 10684 ins_cost(DEFAULT_COST+BRANCH_COST); 10685 10686 format %{ "CmpD $crx, $src1, $src2 \t// postalloc expanded" %} 10687 postalloc_expand %{ 10688 // 10689 // replaces 10690 // 10691 // region src1 src2 10692 // \ | | 10693 // crx=cmpD_reg_reg 10694 // 10695 // with 10696 // 10697 // region src1 src2 10698 // \ | | 10699 // crx=cmpDUnordered_reg_reg 10700 // | 10701 // ^ region 10702 // | \ 10703 // crx=cmov_bns_less 10704 // 10705 10706 // create new nodes 10707 MachNode *m1 = new cmpDUnordered_reg_regNode(); 10708 MachNode *m2 = new cmov_bns_lessNode(); 10709 10710 // inputs for new nodes 10711 m1->add_req(n_region, n_src1, n_src2); 10712 m2->add_req(n_region); 10713 m2->add_prec(m1); 10714 10715 // operands for new nodes 10716 m1->_opnds[0] = op_crx; 10717 m1->_opnds[1] = op_src1; 10718 m1->_opnds[2] = op_src2; 10719 m2->_opnds[0] = op_crx; 10720 10721 // registers for new nodes 10722 ra_->set_pair(m1->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10723 ra_->set_pair(m2->_idx, ra_->get_reg_second(this), ra_->get_reg_first(this)); // crx 10724 10725 // Insert new nodes. 10726 nodes->push(m1); 10727 nodes->push(m2); 10728 %} 10729 %} 10730 10731 // Compare double, generate -1,0,1 10732 instruct cmpD3_reg_reg_ExEx(iRegIdst dst, regD src1, regD src2) %{ 10733 match(Set dst (CmpD3 src1 src2)); 10734 ins_cost(DEFAULT_COST*5+BRANCH_COST); 10735 10736 expand %{ 10737 flagsReg tmp1; 10738 cmpDUnordered_reg_reg(tmp1, src1, src2); 10739 cmovI_conIvalueMinus1_conIvalue0_conIvalue1_Ex(dst, tmp1); 10740 %} 10741 %} 10742 10743 //----------Branches--------------------------------------------------------- 10744 // Jump 10745 10746 // Direct Branch. 10747 instruct branch(label labl) %{ 10748 match(Goto); 10749 effect(USE labl); 10750 ins_cost(BRANCH_COST); 10751 10752 format %{ "B $labl" %} 10753 size(4); 10754 ins_encode %{ 10755 // TODO: PPC port $archOpcode(ppc64Opcode_b); 10756 Label d; // dummy 10757 __ bind(d); 10758 Label* p = $labl$$label; 10759 // `p' is `NULL' when this encoding class is used only to 10760 // determine the size of the encoded instruction. 10761 Label& l = (NULL == p)? d : *(p); 10762 __ b(l); 10763 %} 10764 ins_pipe(pipe_class_default); 10765 %} 10766 10767 // Conditional Near Branch 10768 instruct branchCon(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10769 // Same match rule as `branchConFar'. 10770 match(If cmp crx); 10771 effect(USE lbl); 10772 ins_cost(BRANCH_COST); 10773 10774 // If set to 1 this indicates that the current instruction is a 10775 // short variant of a long branch. This avoids using this 10776 // instruction in first-pass matching. It will then only be used in 10777 // the `Shorten_branches' pass. 10778 ins_short_branch(1); 10779 10780 format %{ "B$cmp $crx, $lbl" %} 10781 size(4); 10782 ins_encode( enc_bc(crx, cmp, lbl) ); 10783 ins_pipe(pipe_class_default); 10784 %} 10785 10786 // This is for cases when the ppc64 `bc' instruction does not 10787 // reach far enough. So we emit a far branch here, which is more 10788 // expensive. 10789 // 10790 // Conditional Far Branch 10791 instruct branchConFar(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10792 // Same match rule as `branchCon'. 10793 match(If cmp crx); 10794 effect(USE crx, USE lbl); 10795 predicate(!false /* TODO: PPC port HB_Schedule*/); 10796 // Higher cost than `branchCon'. 10797 ins_cost(5*BRANCH_COST); 10798 10799 // This is not a short variant of a branch, but the long variant. 10800 ins_short_branch(0); 10801 10802 format %{ "B_FAR$cmp $crx, $lbl" %} 10803 size(8); 10804 ins_encode( enc_bc_far(crx, cmp, lbl) ); 10805 ins_pipe(pipe_class_default); 10806 %} 10807 10808 // Conditional Branch used with Power6 scheduler (can be far or short). 10809 instruct branchConSched(cmpOp cmp, flagsRegSrc crx, label lbl) %{ 10810 // Same match rule as `branchCon'. 10811 match(If cmp crx); 10812 effect(USE crx, USE lbl); 10813 predicate(false /* TODO: PPC port HB_Schedule*/); 10814 // Higher cost than `branchCon'. 10815 ins_cost(5*BRANCH_COST); 10816 10817 // Actually size doesn't depend on alignment but on shortening. 10818 ins_variable_size_depending_on_alignment(true); 10819 // long variant. 10820 ins_short_branch(0); 10821 10822 format %{ "B_FAR$cmp $crx, $lbl" %} 10823 size(8); // worst case 10824 ins_encode( enc_bc_short_far(crx, cmp, lbl) ); 10825 ins_pipe(pipe_class_default); 10826 %} 10827 10828 instruct branchLoopEnd(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10829 match(CountedLoopEnd cmp crx); 10830 effect(USE labl); 10831 ins_cost(BRANCH_COST); 10832 10833 // short variant. 10834 ins_short_branch(1); 10835 10836 format %{ "B$cmp $crx, $labl \t// counted loop end" %} 10837 size(4); 10838 ins_encode( enc_bc(crx, cmp, labl) ); 10839 ins_pipe(pipe_class_default); 10840 %} 10841 10842 instruct branchLoopEndFar(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10843 match(CountedLoopEnd cmp crx); 10844 effect(USE labl); 10845 predicate(!false /* TODO: PPC port HB_Schedule */); 10846 ins_cost(BRANCH_COST); 10847 10848 // Long variant. 10849 ins_short_branch(0); 10850 10851 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10852 size(8); 10853 ins_encode( enc_bc_far(crx, cmp, labl) ); 10854 ins_pipe(pipe_class_default); 10855 %} 10856 10857 // Conditional Branch used with Power6 scheduler (can be far or short). 10858 instruct branchLoopEndSched(cmpOp cmp, flagsRegSrc crx, label labl) %{ 10859 match(CountedLoopEnd cmp crx); 10860 effect(USE labl); 10861 predicate(false /* TODO: PPC port HB_Schedule */); 10862 // Higher cost than `branchCon'. 10863 ins_cost(5*BRANCH_COST); 10864 10865 // Actually size doesn't depend on alignment but on shortening. 10866 ins_variable_size_depending_on_alignment(true); 10867 // Long variant. 10868 ins_short_branch(0); 10869 10870 format %{ "B_FAR$cmp $crx, $labl \t// counted loop end" %} 10871 size(8); // worst case 10872 ins_encode( enc_bc_short_far(crx, cmp, labl) ); 10873 ins_pipe(pipe_class_default); 10874 %} 10875 10876 // ============================================================================ 10877 // Java runtime operations, intrinsics and other complex operations. 10878 10879 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass 10880 // array for an instance of the superklass. Set a hidden internal cache on a 10881 // hit (cache is checked with exposed code in gen_subtype_check()). Return 10882 // not zero for a miss or zero for a hit. The encoding ALSO sets flags. 10883 // 10884 // GL TODO: Improve this. 10885 // - result should not be a TEMP 10886 // - Add match rule as on sparc avoiding additional Cmp. 10887 instruct partialSubtypeCheck(iRegPdst result, iRegP_N2P subklass, iRegP_N2P superklass, 10888 iRegPdst tmp_klass, iRegPdst tmp_arrayptr) %{ 10889 match(Set result (PartialSubtypeCheck subklass superklass)); 10890 effect(TEMP_DEF result, TEMP tmp_klass, TEMP tmp_arrayptr); 10891 ins_cost(DEFAULT_COST*10); 10892 10893 format %{ "PartialSubtypeCheck $result = ($subklass instanceOf $superklass) tmp: $tmp_klass, $tmp_arrayptr" %} 10894 ins_encode %{ 10895 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10896 __ check_klass_subtype_slow_path($subklass$$Register, $superklass$$Register, $tmp_arrayptr$$Register, 10897 $tmp_klass$$Register, NULL, $result$$Register); 10898 %} 10899 ins_pipe(pipe_class_default); 10900 %} 10901 10902 // inlined locking and unlocking 10903 10904 instruct cmpFastLock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2) %{ 10905 match(Set crx (FastLock oop box)); 10906 effect(TEMP tmp1, TEMP tmp2); 10907 predicate(!Compile::current()->use_rtm()); 10908 10909 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2" %} 10910 ins_encode %{ 10911 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10912 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10913 $tmp1$$Register, $tmp2$$Register, /*tmp3*/ R0, 10914 UseBiasedLocking && !UseOptoBiasInlining); 10915 // If locking was successfull, crx should indicate 'EQ'. 10916 // The compiler generates a branch to the runtime call to 10917 // _complete_monitor_locking_Java for the case where crx is 'NE'. 10918 %} 10919 ins_pipe(pipe_class_compare); 10920 %} 10921 10922 // Separate version for TM. Use bound register for box to enable USE_KILL. 10923 instruct cmpFastLock_tm(flagsReg crx, iRegPdst oop, rarg2RegP box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10924 match(Set crx (FastLock oop box)); 10925 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, USE_KILL box); 10926 predicate(Compile::current()->use_rtm()); 10927 10928 format %{ "FASTLOCK $oop, $box, $tmp1, $tmp2, $tmp3 (TM)" %} 10929 ins_encode %{ 10930 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10931 __ compiler_fast_lock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10932 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, 10933 /*Biased Locking*/ false, 10934 _rtm_counters, _stack_rtm_counters, 10935 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(), 10936 /*TM*/ true, ra_->C->profile_rtm()); 10937 // If locking was successfull, crx should indicate 'EQ'. 10938 // The compiler generates a branch to the runtime call to 10939 // _complete_monitor_locking_Java for the case where crx is 'NE'. 10940 %} 10941 ins_pipe(pipe_class_compare); 10942 %} 10943 10944 instruct cmpFastUnlock(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10945 match(Set crx (FastUnlock oop box)); 10946 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10947 predicate(!Compile::current()->use_rtm()); 10948 10949 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2" %} 10950 ins_encode %{ 10951 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10952 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10953 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, 10954 UseBiasedLocking && !UseOptoBiasInlining, 10955 false); 10956 // If unlocking was successfull, crx should indicate 'EQ'. 10957 // The compiler generates a branch to the runtime call to 10958 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. 10959 %} 10960 ins_pipe(pipe_class_compare); 10961 %} 10962 10963 instruct cmpFastUnlock_tm(flagsReg crx, iRegPdst oop, iRegPdst box, iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3) %{ 10964 match(Set crx (FastUnlock oop box)); 10965 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3); 10966 predicate(Compile::current()->use_rtm()); 10967 10968 format %{ "FASTUNLOCK $oop, $box, $tmp1, $tmp2 (TM)" %} 10969 ins_encode %{ 10970 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 10971 __ compiler_fast_unlock_object($crx$$CondRegister, $oop$$Register, $box$$Register, 10972 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, 10973 /*Biased Locking*/ false, /*TM*/ true); 10974 // If unlocking was successfull, crx should indicate 'EQ'. 10975 // The compiler generates a branch to the runtime call to 10976 // _complete_monitor_unlocking_Java for the case where crx is 'NE'. 10977 %} 10978 ins_pipe(pipe_class_compare); 10979 %} 10980 10981 // Align address. 10982 instruct align_addr(iRegPdst dst, iRegPsrc src, immLnegpow2 mask) %{ 10983 match(Set dst (CastX2P (AndL (CastP2X src) mask))); 10984 10985 format %{ "ANDDI $dst, $src, $mask \t// next aligned address" %} 10986 size(4); 10987 ins_encode %{ 10988 // TODO: PPC port $archOpcode(ppc64Opcode_rldicr); 10989 __ clrrdi($dst$$Register, $src$$Register, log2_long((jlong)-$mask$$constant)); 10990 %} 10991 ins_pipe(pipe_class_default); 10992 %} 10993 10994 // Array size computation. 10995 instruct array_size(iRegLdst dst, iRegPsrc end, iRegPsrc start) %{ 10996 match(Set dst (SubL (CastP2X end) (CastP2X start))); 10997 10998 format %{ "SUB $dst, $end, $start \t// array size in bytes" %} 10999 size(4); 11000 ins_encode %{ 11001 // TODO: PPC port $archOpcode(ppc64Opcode_subf); 11002 __ subf($dst$$Register, $start$$Register, $end$$Register); 11003 %} 11004 ins_pipe(pipe_class_default); 11005 %} 11006 11007 // Clear-array with dynamic array-size. 11008 instruct inlineCallClearArray(rarg1RegL cnt, rarg2RegP base, Universe dummy, regCTR ctr) %{ 11009 match(Set dummy (ClearArray cnt base)); 11010 effect(USE_KILL cnt, USE_KILL base, KILL ctr); 11011 ins_cost(MEMORY_REF_COST); 11012 11013 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11014 11015 format %{ "ClearArray $cnt, $base" %} 11016 ins_encode %{ 11017 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11018 __ clear_memory_doubleword($base$$Register, $cnt$$Register); // kills cnt, base, R0 11019 %} 11020 ins_pipe(pipe_class_default); 11021 %} 11022 11023 instruct string_compareL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, 11024 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{ 11025 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL); 11026 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11027 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp); 11028 ins_cost(300); 11029 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %} 11030 ins_encode %{ 11031 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11032 __ string_compare($str1$$Register, $str2$$Register, 11033 $cnt1$$Register, $cnt2$$Register, 11034 $tmp$$Register, 11035 $result$$Register, StrIntrinsicNode::LL); 11036 %} 11037 ins_pipe(pipe_class_default); 11038 %} 11039 11040 instruct string_compareU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, 11041 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{ 11042 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU); 11043 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11044 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp); 11045 ins_cost(300); 11046 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %} 11047 ins_encode %{ 11048 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11049 __ string_compare($str1$$Register, $str2$$Register, 11050 $cnt1$$Register, $cnt2$$Register, 11051 $tmp$$Register, 11052 $result$$Register, StrIntrinsicNode::UU); 11053 %} 11054 ins_pipe(pipe_class_default); 11055 %} 11056 11057 instruct string_compareLU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, 11058 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{ 11059 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU); 11060 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11061 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp); 11062 ins_cost(300); 11063 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %} 11064 ins_encode %{ 11065 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11066 __ string_compare($str1$$Register, $str2$$Register, 11067 $cnt1$$Register, $cnt2$$Register, 11068 $tmp$$Register, 11069 $result$$Register, StrIntrinsicNode::LU); 11070 %} 11071 ins_pipe(pipe_class_default); 11072 %} 11073 11074 instruct string_compareUL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, 11075 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{ 11076 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL); 11077 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11078 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ctr, KILL cr0, TEMP tmp); 11079 ins_cost(300); 11080 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result \t// KILL $tmp" %} 11081 ins_encode %{ 11082 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11083 __ string_compare($str2$$Register, $str1$$Register, 11084 $cnt2$$Register, $cnt1$$Register, 11085 $tmp$$Register, 11086 $result$$Register, StrIntrinsicNode::UL); 11087 %} 11088 ins_pipe(pipe_class_default); 11089 %} 11090 11091 instruct string_equalsL(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result, 11092 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{ 11093 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::LL); 11094 match(Set result (StrEquals (Binary str1 str2) cnt)); 11095 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0); 11096 ins_cost(300); 11097 format %{ "String Equals byte[] $str1,$str2,$cnt -> $result \t// KILL $tmp" %} 11098 ins_encode %{ 11099 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11100 __ array_equals(false, $str1$$Register, $str2$$Register, 11101 $cnt$$Register, $tmp$$Register, 11102 $result$$Register, true /* byte */); 11103 %} 11104 ins_pipe(pipe_class_default); 11105 %} 11106 11107 instruct string_equalsU(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt, iRegIdst result, 11108 iRegIdst tmp, regCTR ctr, flagsRegCR0 cr0) %{ 11109 predicate(((StrEqualsNode*)n)->encoding() == StrIntrinsicNode::UU); 11110 match(Set result (StrEquals (Binary str1 str2) cnt)); 11111 effect(TEMP_DEF result, USE_KILL str1, USE_KILL str2, USE_KILL cnt, TEMP tmp, KILL ctr, KILL cr0); 11112 ins_cost(300); 11113 format %{ "String Equals char[] $str1,$str2,$cnt -> $result \t// KILL $tmp" %} 11114 ins_encode %{ 11115 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11116 __ array_equals(false, $str1$$Register, $str2$$Register, 11117 $cnt$$Register, $tmp$$Register, 11118 $result$$Register, false /* byte */); 11119 %} 11120 ins_pipe(pipe_class_default); 11121 %} 11122 11123 instruct array_equalsB(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result, 11124 iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{ 11125 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL); 11126 match(Set result (AryEq ary1 ary2)); 11127 effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1); 11128 ins_cost(300); 11129 format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %} 11130 ins_encode %{ 11131 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11132 __ array_equals(true, $ary1$$Register, $ary2$$Register, 11133 $tmp1$$Register, $tmp2$$Register, 11134 $result$$Register, true /* byte */); 11135 %} 11136 ins_pipe(pipe_class_default); 11137 %} 11138 11139 instruct array_equalsC(rarg1RegP ary1, rarg2RegP ary2, iRegIdst result, 11140 iRegIdst tmp1, iRegIdst tmp2, regCTR ctr, flagsRegCR0 cr0, flagsRegCR0 cr1) %{ 11141 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU); 11142 match(Set result (AryEq ary1 ary2)); 11143 effect(TEMP_DEF result, USE_KILL ary1, USE_KILL ary2, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0, KILL cr1); 11144 ins_cost(300); 11145 format %{ "Array Equals $ary1,$ary2 -> $result \t// KILL $tmp1,$tmp2" %} 11146 ins_encode %{ 11147 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11148 __ array_equals(true, $ary1$$Register, $ary2$$Register, 11149 $tmp1$$Register, $tmp2$$Register, 11150 $result$$Register, false /* byte */); 11151 %} 11152 ins_pipe(pipe_class_default); 11153 %} 11154 11155 instruct indexOf_imm1_char_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11156 immP needleImm, immL offsetImm, immI_1 needlecntImm, 11157 iRegIdst tmp1, iRegIdst tmp2, 11158 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11159 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); 11160 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11161 // Required for EA: check if it is still a type_array. 11162 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU); 11163 ins_cost(150); 11164 11165 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" 11166 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11167 11168 ins_encode %{ 11169 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11170 immPOper *needleOper = (immPOper *)$needleImm; 11171 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 11172 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 11173 jchar chr; 11174 #ifdef VM_LITTLE_ENDIAN 11175 chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) | 11176 ((jchar)(unsigned char)needle_values->element_value(0).as_byte()); 11177 #else 11178 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) | 11179 ((jchar)(unsigned char)needle_values->element_value(1).as_byte()); 11180 #endif 11181 __ string_indexof_char($result$$Register, 11182 $haystack$$Register, $haycnt$$Register, 11183 R0, chr, 11184 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/); 11185 %} 11186 ins_pipe(pipe_class_compare); 11187 %} 11188 11189 instruct indexOf_imm1_char_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11190 immP needleImm, immL offsetImm, immI_1 needlecntImm, 11191 iRegIdst tmp1, iRegIdst tmp2, 11192 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11193 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); 11194 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11195 // Required for EA: check if it is still a type_array. 11196 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 11197 ins_cost(150); 11198 11199 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" 11200 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11201 11202 ins_encode %{ 11203 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11204 immPOper *needleOper = (immPOper *)$needleImm; 11205 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 11206 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 11207 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 11208 __ string_indexof_char($result$$Register, 11209 $haystack$$Register, $haycnt$$Register, 11210 R0, chr, 11211 $tmp1$$Register, $tmp2$$Register, true /*is_byte*/); 11212 %} 11213 ins_pipe(pipe_class_compare); 11214 %} 11215 11216 instruct indexOf_imm1_char_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11217 immP needleImm, immL offsetImm, immI_1 needlecntImm, 11218 iRegIdst tmp1, iRegIdst tmp2, 11219 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11220 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); 11221 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11222 // Required for EA: check if it is still a type_array. 11223 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 11224 ins_cost(150); 11225 11226 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" 11227 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11228 11229 ins_encode %{ 11230 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11231 immPOper *needleOper = (immPOper *)$needleImm; 11232 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 11233 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 11234 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 11235 __ string_indexof_char($result$$Register, 11236 $haystack$$Register, $haycnt$$Register, 11237 R0, chr, 11238 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/); 11239 %} 11240 ins_pipe(pipe_class_compare); 11241 %} 11242 11243 instruct indexOf_imm1_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11244 rscratch2RegP needle, immI_1 needlecntImm, 11245 iRegIdst tmp1, iRegIdst tmp2, 11246 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11247 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11248 effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11249 // Required for EA: check if it is still a type_array. 11250 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU && 11251 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11252 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11253 ins_cost(180); 11254 11255 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11256 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} 11257 ins_encode %{ 11258 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11259 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11260 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11261 guarantee(needle_values, "sanity"); 11262 jchar chr; 11263 #ifdef VM_LITTLE_ENDIAN 11264 chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) | 11265 ((jchar)(unsigned char)needle_values->element_value(0).as_byte()); 11266 #else 11267 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) | 11268 ((jchar)(unsigned char)needle_values->element_value(1).as_byte()); 11269 #endif 11270 __ string_indexof_char($result$$Register, 11271 $haystack$$Register, $haycnt$$Register, 11272 R0, chr, 11273 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/); 11274 %} 11275 ins_pipe(pipe_class_compare); 11276 %} 11277 11278 instruct indexOf_imm1_L(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11279 rscratch2RegP needle, immI_1 needlecntImm, 11280 iRegIdst tmp1, iRegIdst tmp2, 11281 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11282 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11283 effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11284 // Required for EA: check if it is still a type_array. 11285 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL && 11286 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11287 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11288 ins_cost(180); 11289 11290 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11291 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} 11292 ins_encode %{ 11293 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11294 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11295 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11296 guarantee(needle_values, "sanity"); 11297 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 11298 __ string_indexof_char($result$$Register, 11299 $haystack$$Register, $haycnt$$Register, 11300 R0, chr, 11301 $tmp1$$Register, $tmp2$$Register, true /*is_byte*/); 11302 %} 11303 ins_pipe(pipe_class_compare); 11304 %} 11305 11306 instruct indexOf_imm1_UL(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11307 rscratch2RegP needle, immI_1 needlecntImm, 11308 iRegIdst tmp1, iRegIdst tmp2, 11309 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11310 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11311 effect(USE_KILL needle, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11312 // Required for EA: check if it is still a type_array. 11313 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL && 11314 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11315 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11316 ins_cost(180); 11317 11318 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11319 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} 11320 ins_encode %{ 11321 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11322 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11323 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11324 guarantee(needle_values, "sanity"); 11325 jchar chr = (jchar)needle_values->element_value(0).as_byte(); 11326 __ string_indexof_char($result$$Register, 11327 $haystack$$Register, $haycnt$$Register, 11328 R0, chr, 11329 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/); 11330 %} 11331 ins_pipe(pipe_class_compare); 11332 %} 11333 11334 instruct indexOfChar_U(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11335 iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2, 11336 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11337 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch)); 11338 effect(TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11339 predicate(CompactStrings); 11340 ins_cost(180); 11341 11342 format %{ "String IndexOfChar $haystack[0..$haycnt], $ch" 11343 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11344 ins_encode %{ 11345 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11346 __ string_indexof_char($result$$Register, 11347 $haystack$$Register, $haycnt$$Register, 11348 $ch$$Register, 0 /* this is not used if the character is already in a register */, 11349 $tmp1$$Register, $tmp2$$Register, false /*is_byte*/); 11350 %} 11351 ins_pipe(pipe_class_compare); 11352 %} 11353 11354 instruct indexOf_imm_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, 11355 iRegPsrc needle, uimmI15 needlecntImm, 11356 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, 11357 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11358 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11359 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result, 11360 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11361 // Required for EA: check if it is still a type_array. 11362 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU && 11363 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11364 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11365 ins_cost(250); 11366 11367 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11368 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} 11369 ins_encode %{ 11370 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11371 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11372 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11373 11374 __ string_indexof($result$$Register, 11375 $haystack$$Register, $haycnt$$Register, 11376 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, 11377 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU); 11378 %} 11379 ins_pipe(pipe_class_compare); 11380 %} 11381 11382 instruct indexOf_imm_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, 11383 iRegPsrc needle, uimmI15 needlecntImm, 11384 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, 11385 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11386 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11387 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result, 11388 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11389 // Required for EA: check if it is still a type_array. 11390 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL && 11391 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11392 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11393 ins_cost(250); 11394 11395 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11396 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} 11397 ins_encode %{ 11398 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11399 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11400 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11401 11402 __ string_indexof($result$$Register, 11403 $haystack$$Register, $haycnt$$Register, 11404 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, 11405 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL); 11406 %} 11407 ins_pipe(pipe_class_compare); 11408 %} 11409 11410 instruct indexOf_imm_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, 11411 iRegPsrc needle, uimmI15 needlecntImm, 11412 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, 11413 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11414 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11415 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result, 11416 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11417 // Required for EA: check if it is still a type_array. 11418 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL && 11419 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11420 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11421 ins_cost(250); 11422 11423 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11424 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} 11425 ins_encode %{ 11426 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11427 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11428 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11429 11430 __ string_indexof($result$$Register, 11431 $haystack$$Register, $haycnt$$Register, 11432 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, 11433 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL); 11434 %} 11435 ins_pipe(pipe_class_compare); 11436 %} 11437 11438 instruct indexOf_U(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, 11439 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, 11440 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11441 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 11442 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ 11443 TEMP_DEF result, 11444 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11445 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU); 11446 ins_cost(300); 11447 11448 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" 11449 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} 11450 ins_encode %{ 11451 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11452 __ string_indexof($result$$Register, 11453 $haystack$$Register, $haycnt$$Register, 11454 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. 11455 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UU); 11456 %} 11457 ins_pipe(pipe_class_compare); 11458 %} 11459 11460 instruct indexOf_L(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, 11461 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, 11462 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11463 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 11464 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ 11465 TEMP_DEF result, 11466 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11467 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL); 11468 ins_cost(300); 11469 11470 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" 11471 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} 11472 ins_encode %{ 11473 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11474 __ string_indexof($result$$Register, 11475 $haystack$$Register, $haycnt$$Register, 11476 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. 11477 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::LL); 11478 %} 11479 ins_pipe(pipe_class_compare); 11480 %} 11481 11482 instruct indexOf_UL(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, 11483 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, 11484 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11485 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 11486 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ 11487 TEMP_DEF result, 11488 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11489 predicate(((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL); 11490 ins_cost(300); 11491 11492 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" 11493 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} 11494 ins_encode %{ 11495 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11496 __ string_indexof($result$$Register, 11497 $haystack$$Register, $haycnt$$Register, 11498 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. 11499 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, StrIntrinsicNode::UL); 11500 %} 11501 ins_pipe(pipe_class_compare); 11502 %} 11503 11504 // char[] to byte[] compression 11505 instruct string_compress(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1, 11506 iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{ 11507 match(Set result (StrCompressedCopy src (Binary dst len))); 11508 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, 11509 USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0); 11510 ins_cost(300); 11511 format %{ "String Compress $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} 11512 ins_encode %{ 11513 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11514 Label Lskip, Ldone; 11515 __ li($result$$Register, 0); 11516 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register, 11517 $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Ldone); 11518 __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters. 11519 __ beq(CCR0, Lskip); 11520 __ string_compress($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register, Ldone); 11521 __ bind(Lskip); 11522 __ mr($result$$Register, $len$$Register); 11523 __ bind(Ldone); 11524 %} 11525 ins_pipe(pipe_class_default); 11526 %} 11527 11528 // byte[] to char[] inflation 11529 instruct string_inflate(Universe dummy, rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegLdst tmp1, 11530 iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{ 11531 match(Set dummy (StrInflatedCopy src (Binary dst len))); 11532 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0); 11533 ins_cost(300); 11534 format %{ "String Inflate $src,$dst,$len \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} 11535 ins_encode %{ 11536 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11537 Label Ldone; 11538 __ string_inflate_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register, 11539 $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register); 11540 __ rldicl_($tmp1$$Register, $len$$Register, 0, 64-3); // Remaining characters. 11541 __ beq(CCR0, Ldone); 11542 __ string_inflate($src$$Register, $dst$$Register, $tmp1$$Register, $tmp2$$Register); 11543 __ bind(Ldone); 11544 %} 11545 ins_pipe(pipe_class_default); 11546 %} 11547 11548 // StringCoding.java intrinsics 11549 instruct has_negatives(rarg1RegP ary1, iRegIsrc len, iRegIdst result, iRegLdst tmp1, iRegLdst tmp2, 11550 regCTR ctr, flagsRegCR0 cr0) 11551 %{ 11552 match(Set result (HasNegatives ary1 len)); 11553 effect(TEMP_DEF result, USE_KILL ary1, TEMP tmp1, TEMP tmp2, KILL ctr, KILL cr0); 11554 ins_cost(300); 11555 format %{ "has negatives byte[] $ary1,$len -> $result \t// KILL $tmp1, $tmp2" %} 11556 ins_encode %{ 11557 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11558 __ has_negatives($ary1$$Register, $len$$Register, $result$$Register, 11559 $tmp1$$Register, $tmp2$$Register); 11560 %} 11561 ins_pipe(pipe_class_default); 11562 %} 11563 11564 // encode char[] to byte[] in ISO_8859_1 11565 instruct encode_iso_array(rarg1RegP src, rarg2RegP dst, iRegIsrc len, iRegIdst result, iRegLdst tmp1, 11566 iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, iRegLdst tmp5, regCTR ctr, flagsRegCR0 cr0) %{ 11567 match(Set result (EncodeISOArray src (Binary dst len))); 11568 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, 11569 USE_KILL src, USE_KILL dst, KILL ctr, KILL cr0); 11570 ins_cost(300); 11571 format %{ "Encode array $src,$dst,$len -> $result \t// KILL $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} 11572 ins_encode %{ 11573 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11574 Label Lslow, Lfailure1, Lfailure2, Ldone; 11575 __ string_compress_16($src$$Register, $dst$$Register, $len$$Register, $tmp1$$Register, 11576 $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register, Lfailure1); 11577 __ rldicl_($result$$Register, $len$$Register, 0, 64-3); // Remaining characters. 11578 __ beq(CCR0, Ldone); 11579 __ bind(Lslow); 11580 __ string_compress($src$$Register, $dst$$Register, $result$$Register, $tmp2$$Register, Lfailure2); 11581 __ li($result$$Register, 0); 11582 __ b(Ldone); 11583 11584 __ bind(Lfailure1); 11585 __ mr($result$$Register, $len$$Register); 11586 __ mfctr($tmp1$$Register); 11587 __ rldimi_($result$$Register, $tmp1$$Register, 3, 0); // Remaining characters. 11588 __ beq(CCR0, Ldone); 11589 __ b(Lslow); 11590 11591 __ bind(Lfailure2); 11592 __ mfctr($result$$Register); // Remaining characters. 11593 11594 __ bind(Ldone); 11595 __ subf($result$$Register, $result$$Register, $len$$Register); 11596 %} 11597 ins_pipe(pipe_class_default); 11598 %} 11599 11600 11601 // String_IndexOf for needle of length 1. 11602 // 11603 // Match needle into immediate operands: no loadConP node needed. Saves one 11604 // register and two instructions over string_indexOf_imm1Node. 11605 // 11606 // Assumes register result differs from all input registers. 11607 // 11608 // Preserves registers haystack, haycnt 11609 // Kills registers tmp1, tmp2 11610 // Defines registers result 11611 // 11612 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11613 // 11614 // Unfortunately this does not match too often. In many situations the AddP is used 11615 // by several nodes, even several StrIndexOf nodes, breaking the match tree. 11616 instruct string_indexOf_imm1_char(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11617 immP needleImm, immL offsetImm, immI_1 needlecntImm, 11618 iRegIdst tmp1, iRegIdst tmp2, 11619 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11620 predicate(SpecialStringIndexOf && !CompactStrings); // type check implicit by parameter type, See Matcher::match_rule_supported 11621 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary (AddP needleImm offsetImm) needlecntImm))); 11622 11623 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11624 11625 ins_cost(150); 11626 format %{ "String IndexOf CSCL1 $haystack[0..$haycnt], $needleImm+$offsetImm[0..$needlecntImm]" 11627 "-> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11628 11629 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted 11630 ins_encode %{ 11631 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11632 immPOper *needleOper = (immPOper *)$needleImm; 11633 const TypeOopPtr *t = needleOper->type()->isa_oopptr(); 11634 ciTypeArray* needle_values = t->const_oop()->as_type_array(); // Pointer to live char * 11635 jchar chr; 11636 if (java_lang_String::has_coder_field()) { 11637 // New compact strings byte array strings 11638 #ifdef VM_LITTLE_ENDIAN 11639 chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) | 11640 ((jchar)(unsigned char)needle_values->element_value(0).as_byte()); 11641 #else 11642 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) | 11643 ((jchar)(unsigned char)needle_values->element_value(1).as_byte()); 11644 #endif 11645 } else { 11646 // Old char array strings 11647 chr = needle_values->char_at(0); 11648 } 11649 __ string_indexof_1($result$$Register, 11650 $haystack$$Register, $haycnt$$Register, 11651 R0, chr, 11652 $tmp1$$Register, $tmp2$$Register); 11653 %} 11654 ins_pipe(pipe_class_compare); 11655 %} 11656 11657 // String_IndexOf for needle of length 1. 11658 // 11659 // Special case requires less registers and emits less instructions. 11660 // 11661 // Assumes register result differs from all input registers. 11662 // 11663 // Preserves registers haystack, haycnt 11664 // Kills registers tmp1, tmp2, needle 11665 // Defines registers result 11666 // 11667 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11668 instruct string_indexOf_imm1(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11669 rscratch2RegP needle, immI_1 needlecntImm, 11670 iRegIdst tmp1, iRegIdst tmp2, 11671 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11672 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11673 effect(USE_KILL needle, /* TDEF needle, */ TEMP_DEF result, 11674 TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11675 // Required for EA: check if it is still a type_array. 11676 predicate(SpecialStringIndexOf && !CompactStrings && 11677 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11678 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11679 ins_cost(180); 11680 11681 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11682 11683 format %{ "String IndexOf SCL1 $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11684 " -> $result \t// KILL $haycnt, $needle, $tmp1, $tmp2, $cr0, $cr1" %} 11685 ins_encode %{ 11686 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11687 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11688 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11689 guarantee(needle_values, "sanity"); 11690 jchar chr; 11691 if (java_lang_String::has_coder_field()) { 11692 // New compact strings byte array strings 11693 #ifdef VM_LITTLE_ENDIAN 11694 chr = (((jchar)(unsigned char)needle_values->element_value(1).as_byte()) << 8) | 11695 ((jchar)(unsigned char)needle_values->element_value(0).as_byte()); 11696 #else 11697 chr = (((jchar)(unsigned char)needle_values->element_value(0).as_byte()) << 8) | 11698 ((jchar)(unsigned char)needle_values->element_value(1).as_byte()); 11699 #endif 11700 } else { 11701 // Old char array strings 11702 chr = needle_values->char_at(0); 11703 } 11704 __ string_indexof_1($result$$Register, 11705 $haystack$$Register, $haycnt$$Register, 11706 R0, chr, 11707 $tmp1$$Register, $tmp2$$Register); 11708 %} 11709 ins_pipe(pipe_class_compare); 11710 %} 11711 11712 // String_IndexOfChar 11713 // 11714 // Assumes register result differs from all input registers. 11715 // 11716 // Preserves registers haystack, haycnt 11717 // Kills registers tmp1, tmp2 11718 // Defines registers result 11719 // 11720 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11721 instruct string_indexOfChar(iRegIdst result, iRegPsrc haystack, iRegIsrc haycnt, 11722 iRegIsrc ch, iRegIdst tmp1, iRegIdst tmp2, 11723 flagsRegCR0 cr0, flagsRegCR1 cr1, regCTR ctr) %{ 11724 match(Set result (StrIndexOfChar (Binary haystack haycnt) ch)); 11725 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, KILL cr0, KILL cr1, KILL ctr); 11726 predicate(SpecialStringIndexOf && !CompactStrings); 11727 ins_cost(180); 11728 11729 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11730 11731 format %{ "String IndexOfChar $haystack[0..$haycnt], $ch" 11732 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $cr0, $cr1" %} 11733 ins_encode %{ 11734 __ string_indexof_1($result$$Register, 11735 $haystack$$Register, $haycnt$$Register, 11736 $ch$$Register, 0 /* this is not used if the character is already in a register */, 11737 $tmp1$$Register, $tmp2$$Register); 11738 %} 11739 ins_pipe(pipe_class_compare); 11740 %} 11741 11742 // String_IndexOf. 11743 // 11744 // Length of needle as immediate. This saves instruction loading constant needle 11745 // length. 11746 // @@@ TODO Specify rules for length < 8 or so, and roll out comparison of needle 11747 // completely or do it in vector instruction. This should save registers for 11748 // needlecnt and needle. 11749 // 11750 // Assumes register result differs from all input registers. 11751 // Overwrites haycnt, needlecnt. 11752 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11753 instruct string_indexOf_imm(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, 11754 iRegPsrc needle, uimmI15 needlecntImm, 11755 iRegIdst tmp1, iRegIdst tmp2, iRegIdst tmp3, iRegIdst tmp4, iRegIdst tmp5, 11756 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11757 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecntImm))); 11758 effect(USE_KILL haycnt, /* better: TDEF haycnt, */ TEMP_DEF result, 11759 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11760 // Required for EA: check if it is still a type_array. 11761 predicate(SpecialStringIndexOf && !CompactStrings && n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop() && 11762 n->in(3)->in(1)->bottom_type()->is_aryptr()->const_oop()->is_type_array()); 11763 ins_cost(250); 11764 11765 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11766 11767 format %{ "String IndexOf SCL $haystack[0..$haycnt], $needle[0..$needlecntImm]" 11768 " -> $result \t// KILL $haycnt, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $cr0, $cr1" %} 11769 ins_encode %{ 11770 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11771 Node *ndl = in(operand_index($needle)); // The node that defines needle. 11772 ciTypeArray* needle_values = ndl->bottom_type()->is_aryptr()->const_oop()->as_type_array(); 11773 11774 __ string_indexof($result$$Register, 11775 $haystack$$Register, $haycnt$$Register, 11776 $needle$$Register, needle_values, $tmp5$$Register, $needlecntImm$$constant, 11777 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11778 %} 11779 ins_pipe(pipe_class_compare); 11780 %} 11781 11782 // StrIndexOf node. 11783 // 11784 // Assumes register result differs from all input registers. 11785 // Overwrites haycnt, needlecnt. 11786 // Use dst register classes if register gets killed, as it is the case for tmp registers! 11787 instruct string_indexOf(iRegIdst result, iRegPsrc haystack, rscratch1RegI haycnt, iRegPsrc needle, rscratch2RegI needlecnt, 11788 iRegLdst tmp1, iRegLdst tmp2, iRegLdst tmp3, iRegLdst tmp4, 11789 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11790 match(Set result (StrIndexOf (Binary haystack haycnt) (Binary needle needlecnt))); 11791 effect(USE_KILL haycnt, USE_KILL needlecnt, /*better: TDEF haycnt, TDEF needlecnt,*/ 11792 TEMP_DEF result, 11793 TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11794 predicate(SpecialStringIndexOf && !CompactStrings); // See Matcher::match_rule_supported. 11795 ins_cost(300); 11796 11797 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11798 11799 format %{ "String IndexOf $haystack[0..$haycnt], $needle[0..$needlecnt]" 11800 " -> $result \t// KILL $haycnt, $needlecnt, $tmp1, $tmp2, $tmp3, $tmp4, $cr0, $cr1" %} 11801 ins_encode %{ 11802 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11803 __ string_indexof($result$$Register, 11804 $haystack$$Register, $haycnt$$Register, 11805 $needle$$Register, NULL, $needlecnt$$Register, 0, // needlecnt not constant. 11806 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register); 11807 %} 11808 ins_pipe(pipe_class_compare); 11809 %} 11810 11811 // String equals with immediate. 11812 instruct string_equals_imm(iRegPsrc str1, iRegPsrc str2, uimmI15 cntImm, iRegIdst result, 11813 iRegPdst tmp1, iRegPdst tmp2, 11814 flagsRegCR0 cr0, flagsRegCR6 cr6, regCTR ctr) %{ 11815 match(Set result (StrEquals (Binary str1 str2) cntImm)); 11816 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, 11817 KILL cr0, KILL cr6, KILL ctr); 11818 predicate(SpecialStringEquals && !CompactStrings); // See Matcher::match_rule_supported. 11819 ins_cost(250); 11820 11821 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11822 11823 format %{ "String Equals SCL [0..$cntImm]($str1),[0..$cntImm]($str2)" 11824 " -> $result \t// KILL $cr0, $cr6, $ctr, TEMP $result, $tmp1, $tmp2" %} 11825 ins_encode %{ 11826 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11827 __ char_arrays_equalsImm($str1$$Register, $str2$$Register, $cntImm$$constant, 11828 $result$$Register, $tmp1$$Register, $tmp2$$Register); 11829 %} 11830 ins_pipe(pipe_class_compare); 11831 %} 11832 11833 // String equals. 11834 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11835 instruct string_equals(iRegPsrc str1, iRegPsrc str2, iRegIsrc cnt, iRegIdst result, 11836 iRegPdst tmp1, iRegPdst tmp2, iRegPdst tmp3, iRegPdst tmp4, iRegPdst tmp5, 11837 flagsRegCR0 cr0, flagsRegCR1 cr1, flagsRegCR6 cr6, regCTR ctr) %{ 11838 match(Set result (StrEquals (Binary str1 str2) cnt)); 11839 effect(TEMP_DEF result, TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, TEMP tmp5, 11840 KILL cr0, KILL cr1, KILL cr6, KILL ctr); 11841 predicate(SpecialStringEquals && !CompactStrings); // See Matcher::match_rule_supported. 11842 ins_cost(300); 11843 11844 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11845 11846 format %{ "String Equals [0..$cnt]($str1),[0..$cnt]($str2) -> $result" 11847 " \t// KILL $cr0, $cr1, $cr6, $ctr, TEMP $result, $tmp1, $tmp2, $tmp3, $tmp4, $tmp5" %} 11848 ins_encode %{ 11849 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11850 __ char_arrays_equals($str1$$Register, $str2$$Register, $cnt$$Register, $result$$Register, 11851 $tmp1$$Register, $tmp2$$Register, $tmp3$$Register, $tmp4$$Register, $tmp5$$Register); 11852 %} 11853 ins_pipe(pipe_class_compare); 11854 %} 11855 11856 // String compare. 11857 // Char[] pointers are passed in. 11858 // Use dst register classes if register gets killed, as it is the case for TEMP operands! 11859 instruct string_compare(rarg1RegP str1, rarg2RegP str2, rarg3RegI cnt1, rarg4RegI cnt2, iRegIdst result, 11860 iRegPdst tmp, flagsRegCR0 cr0, regCTR ctr) %{ 11861 predicate(!CompactStrings); 11862 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2))); 11863 effect(USE_KILL cnt1, USE_KILL cnt2, USE_KILL str1, USE_KILL str2, TEMP_DEF result, TEMP tmp, KILL cr0, KILL ctr); 11864 ins_cost(300); 11865 11866 ins_alignment(8); // 'compute_padding()' gets called, up to this number-1 nops will get inserted. 11867 11868 format %{ "String Compare $str1[0..$cnt1], $str2[0..$cnt2] -> $result" 11869 " \t// TEMP $tmp, $result KILLs $str1, $cnt1, $str2, $cnt2, $cr0, $ctr" %} 11870 ins_encode %{ 11871 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11872 __ string_compare($str1$$Register, $str2$$Register, $cnt1$$Register, $cnt2$$Register, 11873 $result$$Register, $tmp$$Register); 11874 %} 11875 ins_pipe(pipe_class_compare); 11876 %} 11877 11878 //---------- Min/Max Instructions --------------------------------------------- 11879 11880 instruct minI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11881 match(Set dst (MinI src1 src2)); 11882 ins_cost(DEFAULT_COST*6); 11883 11884 expand %{ 11885 iRegLdst src1s; 11886 iRegLdst src2s; 11887 iRegLdst diff; 11888 iRegLdst sm; 11889 iRegLdst doz; // difference or zero 11890 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11891 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11892 subL_reg_reg(diff, src2s, src1s); 11893 // Need to consider >=33 bit result, therefore we need signmaskL. 11894 signmask64L_regL(sm, diff); 11895 andL_reg_reg(doz, diff, sm); // <=0 11896 addI_regL_regL(dst, doz, src1s); 11897 %} 11898 %} 11899 11900 instruct minI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{ 11901 match(Set dst (MinI src1 src2)); 11902 effect(KILL cr0); 11903 predicate(VM_Version::has_isel()); 11904 ins_cost(DEFAULT_COST*2); 11905 11906 ins_encode %{ 11907 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11908 __ cmpw(CCR0, $src1$$Register, $src2$$Register); 11909 __ isel($dst$$Register, CCR0, Assembler::less, /*invert*/false, $src1$$Register, $src2$$Register); 11910 %} 11911 ins_pipe(pipe_class_default); 11912 %} 11913 11914 instruct maxI_reg_reg_Ex(iRegIdst dst, iRegIsrc src1, iRegIsrc src2) %{ 11915 match(Set dst (MaxI src1 src2)); 11916 ins_cost(DEFAULT_COST*6); 11917 11918 expand %{ 11919 iRegLdst src1s; 11920 iRegLdst src2s; 11921 iRegLdst diff; 11922 iRegLdst sm; 11923 iRegLdst doz; // difference or zero 11924 convI2L_reg(src1s, src1); // Ensure proper sign extension. 11925 convI2L_reg(src2s, src2); // Ensure proper sign extension. 11926 subL_reg_reg(diff, src2s, src1s); 11927 // Need to consider >=33 bit result, therefore we need signmaskL. 11928 signmask64L_regL(sm, diff); 11929 andcL_reg_reg(doz, diff, sm); // >=0 11930 addI_regL_regL(dst, doz, src1s); 11931 %} 11932 %} 11933 11934 instruct maxI_reg_reg_isel(iRegIdst dst, iRegIsrc src1, iRegIsrc src2, flagsRegCR0 cr0) %{ 11935 match(Set dst (MaxI src1 src2)); 11936 effect(KILL cr0); 11937 predicate(VM_Version::has_isel()); 11938 ins_cost(DEFAULT_COST*2); 11939 11940 ins_encode %{ 11941 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 11942 __ cmpw(CCR0, $src1$$Register, $src2$$Register); 11943 __ isel($dst$$Register, CCR0, Assembler::greater, /*invert*/false, $src1$$Register, $src2$$Register); 11944 %} 11945 ins_pipe(pipe_class_default); 11946 %} 11947 11948 //---------- Population Count Instructions ------------------------------------ 11949 11950 // Popcnt for Power7. 11951 instruct popCountI(iRegIdst dst, iRegIsrc src) %{ 11952 match(Set dst (PopCountI src)); 11953 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11954 ins_cost(DEFAULT_COST); 11955 11956 format %{ "POPCNTW $dst, $src" %} 11957 size(4); 11958 ins_encode %{ 11959 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11960 __ popcntw($dst$$Register, $src$$Register); 11961 %} 11962 ins_pipe(pipe_class_default); 11963 %} 11964 11965 // Popcnt for Power7. 11966 instruct popCountL(iRegIdst dst, iRegLsrc src) %{ 11967 predicate(UsePopCountInstruction && VM_Version::has_popcntw()); 11968 match(Set dst (PopCountL src)); 11969 ins_cost(DEFAULT_COST); 11970 11971 format %{ "POPCNTD $dst, $src" %} 11972 size(4); 11973 ins_encode %{ 11974 // TODO: PPC port $archOpcode(ppc64Opcode_popcntb); 11975 __ popcntd($dst$$Register, $src$$Register); 11976 %} 11977 ins_pipe(pipe_class_default); 11978 %} 11979 11980 instruct countLeadingZerosI(iRegIdst dst, iRegIsrc src) %{ 11981 match(Set dst (CountLeadingZerosI src)); 11982 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11983 ins_cost(DEFAULT_COST); 11984 11985 format %{ "CNTLZW $dst, $src" %} 11986 size(4); 11987 ins_encode %{ 11988 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzw); 11989 __ cntlzw($dst$$Register, $src$$Register); 11990 %} 11991 ins_pipe(pipe_class_default); 11992 %} 11993 11994 instruct countLeadingZerosL(iRegIdst dst, iRegLsrc src) %{ 11995 match(Set dst (CountLeadingZerosL src)); 11996 predicate(UseCountLeadingZerosInstructionsPPC64); // See Matcher::match_rule_supported. 11997 ins_cost(DEFAULT_COST); 11998 11999 format %{ "CNTLZD $dst, $src" %} 12000 size(4); 12001 ins_encode %{ 12002 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 12003 __ cntlzd($dst$$Register, $src$$Register); 12004 %} 12005 ins_pipe(pipe_class_default); 12006 %} 12007 12008 instruct countLeadingZerosP(iRegIdst dst, iRegPsrc src) %{ 12009 // no match-rule, false predicate 12010 effect(DEF dst, USE src); 12011 predicate(false); 12012 12013 format %{ "CNTLZD $dst, $src" %} 12014 size(4); 12015 ins_encode %{ 12016 // TODO: PPC port $archOpcode(ppc64Opcode_cntlzd); 12017 __ cntlzd($dst$$Register, $src$$Register); 12018 %} 12019 ins_pipe(pipe_class_default); 12020 %} 12021 12022 instruct countTrailingZerosI_Ex(iRegIdst dst, iRegIsrc src) %{ 12023 match(Set dst (CountTrailingZerosI src)); 12024 predicate(UseCountLeadingZerosInstructionsPPC64); 12025 ins_cost(DEFAULT_COST); 12026 12027 expand %{ 12028 immI16 imm1 %{ (int)-1 %} 12029 immI16 imm2 %{ (int)32 %} 12030 immI_minus1 m1 %{ -1 %} 12031 iRegIdst tmpI1; 12032 iRegIdst tmpI2; 12033 iRegIdst tmpI3; 12034 addI_reg_imm16(tmpI1, src, imm1); 12035 andcI_reg_reg(tmpI2, src, m1, tmpI1); 12036 countLeadingZerosI(tmpI3, tmpI2); 12037 subI_imm16_reg(dst, imm2, tmpI3); 12038 %} 12039 %} 12040 12041 instruct countTrailingZerosL_Ex(iRegIdst dst, iRegLsrc src) %{ 12042 match(Set dst (CountTrailingZerosL src)); 12043 predicate(UseCountLeadingZerosInstructionsPPC64); 12044 ins_cost(DEFAULT_COST); 12045 12046 expand %{ 12047 immL16 imm1 %{ (long)-1 %} 12048 immI16 imm2 %{ (int)64 %} 12049 iRegLdst tmpL1; 12050 iRegLdst tmpL2; 12051 iRegIdst tmpL3; 12052 addL_reg_imm16(tmpL1, src, imm1); 12053 andcL_reg_reg(tmpL2, tmpL1, src); 12054 countLeadingZerosL(tmpL3, tmpL2); 12055 subI_imm16_reg(dst, imm2, tmpL3); 12056 %} 12057 %} 12058 12059 // Expand nodes for byte_reverse_int. 12060 instruct insrwi_a(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 12061 effect(DEF dst, USE src, USE pos, USE shift); 12062 predicate(false); 12063 12064 format %{ "INSRWI $dst, $src, $pos, $shift" %} 12065 size(4); 12066 ins_encode %{ 12067 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 12068 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 12069 %} 12070 ins_pipe(pipe_class_default); 12071 %} 12072 12073 // As insrwi_a, but with USE_DEF. 12074 instruct insrwi(iRegIdst dst, iRegIsrc src, immI16 pos, immI16 shift) %{ 12075 effect(USE_DEF dst, USE src, USE pos, USE shift); 12076 predicate(false); 12077 12078 format %{ "INSRWI $dst, $src, $pos, $shift" %} 12079 size(4); 12080 ins_encode %{ 12081 // TODO: PPC port $archOpcode(ppc64Opcode_rlwimi); 12082 __ insrwi($dst$$Register, $src$$Register, $shift$$constant, $pos$$constant); 12083 %} 12084 ins_pipe(pipe_class_default); 12085 %} 12086 12087 // Just slightly faster than java implementation. 12088 instruct bytes_reverse_int_Ex(iRegIdst dst, iRegIsrc src) %{ 12089 match(Set dst (ReverseBytesI src)); 12090 predicate(UseCountLeadingZerosInstructionsPPC64); 12091 ins_cost(DEFAULT_COST); 12092 12093 expand %{ 12094 immI16 imm24 %{ (int) 24 %} 12095 immI16 imm16 %{ (int) 16 %} 12096 immI16 imm8 %{ (int) 8 %} 12097 immI16 imm4 %{ (int) 4 %} 12098 immI16 imm0 %{ (int) 0 %} 12099 iRegLdst tmpI1; 12100 iRegLdst tmpI2; 12101 iRegLdst tmpI3; 12102 12103 urShiftI_reg_imm(tmpI1, src, imm24); 12104 insrwi_a(dst, tmpI1, imm24, imm8); 12105 urShiftI_reg_imm(tmpI2, src, imm16); 12106 insrwi(dst, tmpI2, imm8, imm16); 12107 urShiftI_reg_imm(tmpI3, src, imm8); 12108 insrwi(dst, tmpI3, imm8, imm8); 12109 insrwi(dst, src, imm0, imm8); 12110 %} 12111 %} 12112 12113 //---------- Replicate Vector Instructions ------------------------------------ 12114 12115 // Insrdi does replicate if src == dst. 12116 instruct repl32(iRegLdst dst) %{ 12117 predicate(false); 12118 effect(USE_DEF dst); 12119 12120 format %{ "INSRDI $dst, #0, $dst, #32 \t// replicate" %} 12121 size(4); 12122 ins_encode %{ 12123 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 12124 __ insrdi($dst$$Register, $dst$$Register, 32, 0); 12125 %} 12126 ins_pipe(pipe_class_default); 12127 %} 12128 12129 // Insrdi does replicate if src == dst. 12130 instruct repl48(iRegLdst dst) %{ 12131 predicate(false); 12132 effect(USE_DEF dst); 12133 12134 format %{ "INSRDI $dst, #0, $dst, #48 \t// replicate" %} 12135 size(4); 12136 ins_encode %{ 12137 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 12138 __ insrdi($dst$$Register, $dst$$Register, 48, 0); 12139 %} 12140 ins_pipe(pipe_class_default); 12141 %} 12142 12143 // Insrdi does replicate if src == dst. 12144 instruct repl56(iRegLdst dst) %{ 12145 predicate(false); 12146 effect(USE_DEF dst); 12147 12148 format %{ "INSRDI $dst, #0, $dst, #56 \t// replicate" %} 12149 size(4); 12150 ins_encode %{ 12151 // TODO: PPC port $archOpcode(ppc64Opcode_rldimi); 12152 __ insrdi($dst$$Register, $dst$$Register, 56, 0); 12153 %} 12154 ins_pipe(pipe_class_default); 12155 %} 12156 12157 instruct repl8B_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 12158 match(Set dst (ReplicateB src)); 12159 predicate(n->as_Vector()->length() == 8); 12160 expand %{ 12161 moveReg(dst, src); 12162 repl56(dst); 12163 repl48(dst); 12164 repl32(dst); 12165 %} 12166 %} 12167 12168 instruct repl8B_immI0(iRegLdst dst, immI_0 zero) %{ 12169 match(Set dst (ReplicateB zero)); 12170 predicate(n->as_Vector()->length() == 8); 12171 format %{ "LI $dst, #0 \t// replicate8B" %} 12172 size(4); 12173 ins_encode %{ 12174 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 12175 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 12176 %} 12177 ins_pipe(pipe_class_default); 12178 %} 12179 12180 instruct repl8B_immIminus1(iRegLdst dst, immI_minus1 src) %{ 12181 match(Set dst (ReplicateB src)); 12182 predicate(n->as_Vector()->length() == 8); 12183 format %{ "LI $dst, #-1 \t// replicate8B" %} 12184 size(4); 12185 ins_encode %{ 12186 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 12187 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 12188 %} 12189 ins_pipe(pipe_class_default); 12190 %} 12191 12192 instruct repl4S_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 12193 match(Set dst (ReplicateS src)); 12194 predicate(n->as_Vector()->length() == 4); 12195 expand %{ 12196 moveReg(dst, src); 12197 repl48(dst); 12198 repl32(dst); 12199 %} 12200 %} 12201 12202 instruct repl4S_immI0(iRegLdst dst, immI_0 zero) %{ 12203 match(Set dst (ReplicateS zero)); 12204 predicate(n->as_Vector()->length() == 4); 12205 format %{ "LI $dst, #0 \t// replicate4C" %} 12206 size(4); 12207 ins_encode %{ 12208 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 12209 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 12210 %} 12211 ins_pipe(pipe_class_default); 12212 %} 12213 12214 instruct repl4S_immIminus1(iRegLdst dst, immI_minus1 src) %{ 12215 match(Set dst (ReplicateS src)); 12216 predicate(n->as_Vector()->length() == 4); 12217 format %{ "LI $dst, -1 \t// replicate4C" %} 12218 size(4); 12219 ins_encode %{ 12220 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 12221 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 12222 %} 12223 ins_pipe(pipe_class_default); 12224 %} 12225 12226 instruct repl2I_reg_Ex(iRegLdst dst, iRegIsrc src) %{ 12227 match(Set dst (ReplicateI src)); 12228 predicate(n->as_Vector()->length() == 2); 12229 ins_cost(2 * DEFAULT_COST); 12230 expand %{ 12231 moveReg(dst, src); 12232 repl32(dst); 12233 %} 12234 %} 12235 12236 instruct repl2I_immI0(iRegLdst dst, immI_0 zero) %{ 12237 match(Set dst (ReplicateI zero)); 12238 predicate(n->as_Vector()->length() == 2); 12239 format %{ "LI $dst, #0 \t// replicate4C" %} 12240 size(4); 12241 ins_encode %{ 12242 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 12243 __ li($dst$$Register, (int)((short)($zero$$constant & 0xFFFF))); 12244 %} 12245 ins_pipe(pipe_class_default); 12246 %} 12247 12248 instruct repl2I_immIminus1(iRegLdst dst, immI_minus1 src) %{ 12249 match(Set dst (ReplicateI src)); 12250 predicate(n->as_Vector()->length() == 2); 12251 format %{ "LI $dst, -1 \t// replicate4C" %} 12252 size(4); 12253 ins_encode %{ 12254 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 12255 __ li($dst$$Register, (int)((short)($src$$constant & 0xFFFF))); 12256 %} 12257 ins_pipe(pipe_class_default); 12258 %} 12259 12260 // Move float to int register via stack, replicate. 12261 instruct repl2F_reg_Ex(iRegLdst dst, regF src) %{ 12262 match(Set dst (ReplicateF src)); 12263 predicate(n->as_Vector()->length() == 2); 12264 ins_cost(2 * MEMORY_REF_COST + DEFAULT_COST); 12265 expand %{ 12266 stackSlotL tmpS; 12267 iRegIdst tmpI; 12268 moveF2I_reg_stack(tmpS, src); // Move float to stack. 12269 moveF2I_stack_reg(tmpI, tmpS); // Move stack to int reg. 12270 moveReg(dst, tmpI); // Move int to long reg. 12271 repl32(dst); // Replicate bitpattern. 12272 %} 12273 %} 12274 12275 // Replicate scalar constant to packed float values in Double register 12276 instruct repl2F_immF_Ex(iRegLdst dst, immF src) %{ 12277 match(Set dst (ReplicateF src)); 12278 predicate(n->as_Vector()->length() == 2); 12279 ins_cost(5 * DEFAULT_COST); 12280 12281 format %{ "LD $dst, offset, $constanttablebase\t// load replicated float $src $src from table, postalloc expanded" %} 12282 postalloc_expand( postalloc_expand_load_replF_constant(dst, src, constanttablebase) ); 12283 %} 12284 12285 // Replicate scalar zero constant to packed float values in Double register 12286 instruct repl2F_immF0(iRegLdst dst, immF_0 zero) %{ 12287 match(Set dst (ReplicateF zero)); 12288 predicate(n->as_Vector()->length() == 2); 12289 12290 format %{ "LI $dst, #0 \t// replicate2F" %} 12291 ins_encode %{ 12292 // TODO: PPC port $archOpcode(ppc64Opcode_addi); 12293 __ li($dst$$Register, 0x0); 12294 %} 12295 ins_pipe(pipe_class_default); 12296 %} 12297 12298 12299 //----------Overflow Math Instructions----------------------------------------- 12300 12301 // Note that we have to make sure that XER.SO is reset before using overflow instructions. 12302 // Simple Overflow operations can be matched by very few instructions (e.g. addExact: xor, and_, bc). 12303 // Seems like only Long intrinsincs have an advantage. (The only expensive one is OverflowMulL.) 12304 12305 instruct overflowAddL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 12306 match(Set cr0 (OverflowAddL op1 op2)); 12307 12308 format %{ "add_ $op1, $op2\t# overflow check long" %} 12309 ins_encode %{ 12310 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 12311 __ li(R0, 0); 12312 __ mtxer(R0); // clear XER.SO 12313 __ addo_(R0, $op1$$Register, $op2$$Register); 12314 %} 12315 ins_pipe(pipe_class_default); 12316 %} 12317 12318 instruct overflowSubL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 12319 match(Set cr0 (OverflowSubL op1 op2)); 12320 12321 format %{ "subfo_ R0, $op2, $op1\t# overflow check long" %} 12322 ins_encode %{ 12323 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 12324 __ li(R0, 0); 12325 __ mtxer(R0); // clear XER.SO 12326 __ subfo_(R0, $op2$$Register, $op1$$Register); 12327 %} 12328 ins_pipe(pipe_class_default); 12329 %} 12330 12331 instruct overflowNegL_reg(flagsRegCR0 cr0, immL_0 zero, iRegLsrc op2) %{ 12332 match(Set cr0 (OverflowSubL zero op2)); 12333 12334 format %{ "nego_ R0, $op2\t# overflow check long" %} 12335 ins_encode %{ 12336 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 12337 __ li(R0, 0); 12338 __ mtxer(R0); // clear XER.SO 12339 __ nego_(R0, $op2$$Register); 12340 %} 12341 ins_pipe(pipe_class_default); 12342 %} 12343 12344 instruct overflowMulL_reg_reg(flagsRegCR0 cr0, iRegLsrc op1, iRegLsrc op2) %{ 12345 match(Set cr0 (OverflowMulL op1 op2)); 12346 12347 format %{ "mulldo_ R0, $op1, $op2\t# overflow check long" %} 12348 ins_encode %{ 12349 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 12350 __ li(R0, 0); 12351 __ mtxer(R0); // clear XER.SO 12352 __ mulldo_(R0, $op1$$Register, $op2$$Register); 12353 %} 12354 ins_pipe(pipe_class_default); 12355 %} 12356 12357 12358 // ============================================================================ 12359 // Safepoint Instruction 12360 12361 instruct safePoint_poll(iRegPdst poll) %{ 12362 match(SafePoint poll); 12363 predicate(LoadPollAddressFromThread); 12364 12365 // It caused problems to add the effect that r0 is killed, but this 12366 // effect no longer needs to be mentioned, since r0 is not contained 12367 // in a reg_class. 12368 12369 format %{ "LD R0, #0, $poll \t// Safepoint poll for GC" %} 12370 size(4); 12371 ins_encode( enc_poll(0x0, poll) ); 12372 ins_pipe(pipe_class_default); 12373 %} 12374 12375 // Safepoint without per-thread support. Load address of page to poll 12376 // as constant. 12377 // Rscratch2RegP is R12. 12378 // LoadConPollAddr node is added in pd_post_matching_hook(). It must be 12379 // a seperate node so that the oop map is at the right location. 12380 instruct safePoint_poll_conPollAddr(rscratch2RegP poll) %{ 12381 match(SafePoint poll); 12382 predicate(!LoadPollAddressFromThread); 12383 12384 // It caused problems to add the effect that r0 is killed, but this 12385 // effect no longer needs to be mentioned, since r0 is not contained 12386 // in a reg_class. 12387 12388 format %{ "LD R0, #0, R12 \t// Safepoint poll for GC" %} 12389 ins_encode( enc_poll(0x0, poll) ); 12390 ins_pipe(pipe_class_default); 12391 %} 12392 12393 // ============================================================================ 12394 // Call Instructions 12395 12396 // Call Java Static Instruction 12397 12398 // Schedulable version of call static node. 12399 instruct CallStaticJavaDirect(method meth) %{ 12400 match(CallStaticJava); 12401 effect(USE meth); 12402 ins_cost(CALL_COST); 12403 12404 ins_num_consts(3 /* up to 3 patchable constants: inline cache, 2 call targets. */); 12405 12406 format %{ "CALL,static $meth \t// ==> " %} 12407 size(4); 12408 ins_encode( enc_java_static_call(meth) ); 12409 ins_pipe(pipe_class_call); 12410 %} 12411 12412 // Call Java Dynamic Instruction 12413 12414 // Used by postalloc expand of CallDynamicJavaDirectSchedEx (actual call). 12415 // Loading of IC was postalloc expanded. The nodes loading the IC are reachable 12416 // via fields ins_field_load_ic_hi_node and ins_field_load_ic_node. 12417 // The call destination must still be placed in the constant pool. 12418 instruct CallDynamicJavaDirectSched(method meth) %{ 12419 match(CallDynamicJava); // To get all the data fields we need ... 12420 effect(USE meth); 12421 predicate(false); // ... but never match. 12422 12423 ins_field_load_ic_hi_node(loadConL_hiNode*); 12424 ins_field_load_ic_node(loadConLNode*); 12425 ins_num_consts(1 /* 1 patchable constant: call destination */); 12426 12427 format %{ "BL \t// dynamic $meth ==> " %} 12428 size(4); 12429 ins_encode( enc_java_dynamic_call_sched(meth) ); 12430 ins_pipe(pipe_class_call); 12431 %} 12432 12433 // Schedulable (i.e. postalloc expanded) version of call dynamic java. 12434 // We use postalloc expanded calls if we use inline caches 12435 // and do not update method data. 12436 // 12437 // This instruction has two constants: inline cache (IC) and call destination. 12438 // Loading the inline cache will be postalloc expanded, thus leaving a call with 12439 // one constant. 12440 instruct CallDynamicJavaDirectSched_Ex(method meth) %{ 12441 match(CallDynamicJava); 12442 effect(USE meth); 12443 predicate(UseInlineCaches); 12444 ins_cost(CALL_COST); 12445 12446 ins_num_consts(2 /* 2 patchable constants: inline cache, call destination. */); 12447 12448 format %{ "CALL,dynamic $meth \t// postalloc expanded" %} 12449 postalloc_expand( postalloc_expand_java_dynamic_call_sched(meth, constanttablebase) ); 12450 %} 12451 12452 // Compound version of call dynamic java 12453 // We use postalloc expanded calls if we use inline caches 12454 // and do not update method data. 12455 instruct CallDynamicJavaDirect(method meth) %{ 12456 match(CallDynamicJava); 12457 effect(USE meth); 12458 predicate(!UseInlineCaches); 12459 ins_cost(CALL_COST); 12460 12461 // Enc_java_to_runtime_call needs up to 4 constants (method data oop). 12462 ins_num_consts(4); 12463 12464 format %{ "CALL,dynamic $meth \t// ==> " %} 12465 ins_encode( enc_java_dynamic_call(meth, constanttablebase) ); 12466 ins_pipe(pipe_class_call); 12467 %} 12468 12469 // Call Runtime Instruction 12470 12471 instruct CallRuntimeDirect(method meth) %{ 12472 match(CallRuntime); 12473 effect(USE meth); 12474 ins_cost(CALL_COST); 12475 12476 // Enc_java_to_runtime_call needs up to 3 constants: call target, 12477 // env for callee, C-toc. 12478 ins_num_consts(3); 12479 12480 format %{ "CALL,runtime" %} 12481 ins_encode( enc_java_to_runtime_call(meth) ); 12482 ins_pipe(pipe_class_call); 12483 %} 12484 12485 // Call Leaf 12486 12487 // Used by postalloc expand of CallLeafDirect_Ex (mtctr). 12488 instruct CallLeafDirect_mtctr(iRegLdst dst, iRegLsrc src) %{ 12489 effect(DEF dst, USE src); 12490 12491 ins_num_consts(1); 12492 12493 format %{ "MTCTR $src" %} 12494 size(4); 12495 ins_encode( enc_leaf_call_mtctr(src) ); 12496 ins_pipe(pipe_class_default); 12497 %} 12498 12499 // Used by postalloc expand of CallLeafDirect_Ex (actual call). 12500 instruct CallLeafDirect(method meth) %{ 12501 match(CallLeaf); // To get the data all the data fields we need ... 12502 effect(USE meth); 12503 predicate(false); // but never match. 12504 12505 format %{ "BCTRL \t// leaf call $meth ==> " %} 12506 size(4); 12507 ins_encode %{ 12508 // TODO: PPC port $archOpcode(ppc64Opcode_bctrl); 12509 __ bctrl(); 12510 %} 12511 ins_pipe(pipe_class_call); 12512 %} 12513 12514 // postalloc expand of CallLeafDirect. 12515 // Load adress to call from TOC, then bl to it. 12516 instruct CallLeafDirect_Ex(method meth) %{ 12517 match(CallLeaf); 12518 effect(USE meth); 12519 ins_cost(CALL_COST); 12520 12521 // Postalloc_expand_java_to_runtime_call needs up to 3 constants: call target, 12522 // env for callee, C-toc. 12523 ins_num_consts(3); 12524 12525 format %{ "CALL,runtime leaf $meth \t// postalloc expanded" %} 12526 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 12527 %} 12528 12529 // Call runtime without safepoint - same as CallLeaf. 12530 // postalloc expand of CallLeafNoFPDirect. 12531 // Load adress to call from TOC, then bl to it. 12532 instruct CallLeafNoFPDirect_Ex(method meth) %{ 12533 match(CallLeafNoFP); 12534 effect(USE meth); 12535 ins_cost(CALL_COST); 12536 12537 // Enc_java_to_runtime_call needs up to 3 constants: call target, 12538 // env for callee, C-toc. 12539 ins_num_consts(3); 12540 12541 format %{ "CALL,runtime leaf nofp $meth \t// postalloc expanded" %} 12542 postalloc_expand( postalloc_expand_java_to_runtime_call(meth, constanttablebase) ); 12543 %} 12544 12545 // Tail Call; Jump from runtime stub to Java code. 12546 // Also known as an 'interprocedural jump'. 12547 // Target of jump will eventually return to caller. 12548 // TailJump below removes the return address. 12549 instruct TailCalljmpInd(iRegPdstNoScratch jump_target, inline_cache_regP method_oop) %{ 12550 match(TailCall jump_target method_oop); 12551 ins_cost(CALL_COST); 12552 12553 format %{ "MTCTR $jump_target \t// $method_oop holds method oop\n\t" 12554 "BCTR \t// tail call" %} 12555 size(8); 12556 ins_encode %{ 12557 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 12558 __ mtctr($jump_target$$Register); 12559 __ bctr(); 12560 %} 12561 ins_pipe(pipe_class_call); 12562 %} 12563 12564 // Return Instruction 12565 instruct Ret() %{ 12566 match(Return); 12567 format %{ "BLR \t// branch to link register" %} 12568 size(4); 12569 ins_encode %{ 12570 // TODO: PPC port $archOpcode(ppc64Opcode_blr); 12571 // LR is restored in MachEpilogNode. Just do the RET here. 12572 __ blr(); 12573 %} 12574 ins_pipe(pipe_class_default); 12575 %} 12576 12577 // Tail Jump; remove the return address; jump to target. 12578 // TailCall above leaves the return address around. 12579 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2). 12580 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a 12581 // "restore" before this instruction (in Epilogue), we need to materialize it 12582 // in %i0. 12583 instruct tailjmpInd(iRegPdstNoScratch jump_target, rarg1RegP ex_oop) %{ 12584 match(TailJump jump_target ex_oop); 12585 ins_cost(CALL_COST); 12586 12587 format %{ "LD R4_ARG2 = LR\n\t" 12588 "MTCTR $jump_target\n\t" 12589 "BCTR \t// TailJump, exception oop: $ex_oop" %} 12590 size(12); 12591 ins_encode %{ 12592 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 12593 __ ld(R4_ARG2/* issuing pc */, _abi(lr), R1_SP); 12594 __ mtctr($jump_target$$Register); 12595 __ bctr(); 12596 %} 12597 ins_pipe(pipe_class_call); 12598 %} 12599 12600 // Create exception oop: created by stack-crawling runtime code. 12601 // Created exception is now available to this handler, and is setup 12602 // just prior to jumping to this handler. No code emitted. 12603 instruct CreateException(rarg1RegP ex_oop) %{ 12604 match(Set ex_oop (CreateEx)); 12605 ins_cost(0); 12606 12607 format %{ " -- \t// exception oop; no code emitted" %} 12608 size(0); 12609 ins_encode( /*empty*/ ); 12610 ins_pipe(pipe_class_default); 12611 %} 12612 12613 // Rethrow exception: The exception oop will come in the first 12614 // argument position. Then JUMP (not call) to the rethrow stub code. 12615 instruct RethrowException() %{ 12616 match(Rethrow); 12617 ins_cost(CALL_COST); 12618 12619 format %{ "Jmp rethrow_stub" %} 12620 ins_encode %{ 12621 // TODO: PPC port $archOpcode(ppc64Opcode_compound); 12622 cbuf.set_insts_mark(); 12623 __ b64_patchable((address)OptoRuntime::rethrow_stub(), relocInfo::runtime_call_type); 12624 %} 12625 ins_pipe(pipe_class_call); 12626 %} 12627 12628 // Die now. 12629 instruct ShouldNotReachHere() %{ 12630 match(Halt); 12631 ins_cost(CALL_COST); 12632 12633 format %{ "ShouldNotReachHere" %} 12634 size(4); 12635 ins_encode %{ 12636 // TODO: PPC port $archOpcode(ppc64Opcode_tdi); 12637 __ trap_should_not_reach_here(); 12638 %} 12639 ins_pipe(pipe_class_default); 12640 %} 12641 12642 // This name is KNOWN by the ADLC and cannot be changed. The ADLC 12643 // forces a 'TypeRawPtr::BOTTOM' output type for this guy. 12644 // Get a DEF on threadRegP, no costs, no encoding, use 12645 // 'ins_should_rematerialize(true)' to avoid spilling. 12646 instruct tlsLoadP(threadRegP dst) %{ 12647 match(Set dst (ThreadLocal)); 12648 ins_cost(0); 12649 12650 ins_should_rematerialize(true); 12651 12652 format %{ " -- \t// $dst=Thread::current(), empty" %} 12653 size(0); 12654 ins_encode( /*empty*/ ); 12655 ins_pipe(pipe_class_empty); 12656 %} 12657 12658 //---Some PPC specific nodes--------------------------------------------------- 12659 12660 // Stop a group. 12661 instruct endGroup() %{ 12662 ins_cost(0); 12663 12664 ins_is_nop(true); 12665 12666 format %{ "End Bundle (ori r1, r1, 0)" %} 12667 size(4); 12668 ins_encode %{ 12669 // TODO: PPC port $archOpcode(ppc64Opcode_endgroup); 12670 __ endgroup(); 12671 %} 12672 ins_pipe(pipe_class_default); 12673 %} 12674 12675 // Nop instructions 12676 12677 instruct fxNop() %{ 12678 ins_cost(0); 12679 12680 ins_is_nop(true); 12681 12682 format %{ "fxNop" %} 12683 size(4); 12684 ins_encode %{ 12685 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12686 __ nop(); 12687 %} 12688 ins_pipe(pipe_class_default); 12689 %} 12690 12691 instruct fpNop0() %{ 12692 ins_cost(0); 12693 12694 ins_is_nop(true); 12695 12696 format %{ "fpNop0" %} 12697 size(4); 12698 ins_encode %{ 12699 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12700 __ fpnop0(); 12701 %} 12702 ins_pipe(pipe_class_default); 12703 %} 12704 12705 instruct fpNop1() %{ 12706 ins_cost(0); 12707 12708 ins_is_nop(true); 12709 12710 format %{ "fpNop1" %} 12711 size(4); 12712 ins_encode %{ 12713 // TODO: PPC port $archOpcode(ppc64Opcode_fmr); 12714 __ fpnop1(); 12715 %} 12716 ins_pipe(pipe_class_default); 12717 %} 12718 12719 instruct brNop0() %{ 12720 ins_cost(0); 12721 size(4); 12722 format %{ "brNop0" %} 12723 ins_encode %{ 12724 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12725 __ brnop0(); 12726 %} 12727 ins_is_nop(true); 12728 ins_pipe(pipe_class_default); 12729 %} 12730 12731 instruct brNop1() %{ 12732 ins_cost(0); 12733 12734 ins_is_nop(true); 12735 12736 format %{ "brNop1" %} 12737 size(4); 12738 ins_encode %{ 12739 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12740 __ brnop1(); 12741 %} 12742 ins_pipe(pipe_class_default); 12743 %} 12744 12745 instruct brNop2() %{ 12746 ins_cost(0); 12747 12748 ins_is_nop(true); 12749 12750 format %{ "brNop2" %} 12751 size(4); 12752 ins_encode %{ 12753 // TODO: PPC port $archOpcode(ppc64Opcode_mcrf); 12754 __ brnop2(); 12755 %} 12756 ins_pipe(pipe_class_default); 12757 %} 12758 12759 //----------PEEPHOLE RULES----------------------------------------------------- 12760 // These must follow all instruction definitions as they use the names 12761 // defined in the instructions definitions. 12762 // 12763 // peepmatch ( root_instr_name [preceeding_instruction]* ); 12764 // 12765 // peepconstraint %{ 12766 // (instruction_number.operand_name relational_op instruction_number.operand_name 12767 // [, ...] ); 12768 // // instruction numbers are zero-based using left to right order in peepmatch 12769 // 12770 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) ); 12771 // // provide an instruction_number.operand_name for each operand that appears 12772 // // in the replacement instruction's match rule 12773 // 12774 // ---------VM FLAGS--------------------------------------------------------- 12775 // 12776 // All peephole optimizations can be turned off using -XX:-OptoPeephole 12777 // 12778 // Each peephole rule is given an identifying number starting with zero and 12779 // increasing by one in the order seen by the parser. An individual peephole 12780 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=# 12781 // on the command-line. 12782 // 12783 // ---------CURRENT LIMITATIONS---------------------------------------------- 12784 // 12785 // Only match adjacent instructions in same basic block 12786 // Only equality constraints 12787 // Only constraints between operands, not (0.dest_reg == EAX_enc) 12788 // Only one replacement instruction 12789 // 12790 // ---------EXAMPLE---------------------------------------------------------- 12791 // 12792 // // pertinent parts of existing instructions in architecture description 12793 // instruct movI(eRegI dst, eRegI src) %{ 12794 // match(Set dst (CopyI src)); 12795 // %} 12796 // 12797 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{ 12798 // match(Set dst (AddI dst src)); 12799 // effect(KILL cr); 12800 // %} 12801 // 12802 // // Change (inc mov) to lea 12803 // peephole %{ 12804 // // increment preceeded by register-register move 12805 // peepmatch ( incI_eReg movI ); 12806 // // require that the destination register of the increment 12807 // // match the destination register of the move 12808 // peepconstraint ( 0.dst == 1.dst ); 12809 // // construct a replacement instruction that sets 12810 // // the destination to ( move's source register + one ) 12811 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12812 // %} 12813 // 12814 // Implementation no longer uses movX instructions since 12815 // machine-independent system no longer uses CopyX nodes. 12816 // 12817 // peephole %{ 12818 // peepmatch ( incI_eReg movI ); 12819 // peepconstraint ( 0.dst == 1.dst ); 12820 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12821 // %} 12822 // 12823 // peephole %{ 12824 // peepmatch ( decI_eReg movI ); 12825 // peepconstraint ( 0.dst == 1.dst ); 12826 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12827 // %} 12828 // 12829 // peephole %{ 12830 // peepmatch ( addI_eReg_imm movI ); 12831 // peepconstraint ( 0.dst == 1.dst ); 12832 // peepreplace ( leaI_eReg_immI( 0.dst 1.src 0.src ) ); 12833 // %} 12834 // 12835 // peephole %{ 12836 // peepmatch ( addP_eReg_imm movP ); 12837 // peepconstraint ( 0.dst == 1.dst ); 12838 // peepreplace ( leaP_eReg_immI( 0.dst 1.src 0.src ) ); 12839 // %} 12840 12841 // // Change load of spilled value to only a spill 12842 // instruct storeI(memory mem, eRegI src) %{ 12843 // match(Set mem (StoreI mem src)); 12844 // %} 12845 // 12846 // instruct loadI(eRegI dst, memory mem) %{ 12847 // match(Set dst (LoadI mem)); 12848 // %} 12849 // 12850 peephole %{ 12851 peepmatch ( loadI storeI ); 12852 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12853 peepreplace ( storeI( 1.mem 1.mem 1.src ) ); 12854 %} 12855 12856 peephole %{ 12857 peepmatch ( loadL storeL ); 12858 peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem ); 12859 peepreplace ( storeL( 1.mem 1.mem 1.src ) ); 12860 %} 12861 12862 peephole %{ 12863 peepmatch ( loadP storeP ); 12864 peepconstraint ( 1.src == 0.dst, 1.dst == 0.mem ); 12865 peepreplace ( storeP( 1.dst 1.dst 1.src ) ); 12866 %} 12867 12868 //----------SMARTSPILL RULES--------------------------------------------------- 12869 // These must follow all instruction definitions as they use the names 12870 // defined in the instructions definitions.