1963 //
1964 // NOTE: If the platform does not provide any short branch variants, then
1965 // this method should return false for offset 0.
1966 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1967 // The passed offset is relative to address of the branch.
1968 // Don't need to adjust the offset.
1969 return UseCBCond && Assembler::is_simm12(offset);
1970 }
1971
1972 const bool Matcher::isSimpleConstant64(jlong value) {
1973 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1974 // Depends on optimizations in MacroAssembler::setx.
1975 int hi = (int)(value >> 32);
1976 int lo = (int)(value & ~0);
1977 return (hi == 0) || (hi == -1) || (lo == 0);
1978 }
1979
1980 // No scaling for the parameter the ClearArray node.
1981 const bool Matcher::init_array_count_is_in_bytes = true;
1982
1983 // Threshold size for cleararray.
1984 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1985
1986 // No additional cost for CMOVL.
1987 const int Matcher::long_cmove_cost() { return 0; }
1988
1989 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1990 const int Matcher::float_cmove_cost() {
1991 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1992 }
1993
1994 // Does the CPU require late expand (see block.cpp for description of late expand)?
1995 const bool Matcher::require_postalloc_expand = false;
1996
1997 // Should the Matcher clone shifts on addressing modes, expecting them to
1998 // be subsumed into complex addressing expressions or compute them into
1999 // registers? True for Intel but false for most RISCs
2000 const bool Matcher::clone_shift_expressions = false;
2001
2002 // Do we need to mask the count passed to shift instructions or does
2003 // the cpu only look at the lower 5/6 bits anyway?
2004 const bool Matcher::need_masked_shift_count = false;
2005
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1963 //
1964 // NOTE: If the platform does not provide any short branch variants, then
1965 // this method should return false for offset 0.
1966 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1967 // The passed offset is relative to address of the branch.
1968 // Don't need to adjust the offset.
1969 return UseCBCond && Assembler::is_simm12(offset);
1970 }
1971
1972 const bool Matcher::isSimpleConstant64(jlong value) {
1973 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1974 // Depends on optimizations in MacroAssembler::setx.
1975 int hi = (int)(value >> 32);
1976 int lo = (int)(value & ~0);
1977 return (hi == 0) || (hi == -1) || (lo == 0);
1978 }
1979
1980 // No scaling for the parameter the ClearArray node.
1981 const bool Matcher::init_array_count_is_in_bytes = true;
1982
1983 // No additional cost for CMOVL.
1984 const int Matcher::long_cmove_cost() { return 0; }
1985
1986 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1987 const int Matcher::float_cmove_cost() {
1988 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1989 }
1990
1991 // Does the CPU require late expand (see block.cpp for description of late expand)?
1992 const bool Matcher::require_postalloc_expand = false;
1993
1994 // Should the Matcher clone shifts on addressing modes, expecting them to
1995 // be subsumed into complex addressing expressions or compute them into
1996 // registers? True for Intel but false for most RISCs
1997 const bool Matcher::clone_shift_expressions = false;
1998
1999 // Do we need to mask the count passed to shift instructions or does
2000 // the cpu only look at the lower 5/6 bits anyway?
2001 const bool Matcher::need_masked_shift_count = false;
2002
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