1 //
2 // Copyright (c) 2003, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
15 // You should have received a copy of the GNU General Public License version
16 // 2 along with this work; if not, write to the Free Software Foundation,
17 // Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 //
19 // Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // AMD64 Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31
32 register %{
33 //----------Architecture Description Register Definitions----------------------
34 // General Registers
35 // "reg_def" name ( register save type, C convention save type,
36 // ideal register type, encoding );
37 // Register Save Types:
38 //
39 // NS = No-Save: The register allocator assumes that these registers
40 // can be used without saving upon entry to the method, &
41 // that they do not need to be saved at call sites.
42 //
43 // SOC = Save-On-Call: The register allocator assumes that these registers
44 // can be used without saving upon entry to the method,
45 // but that they must be saved at call sites.
46 //
47 // SOE = Save-On-Entry: The register allocator assumes that these registers
48 // must be saved before using them upon entry to the
49 // method, but they do not need to be saved at call
50 // sites.
51 //
52 // AS = Always-Save: The register allocator assumes that these registers
53 // must be saved before using them upon entry to the
54 // method, & that they must be saved at call sites.
55 //
56 // Ideal Register Type is used to determine how to save & restore a
57 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
58 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
59 //
60 // The encoding number is the actual bit-pattern placed into the opcodes.
61
62 // General Registers
63 // R8-R15 must be encoded with REX. (RSP, RBP, RSI, RDI need REX when
64 // used as byte registers)
65
66 // Previously set RBX, RSI, and RDI as save-on-entry for java code
67 // Turn off SOE in java-code due to frequent use of uncommon-traps.
68 // Now that allocator is better, turn on RSI and RDI as SOE registers.
69
70 reg_def RAX (SOC, SOC, Op_RegI, 0, rax->as_VMReg());
71 reg_def RAX_H(SOC, SOC, Op_RegI, 0, rax->as_VMReg()->next());
72
73 reg_def RCX (SOC, SOC, Op_RegI, 1, rcx->as_VMReg());
74 reg_def RCX_H(SOC, SOC, Op_RegI, 1, rcx->as_VMReg()->next());
75
76 reg_def RDX (SOC, SOC, Op_RegI, 2, rdx->as_VMReg());
77 reg_def RDX_H(SOC, SOC, Op_RegI, 2, rdx->as_VMReg()->next());
78
79 reg_def RBX (SOC, SOE, Op_RegI, 3, rbx->as_VMReg());
80 reg_def RBX_H(SOC, SOE, Op_RegI, 3, rbx->as_VMReg()->next());
81
82 reg_def RSP (NS, NS, Op_RegI, 4, rsp->as_VMReg());
83 reg_def RSP_H(NS, NS, Op_RegI, 4, rsp->as_VMReg()->next());
84
85 // now that adapter frames are gone RBP is always saved and restored by the prolog/epilog code
86 reg_def RBP (NS, SOE, Op_RegI, 5, rbp->as_VMReg());
87 reg_def RBP_H(NS, SOE, Op_RegI, 5, rbp->as_VMReg()->next());
88
89 #ifdef _WIN64
90
91 reg_def RSI (SOC, SOE, Op_RegI, 6, rsi->as_VMReg());
92 reg_def RSI_H(SOC, SOE, Op_RegI, 6, rsi->as_VMReg()->next());
93
94 reg_def RDI (SOC, SOE, Op_RegI, 7, rdi->as_VMReg());
95 reg_def RDI_H(SOC, SOE, Op_RegI, 7, rdi->as_VMReg()->next());
96
97 #else
98
99 reg_def RSI (SOC, SOC, Op_RegI, 6, rsi->as_VMReg());
100 reg_def RSI_H(SOC, SOC, Op_RegI, 6, rsi->as_VMReg()->next());
101
102 reg_def RDI (SOC, SOC, Op_RegI, 7, rdi->as_VMReg());
103 reg_def RDI_H(SOC, SOC, Op_RegI, 7, rdi->as_VMReg()->next());
104
105 #endif
106
107 reg_def R8 (SOC, SOC, Op_RegI, 8, r8->as_VMReg());
108 reg_def R8_H (SOC, SOC, Op_RegI, 8, r8->as_VMReg()->next());
109
110 reg_def R9 (SOC, SOC, Op_RegI, 9, r9->as_VMReg());
111 reg_def R9_H (SOC, SOC, Op_RegI, 9, r9->as_VMReg()->next());
112
113 reg_def R10 (SOC, SOC, Op_RegI, 10, r10->as_VMReg());
114 reg_def R10_H(SOC, SOC, Op_RegI, 10, r10->as_VMReg()->next());
115
116 reg_def R11 (SOC, SOC, Op_RegI, 11, r11->as_VMReg());
117 reg_def R11_H(SOC, SOC, Op_RegI, 11, r11->as_VMReg()->next());
118
119 reg_def R12 (SOC, SOE, Op_RegI, 12, r12->as_VMReg());
120 reg_def R12_H(SOC, SOE, Op_RegI, 12, r12->as_VMReg()->next());
121
122 reg_def R13 (SOC, SOE, Op_RegI, 13, r13->as_VMReg());
123 reg_def R13_H(SOC, SOE, Op_RegI, 13, r13->as_VMReg()->next());
124
125 reg_def R14 (SOC, SOE, Op_RegI, 14, r14->as_VMReg());
126 reg_def R14_H(SOC, SOE, Op_RegI, 14, r14->as_VMReg()->next());
127
128 reg_def R15 (SOC, SOE, Op_RegI, 15, r15->as_VMReg());
129 reg_def R15_H(SOC, SOE, Op_RegI, 15, r15->as_VMReg()->next());
130
131
132 // Floating Point Registers
133
134 // Specify priority of register selection within phases of register
135 // allocation. Highest priority is first. A useful heuristic is to
136 // give registers a low priority when they are required by machine
137 // instructions, like EAX and EDX on I486, and choose no-save registers
138 // before save-on-call, & save-on-call before save-on-entry. Registers
139 // which participate in fixed calling sequences should come last.
140 // Registers which are used as pairs must fall on an even boundary.
141
142 alloc_class chunk0(R10, R10_H,
143 R11, R11_H,
144 R8, R8_H,
145 R9, R9_H,
146 R12, R12_H,
147 RCX, RCX_H,
148 RBX, RBX_H,
149 RDI, RDI_H,
150 RDX, RDX_H,
151 RSI, RSI_H,
152 RAX, RAX_H,
153 RBP, RBP_H,
154 R13, R13_H,
155 R14, R14_H,
156 R15, R15_H,
157 RSP, RSP_H);
158
159
160 //----------Architecture Description Register Classes--------------------------
161 // Several register classes are automatically defined based upon information in
162 // this architecture description.
163 // 1) reg_class inline_cache_reg ( /* as def'd in frame section */ )
164 // 2) reg_class compiler_method_oop_reg ( /* as def'd in frame section */ )
165 // 2) reg_class interpreter_method_oop_reg ( /* as def'd in frame section */ )
166 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
167 //
168
169 // Empty register class.
170 reg_class no_reg();
171
172 // Class for all pointer registers (including RSP and RBP)
173 reg_class any_reg_with_rbp(RAX, RAX_H,
174 RDX, RDX_H,
175 RBP, RBP_H,
176 RDI, RDI_H,
177 RSI, RSI_H,
178 RCX, RCX_H,
179 RBX, RBX_H,
180 RSP, RSP_H,
181 R8, R8_H,
182 R9, R9_H,
183 R10, R10_H,
184 R11, R11_H,
185 R12, R12_H,
186 R13, R13_H,
187 R14, R14_H,
188 R15, R15_H);
189
190 // Class for all pointer registers (including RSP, but excluding RBP)
191 reg_class any_reg_no_rbp(RAX, RAX_H,
192 RDX, RDX_H,
193 RDI, RDI_H,
194 RSI, RSI_H,
195 RCX, RCX_H,
196 RBX, RBX_H,
197 RSP, RSP_H,
198 R8, R8_H,
199 R9, R9_H,
200 R10, R10_H,
201 R11, R11_H,
202 R12, R12_H,
203 R13, R13_H,
204 R14, R14_H,
205 R15, R15_H);
206
207 // Dynamic register class that selects at runtime between register classes
208 // any_reg_no_rbp and any_reg_with_rbp (depending on the value of the flag PreserveFramePointer).
209 // Equivalent to: return PreserveFramePointer ? any_reg_no_rbp : any_reg_with_rbp;
210 reg_class_dynamic any_reg(any_reg_no_rbp, any_reg_with_rbp, %{ PreserveFramePointer %});
211
212 // Class for all pointer registers (excluding RSP)
213 reg_class ptr_reg_with_rbp(RAX, RAX_H,
214 RDX, RDX_H,
215 RBP, RBP_H,
216 RDI, RDI_H,
217 RSI, RSI_H,
218 RCX, RCX_H,
219 RBX, RBX_H,
220 R8, R8_H,
221 R9, R9_H,
222 R10, R10_H,
223 R11, R11_H,
224 R13, R13_H,
225 R14, R14_H);
226
227 // Class for all pointer registers (excluding RSP and RBP)
228 reg_class ptr_reg_no_rbp(RAX, RAX_H,
229 RDX, RDX_H,
230 RDI, RDI_H,
231 RSI, RSI_H,
232 RCX, RCX_H,
233 RBX, RBX_H,
234 R8, R8_H,
235 R9, R9_H,
236 R10, R10_H,
237 R11, R11_H,
238 R13, R13_H,
239 R14, R14_H);
240
241 // Dynamic register class that selects between ptr_reg_no_rbp and ptr_reg_with_rbp.
242 reg_class_dynamic ptr_reg(ptr_reg_no_rbp, ptr_reg_with_rbp, %{ PreserveFramePointer %});
243
244 // Class for all pointer registers (excluding RAX and RSP)
245 reg_class ptr_no_rax_reg_with_rbp(RDX, RDX_H,
246 RBP, RBP_H,
247 RDI, RDI_H,
248 RSI, RSI_H,
249 RCX, RCX_H,
250 RBX, RBX_H,
251 R8, R8_H,
252 R9, R9_H,
253 R10, R10_H,
254 R11, R11_H,
255 R13, R13_H,
256 R14, R14_H);
257
258 // Class for all pointer registers (excluding RAX, RSP, and RBP)
259 reg_class ptr_no_rax_reg_no_rbp(RDX, RDX_H,
260 RDI, RDI_H,
261 RSI, RSI_H,
262 RCX, RCX_H,
263 RBX, RBX_H,
264 R8, R8_H,
265 R9, R9_H,
266 R10, R10_H,
267 R11, R11_H,
268 R13, R13_H,
269 R14, R14_H);
270
271 // Dynamic register class that selects between ptr_no_rax_reg_no_rbp and ptr_no_rax_reg_with_rbp.
272 reg_class_dynamic ptr_no_rax_reg(ptr_no_rax_reg_no_rbp, ptr_no_rax_reg_with_rbp, %{ PreserveFramePointer %});
273
274 // Class for all pointer registers (excluding RAX, RBX, and RSP)
275 reg_class ptr_no_rax_rbx_reg_with_rbp(RDX, RDX_H,
276 RBP, RBP_H,
277 RDI, RDI_H,
278 RSI, RSI_H,
279 RCX, RCX_H,
280 R8, R8_H,
281 R9, R9_H,
282 R10, R10_H,
283 R11, R11_H,
284 R13, R13_H,
285 R14, R14_H);
286
287 // Class for all pointer registers (excluding RAX, RBX, RSP, and RBP)
288 reg_class ptr_no_rax_rbx_reg_no_rbp(RDX, RDX_H,
289 RDI, RDI_H,
290 RSI, RSI_H,
291 RCX, RCX_H,
292 R8, R8_H,
293 R9, R9_H,
294 R10, R10_H,
295 R11, R11_H,
296 R13, R13_H,
297 R14, R14_H);
298
299 // Dynamic register class that selects between ptr_no_rax_rbx_reg_no_rbp and ptr_no_rax_rbx_reg_with_rbp.
300 reg_class_dynamic ptr_no_rax_rbx_reg(ptr_no_rax_rbx_reg_no_rbp, ptr_no_rax_rbx_reg_with_rbp, %{ PreserveFramePointer %});
301
302 // Singleton class for RAX pointer register
303 reg_class ptr_rax_reg(RAX, RAX_H);
304
305 // Singleton class for RBX pointer register
306 reg_class ptr_rbx_reg(RBX, RBX_H);
307
308 // Singleton class for RSI pointer register
309 reg_class ptr_rsi_reg(RSI, RSI_H);
310
311 // Singleton class for RDI pointer register
312 reg_class ptr_rdi_reg(RDI, RDI_H);
313
314 // Singleton class for stack pointer
315 reg_class ptr_rsp_reg(RSP, RSP_H);
316
317 // Singleton class for TLS pointer
318 reg_class ptr_r15_reg(R15, R15_H);
319
320 // Class for all long registers (excluding RSP)
321 reg_class long_reg_with_rbp(RAX, RAX_H,
322 RDX, RDX_H,
323 RBP, RBP_H,
324 RDI, RDI_H,
325 RSI, RSI_H,
326 RCX, RCX_H,
327 RBX, RBX_H,
328 R8, R8_H,
329 R9, R9_H,
330 R10, R10_H,
331 R11, R11_H,
332 R13, R13_H,
333 R14, R14_H);
334
335 // Class for all long registers (excluding RSP and RBP)
336 reg_class long_reg_no_rbp(RAX, RAX_H,
337 RDX, RDX_H,
338 RDI, RDI_H,
339 RSI, RSI_H,
340 RCX, RCX_H,
341 RBX, RBX_H,
342 R8, R8_H,
343 R9, R9_H,
344 R10, R10_H,
345 R11, R11_H,
346 R13, R13_H,
347 R14, R14_H);
348
349 // Dynamic register class that selects between long_reg_no_rbp and long_reg_with_rbp.
350 reg_class_dynamic long_reg(long_reg_no_rbp, long_reg_with_rbp, %{ PreserveFramePointer %});
351
352 // Class for all long registers (excluding RAX, RDX and RSP)
353 reg_class long_no_rax_rdx_reg_with_rbp(RBP, RBP_H,
354 RDI, RDI_H,
355 RSI, RSI_H,
356 RCX, RCX_H,
357 RBX, RBX_H,
358 R8, R8_H,
359 R9, R9_H,
360 R10, R10_H,
361 R11, R11_H,
362 R13, R13_H,
363 R14, R14_H);
364
365 // Class for all long registers (excluding RAX, RDX, RSP, and RBP)
366 reg_class long_no_rax_rdx_reg_no_rbp(RDI, RDI_H,
367 RSI, RSI_H,
368 RCX, RCX_H,
369 RBX, RBX_H,
370 R8, R8_H,
371 R9, R9_H,
372 R10, R10_H,
373 R11, R11_H,
374 R13, R13_H,
375 R14, R14_H);
376
377 // Dynamic register class that selects between long_no_rax_rdx_reg_no_rbp and long_no_rax_rdx_reg_with_rbp.
378 reg_class_dynamic long_no_rax_rdx_reg(long_no_rax_rdx_reg_no_rbp, long_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
379
380 // Class for all long registers (excluding RCX and RSP)
381 reg_class long_no_rcx_reg_with_rbp(RBP, RBP_H,
382 RDI, RDI_H,
383 RSI, RSI_H,
384 RAX, RAX_H,
385 RDX, RDX_H,
386 RBX, RBX_H,
387 R8, R8_H,
388 R9, R9_H,
389 R10, R10_H,
390 R11, R11_H,
391 R13, R13_H,
392 R14, R14_H);
393
394 // Class for all long registers (excluding RCX, RSP, and RBP)
395 reg_class long_no_rcx_reg_no_rbp(RDI, RDI_H,
396 RSI, RSI_H,
397 RAX, RAX_H,
398 RDX, RDX_H,
399 RBX, RBX_H,
400 R8, R8_H,
401 R9, R9_H,
402 R10, R10_H,
403 R11, R11_H,
404 R13, R13_H,
405 R14, R14_H);
406
407 // Dynamic register class that selects between long_no_rcx_reg_no_rbp and long_no_rcx_reg_with_rbp.
408 reg_class_dynamic long_no_rcx_reg(long_no_rcx_reg_no_rbp, long_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
409
410 // Singleton class for RAX long register
411 reg_class long_rax_reg(RAX, RAX_H);
412
413 // Singleton class for RCX long register
414 reg_class long_rcx_reg(RCX, RCX_H);
415
416 // Singleton class for RDX long register
417 reg_class long_rdx_reg(RDX, RDX_H);
418
419 // Class for all int registers (excluding RSP)
420 reg_class int_reg_with_rbp(RAX,
421 RDX,
422 RBP,
423 RDI,
424 RSI,
425 RCX,
426 RBX,
427 R8,
428 R9,
429 R10,
430 R11,
431 R13,
432 R14);
433
434 // Class for all int registers (excluding RSP and RBP)
435 reg_class int_reg_no_rbp(RAX,
436 RDX,
437 RDI,
438 RSI,
439 RCX,
440 RBX,
441 R8,
442 R9,
443 R10,
444 R11,
445 R13,
446 R14);
447
448 // Dynamic register class that selects between int_reg_no_rbp and int_reg_with_rbp.
449 reg_class_dynamic int_reg(int_reg_no_rbp, int_reg_with_rbp, %{ PreserveFramePointer %});
450
451 // Class for all int registers (excluding RCX and RSP)
452 reg_class int_no_rcx_reg_with_rbp(RAX,
453 RDX,
454 RBP,
455 RDI,
456 RSI,
457 RBX,
458 R8,
459 R9,
460 R10,
461 R11,
462 R13,
463 R14);
464
465 // Class for all int registers (excluding RCX, RSP, and RBP)
466 reg_class int_no_rcx_reg_no_rbp(RAX,
467 RDX,
468 RDI,
469 RSI,
470 RBX,
471 R8,
472 R9,
473 R10,
474 R11,
475 R13,
476 R14);
477
478 // Dynamic register class that selects between int_no_rcx_reg_no_rbp and int_no_rcx_reg_with_rbp.
479 reg_class_dynamic int_no_rcx_reg(int_no_rcx_reg_no_rbp, int_no_rcx_reg_with_rbp, %{ PreserveFramePointer %});
480
481 // Class for all int registers (excluding RAX, RDX, and RSP)
482 reg_class int_no_rax_rdx_reg_with_rbp(RBP,
483 RDI,
484 RSI,
485 RCX,
486 RBX,
487 R8,
488 R9,
489 R10,
490 R11,
491 R13,
492 R14);
493
494 // Class for all int registers (excluding RAX, RDX, RSP, and RBP)
495 reg_class int_no_rax_rdx_reg_no_rbp(RDI,
496 RSI,
497 RCX,
498 RBX,
499 R8,
500 R9,
501 R10,
502 R11,
503 R13,
504 R14);
505
506 // Dynamic register class that selects between int_no_rax_rdx_reg_no_rbp and int_no_rax_rdx_reg_with_rbp.
507 reg_class_dynamic int_no_rax_rdx_reg(int_no_rax_rdx_reg_no_rbp, int_no_rax_rdx_reg_with_rbp, %{ PreserveFramePointer %});
508
509 // Singleton class for RAX int register
510 reg_class int_rax_reg(RAX);
511
512 // Singleton class for RBX int register
513 reg_class int_rbx_reg(RBX);
514
515 // Singleton class for RCX int register
516 reg_class int_rcx_reg(RCX);
517
518 // Singleton class for RCX int register
519 reg_class int_rdx_reg(RDX);
520
521 // Singleton class for RCX int register
522 reg_class int_rdi_reg(RDI);
523
524 // Singleton class for instruction pointer
525 // reg_class ip_reg(RIP);
526
527 %}
528
529 //----------SOURCE BLOCK-------------------------------------------------------
530 // This is a block of C++ code which provides values, functions, and
531 // definitions necessary in the rest of the architecture description
532 source %{
533 #define RELOC_IMM64 Assembler::imm_operand
534 #define RELOC_DISP32 Assembler::disp32_operand
535
536 #define __ _masm.
537
538 static int clear_avx_size() {
539 return (Compile::current()->max_vector_size() > 16) ? 3 : 0; // vzeroupper
540 }
541
542 // !!!!! Special hack to get all types of calls to specify the byte offset
543 // from the start of the call to the point where the return address
544 // will point.
545 int MachCallStaticJavaNode::ret_addr_offset()
546 {
547 int offset = 5; // 5 bytes from start of call to where return address points
548 offset += clear_avx_size();
549 return offset;
550 }
551
552 int MachCallDynamicJavaNode::ret_addr_offset()
553 {
554 int offset = 15; // 15 bytes from start of call to where return address points
555 offset += clear_avx_size();
556 return offset;
557 }
558
559 int MachCallRuntimeNode::ret_addr_offset() {
560 int offset = 13; // movq r10,#addr; callq (r10)
561 offset += clear_avx_size();
562 return offset;
563 }
564
565 // Indicate if the safepoint node needs the polling page as an input,
566 // it does if the polling page is more than disp32 away.
567 bool SafePointNode::needs_polling_address_input()
568 {
569 return Assembler::is_polling_page_far();
570 }
571
572 //
573 // Compute padding required for nodes which need alignment
574 //
575
576 // The address of the call instruction needs to be 4-byte aligned to
577 // ensure that it does not span a cache line so that it can be patched.
578 int CallStaticJavaDirectNode::compute_padding(int current_offset) const
579 {
580 current_offset += clear_avx_size(); // skip vzeroupper
581 current_offset += 1; // skip call opcode byte
582 return round_to(current_offset, alignment_required()) - current_offset;
583 }
584
585 // The address of the call instruction needs to be 4-byte aligned to
586 // ensure that it does not span a cache line so that it can be patched.
587 int CallDynamicJavaDirectNode::compute_padding(int current_offset) const
588 {
589 current_offset += clear_avx_size(); // skip vzeroupper
590 current_offset += 11; // skip movq instruction + call opcode byte
591 return round_to(current_offset, alignment_required()) - current_offset;
592 }
593
594 // EMIT_RM()
595 void emit_rm(CodeBuffer &cbuf, int f1, int f2, int f3) {
596 unsigned char c = (unsigned char) ((f1 << 6) | (f2 << 3) | f3);
597 cbuf.insts()->emit_int8(c);
598 }
599
600 // EMIT_CC()
601 void emit_cc(CodeBuffer &cbuf, int f1, int f2) {
602 unsigned char c = (unsigned char) (f1 | f2);
603 cbuf.insts()->emit_int8(c);
604 }
605
606 // EMIT_OPCODE()
607 void emit_opcode(CodeBuffer &cbuf, int code) {
608 cbuf.insts()->emit_int8((unsigned char) code);
609 }
610
611 // EMIT_OPCODE() w/ relocation information
612 void emit_opcode(CodeBuffer &cbuf,
613 int code, relocInfo::relocType reloc, int offset, int format)
614 {
615 cbuf.relocate(cbuf.insts_mark() + offset, reloc, format);
616 emit_opcode(cbuf, code);
617 }
618
619 // EMIT_D8()
620 void emit_d8(CodeBuffer &cbuf, int d8) {
621 cbuf.insts()->emit_int8((unsigned char) d8);
622 }
623
624 // EMIT_D16()
625 void emit_d16(CodeBuffer &cbuf, int d16) {
626 cbuf.insts()->emit_int16(d16);
627 }
628
629 // EMIT_D32()
630 void emit_d32(CodeBuffer &cbuf, int d32) {
631 cbuf.insts()->emit_int32(d32);
632 }
633
634 // EMIT_D64()
635 void emit_d64(CodeBuffer &cbuf, int64_t d64) {
636 cbuf.insts()->emit_int64(d64);
637 }
638
639 // emit 32 bit value and construct relocation entry from relocInfo::relocType
640 void emit_d32_reloc(CodeBuffer& cbuf,
641 int d32,
642 relocInfo::relocType reloc,
643 int format)
644 {
645 assert(reloc != relocInfo::external_word_type, "use 2-arg emit_d32_reloc");
646 cbuf.relocate(cbuf.insts_mark(), reloc, format);
647 cbuf.insts()->emit_int32(d32);
648 }
649
650 // emit 32 bit value and construct relocation entry from RelocationHolder
651 void emit_d32_reloc(CodeBuffer& cbuf, int d32, RelocationHolder const& rspec, int format) {
652 #ifdef ASSERT
653 if (rspec.reloc()->type() == relocInfo::oop_type &&
654 d32 != 0 && d32 != (intptr_t) Universe::non_oop_word()) {
655 assert(Universe::heap()->is_in_reserved((address)(intptr_t)d32), "should be real oop");
656 assert(cast_to_oop((intptr_t)d32)->is_oop() && (ScavengeRootsInCode || !cast_to_oop((intptr_t)d32)->is_scavengable()), "cannot embed scavengable oops in code");
657 }
658 #endif
659 cbuf.relocate(cbuf.insts_mark(), rspec, format);
660 cbuf.insts()->emit_int32(d32);
661 }
662
663 void emit_d32_reloc(CodeBuffer& cbuf, address addr) {
664 address next_ip = cbuf.insts_end() + 4;
665 emit_d32_reloc(cbuf, (int) (addr - next_ip),
666 external_word_Relocation::spec(addr),
667 RELOC_DISP32);
668 }
669
670
671 // emit 64 bit value and construct relocation entry from relocInfo::relocType
672 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, relocInfo::relocType reloc, int format) {
673 cbuf.relocate(cbuf.insts_mark(), reloc, format);
674 cbuf.insts()->emit_int64(d64);
675 }
676
677 // emit 64 bit value and construct relocation entry from RelocationHolder
678 void emit_d64_reloc(CodeBuffer& cbuf, int64_t d64, RelocationHolder const& rspec, int format) {
679 #ifdef ASSERT
680 if (rspec.reloc()->type() == relocInfo::oop_type &&
681 d64 != 0 && d64 != (int64_t) Universe::non_oop_word()) {
682 assert(Universe::heap()->is_in_reserved((address)d64), "should be real oop");
683 assert(cast_to_oop(d64)->is_oop() && (ScavengeRootsInCode || !cast_to_oop(d64)->is_scavengable()),
684 "cannot embed scavengable oops in code");
685 }
686 #endif
687 cbuf.relocate(cbuf.insts_mark(), rspec, format);
688 cbuf.insts()->emit_int64(d64);
689 }
690
691 // Access stack slot for load or store
692 void store_to_stackslot(CodeBuffer &cbuf, int opcode, int rm_field, int disp)
693 {
694 emit_opcode(cbuf, opcode); // (e.g., FILD [RSP+src])
695 if (-0x80 <= disp && disp < 0x80) {
696 emit_rm(cbuf, 0x01, rm_field, RSP_enc); // R/M byte
697 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
698 emit_d8(cbuf, disp); // Displacement // R/M byte
699 } else {
700 emit_rm(cbuf, 0x02, rm_field, RSP_enc); // R/M byte
701 emit_rm(cbuf, 0x00, RSP_enc, RSP_enc); // SIB byte
702 emit_d32(cbuf, disp); // Displacement // R/M byte
703 }
704 }
705
706 // rRegI ereg, memory mem) %{ // emit_reg_mem
707 void encode_RegMem(CodeBuffer &cbuf,
708 int reg,
709 int base, int index, int scale, int disp, relocInfo::relocType disp_reloc)
710 {
711 assert(disp_reloc == relocInfo::none, "cannot have disp");
712 int regenc = reg & 7;
713 int baseenc = base & 7;
714 int indexenc = index & 7;
715
716 // There is no index & no scale, use form without SIB byte
717 if (index == 0x4 && scale == 0 && base != RSP_enc && base != R12_enc) {
718 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
719 if (disp == 0 && base != RBP_enc && base != R13_enc) {
720 emit_rm(cbuf, 0x0, regenc, baseenc); // *
721 } else if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
722 // If 8-bit displacement, mode 0x1
723 emit_rm(cbuf, 0x1, regenc, baseenc); // *
724 emit_d8(cbuf, disp);
725 } else {
726 // If 32-bit displacement
727 if (base == -1) { // Special flag for absolute address
728 emit_rm(cbuf, 0x0, regenc, 0x5); // *
729 if (disp_reloc != relocInfo::none) {
730 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
731 } else {
732 emit_d32(cbuf, disp);
733 }
734 } else {
735 // Normal base + offset
736 emit_rm(cbuf, 0x2, regenc, baseenc); // *
737 if (disp_reloc != relocInfo::none) {
738 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
739 } else {
740 emit_d32(cbuf, disp);
741 }
742 }
743 }
744 } else {
745 // Else, encode with the SIB byte
746 // If no displacement, mode is 0x0; unless base is [RBP] or [R13]
747 if (disp == 0 && base != RBP_enc && base != R13_enc) {
748 // If no displacement
749 emit_rm(cbuf, 0x0, regenc, 0x4); // *
750 emit_rm(cbuf, scale, indexenc, baseenc);
751 } else {
752 if (-0x80 <= disp && disp < 0x80 && disp_reloc == relocInfo::none) {
753 // If 8-bit displacement, mode 0x1
754 emit_rm(cbuf, 0x1, regenc, 0x4); // *
755 emit_rm(cbuf, scale, indexenc, baseenc);
756 emit_d8(cbuf, disp);
757 } else {
758 // If 32-bit displacement
759 if (base == 0x04 ) {
760 emit_rm(cbuf, 0x2, regenc, 0x4);
761 emit_rm(cbuf, scale, indexenc, 0x04); // XXX is this valid???
762 } else {
763 emit_rm(cbuf, 0x2, regenc, 0x4);
764 emit_rm(cbuf, scale, indexenc, baseenc); // *
765 }
766 if (disp_reloc != relocInfo::none) {
767 emit_d32_reloc(cbuf, disp, relocInfo::oop_type, RELOC_DISP32);
768 } else {
769 emit_d32(cbuf, disp);
770 }
771 }
772 }
773 }
774 }
775
776 // This could be in MacroAssembler but it's fairly C2 specific
777 void emit_cmpfp_fixup(MacroAssembler& _masm) {
778 Label exit;
779 __ jccb(Assembler::noParity, exit);
780 __ pushf();
781 //
782 // comiss/ucomiss instructions set ZF,PF,CF flags and
783 // zero OF,AF,SF for NaN values.
784 // Fixup flags by zeroing ZF,PF so that compare of NaN
785 // values returns 'less than' result (CF is set).
786 // Leave the rest of flags unchanged.
787 //
788 // 7 6 5 4 3 2 1 0
789 // |S|Z|r|A|r|P|r|C| (r - reserved bit)
790 // 0 0 1 0 1 0 1 1 (0x2B)
791 //
792 __ andq(Address(rsp, 0), 0xffffff2b);
793 __ popf();
794 __ bind(exit);
795 }
796
797 void emit_cmpfp3(MacroAssembler& _masm, Register dst) {
798 Label done;
799 __ movl(dst, -1);
800 __ jcc(Assembler::parity, done);
801 __ jcc(Assembler::below, done);
802 __ setb(Assembler::notEqual, dst);
803 __ movzbl(dst, dst);
804 __ bind(done);
805 }
806
807
808 //=============================================================================
809 const RegMask& MachConstantBaseNode::_out_RegMask = RegMask::Empty;
810
811 int Compile::ConstantTable::calculate_table_base_offset() const {
812 return 0; // absolute addressing, no offset
813 }
814
815 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
816 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
817 ShouldNotReachHere();
818 }
819
820 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
821 // Empty encoding
822 }
823
824 uint MachConstantBaseNode::size(PhaseRegAlloc* ra_) const {
825 return 0;
826 }
827
828 #ifndef PRODUCT
829 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
830 st->print("# MachConstantBaseNode (empty encoding)");
831 }
832 #endif
833
834
835 //=============================================================================
836 #ifndef PRODUCT
837 void MachPrologNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
838 Compile* C = ra_->C;
839
840 int framesize = C->frame_size_in_bytes();
841 int bangsize = C->bang_size_in_bytes();
842 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
843 // Remove wordSize for return addr which is already pushed.
844 framesize -= wordSize;
845
846 if (C->need_stack_bang(bangsize)) {
847 framesize -= wordSize;
848 st->print("# stack bang (%d bytes)", bangsize);
849 st->print("\n\t");
850 st->print("pushq rbp\t# Save rbp");
851 if (PreserveFramePointer) {
852 st->print("\n\t");
853 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
854 }
855 if (framesize) {
856 st->print("\n\t");
857 st->print("subq rsp, #%d\t# Create frame",framesize);
858 }
859 } else {
860 st->print("subq rsp, #%d\t# Create frame",framesize);
861 st->print("\n\t");
862 framesize -= wordSize;
863 st->print("movq [rsp + #%d], rbp\t# Save rbp",framesize);
864 if (PreserveFramePointer) {
865 st->print("\n\t");
866 st->print("movq rbp, rsp\t# Save the caller's SP into rbp");
867 if (framesize > 0) {
868 st->print("\n\t");
869 st->print("addq rbp, #%d", framesize);
870 }
871 }
872 }
873
874 if (VerifyStackAtCalls) {
875 st->print("\n\t");
876 framesize -= wordSize;
877 st->print("movq [rsp + #%d], 0xbadb100d\t# Majik cookie for stack depth check",framesize);
878 #ifdef ASSERT
879 st->print("\n\t");
880 st->print("# stack alignment check");
881 #endif
882 }
883 st->cr();
884 }
885 #endif
886
887 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
888 Compile* C = ra_->C;
889 MacroAssembler _masm(&cbuf);
890
891 int framesize = C->frame_size_in_bytes();
892 int bangsize = C->bang_size_in_bytes();
893
894 __ verified_entry(framesize, C->need_stack_bang(bangsize)?bangsize:0, false);
895
896 C->set_frame_complete(cbuf.insts_size());
897
898 if (C->has_mach_constant_base_node()) {
899 // NOTE: We set the table base offset here because users might be
900 // emitted before MachConstantBaseNode.
901 Compile::ConstantTable& constant_table = C->constant_table();
902 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
903 }
904 }
905
906 uint MachPrologNode::size(PhaseRegAlloc* ra_) const
907 {
908 return MachNode::size(ra_); // too many variables; just compute it
909 // the hard way
910 }
911
912 int MachPrologNode::reloc() const
913 {
914 return 0; // a large enough number
915 }
916
917 //=============================================================================
918 #ifndef PRODUCT
919 void MachEpilogNode::format(PhaseRegAlloc* ra_, outputStream* st) const
920 {
921 Compile* C = ra_->C;
922 if (C->max_vector_size() > 16) {
923 st->print("vzeroupper");
924 st->cr(); st->print("\t");
925 }
926
927 int framesize = C->frame_size_in_bytes();
928 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
929 // Remove word for return adr already pushed
930 // and RBP
931 framesize -= 2*wordSize;
932
933 if (framesize) {
934 st->print_cr("addq rsp, %d\t# Destroy frame", framesize);
935 st->print("\t");
936 }
937
938 st->print_cr("popq rbp");
939 if (do_polling() && C->is_method_compilation()) {
940 st->print("\t");
941 if (Assembler::is_polling_page_far()) {
942 st->print_cr("movq rscratch1, #polling_page_address\n\t"
943 "testl rax, [rscratch1]\t"
944 "# Safepoint: poll for GC");
945 } else {
946 st->print_cr("testl rax, [rip + #offset_to_poll_page]\t"
947 "# Safepoint: poll for GC");
948 }
949 }
950 }
951 #endif
952
953 void MachEpilogNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
954 {
955 Compile* C = ra_->C;
956 MacroAssembler _masm(&cbuf);
957
958 if (C->max_vector_size() > 16) {
959 // Clear upper bits of YMM registers when current compiled code uses
960 // wide vectors to avoid AVX <-> SSE transition penalty during call.
961 __ vzeroupper();
962 }
963
964 int framesize = C->frame_size_in_bytes();
965 assert((framesize & (StackAlignmentInBytes-1)) == 0, "frame size not aligned");
966 // Remove word for return adr already pushed
967 // and RBP
968 framesize -= 2*wordSize;
969
970 // Note that VerifyStackAtCalls' Majik cookie does not change the frame size popped here
971
972 if (framesize) {
973 emit_opcode(cbuf, Assembler::REX_W);
974 if (framesize < 0x80) {
975 emit_opcode(cbuf, 0x83); // addq rsp, #framesize
976 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
977 emit_d8(cbuf, framesize);
978 } else {
979 emit_opcode(cbuf, 0x81); // addq rsp, #framesize
980 emit_rm(cbuf, 0x3, 0x00, RSP_enc);
981 emit_d32(cbuf, framesize);
982 }
983 }
984
985 // popq rbp
986 emit_opcode(cbuf, 0x58 | RBP_enc);
987
988 if (StackReservedPages > 0 && C->has_reserved_stack_access()) {
989 __ reserved_stack_check();
990 }
991
992 if (do_polling() && C->is_method_compilation()) {
993 MacroAssembler _masm(&cbuf);
994 AddressLiteral polling_page(os::get_polling_page(), relocInfo::poll_return_type);
995 if (Assembler::is_polling_page_far()) {
996 __ lea(rscratch1, polling_page);
997 __ relocate(relocInfo::poll_return_type);
998 __ testl(rax, Address(rscratch1, 0));
999 } else {
1000 __ testl(rax, polling_page);
1001 }
1002 }
1003 }
1004
1005 uint MachEpilogNode::size(PhaseRegAlloc* ra_) const
1006 {
1007 return MachNode::size(ra_); // too many variables; just compute it
1008 // the hard way
1009 }
1010
1011 int MachEpilogNode::reloc() const
1012 {
1013 return 2; // a large enough number
1014 }
1015
1016 const Pipeline* MachEpilogNode::pipeline() const
1017 {
1018 return MachNode::pipeline_class();
1019 }
1020
1021 int MachEpilogNode::safepoint_offset() const
1022 {
1023 return 0;
1024 }
1025
1026 //=============================================================================
1027
1028 enum RC {
1029 rc_bad,
1030 rc_int,
1031 rc_float,
1032 rc_stack
1033 };
1034
1035 static enum RC rc_class(OptoReg::Name reg)
1036 {
1037 if( !OptoReg::is_valid(reg) ) return rc_bad;
1038
1039 if (OptoReg::is_stack(reg)) return rc_stack;
1040
1041 VMReg r = OptoReg::as_VMReg(reg);
1042
1043 if (r->is_Register()) return rc_int;
1044
1045 assert(r->is_XMMRegister(), "must be");
1046 return rc_float;
1047 }
1048
1049 // Next two methods are shared by 32- and 64-bit VM. They are defined in x86.ad.
1050 static int vec_mov_helper(CodeBuffer *cbuf, bool do_size, int src_lo, int dst_lo,
1051 int src_hi, int dst_hi, uint ireg, outputStream* st);
1052
1053 static int vec_spill_helper(CodeBuffer *cbuf, bool do_size, bool is_load,
1054 int stack_offset, int reg, uint ireg, outputStream* st);
1055
1056 static void vec_stack_to_stack_helper(CodeBuffer *cbuf, int src_offset,
1057 int dst_offset, uint ireg, outputStream* st) {
1058 if (cbuf) {
1059 MacroAssembler _masm(cbuf);
1060 switch (ireg) {
1061 case Op_VecS:
1062 __ movq(Address(rsp, -8), rax);
1063 __ movl(rax, Address(rsp, src_offset));
1064 __ movl(Address(rsp, dst_offset), rax);
1065 __ movq(rax, Address(rsp, -8));
1066 break;
1067 case Op_VecD:
1068 __ pushq(Address(rsp, src_offset));
1069 __ popq (Address(rsp, dst_offset));
1070 break;
1071 case Op_VecX:
1072 __ pushq(Address(rsp, src_offset));
1073 __ popq (Address(rsp, dst_offset));
1074 __ pushq(Address(rsp, src_offset+8));
1075 __ popq (Address(rsp, dst_offset+8));
1076 break;
1077 case Op_VecY:
1078 __ vmovdqu(Address(rsp, -32), xmm0);
1079 __ vmovdqu(xmm0, Address(rsp, src_offset));
1080 __ vmovdqu(Address(rsp, dst_offset), xmm0);
1081 __ vmovdqu(xmm0, Address(rsp, -32));
1082 break;
1083 case Op_VecZ:
1084 __ evmovdqul(Address(rsp, -64), xmm0, 2);
1085 __ evmovdqul(xmm0, Address(rsp, src_offset), 2);
1086 __ evmovdqul(Address(rsp, dst_offset), xmm0, 2);
1087 __ evmovdqul(xmm0, Address(rsp, -64), 2);
1088 break;
1089 default:
1090 ShouldNotReachHere();
1091 }
1092 #ifndef PRODUCT
1093 } else {
1094 switch (ireg) {
1095 case Op_VecS:
1096 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1097 "movl rax, [rsp + #%d]\n\t"
1098 "movl [rsp + #%d], rax\n\t"
1099 "movq rax, [rsp - #8]",
1100 src_offset, dst_offset);
1101 break;
1102 case Op_VecD:
1103 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1104 "popq [rsp + #%d]",
1105 src_offset, dst_offset);
1106 break;
1107 case Op_VecX:
1108 st->print("pushq [rsp + #%d]\t# 128-bit mem-mem spill\n\t"
1109 "popq [rsp + #%d]\n\t"
1110 "pushq [rsp + #%d]\n\t"
1111 "popq [rsp + #%d]",
1112 src_offset, dst_offset, src_offset+8, dst_offset+8);
1113 break;
1114 case Op_VecY:
1115 st->print("vmovdqu [rsp - #32], xmm0\t# 256-bit mem-mem spill\n\t"
1116 "vmovdqu xmm0, [rsp + #%d]\n\t"
1117 "vmovdqu [rsp + #%d], xmm0\n\t"
1118 "vmovdqu xmm0, [rsp - #32]",
1119 src_offset, dst_offset);
1120 break;
1121 case Op_VecZ:
1122 st->print("vmovdqu [rsp - #64], xmm0\t# 512-bit mem-mem spill\n\t"
1123 "vmovdqu xmm0, [rsp + #%d]\n\t"
1124 "vmovdqu [rsp + #%d], xmm0\n\t"
1125 "vmovdqu xmm0, [rsp - #64]",
1126 src_offset, dst_offset);
1127 break;
1128 default:
1129 ShouldNotReachHere();
1130 }
1131 #endif
1132 }
1133 }
1134
1135 uint MachSpillCopyNode::implementation(CodeBuffer* cbuf,
1136 PhaseRegAlloc* ra_,
1137 bool do_size,
1138 outputStream* st) const {
1139 assert(cbuf != NULL || st != NULL, "sanity");
1140 // Get registers to move
1141 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1142 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1143 OptoReg::Name dst_second = ra_->get_reg_second(this);
1144 OptoReg::Name dst_first = ra_->get_reg_first(this);
1145
1146 enum RC src_second_rc = rc_class(src_second);
1147 enum RC src_first_rc = rc_class(src_first);
1148 enum RC dst_second_rc = rc_class(dst_second);
1149 enum RC dst_first_rc = rc_class(dst_first);
1150
1151 assert(OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first),
1152 "must move at least 1 register" );
1153
1154 if (src_first == dst_first && src_second == dst_second) {
1155 // Self copy, no move
1156 return 0;
1157 }
1158 if (bottom_type()->isa_vect() != NULL) {
1159 uint ireg = ideal_reg();
1160 assert((src_first_rc != rc_int && dst_first_rc != rc_int), "sanity");
1161 assert((ireg == Op_VecS || ireg == Op_VecD || ireg == Op_VecX || ireg == Op_VecY || ireg == Op_VecZ ), "sanity");
1162 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1163 // mem -> mem
1164 int src_offset = ra_->reg2offset(src_first);
1165 int dst_offset = ra_->reg2offset(dst_first);
1166 vec_stack_to_stack_helper(cbuf, src_offset, dst_offset, ireg, st);
1167 } else if (src_first_rc == rc_float && dst_first_rc == rc_float ) {
1168 vec_mov_helper(cbuf, false, src_first, dst_first, src_second, dst_second, ireg, st);
1169 } else if (src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1170 int stack_offset = ra_->reg2offset(dst_first);
1171 vec_spill_helper(cbuf, false, false, stack_offset, src_first, ireg, st);
1172 } else if (src_first_rc == rc_stack && dst_first_rc == rc_float ) {
1173 int stack_offset = ra_->reg2offset(src_first);
1174 vec_spill_helper(cbuf, false, true, stack_offset, dst_first, ireg, st);
1175 } else {
1176 ShouldNotReachHere();
1177 }
1178 return 0;
1179 }
1180 if (src_first_rc == rc_stack) {
1181 // mem ->
1182 if (dst_first_rc == rc_stack) {
1183 // mem -> mem
1184 assert(src_second != dst_first, "overlap");
1185 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1186 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1187 // 64-bit
1188 int src_offset = ra_->reg2offset(src_first);
1189 int dst_offset = ra_->reg2offset(dst_first);
1190 if (cbuf) {
1191 MacroAssembler _masm(cbuf);
1192 __ pushq(Address(rsp, src_offset));
1193 __ popq (Address(rsp, dst_offset));
1194 #ifndef PRODUCT
1195 } else {
1196 st->print("pushq [rsp + #%d]\t# 64-bit mem-mem spill\n\t"
1197 "popq [rsp + #%d]",
1198 src_offset, dst_offset);
1199 #endif
1200 }
1201 } else {
1202 // 32-bit
1203 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1204 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1205 // No pushl/popl, so:
1206 int src_offset = ra_->reg2offset(src_first);
1207 int dst_offset = ra_->reg2offset(dst_first);
1208 if (cbuf) {
1209 MacroAssembler _masm(cbuf);
1210 __ movq(Address(rsp, -8), rax);
1211 __ movl(rax, Address(rsp, src_offset));
1212 __ movl(Address(rsp, dst_offset), rax);
1213 __ movq(rax, Address(rsp, -8));
1214 #ifndef PRODUCT
1215 } else {
1216 st->print("movq [rsp - #8], rax\t# 32-bit mem-mem spill\n\t"
1217 "movl rax, [rsp + #%d]\n\t"
1218 "movl [rsp + #%d], rax\n\t"
1219 "movq rax, [rsp - #8]",
1220 src_offset, dst_offset);
1221 #endif
1222 }
1223 }
1224 return 0;
1225 } else if (dst_first_rc == rc_int) {
1226 // mem -> gpr
1227 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1228 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1229 // 64-bit
1230 int offset = ra_->reg2offset(src_first);
1231 if (cbuf) {
1232 MacroAssembler _masm(cbuf);
1233 __ movq(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1234 #ifndef PRODUCT
1235 } else {
1236 st->print("movq %s, [rsp + #%d]\t# spill",
1237 Matcher::regName[dst_first],
1238 offset);
1239 #endif
1240 }
1241 } else {
1242 // 32-bit
1243 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1244 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1245 int offset = ra_->reg2offset(src_first);
1246 if (cbuf) {
1247 MacroAssembler _masm(cbuf);
1248 __ movl(as_Register(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1249 #ifndef PRODUCT
1250 } else {
1251 st->print("movl %s, [rsp + #%d]\t# spill",
1252 Matcher::regName[dst_first],
1253 offset);
1254 #endif
1255 }
1256 }
1257 return 0;
1258 } else if (dst_first_rc == rc_float) {
1259 // mem-> xmm
1260 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1261 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1262 // 64-bit
1263 int offset = ra_->reg2offset(src_first);
1264 if (cbuf) {
1265 MacroAssembler _masm(cbuf);
1266 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1267 #ifndef PRODUCT
1268 } else {
1269 st->print("%s %s, [rsp + #%d]\t# spill",
1270 UseXmmLoadAndClearUpper ? "movsd " : "movlpd",
1271 Matcher::regName[dst_first],
1272 offset);
1273 #endif
1274 }
1275 } else {
1276 // 32-bit
1277 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1278 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1279 int offset = ra_->reg2offset(src_first);
1280 if (cbuf) {
1281 MacroAssembler _masm(cbuf);
1282 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), Address(rsp, offset));
1283 #ifndef PRODUCT
1284 } else {
1285 st->print("movss %s, [rsp + #%d]\t# spill",
1286 Matcher::regName[dst_first],
1287 offset);
1288 #endif
1289 }
1290 }
1291 return 0;
1292 }
1293 } else if (src_first_rc == rc_int) {
1294 // gpr ->
1295 if (dst_first_rc == rc_stack) {
1296 // gpr -> mem
1297 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1298 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1299 // 64-bit
1300 int offset = ra_->reg2offset(dst_first);
1301 if (cbuf) {
1302 MacroAssembler _masm(cbuf);
1303 __ movq(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1304 #ifndef PRODUCT
1305 } else {
1306 st->print("movq [rsp + #%d], %s\t# spill",
1307 offset,
1308 Matcher::regName[src_first]);
1309 #endif
1310 }
1311 } else {
1312 // 32-bit
1313 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1314 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1315 int offset = ra_->reg2offset(dst_first);
1316 if (cbuf) {
1317 MacroAssembler _masm(cbuf);
1318 __ movl(Address(rsp, offset), as_Register(Matcher::_regEncode[src_first]));
1319 #ifndef PRODUCT
1320 } else {
1321 st->print("movl [rsp + #%d], %s\t# spill",
1322 offset,
1323 Matcher::regName[src_first]);
1324 #endif
1325 }
1326 }
1327 return 0;
1328 } else if (dst_first_rc == rc_int) {
1329 // gpr -> gpr
1330 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1331 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1332 // 64-bit
1333 if (cbuf) {
1334 MacroAssembler _masm(cbuf);
1335 __ movq(as_Register(Matcher::_regEncode[dst_first]),
1336 as_Register(Matcher::_regEncode[src_first]));
1337 #ifndef PRODUCT
1338 } else {
1339 st->print("movq %s, %s\t# spill",
1340 Matcher::regName[dst_first],
1341 Matcher::regName[src_first]);
1342 #endif
1343 }
1344 return 0;
1345 } else {
1346 // 32-bit
1347 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1348 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1349 if (cbuf) {
1350 MacroAssembler _masm(cbuf);
1351 __ movl(as_Register(Matcher::_regEncode[dst_first]),
1352 as_Register(Matcher::_regEncode[src_first]));
1353 #ifndef PRODUCT
1354 } else {
1355 st->print("movl %s, %s\t# spill",
1356 Matcher::regName[dst_first],
1357 Matcher::regName[src_first]);
1358 #endif
1359 }
1360 return 0;
1361 }
1362 } else if (dst_first_rc == rc_float) {
1363 // gpr -> xmm
1364 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1365 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1366 // 64-bit
1367 if (cbuf) {
1368 MacroAssembler _masm(cbuf);
1369 __ movdq( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1370 #ifndef PRODUCT
1371 } else {
1372 st->print("movdq %s, %s\t# spill",
1373 Matcher::regName[dst_first],
1374 Matcher::regName[src_first]);
1375 #endif
1376 }
1377 } else {
1378 // 32-bit
1379 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1380 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1381 if (cbuf) {
1382 MacroAssembler _masm(cbuf);
1383 __ movdl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_Register(Matcher::_regEncode[src_first]));
1384 #ifndef PRODUCT
1385 } else {
1386 st->print("movdl %s, %s\t# spill",
1387 Matcher::regName[dst_first],
1388 Matcher::regName[src_first]);
1389 #endif
1390 }
1391 }
1392 return 0;
1393 }
1394 } else if (src_first_rc == rc_float) {
1395 // xmm ->
1396 if (dst_first_rc == rc_stack) {
1397 // xmm -> mem
1398 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1399 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1400 // 64-bit
1401 int offset = ra_->reg2offset(dst_first);
1402 if (cbuf) {
1403 MacroAssembler _masm(cbuf);
1404 __ movdbl( Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1405 #ifndef PRODUCT
1406 } else {
1407 st->print("movsd [rsp + #%d], %s\t# spill",
1408 offset,
1409 Matcher::regName[src_first]);
1410 #endif
1411 }
1412 } else {
1413 // 32-bit
1414 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1415 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1416 int offset = ra_->reg2offset(dst_first);
1417 if (cbuf) {
1418 MacroAssembler _masm(cbuf);
1419 __ movflt(Address(rsp, offset), as_XMMRegister(Matcher::_regEncode[src_first]));
1420 #ifndef PRODUCT
1421 } else {
1422 st->print("movss [rsp + #%d], %s\t# spill",
1423 offset,
1424 Matcher::regName[src_first]);
1425 #endif
1426 }
1427 }
1428 return 0;
1429 } else if (dst_first_rc == rc_int) {
1430 // xmm -> gpr
1431 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1432 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1433 // 64-bit
1434 if (cbuf) {
1435 MacroAssembler _masm(cbuf);
1436 __ movdq( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1437 #ifndef PRODUCT
1438 } else {
1439 st->print("movdq %s, %s\t# spill",
1440 Matcher::regName[dst_first],
1441 Matcher::regName[src_first]);
1442 #endif
1443 }
1444 } else {
1445 // 32-bit
1446 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1447 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1448 if (cbuf) {
1449 MacroAssembler _masm(cbuf);
1450 __ movdl( as_Register(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1451 #ifndef PRODUCT
1452 } else {
1453 st->print("movdl %s, %s\t# spill",
1454 Matcher::regName[dst_first],
1455 Matcher::regName[src_first]);
1456 #endif
1457 }
1458 }
1459 return 0;
1460 } else if (dst_first_rc == rc_float) {
1461 // xmm -> xmm
1462 if ((src_first & 1) == 0 && src_first + 1 == src_second &&
1463 (dst_first & 1) == 0 && dst_first + 1 == dst_second) {
1464 // 64-bit
1465 if (cbuf) {
1466 MacroAssembler _masm(cbuf);
1467 __ movdbl( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1468 #ifndef PRODUCT
1469 } else {
1470 st->print("%s %s, %s\t# spill",
1471 UseXmmRegToRegMoveAll ? "movapd" : "movsd ",
1472 Matcher::regName[dst_first],
1473 Matcher::regName[src_first]);
1474 #endif
1475 }
1476 } else {
1477 // 32-bit
1478 assert(!((src_first & 1) == 0 && src_first + 1 == src_second), "no transform");
1479 assert(!((dst_first & 1) == 0 && dst_first + 1 == dst_second), "no transform");
1480 if (cbuf) {
1481 MacroAssembler _masm(cbuf);
1482 __ movflt( as_XMMRegister(Matcher::_regEncode[dst_first]), as_XMMRegister(Matcher::_regEncode[src_first]));
1483 #ifndef PRODUCT
1484 } else {
1485 st->print("%s %s, %s\t# spill",
1486 UseXmmRegToRegMoveAll ? "movaps" : "movss ",
1487 Matcher::regName[dst_first],
1488 Matcher::regName[src_first]);
1489 #endif
1490 }
1491 }
1492 return 0;
1493 }
1494 }
1495
1496 assert(0," foo ");
1497 Unimplemented();
1498 return 0;
1499 }
1500
1501 #ifndef PRODUCT
1502 void MachSpillCopyNode::format(PhaseRegAlloc *ra_, outputStream* st) const {
1503 implementation(NULL, ra_, false, st);
1504 }
1505 #endif
1506
1507 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1508 implementation(&cbuf, ra_, false, NULL);
1509 }
1510
1511 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1512 return MachNode::size(ra_);
1513 }
1514
1515 //=============================================================================
1516 #ifndef PRODUCT
1517 void BoxLockNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1518 {
1519 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1520 int reg = ra_->get_reg_first(this);
1521 st->print("leaq %s, [rsp + #%d]\t# box lock",
1522 Matcher::regName[reg], offset);
1523 }
1524 #endif
1525
1526 void BoxLockNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1527 {
1528 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1529 int reg = ra_->get_encode(this);
1530 if (offset >= 0x80) {
1531 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1532 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1533 emit_rm(cbuf, 0x2, reg & 7, 0x04);
1534 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1535 emit_d32(cbuf, offset);
1536 } else {
1537 emit_opcode(cbuf, reg < 8 ? Assembler::REX_W : Assembler::REX_WR);
1538 emit_opcode(cbuf, 0x8D); // LEA reg,[SP+offset]
1539 emit_rm(cbuf, 0x1, reg & 7, 0x04);
1540 emit_rm(cbuf, 0x0, 0x04, RSP_enc);
1541 emit_d8(cbuf, offset);
1542 }
1543 }
1544
1545 uint BoxLockNode::size(PhaseRegAlloc *ra_) const
1546 {
1547 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1548 return (offset < 0x80) ? 5 : 8; // REX
1549 }
1550
1551 //=============================================================================
1552 #ifndef PRODUCT
1553 void MachUEPNode::format(PhaseRegAlloc* ra_, outputStream* st) const
1554 {
1555 if (UseCompressedClassPointers) {
1556 st->print_cr("movl rscratch1, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t# compressed klass");
1557 st->print_cr("\tdecode_klass_not_null rscratch1, rscratch1");
1558 st->print_cr("\tcmpq rax, rscratch1\t # Inline cache check");
1559 } else {
1560 st->print_cr("\tcmpq rax, [j_rarg0 + oopDesc::klass_offset_in_bytes()]\t"
1561 "# Inline cache check");
1562 }
1563 st->print_cr("\tjne SharedRuntime::_ic_miss_stub");
1564 st->print_cr("\tnop\t# nops to align entry point");
1565 }
1566 #endif
1567
1568 void MachUEPNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const
1569 {
1570 MacroAssembler masm(&cbuf);
1571 uint insts_size = cbuf.insts_size();
1572 if (UseCompressedClassPointers) {
1573 masm.load_klass(rscratch1, j_rarg0);
1574 masm.cmpptr(rax, rscratch1);
1575 } else {
1576 masm.cmpptr(rax, Address(j_rarg0, oopDesc::klass_offset_in_bytes()));
1577 }
1578
1579 masm.jump_cc(Assembler::notEqual, RuntimeAddress(SharedRuntime::get_ic_miss_stub()));
1580
1581 /* WARNING these NOPs are critical so that verified entry point is properly
1582 4 bytes aligned for patching by NativeJump::patch_verified_entry() */
1583 int nops_cnt = 4 - ((cbuf.insts_size() - insts_size) & 0x3);
1584 if (OptoBreakpoint) {
1585 // Leave space for int3
1586 nops_cnt -= 1;
1587 }
1588 nops_cnt &= 0x3; // Do not add nops if code is aligned.
1589 if (nops_cnt > 0)
1590 masm.nop(nops_cnt);
1591 }
1592
1593 uint MachUEPNode::size(PhaseRegAlloc* ra_) const
1594 {
1595 return MachNode::size(ra_); // too many variables; just compute it
1596 // the hard way
1597 }
1598
1599
1600 //=============================================================================
1601
1602 int Matcher::regnum_to_fpu_offset(int regnum)
1603 {
1604 return regnum - 32; // The FP registers are in the second chunk
1605 }
1606
1607 // This is UltraSparc specific, true just means we have fast l2f conversion
1608 const bool Matcher::convL2FSupported(void) {
1609 return true;
1610 }
1611
1612 // Is this branch offset short enough that a short branch can be used?
1613 //
1614 // NOTE: If the platform does not provide any short branch variants, then
1615 // this method should return false for offset 0.
1616 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1617 // The passed offset is relative to address of the branch.
1618 // On 86 a branch displacement is calculated relative to address
1619 // of a next instruction.
1620 offset -= br_size;
1621
1622 // the short version of jmpConUCF2 contains multiple branches,
1623 // making the reach slightly less
1624 if (rule == jmpConUCF2_rule)
1625 return (-126 <= offset && offset <= 125);
1626 return (-128 <= offset && offset <= 127);
1627 }
1628
1629 const bool Matcher::isSimpleConstant64(jlong value) {
1630 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1631 //return value == (int) value; // Cf. storeImmL and immL32.
1632
1633 // Probably always true, even if a temp register is required.
1634 return true;
1635 }
1636
1637 // The ecx parameter to rep stosq for the ClearArray node is in words.
1638 const bool Matcher::init_array_count_is_in_bytes = false;
1639
1640 // Threshold size for cleararray.
1641 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1642
1643 // No additional cost for CMOVL.
1644 const int Matcher::long_cmove_cost() { return 0; }
1645
1646 // No CMOVF/CMOVD with SSE2
1647 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
1648
1649 // Does the CPU require late expand (see block.cpp for description of late expand)?
1650 const bool Matcher::require_postalloc_expand = false;
1651
1652 // Should the Matcher clone shifts on addressing modes, expecting them
1653 // to be subsumed into complex addressing expressions or compute them
1654 // into registers? True for Intel but false for most RISCs
1655 const bool Matcher::clone_shift_expressions = true;
1656
1657 // Do we need to mask the count passed to shift instructions or does
1658 // the cpu only look at the lower 5/6 bits anyway?
1659 const bool Matcher::need_masked_shift_count = false;
1660
1661 bool Matcher::narrow_oop_use_complex_address() {
1662 assert(UseCompressedOops, "only for compressed oops code");
1663 return (LogMinObjAlignmentInBytes <= 3);
1664 }
1665
1666 bool Matcher::narrow_klass_use_complex_address() {
1667 assert(UseCompressedClassPointers, "only for compressed klass code");
1668 return (LogKlassAlignmentInBytes <= 3);
1669 }
1670
1671 // Is it better to copy float constants, or load them directly from
1672 // memory? Intel can load a float constant from a direct address,
1673 // requiring no extra registers. Most RISCs will have to materialize
1674 // an address into a register first, so they would do better to copy
1675 // the constant from stack.
1676 const bool Matcher::rematerialize_float_constants = true; // XXX
1677
1678 // If CPU can load and store mis-aligned doubles directly then no
1679 // fixup is needed. Else we split the double into 2 integer pieces
1680 // and move it piece-by-piece. Only happens when passing doubles into
1681 // C code as the Java calling convention forces doubles to be aligned.
1682 const bool Matcher::misaligned_doubles_ok = true;
1683
1684 // No-op on amd64
1685 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {}
1686
1687 // Advertise here if the CPU requires explicit rounding operations to
1688 // implement the UseStrictFP mode.
1689 const bool Matcher::strict_fp_requires_explicit_rounding = true;
1690
1691 // Are floats conerted to double when stored to stack during deoptimization?
1692 // On x64 it is stored without convertion so we can use normal access.
1693 bool Matcher::float_in_double() { return false; }
1694
1695 // Do ints take an entire long register or just half?
1696 const bool Matcher::int_in_long = true;
1697
1698 // Return whether or not this register is ever used as an argument.
1699 // This function is used on startup to build the trampoline stubs in
1700 // generateOptoStub. Registers not mentioned will be killed by the VM
1701 // call in the trampoline, and arguments in those registers not be
1702 // available to the callee.
1703 bool Matcher::can_be_java_arg(int reg)
1704 {
1705 return
1706 reg == RDI_num || reg == RDI_H_num ||
1707 reg == RSI_num || reg == RSI_H_num ||
1708 reg == RDX_num || reg == RDX_H_num ||
1709 reg == RCX_num || reg == RCX_H_num ||
1710 reg == R8_num || reg == R8_H_num ||
1711 reg == R9_num || reg == R9_H_num ||
1712 reg == R12_num || reg == R12_H_num ||
1713 reg == XMM0_num || reg == XMM0b_num ||
1714 reg == XMM1_num || reg == XMM1b_num ||
1715 reg == XMM2_num || reg == XMM2b_num ||
1716 reg == XMM3_num || reg == XMM3b_num ||
1717 reg == XMM4_num || reg == XMM4b_num ||
1718 reg == XMM5_num || reg == XMM5b_num ||
1719 reg == XMM6_num || reg == XMM6b_num ||
1720 reg == XMM7_num || reg == XMM7b_num;
1721 }
1722
1723 bool Matcher::is_spillable_arg(int reg)
1724 {
1725 return can_be_java_arg(reg);
1726 }
1727
1728 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
1729 // In 64 bit mode a code which use multiply when
1730 // devisor is constant is faster than hardware
1731 // DIV instruction (it uses MulHiL).
1732 return false;
1733 }
1734
1735 // Register for DIVI projection of divmodI
1736 RegMask Matcher::divI_proj_mask() {
1737 return INT_RAX_REG_mask();
1738 }
1739
1740 // Register for MODI projection of divmodI
1741 RegMask Matcher::modI_proj_mask() {
1742 return INT_RDX_REG_mask();
1743 }
1744
1745 // Register for DIVL projection of divmodL
1746 RegMask Matcher::divL_proj_mask() {
1747 return LONG_RAX_REG_mask();
1748 }
1749
1750 // Register for MODL projection of divmodL
1751 RegMask Matcher::modL_proj_mask() {
1752 return LONG_RDX_REG_mask();
1753 }
1754
1755 // Register for saving SP into on method handle invokes. Not used on x86_64.
1756 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
1757 return NO_REG_mask();
1758 }
1759
1760 %}
1761
1762 //----------ENCODING BLOCK-----------------------------------------------------
1763 // This block specifies the encoding classes used by the compiler to
1764 // output byte streams. Encoding classes are parameterized macros
1765 // used by Machine Instruction Nodes in order to generate the bit
1766 // encoding of the instruction. Operands specify their base encoding
1767 // interface with the interface keyword. There are currently
1768 // supported four interfaces, REG_INTER, CONST_INTER, MEMORY_INTER, &
1769 // COND_INTER. REG_INTER causes an operand to generate a function
1770 // which returns its register number when queried. CONST_INTER causes
1771 // an operand to generate a function which returns the value of the
1772 // constant when queried. MEMORY_INTER causes an operand to generate
1773 // four functions which return the Base Register, the Index Register,
1774 // the Scale Value, and the Offset Value of the operand when queried.
1775 // COND_INTER causes an operand to generate six functions which return
1776 // the encoding code (ie - encoding bits for the instruction)
1777 // associated with each basic boolean condition for a conditional
1778 // instruction.
1779 //
1780 // Instructions specify two basic values for encoding. Again, a
1781 // function is available to check if the constant displacement is an
1782 // oop. They use the ins_encode keyword to specify their encoding
1783 // classes (which must be a sequence of enc_class names, and their
1784 // parameters, specified in the encoding block), and they use the
1785 // opcode keyword to specify, in order, their primary, secondary, and
1786 // tertiary opcode. Only the opcode sections which a particular
1787 // instruction needs for encoding need to be specified.
1788 encode %{
1789 // Build emit functions for each basic byte or larger field in the
1790 // intel encoding scheme (opcode, rm, sib, immediate), and call them
1791 // from C++ code in the enc_class source block. Emit functions will
1792 // live in the main source block for now. In future, we can
1793 // generalize this by adding a syntax that specifies the sizes of
1794 // fields in an order, so that the adlc can build the emit functions
1795 // automagically
1796
1797 // Emit primary opcode
1798 enc_class OpcP
1799 %{
1800 emit_opcode(cbuf, $primary);
1801 %}
1802
1803 // Emit secondary opcode
1804 enc_class OpcS
1805 %{
1806 emit_opcode(cbuf, $secondary);
1807 %}
1808
1809 // Emit tertiary opcode
1810 enc_class OpcT
1811 %{
1812 emit_opcode(cbuf, $tertiary);
1813 %}
1814
1815 // Emit opcode directly
1816 enc_class Opcode(immI d8)
1817 %{
1818 emit_opcode(cbuf, $d8$$constant);
1819 %}
1820
1821 // Emit size prefix
1822 enc_class SizePrefix
1823 %{
1824 emit_opcode(cbuf, 0x66);
1825 %}
1826
1827 enc_class reg(rRegI reg)
1828 %{
1829 emit_rm(cbuf, 0x3, 0, $reg$$reg & 7);
1830 %}
1831
1832 enc_class reg_reg(rRegI dst, rRegI src)
1833 %{
1834 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1835 %}
1836
1837 enc_class opc_reg_reg(immI opcode, rRegI dst, rRegI src)
1838 %{
1839 emit_opcode(cbuf, $opcode$$constant);
1840 emit_rm(cbuf, 0x3, $dst$$reg & 7, $src$$reg & 7);
1841 %}
1842
1843 enc_class cdql_enc(no_rax_rdx_RegI div)
1844 %{
1845 // Full implementation of Java idiv and irem; checks for
1846 // special case as described in JVM spec., p.243 & p.271.
1847 //
1848 // normal case special case
1849 //
1850 // input : rax: dividend min_int
1851 // reg: divisor -1
1852 //
1853 // output: rax: quotient (= rax idiv reg) min_int
1854 // rdx: remainder (= rax irem reg) 0
1855 //
1856 // Code sequnce:
1857 //
1858 // 0: 3d 00 00 00 80 cmp $0x80000000,%eax
1859 // 5: 75 07/08 jne e <normal>
1860 // 7: 33 d2 xor %edx,%edx
1861 // [div >= 8 -> offset + 1]
1862 // [REX_B]
1863 // 9: 83 f9 ff cmp $0xffffffffffffffff,$div
1864 // c: 74 03/04 je 11 <done>
1865 // 000000000000000e <normal>:
1866 // e: 99 cltd
1867 // [div >= 8 -> offset + 1]
1868 // [REX_B]
1869 // f: f7 f9 idiv $div
1870 // 0000000000000011 <done>:
1871
1872 // cmp $0x80000000,%eax
1873 emit_opcode(cbuf, 0x3d);
1874 emit_d8(cbuf, 0x00);
1875 emit_d8(cbuf, 0x00);
1876 emit_d8(cbuf, 0x00);
1877 emit_d8(cbuf, 0x80);
1878
1879 // jne e <normal>
1880 emit_opcode(cbuf, 0x75);
1881 emit_d8(cbuf, $div$$reg < 8 ? 0x07 : 0x08);
1882
1883 // xor %edx,%edx
1884 emit_opcode(cbuf, 0x33);
1885 emit_d8(cbuf, 0xD2);
1886
1887 // cmp $0xffffffffffffffff,%ecx
1888 if ($div$$reg >= 8) {
1889 emit_opcode(cbuf, Assembler::REX_B);
1890 }
1891 emit_opcode(cbuf, 0x83);
1892 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1893 emit_d8(cbuf, 0xFF);
1894
1895 // je 11 <done>
1896 emit_opcode(cbuf, 0x74);
1897 emit_d8(cbuf, $div$$reg < 8 ? 0x03 : 0x04);
1898
1899 // <normal>
1900 // cltd
1901 emit_opcode(cbuf, 0x99);
1902
1903 // idivl (note: must be emitted by the user of this rule)
1904 // <done>
1905 %}
1906
1907 enc_class cdqq_enc(no_rax_rdx_RegL div)
1908 %{
1909 // Full implementation of Java ldiv and lrem; checks for
1910 // special case as described in JVM spec., p.243 & p.271.
1911 //
1912 // normal case special case
1913 //
1914 // input : rax: dividend min_long
1915 // reg: divisor -1
1916 //
1917 // output: rax: quotient (= rax idiv reg) min_long
1918 // rdx: remainder (= rax irem reg) 0
1919 //
1920 // Code sequnce:
1921 //
1922 // 0: 48 ba 00 00 00 00 00 mov $0x8000000000000000,%rdx
1923 // 7: 00 00 80
1924 // a: 48 39 d0 cmp %rdx,%rax
1925 // d: 75 08 jne 17 <normal>
1926 // f: 33 d2 xor %edx,%edx
1927 // 11: 48 83 f9 ff cmp $0xffffffffffffffff,$div
1928 // 15: 74 05 je 1c <done>
1929 // 0000000000000017 <normal>:
1930 // 17: 48 99 cqto
1931 // 19: 48 f7 f9 idiv $div
1932 // 000000000000001c <done>:
1933
1934 // mov $0x8000000000000000,%rdx
1935 emit_opcode(cbuf, Assembler::REX_W);
1936 emit_opcode(cbuf, 0xBA);
1937 emit_d8(cbuf, 0x00);
1938 emit_d8(cbuf, 0x00);
1939 emit_d8(cbuf, 0x00);
1940 emit_d8(cbuf, 0x00);
1941 emit_d8(cbuf, 0x00);
1942 emit_d8(cbuf, 0x00);
1943 emit_d8(cbuf, 0x00);
1944 emit_d8(cbuf, 0x80);
1945
1946 // cmp %rdx,%rax
1947 emit_opcode(cbuf, Assembler::REX_W);
1948 emit_opcode(cbuf, 0x39);
1949 emit_d8(cbuf, 0xD0);
1950
1951 // jne 17 <normal>
1952 emit_opcode(cbuf, 0x75);
1953 emit_d8(cbuf, 0x08);
1954
1955 // xor %edx,%edx
1956 emit_opcode(cbuf, 0x33);
1957 emit_d8(cbuf, 0xD2);
1958
1959 // cmp $0xffffffffffffffff,$div
1960 emit_opcode(cbuf, $div$$reg < 8 ? Assembler::REX_W : Assembler::REX_WB);
1961 emit_opcode(cbuf, 0x83);
1962 emit_rm(cbuf, 0x3, 0x7, $div$$reg & 7);
1963 emit_d8(cbuf, 0xFF);
1964
1965 // je 1e <done>
1966 emit_opcode(cbuf, 0x74);
1967 emit_d8(cbuf, 0x05);
1968
1969 // <normal>
1970 // cqto
1971 emit_opcode(cbuf, Assembler::REX_W);
1972 emit_opcode(cbuf, 0x99);
1973
1974 // idivq (note: must be emitted by the user of this rule)
1975 // <done>
1976 %}
1977
1978 // Opcde enc_class for 8/32 bit immediate instructions with sign-extension
1979 enc_class OpcSE(immI imm)
1980 %{
1981 // Emit primary opcode and set sign-extend bit
1982 // Check for 8-bit immediate, and set sign extend bit in opcode
1983 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
1984 emit_opcode(cbuf, $primary | 0x02);
1985 } else {
1986 // 32-bit immediate
1987 emit_opcode(cbuf, $primary);
1988 }
1989 %}
1990
1991 enc_class OpcSErm(rRegI dst, immI imm)
1992 %{
1993 // OpcSEr/m
1994 int dstenc = $dst$$reg;
1995 if (dstenc >= 8) {
1996 emit_opcode(cbuf, Assembler::REX_B);
1997 dstenc -= 8;
1998 }
1999 // Emit primary opcode and set sign-extend bit
2000 // Check for 8-bit immediate, and set sign extend bit in opcode
2001 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2002 emit_opcode(cbuf, $primary | 0x02);
2003 } else {
2004 // 32-bit immediate
2005 emit_opcode(cbuf, $primary);
2006 }
2007 // Emit r/m byte with secondary opcode, after primary opcode.
2008 emit_rm(cbuf, 0x3, $secondary, dstenc);
2009 %}
2010
2011 enc_class OpcSErm_wide(rRegL dst, immI imm)
2012 %{
2013 // OpcSEr/m
2014 int dstenc = $dst$$reg;
2015 if (dstenc < 8) {
2016 emit_opcode(cbuf, Assembler::REX_W);
2017 } else {
2018 emit_opcode(cbuf, Assembler::REX_WB);
2019 dstenc -= 8;
2020 }
2021 // Emit primary opcode and set sign-extend bit
2022 // Check for 8-bit immediate, and set sign extend bit in opcode
2023 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2024 emit_opcode(cbuf, $primary | 0x02);
2025 } else {
2026 // 32-bit immediate
2027 emit_opcode(cbuf, $primary);
2028 }
2029 // Emit r/m byte with secondary opcode, after primary opcode.
2030 emit_rm(cbuf, 0x3, $secondary, dstenc);
2031 %}
2032
2033 enc_class Con8or32(immI imm)
2034 %{
2035 // Check for 8-bit immediate, and set sign extend bit in opcode
2036 if (-0x80 <= $imm$$constant && $imm$$constant < 0x80) {
2037 $$$emit8$imm$$constant;
2038 } else {
2039 // 32-bit immediate
2040 $$$emit32$imm$$constant;
2041 }
2042 %}
2043
2044 enc_class opc2_reg(rRegI dst)
2045 %{
2046 // BSWAP
2047 emit_cc(cbuf, $secondary, $dst$$reg);
2048 %}
2049
2050 enc_class opc3_reg(rRegI dst)
2051 %{
2052 // BSWAP
2053 emit_cc(cbuf, $tertiary, $dst$$reg);
2054 %}
2055
2056 enc_class reg_opc(rRegI div)
2057 %{
2058 // INC, DEC, IDIV, IMOD, JMP indirect, ...
2059 emit_rm(cbuf, 0x3, $secondary, $div$$reg & 7);
2060 %}
2061
2062 enc_class enc_cmov(cmpOp cop)
2063 %{
2064 // CMOV
2065 $$$emit8$primary;
2066 emit_cc(cbuf, $secondary, $cop$$cmpcode);
2067 %}
2068
2069 enc_class enc_PartialSubtypeCheck()
2070 %{
2071 Register Rrdi = as_Register(RDI_enc); // result register
2072 Register Rrax = as_Register(RAX_enc); // super class
2073 Register Rrcx = as_Register(RCX_enc); // killed
2074 Register Rrsi = as_Register(RSI_enc); // sub class
2075 Label miss;
2076 const bool set_cond_codes = true;
2077
2078 MacroAssembler _masm(&cbuf);
2079 __ check_klass_subtype_slow_path(Rrsi, Rrax, Rrcx, Rrdi,
2080 NULL, &miss,
2081 /*set_cond_codes:*/ true);
2082 if ($primary) {
2083 __ xorptr(Rrdi, Rrdi);
2084 }
2085 __ bind(miss);
2086 %}
2087
2088 enc_class clear_avx %{
2089 debug_only(int off0 = cbuf.insts_size());
2090 if (ra_->C->max_vector_size() > 16) {
2091 // Clear upper bits of YMM registers when current compiled code uses
2092 // wide vectors to avoid AVX <-> SSE transition penalty during call.
2093 MacroAssembler _masm(&cbuf);
2094 __ vzeroupper();
2095 }
2096 debug_only(int off1 = cbuf.insts_size());
2097 assert(off1 - off0 == clear_avx_size(), "correct size prediction");
2098 %}
2099
2100 enc_class Java_To_Runtime(method meth) %{
2101 // No relocation needed
2102 MacroAssembler _masm(&cbuf);
2103 __ mov64(r10, (int64_t) $meth$$method);
2104 __ call(r10);
2105 %}
2106
2107 enc_class Java_To_Interpreter(method meth)
2108 %{
2109 // CALL Java_To_Interpreter
2110 // This is the instruction starting address for relocation info.
2111 cbuf.set_insts_mark();
2112 $$$emit8$primary;
2113 // CALL directly to the runtime
2114 emit_d32_reloc(cbuf,
2115 (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2116 runtime_call_Relocation::spec(),
2117 RELOC_DISP32);
2118 %}
2119
2120 enc_class Java_Static_Call(method meth)
2121 %{
2122 // JAVA STATIC CALL
2123 // CALL to fixup routine. Fixup routine uses ScopeDesc info to
2124 // determine who we intended to call.
2125 cbuf.set_insts_mark();
2126 $$$emit8$primary;
2127
2128 if (!_method) {
2129 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2130 runtime_call_Relocation::spec(),
2131 RELOC_DISP32);
2132 } else {
2133 int method_index = resolved_method_index(cbuf);
2134 RelocationHolder rspec = _optimized_virtual ? opt_virtual_call_Relocation::spec(method_index)
2135 : static_call_Relocation::spec(method_index);
2136 emit_d32_reloc(cbuf, (int) ($meth$$method - ((intptr_t) cbuf.insts_end()) - 4),
2137 rspec, RELOC_DISP32);
2138 // Emit stubs for static call.
2139 address mark = cbuf.insts_mark();
2140 address stub = CompiledStaticCall::emit_to_interp_stub(cbuf, mark);
2141 if (stub == NULL) {
2142 ciEnv::current()->record_failure("CodeCache is full");
2143 return;
2144 }
2145 }
2146 %}
2147
2148 enc_class Java_Dynamic_Call(method meth) %{
2149 MacroAssembler _masm(&cbuf);
2150 __ ic_call((address)$meth$$method, resolved_method_index(cbuf));
2151 %}
2152
2153 enc_class Java_Compiled_Call(method meth)
2154 %{
2155 // JAVA COMPILED CALL
2156 int disp = in_bytes(Method:: from_compiled_offset());
2157
2158 // XXX XXX offset is 128 is 1.5 NON-PRODUCT !!!
2159 // assert(-0x80 <= disp && disp < 0x80, "compiled_code_offset isn't small");
2160
2161 // callq *disp(%rax)
2162 cbuf.set_insts_mark();
2163 $$$emit8$primary;
2164 if (disp < 0x80) {
2165 emit_rm(cbuf, 0x01, $secondary, RAX_enc); // R/M byte
2166 emit_d8(cbuf, disp); // Displacement
2167 } else {
2168 emit_rm(cbuf, 0x02, $secondary, RAX_enc); // R/M byte
2169 emit_d32(cbuf, disp); // Displacement
2170 }
2171 %}
2172
2173 enc_class reg_opc_imm(rRegI dst, immI8 shift)
2174 %{
2175 // SAL, SAR, SHR
2176 int dstenc = $dst$$reg;
2177 if (dstenc >= 8) {
2178 emit_opcode(cbuf, Assembler::REX_B);
2179 dstenc -= 8;
2180 }
2181 $$$emit8$primary;
2182 emit_rm(cbuf, 0x3, $secondary, dstenc);
2183 $$$emit8$shift$$constant;
2184 %}
2185
2186 enc_class reg_opc_imm_wide(rRegL dst, immI8 shift)
2187 %{
2188 // SAL, SAR, SHR
2189 int dstenc = $dst$$reg;
2190 if (dstenc < 8) {
2191 emit_opcode(cbuf, Assembler::REX_W);
2192 } else {
2193 emit_opcode(cbuf, Assembler::REX_WB);
2194 dstenc -= 8;
2195 }
2196 $$$emit8$primary;
2197 emit_rm(cbuf, 0x3, $secondary, dstenc);
2198 $$$emit8$shift$$constant;
2199 %}
2200
2201 enc_class load_immI(rRegI dst, immI src)
2202 %{
2203 int dstenc = $dst$$reg;
2204 if (dstenc >= 8) {
2205 emit_opcode(cbuf, Assembler::REX_B);
2206 dstenc -= 8;
2207 }
2208 emit_opcode(cbuf, 0xB8 | dstenc);
2209 $$$emit32$src$$constant;
2210 %}
2211
2212 enc_class load_immL(rRegL dst, immL src)
2213 %{
2214 int dstenc = $dst$$reg;
2215 if (dstenc < 8) {
2216 emit_opcode(cbuf, Assembler::REX_W);
2217 } else {
2218 emit_opcode(cbuf, Assembler::REX_WB);
2219 dstenc -= 8;
2220 }
2221 emit_opcode(cbuf, 0xB8 | dstenc);
2222 emit_d64(cbuf, $src$$constant);
2223 %}
2224
2225 enc_class load_immUL32(rRegL dst, immUL32 src)
2226 %{
2227 // same as load_immI, but this time we care about zeroes in the high word
2228 int dstenc = $dst$$reg;
2229 if (dstenc >= 8) {
2230 emit_opcode(cbuf, Assembler::REX_B);
2231 dstenc -= 8;
2232 }
2233 emit_opcode(cbuf, 0xB8 | dstenc);
2234 $$$emit32$src$$constant;
2235 %}
2236
2237 enc_class load_immL32(rRegL dst, immL32 src)
2238 %{
2239 int dstenc = $dst$$reg;
2240 if (dstenc < 8) {
2241 emit_opcode(cbuf, Assembler::REX_W);
2242 } else {
2243 emit_opcode(cbuf, Assembler::REX_WB);
2244 dstenc -= 8;
2245 }
2246 emit_opcode(cbuf, 0xC7);
2247 emit_rm(cbuf, 0x03, 0x00, dstenc);
2248 $$$emit32$src$$constant;
2249 %}
2250
2251 enc_class load_immP31(rRegP dst, immP32 src)
2252 %{
2253 // same as load_immI, but this time we care about zeroes in the high word
2254 int dstenc = $dst$$reg;
2255 if (dstenc >= 8) {
2256 emit_opcode(cbuf, Assembler::REX_B);
2257 dstenc -= 8;
2258 }
2259 emit_opcode(cbuf, 0xB8 | dstenc);
2260 $$$emit32$src$$constant;
2261 %}
2262
2263 enc_class load_immP(rRegP dst, immP src)
2264 %{
2265 int dstenc = $dst$$reg;
2266 if (dstenc < 8) {
2267 emit_opcode(cbuf, Assembler::REX_W);
2268 } else {
2269 emit_opcode(cbuf, Assembler::REX_WB);
2270 dstenc -= 8;
2271 }
2272 emit_opcode(cbuf, 0xB8 | dstenc);
2273 // This next line should be generated from ADLC
2274 if ($src->constant_reloc() != relocInfo::none) {
2275 emit_d64_reloc(cbuf, $src$$constant, $src->constant_reloc(), RELOC_IMM64);
2276 } else {
2277 emit_d64(cbuf, $src$$constant);
2278 }
2279 %}
2280
2281 enc_class Con32(immI src)
2282 %{
2283 // Output immediate
2284 $$$emit32$src$$constant;
2285 %}
2286
2287 enc_class Con32F_as_bits(immF src)
2288 %{
2289 // Output Float immediate bits
2290 jfloat jf = $src$$constant;
2291 jint jf_as_bits = jint_cast(jf);
2292 emit_d32(cbuf, jf_as_bits);
2293 %}
2294
2295 enc_class Con16(immI src)
2296 %{
2297 // Output immediate
2298 $$$emit16$src$$constant;
2299 %}
2300
2301 // How is this different from Con32??? XXX
2302 enc_class Con_d32(immI src)
2303 %{
2304 emit_d32(cbuf,$src$$constant);
2305 %}
2306
2307 enc_class conmemref (rRegP t1) %{ // Con32(storeImmI)
2308 // Output immediate memory reference
2309 emit_rm(cbuf, 0x00, $t1$$reg, 0x05 );
2310 emit_d32(cbuf, 0x00);
2311 %}
2312
2313 enc_class lock_prefix()
2314 %{
2315 if (os::is_MP()) {
2316 emit_opcode(cbuf, 0xF0); // lock
2317 }
2318 %}
2319
2320 enc_class REX_mem(memory mem)
2321 %{
2322 if ($mem$$base >= 8) {
2323 if ($mem$$index < 8) {
2324 emit_opcode(cbuf, Assembler::REX_B);
2325 } else {
2326 emit_opcode(cbuf, Assembler::REX_XB);
2327 }
2328 } else {
2329 if ($mem$$index >= 8) {
2330 emit_opcode(cbuf, Assembler::REX_X);
2331 }
2332 }
2333 %}
2334
2335 enc_class REX_mem_wide(memory mem)
2336 %{
2337 if ($mem$$base >= 8) {
2338 if ($mem$$index < 8) {
2339 emit_opcode(cbuf, Assembler::REX_WB);
2340 } else {
2341 emit_opcode(cbuf, Assembler::REX_WXB);
2342 }
2343 } else {
2344 if ($mem$$index < 8) {
2345 emit_opcode(cbuf, Assembler::REX_W);
2346 } else {
2347 emit_opcode(cbuf, Assembler::REX_WX);
2348 }
2349 }
2350 %}
2351
2352 // for byte regs
2353 enc_class REX_breg(rRegI reg)
2354 %{
2355 if ($reg$$reg >= 4) {
2356 emit_opcode(cbuf, $reg$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2357 }
2358 %}
2359
2360 // for byte regs
2361 enc_class REX_reg_breg(rRegI dst, rRegI src)
2362 %{
2363 if ($dst$$reg < 8) {
2364 if ($src$$reg >= 4) {
2365 emit_opcode(cbuf, $src$$reg < 8 ? Assembler::REX : Assembler::REX_B);
2366 }
2367 } else {
2368 if ($src$$reg < 8) {
2369 emit_opcode(cbuf, Assembler::REX_R);
2370 } else {
2371 emit_opcode(cbuf, Assembler::REX_RB);
2372 }
2373 }
2374 %}
2375
2376 // for byte regs
2377 enc_class REX_breg_mem(rRegI reg, memory mem)
2378 %{
2379 if ($reg$$reg < 8) {
2380 if ($mem$$base < 8) {
2381 if ($mem$$index >= 8) {
2382 emit_opcode(cbuf, Assembler::REX_X);
2383 } else if ($reg$$reg >= 4) {
2384 emit_opcode(cbuf, Assembler::REX);
2385 }
2386 } else {
2387 if ($mem$$index < 8) {
2388 emit_opcode(cbuf, Assembler::REX_B);
2389 } else {
2390 emit_opcode(cbuf, Assembler::REX_XB);
2391 }
2392 }
2393 } else {
2394 if ($mem$$base < 8) {
2395 if ($mem$$index < 8) {
2396 emit_opcode(cbuf, Assembler::REX_R);
2397 } else {
2398 emit_opcode(cbuf, Assembler::REX_RX);
2399 }
2400 } else {
2401 if ($mem$$index < 8) {
2402 emit_opcode(cbuf, Assembler::REX_RB);
2403 } else {
2404 emit_opcode(cbuf, Assembler::REX_RXB);
2405 }
2406 }
2407 }
2408 %}
2409
2410 enc_class REX_reg(rRegI reg)
2411 %{
2412 if ($reg$$reg >= 8) {
2413 emit_opcode(cbuf, Assembler::REX_B);
2414 }
2415 %}
2416
2417 enc_class REX_reg_wide(rRegI reg)
2418 %{
2419 if ($reg$$reg < 8) {
2420 emit_opcode(cbuf, Assembler::REX_W);
2421 } else {
2422 emit_opcode(cbuf, Assembler::REX_WB);
2423 }
2424 %}
2425
2426 enc_class REX_reg_reg(rRegI dst, rRegI src)
2427 %{
2428 if ($dst$$reg < 8) {
2429 if ($src$$reg >= 8) {
2430 emit_opcode(cbuf, Assembler::REX_B);
2431 }
2432 } else {
2433 if ($src$$reg < 8) {
2434 emit_opcode(cbuf, Assembler::REX_R);
2435 } else {
2436 emit_opcode(cbuf, Assembler::REX_RB);
2437 }
2438 }
2439 %}
2440
2441 enc_class REX_reg_reg_wide(rRegI dst, rRegI src)
2442 %{
2443 if ($dst$$reg < 8) {
2444 if ($src$$reg < 8) {
2445 emit_opcode(cbuf, Assembler::REX_W);
2446 } else {
2447 emit_opcode(cbuf, Assembler::REX_WB);
2448 }
2449 } else {
2450 if ($src$$reg < 8) {
2451 emit_opcode(cbuf, Assembler::REX_WR);
2452 } else {
2453 emit_opcode(cbuf, Assembler::REX_WRB);
2454 }
2455 }
2456 %}
2457
2458 enc_class REX_reg_mem(rRegI reg, memory mem)
2459 %{
2460 if ($reg$$reg < 8) {
2461 if ($mem$$base < 8) {
2462 if ($mem$$index >= 8) {
2463 emit_opcode(cbuf, Assembler::REX_X);
2464 }
2465 } else {
2466 if ($mem$$index < 8) {
2467 emit_opcode(cbuf, Assembler::REX_B);
2468 } else {
2469 emit_opcode(cbuf, Assembler::REX_XB);
2470 }
2471 }
2472 } else {
2473 if ($mem$$base < 8) {
2474 if ($mem$$index < 8) {
2475 emit_opcode(cbuf, Assembler::REX_R);
2476 } else {
2477 emit_opcode(cbuf, Assembler::REX_RX);
2478 }
2479 } else {
2480 if ($mem$$index < 8) {
2481 emit_opcode(cbuf, Assembler::REX_RB);
2482 } else {
2483 emit_opcode(cbuf, Assembler::REX_RXB);
2484 }
2485 }
2486 }
2487 %}
2488
2489 enc_class REX_reg_mem_wide(rRegL reg, memory mem)
2490 %{
2491 if ($reg$$reg < 8) {
2492 if ($mem$$base < 8) {
2493 if ($mem$$index < 8) {
2494 emit_opcode(cbuf, Assembler::REX_W);
2495 } else {
2496 emit_opcode(cbuf, Assembler::REX_WX);
2497 }
2498 } else {
2499 if ($mem$$index < 8) {
2500 emit_opcode(cbuf, Assembler::REX_WB);
2501 } else {
2502 emit_opcode(cbuf, Assembler::REX_WXB);
2503 }
2504 }
2505 } else {
2506 if ($mem$$base < 8) {
2507 if ($mem$$index < 8) {
2508 emit_opcode(cbuf, Assembler::REX_WR);
2509 } else {
2510 emit_opcode(cbuf, Assembler::REX_WRX);
2511 }
2512 } else {
2513 if ($mem$$index < 8) {
2514 emit_opcode(cbuf, Assembler::REX_WRB);
2515 } else {
2516 emit_opcode(cbuf, Assembler::REX_WRXB);
2517 }
2518 }
2519 }
2520 %}
2521
2522 enc_class reg_mem(rRegI ereg, memory mem)
2523 %{
2524 // High registers handle in encode_RegMem
2525 int reg = $ereg$$reg;
2526 int base = $mem$$base;
2527 int index = $mem$$index;
2528 int scale = $mem$$scale;
2529 int disp = $mem$$disp;
2530 relocInfo::relocType disp_reloc = $mem->disp_reloc();
2531
2532 encode_RegMem(cbuf, reg, base, index, scale, disp, disp_reloc);
2533 %}
2534
2535 enc_class RM_opc_mem(immI rm_opcode, memory mem)
2536 %{
2537 int rm_byte_opcode = $rm_opcode$$constant;
2538
2539 // High registers handle in encode_RegMem
2540 int base = $mem$$base;
2541 int index = $mem$$index;
2542 int scale = $mem$$scale;
2543 int displace = $mem$$disp;
2544
2545 relocInfo::relocType disp_reloc = $mem->disp_reloc(); // disp-as-oop when
2546 // working with static
2547 // globals
2548 encode_RegMem(cbuf, rm_byte_opcode, base, index, scale, displace,
2549 disp_reloc);
2550 %}
2551
2552 enc_class reg_lea(rRegI dst, rRegI src0, immI src1)
2553 %{
2554 int reg_encoding = $dst$$reg;
2555 int base = $src0$$reg; // 0xFFFFFFFF indicates no base
2556 int index = 0x04; // 0x04 indicates no index
2557 int scale = 0x00; // 0x00 indicates no scale
2558 int displace = $src1$$constant; // 0x00 indicates no displacement
2559 relocInfo::relocType disp_reloc = relocInfo::none;
2560 encode_RegMem(cbuf, reg_encoding, base, index, scale, displace,
2561 disp_reloc);
2562 %}
2563
2564 enc_class neg_reg(rRegI dst)
2565 %{
2566 int dstenc = $dst$$reg;
2567 if (dstenc >= 8) {
2568 emit_opcode(cbuf, Assembler::REX_B);
2569 dstenc -= 8;
2570 }
2571 // NEG $dst
2572 emit_opcode(cbuf, 0xF7);
2573 emit_rm(cbuf, 0x3, 0x03, dstenc);
2574 %}
2575
2576 enc_class neg_reg_wide(rRegI dst)
2577 %{
2578 int dstenc = $dst$$reg;
2579 if (dstenc < 8) {
2580 emit_opcode(cbuf, Assembler::REX_W);
2581 } else {
2582 emit_opcode(cbuf, Assembler::REX_WB);
2583 dstenc -= 8;
2584 }
2585 // NEG $dst
2586 emit_opcode(cbuf, 0xF7);
2587 emit_rm(cbuf, 0x3, 0x03, dstenc);
2588 %}
2589
2590 enc_class setLT_reg(rRegI dst)
2591 %{
2592 int dstenc = $dst$$reg;
2593 if (dstenc >= 8) {
2594 emit_opcode(cbuf, Assembler::REX_B);
2595 dstenc -= 8;
2596 } else if (dstenc >= 4) {
2597 emit_opcode(cbuf, Assembler::REX);
2598 }
2599 // SETLT $dst
2600 emit_opcode(cbuf, 0x0F);
2601 emit_opcode(cbuf, 0x9C);
2602 emit_rm(cbuf, 0x3, 0x0, dstenc);
2603 %}
2604
2605 enc_class setNZ_reg(rRegI dst)
2606 %{
2607 int dstenc = $dst$$reg;
2608 if (dstenc >= 8) {
2609 emit_opcode(cbuf, Assembler::REX_B);
2610 dstenc -= 8;
2611 } else if (dstenc >= 4) {
2612 emit_opcode(cbuf, Assembler::REX);
2613 }
2614 // SETNZ $dst
2615 emit_opcode(cbuf, 0x0F);
2616 emit_opcode(cbuf, 0x95);
2617 emit_rm(cbuf, 0x3, 0x0, dstenc);
2618 %}
2619
2620
2621 // Compare the lonogs and set -1, 0, or 1 into dst
2622 enc_class cmpl3_flag(rRegL src1, rRegL src2, rRegI dst)
2623 %{
2624 int src1enc = $src1$$reg;
2625 int src2enc = $src2$$reg;
2626 int dstenc = $dst$$reg;
2627
2628 // cmpq $src1, $src2
2629 if (src1enc < 8) {
2630 if (src2enc < 8) {
2631 emit_opcode(cbuf, Assembler::REX_W);
2632 } else {
2633 emit_opcode(cbuf, Assembler::REX_WB);
2634 }
2635 } else {
2636 if (src2enc < 8) {
2637 emit_opcode(cbuf, Assembler::REX_WR);
2638 } else {
2639 emit_opcode(cbuf, Assembler::REX_WRB);
2640 }
2641 }
2642 emit_opcode(cbuf, 0x3B);
2643 emit_rm(cbuf, 0x3, src1enc & 7, src2enc & 7);
2644
2645 // movl $dst, -1
2646 if (dstenc >= 8) {
2647 emit_opcode(cbuf, Assembler::REX_B);
2648 }
2649 emit_opcode(cbuf, 0xB8 | (dstenc & 7));
2650 emit_d32(cbuf, -1);
2651
2652 // jl,s done
2653 emit_opcode(cbuf, 0x7C);
2654 emit_d8(cbuf, dstenc < 4 ? 0x06 : 0x08);
2655
2656 // setne $dst
2657 if (dstenc >= 4) {
2658 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_B);
2659 }
2660 emit_opcode(cbuf, 0x0F);
2661 emit_opcode(cbuf, 0x95);
2662 emit_opcode(cbuf, 0xC0 | (dstenc & 7));
2663
2664 // movzbl $dst, $dst
2665 if (dstenc >= 4) {
2666 emit_opcode(cbuf, dstenc < 8 ? Assembler::REX : Assembler::REX_RB);
2667 }
2668 emit_opcode(cbuf, 0x0F);
2669 emit_opcode(cbuf, 0xB6);
2670 emit_rm(cbuf, 0x3, dstenc & 7, dstenc & 7);
2671 %}
2672
2673 enc_class Push_ResultXD(regD dst) %{
2674 MacroAssembler _masm(&cbuf);
2675 __ fstp_d(Address(rsp, 0));
2676 __ movdbl($dst$$XMMRegister, Address(rsp, 0));
2677 __ addptr(rsp, 8);
2678 %}
2679
2680 enc_class Push_SrcXD(regD src) %{
2681 MacroAssembler _masm(&cbuf);
2682 __ subptr(rsp, 8);
2683 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
2684 __ fld_d(Address(rsp, 0));
2685 %}
2686
2687
2688 enc_class enc_rethrow()
2689 %{
2690 cbuf.set_insts_mark();
2691 emit_opcode(cbuf, 0xE9); // jmp entry
2692 emit_d32_reloc(cbuf,
2693 (int) (OptoRuntime::rethrow_stub() - cbuf.insts_end() - 4),
2694 runtime_call_Relocation::spec(),
2695 RELOC_DISP32);
2696 %}
2697
2698 %}
2699
2700
2701
2702 //----------FRAME--------------------------------------------------------------
2703 // Definition of frame structure and management information.
2704 //
2705 // S T A C K L A Y O U T Allocators stack-slot number
2706 // | (to get allocators register number
2707 // G Owned by | | v add OptoReg::stack0())
2708 // r CALLER | |
2709 // o | +--------+ pad to even-align allocators stack-slot
2710 // w V | pad0 | numbers; owned by CALLER
2711 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
2712 // h ^ | in | 5
2713 // | | args | 4 Holes in incoming args owned by SELF
2714 // | | | | 3
2715 // | | +--------+
2716 // V | | old out| Empty on Intel, window on Sparc
2717 // | old |preserve| Must be even aligned.
2718 // | SP-+--------+----> Matcher::_old_SP, even aligned
2719 // | | in | 3 area for Intel ret address
2720 // Owned by |preserve| Empty on Sparc.
2721 // SELF +--------+
2722 // | | pad2 | 2 pad to align old SP
2723 // | +--------+ 1
2724 // | | locks | 0
2725 // | +--------+----> OptoReg::stack0(), even aligned
2726 // | | pad1 | 11 pad to align new SP
2727 // | +--------+
2728 // | | | 10
2729 // | | spills | 9 spills
2730 // V | | 8 (pad0 slot for callee)
2731 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
2732 // ^ | out | 7
2733 // | | args | 6 Holes in outgoing args owned by CALLEE
2734 // Owned by +--------+
2735 // CALLEE | new out| 6 Empty on Intel, window on Sparc
2736 // | new |preserve| Must be even-aligned.
2737 // | SP-+--------+----> Matcher::_new_SP, even aligned
2738 // | | |
2739 //
2740 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
2741 // known from SELF's arguments and the Java calling convention.
2742 // Region 6-7 is determined per call site.
2743 // Note 2: If the calling convention leaves holes in the incoming argument
2744 // area, those holes are owned by SELF. Holes in the outgoing area
2745 // are owned by the CALLEE. Holes should not be nessecary in the
2746 // incoming area, as the Java calling convention is completely under
2747 // the control of the AD file. Doubles can be sorted and packed to
2748 // avoid holes. Holes in the outgoing arguments may be nessecary for
2749 // varargs C calling conventions.
2750 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
2751 // even aligned with pad0 as needed.
2752 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
2753 // region 6-11 is even aligned; it may be padded out more so that
2754 // the region from SP to FP meets the minimum stack alignment.
2755 // Note 4: For I2C adapters, the incoming FP may not meet the minimum stack
2756 // alignment. Region 11, pad1, may be dynamically extended so that
2757 // SP meets the minimum alignment.
2758
2759 frame
2760 %{
2761 // What direction does stack grow in (assumed to be same for C & Java)
2762 stack_direction(TOWARDS_LOW);
2763
2764 // These three registers define part of the calling convention
2765 // between compiled code and the interpreter.
2766 inline_cache_reg(RAX); // Inline Cache Register
2767 interpreter_method_oop_reg(RBX); // Method Oop Register when
2768 // calling interpreter
2769
2770 // Optional: name the operand used by cisc-spilling to access
2771 // [stack_pointer + offset]
2772 cisc_spilling_operand_name(indOffset32);
2773
2774 // Number of stack slots consumed by locking an object
2775 sync_stack_slots(2);
2776
2777 // Compiled code's Frame Pointer
2778 frame_pointer(RSP);
2779
2780 // Interpreter stores its frame pointer in a register which is
2781 // stored to the stack by I2CAdaptors.
2782 // I2CAdaptors convert from interpreted java to compiled java.
2783 interpreter_frame_pointer(RBP);
2784
2785 // Stack alignment requirement
2786 stack_alignment(StackAlignmentInBytes); // Alignment size in bytes (128-bit -> 16 bytes)
2787
2788 // Number of stack slots between incoming argument block and the start of
2789 // a new frame. The PROLOG must add this many slots to the stack. The
2790 // EPILOG must remove this many slots. amd64 needs two slots for
2791 // return address.
2792 in_preserve_stack_slots(4 + 2 * VerifyStackAtCalls);
2793
2794 // Number of outgoing stack slots killed above the out_preserve_stack_slots
2795 // for calls to C. Supports the var-args backing area for register parms.
2796 varargs_C_out_slots_killed(frame::arg_reg_save_area_bytes/BytesPerInt);
2797
2798 // The after-PROLOG location of the return address. Location of
2799 // return address specifies a type (REG or STACK) and a number
2800 // representing the register number (i.e. - use a register name) or
2801 // stack slot.
2802 // Ret Addr is on stack in slot 0 if no locks or verification or alignment.
2803 // Otherwise, it is above the locks and verification slot and alignment word
2804 return_addr(STACK - 2 +
2805 round_to((Compile::current()->in_preserve_stack_slots() +
2806 Compile::current()->fixed_slots()),
2807 stack_alignment_in_slots()));
2808
2809 // Body of function which returns an integer array locating
2810 // arguments either in registers or in stack slots. Passed an array
2811 // of ideal registers called "sig" and a "length" count. Stack-slot
2812 // offsets are based on outgoing arguments, i.e. a CALLER setting up
2813 // arguments for a CALLEE. Incoming stack arguments are
2814 // automatically biased by the preserve_stack_slots field above.
2815
2816 calling_convention
2817 %{
2818 // No difference between ingoing/outgoing just pass false
2819 SharedRuntime::java_calling_convention(sig_bt, regs, length, false);
2820 %}
2821
2822 c_calling_convention
2823 %{
2824 // This is obviously always outgoing
2825 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
2826 %}
2827
2828 // Location of compiled Java return values. Same as C for now.
2829 return_value
2830 %{
2831 assert(ideal_reg >= Op_RegI && ideal_reg <= Op_RegL,
2832 "only return normal values");
2833
2834 static const int lo[Op_RegL + 1] = {
2835 0,
2836 0,
2837 RAX_num, // Op_RegN
2838 RAX_num, // Op_RegI
2839 RAX_num, // Op_RegP
2840 XMM0_num, // Op_RegF
2841 XMM0_num, // Op_RegD
2842 RAX_num // Op_RegL
2843 };
2844 static const int hi[Op_RegL + 1] = {
2845 0,
2846 0,
2847 OptoReg::Bad, // Op_RegN
2848 OptoReg::Bad, // Op_RegI
2849 RAX_H_num, // Op_RegP
2850 OptoReg::Bad, // Op_RegF
2851 XMM0b_num, // Op_RegD
2852 RAX_H_num // Op_RegL
2853 };
2854 // Excluded flags and vector registers.
2855 assert(ARRAY_SIZE(hi) == _last_machine_leaf - 6, "missing type");
2856 return OptoRegPair(hi[ideal_reg], lo[ideal_reg]);
2857 %}
2858 %}
2859
2860 //----------ATTRIBUTES---------------------------------------------------------
2861 //----------Operand Attributes-------------------------------------------------
2862 op_attrib op_cost(0); // Required cost attribute
2863
2864 //----------Instruction Attributes---------------------------------------------
2865 ins_attrib ins_cost(100); // Required cost attribute
2866 ins_attrib ins_size(8); // Required size attribute (in bits)
2867 ins_attrib ins_short_branch(0); // Required flag: is this instruction
2868 // a non-matching short branch variant
2869 // of some long branch?
2870 ins_attrib ins_alignment(1); // Required alignment attribute (must
2871 // be a power of 2) specifies the
2872 // alignment that some part of the
2873 // instruction (not necessarily the
2874 // start) requires. If > 1, a
2875 // compute_padding() function must be
2876 // provided for the instruction
2877
2878 //----------OPERANDS-----------------------------------------------------------
2879 // Operand definitions must precede instruction definitions for correct parsing
2880 // in the ADLC because operands constitute user defined types which are used in
2881 // instruction definitions.
2882
2883 //----------Simple Operands----------------------------------------------------
2884 // Immediate Operands
2885 // Integer Immediate
2886 operand immI()
2887 %{
2888 match(ConI);
2889
2890 op_cost(10);
2891 format %{ %}
2892 interface(CONST_INTER);
2893 %}
2894
2895 // Constant for test vs zero
2896 operand immI0()
2897 %{
2898 predicate(n->get_int() == 0);
2899 match(ConI);
2900
2901 op_cost(0);
2902 format %{ %}
2903 interface(CONST_INTER);
2904 %}
2905
2906 // Constant for increment
2907 operand immI1()
2908 %{
2909 predicate(n->get_int() == 1);
2910 match(ConI);
2911
2912 op_cost(0);
2913 format %{ %}
2914 interface(CONST_INTER);
2915 %}
2916
2917 // Constant for decrement
2918 operand immI_M1()
2919 %{
2920 predicate(n->get_int() == -1);
2921 match(ConI);
2922
2923 op_cost(0);
2924 format %{ %}
2925 interface(CONST_INTER);
2926 %}
2927
2928 // Valid scale values for addressing modes
2929 operand immI2()
2930 %{
2931 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2932 match(ConI);
2933
2934 format %{ %}
2935 interface(CONST_INTER);
2936 %}
2937
2938 operand immI8()
2939 %{
2940 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2941 match(ConI);
2942
2943 op_cost(5);
2944 format %{ %}
2945 interface(CONST_INTER);
2946 %}
2947
2948 operand immI16()
2949 %{
2950 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2951 match(ConI);
2952
2953 op_cost(10);
2954 format %{ %}
2955 interface(CONST_INTER);
2956 %}
2957
2958 // Int Immediate non-negative
2959 operand immU31()
2960 %{
2961 predicate(n->get_int() >= 0);
2962 match(ConI);
2963
2964 op_cost(0);
2965 format %{ %}
2966 interface(CONST_INTER);
2967 %}
2968
2969 // Constant for long shifts
2970 operand immI_32()
2971 %{
2972 predicate( n->get_int() == 32 );
2973 match(ConI);
2974
2975 op_cost(0);
2976 format %{ %}
2977 interface(CONST_INTER);
2978 %}
2979
2980 // Constant for long shifts
2981 operand immI_64()
2982 %{
2983 predicate( n->get_int() == 64 );
2984 match(ConI);
2985
2986 op_cost(0);
2987 format %{ %}
2988 interface(CONST_INTER);
2989 %}
2990
2991 // Pointer Immediate
2992 operand immP()
2993 %{
2994 match(ConP);
2995
2996 op_cost(10);
2997 format %{ %}
2998 interface(CONST_INTER);
2999 %}
3000
3001 // NULL Pointer Immediate
3002 operand immP0()
3003 %{
3004 predicate(n->get_ptr() == 0);
3005 match(ConP);
3006
3007 op_cost(5);
3008 format %{ %}
3009 interface(CONST_INTER);
3010 %}
3011
3012 // Pointer Immediate
3013 operand immN() %{
3014 match(ConN);
3015
3016 op_cost(10);
3017 format %{ %}
3018 interface(CONST_INTER);
3019 %}
3020
3021 operand immNKlass() %{
3022 match(ConNKlass);
3023
3024 op_cost(10);
3025 format %{ %}
3026 interface(CONST_INTER);
3027 %}
3028
3029 // NULL Pointer Immediate
3030 operand immN0() %{
3031 predicate(n->get_narrowcon() == 0);
3032 match(ConN);
3033
3034 op_cost(5);
3035 format %{ %}
3036 interface(CONST_INTER);
3037 %}
3038
3039 operand immP31()
3040 %{
3041 predicate(n->as_Type()->type()->reloc() == relocInfo::none
3042 && (n->get_ptr() >> 31) == 0);
3043 match(ConP);
3044
3045 op_cost(5);
3046 format %{ %}
3047 interface(CONST_INTER);
3048 %}
3049
3050
3051 // Long Immediate
3052 operand immL()
3053 %{
3054 match(ConL);
3055
3056 op_cost(20);
3057 format %{ %}
3058 interface(CONST_INTER);
3059 %}
3060
3061 // Long Immediate 8-bit
3062 operand immL8()
3063 %{
3064 predicate(-0x80L <= n->get_long() && n->get_long() < 0x80L);
3065 match(ConL);
3066
3067 op_cost(5);
3068 format %{ %}
3069 interface(CONST_INTER);
3070 %}
3071
3072 // Long Immediate 32-bit unsigned
3073 operand immUL32()
3074 %{
3075 predicate(n->get_long() == (unsigned int) (n->get_long()));
3076 match(ConL);
3077
3078 op_cost(10);
3079 format %{ %}
3080 interface(CONST_INTER);
3081 %}
3082
3083 // Long Immediate 32-bit signed
3084 operand immL32()
3085 %{
3086 predicate(n->get_long() == (int) (n->get_long()));
3087 match(ConL);
3088
3089 op_cost(15);
3090 format %{ %}
3091 interface(CONST_INTER);
3092 %}
3093
3094 // Long Immediate zero
3095 operand immL0()
3096 %{
3097 predicate(n->get_long() == 0L);
3098 match(ConL);
3099
3100 op_cost(10);
3101 format %{ %}
3102 interface(CONST_INTER);
3103 %}
3104
3105 // Constant for increment
3106 operand immL1()
3107 %{
3108 predicate(n->get_long() == 1);
3109 match(ConL);
3110
3111 format %{ %}
3112 interface(CONST_INTER);
3113 %}
3114
3115 // Constant for decrement
3116 operand immL_M1()
3117 %{
3118 predicate(n->get_long() == -1);
3119 match(ConL);
3120
3121 format %{ %}
3122 interface(CONST_INTER);
3123 %}
3124
3125 // Long Immediate: the value 10
3126 operand immL10()
3127 %{
3128 predicate(n->get_long() == 10);
3129 match(ConL);
3130
3131 format %{ %}
3132 interface(CONST_INTER);
3133 %}
3134
3135 // Long immediate from 0 to 127.
3136 // Used for a shorter form of long mul by 10.
3137 operand immL_127()
3138 %{
3139 predicate(0 <= n->get_long() && n->get_long() < 0x80);
3140 match(ConL);
3141
3142 op_cost(10);
3143 format %{ %}
3144 interface(CONST_INTER);
3145 %}
3146
3147 // Long Immediate: low 32-bit mask
3148 operand immL_32bits()
3149 %{
3150 predicate(n->get_long() == 0xFFFFFFFFL);
3151 match(ConL);
3152 op_cost(20);
3153
3154 format %{ %}
3155 interface(CONST_INTER);
3156 %}
3157
3158 // Float Immediate zero
3159 operand immF0()
3160 %{
3161 predicate(jint_cast(n->getf()) == 0);
3162 match(ConF);
3163
3164 op_cost(5);
3165 format %{ %}
3166 interface(CONST_INTER);
3167 %}
3168
3169 // Float Immediate
3170 operand immF()
3171 %{
3172 match(ConF);
3173
3174 op_cost(15);
3175 format %{ %}
3176 interface(CONST_INTER);
3177 %}
3178
3179 // Double Immediate zero
3180 operand immD0()
3181 %{
3182 predicate(jlong_cast(n->getd()) == 0);
3183 match(ConD);
3184
3185 op_cost(5);
3186 format %{ %}
3187 interface(CONST_INTER);
3188 %}
3189
3190 // Double Immediate
3191 operand immD()
3192 %{
3193 match(ConD);
3194
3195 op_cost(15);
3196 format %{ %}
3197 interface(CONST_INTER);
3198 %}
3199
3200 // Immediates for special shifts (sign extend)
3201
3202 // Constants for increment
3203 operand immI_16()
3204 %{
3205 predicate(n->get_int() == 16);
3206 match(ConI);
3207
3208 format %{ %}
3209 interface(CONST_INTER);
3210 %}
3211
3212 operand immI_24()
3213 %{
3214 predicate(n->get_int() == 24);
3215 match(ConI);
3216
3217 format %{ %}
3218 interface(CONST_INTER);
3219 %}
3220
3221 // Constant for byte-wide masking
3222 operand immI_255()
3223 %{
3224 predicate(n->get_int() == 255);
3225 match(ConI);
3226
3227 format %{ %}
3228 interface(CONST_INTER);
3229 %}
3230
3231 // Constant for short-wide masking
3232 operand immI_65535()
3233 %{
3234 predicate(n->get_int() == 65535);
3235 match(ConI);
3236
3237 format %{ %}
3238 interface(CONST_INTER);
3239 %}
3240
3241 // Constant for byte-wide masking
3242 operand immL_255()
3243 %{
3244 predicate(n->get_long() == 255);
3245 match(ConL);
3246
3247 format %{ %}
3248 interface(CONST_INTER);
3249 %}
3250
3251 // Constant for short-wide masking
3252 operand immL_65535()
3253 %{
3254 predicate(n->get_long() == 65535);
3255 match(ConL);
3256
3257 format %{ %}
3258 interface(CONST_INTER);
3259 %}
3260
3261 // Register Operands
3262 // Integer Register
3263 operand rRegI()
3264 %{
3265 constraint(ALLOC_IN_RC(int_reg));
3266 match(RegI);
3267
3268 match(rax_RegI);
3269 match(rbx_RegI);
3270 match(rcx_RegI);
3271 match(rdx_RegI);
3272 match(rdi_RegI);
3273
3274 format %{ %}
3275 interface(REG_INTER);
3276 %}
3277
3278 // Special Registers
3279 operand rax_RegI()
3280 %{
3281 constraint(ALLOC_IN_RC(int_rax_reg));
3282 match(RegI);
3283 match(rRegI);
3284
3285 format %{ "RAX" %}
3286 interface(REG_INTER);
3287 %}
3288
3289 // Special Registers
3290 operand rbx_RegI()
3291 %{
3292 constraint(ALLOC_IN_RC(int_rbx_reg));
3293 match(RegI);
3294 match(rRegI);
3295
3296 format %{ "RBX" %}
3297 interface(REG_INTER);
3298 %}
3299
3300 operand rcx_RegI()
3301 %{
3302 constraint(ALLOC_IN_RC(int_rcx_reg));
3303 match(RegI);
3304 match(rRegI);
3305
3306 format %{ "RCX" %}
3307 interface(REG_INTER);
3308 %}
3309
3310 operand rdx_RegI()
3311 %{
3312 constraint(ALLOC_IN_RC(int_rdx_reg));
3313 match(RegI);
3314 match(rRegI);
3315
3316 format %{ "RDX" %}
3317 interface(REG_INTER);
3318 %}
3319
3320 operand rdi_RegI()
3321 %{
3322 constraint(ALLOC_IN_RC(int_rdi_reg));
3323 match(RegI);
3324 match(rRegI);
3325
3326 format %{ "RDI" %}
3327 interface(REG_INTER);
3328 %}
3329
3330 operand no_rcx_RegI()
3331 %{
3332 constraint(ALLOC_IN_RC(int_no_rcx_reg));
3333 match(RegI);
3334 match(rax_RegI);
3335 match(rbx_RegI);
3336 match(rdx_RegI);
3337 match(rdi_RegI);
3338
3339 format %{ %}
3340 interface(REG_INTER);
3341 %}
3342
3343 operand no_rax_rdx_RegI()
3344 %{
3345 constraint(ALLOC_IN_RC(int_no_rax_rdx_reg));
3346 match(RegI);
3347 match(rbx_RegI);
3348 match(rcx_RegI);
3349 match(rdi_RegI);
3350
3351 format %{ %}
3352 interface(REG_INTER);
3353 %}
3354
3355 // Pointer Register
3356 operand any_RegP()
3357 %{
3358 constraint(ALLOC_IN_RC(any_reg));
3359 match(RegP);
3360 match(rax_RegP);
3361 match(rbx_RegP);
3362 match(rdi_RegP);
3363 match(rsi_RegP);
3364 match(rbp_RegP);
3365 match(r15_RegP);
3366 match(rRegP);
3367
3368 format %{ %}
3369 interface(REG_INTER);
3370 %}
3371
3372 operand rRegP()
3373 %{
3374 constraint(ALLOC_IN_RC(ptr_reg));
3375 match(RegP);
3376 match(rax_RegP);
3377 match(rbx_RegP);
3378 match(rdi_RegP);
3379 match(rsi_RegP);
3380 match(rbp_RegP); // See Q&A below about
3381 match(r15_RegP); // r15_RegP and rbp_RegP.
3382
3383 format %{ %}
3384 interface(REG_INTER);
3385 %}
3386
3387 operand rRegN() %{
3388 constraint(ALLOC_IN_RC(int_reg));
3389 match(RegN);
3390
3391 format %{ %}
3392 interface(REG_INTER);
3393 %}
3394
3395 // Question: Why is r15_RegP (the read-only TLS register) a match for rRegP?
3396 // Answer: Operand match rules govern the DFA as it processes instruction inputs.
3397 // It's fine for an instruction input that expects rRegP to match a r15_RegP.
3398 // The output of an instruction is controlled by the allocator, which respects
3399 // register class masks, not match rules. Unless an instruction mentions
3400 // r15_RegP or any_RegP explicitly as its output, r15 will not be considered
3401 // by the allocator as an input.
3402 // The same logic applies to rbp_RegP being a match for rRegP: If PreserveFramePointer==true,
3403 // the RBP is used as a proper frame pointer and is not included in ptr_reg. As a
3404 // result, RBP is not included in the output of the instruction either.
3405
3406 operand no_rax_RegP()
3407 %{
3408 constraint(ALLOC_IN_RC(ptr_no_rax_reg));
3409 match(RegP);
3410 match(rbx_RegP);
3411 match(rsi_RegP);
3412 match(rdi_RegP);
3413
3414 format %{ %}
3415 interface(REG_INTER);
3416 %}
3417
3418 // This operand is not allowed to use RBP even if
3419 // RBP is not used to hold the frame pointer.
3420 operand no_rbp_RegP()
3421 %{
3422 constraint(ALLOC_IN_RC(ptr_reg_no_rbp));
3423 match(RegP);
3424 match(rbx_RegP);
3425 match(rsi_RegP);
3426 match(rdi_RegP);
3427
3428 format %{ %}
3429 interface(REG_INTER);
3430 %}
3431
3432 operand no_rax_rbx_RegP()
3433 %{
3434 constraint(ALLOC_IN_RC(ptr_no_rax_rbx_reg));
3435 match(RegP);
3436 match(rsi_RegP);
3437 match(rdi_RegP);
3438
3439 format %{ %}
3440 interface(REG_INTER);
3441 %}
3442
3443 // Special Registers
3444 // Return a pointer value
3445 operand rax_RegP()
3446 %{
3447 constraint(ALLOC_IN_RC(ptr_rax_reg));
3448 match(RegP);
3449 match(rRegP);
3450
3451 format %{ %}
3452 interface(REG_INTER);
3453 %}
3454
3455 // Special Registers
3456 // Return a compressed pointer value
3457 operand rax_RegN()
3458 %{
3459 constraint(ALLOC_IN_RC(int_rax_reg));
3460 match(RegN);
3461 match(rRegN);
3462
3463 format %{ %}
3464 interface(REG_INTER);
3465 %}
3466
3467 // Used in AtomicAdd
3468 operand rbx_RegP()
3469 %{
3470 constraint(ALLOC_IN_RC(ptr_rbx_reg));
3471 match(RegP);
3472 match(rRegP);
3473
3474 format %{ %}
3475 interface(REG_INTER);
3476 %}
3477
3478 operand rsi_RegP()
3479 %{
3480 constraint(ALLOC_IN_RC(ptr_rsi_reg));
3481 match(RegP);
3482 match(rRegP);
3483
3484 format %{ %}
3485 interface(REG_INTER);
3486 %}
3487
3488 // Used in rep stosq
3489 operand rdi_RegP()
3490 %{
3491 constraint(ALLOC_IN_RC(ptr_rdi_reg));
3492 match(RegP);
3493 match(rRegP);
3494
3495 format %{ %}
3496 interface(REG_INTER);
3497 %}
3498
3499 operand r15_RegP()
3500 %{
3501 constraint(ALLOC_IN_RC(ptr_r15_reg));
3502 match(RegP);
3503 match(rRegP);
3504
3505 format %{ %}
3506 interface(REG_INTER);
3507 %}
3508
3509 operand rRegL()
3510 %{
3511 constraint(ALLOC_IN_RC(long_reg));
3512 match(RegL);
3513 match(rax_RegL);
3514 match(rdx_RegL);
3515
3516 format %{ %}
3517 interface(REG_INTER);
3518 %}
3519
3520 // Special Registers
3521 operand no_rax_rdx_RegL()
3522 %{
3523 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3524 match(RegL);
3525 match(rRegL);
3526
3527 format %{ %}
3528 interface(REG_INTER);
3529 %}
3530
3531 operand no_rax_RegL()
3532 %{
3533 constraint(ALLOC_IN_RC(long_no_rax_rdx_reg));
3534 match(RegL);
3535 match(rRegL);
3536 match(rdx_RegL);
3537
3538 format %{ %}
3539 interface(REG_INTER);
3540 %}
3541
3542 operand no_rcx_RegL()
3543 %{
3544 constraint(ALLOC_IN_RC(long_no_rcx_reg));
3545 match(RegL);
3546 match(rRegL);
3547
3548 format %{ %}
3549 interface(REG_INTER);
3550 %}
3551
3552 operand rax_RegL()
3553 %{
3554 constraint(ALLOC_IN_RC(long_rax_reg));
3555 match(RegL);
3556 match(rRegL);
3557
3558 format %{ "RAX" %}
3559 interface(REG_INTER);
3560 %}
3561
3562 operand rcx_RegL()
3563 %{
3564 constraint(ALLOC_IN_RC(long_rcx_reg));
3565 match(RegL);
3566 match(rRegL);
3567
3568 format %{ %}
3569 interface(REG_INTER);
3570 %}
3571
3572 operand rdx_RegL()
3573 %{
3574 constraint(ALLOC_IN_RC(long_rdx_reg));
3575 match(RegL);
3576 match(rRegL);
3577
3578 format %{ %}
3579 interface(REG_INTER);
3580 %}
3581
3582 // Flags register, used as output of compare instructions
3583 operand rFlagsReg()
3584 %{
3585 constraint(ALLOC_IN_RC(int_flags));
3586 match(RegFlags);
3587
3588 format %{ "RFLAGS" %}
3589 interface(REG_INTER);
3590 %}
3591
3592 // Flags register, used as output of FLOATING POINT compare instructions
3593 operand rFlagsRegU()
3594 %{
3595 constraint(ALLOC_IN_RC(int_flags));
3596 match(RegFlags);
3597
3598 format %{ "RFLAGS_U" %}
3599 interface(REG_INTER);
3600 %}
3601
3602 operand rFlagsRegUCF() %{
3603 constraint(ALLOC_IN_RC(int_flags));
3604 match(RegFlags);
3605 predicate(false);
3606
3607 format %{ "RFLAGS_U_CF" %}
3608 interface(REG_INTER);
3609 %}
3610
3611 // Float register operands
3612 operand regF() %{
3613 constraint(ALLOC_IN_RC(float_reg));
3614 match(RegF);
3615
3616 format %{ %}
3617 interface(REG_INTER);
3618 %}
3619
3620 // Double register operands
3621 operand regD() %{
3622 constraint(ALLOC_IN_RC(double_reg));
3623 match(RegD);
3624
3625 format %{ %}
3626 interface(REG_INTER);
3627 %}
3628
3629 // Vectors
3630 operand vecS() %{
3631 constraint(ALLOC_IN_RC(vectors_reg));
3632 match(VecS);
3633
3634 format %{ %}
3635 interface(REG_INTER);
3636 %}
3637
3638 operand vecD() %{
3639 constraint(ALLOC_IN_RC(vectord_reg));
3640 match(VecD);
3641
3642 format %{ %}
3643 interface(REG_INTER);
3644 %}
3645
3646 operand vecX() %{
3647 constraint(ALLOC_IN_RC(vectorx_reg));
3648 match(VecX);
3649
3650 format %{ %}
3651 interface(REG_INTER);
3652 %}
3653
3654 operand vecY() %{
3655 constraint(ALLOC_IN_RC(vectory_reg));
3656 match(VecY);
3657
3658 format %{ %}
3659 interface(REG_INTER);
3660 %}
3661
3662 //----------Memory Operands----------------------------------------------------
3663 // Direct Memory Operand
3664 // operand direct(immP addr)
3665 // %{
3666 // match(addr);
3667
3668 // format %{ "[$addr]" %}
3669 // interface(MEMORY_INTER) %{
3670 // base(0xFFFFFFFF);
3671 // index(0x4);
3672 // scale(0x0);
3673 // disp($addr);
3674 // %}
3675 // %}
3676
3677 // Indirect Memory Operand
3678 operand indirect(any_RegP reg)
3679 %{
3680 constraint(ALLOC_IN_RC(ptr_reg));
3681 match(reg);
3682
3683 format %{ "[$reg]" %}
3684 interface(MEMORY_INTER) %{
3685 base($reg);
3686 index(0x4);
3687 scale(0x0);
3688 disp(0x0);
3689 %}
3690 %}
3691
3692 // Indirect Memory Plus Short Offset Operand
3693 operand indOffset8(any_RegP reg, immL8 off)
3694 %{
3695 constraint(ALLOC_IN_RC(ptr_reg));
3696 match(AddP reg off);
3697
3698 format %{ "[$reg + $off (8-bit)]" %}
3699 interface(MEMORY_INTER) %{
3700 base($reg);
3701 index(0x4);
3702 scale(0x0);
3703 disp($off);
3704 %}
3705 %}
3706
3707 // Indirect Memory Plus Long Offset Operand
3708 operand indOffset32(any_RegP reg, immL32 off)
3709 %{
3710 constraint(ALLOC_IN_RC(ptr_reg));
3711 match(AddP reg off);
3712
3713 format %{ "[$reg + $off (32-bit)]" %}
3714 interface(MEMORY_INTER) %{
3715 base($reg);
3716 index(0x4);
3717 scale(0x0);
3718 disp($off);
3719 %}
3720 %}
3721
3722 // Indirect Memory Plus Index Register Plus Offset Operand
3723 operand indIndexOffset(any_RegP reg, rRegL lreg, immL32 off)
3724 %{
3725 constraint(ALLOC_IN_RC(ptr_reg));
3726 match(AddP (AddP reg lreg) off);
3727
3728 op_cost(10);
3729 format %{"[$reg + $off + $lreg]" %}
3730 interface(MEMORY_INTER) %{
3731 base($reg);
3732 index($lreg);
3733 scale(0x0);
3734 disp($off);
3735 %}
3736 %}
3737
3738 // Indirect Memory Plus Index Register Plus Offset Operand
3739 operand indIndex(any_RegP reg, rRegL lreg)
3740 %{
3741 constraint(ALLOC_IN_RC(ptr_reg));
3742 match(AddP reg lreg);
3743
3744 op_cost(10);
3745 format %{"[$reg + $lreg]" %}
3746 interface(MEMORY_INTER) %{
3747 base($reg);
3748 index($lreg);
3749 scale(0x0);
3750 disp(0x0);
3751 %}
3752 %}
3753
3754 // Indirect Memory Times Scale Plus Index Register
3755 operand indIndexScale(any_RegP reg, rRegL lreg, immI2 scale)
3756 %{
3757 constraint(ALLOC_IN_RC(ptr_reg));
3758 match(AddP reg (LShiftL lreg scale));
3759
3760 op_cost(10);
3761 format %{"[$reg + $lreg << $scale]" %}
3762 interface(MEMORY_INTER) %{
3763 base($reg);
3764 index($lreg);
3765 scale($scale);
3766 disp(0x0);
3767 %}
3768 %}
3769
3770 operand indPosIndexScale(any_RegP reg, rRegI idx, immI2 scale)
3771 %{
3772 constraint(ALLOC_IN_RC(ptr_reg));
3773 predicate(n->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3774 match(AddP reg (LShiftL (ConvI2L idx) scale));
3775
3776 op_cost(10);
3777 format %{"[$reg + pos $idx << $scale]" %}
3778 interface(MEMORY_INTER) %{
3779 base($reg);
3780 index($idx);
3781 scale($scale);
3782 disp(0x0);
3783 %}
3784 %}
3785
3786 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3787 operand indIndexScaleOffset(any_RegP reg, immL32 off, rRegL lreg, immI2 scale)
3788 %{
3789 constraint(ALLOC_IN_RC(ptr_reg));
3790 match(AddP (AddP reg (LShiftL lreg scale)) off);
3791
3792 op_cost(10);
3793 format %{"[$reg + $off + $lreg << $scale]" %}
3794 interface(MEMORY_INTER) %{
3795 base($reg);
3796 index($lreg);
3797 scale($scale);
3798 disp($off);
3799 %}
3800 %}
3801
3802 // Indirect Memory Plus Positive Index Register Plus Offset Operand
3803 operand indPosIndexOffset(any_RegP reg, immL32 off, rRegI idx)
3804 %{
3805 constraint(ALLOC_IN_RC(ptr_reg));
3806 predicate(n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3807 match(AddP (AddP reg (ConvI2L idx)) off);
3808
3809 op_cost(10);
3810 format %{"[$reg + $off + $idx]" %}
3811 interface(MEMORY_INTER) %{
3812 base($reg);
3813 index($idx);
3814 scale(0x0);
3815 disp($off);
3816 %}
3817 %}
3818
3819 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3820 operand indPosIndexScaleOffset(any_RegP reg, immL32 off, rRegI idx, immI2 scale)
3821 %{
3822 constraint(ALLOC_IN_RC(ptr_reg));
3823 predicate(n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3824 match(AddP (AddP reg (LShiftL (ConvI2L idx) scale)) off);
3825
3826 op_cost(10);
3827 format %{"[$reg + $off + $idx << $scale]" %}
3828 interface(MEMORY_INTER) %{
3829 base($reg);
3830 index($idx);
3831 scale($scale);
3832 disp($off);
3833 %}
3834 %}
3835
3836 // Indirect Narrow Oop Plus Offset Operand
3837 // Note: x86 architecture doesn't support "scale * index + offset" without a base
3838 // we can't free r12 even with Universe::narrow_oop_base() == NULL.
3839 operand indCompressedOopOffset(rRegN reg, immL32 off) %{
3840 predicate(UseCompressedOops && (Universe::narrow_oop_shift() == Address::times_8));
3841 constraint(ALLOC_IN_RC(ptr_reg));
3842 match(AddP (DecodeN reg) off);
3843
3844 op_cost(10);
3845 format %{"[R12 + $reg << 3 + $off] (compressed oop addressing)" %}
3846 interface(MEMORY_INTER) %{
3847 base(0xc); // R12
3848 index($reg);
3849 scale(0x3);
3850 disp($off);
3851 %}
3852 %}
3853
3854 // Indirect Memory Operand
3855 operand indirectNarrow(rRegN reg)
3856 %{
3857 predicate(Universe::narrow_oop_shift() == 0);
3858 constraint(ALLOC_IN_RC(ptr_reg));
3859 match(DecodeN reg);
3860
3861 format %{ "[$reg]" %}
3862 interface(MEMORY_INTER) %{
3863 base($reg);
3864 index(0x4);
3865 scale(0x0);
3866 disp(0x0);
3867 %}
3868 %}
3869
3870 // Indirect Memory Plus Short Offset Operand
3871 operand indOffset8Narrow(rRegN reg, immL8 off)
3872 %{
3873 predicate(Universe::narrow_oop_shift() == 0);
3874 constraint(ALLOC_IN_RC(ptr_reg));
3875 match(AddP (DecodeN reg) off);
3876
3877 format %{ "[$reg + $off (8-bit)]" %}
3878 interface(MEMORY_INTER) %{
3879 base($reg);
3880 index(0x4);
3881 scale(0x0);
3882 disp($off);
3883 %}
3884 %}
3885
3886 // Indirect Memory Plus Long Offset Operand
3887 operand indOffset32Narrow(rRegN reg, immL32 off)
3888 %{
3889 predicate(Universe::narrow_oop_shift() == 0);
3890 constraint(ALLOC_IN_RC(ptr_reg));
3891 match(AddP (DecodeN reg) off);
3892
3893 format %{ "[$reg + $off (32-bit)]" %}
3894 interface(MEMORY_INTER) %{
3895 base($reg);
3896 index(0x4);
3897 scale(0x0);
3898 disp($off);
3899 %}
3900 %}
3901
3902 // Indirect Memory Plus Index Register Plus Offset Operand
3903 operand indIndexOffsetNarrow(rRegN reg, rRegL lreg, immL32 off)
3904 %{
3905 predicate(Universe::narrow_oop_shift() == 0);
3906 constraint(ALLOC_IN_RC(ptr_reg));
3907 match(AddP (AddP (DecodeN reg) lreg) off);
3908
3909 op_cost(10);
3910 format %{"[$reg + $off + $lreg]" %}
3911 interface(MEMORY_INTER) %{
3912 base($reg);
3913 index($lreg);
3914 scale(0x0);
3915 disp($off);
3916 %}
3917 %}
3918
3919 // Indirect Memory Plus Index Register Plus Offset Operand
3920 operand indIndexNarrow(rRegN reg, rRegL lreg)
3921 %{
3922 predicate(Universe::narrow_oop_shift() == 0);
3923 constraint(ALLOC_IN_RC(ptr_reg));
3924 match(AddP (DecodeN reg) lreg);
3925
3926 op_cost(10);
3927 format %{"[$reg + $lreg]" %}
3928 interface(MEMORY_INTER) %{
3929 base($reg);
3930 index($lreg);
3931 scale(0x0);
3932 disp(0x0);
3933 %}
3934 %}
3935
3936 // Indirect Memory Times Scale Plus Index Register
3937 operand indIndexScaleNarrow(rRegN reg, rRegL lreg, immI2 scale)
3938 %{
3939 predicate(Universe::narrow_oop_shift() == 0);
3940 constraint(ALLOC_IN_RC(ptr_reg));
3941 match(AddP (DecodeN reg) (LShiftL lreg scale));
3942
3943 op_cost(10);
3944 format %{"[$reg + $lreg << $scale]" %}
3945 interface(MEMORY_INTER) %{
3946 base($reg);
3947 index($lreg);
3948 scale($scale);
3949 disp(0x0);
3950 %}
3951 %}
3952
3953 // Indirect Memory Times Scale Plus Index Register Plus Offset Operand
3954 operand indIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegL lreg, immI2 scale)
3955 %{
3956 predicate(Universe::narrow_oop_shift() == 0);
3957 constraint(ALLOC_IN_RC(ptr_reg));
3958 match(AddP (AddP (DecodeN reg) (LShiftL lreg scale)) off);
3959
3960 op_cost(10);
3961 format %{"[$reg + $off + $lreg << $scale]" %}
3962 interface(MEMORY_INTER) %{
3963 base($reg);
3964 index($lreg);
3965 scale($scale);
3966 disp($off);
3967 %}
3968 %}
3969
3970 // Indirect Memory Times Plus Positive Index Register Plus Offset Operand
3971 operand indPosIndexOffsetNarrow(rRegN reg, immL32 off, rRegI idx)
3972 %{
3973 constraint(ALLOC_IN_RC(ptr_reg));
3974 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->as_Type()->type()->is_long()->_lo >= 0);
3975 match(AddP (AddP (DecodeN reg) (ConvI2L idx)) off);
3976
3977 op_cost(10);
3978 format %{"[$reg + $off + $idx]" %}
3979 interface(MEMORY_INTER) %{
3980 base($reg);
3981 index($idx);
3982 scale(0x0);
3983 disp($off);
3984 %}
3985 %}
3986
3987 // Indirect Memory Times Scale Plus Positive Index Register Plus Offset Operand
3988 operand indPosIndexScaleOffsetNarrow(rRegN reg, immL32 off, rRegI idx, immI2 scale)
3989 %{
3990 constraint(ALLOC_IN_RC(ptr_reg));
3991 predicate(Universe::narrow_oop_shift() == 0 && n->in(2)->in(3)->in(1)->as_Type()->type()->is_long()->_lo >= 0);
3992 match(AddP (AddP (DecodeN reg) (LShiftL (ConvI2L idx) scale)) off);
3993
3994 op_cost(10);
3995 format %{"[$reg + $off + $idx << $scale]" %}
3996 interface(MEMORY_INTER) %{
3997 base($reg);
3998 index($idx);
3999 scale($scale);
4000 disp($off);
4001 %}
4002 %}
4003
4004 //----------Special Memory Operands--------------------------------------------
4005 // Stack Slot Operand - This operand is used for loading and storing temporary
4006 // values on the stack where a match requires a value to
4007 // flow through memory.
4008 operand stackSlotP(sRegP reg)
4009 %{
4010 constraint(ALLOC_IN_RC(stack_slots));
4011 // No match rule because this operand is only generated in matching
4012
4013 format %{ "[$reg]" %}
4014 interface(MEMORY_INTER) %{
4015 base(0x4); // RSP
4016 index(0x4); // No Index
4017 scale(0x0); // No Scale
4018 disp($reg); // Stack Offset
4019 %}
4020 %}
4021
4022 operand stackSlotI(sRegI reg)
4023 %{
4024 constraint(ALLOC_IN_RC(stack_slots));
4025 // No match rule because this operand is only generated in matching
4026
4027 format %{ "[$reg]" %}
4028 interface(MEMORY_INTER) %{
4029 base(0x4); // RSP
4030 index(0x4); // No Index
4031 scale(0x0); // No Scale
4032 disp($reg); // Stack Offset
4033 %}
4034 %}
4035
4036 operand stackSlotF(sRegF reg)
4037 %{
4038 constraint(ALLOC_IN_RC(stack_slots));
4039 // No match rule because this operand is only generated in matching
4040
4041 format %{ "[$reg]" %}
4042 interface(MEMORY_INTER) %{
4043 base(0x4); // RSP
4044 index(0x4); // No Index
4045 scale(0x0); // No Scale
4046 disp($reg); // Stack Offset
4047 %}
4048 %}
4049
4050 operand stackSlotD(sRegD reg)
4051 %{
4052 constraint(ALLOC_IN_RC(stack_slots));
4053 // No match rule because this operand is only generated in matching
4054
4055 format %{ "[$reg]" %}
4056 interface(MEMORY_INTER) %{
4057 base(0x4); // RSP
4058 index(0x4); // No Index
4059 scale(0x0); // No Scale
4060 disp($reg); // Stack Offset
4061 %}
4062 %}
4063 operand stackSlotL(sRegL reg)
4064 %{
4065 constraint(ALLOC_IN_RC(stack_slots));
4066 // No match rule because this operand is only generated in matching
4067
4068 format %{ "[$reg]" %}
4069 interface(MEMORY_INTER) %{
4070 base(0x4); // RSP
4071 index(0x4); // No Index
4072 scale(0x0); // No Scale
4073 disp($reg); // Stack Offset
4074 %}
4075 %}
4076
4077 //----------Conditional Branch Operands----------------------------------------
4078 // Comparison Op - This is the operation of the comparison, and is limited to
4079 // the following set of codes:
4080 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4081 //
4082 // Other attributes of the comparison, such as unsignedness, are specified
4083 // by the comparison instruction that sets a condition code flags register.
4084 // That result is represented by a flags operand whose subtype is appropriate
4085 // to the unsignedness (etc.) of the comparison.
4086 //
4087 // Later, the instruction which matches both the Comparison Op (a Bool) and
4088 // the flags (produced by the Cmp) specifies the coding of the comparison op
4089 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4090
4091 // Comparision Code
4092 operand cmpOp()
4093 %{
4094 match(Bool);
4095
4096 format %{ "" %}
4097 interface(COND_INTER) %{
4098 equal(0x4, "e");
4099 not_equal(0x5, "ne");
4100 less(0xC, "l");
4101 greater_equal(0xD, "ge");
4102 less_equal(0xE, "le");
4103 greater(0xF, "g");
4104 overflow(0x0, "o");
4105 no_overflow(0x1, "no");
4106 %}
4107 %}
4108
4109 // Comparison Code, unsigned compare. Used by FP also, with
4110 // C2 (unordered) turned into GT or LT already. The other bits
4111 // C0 and C3 are turned into Carry & Zero flags.
4112 operand cmpOpU()
4113 %{
4114 match(Bool);
4115
4116 format %{ "" %}
4117 interface(COND_INTER) %{
4118 equal(0x4, "e");
4119 not_equal(0x5, "ne");
4120 less(0x2, "b");
4121 greater_equal(0x3, "nb");
4122 less_equal(0x6, "be");
4123 greater(0x7, "nbe");
4124 overflow(0x0, "o");
4125 no_overflow(0x1, "no");
4126 %}
4127 %}
4128
4129
4130 // Floating comparisons that don't require any fixup for the unordered case
4131 operand cmpOpUCF() %{
4132 match(Bool);
4133 predicate(n->as_Bool()->_test._test == BoolTest::lt ||
4134 n->as_Bool()->_test._test == BoolTest::ge ||
4135 n->as_Bool()->_test._test == BoolTest::le ||
4136 n->as_Bool()->_test._test == BoolTest::gt);
4137 format %{ "" %}
4138 interface(COND_INTER) %{
4139 equal(0x4, "e");
4140 not_equal(0x5, "ne");
4141 less(0x2, "b");
4142 greater_equal(0x3, "nb");
4143 less_equal(0x6, "be");
4144 greater(0x7, "nbe");
4145 overflow(0x0, "o");
4146 no_overflow(0x1, "no");
4147 %}
4148 %}
4149
4150
4151 // Floating comparisons that can be fixed up with extra conditional jumps
4152 operand cmpOpUCF2() %{
4153 match(Bool);
4154 predicate(n->as_Bool()->_test._test == BoolTest::ne ||
4155 n->as_Bool()->_test._test == BoolTest::eq);
4156 format %{ "" %}
4157 interface(COND_INTER) %{
4158 equal(0x4, "e");
4159 not_equal(0x5, "ne");
4160 less(0x2, "b");
4161 greater_equal(0x3, "nb");
4162 less_equal(0x6, "be");
4163 greater(0x7, "nbe");
4164 overflow(0x0, "o");
4165 no_overflow(0x1, "no");
4166 %}
4167 %}
4168
4169
4170 //----------OPERAND CLASSES----------------------------------------------------
4171 // Operand Classes are groups of operands that are used as to simplify
4172 // instruction definitions by not requiring the AD writer to specify separate
4173 // instructions for every form of operand when the instruction accepts
4174 // multiple operand types with the same basic encoding and format. The classic
4175 // case of this is memory operands.
4176
4177 opclass memory(indirect, indOffset8, indOffset32, indIndexOffset, indIndex,
4178 indIndexScale, indPosIndexScale, indIndexScaleOffset, indPosIndexOffset, indPosIndexScaleOffset,
4179 indCompressedOopOffset,
4180 indirectNarrow, indOffset8Narrow, indOffset32Narrow,
4181 indIndexOffsetNarrow, indIndexNarrow, indIndexScaleNarrow,
4182 indIndexScaleOffsetNarrow, indPosIndexOffsetNarrow, indPosIndexScaleOffsetNarrow);
4183
4184 //----------PIPELINE-----------------------------------------------------------
4185 // Rules which define the behavior of the target architectures pipeline.
4186 pipeline %{
4187
4188 //----------ATTRIBUTES---------------------------------------------------------
4189 attributes %{
4190 variable_size_instructions; // Fixed size instructions
4191 max_instructions_per_bundle = 3; // Up to 3 instructions per bundle
4192 instruction_unit_size = 1; // An instruction is 1 bytes long
4193 instruction_fetch_unit_size = 16; // The processor fetches one line
4194 instruction_fetch_units = 1; // of 16 bytes
4195
4196 // List of nop instructions
4197 nops( MachNop );
4198 %}
4199
4200 //----------RESOURCES----------------------------------------------------------
4201 // Resources are the functional units available to the machine
4202
4203 // Generic P2/P3 pipeline
4204 // 3 decoders, only D0 handles big operands; a "bundle" is the limit of
4205 // 3 instructions decoded per cycle.
4206 // 2 load/store ops per cycle, 1 branch, 1 FPU,
4207 // 3 ALU op, only ALU0 handles mul instructions.
4208 resources( D0, D1, D2, DECODE = D0 | D1 | D2,
4209 MS0, MS1, MS2, MEM = MS0 | MS1 | MS2,
4210 BR, FPU,
4211 ALU0, ALU1, ALU2, ALU = ALU0 | ALU1 | ALU2);
4212
4213 //----------PIPELINE DESCRIPTION-----------------------------------------------
4214 // Pipeline Description specifies the stages in the machine's pipeline
4215
4216 // Generic P2/P3 pipeline
4217 pipe_desc(S0, S1, S2, S3, S4, S5);
4218
4219 //----------PIPELINE CLASSES---------------------------------------------------
4220 // Pipeline Classes describe the stages in which input and output are
4221 // referenced by the hardware pipeline.
4222
4223 // Naming convention: ialu or fpu
4224 // Then: _reg
4225 // Then: _reg if there is a 2nd register
4226 // Then: _long if it's a pair of instructions implementing a long
4227 // Then: _fat if it requires the big decoder
4228 // Or: _mem if it requires the big decoder and a memory unit.
4229
4230 // Integer ALU reg operation
4231 pipe_class ialu_reg(rRegI dst)
4232 %{
4233 single_instruction;
4234 dst : S4(write);
4235 dst : S3(read);
4236 DECODE : S0; // any decoder
4237 ALU : S3; // any alu
4238 %}
4239
4240 // Long ALU reg operation
4241 pipe_class ialu_reg_long(rRegL dst)
4242 %{
4243 instruction_count(2);
4244 dst : S4(write);
4245 dst : S3(read);
4246 DECODE : S0(2); // any 2 decoders
4247 ALU : S3(2); // both alus
4248 %}
4249
4250 // Integer ALU reg operation using big decoder
4251 pipe_class ialu_reg_fat(rRegI dst)
4252 %{
4253 single_instruction;
4254 dst : S4(write);
4255 dst : S3(read);
4256 D0 : S0; // big decoder only
4257 ALU : S3; // any alu
4258 %}
4259
4260 // Long ALU reg operation using big decoder
4261 pipe_class ialu_reg_long_fat(rRegL dst)
4262 %{
4263 instruction_count(2);
4264 dst : S4(write);
4265 dst : S3(read);
4266 D0 : S0(2); // big decoder only; twice
4267 ALU : S3(2); // any 2 alus
4268 %}
4269
4270 // Integer ALU reg-reg operation
4271 pipe_class ialu_reg_reg(rRegI dst, rRegI src)
4272 %{
4273 single_instruction;
4274 dst : S4(write);
4275 src : S3(read);
4276 DECODE : S0; // any decoder
4277 ALU : S3; // any alu
4278 %}
4279
4280 // Long ALU reg-reg operation
4281 pipe_class ialu_reg_reg_long(rRegL dst, rRegL src)
4282 %{
4283 instruction_count(2);
4284 dst : S4(write);
4285 src : S3(read);
4286 DECODE : S0(2); // any 2 decoders
4287 ALU : S3(2); // both alus
4288 %}
4289
4290 // Integer ALU reg-reg operation
4291 pipe_class ialu_reg_reg_fat(rRegI dst, memory src)
4292 %{
4293 single_instruction;
4294 dst : S4(write);
4295 src : S3(read);
4296 D0 : S0; // big decoder only
4297 ALU : S3; // any alu
4298 %}
4299
4300 // Long ALU reg-reg operation
4301 pipe_class ialu_reg_reg_long_fat(rRegL dst, rRegL src)
4302 %{
4303 instruction_count(2);
4304 dst : S4(write);
4305 src : S3(read);
4306 D0 : S0(2); // big decoder only; twice
4307 ALU : S3(2); // both alus
4308 %}
4309
4310 // Integer ALU reg-mem operation
4311 pipe_class ialu_reg_mem(rRegI dst, memory mem)
4312 %{
4313 single_instruction;
4314 dst : S5(write);
4315 mem : S3(read);
4316 D0 : S0; // big decoder only
4317 ALU : S4; // any alu
4318 MEM : S3; // any mem
4319 %}
4320
4321 // Integer mem operation (prefetch)
4322 pipe_class ialu_mem(memory mem)
4323 %{
4324 single_instruction;
4325 mem : S3(read);
4326 D0 : S0; // big decoder only
4327 MEM : S3; // any mem
4328 %}
4329
4330 // Integer Store to Memory
4331 pipe_class ialu_mem_reg(memory mem, rRegI src)
4332 %{
4333 single_instruction;
4334 mem : S3(read);
4335 src : S5(read);
4336 D0 : S0; // big decoder only
4337 ALU : S4; // any alu
4338 MEM : S3;
4339 %}
4340
4341 // // Long Store to Memory
4342 // pipe_class ialu_mem_long_reg(memory mem, rRegL src)
4343 // %{
4344 // instruction_count(2);
4345 // mem : S3(read);
4346 // src : S5(read);
4347 // D0 : S0(2); // big decoder only; twice
4348 // ALU : S4(2); // any 2 alus
4349 // MEM : S3(2); // Both mems
4350 // %}
4351
4352 // Integer Store to Memory
4353 pipe_class ialu_mem_imm(memory mem)
4354 %{
4355 single_instruction;
4356 mem : S3(read);
4357 D0 : S0; // big decoder only
4358 ALU : S4; // any alu
4359 MEM : S3;
4360 %}
4361
4362 // Integer ALU0 reg-reg operation
4363 pipe_class ialu_reg_reg_alu0(rRegI dst, rRegI src)
4364 %{
4365 single_instruction;
4366 dst : S4(write);
4367 src : S3(read);
4368 D0 : S0; // Big decoder only
4369 ALU0 : S3; // only alu0
4370 %}
4371
4372 // Integer ALU0 reg-mem operation
4373 pipe_class ialu_reg_mem_alu0(rRegI dst, memory mem)
4374 %{
4375 single_instruction;
4376 dst : S5(write);
4377 mem : S3(read);
4378 D0 : S0; // big decoder only
4379 ALU0 : S4; // ALU0 only
4380 MEM : S3; // any mem
4381 %}
4382
4383 // Integer ALU reg-reg operation
4384 pipe_class ialu_cr_reg_reg(rFlagsReg cr, rRegI src1, rRegI src2)
4385 %{
4386 single_instruction;
4387 cr : S4(write);
4388 src1 : S3(read);
4389 src2 : S3(read);
4390 DECODE : S0; // any decoder
4391 ALU : S3; // any alu
4392 %}
4393
4394 // Integer ALU reg-imm operation
4395 pipe_class ialu_cr_reg_imm(rFlagsReg cr, rRegI src1)
4396 %{
4397 single_instruction;
4398 cr : S4(write);
4399 src1 : S3(read);
4400 DECODE : S0; // any decoder
4401 ALU : S3; // any alu
4402 %}
4403
4404 // Integer ALU reg-mem operation
4405 pipe_class ialu_cr_reg_mem(rFlagsReg cr, rRegI src1, memory src2)
4406 %{
4407 single_instruction;
4408 cr : S4(write);
4409 src1 : S3(read);
4410 src2 : S3(read);
4411 D0 : S0; // big decoder only
4412 ALU : S4; // any alu
4413 MEM : S3;
4414 %}
4415
4416 // Conditional move reg-reg
4417 pipe_class pipe_cmplt( rRegI p, rRegI q, rRegI y)
4418 %{
4419 instruction_count(4);
4420 y : S4(read);
4421 q : S3(read);
4422 p : S3(read);
4423 DECODE : S0(4); // any decoder
4424 %}
4425
4426 // Conditional move reg-reg
4427 pipe_class pipe_cmov_reg( rRegI dst, rRegI src, rFlagsReg cr)
4428 %{
4429 single_instruction;
4430 dst : S4(write);
4431 src : S3(read);
4432 cr : S3(read);
4433 DECODE : S0; // any decoder
4434 %}
4435
4436 // Conditional move reg-mem
4437 pipe_class pipe_cmov_mem( rFlagsReg cr, rRegI dst, memory src)
4438 %{
4439 single_instruction;
4440 dst : S4(write);
4441 src : S3(read);
4442 cr : S3(read);
4443 DECODE : S0; // any decoder
4444 MEM : S3;
4445 %}
4446
4447 // Conditional move reg-reg long
4448 pipe_class pipe_cmov_reg_long( rFlagsReg cr, rRegL dst, rRegL src)
4449 %{
4450 single_instruction;
4451 dst : S4(write);
4452 src : S3(read);
4453 cr : S3(read);
4454 DECODE : S0(2); // any 2 decoders
4455 %}
4456
4457 // XXX
4458 // // Conditional move double reg-reg
4459 // pipe_class pipe_cmovD_reg( rFlagsReg cr, regDPR1 dst, regD src)
4460 // %{
4461 // single_instruction;
4462 // dst : S4(write);
4463 // src : S3(read);
4464 // cr : S3(read);
4465 // DECODE : S0; // any decoder
4466 // %}
4467
4468 // Float reg-reg operation
4469 pipe_class fpu_reg(regD dst)
4470 %{
4471 instruction_count(2);
4472 dst : S3(read);
4473 DECODE : S0(2); // any 2 decoders
4474 FPU : S3;
4475 %}
4476
4477 // Float reg-reg operation
4478 pipe_class fpu_reg_reg(regD dst, regD src)
4479 %{
4480 instruction_count(2);
4481 dst : S4(write);
4482 src : S3(read);
4483 DECODE : S0(2); // any 2 decoders
4484 FPU : S3;
4485 %}
4486
4487 // Float reg-reg operation
4488 pipe_class fpu_reg_reg_reg(regD dst, regD src1, regD src2)
4489 %{
4490 instruction_count(3);
4491 dst : S4(write);
4492 src1 : S3(read);
4493 src2 : S3(read);
4494 DECODE : S0(3); // any 3 decoders
4495 FPU : S3(2);
4496 %}
4497
4498 // Float reg-reg operation
4499 pipe_class fpu_reg_reg_reg_reg(regD dst, regD src1, regD src2, regD src3)
4500 %{
4501 instruction_count(4);
4502 dst : S4(write);
4503 src1 : S3(read);
4504 src2 : S3(read);
4505 src3 : S3(read);
4506 DECODE : S0(4); // any 3 decoders
4507 FPU : S3(2);
4508 %}
4509
4510 // Float reg-reg operation
4511 pipe_class fpu_reg_mem_reg_reg(regD dst, memory src1, regD src2, regD src3)
4512 %{
4513 instruction_count(4);
4514 dst : S4(write);
4515 src1 : S3(read);
4516 src2 : S3(read);
4517 src3 : S3(read);
4518 DECODE : S1(3); // any 3 decoders
4519 D0 : S0; // Big decoder only
4520 FPU : S3(2);
4521 MEM : S3;
4522 %}
4523
4524 // Float reg-mem operation
4525 pipe_class fpu_reg_mem(regD dst, memory mem)
4526 %{
4527 instruction_count(2);
4528 dst : S5(write);
4529 mem : S3(read);
4530 D0 : S0; // big decoder only
4531 DECODE : S1; // any decoder for FPU POP
4532 FPU : S4;
4533 MEM : S3; // any mem
4534 %}
4535
4536 // Float reg-mem operation
4537 pipe_class fpu_reg_reg_mem(regD dst, regD src1, memory mem)
4538 %{
4539 instruction_count(3);
4540 dst : S5(write);
4541 src1 : S3(read);
4542 mem : S3(read);
4543 D0 : S0; // big decoder only
4544 DECODE : S1(2); // any decoder for FPU POP
4545 FPU : S4;
4546 MEM : S3; // any mem
4547 %}
4548
4549 // Float mem-reg operation
4550 pipe_class fpu_mem_reg(memory mem, regD src)
4551 %{
4552 instruction_count(2);
4553 src : S5(read);
4554 mem : S3(read);
4555 DECODE : S0; // any decoder for FPU PUSH
4556 D0 : S1; // big decoder only
4557 FPU : S4;
4558 MEM : S3; // any mem
4559 %}
4560
4561 pipe_class fpu_mem_reg_reg(memory mem, regD src1, regD src2)
4562 %{
4563 instruction_count(3);
4564 src1 : S3(read);
4565 src2 : S3(read);
4566 mem : S3(read);
4567 DECODE : S0(2); // any decoder for FPU PUSH
4568 D0 : S1; // big decoder only
4569 FPU : S4;
4570 MEM : S3; // any mem
4571 %}
4572
4573 pipe_class fpu_mem_reg_mem(memory mem, regD src1, memory src2)
4574 %{
4575 instruction_count(3);
4576 src1 : S3(read);
4577 src2 : S3(read);
4578 mem : S4(read);
4579 DECODE : S0; // any decoder for FPU PUSH
4580 D0 : S0(2); // big decoder only
4581 FPU : S4;
4582 MEM : S3(2); // any mem
4583 %}
4584
4585 pipe_class fpu_mem_mem(memory dst, memory src1)
4586 %{
4587 instruction_count(2);
4588 src1 : S3(read);
4589 dst : S4(read);
4590 D0 : S0(2); // big decoder only
4591 MEM : S3(2); // any mem
4592 %}
4593
4594 pipe_class fpu_mem_mem_mem(memory dst, memory src1, memory src2)
4595 %{
4596 instruction_count(3);
4597 src1 : S3(read);
4598 src2 : S3(read);
4599 dst : S4(read);
4600 D0 : S0(3); // big decoder only
4601 FPU : S4;
4602 MEM : S3(3); // any mem
4603 %}
4604
4605 pipe_class fpu_mem_reg_con(memory mem, regD src1)
4606 %{
4607 instruction_count(3);
4608 src1 : S4(read);
4609 mem : S4(read);
4610 DECODE : S0; // any decoder for FPU PUSH
4611 D0 : S0(2); // big decoder only
4612 FPU : S4;
4613 MEM : S3(2); // any mem
4614 %}
4615
4616 // Float load constant
4617 pipe_class fpu_reg_con(regD dst)
4618 %{
4619 instruction_count(2);
4620 dst : S5(write);
4621 D0 : S0; // big decoder only for the load
4622 DECODE : S1; // any decoder for FPU POP
4623 FPU : S4;
4624 MEM : S3; // any mem
4625 %}
4626
4627 // Float load constant
4628 pipe_class fpu_reg_reg_con(regD dst, regD src)
4629 %{
4630 instruction_count(3);
4631 dst : S5(write);
4632 src : S3(read);
4633 D0 : S0; // big decoder only for the load
4634 DECODE : S1(2); // any decoder for FPU POP
4635 FPU : S4;
4636 MEM : S3; // any mem
4637 %}
4638
4639 // UnConditional branch
4640 pipe_class pipe_jmp(label labl)
4641 %{
4642 single_instruction;
4643 BR : S3;
4644 %}
4645
4646 // Conditional branch
4647 pipe_class pipe_jcc(cmpOp cmp, rFlagsReg cr, label labl)
4648 %{
4649 single_instruction;
4650 cr : S1(read);
4651 BR : S3;
4652 %}
4653
4654 // Allocation idiom
4655 pipe_class pipe_cmpxchg(rRegP dst, rRegP heap_ptr)
4656 %{
4657 instruction_count(1); force_serialization;
4658 fixed_latency(6);
4659 heap_ptr : S3(read);
4660 DECODE : S0(3);
4661 D0 : S2;
4662 MEM : S3;
4663 ALU : S3(2);
4664 dst : S5(write);
4665 BR : S5;
4666 %}
4667
4668 // Generic big/slow expanded idiom
4669 pipe_class pipe_slow()
4670 %{
4671 instruction_count(10); multiple_bundles; force_serialization;
4672 fixed_latency(100);
4673 D0 : S0(2);
4674 MEM : S3(2);
4675 %}
4676
4677 // The real do-nothing guy
4678 pipe_class empty()
4679 %{
4680 instruction_count(0);
4681 %}
4682
4683 // Define the class for the Nop node
4684 define
4685 %{
4686 MachNop = empty;
4687 %}
4688
4689 %}
4690
4691 //----------INSTRUCTIONS-------------------------------------------------------
4692 //
4693 // match -- States which machine-independent subtree may be replaced
4694 // by this instruction.
4695 // ins_cost -- The estimated cost of this instruction is used by instruction
4696 // selection to identify a minimum cost tree of machine
4697 // instructions that matches a tree of machine-independent
4698 // instructions.
4699 // format -- A string providing the disassembly for this instruction.
4700 // The value of an instruction's operand may be inserted
4701 // by referring to it with a '$' prefix.
4702 // opcode -- Three instruction opcodes may be provided. These are referred
4703 // to within an encode class as $primary, $secondary, and $tertiary
4704 // rrspectively. The primary opcode is commonly used to
4705 // indicate the type of machine instruction, while secondary
4706 // and tertiary are often used for prefix options or addressing
4707 // modes.
4708 // ins_encode -- A list of encode classes with parameters. The encode class
4709 // name must have been defined in an 'enc_class' specification
4710 // in the encode section of the architecture description.
4711
4712
4713 //----------Load/Store/Move Instructions---------------------------------------
4714 //----------Load Instructions--------------------------------------------------
4715
4716 // Load Byte (8 bit signed)
4717 instruct loadB(rRegI dst, memory mem)
4718 %{
4719 match(Set dst (LoadB mem));
4720
4721 ins_cost(125);
4722 format %{ "movsbl $dst, $mem\t# byte" %}
4723
4724 ins_encode %{
4725 __ movsbl($dst$$Register, $mem$$Address);
4726 %}
4727
4728 ins_pipe(ialu_reg_mem);
4729 %}
4730
4731 // Load Byte (8 bit signed) into Long Register
4732 instruct loadB2L(rRegL dst, memory mem)
4733 %{
4734 match(Set dst (ConvI2L (LoadB mem)));
4735
4736 ins_cost(125);
4737 format %{ "movsbq $dst, $mem\t# byte -> long" %}
4738
4739 ins_encode %{
4740 __ movsbq($dst$$Register, $mem$$Address);
4741 %}
4742
4743 ins_pipe(ialu_reg_mem);
4744 %}
4745
4746 // Load Unsigned Byte (8 bit UNsigned)
4747 instruct loadUB(rRegI dst, memory mem)
4748 %{
4749 match(Set dst (LoadUB mem));
4750
4751 ins_cost(125);
4752 format %{ "movzbl $dst, $mem\t# ubyte" %}
4753
4754 ins_encode %{
4755 __ movzbl($dst$$Register, $mem$$Address);
4756 %}
4757
4758 ins_pipe(ialu_reg_mem);
4759 %}
4760
4761 // Load Unsigned Byte (8 bit UNsigned) into Long Register
4762 instruct loadUB2L(rRegL dst, memory mem)
4763 %{
4764 match(Set dst (ConvI2L (LoadUB mem)));
4765
4766 ins_cost(125);
4767 format %{ "movzbq $dst, $mem\t# ubyte -> long" %}
4768
4769 ins_encode %{
4770 __ movzbq($dst$$Register, $mem$$Address);
4771 %}
4772
4773 ins_pipe(ialu_reg_mem);
4774 %}
4775
4776 // Load Unsigned Byte (8 bit UNsigned) with 32-bit mask into Long Register
4777 instruct loadUB2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4778 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
4779 effect(KILL cr);
4780
4781 format %{ "movzbq $dst, $mem\t# ubyte & 32-bit mask -> long\n\t"
4782 "andl $dst, right_n_bits($mask, 8)" %}
4783 ins_encode %{
4784 Register Rdst = $dst$$Register;
4785 __ movzbq(Rdst, $mem$$Address);
4786 __ andl(Rdst, $mask$$constant & right_n_bits(8));
4787 %}
4788 ins_pipe(ialu_reg_mem);
4789 %}
4790
4791 // Load Short (16 bit signed)
4792 instruct loadS(rRegI dst, memory mem)
4793 %{
4794 match(Set dst (LoadS mem));
4795
4796 ins_cost(125);
4797 format %{ "movswl $dst, $mem\t# short" %}
4798
4799 ins_encode %{
4800 __ movswl($dst$$Register, $mem$$Address);
4801 %}
4802
4803 ins_pipe(ialu_reg_mem);
4804 %}
4805
4806 // Load Short (16 bit signed) to Byte (8 bit signed)
4807 instruct loadS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4808 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
4809
4810 ins_cost(125);
4811 format %{ "movsbl $dst, $mem\t# short -> byte" %}
4812 ins_encode %{
4813 __ movsbl($dst$$Register, $mem$$Address);
4814 %}
4815 ins_pipe(ialu_reg_mem);
4816 %}
4817
4818 // Load Short (16 bit signed) into Long Register
4819 instruct loadS2L(rRegL dst, memory mem)
4820 %{
4821 match(Set dst (ConvI2L (LoadS mem)));
4822
4823 ins_cost(125);
4824 format %{ "movswq $dst, $mem\t# short -> long" %}
4825
4826 ins_encode %{
4827 __ movswq($dst$$Register, $mem$$Address);
4828 %}
4829
4830 ins_pipe(ialu_reg_mem);
4831 %}
4832
4833 // Load Unsigned Short/Char (16 bit UNsigned)
4834 instruct loadUS(rRegI dst, memory mem)
4835 %{
4836 match(Set dst (LoadUS mem));
4837
4838 ins_cost(125);
4839 format %{ "movzwl $dst, $mem\t# ushort/char" %}
4840
4841 ins_encode %{
4842 __ movzwl($dst$$Register, $mem$$Address);
4843 %}
4844
4845 ins_pipe(ialu_reg_mem);
4846 %}
4847
4848 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
4849 instruct loadUS2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4850 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
4851
4852 ins_cost(125);
4853 format %{ "movsbl $dst, $mem\t# ushort -> byte" %}
4854 ins_encode %{
4855 __ movsbl($dst$$Register, $mem$$Address);
4856 %}
4857 ins_pipe(ialu_reg_mem);
4858 %}
4859
4860 // Load Unsigned Short/Char (16 bit UNsigned) into Long Register
4861 instruct loadUS2L(rRegL dst, memory mem)
4862 %{
4863 match(Set dst (ConvI2L (LoadUS mem)));
4864
4865 ins_cost(125);
4866 format %{ "movzwq $dst, $mem\t# ushort/char -> long" %}
4867
4868 ins_encode %{
4869 __ movzwq($dst$$Register, $mem$$Address);
4870 %}
4871
4872 ins_pipe(ialu_reg_mem);
4873 %}
4874
4875 // Load Unsigned Short/Char (16 bit UNsigned) with mask 0xFF into Long Register
4876 instruct loadUS2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4877 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4878
4879 format %{ "movzbq $dst, $mem\t# ushort/char & 0xFF -> long" %}
4880 ins_encode %{
4881 __ movzbq($dst$$Register, $mem$$Address);
4882 %}
4883 ins_pipe(ialu_reg_mem);
4884 %}
4885
4886 // Load Unsigned Short/Char (16 bit UNsigned) with 32-bit mask into Long Register
4887 instruct loadUS2L_immI(rRegL dst, memory mem, immI mask, rFlagsReg cr) %{
4888 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
4889 effect(KILL cr);
4890
4891 format %{ "movzwq $dst, $mem\t# ushort/char & 32-bit mask -> long\n\t"
4892 "andl $dst, right_n_bits($mask, 16)" %}
4893 ins_encode %{
4894 Register Rdst = $dst$$Register;
4895 __ movzwq(Rdst, $mem$$Address);
4896 __ andl(Rdst, $mask$$constant & right_n_bits(16));
4897 %}
4898 ins_pipe(ialu_reg_mem);
4899 %}
4900
4901 // Load Integer
4902 instruct loadI(rRegI dst, memory mem)
4903 %{
4904 match(Set dst (LoadI mem));
4905
4906 ins_cost(125);
4907 format %{ "movl $dst, $mem\t# int" %}
4908
4909 ins_encode %{
4910 __ movl($dst$$Register, $mem$$Address);
4911 %}
4912
4913 ins_pipe(ialu_reg_mem);
4914 %}
4915
4916 // Load Integer (32 bit signed) to Byte (8 bit signed)
4917 instruct loadI2B(rRegI dst, memory mem, immI_24 twentyfour) %{
4918 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
4919
4920 ins_cost(125);
4921 format %{ "movsbl $dst, $mem\t# int -> byte" %}
4922 ins_encode %{
4923 __ movsbl($dst$$Register, $mem$$Address);
4924 %}
4925 ins_pipe(ialu_reg_mem);
4926 %}
4927
4928 // Load Integer (32 bit signed) to Unsigned Byte (8 bit UNsigned)
4929 instruct loadI2UB(rRegI dst, memory mem, immI_255 mask) %{
4930 match(Set dst (AndI (LoadI mem) mask));
4931
4932 ins_cost(125);
4933 format %{ "movzbl $dst, $mem\t# int -> ubyte" %}
4934 ins_encode %{
4935 __ movzbl($dst$$Register, $mem$$Address);
4936 %}
4937 ins_pipe(ialu_reg_mem);
4938 %}
4939
4940 // Load Integer (32 bit signed) to Short (16 bit signed)
4941 instruct loadI2S(rRegI dst, memory mem, immI_16 sixteen) %{
4942 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
4943
4944 ins_cost(125);
4945 format %{ "movswl $dst, $mem\t# int -> short" %}
4946 ins_encode %{
4947 __ movswl($dst$$Register, $mem$$Address);
4948 %}
4949 ins_pipe(ialu_reg_mem);
4950 %}
4951
4952 // Load Integer (32 bit signed) to Unsigned Short/Char (16 bit UNsigned)
4953 instruct loadI2US(rRegI dst, memory mem, immI_65535 mask) %{
4954 match(Set dst (AndI (LoadI mem) mask));
4955
4956 ins_cost(125);
4957 format %{ "movzwl $dst, $mem\t# int -> ushort/char" %}
4958 ins_encode %{
4959 __ movzwl($dst$$Register, $mem$$Address);
4960 %}
4961 ins_pipe(ialu_reg_mem);
4962 %}
4963
4964 // Load Integer into Long Register
4965 instruct loadI2L(rRegL dst, memory mem)
4966 %{
4967 match(Set dst (ConvI2L (LoadI mem)));
4968
4969 ins_cost(125);
4970 format %{ "movslq $dst, $mem\t# int -> long" %}
4971
4972 ins_encode %{
4973 __ movslq($dst$$Register, $mem$$Address);
4974 %}
4975
4976 ins_pipe(ialu_reg_mem);
4977 %}
4978
4979 // Load Integer with mask 0xFF into Long Register
4980 instruct loadI2L_immI_255(rRegL dst, memory mem, immI_255 mask) %{
4981 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4982
4983 format %{ "movzbq $dst, $mem\t# int & 0xFF -> long" %}
4984 ins_encode %{
4985 __ movzbq($dst$$Register, $mem$$Address);
4986 %}
4987 ins_pipe(ialu_reg_mem);
4988 %}
4989
4990 // Load Integer with mask 0xFFFF into Long Register
4991 instruct loadI2L_immI_65535(rRegL dst, memory mem, immI_65535 mask) %{
4992 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
4993
4994 format %{ "movzwq $dst, $mem\t# int & 0xFFFF -> long" %}
4995 ins_encode %{
4996 __ movzwq($dst$$Register, $mem$$Address);
4997 %}
4998 ins_pipe(ialu_reg_mem);
4999 %}
5000
5001 // Load Integer with a 31-bit mask into Long Register
5002 instruct loadI2L_immU31(rRegL dst, memory mem, immU31 mask, rFlagsReg cr) %{
5003 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5004 effect(KILL cr);
5005
5006 format %{ "movl $dst, $mem\t# int & 31-bit mask -> long\n\t"
5007 "andl $dst, $mask" %}
5008 ins_encode %{
5009 Register Rdst = $dst$$Register;
5010 __ movl(Rdst, $mem$$Address);
5011 __ andl(Rdst, $mask$$constant);
5012 %}
5013 ins_pipe(ialu_reg_mem);
5014 %}
5015
5016 // Load Unsigned Integer into Long Register
5017 instruct loadUI2L(rRegL dst, memory mem, immL_32bits mask)
5018 %{
5019 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5020
5021 ins_cost(125);
5022 format %{ "movl $dst, $mem\t# uint -> long" %}
5023
5024 ins_encode %{
5025 __ movl($dst$$Register, $mem$$Address);
5026 %}
5027
5028 ins_pipe(ialu_reg_mem);
5029 %}
5030
5031 // Load Long
5032 instruct loadL(rRegL dst, memory mem)
5033 %{
5034 match(Set dst (LoadL mem));
5035
5036 ins_cost(125);
5037 format %{ "movq $dst, $mem\t# long" %}
5038
5039 ins_encode %{
5040 __ movq($dst$$Register, $mem$$Address);
5041 %}
5042
5043 ins_pipe(ialu_reg_mem); // XXX
5044 %}
5045
5046 // Load Range
5047 instruct loadRange(rRegI dst, memory mem)
5048 %{
5049 match(Set dst (LoadRange mem));
5050
5051 ins_cost(125); // XXX
5052 format %{ "movl $dst, $mem\t# range" %}
5053 opcode(0x8B);
5054 ins_encode(REX_reg_mem(dst, mem), OpcP, reg_mem(dst, mem));
5055 ins_pipe(ialu_reg_mem);
5056 %}
5057
5058 // Load Pointer
5059 instruct loadP(rRegP dst, memory mem)
5060 %{
5061 match(Set dst (LoadP mem));
5062
5063 ins_cost(125); // XXX
5064 format %{ "movq $dst, $mem\t# ptr" %}
5065 opcode(0x8B);
5066 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5067 ins_pipe(ialu_reg_mem); // XXX
5068 %}
5069
5070 // Load Compressed Pointer
5071 instruct loadN(rRegN dst, memory mem)
5072 %{
5073 match(Set dst (LoadN mem));
5074
5075 ins_cost(125); // XXX
5076 format %{ "movl $dst, $mem\t# compressed ptr" %}
5077 ins_encode %{
5078 __ movl($dst$$Register, $mem$$Address);
5079 %}
5080 ins_pipe(ialu_reg_mem); // XXX
5081 %}
5082
5083
5084 // Load Klass Pointer
5085 instruct loadKlass(rRegP dst, memory mem)
5086 %{
5087 match(Set dst (LoadKlass mem));
5088
5089 ins_cost(125); // XXX
5090 format %{ "movq $dst, $mem\t# class" %}
5091 opcode(0x8B);
5092 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5093 ins_pipe(ialu_reg_mem); // XXX
5094 %}
5095
5096 // Load narrow Klass Pointer
5097 instruct loadNKlass(rRegN dst, memory mem)
5098 %{
5099 match(Set dst (LoadNKlass mem));
5100
5101 ins_cost(125); // XXX
5102 format %{ "movl $dst, $mem\t# compressed klass ptr" %}
5103 ins_encode %{
5104 __ movl($dst$$Register, $mem$$Address);
5105 %}
5106 ins_pipe(ialu_reg_mem); // XXX
5107 %}
5108
5109 // Load Float
5110 instruct loadF(regF dst, memory mem)
5111 %{
5112 match(Set dst (LoadF mem));
5113
5114 ins_cost(145); // XXX
5115 format %{ "movss $dst, $mem\t# float" %}
5116 ins_encode %{
5117 __ movflt($dst$$XMMRegister, $mem$$Address);
5118 %}
5119 ins_pipe(pipe_slow); // XXX
5120 %}
5121
5122 // Load Double
5123 instruct loadD_partial(regD dst, memory mem)
5124 %{
5125 predicate(!UseXmmLoadAndClearUpper);
5126 match(Set dst (LoadD mem));
5127
5128 ins_cost(145); // XXX
5129 format %{ "movlpd $dst, $mem\t# double" %}
5130 ins_encode %{
5131 __ movdbl($dst$$XMMRegister, $mem$$Address);
5132 %}
5133 ins_pipe(pipe_slow); // XXX
5134 %}
5135
5136 instruct loadD(regD dst, memory mem)
5137 %{
5138 predicate(UseXmmLoadAndClearUpper);
5139 match(Set dst (LoadD mem));
5140
5141 ins_cost(145); // XXX
5142 format %{ "movsd $dst, $mem\t# double" %}
5143 ins_encode %{
5144 __ movdbl($dst$$XMMRegister, $mem$$Address);
5145 %}
5146 ins_pipe(pipe_slow); // XXX
5147 %}
5148
5149 // Load Effective Address
5150 instruct leaP8(rRegP dst, indOffset8 mem)
5151 %{
5152 match(Set dst mem);
5153
5154 ins_cost(110); // XXX
5155 format %{ "leaq $dst, $mem\t# ptr 8" %}
5156 opcode(0x8D);
5157 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5158 ins_pipe(ialu_reg_reg_fat);
5159 %}
5160
5161 instruct leaP32(rRegP dst, indOffset32 mem)
5162 %{
5163 match(Set dst mem);
5164
5165 ins_cost(110);
5166 format %{ "leaq $dst, $mem\t# ptr 32" %}
5167 opcode(0x8D);
5168 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5169 ins_pipe(ialu_reg_reg_fat);
5170 %}
5171
5172 // instruct leaPIdx(rRegP dst, indIndex mem)
5173 // %{
5174 // match(Set dst mem);
5175
5176 // ins_cost(110);
5177 // format %{ "leaq $dst, $mem\t# ptr idx" %}
5178 // opcode(0x8D);
5179 // ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5180 // ins_pipe(ialu_reg_reg_fat);
5181 // %}
5182
5183 instruct leaPIdxOff(rRegP dst, indIndexOffset mem)
5184 %{
5185 match(Set dst mem);
5186
5187 ins_cost(110);
5188 format %{ "leaq $dst, $mem\t# ptr idxoff" %}
5189 opcode(0x8D);
5190 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5191 ins_pipe(ialu_reg_reg_fat);
5192 %}
5193
5194 instruct leaPIdxScale(rRegP dst, indIndexScale mem)
5195 %{
5196 match(Set dst mem);
5197
5198 ins_cost(110);
5199 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5200 opcode(0x8D);
5201 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5202 ins_pipe(ialu_reg_reg_fat);
5203 %}
5204
5205 instruct leaPPosIdxScale(rRegP dst, indPosIndexScale mem)
5206 %{
5207 match(Set dst mem);
5208
5209 ins_cost(110);
5210 format %{ "leaq $dst, $mem\t# ptr idxscale" %}
5211 opcode(0x8D);
5212 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5213 ins_pipe(ialu_reg_reg_fat);
5214 %}
5215
5216 instruct leaPIdxScaleOff(rRegP dst, indIndexScaleOffset mem)
5217 %{
5218 match(Set dst mem);
5219
5220 ins_cost(110);
5221 format %{ "leaq $dst, $mem\t# ptr idxscaleoff" %}
5222 opcode(0x8D);
5223 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5224 ins_pipe(ialu_reg_reg_fat);
5225 %}
5226
5227 instruct leaPPosIdxOff(rRegP dst, indPosIndexOffset mem)
5228 %{
5229 match(Set dst mem);
5230
5231 ins_cost(110);
5232 format %{ "leaq $dst, $mem\t# ptr posidxoff" %}
5233 opcode(0x8D);
5234 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5235 ins_pipe(ialu_reg_reg_fat);
5236 %}
5237
5238 instruct leaPPosIdxScaleOff(rRegP dst, indPosIndexScaleOffset mem)
5239 %{
5240 match(Set dst mem);
5241
5242 ins_cost(110);
5243 format %{ "leaq $dst, $mem\t# ptr posidxscaleoff" %}
5244 opcode(0x8D);
5245 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5246 ins_pipe(ialu_reg_reg_fat);
5247 %}
5248
5249 // Load Effective Address which uses Narrow (32-bits) oop
5250 instruct leaPCompressedOopOffset(rRegP dst, indCompressedOopOffset mem)
5251 %{
5252 predicate(UseCompressedOops && (Universe::narrow_oop_shift() != 0));
5253 match(Set dst mem);
5254
5255 ins_cost(110);
5256 format %{ "leaq $dst, $mem\t# ptr compressedoopoff32" %}
5257 opcode(0x8D);
5258 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5259 ins_pipe(ialu_reg_reg_fat);
5260 %}
5261
5262 instruct leaP8Narrow(rRegP dst, indOffset8Narrow mem)
5263 %{
5264 predicate(Universe::narrow_oop_shift() == 0);
5265 match(Set dst mem);
5266
5267 ins_cost(110); // XXX
5268 format %{ "leaq $dst, $mem\t# ptr off8narrow" %}
5269 opcode(0x8D);
5270 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5271 ins_pipe(ialu_reg_reg_fat);
5272 %}
5273
5274 instruct leaP32Narrow(rRegP dst, indOffset32Narrow mem)
5275 %{
5276 predicate(Universe::narrow_oop_shift() == 0);
5277 match(Set dst mem);
5278
5279 ins_cost(110);
5280 format %{ "leaq $dst, $mem\t# ptr off32narrow" %}
5281 opcode(0x8D);
5282 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5283 ins_pipe(ialu_reg_reg_fat);
5284 %}
5285
5286 instruct leaPIdxOffNarrow(rRegP dst, indIndexOffsetNarrow mem)
5287 %{
5288 predicate(Universe::narrow_oop_shift() == 0);
5289 match(Set dst mem);
5290
5291 ins_cost(110);
5292 format %{ "leaq $dst, $mem\t# ptr idxoffnarrow" %}
5293 opcode(0x8D);
5294 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5295 ins_pipe(ialu_reg_reg_fat);
5296 %}
5297
5298 instruct leaPIdxScaleNarrow(rRegP dst, indIndexScaleNarrow mem)
5299 %{
5300 predicate(Universe::narrow_oop_shift() == 0);
5301 match(Set dst mem);
5302
5303 ins_cost(110);
5304 format %{ "leaq $dst, $mem\t# ptr idxscalenarrow" %}
5305 opcode(0x8D);
5306 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5307 ins_pipe(ialu_reg_reg_fat);
5308 %}
5309
5310 instruct leaPIdxScaleOffNarrow(rRegP dst, indIndexScaleOffsetNarrow mem)
5311 %{
5312 predicate(Universe::narrow_oop_shift() == 0);
5313 match(Set dst mem);
5314
5315 ins_cost(110);
5316 format %{ "leaq $dst, $mem\t# ptr idxscaleoffnarrow" %}
5317 opcode(0x8D);
5318 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5319 ins_pipe(ialu_reg_reg_fat);
5320 %}
5321
5322 instruct leaPPosIdxOffNarrow(rRegP dst, indPosIndexOffsetNarrow mem)
5323 %{
5324 predicate(Universe::narrow_oop_shift() == 0);
5325 match(Set dst mem);
5326
5327 ins_cost(110);
5328 format %{ "leaq $dst, $mem\t# ptr posidxoffnarrow" %}
5329 opcode(0x8D);
5330 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5331 ins_pipe(ialu_reg_reg_fat);
5332 %}
5333
5334 instruct leaPPosIdxScaleOffNarrow(rRegP dst, indPosIndexScaleOffsetNarrow mem)
5335 %{
5336 predicate(Universe::narrow_oop_shift() == 0);
5337 match(Set dst mem);
5338
5339 ins_cost(110);
5340 format %{ "leaq $dst, $mem\t# ptr posidxscaleoffnarrow" %}
5341 opcode(0x8D);
5342 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
5343 ins_pipe(ialu_reg_reg_fat);
5344 %}
5345
5346 instruct loadConI(rRegI dst, immI src)
5347 %{
5348 match(Set dst src);
5349
5350 format %{ "movl $dst, $src\t# int" %}
5351 ins_encode(load_immI(dst, src));
5352 ins_pipe(ialu_reg_fat); // XXX
5353 %}
5354
5355 instruct loadConI0(rRegI dst, immI0 src, rFlagsReg cr)
5356 %{
5357 match(Set dst src);
5358 effect(KILL cr);
5359
5360 ins_cost(50);
5361 format %{ "xorl $dst, $dst\t# int" %}
5362 opcode(0x33); /* + rd */
5363 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5364 ins_pipe(ialu_reg);
5365 %}
5366
5367 instruct loadConL(rRegL dst, immL src)
5368 %{
5369 match(Set dst src);
5370
5371 ins_cost(150);
5372 format %{ "movq $dst, $src\t# long" %}
5373 ins_encode(load_immL(dst, src));
5374 ins_pipe(ialu_reg);
5375 %}
5376
5377 instruct loadConL0(rRegL dst, immL0 src, rFlagsReg cr)
5378 %{
5379 match(Set dst src);
5380 effect(KILL cr);
5381
5382 ins_cost(50);
5383 format %{ "xorl $dst, $dst\t# long" %}
5384 opcode(0x33); /* + rd */
5385 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5386 ins_pipe(ialu_reg); // XXX
5387 %}
5388
5389 instruct loadConUL32(rRegL dst, immUL32 src)
5390 %{
5391 match(Set dst src);
5392
5393 ins_cost(60);
5394 format %{ "movl $dst, $src\t# long (unsigned 32-bit)" %}
5395 ins_encode(load_immUL32(dst, src));
5396 ins_pipe(ialu_reg);
5397 %}
5398
5399 instruct loadConL32(rRegL dst, immL32 src)
5400 %{
5401 match(Set dst src);
5402
5403 ins_cost(70);
5404 format %{ "movq $dst, $src\t# long (32-bit)" %}
5405 ins_encode(load_immL32(dst, src));
5406 ins_pipe(ialu_reg);
5407 %}
5408
5409 instruct loadConP(rRegP dst, immP con) %{
5410 match(Set dst con);
5411
5412 format %{ "movq $dst, $con\t# ptr" %}
5413 ins_encode(load_immP(dst, con));
5414 ins_pipe(ialu_reg_fat); // XXX
5415 %}
5416
5417 instruct loadConP0(rRegP dst, immP0 src, rFlagsReg cr)
5418 %{
5419 match(Set dst src);
5420 effect(KILL cr);
5421
5422 ins_cost(50);
5423 format %{ "xorl $dst, $dst\t# ptr" %}
5424 opcode(0x33); /* + rd */
5425 ins_encode(REX_reg_reg(dst, dst), OpcP, reg_reg(dst, dst));
5426 ins_pipe(ialu_reg);
5427 %}
5428
5429 instruct loadConP31(rRegP dst, immP31 src, rFlagsReg cr)
5430 %{
5431 match(Set dst src);
5432 effect(KILL cr);
5433
5434 ins_cost(60);
5435 format %{ "movl $dst, $src\t# ptr (positive 32-bit)" %}
5436 ins_encode(load_immP31(dst, src));
5437 ins_pipe(ialu_reg);
5438 %}
5439
5440 instruct loadConF(regF dst, immF con) %{
5441 match(Set dst con);
5442 ins_cost(125);
5443 format %{ "movss $dst, [$constantaddress]\t# load from constant table: float=$con" %}
5444 ins_encode %{
5445 __ movflt($dst$$XMMRegister, $constantaddress($con));
5446 %}
5447 ins_pipe(pipe_slow);
5448 %}
5449
5450 instruct loadConN0(rRegN dst, immN0 src, rFlagsReg cr) %{
5451 match(Set dst src);
5452 effect(KILL cr);
5453 format %{ "xorq $dst, $src\t# compressed NULL ptr" %}
5454 ins_encode %{
5455 __ xorq($dst$$Register, $dst$$Register);
5456 %}
5457 ins_pipe(ialu_reg);
5458 %}
5459
5460 instruct loadConN(rRegN dst, immN src) %{
5461 match(Set dst src);
5462
5463 ins_cost(125);
5464 format %{ "movl $dst, $src\t# compressed ptr" %}
5465 ins_encode %{
5466 address con = (address)$src$$constant;
5467 if (con == NULL) {
5468 ShouldNotReachHere();
5469 } else {
5470 __ set_narrow_oop($dst$$Register, (jobject)$src$$constant);
5471 }
5472 %}
5473 ins_pipe(ialu_reg_fat); // XXX
5474 %}
5475
5476 instruct loadConNKlass(rRegN dst, immNKlass src) %{
5477 match(Set dst src);
5478
5479 ins_cost(125);
5480 format %{ "movl $dst, $src\t# compressed klass ptr" %}
5481 ins_encode %{
5482 address con = (address)$src$$constant;
5483 if (con == NULL) {
5484 ShouldNotReachHere();
5485 } else {
5486 __ set_narrow_klass($dst$$Register, (Klass*)$src$$constant);
5487 }
5488 %}
5489 ins_pipe(ialu_reg_fat); // XXX
5490 %}
5491
5492 instruct loadConF0(regF dst, immF0 src)
5493 %{
5494 match(Set dst src);
5495 ins_cost(100);
5496
5497 format %{ "xorps $dst, $dst\t# float 0.0" %}
5498 ins_encode %{
5499 __ xorps($dst$$XMMRegister, $dst$$XMMRegister);
5500 %}
5501 ins_pipe(pipe_slow);
5502 %}
5503
5504 // Use the same format since predicate() can not be used here.
5505 instruct loadConD(regD dst, immD con) %{
5506 match(Set dst con);
5507 ins_cost(125);
5508 format %{ "movsd $dst, [$constantaddress]\t# load from constant table: double=$con" %}
5509 ins_encode %{
5510 __ movdbl($dst$$XMMRegister, $constantaddress($con));
5511 %}
5512 ins_pipe(pipe_slow);
5513 %}
5514
5515 instruct loadConD0(regD dst, immD0 src)
5516 %{
5517 match(Set dst src);
5518 ins_cost(100);
5519
5520 format %{ "xorpd $dst, $dst\t# double 0.0" %}
5521 ins_encode %{
5522 __ xorpd ($dst$$XMMRegister, $dst$$XMMRegister);
5523 %}
5524 ins_pipe(pipe_slow);
5525 %}
5526
5527 instruct loadSSI(rRegI dst, stackSlotI src)
5528 %{
5529 match(Set dst src);
5530
5531 ins_cost(125);
5532 format %{ "movl $dst, $src\t# int stk" %}
5533 opcode(0x8B);
5534 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
5535 ins_pipe(ialu_reg_mem);
5536 %}
5537
5538 instruct loadSSL(rRegL dst, stackSlotL src)
5539 %{
5540 match(Set dst src);
5541
5542 ins_cost(125);
5543 format %{ "movq $dst, $src\t# long stk" %}
5544 opcode(0x8B);
5545 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5546 ins_pipe(ialu_reg_mem);
5547 %}
5548
5549 instruct loadSSP(rRegP dst, stackSlotP src)
5550 %{
5551 match(Set dst src);
5552
5553 ins_cost(125);
5554 format %{ "movq $dst, $src\t# ptr stk" %}
5555 opcode(0x8B);
5556 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
5557 ins_pipe(ialu_reg_mem);
5558 %}
5559
5560 instruct loadSSF(regF dst, stackSlotF src)
5561 %{
5562 match(Set dst src);
5563
5564 ins_cost(125);
5565 format %{ "movss $dst, $src\t# float stk" %}
5566 ins_encode %{
5567 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
5568 %}
5569 ins_pipe(pipe_slow); // XXX
5570 %}
5571
5572 // Use the same format since predicate() can not be used here.
5573 instruct loadSSD(regD dst, stackSlotD src)
5574 %{
5575 match(Set dst src);
5576
5577 ins_cost(125);
5578 format %{ "movsd $dst, $src\t# double stk" %}
5579 ins_encode %{
5580 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
5581 %}
5582 ins_pipe(pipe_slow); // XXX
5583 %}
5584
5585 // Prefetch instructions for allocation.
5586 // Must be safe to execute with invalid address (cannot fault).
5587
5588 instruct prefetchAlloc( memory mem ) %{
5589 predicate(AllocatePrefetchInstr==3);
5590 match(PrefetchAllocation mem);
5591 ins_cost(125);
5592
5593 format %{ "PREFETCHW $mem\t# Prefetch allocation into level 1 cache and mark modified" %}
5594 ins_encode %{
5595 __ prefetchw($mem$$Address);
5596 %}
5597 ins_pipe(ialu_mem);
5598 %}
5599
5600 instruct prefetchAllocNTA( memory mem ) %{
5601 predicate(AllocatePrefetchInstr==0);
5602 match(PrefetchAllocation mem);
5603 ins_cost(125);
5604
5605 format %{ "PREFETCHNTA $mem\t# Prefetch allocation to non-temporal cache for write" %}
5606 ins_encode %{
5607 __ prefetchnta($mem$$Address);
5608 %}
5609 ins_pipe(ialu_mem);
5610 %}
5611
5612 instruct prefetchAllocT0( memory mem ) %{
5613 predicate(AllocatePrefetchInstr==1);
5614 match(PrefetchAllocation mem);
5615 ins_cost(125);
5616
5617 format %{ "PREFETCHT0 $mem\t# Prefetch allocation to level 1 and 2 caches for write" %}
5618 ins_encode %{
5619 __ prefetcht0($mem$$Address);
5620 %}
5621 ins_pipe(ialu_mem);
5622 %}
5623
5624 instruct prefetchAllocT2( memory mem ) %{
5625 predicate(AllocatePrefetchInstr==2);
5626 match(PrefetchAllocation mem);
5627 ins_cost(125);
5628
5629 format %{ "PREFETCHT2 $mem\t# Prefetch allocation to level 2 cache for write" %}
5630 ins_encode %{
5631 __ prefetcht2($mem$$Address);
5632 %}
5633 ins_pipe(ialu_mem);
5634 %}
5635
5636 //----------Store Instructions-------------------------------------------------
5637
5638 // Store Byte
5639 instruct storeB(memory mem, rRegI src)
5640 %{
5641 match(Set mem (StoreB mem src));
5642
5643 ins_cost(125); // XXX
5644 format %{ "movb $mem, $src\t# byte" %}
5645 opcode(0x88);
5646 ins_encode(REX_breg_mem(src, mem), OpcP, reg_mem(src, mem));
5647 ins_pipe(ialu_mem_reg);
5648 %}
5649
5650 // Store Char/Short
5651 instruct storeC(memory mem, rRegI src)
5652 %{
5653 match(Set mem (StoreC mem src));
5654
5655 ins_cost(125); // XXX
5656 format %{ "movw $mem, $src\t# char/short" %}
5657 opcode(0x89);
5658 ins_encode(SizePrefix, REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5659 ins_pipe(ialu_mem_reg);
5660 %}
5661
5662 // Store Integer
5663 instruct storeI(memory mem, rRegI src)
5664 %{
5665 match(Set mem (StoreI mem src));
5666
5667 ins_cost(125); // XXX
5668 format %{ "movl $mem, $src\t# int" %}
5669 opcode(0x89);
5670 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
5671 ins_pipe(ialu_mem_reg);
5672 %}
5673
5674 // Store Long
5675 instruct storeL(memory mem, rRegL src)
5676 %{
5677 match(Set mem (StoreL mem src));
5678
5679 ins_cost(125); // XXX
5680 format %{ "movq $mem, $src\t# long" %}
5681 opcode(0x89);
5682 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5683 ins_pipe(ialu_mem_reg); // XXX
5684 %}
5685
5686 // Store Pointer
5687 instruct storeP(memory mem, any_RegP src)
5688 %{
5689 match(Set mem (StoreP mem src));
5690
5691 ins_cost(125); // XXX
5692 format %{ "movq $mem, $src\t# ptr" %}
5693 opcode(0x89);
5694 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
5695 ins_pipe(ialu_mem_reg);
5696 %}
5697
5698 instruct storeImmP0(memory mem, immP0 zero)
5699 %{
5700 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5701 match(Set mem (StoreP mem zero));
5702
5703 ins_cost(125); // XXX
5704 format %{ "movq $mem, R12\t# ptr (R12_heapbase==0)" %}
5705 ins_encode %{
5706 __ movq($mem$$Address, r12);
5707 %}
5708 ins_pipe(ialu_mem_reg);
5709 %}
5710
5711 // Store NULL Pointer, mark word, or other simple pointer constant.
5712 instruct storeImmP(memory mem, immP31 src)
5713 %{
5714 match(Set mem (StoreP mem src));
5715
5716 ins_cost(150); // XXX
5717 format %{ "movq $mem, $src\t# ptr" %}
5718 opcode(0xC7); /* C7 /0 */
5719 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5720 ins_pipe(ialu_mem_imm);
5721 %}
5722
5723 // Store Compressed Pointer
5724 instruct storeN(memory mem, rRegN src)
5725 %{
5726 match(Set mem (StoreN mem src));
5727
5728 ins_cost(125); // XXX
5729 format %{ "movl $mem, $src\t# compressed ptr" %}
5730 ins_encode %{
5731 __ movl($mem$$Address, $src$$Register);
5732 %}
5733 ins_pipe(ialu_mem_reg);
5734 %}
5735
5736 instruct storeNKlass(memory mem, rRegN src)
5737 %{
5738 match(Set mem (StoreNKlass mem src));
5739
5740 ins_cost(125); // XXX
5741 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5742 ins_encode %{
5743 __ movl($mem$$Address, $src$$Register);
5744 %}
5745 ins_pipe(ialu_mem_reg);
5746 %}
5747
5748 instruct storeImmN0(memory mem, immN0 zero)
5749 %{
5750 predicate(Universe::narrow_oop_base() == NULL && Universe::narrow_klass_base() == NULL);
5751 match(Set mem (StoreN mem zero));
5752
5753 ins_cost(125); // XXX
5754 format %{ "movl $mem, R12\t# compressed ptr (R12_heapbase==0)" %}
5755 ins_encode %{
5756 __ movl($mem$$Address, r12);
5757 %}
5758 ins_pipe(ialu_mem_reg);
5759 %}
5760
5761 instruct storeImmN(memory mem, immN src)
5762 %{
5763 match(Set mem (StoreN mem src));
5764
5765 ins_cost(150); // XXX
5766 format %{ "movl $mem, $src\t# compressed ptr" %}
5767 ins_encode %{
5768 address con = (address)$src$$constant;
5769 if (con == NULL) {
5770 __ movl($mem$$Address, (int32_t)0);
5771 } else {
5772 __ set_narrow_oop($mem$$Address, (jobject)$src$$constant);
5773 }
5774 %}
5775 ins_pipe(ialu_mem_imm);
5776 %}
5777
5778 instruct storeImmNKlass(memory mem, immNKlass src)
5779 %{
5780 match(Set mem (StoreNKlass mem src));
5781
5782 ins_cost(150); // XXX
5783 format %{ "movl $mem, $src\t# compressed klass ptr" %}
5784 ins_encode %{
5785 __ set_narrow_klass($mem$$Address, (Klass*)$src$$constant);
5786 %}
5787 ins_pipe(ialu_mem_imm);
5788 %}
5789
5790 // Store Integer Immediate
5791 instruct storeImmI0(memory mem, immI0 zero)
5792 %{
5793 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5794 match(Set mem (StoreI mem zero));
5795
5796 ins_cost(125); // XXX
5797 format %{ "movl $mem, R12\t# int (R12_heapbase==0)" %}
5798 ins_encode %{
5799 __ movl($mem$$Address, r12);
5800 %}
5801 ins_pipe(ialu_mem_reg);
5802 %}
5803
5804 instruct storeImmI(memory mem, immI src)
5805 %{
5806 match(Set mem (StoreI mem src));
5807
5808 ins_cost(150);
5809 format %{ "movl $mem, $src\t# int" %}
5810 opcode(0xC7); /* C7 /0 */
5811 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5812 ins_pipe(ialu_mem_imm);
5813 %}
5814
5815 // Store Long Immediate
5816 instruct storeImmL0(memory mem, immL0 zero)
5817 %{
5818 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5819 match(Set mem (StoreL mem zero));
5820
5821 ins_cost(125); // XXX
5822 format %{ "movq $mem, R12\t# long (R12_heapbase==0)" %}
5823 ins_encode %{
5824 __ movq($mem$$Address, r12);
5825 %}
5826 ins_pipe(ialu_mem_reg);
5827 %}
5828
5829 instruct storeImmL(memory mem, immL32 src)
5830 %{
5831 match(Set mem (StoreL mem src));
5832
5833 ins_cost(150);
5834 format %{ "movq $mem, $src\t# long" %}
5835 opcode(0xC7); /* C7 /0 */
5836 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32(src));
5837 ins_pipe(ialu_mem_imm);
5838 %}
5839
5840 // Store Short/Char Immediate
5841 instruct storeImmC0(memory mem, immI0 zero)
5842 %{
5843 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5844 match(Set mem (StoreC mem zero));
5845
5846 ins_cost(125); // XXX
5847 format %{ "movw $mem, R12\t# short/char (R12_heapbase==0)" %}
5848 ins_encode %{
5849 __ movw($mem$$Address, r12);
5850 %}
5851 ins_pipe(ialu_mem_reg);
5852 %}
5853
5854 instruct storeImmI16(memory mem, immI16 src)
5855 %{
5856 predicate(UseStoreImmI16);
5857 match(Set mem (StoreC mem src));
5858
5859 ins_cost(150);
5860 format %{ "movw $mem, $src\t# short/char" %}
5861 opcode(0xC7); /* C7 /0 Same as 32 store immediate with prefix */
5862 ins_encode(SizePrefix, REX_mem(mem), OpcP, RM_opc_mem(0x00, mem),Con16(src));
5863 ins_pipe(ialu_mem_imm);
5864 %}
5865
5866 // Store Byte Immediate
5867 instruct storeImmB0(memory mem, immI0 zero)
5868 %{
5869 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5870 match(Set mem (StoreB mem zero));
5871
5872 ins_cost(125); // XXX
5873 format %{ "movb $mem, R12\t# short/char (R12_heapbase==0)" %}
5874 ins_encode %{
5875 __ movb($mem$$Address, r12);
5876 %}
5877 ins_pipe(ialu_mem_reg);
5878 %}
5879
5880 instruct storeImmB(memory mem, immI8 src)
5881 %{
5882 match(Set mem (StoreB mem src));
5883
5884 ins_cost(150); // XXX
5885 format %{ "movb $mem, $src\t# byte" %}
5886 opcode(0xC6); /* C6 /0 */
5887 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5888 ins_pipe(ialu_mem_imm);
5889 %}
5890
5891 // Store CMS card-mark Immediate
5892 instruct storeImmCM0_reg(memory mem, immI0 zero)
5893 %{
5894 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5895 match(Set mem (StoreCM mem zero));
5896
5897 ins_cost(125); // XXX
5898 format %{ "movb $mem, R12\t# CMS card-mark byte 0 (R12_heapbase==0)" %}
5899 ins_encode %{
5900 __ movb($mem$$Address, r12);
5901 %}
5902 ins_pipe(ialu_mem_reg);
5903 %}
5904
5905 instruct storeImmCM0(memory mem, immI0 src)
5906 %{
5907 match(Set mem (StoreCM mem src));
5908
5909 ins_cost(150); // XXX
5910 format %{ "movb $mem, $src\t# CMS card-mark byte 0" %}
5911 opcode(0xC6); /* C6 /0 */
5912 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con8or32(src));
5913 ins_pipe(ialu_mem_imm);
5914 %}
5915
5916 // Store Float
5917 instruct storeF(memory mem, regF src)
5918 %{
5919 match(Set mem (StoreF mem src));
5920
5921 ins_cost(95); // XXX
5922 format %{ "movss $mem, $src\t# float" %}
5923 ins_encode %{
5924 __ movflt($mem$$Address, $src$$XMMRegister);
5925 %}
5926 ins_pipe(pipe_slow); // XXX
5927 %}
5928
5929 // Store immediate Float value (it is faster than store from XMM register)
5930 instruct storeF0(memory mem, immF0 zero)
5931 %{
5932 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5933 match(Set mem (StoreF mem zero));
5934
5935 ins_cost(25); // XXX
5936 format %{ "movl $mem, R12\t# float 0. (R12_heapbase==0)" %}
5937 ins_encode %{
5938 __ movl($mem$$Address, r12);
5939 %}
5940 ins_pipe(ialu_mem_reg);
5941 %}
5942
5943 instruct storeF_imm(memory mem, immF src)
5944 %{
5945 match(Set mem (StoreF mem src));
5946
5947 ins_cost(50);
5948 format %{ "movl $mem, $src\t# float" %}
5949 opcode(0xC7); /* C7 /0 */
5950 ins_encode(REX_mem(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5951 ins_pipe(ialu_mem_imm);
5952 %}
5953
5954 // Store Double
5955 instruct storeD(memory mem, regD src)
5956 %{
5957 match(Set mem (StoreD mem src));
5958
5959 ins_cost(95); // XXX
5960 format %{ "movsd $mem, $src\t# double" %}
5961 ins_encode %{
5962 __ movdbl($mem$$Address, $src$$XMMRegister);
5963 %}
5964 ins_pipe(pipe_slow); // XXX
5965 %}
5966
5967 // Store immediate double 0.0 (it is faster than store from XMM register)
5968 instruct storeD0_imm(memory mem, immD0 src)
5969 %{
5970 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
5971 match(Set mem (StoreD mem src));
5972
5973 ins_cost(50);
5974 format %{ "movq $mem, $src\t# double 0." %}
5975 opcode(0xC7); /* C7 /0 */
5976 ins_encode(REX_mem_wide(mem), OpcP, RM_opc_mem(0x00, mem), Con32F_as_bits(src));
5977 ins_pipe(ialu_mem_imm);
5978 %}
5979
5980 instruct storeD0(memory mem, immD0 zero)
5981 %{
5982 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
5983 match(Set mem (StoreD mem zero));
5984
5985 ins_cost(25); // XXX
5986 format %{ "movq $mem, R12\t# double 0. (R12_heapbase==0)" %}
5987 ins_encode %{
5988 __ movq($mem$$Address, r12);
5989 %}
5990 ins_pipe(ialu_mem_reg);
5991 %}
5992
5993 instruct storeSSI(stackSlotI dst, rRegI src)
5994 %{
5995 match(Set dst src);
5996
5997 ins_cost(100);
5998 format %{ "movl $dst, $src\t# int stk" %}
5999 opcode(0x89);
6000 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6001 ins_pipe( ialu_mem_reg );
6002 %}
6003
6004 instruct storeSSL(stackSlotL dst, rRegL src)
6005 %{
6006 match(Set dst src);
6007
6008 ins_cost(100);
6009 format %{ "movq $dst, $src\t# long stk" %}
6010 opcode(0x89);
6011 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6012 ins_pipe(ialu_mem_reg);
6013 %}
6014
6015 instruct storeSSP(stackSlotP dst, rRegP src)
6016 %{
6017 match(Set dst src);
6018
6019 ins_cost(100);
6020 format %{ "movq $dst, $src\t# ptr stk" %}
6021 opcode(0x89);
6022 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
6023 ins_pipe(ialu_mem_reg);
6024 %}
6025
6026 instruct storeSSF(stackSlotF dst, regF src)
6027 %{
6028 match(Set dst src);
6029
6030 ins_cost(95); // XXX
6031 format %{ "movss $dst, $src\t# float stk" %}
6032 ins_encode %{
6033 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
6034 %}
6035 ins_pipe(pipe_slow); // XXX
6036 %}
6037
6038 instruct storeSSD(stackSlotD dst, regD src)
6039 %{
6040 match(Set dst src);
6041
6042 ins_cost(95); // XXX
6043 format %{ "movsd $dst, $src\t# double stk" %}
6044 ins_encode %{
6045 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
6046 %}
6047 ins_pipe(pipe_slow); // XXX
6048 %}
6049
6050 //----------BSWAP Instructions-------------------------------------------------
6051 instruct bytes_reverse_int(rRegI dst) %{
6052 match(Set dst (ReverseBytesI dst));
6053
6054 format %{ "bswapl $dst" %}
6055 opcode(0x0F, 0xC8); /*Opcode 0F /C8 */
6056 ins_encode( REX_reg(dst), OpcP, opc2_reg(dst) );
6057 ins_pipe( ialu_reg );
6058 %}
6059
6060 instruct bytes_reverse_long(rRegL dst) %{
6061 match(Set dst (ReverseBytesL dst));
6062
6063 format %{ "bswapq $dst" %}
6064 opcode(0x0F, 0xC8); /* Opcode 0F /C8 */
6065 ins_encode( REX_reg_wide(dst), OpcP, opc2_reg(dst) );
6066 ins_pipe( ialu_reg);
6067 %}
6068
6069 instruct bytes_reverse_unsigned_short(rRegI dst, rFlagsReg cr) %{
6070 match(Set dst (ReverseBytesUS dst));
6071 effect(KILL cr);
6072
6073 format %{ "bswapl $dst\n\t"
6074 "shrl $dst,16\n\t" %}
6075 ins_encode %{
6076 __ bswapl($dst$$Register);
6077 __ shrl($dst$$Register, 16);
6078 %}
6079 ins_pipe( ialu_reg );
6080 %}
6081
6082 instruct bytes_reverse_short(rRegI dst, rFlagsReg cr) %{
6083 match(Set dst (ReverseBytesS dst));
6084 effect(KILL cr);
6085
6086 format %{ "bswapl $dst\n\t"
6087 "sar $dst,16\n\t" %}
6088 ins_encode %{
6089 __ bswapl($dst$$Register);
6090 __ sarl($dst$$Register, 16);
6091 %}
6092 ins_pipe( ialu_reg );
6093 %}
6094
6095 //---------- Zeros Count Instructions ------------------------------------------
6096
6097 instruct countLeadingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6098 predicate(UseCountLeadingZerosInstruction);
6099 match(Set dst (CountLeadingZerosI src));
6100 effect(KILL cr);
6101
6102 format %{ "lzcntl $dst, $src\t# count leading zeros (int)" %}
6103 ins_encode %{
6104 __ lzcntl($dst$$Register, $src$$Register);
6105 %}
6106 ins_pipe(ialu_reg);
6107 %}
6108
6109 instruct countLeadingZerosI_bsr(rRegI dst, rRegI src, rFlagsReg cr) %{
6110 predicate(!UseCountLeadingZerosInstruction);
6111 match(Set dst (CountLeadingZerosI src));
6112 effect(KILL cr);
6113
6114 format %{ "bsrl $dst, $src\t# count leading zeros (int)\n\t"
6115 "jnz skip\n\t"
6116 "movl $dst, -1\n"
6117 "skip:\n\t"
6118 "negl $dst\n\t"
6119 "addl $dst, 31" %}
6120 ins_encode %{
6121 Register Rdst = $dst$$Register;
6122 Register Rsrc = $src$$Register;
6123 Label skip;
6124 __ bsrl(Rdst, Rsrc);
6125 __ jccb(Assembler::notZero, skip);
6126 __ movl(Rdst, -1);
6127 __ bind(skip);
6128 __ negl(Rdst);
6129 __ addl(Rdst, BitsPerInt - 1);
6130 %}
6131 ins_pipe(ialu_reg);
6132 %}
6133
6134 instruct countLeadingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6135 predicate(UseCountLeadingZerosInstruction);
6136 match(Set dst (CountLeadingZerosL src));
6137 effect(KILL cr);
6138
6139 format %{ "lzcntq $dst, $src\t# count leading zeros (long)" %}
6140 ins_encode %{
6141 __ lzcntq($dst$$Register, $src$$Register);
6142 %}
6143 ins_pipe(ialu_reg);
6144 %}
6145
6146 instruct countLeadingZerosL_bsr(rRegI dst, rRegL src, rFlagsReg cr) %{
6147 predicate(!UseCountLeadingZerosInstruction);
6148 match(Set dst (CountLeadingZerosL src));
6149 effect(KILL cr);
6150
6151 format %{ "bsrq $dst, $src\t# count leading zeros (long)\n\t"
6152 "jnz skip\n\t"
6153 "movl $dst, -1\n"
6154 "skip:\n\t"
6155 "negl $dst\n\t"
6156 "addl $dst, 63" %}
6157 ins_encode %{
6158 Register Rdst = $dst$$Register;
6159 Register Rsrc = $src$$Register;
6160 Label skip;
6161 __ bsrq(Rdst, Rsrc);
6162 __ jccb(Assembler::notZero, skip);
6163 __ movl(Rdst, -1);
6164 __ bind(skip);
6165 __ negl(Rdst);
6166 __ addl(Rdst, BitsPerLong - 1);
6167 %}
6168 ins_pipe(ialu_reg);
6169 %}
6170
6171 instruct countTrailingZerosI(rRegI dst, rRegI src, rFlagsReg cr) %{
6172 predicate(UseCountTrailingZerosInstruction);
6173 match(Set dst (CountTrailingZerosI src));
6174 effect(KILL cr);
6175
6176 format %{ "tzcntl $dst, $src\t# count trailing zeros (int)" %}
6177 ins_encode %{
6178 __ tzcntl($dst$$Register, $src$$Register);
6179 %}
6180 ins_pipe(ialu_reg);
6181 %}
6182
6183 instruct countTrailingZerosI_bsf(rRegI dst, rRegI src, rFlagsReg cr) %{
6184 predicate(!UseCountTrailingZerosInstruction);
6185 match(Set dst (CountTrailingZerosI src));
6186 effect(KILL cr);
6187
6188 format %{ "bsfl $dst, $src\t# count trailing zeros (int)\n\t"
6189 "jnz done\n\t"
6190 "movl $dst, 32\n"
6191 "done:" %}
6192 ins_encode %{
6193 Register Rdst = $dst$$Register;
6194 Label done;
6195 __ bsfl(Rdst, $src$$Register);
6196 __ jccb(Assembler::notZero, done);
6197 __ movl(Rdst, BitsPerInt);
6198 __ bind(done);
6199 %}
6200 ins_pipe(ialu_reg);
6201 %}
6202
6203 instruct countTrailingZerosL(rRegI dst, rRegL src, rFlagsReg cr) %{
6204 predicate(UseCountTrailingZerosInstruction);
6205 match(Set dst (CountTrailingZerosL src));
6206 effect(KILL cr);
6207
6208 format %{ "tzcntq $dst, $src\t# count trailing zeros (long)" %}
6209 ins_encode %{
6210 __ tzcntq($dst$$Register, $src$$Register);
6211 %}
6212 ins_pipe(ialu_reg);
6213 %}
6214
6215 instruct countTrailingZerosL_bsf(rRegI dst, rRegL src, rFlagsReg cr) %{
6216 predicate(!UseCountTrailingZerosInstruction);
6217 match(Set dst (CountTrailingZerosL src));
6218 effect(KILL cr);
6219
6220 format %{ "bsfq $dst, $src\t# count trailing zeros (long)\n\t"
6221 "jnz done\n\t"
6222 "movl $dst, 64\n"
6223 "done:" %}
6224 ins_encode %{
6225 Register Rdst = $dst$$Register;
6226 Label done;
6227 __ bsfq(Rdst, $src$$Register);
6228 __ jccb(Assembler::notZero, done);
6229 __ movl(Rdst, BitsPerLong);
6230 __ bind(done);
6231 %}
6232 ins_pipe(ialu_reg);
6233 %}
6234
6235
6236 //---------- Population Count Instructions -------------------------------------
6237
6238 instruct popCountI(rRegI dst, rRegI src, rFlagsReg cr) %{
6239 predicate(UsePopCountInstruction);
6240 match(Set dst (PopCountI src));
6241 effect(KILL cr);
6242
6243 format %{ "popcnt $dst, $src" %}
6244 ins_encode %{
6245 __ popcntl($dst$$Register, $src$$Register);
6246 %}
6247 ins_pipe(ialu_reg);
6248 %}
6249
6250 instruct popCountI_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6251 predicate(UsePopCountInstruction);
6252 match(Set dst (PopCountI (LoadI mem)));
6253 effect(KILL cr);
6254
6255 format %{ "popcnt $dst, $mem" %}
6256 ins_encode %{
6257 __ popcntl($dst$$Register, $mem$$Address);
6258 %}
6259 ins_pipe(ialu_reg);
6260 %}
6261
6262 // Note: Long.bitCount(long) returns an int.
6263 instruct popCountL(rRegI dst, rRegL src, rFlagsReg cr) %{
6264 predicate(UsePopCountInstruction);
6265 match(Set dst (PopCountL src));
6266 effect(KILL cr);
6267
6268 format %{ "popcnt $dst, $src" %}
6269 ins_encode %{
6270 __ popcntq($dst$$Register, $src$$Register);
6271 %}
6272 ins_pipe(ialu_reg);
6273 %}
6274
6275 // Note: Long.bitCount(long) returns an int.
6276 instruct popCountL_mem(rRegI dst, memory mem, rFlagsReg cr) %{
6277 predicate(UsePopCountInstruction);
6278 match(Set dst (PopCountL (LoadL mem)));
6279 effect(KILL cr);
6280
6281 format %{ "popcnt $dst, $mem" %}
6282 ins_encode %{
6283 __ popcntq($dst$$Register, $mem$$Address);
6284 %}
6285 ins_pipe(ialu_reg);
6286 %}
6287
6288
6289 //----------MemBar Instructions-----------------------------------------------
6290 // Memory barrier flavors
6291
6292 instruct membar_acquire()
6293 %{
6294 match(MemBarAcquire);
6295 match(LoadFence);
6296 ins_cost(0);
6297
6298 size(0);
6299 format %{ "MEMBAR-acquire ! (empty encoding)" %}
6300 ins_encode();
6301 ins_pipe(empty);
6302 %}
6303
6304 instruct membar_acquire_lock()
6305 %{
6306 match(MemBarAcquireLock);
6307 ins_cost(0);
6308
6309 size(0);
6310 format %{ "MEMBAR-acquire (prior CMPXCHG in FastLock so empty encoding)" %}
6311 ins_encode();
6312 ins_pipe(empty);
6313 %}
6314
6315 instruct membar_release()
6316 %{
6317 match(MemBarRelease);
6318 match(StoreFence);
6319 ins_cost(0);
6320
6321 size(0);
6322 format %{ "MEMBAR-release ! (empty encoding)" %}
6323 ins_encode();
6324 ins_pipe(empty);
6325 %}
6326
6327 instruct membar_release_lock()
6328 %{
6329 match(MemBarReleaseLock);
6330 ins_cost(0);
6331
6332 size(0);
6333 format %{ "MEMBAR-release (a FastUnlock follows so empty encoding)" %}
6334 ins_encode();
6335 ins_pipe(empty);
6336 %}
6337
6338 instruct membar_volatile(rFlagsReg cr) %{
6339 match(MemBarVolatile);
6340 effect(KILL cr);
6341 ins_cost(400);
6342
6343 format %{
6344 $$template
6345 if (os::is_MP()) {
6346 $$emit$$"lock addl [rsp + #0], 0\t! membar_volatile"
6347 } else {
6348 $$emit$$"MEMBAR-volatile ! (empty encoding)"
6349 }
6350 %}
6351 ins_encode %{
6352 __ membar(Assembler::StoreLoad);
6353 %}
6354 ins_pipe(pipe_slow);
6355 %}
6356
6357 instruct unnecessary_membar_volatile()
6358 %{
6359 match(MemBarVolatile);
6360 predicate(Matcher::post_store_load_barrier(n));
6361 ins_cost(0);
6362
6363 size(0);
6364 format %{ "MEMBAR-volatile (unnecessary so empty encoding)" %}
6365 ins_encode();
6366 ins_pipe(empty);
6367 %}
6368
6369 instruct membar_storestore() %{
6370 match(MemBarStoreStore);
6371 ins_cost(0);
6372
6373 size(0);
6374 format %{ "MEMBAR-storestore (empty encoding)" %}
6375 ins_encode( );
6376 ins_pipe(empty);
6377 %}
6378
6379 //----------Move Instructions--------------------------------------------------
6380
6381 instruct castX2P(rRegP dst, rRegL src)
6382 %{
6383 match(Set dst (CastX2P src));
6384
6385 format %{ "movq $dst, $src\t# long->ptr" %}
6386 ins_encode %{
6387 if ($dst$$reg != $src$$reg) {
6388 __ movptr($dst$$Register, $src$$Register);
6389 }
6390 %}
6391 ins_pipe(ialu_reg_reg); // XXX
6392 %}
6393
6394 instruct castP2X(rRegL dst, rRegP src)
6395 %{
6396 match(Set dst (CastP2X src));
6397
6398 format %{ "movq $dst, $src\t# ptr -> long" %}
6399 ins_encode %{
6400 if ($dst$$reg != $src$$reg) {
6401 __ movptr($dst$$Register, $src$$Register);
6402 }
6403 %}
6404 ins_pipe(ialu_reg_reg); // XXX
6405 %}
6406
6407 // Convert oop into int for vectors alignment masking
6408 instruct convP2I(rRegI dst, rRegP src)
6409 %{
6410 match(Set dst (ConvL2I (CastP2X src)));
6411
6412 format %{ "movl $dst, $src\t# ptr -> int" %}
6413 ins_encode %{
6414 __ movl($dst$$Register, $src$$Register);
6415 %}
6416 ins_pipe(ialu_reg_reg); // XXX
6417 %}
6418
6419 // Convert compressed oop into int for vectors alignment masking
6420 // in case of 32bit oops (heap < 4Gb).
6421 instruct convN2I(rRegI dst, rRegN src)
6422 %{
6423 predicate(Universe::narrow_oop_shift() == 0);
6424 match(Set dst (ConvL2I (CastP2X (DecodeN src))));
6425
6426 format %{ "movl $dst, $src\t# compressed ptr -> int" %}
6427 ins_encode %{
6428 __ movl($dst$$Register, $src$$Register);
6429 %}
6430 ins_pipe(ialu_reg_reg); // XXX
6431 %}
6432
6433 // Convert oop pointer into compressed form
6434 instruct encodeHeapOop(rRegN dst, rRegP src, rFlagsReg cr) %{
6435 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6436 match(Set dst (EncodeP src));
6437 effect(KILL cr);
6438 format %{ "encode_heap_oop $dst,$src" %}
6439 ins_encode %{
6440 Register s = $src$$Register;
6441 Register d = $dst$$Register;
6442 if (s != d) {
6443 __ movq(d, s);
6444 }
6445 __ encode_heap_oop(d);
6446 %}
6447 ins_pipe(ialu_reg_long);
6448 %}
6449
6450 instruct encodeHeapOop_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6451 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6452 match(Set dst (EncodeP src));
6453 effect(KILL cr);
6454 format %{ "encode_heap_oop_not_null $dst,$src" %}
6455 ins_encode %{
6456 __ encode_heap_oop_not_null($dst$$Register, $src$$Register);
6457 %}
6458 ins_pipe(ialu_reg_long);
6459 %}
6460
6461 instruct decodeHeapOop(rRegP dst, rRegN src, rFlagsReg cr) %{
6462 predicate(n->bottom_type()->is_ptr()->ptr() != TypePtr::NotNull &&
6463 n->bottom_type()->is_ptr()->ptr() != TypePtr::Constant);
6464 match(Set dst (DecodeN src));
6465 effect(KILL cr);
6466 format %{ "decode_heap_oop $dst,$src" %}
6467 ins_encode %{
6468 Register s = $src$$Register;
6469 Register d = $dst$$Register;
6470 if (s != d) {
6471 __ movq(d, s);
6472 }
6473 __ decode_heap_oop(d);
6474 %}
6475 ins_pipe(ialu_reg_long);
6476 %}
6477
6478 instruct decodeHeapOop_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6479 predicate(n->bottom_type()->is_ptr()->ptr() == TypePtr::NotNull ||
6480 n->bottom_type()->is_ptr()->ptr() == TypePtr::Constant);
6481 match(Set dst (DecodeN src));
6482 effect(KILL cr);
6483 format %{ "decode_heap_oop_not_null $dst,$src" %}
6484 ins_encode %{
6485 Register s = $src$$Register;
6486 Register d = $dst$$Register;
6487 if (s != d) {
6488 __ decode_heap_oop_not_null(d, s);
6489 } else {
6490 __ decode_heap_oop_not_null(d);
6491 }
6492 %}
6493 ins_pipe(ialu_reg_long);
6494 %}
6495
6496 instruct encodeKlass_not_null(rRegN dst, rRegP src, rFlagsReg cr) %{
6497 match(Set dst (EncodePKlass src));
6498 effect(KILL cr);
6499 format %{ "encode_klass_not_null $dst,$src" %}
6500 ins_encode %{
6501 __ encode_klass_not_null($dst$$Register, $src$$Register);
6502 %}
6503 ins_pipe(ialu_reg_long);
6504 %}
6505
6506 instruct decodeKlass_not_null(rRegP dst, rRegN src, rFlagsReg cr) %{
6507 match(Set dst (DecodeNKlass src));
6508 effect(KILL cr);
6509 format %{ "decode_klass_not_null $dst,$src" %}
6510 ins_encode %{
6511 Register s = $src$$Register;
6512 Register d = $dst$$Register;
6513 if (s != d) {
6514 __ decode_klass_not_null(d, s);
6515 } else {
6516 __ decode_klass_not_null(d);
6517 }
6518 %}
6519 ins_pipe(ialu_reg_long);
6520 %}
6521
6522
6523 //----------Conditional Move---------------------------------------------------
6524 // Jump
6525 // dummy instruction for generating temp registers
6526 instruct jumpXtnd_offset(rRegL switch_val, immI2 shift, rRegI dest) %{
6527 match(Jump (LShiftL switch_val shift));
6528 ins_cost(350);
6529 predicate(false);
6530 effect(TEMP dest);
6531
6532 format %{ "leaq $dest, [$constantaddress]\n\t"
6533 "jmp [$dest + $switch_val << $shift]\n\t" %}
6534 ins_encode %{
6535 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6536 // to do that and the compiler is using that register as one it can allocate.
6537 // So we build it all by hand.
6538 // Address index(noreg, switch_reg, (Address::ScaleFactor)$shift$$constant);
6539 // ArrayAddress dispatch(table, index);
6540 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant);
6541 __ lea($dest$$Register, $constantaddress);
6542 __ jmp(dispatch);
6543 %}
6544 ins_pipe(pipe_jmp);
6545 %}
6546
6547 instruct jumpXtnd_addr(rRegL switch_val, immI2 shift, immL32 offset, rRegI dest) %{
6548 match(Jump (AddL (LShiftL switch_val shift) offset));
6549 ins_cost(350);
6550 effect(TEMP dest);
6551
6552 format %{ "leaq $dest, [$constantaddress]\n\t"
6553 "jmp [$dest + $switch_val << $shift + $offset]\n\t" %}
6554 ins_encode %{
6555 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6556 // to do that and the compiler is using that register as one it can allocate.
6557 // So we build it all by hand.
6558 // Address index(noreg, switch_reg, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6559 // ArrayAddress dispatch(table, index);
6560 Address dispatch($dest$$Register, $switch_val$$Register, (Address::ScaleFactor) $shift$$constant, (int) $offset$$constant);
6561 __ lea($dest$$Register, $constantaddress);
6562 __ jmp(dispatch);
6563 %}
6564 ins_pipe(pipe_jmp);
6565 %}
6566
6567 instruct jumpXtnd(rRegL switch_val, rRegI dest) %{
6568 match(Jump switch_val);
6569 ins_cost(350);
6570 effect(TEMP dest);
6571
6572 format %{ "leaq $dest, [$constantaddress]\n\t"
6573 "jmp [$dest + $switch_val]\n\t" %}
6574 ins_encode %{
6575 // We could use jump(ArrayAddress) except that the macro assembler needs to use r10
6576 // to do that and the compiler is using that register as one it can allocate.
6577 // So we build it all by hand.
6578 // Address index(noreg, switch_reg, Address::times_1);
6579 // ArrayAddress dispatch(table, index);
6580 Address dispatch($dest$$Register, $switch_val$$Register, Address::times_1);
6581 __ lea($dest$$Register, $constantaddress);
6582 __ jmp(dispatch);
6583 %}
6584 ins_pipe(pipe_jmp);
6585 %}
6586
6587 // Conditional move
6588 instruct cmovI_reg(rRegI dst, rRegI src, rFlagsReg cr, cmpOp cop)
6589 %{
6590 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6591
6592 ins_cost(200); // XXX
6593 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6594 opcode(0x0F, 0x40);
6595 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6596 ins_pipe(pipe_cmov_reg);
6597 %}
6598
6599 instruct cmovI_regU(cmpOpU cop, rFlagsRegU cr, rRegI dst, rRegI src) %{
6600 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6601
6602 ins_cost(200); // XXX
6603 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6604 opcode(0x0F, 0x40);
6605 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6606 ins_pipe(pipe_cmov_reg);
6607 %}
6608
6609 instruct cmovI_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, rRegI src) %{
6610 match(Set dst (CMoveI (Binary cop cr) (Binary dst src)));
6611 ins_cost(200);
6612 expand %{
6613 cmovI_regU(cop, cr, dst, src);
6614 %}
6615 %}
6616
6617 // Conditional move
6618 instruct cmovI_mem(cmpOp cop, rFlagsReg cr, rRegI dst, memory src) %{
6619 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6620
6621 ins_cost(250); // XXX
6622 format %{ "cmovl$cop $dst, $src\t# signed, int" %}
6623 opcode(0x0F, 0x40);
6624 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6625 ins_pipe(pipe_cmov_mem);
6626 %}
6627
6628 // Conditional move
6629 instruct cmovI_memU(cmpOpU cop, rFlagsRegU cr, rRegI dst, memory src)
6630 %{
6631 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6632
6633 ins_cost(250); // XXX
6634 format %{ "cmovl$cop $dst, $src\t# unsigned, int" %}
6635 opcode(0x0F, 0x40);
6636 ins_encode(REX_reg_mem(dst, src), enc_cmov(cop), reg_mem(dst, src));
6637 ins_pipe(pipe_cmov_mem);
6638 %}
6639
6640 instruct cmovI_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegI dst, memory src) %{
6641 match(Set dst (CMoveI (Binary cop cr) (Binary dst (LoadI src))));
6642 ins_cost(250);
6643 expand %{
6644 cmovI_memU(cop, cr, dst, src);
6645 %}
6646 %}
6647
6648 // Conditional move
6649 instruct cmovN_reg(rRegN dst, rRegN src, rFlagsReg cr, cmpOp cop)
6650 %{
6651 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6652
6653 ins_cost(200); // XXX
6654 format %{ "cmovl$cop $dst, $src\t# signed, compressed ptr" %}
6655 opcode(0x0F, 0x40);
6656 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6657 ins_pipe(pipe_cmov_reg);
6658 %}
6659
6660 // Conditional move
6661 instruct cmovN_regU(cmpOpU cop, rFlagsRegU cr, rRegN dst, rRegN src)
6662 %{
6663 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6664
6665 ins_cost(200); // XXX
6666 format %{ "cmovl$cop $dst, $src\t# unsigned, compressed ptr" %}
6667 opcode(0x0F, 0x40);
6668 ins_encode(REX_reg_reg(dst, src), enc_cmov(cop), reg_reg(dst, src));
6669 ins_pipe(pipe_cmov_reg);
6670 %}
6671
6672 instruct cmovN_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegN dst, rRegN src) %{
6673 match(Set dst (CMoveN (Binary cop cr) (Binary dst src)));
6674 ins_cost(200);
6675 expand %{
6676 cmovN_regU(cop, cr, dst, src);
6677 %}
6678 %}
6679
6680 // Conditional move
6681 instruct cmovP_reg(rRegP dst, rRegP src, rFlagsReg cr, cmpOp cop)
6682 %{
6683 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6684
6685 ins_cost(200); // XXX
6686 format %{ "cmovq$cop $dst, $src\t# signed, ptr" %}
6687 opcode(0x0F, 0x40);
6688 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6689 ins_pipe(pipe_cmov_reg); // XXX
6690 %}
6691
6692 // Conditional move
6693 instruct cmovP_regU(cmpOpU cop, rFlagsRegU cr, rRegP dst, rRegP src)
6694 %{
6695 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6696
6697 ins_cost(200); // XXX
6698 format %{ "cmovq$cop $dst, $src\t# unsigned, ptr" %}
6699 opcode(0x0F, 0x40);
6700 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6701 ins_pipe(pipe_cmov_reg); // XXX
6702 %}
6703
6704 instruct cmovP_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegP dst, rRegP src) %{
6705 match(Set dst (CMoveP (Binary cop cr) (Binary dst src)));
6706 ins_cost(200);
6707 expand %{
6708 cmovP_regU(cop, cr, dst, src);
6709 %}
6710 %}
6711
6712 // DISABLED: Requires the ADLC to emit a bottom_type call that
6713 // correctly meets the two pointer arguments; one is an incoming
6714 // register but the other is a memory operand. ALSO appears to
6715 // be buggy with implicit null checks.
6716 //
6717 //// Conditional move
6718 //instruct cmovP_mem(cmpOp cop, rFlagsReg cr, rRegP dst, memory src)
6719 //%{
6720 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6721 // ins_cost(250);
6722 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6723 // opcode(0x0F,0x40);
6724 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6725 // ins_pipe( pipe_cmov_mem );
6726 //%}
6727 //
6728 //// Conditional move
6729 //instruct cmovP_memU(cmpOpU cop, rFlagsRegU cr, rRegP dst, memory src)
6730 //%{
6731 // match(Set dst (CMoveP (Binary cop cr) (Binary dst (LoadP src))));
6732 // ins_cost(250);
6733 // format %{ "CMOV$cop $dst,$src\t# ptr" %}
6734 // opcode(0x0F,0x40);
6735 // ins_encode( enc_cmov(cop), reg_mem( dst, src ) );
6736 // ins_pipe( pipe_cmov_mem );
6737 //%}
6738
6739 instruct cmovL_reg(cmpOp cop, rFlagsReg cr, rRegL dst, rRegL src)
6740 %{
6741 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6742
6743 ins_cost(200); // XXX
6744 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6745 opcode(0x0F, 0x40);
6746 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6747 ins_pipe(pipe_cmov_reg); // XXX
6748 %}
6749
6750 instruct cmovL_mem(cmpOp cop, rFlagsReg cr, rRegL dst, memory src)
6751 %{
6752 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6753
6754 ins_cost(200); // XXX
6755 format %{ "cmovq$cop $dst, $src\t# signed, long" %}
6756 opcode(0x0F, 0x40);
6757 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6758 ins_pipe(pipe_cmov_mem); // XXX
6759 %}
6760
6761 instruct cmovL_regU(cmpOpU cop, rFlagsRegU cr, rRegL dst, rRegL src)
6762 %{
6763 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6764
6765 ins_cost(200); // XXX
6766 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6767 opcode(0x0F, 0x40);
6768 ins_encode(REX_reg_reg_wide(dst, src), enc_cmov(cop), reg_reg(dst, src));
6769 ins_pipe(pipe_cmov_reg); // XXX
6770 %}
6771
6772 instruct cmovL_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, rRegL src) %{
6773 match(Set dst (CMoveL (Binary cop cr) (Binary dst src)));
6774 ins_cost(200);
6775 expand %{
6776 cmovL_regU(cop, cr, dst, src);
6777 %}
6778 %}
6779
6780 instruct cmovL_memU(cmpOpU cop, rFlagsRegU cr, rRegL dst, memory src)
6781 %{
6782 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6783
6784 ins_cost(200); // XXX
6785 format %{ "cmovq$cop $dst, $src\t# unsigned, long" %}
6786 opcode(0x0F, 0x40);
6787 ins_encode(REX_reg_mem_wide(dst, src), enc_cmov(cop), reg_mem(dst, src));
6788 ins_pipe(pipe_cmov_mem); // XXX
6789 %}
6790
6791 instruct cmovL_memUCF(cmpOpUCF cop, rFlagsRegUCF cr, rRegL dst, memory src) %{
6792 match(Set dst (CMoveL (Binary cop cr) (Binary dst (LoadL src))));
6793 ins_cost(200);
6794 expand %{
6795 cmovL_memU(cop, cr, dst, src);
6796 %}
6797 %}
6798
6799 instruct cmovF_reg(cmpOp cop, rFlagsReg cr, regF dst, regF src)
6800 %{
6801 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6802
6803 ins_cost(200); // XXX
6804 format %{ "jn$cop skip\t# signed cmove float\n\t"
6805 "movss $dst, $src\n"
6806 "skip:" %}
6807 ins_encode %{
6808 Label Lskip;
6809 // Invert sense of branch from sense of CMOV
6810 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6811 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6812 __ bind(Lskip);
6813 %}
6814 ins_pipe(pipe_slow);
6815 %}
6816
6817 // instruct cmovF_mem(cmpOp cop, rFlagsReg cr, regF dst, memory src)
6818 // %{
6819 // match(Set dst (CMoveF (Binary cop cr) (Binary dst (LoadL src))));
6820
6821 // ins_cost(200); // XXX
6822 // format %{ "jn$cop skip\t# signed cmove float\n\t"
6823 // "movss $dst, $src\n"
6824 // "skip:" %}
6825 // ins_encode(enc_cmovf_mem_branch(cop, dst, src));
6826 // ins_pipe(pipe_slow);
6827 // %}
6828
6829 instruct cmovF_regU(cmpOpU cop, rFlagsRegU cr, regF dst, regF src)
6830 %{
6831 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6832
6833 ins_cost(200); // XXX
6834 format %{ "jn$cop skip\t# unsigned cmove float\n\t"
6835 "movss $dst, $src\n"
6836 "skip:" %}
6837 ins_encode %{
6838 Label Lskip;
6839 // Invert sense of branch from sense of CMOV
6840 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6841 __ movflt($dst$$XMMRegister, $src$$XMMRegister);
6842 __ bind(Lskip);
6843 %}
6844 ins_pipe(pipe_slow);
6845 %}
6846
6847 instruct cmovF_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regF dst, regF src) %{
6848 match(Set dst (CMoveF (Binary cop cr) (Binary dst src)));
6849 ins_cost(200);
6850 expand %{
6851 cmovF_regU(cop, cr, dst, src);
6852 %}
6853 %}
6854
6855 instruct cmovD_reg(cmpOp cop, rFlagsReg cr, regD dst, regD src)
6856 %{
6857 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6858
6859 ins_cost(200); // XXX
6860 format %{ "jn$cop skip\t# signed cmove double\n\t"
6861 "movsd $dst, $src\n"
6862 "skip:" %}
6863 ins_encode %{
6864 Label Lskip;
6865 // Invert sense of branch from sense of CMOV
6866 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6867 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6868 __ bind(Lskip);
6869 %}
6870 ins_pipe(pipe_slow);
6871 %}
6872
6873 instruct cmovD_regU(cmpOpU cop, rFlagsRegU cr, regD dst, regD src)
6874 %{
6875 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6876
6877 ins_cost(200); // XXX
6878 format %{ "jn$cop skip\t# unsigned cmove double\n\t"
6879 "movsd $dst, $src\n"
6880 "skip:" %}
6881 ins_encode %{
6882 Label Lskip;
6883 // Invert sense of branch from sense of CMOV
6884 __ jccb((Assembler::Condition)($cop$$cmpcode^1), Lskip);
6885 __ movdbl($dst$$XMMRegister, $src$$XMMRegister);
6886 __ bind(Lskip);
6887 %}
6888 ins_pipe(pipe_slow);
6889 %}
6890
6891 instruct cmovD_regUCF(cmpOpUCF cop, rFlagsRegUCF cr, regD dst, regD src) %{
6892 match(Set dst (CMoveD (Binary cop cr) (Binary dst src)));
6893 ins_cost(200);
6894 expand %{
6895 cmovD_regU(cop, cr, dst, src);
6896 %}
6897 %}
6898
6899 //----------Arithmetic Instructions--------------------------------------------
6900 //----------Addition Instructions----------------------------------------------
6901
6902 instruct addI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
6903 %{
6904 match(Set dst (AddI dst src));
6905 effect(KILL cr);
6906
6907 format %{ "addl $dst, $src\t# int" %}
6908 opcode(0x03);
6909 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
6910 ins_pipe(ialu_reg_reg);
6911 %}
6912
6913 instruct addI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
6914 %{
6915 match(Set dst (AddI dst src));
6916 effect(KILL cr);
6917
6918 format %{ "addl $dst, $src\t# int" %}
6919 opcode(0x81, 0x00); /* /0 id */
6920 ins_encode(OpcSErm(dst, src), Con8or32(src));
6921 ins_pipe( ialu_reg );
6922 %}
6923
6924 instruct addI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
6925 %{
6926 match(Set dst (AddI dst (LoadI src)));
6927 effect(KILL cr);
6928
6929 ins_cost(125); // XXX
6930 format %{ "addl $dst, $src\t# int" %}
6931 opcode(0x03);
6932 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
6933 ins_pipe(ialu_reg_mem);
6934 %}
6935
6936 instruct addI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
6937 %{
6938 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6939 effect(KILL cr);
6940
6941 ins_cost(150); // XXX
6942 format %{ "addl $dst, $src\t# int" %}
6943 opcode(0x01); /* Opcode 01 /r */
6944 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
6945 ins_pipe(ialu_mem_reg);
6946 %}
6947
6948 instruct addI_mem_imm(memory dst, immI src, rFlagsReg cr)
6949 %{
6950 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6951 effect(KILL cr);
6952
6953 ins_cost(125); // XXX
6954 format %{ "addl $dst, $src\t# int" %}
6955 opcode(0x81); /* Opcode 81 /0 id */
6956 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
6957 ins_pipe(ialu_mem_imm);
6958 %}
6959
6960 instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
6961 %{
6962 predicate(UseIncDec);
6963 match(Set dst (AddI dst src));
6964 effect(KILL cr);
6965
6966 format %{ "incl $dst\t# int" %}
6967 opcode(0xFF, 0x00); // FF /0
6968 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6969 ins_pipe(ialu_reg);
6970 %}
6971
6972 instruct incI_mem(memory dst, immI1 src, rFlagsReg cr)
6973 %{
6974 predicate(UseIncDec);
6975 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
6976 effect(KILL cr);
6977
6978 ins_cost(125); // XXX
6979 format %{ "incl $dst\t# int" %}
6980 opcode(0xFF); /* Opcode FF /0 */
6981 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x00, dst));
6982 ins_pipe(ialu_mem_imm);
6983 %}
6984
6985 // XXX why does that use AddI
6986 instruct decI_rReg(rRegI dst, immI_M1 src, rFlagsReg cr)
6987 %{
6988 predicate(UseIncDec);
6989 match(Set dst (AddI dst src));
6990 effect(KILL cr);
6991
6992 format %{ "decl $dst\t# int" %}
6993 opcode(0xFF, 0x01); // FF /1
6994 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
6995 ins_pipe(ialu_reg);
6996 %}
6997
6998 // XXX why does that use AddI
6999 instruct decI_mem(memory dst, immI_M1 src, rFlagsReg cr)
7000 %{
7001 predicate(UseIncDec);
7002 match(Set dst (StoreI dst (AddI (LoadI dst) src)));
7003 effect(KILL cr);
7004
7005 ins_cost(125); // XXX
7006 format %{ "decl $dst\t# int" %}
7007 opcode(0xFF); /* Opcode FF /1 */
7008 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(0x01, dst));
7009 ins_pipe(ialu_mem_imm);
7010 %}
7011
7012 instruct leaI_rReg_immI(rRegI dst, rRegI src0, immI src1)
7013 %{
7014 match(Set dst (AddI src0 src1));
7015
7016 ins_cost(110);
7017 format %{ "addr32 leal $dst, [$src0 + $src1]\t# int" %}
7018 opcode(0x8D); /* 0x8D /r */
7019 ins_encode(Opcode(0x67), REX_reg_reg(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7020 ins_pipe(ialu_reg_reg);
7021 %}
7022
7023 instruct addL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7024 %{
7025 match(Set dst (AddL dst src));
7026 effect(KILL cr);
7027
7028 format %{ "addq $dst, $src\t# long" %}
7029 opcode(0x03);
7030 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7031 ins_pipe(ialu_reg_reg);
7032 %}
7033
7034 instruct addL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
7035 %{
7036 match(Set dst (AddL dst src));
7037 effect(KILL cr);
7038
7039 format %{ "addq $dst, $src\t# long" %}
7040 opcode(0x81, 0x00); /* /0 id */
7041 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7042 ins_pipe( ialu_reg );
7043 %}
7044
7045 instruct addL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7046 %{
7047 match(Set dst (AddL dst (LoadL src)));
7048 effect(KILL cr);
7049
7050 ins_cost(125); // XXX
7051 format %{ "addq $dst, $src\t# long" %}
7052 opcode(0x03);
7053 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7054 ins_pipe(ialu_reg_mem);
7055 %}
7056
7057 instruct addL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7058 %{
7059 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7060 effect(KILL cr);
7061
7062 ins_cost(150); // XXX
7063 format %{ "addq $dst, $src\t# long" %}
7064 opcode(0x01); /* Opcode 01 /r */
7065 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7066 ins_pipe(ialu_mem_reg);
7067 %}
7068
7069 instruct addL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7070 %{
7071 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7072 effect(KILL cr);
7073
7074 ins_cost(125); // XXX
7075 format %{ "addq $dst, $src\t# long" %}
7076 opcode(0x81); /* Opcode 81 /0 id */
7077 ins_encode(REX_mem_wide(dst),
7078 OpcSE(src), RM_opc_mem(0x00, dst), Con8or32(src));
7079 ins_pipe(ialu_mem_imm);
7080 %}
7081
7082 instruct incL_rReg(rRegI dst, immL1 src, rFlagsReg cr)
7083 %{
7084 predicate(UseIncDec);
7085 match(Set dst (AddL dst src));
7086 effect(KILL cr);
7087
7088 format %{ "incq $dst\t# long" %}
7089 opcode(0xFF, 0x00); // FF /0
7090 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7091 ins_pipe(ialu_reg);
7092 %}
7093
7094 instruct incL_mem(memory dst, immL1 src, rFlagsReg cr)
7095 %{
7096 predicate(UseIncDec);
7097 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7098 effect(KILL cr);
7099
7100 ins_cost(125); // XXX
7101 format %{ "incq $dst\t# long" %}
7102 opcode(0xFF); /* Opcode FF /0 */
7103 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x00, dst));
7104 ins_pipe(ialu_mem_imm);
7105 %}
7106
7107 // XXX why does that use AddL
7108 instruct decL_rReg(rRegL dst, immL_M1 src, rFlagsReg cr)
7109 %{
7110 predicate(UseIncDec);
7111 match(Set dst (AddL dst src));
7112 effect(KILL cr);
7113
7114 format %{ "decq $dst\t# long" %}
7115 opcode(0xFF, 0x01); // FF /1
7116 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7117 ins_pipe(ialu_reg);
7118 %}
7119
7120 // XXX why does that use AddL
7121 instruct decL_mem(memory dst, immL_M1 src, rFlagsReg cr)
7122 %{
7123 predicate(UseIncDec);
7124 match(Set dst (StoreL dst (AddL (LoadL dst) src)));
7125 effect(KILL cr);
7126
7127 ins_cost(125); // XXX
7128 format %{ "decq $dst\t# long" %}
7129 opcode(0xFF); /* Opcode FF /1 */
7130 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(0x01, dst));
7131 ins_pipe(ialu_mem_imm);
7132 %}
7133
7134 instruct leaL_rReg_immL(rRegL dst, rRegL src0, immL32 src1)
7135 %{
7136 match(Set dst (AddL src0 src1));
7137
7138 ins_cost(110);
7139 format %{ "leaq $dst, [$src0 + $src1]\t# long" %}
7140 opcode(0x8D); /* 0x8D /r */
7141 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1)); // XXX
7142 ins_pipe(ialu_reg_reg);
7143 %}
7144
7145 instruct addP_rReg(rRegP dst, rRegL src, rFlagsReg cr)
7146 %{
7147 match(Set dst (AddP dst src));
7148 effect(KILL cr);
7149
7150 format %{ "addq $dst, $src\t# ptr" %}
7151 opcode(0x03);
7152 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7153 ins_pipe(ialu_reg_reg);
7154 %}
7155
7156 instruct addP_rReg_imm(rRegP dst, immL32 src, rFlagsReg cr)
7157 %{
7158 match(Set dst (AddP dst src));
7159 effect(KILL cr);
7160
7161 format %{ "addq $dst, $src\t# ptr" %}
7162 opcode(0x81, 0x00); /* /0 id */
7163 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7164 ins_pipe( ialu_reg );
7165 %}
7166
7167 // XXX addP mem ops ????
7168
7169 instruct leaP_rReg_imm(rRegP dst, rRegP src0, immL32 src1)
7170 %{
7171 match(Set dst (AddP src0 src1));
7172
7173 ins_cost(110);
7174 format %{ "leaq $dst, [$src0 + $src1]\t# ptr" %}
7175 opcode(0x8D); /* 0x8D /r */
7176 ins_encode(REX_reg_reg_wide(dst, src0), OpcP, reg_lea(dst, src0, src1));// XXX
7177 ins_pipe(ialu_reg_reg);
7178 %}
7179
7180 instruct checkCastPP(rRegP dst)
7181 %{
7182 match(Set dst (CheckCastPP dst));
7183
7184 size(0);
7185 format %{ "# checkcastPP of $dst" %}
7186 ins_encode(/* empty encoding */);
7187 ins_pipe(empty);
7188 %}
7189
7190 instruct castPP(rRegP dst)
7191 %{
7192 match(Set dst (CastPP dst));
7193
7194 size(0);
7195 format %{ "# castPP of $dst" %}
7196 ins_encode(/* empty encoding */);
7197 ins_pipe(empty);
7198 %}
7199
7200 instruct castII(rRegI dst)
7201 %{
7202 match(Set dst (CastII dst));
7203
7204 size(0);
7205 format %{ "# castII of $dst" %}
7206 ins_encode(/* empty encoding */);
7207 ins_cost(0);
7208 ins_pipe(empty);
7209 %}
7210
7211 // LoadP-locked same as a regular LoadP when used with compare-swap
7212 instruct loadPLocked(rRegP dst, memory mem)
7213 %{
7214 match(Set dst (LoadPLocked mem));
7215
7216 ins_cost(125); // XXX
7217 format %{ "movq $dst, $mem\t# ptr locked" %}
7218 opcode(0x8B);
7219 ins_encode(REX_reg_mem_wide(dst, mem), OpcP, reg_mem(dst, mem));
7220 ins_pipe(ialu_reg_mem); // XXX
7221 %}
7222
7223 // Conditional-store of the updated heap-top.
7224 // Used during allocation of the shared heap.
7225 // Sets flags (EQ) on success. Implemented with a CMPXCHG on Intel.
7226
7227 instruct storePConditional(memory heap_top_ptr,
7228 rax_RegP oldval, rRegP newval,
7229 rFlagsReg cr)
7230 %{
7231 match(Set cr (StorePConditional heap_top_ptr (Binary oldval newval)));
7232
7233 format %{ "cmpxchgq $heap_top_ptr, $newval\t# (ptr) "
7234 "If rax == $heap_top_ptr then store $newval into $heap_top_ptr" %}
7235 opcode(0x0F, 0xB1);
7236 ins_encode(lock_prefix,
7237 REX_reg_mem_wide(newval, heap_top_ptr),
7238 OpcP, OpcS,
7239 reg_mem(newval, heap_top_ptr));
7240 ins_pipe(pipe_cmpxchg);
7241 %}
7242
7243 // Conditional-store of an int value.
7244 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7245 instruct storeIConditional(memory mem, rax_RegI oldval, rRegI newval, rFlagsReg cr)
7246 %{
7247 match(Set cr (StoreIConditional mem (Binary oldval newval)));
7248 effect(KILL oldval);
7249
7250 format %{ "cmpxchgl $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7251 opcode(0x0F, 0xB1);
7252 ins_encode(lock_prefix,
7253 REX_reg_mem(newval, mem),
7254 OpcP, OpcS,
7255 reg_mem(newval, mem));
7256 ins_pipe(pipe_cmpxchg);
7257 %}
7258
7259 // Conditional-store of a long value.
7260 // ZF flag is set on success, reset otherwise. Implemented with a CMPXCHG.
7261 instruct storeLConditional(memory mem, rax_RegL oldval, rRegL newval, rFlagsReg cr)
7262 %{
7263 match(Set cr (StoreLConditional mem (Binary oldval newval)));
7264 effect(KILL oldval);
7265
7266 format %{ "cmpxchgq $mem, $newval\t# If rax == $mem then store $newval into $mem" %}
7267 opcode(0x0F, 0xB1);
7268 ins_encode(lock_prefix,
7269 REX_reg_mem_wide(newval, mem),
7270 OpcP, OpcS,
7271 reg_mem(newval, mem));
7272 ins_pipe(pipe_cmpxchg);
7273 %}
7274
7275
7276 // XXX No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7277 instruct compareAndSwapP(rRegI res,
7278 memory mem_ptr,
7279 rax_RegP oldval, rRegP newval,
7280 rFlagsReg cr)
7281 %{
7282 predicate(VM_Version::supports_cx8());
7283 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7284 match(Set res (WeakCompareAndSwapP mem_ptr (Binary oldval newval)));
7285 effect(KILL cr, KILL oldval);
7286
7287 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7288 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7289 "sete $res\n\t"
7290 "movzbl $res, $res" %}
7291 opcode(0x0F, 0xB1);
7292 ins_encode(lock_prefix,
7293 REX_reg_mem_wide(newval, mem_ptr),
7294 OpcP, OpcS,
7295 reg_mem(newval, mem_ptr),
7296 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7297 REX_reg_breg(res, res), // movzbl
7298 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7299 ins_pipe( pipe_cmpxchg );
7300 %}
7301
7302 instruct compareAndSwapL(rRegI res,
7303 memory mem_ptr,
7304 rax_RegL oldval, rRegL newval,
7305 rFlagsReg cr)
7306 %{
7307 predicate(VM_Version::supports_cx8());
7308 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7309 match(Set res (WeakCompareAndSwapL mem_ptr (Binary oldval newval)));
7310 effect(KILL cr, KILL oldval);
7311
7312 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7313 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7314 "sete $res\n\t"
7315 "movzbl $res, $res" %}
7316 opcode(0x0F, 0xB1);
7317 ins_encode(lock_prefix,
7318 REX_reg_mem_wide(newval, mem_ptr),
7319 OpcP, OpcS,
7320 reg_mem(newval, mem_ptr),
7321 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7322 REX_reg_breg(res, res), // movzbl
7323 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7324 ins_pipe( pipe_cmpxchg );
7325 %}
7326
7327 instruct compareAndSwapI(rRegI res,
7328 memory mem_ptr,
7329 rax_RegI oldval, rRegI newval,
7330 rFlagsReg cr)
7331 %{
7332 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7333 match(Set res (WeakCompareAndSwapI mem_ptr (Binary oldval newval)));
7334 effect(KILL cr, KILL oldval);
7335
7336 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7337 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7338 "sete $res\n\t"
7339 "movzbl $res, $res" %}
7340 opcode(0x0F, 0xB1);
7341 ins_encode(lock_prefix,
7342 REX_reg_mem(newval, mem_ptr),
7343 OpcP, OpcS,
7344 reg_mem(newval, mem_ptr),
7345 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7346 REX_reg_breg(res, res), // movzbl
7347 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7348 ins_pipe( pipe_cmpxchg );
7349 %}
7350
7351
7352 instruct compareAndSwapN(rRegI res,
7353 memory mem_ptr,
7354 rax_RegN oldval, rRegN newval,
7355 rFlagsReg cr) %{
7356 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7357 match(Set res (WeakCompareAndSwapN mem_ptr (Binary oldval newval)));
7358 effect(KILL cr, KILL oldval);
7359
7360 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7361 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t"
7362 "sete $res\n\t"
7363 "movzbl $res, $res" %}
7364 opcode(0x0F, 0xB1);
7365 ins_encode(lock_prefix,
7366 REX_reg_mem(newval, mem_ptr),
7367 OpcP, OpcS,
7368 reg_mem(newval, mem_ptr),
7369 REX_breg(res), Opcode(0x0F), Opcode(0x94), reg(res), // sete
7370 REX_reg_breg(res, res), // movzbl
7371 Opcode(0xF), Opcode(0xB6), reg_reg(res, res));
7372 ins_pipe( pipe_cmpxchg );
7373 %}
7374
7375 instruct compareAndExchangeI(
7376 memory mem_ptr,
7377 rax_RegI oldval, rRegI newval,
7378 rFlagsReg cr)
7379 %{
7380 match(Set oldval (CompareAndExchangeI mem_ptr (Binary oldval newval)));
7381 effect(KILL cr);
7382
7383 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7384 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7385 opcode(0x0F, 0xB1);
7386 ins_encode(lock_prefix,
7387 REX_reg_mem(newval, mem_ptr),
7388 OpcP, OpcS,
7389 reg_mem(newval, mem_ptr) // lock cmpxchg
7390 );
7391 ins_pipe( pipe_cmpxchg );
7392 %}
7393
7394 instruct compareAndExchangeL(
7395 memory mem_ptr,
7396 rax_RegL oldval, rRegL newval,
7397 rFlagsReg cr)
7398 %{
7399 predicate(VM_Version::supports_cx8());
7400 match(Set oldval (CompareAndExchangeL mem_ptr (Binary oldval newval)));
7401 effect(KILL cr);
7402
7403 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7404 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7405 opcode(0x0F, 0xB1);
7406 ins_encode(lock_prefix,
7407 REX_reg_mem_wide(newval, mem_ptr),
7408 OpcP, OpcS,
7409 reg_mem(newval, mem_ptr) // lock cmpxchg
7410 );
7411 ins_pipe( pipe_cmpxchg );
7412 %}
7413
7414 instruct compareAndExchangeN(
7415 memory mem_ptr,
7416 rax_RegN oldval, rRegN newval,
7417 rFlagsReg cr) %{
7418 match(Set oldval (CompareAndExchangeN mem_ptr (Binary oldval newval)));
7419 effect(KILL cr);
7420
7421 format %{ "cmpxchgl $mem_ptr,$newval\t# "
7422 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7423 opcode(0x0F, 0xB1);
7424 ins_encode(lock_prefix,
7425 REX_reg_mem(newval, mem_ptr),
7426 OpcP, OpcS,
7427 reg_mem(newval, mem_ptr) // lock cmpxchg
7428 );
7429 ins_pipe( pipe_cmpxchg );
7430 %}
7431
7432 instruct compareAndExchangeP(
7433 memory mem_ptr,
7434 rax_RegP oldval, rRegP newval,
7435 rFlagsReg cr)
7436 %{
7437 predicate(VM_Version::supports_cx8());
7438 match(Set oldval (CompareAndExchangeP mem_ptr (Binary oldval newval)));
7439 effect(KILL cr);
7440
7441 format %{ "cmpxchgq $mem_ptr,$newval\t# "
7442 "If rax == $mem_ptr then store $newval into $mem_ptr\n\t" %}
7443 opcode(0x0F, 0xB1);
7444 ins_encode(lock_prefix,
7445 REX_reg_mem_wide(newval, mem_ptr),
7446 OpcP, OpcS,
7447 reg_mem(newval, mem_ptr) // lock cmpxchg
7448 );
7449 ins_pipe( pipe_cmpxchg );
7450 %}
7451
7452 instruct xaddI_no_res( memory mem, Universe dummy, immI add, rFlagsReg cr) %{
7453 predicate(n->as_LoadStore()->result_not_used());
7454 match(Set dummy (GetAndAddI mem add));
7455 effect(KILL cr);
7456 format %{ "ADDL [$mem],$add" %}
7457 ins_encode %{
7458 if (os::is_MP()) { __ lock(); }
7459 __ addl($mem$$Address, $add$$constant);
7460 %}
7461 ins_pipe( pipe_cmpxchg );
7462 %}
7463
7464 instruct xaddI( memory mem, rRegI newval, rFlagsReg cr) %{
7465 match(Set newval (GetAndAddI mem newval));
7466 effect(KILL cr);
7467 format %{ "XADDL [$mem],$newval" %}
7468 ins_encode %{
7469 if (os::is_MP()) { __ lock(); }
7470 __ xaddl($mem$$Address, $newval$$Register);
7471 %}
7472 ins_pipe( pipe_cmpxchg );
7473 %}
7474
7475 instruct xaddL_no_res( memory mem, Universe dummy, immL32 add, rFlagsReg cr) %{
7476 predicate(n->as_LoadStore()->result_not_used());
7477 match(Set dummy (GetAndAddL mem add));
7478 effect(KILL cr);
7479 format %{ "ADDQ [$mem],$add" %}
7480 ins_encode %{
7481 if (os::is_MP()) { __ lock(); }
7482 __ addq($mem$$Address, $add$$constant);
7483 %}
7484 ins_pipe( pipe_cmpxchg );
7485 %}
7486
7487 instruct xaddL( memory mem, rRegL newval, rFlagsReg cr) %{
7488 match(Set newval (GetAndAddL mem newval));
7489 effect(KILL cr);
7490 format %{ "XADDQ [$mem],$newval" %}
7491 ins_encode %{
7492 if (os::is_MP()) { __ lock(); }
7493 __ xaddq($mem$$Address, $newval$$Register);
7494 %}
7495 ins_pipe( pipe_cmpxchg );
7496 %}
7497
7498 instruct xchgI( memory mem, rRegI newval) %{
7499 match(Set newval (GetAndSetI mem newval));
7500 format %{ "XCHGL $newval,[$mem]" %}
7501 ins_encode %{
7502 __ xchgl($newval$$Register, $mem$$Address);
7503 %}
7504 ins_pipe( pipe_cmpxchg );
7505 %}
7506
7507 instruct xchgL( memory mem, rRegL newval) %{
7508 match(Set newval (GetAndSetL mem newval));
7509 format %{ "XCHGL $newval,[$mem]" %}
7510 ins_encode %{
7511 __ xchgq($newval$$Register, $mem$$Address);
7512 %}
7513 ins_pipe( pipe_cmpxchg );
7514 %}
7515
7516 instruct xchgP( memory mem, rRegP newval) %{
7517 match(Set newval (GetAndSetP mem newval));
7518 format %{ "XCHGQ $newval,[$mem]" %}
7519 ins_encode %{
7520 __ xchgq($newval$$Register, $mem$$Address);
7521 %}
7522 ins_pipe( pipe_cmpxchg );
7523 %}
7524
7525 instruct xchgN( memory mem, rRegN newval) %{
7526 match(Set newval (GetAndSetN mem newval));
7527 format %{ "XCHGL $newval,$mem]" %}
7528 ins_encode %{
7529 __ xchgl($newval$$Register, $mem$$Address);
7530 %}
7531 ins_pipe( pipe_cmpxchg );
7532 %}
7533
7534 //----------Subtraction Instructions-------------------------------------------
7535
7536 // Integer Subtraction Instructions
7537 instruct subI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7538 %{
7539 match(Set dst (SubI dst src));
7540 effect(KILL cr);
7541
7542 format %{ "subl $dst, $src\t# int" %}
7543 opcode(0x2B);
7544 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
7545 ins_pipe(ialu_reg_reg);
7546 %}
7547
7548 instruct subI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
7549 %{
7550 match(Set dst (SubI dst src));
7551 effect(KILL cr);
7552
7553 format %{ "subl $dst, $src\t# int" %}
7554 opcode(0x81, 0x05); /* Opcode 81 /5 */
7555 ins_encode(OpcSErm(dst, src), Con8or32(src));
7556 ins_pipe(ialu_reg);
7557 %}
7558
7559 instruct subI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
7560 %{
7561 match(Set dst (SubI dst (LoadI src)));
7562 effect(KILL cr);
7563
7564 ins_cost(125);
7565 format %{ "subl $dst, $src\t# int" %}
7566 opcode(0x2B);
7567 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
7568 ins_pipe(ialu_reg_mem);
7569 %}
7570
7571 instruct subI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
7572 %{
7573 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7574 effect(KILL cr);
7575
7576 ins_cost(150);
7577 format %{ "subl $dst, $src\t# int" %}
7578 opcode(0x29); /* Opcode 29 /r */
7579 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
7580 ins_pipe(ialu_mem_reg);
7581 %}
7582
7583 instruct subI_mem_imm(memory dst, immI src, rFlagsReg cr)
7584 %{
7585 match(Set dst (StoreI dst (SubI (LoadI dst) src)));
7586 effect(KILL cr);
7587
7588 ins_cost(125); // XXX
7589 format %{ "subl $dst, $src\t# int" %}
7590 opcode(0x81); /* Opcode 81 /5 id */
7591 ins_encode(REX_mem(dst), OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7592 ins_pipe(ialu_mem_imm);
7593 %}
7594
7595 instruct subL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7596 %{
7597 match(Set dst (SubL dst src));
7598 effect(KILL cr);
7599
7600 format %{ "subq $dst, $src\t# long" %}
7601 opcode(0x2B);
7602 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7603 ins_pipe(ialu_reg_reg);
7604 %}
7605
7606 instruct subL_rReg_imm(rRegI dst, immL32 src, rFlagsReg cr)
7607 %{
7608 match(Set dst (SubL dst src));
7609 effect(KILL cr);
7610
7611 format %{ "subq $dst, $src\t# long" %}
7612 opcode(0x81, 0x05); /* Opcode 81 /5 */
7613 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
7614 ins_pipe(ialu_reg);
7615 %}
7616
7617 instruct subL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
7618 %{
7619 match(Set dst (SubL dst (LoadL src)));
7620 effect(KILL cr);
7621
7622 ins_cost(125);
7623 format %{ "subq $dst, $src\t# long" %}
7624 opcode(0x2B);
7625 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
7626 ins_pipe(ialu_reg_mem);
7627 %}
7628
7629 instruct subL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
7630 %{
7631 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7632 effect(KILL cr);
7633
7634 ins_cost(150);
7635 format %{ "subq $dst, $src\t# long" %}
7636 opcode(0x29); /* Opcode 29 /r */
7637 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
7638 ins_pipe(ialu_mem_reg);
7639 %}
7640
7641 instruct subL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
7642 %{
7643 match(Set dst (StoreL dst (SubL (LoadL dst) src)));
7644 effect(KILL cr);
7645
7646 ins_cost(125); // XXX
7647 format %{ "subq $dst, $src\t# long" %}
7648 opcode(0x81); /* Opcode 81 /5 id */
7649 ins_encode(REX_mem_wide(dst),
7650 OpcSE(src), RM_opc_mem(0x05, dst), Con8or32(src));
7651 ins_pipe(ialu_mem_imm);
7652 %}
7653
7654 // Subtract from a pointer
7655 // XXX hmpf???
7656 instruct subP_rReg(rRegP dst, rRegI src, immI0 zero, rFlagsReg cr)
7657 %{
7658 match(Set dst (AddP dst (SubI zero src)));
7659 effect(KILL cr);
7660
7661 format %{ "subq $dst, $src\t# ptr - int" %}
7662 opcode(0x2B);
7663 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
7664 ins_pipe(ialu_reg_reg);
7665 %}
7666
7667 instruct negI_rReg(rRegI dst, immI0 zero, rFlagsReg cr)
7668 %{
7669 match(Set dst (SubI zero dst));
7670 effect(KILL cr);
7671
7672 format %{ "negl $dst\t# int" %}
7673 opcode(0xF7, 0x03); // Opcode F7 /3
7674 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
7675 ins_pipe(ialu_reg);
7676 %}
7677
7678 instruct negI_mem(memory dst, immI0 zero, rFlagsReg cr)
7679 %{
7680 match(Set dst (StoreI dst (SubI zero (LoadI dst))));
7681 effect(KILL cr);
7682
7683 format %{ "negl $dst\t# int" %}
7684 opcode(0xF7, 0x03); // Opcode F7 /3
7685 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
7686 ins_pipe(ialu_reg);
7687 %}
7688
7689 instruct negL_rReg(rRegL dst, immL0 zero, rFlagsReg cr)
7690 %{
7691 match(Set dst (SubL zero dst));
7692 effect(KILL cr);
7693
7694 format %{ "negq $dst\t# long" %}
7695 opcode(0xF7, 0x03); // Opcode F7 /3
7696 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
7697 ins_pipe(ialu_reg);
7698 %}
7699
7700 instruct negL_mem(memory dst, immL0 zero, rFlagsReg cr)
7701 %{
7702 match(Set dst (StoreL dst (SubL zero (LoadL dst))));
7703 effect(KILL cr);
7704
7705 format %{ "negq $dst\t# long" %}
7706 opcode(0xF7, 0x03); // Opcode F7 /3
7707 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
7708 ins_pipe(ialu_reg);
7709 %}
7710
7711 //----------Multiplication/Division Instructions-------------------------------
7712 // Integer Multiplication Instructions
7713 // Multiply Register
7714
7715 instruct mulI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
7716 %{
7717 match(Set dst (MulI dst src));
7718 effect(KILL cr);
7719
7720 ins_cost(300);
7721 format %{ "imull $dst, $src\t# int" %}
7722 opcode(0x0F, 0xAF);
7723 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
7724 ins_pipe(ialu_reg_reg_alu0);
7725 %}
7726
7727 instruct mulI_rReg_imm(rRegI dst, rRegI src, immI imm, rFlagsReg cr)
7728 %{
7729 match(Set dst (MulI src imm));
7730 effect(KILL cr);
7731
7732 ins_cost(300);
7733 format %{ "imull $dst, $src, $imm\t# int" %}
7734 opcode(0x69); /* 69 /r id */
7735 ins_encode(REX_reg_reg(dst, src),
7736 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7737 ins_pipe(ialu_reg_reg_alu0);
7738 %}
7739
7740 instruct mulI_mem(rRegI dst, memory src, rFlagsReg cr)
7741 %{
7742 match(Set dst (MulI dst (LoadI src)));
7743 effect(KILL cr);
7744
7745 ins_cost(350);
7746 format %{ "imull $dst, $src\t# int" %}
7747 opcode(0x0F, 0xAF);
7748 ins_encode(REX_reg_mem(dst, src), OpcP, OpcS, reg_mem(dst, src));
7749 ins_pipe(ialu_reg_mem_alu0);
7750 %}
7751
7752 instruct mulI_mem_imm(rRegI dst, memory src, immI imm, rFlagsReg cr)
7753 %{
7754 match(Set dst (MulI (LoadI src) imm));
7755 effect(KILL cr);
7756
7757 ins_cost(300);
7758 format %{ "imull $dst, $src, $imm\t# int" %}
7759 opcode(0x69); /* 69 /r id */
7760 ins_encode(REX_reg_mem(dst, src),
7761 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7762 ins_pipe(ialu_reg_mem_alu0);
7763 %}
7764
7765 instruct mulL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
7766 %{
7767 match(Set dst (MulL dst src));
7768 effect(KILL cr);
7769
7770 ins_cost(300);
7771 format %{ "imulq $dst, $src\t# long" %}
7772 opcode(0x0F, 0xAF);
7773 ins_encode(REX_reg_reg_wide(dst, src), OpcP, OpcS, reg_reg(dst, src));
7774 ins_pipe(ialu_reg_reg_alu0);
7775 %}
7776
7777 instruct mulL_rReg_imm(rRegL dst, rRegL src, immL32 imm, rFlagsReg cr)
7778 %{
7779 match(Set dst (MulL src imm));
7780 effect(KILL cr);
7781
7782 ins_cost(300);
7783 format %{ "imulq $dst, $src, $imm\t# long" %}
7784 opcode(0x69); /* 69 /r id */
7785 ins_encode(REX_reg_reg_wide(dst, src),
7786 OpcSE(imm), reg_reg(dst, src), Con8or32(imm));
7787 ins_pipe(ialu_reg_reg_alu0);
7788 %}
7789
7790 instruct mulL_mem(rRegL dst, memory src, rFlagsReg cr)
7791 %{
7792 match(Set dst (MulL dst (LoadL src)));
7793 effect(KILL cr);
7794
7795 ins_cost(350);
7796 format %{ "imulq $dst, $src\t# long" %}
7797 opcode(0x0F, 0xAF);
7798 ins_encode(REX_reg_mem_wide(dst, src), OpcP, OpcS, reg_mem(dst, src));
7799 ins_pipe(ialu_reg_mem_alu0);
7800 %}
7801
7802 instruct mulL_mem_imm(rRegL dst, memory src, immL32 imm, rFlagsReg cr)
7803 %{
7804 match(Set dst (MulL (LoadL src) imm));
7805 effect(KILL cr);
7806
7807 ins_cost(300);
7808 format %{ "imulq $dst, $src, $imm\t# long" %}
7809 opcode(0x69); /* 69 /r id */
7810 ins_encode(REX_reg_mem_wide(dst, src),
7811 OpcSE(imm), reg_mem(dst, src), Con8or32(imm));
7812 ins_pipe(ialu_reg_mem_alu0);
7813 %}
7814
7815 instruct mulHiL_rReg(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7816 %{
7817 match(Set dst (MulHiL src rax));
7818 effect(USE_KILL rax, KILL cr);
7819
7820 ins_cost(300);
7821 format %{ "imulq RDX:RAX, RAX, $src\t# mulhi" %}
7822 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7823 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7824 ins_pipe(ialu_reg_reg_alu0);
7825 %}
7826
7827 instruct divI_rReg(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7828 rFlagsReg cr)
7829 %{
7830 match(Set rax (DivI rax div));
7831 effect(KILL rdx, KILL cr);
7832
7833 ins_cost(30*100+10*100); // XXX
7834 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7835 "jne,s normal\n\t"
7836 "xorl rdx, rdx\n\t"
7837 "cmpl $div, -1\n\t"
7838 "je,s done\n"
7839 "normal: cdql\n\t"
7840 "idivl $div\n"
7841 "done:" %}
7842 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7843 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7844 ins_pipe(ialu_reg_reg_alu0);
7845 %}
7846
7847 instruct divL_rReg(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7848 rFlagsReg cr)
7849 %{
7850 match(Set rax (DivL rax div));
7851 effect(KILL rdx, KILL cr);
7852
7853 ins_cost(30*100+10*100); // XXX
7854 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7855 "cmpq rax, rdx\n\t"
7856 "jne,s normal\n\t"
7857 "xorl rdx, rdx\n\t"
7858 "cmpq $div, -1\n\t"
7859 "je,s done\n"
7860 "normal: cdqq\n\t"
7861 "idivq $div\n"
7862 "done:" %}
7863 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7864 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7865 ins_pipe(ialu_reg_reg_alu0);
7866 %}
7867
7868 // Integer DIVMOD with Register, both quotient and mod results
7869 instruct divModI_rReg_divmod(rax_RegI rax, rdx_RegI rdx, no_rax_rdx_RegI div,
7870 rFlagsReg cr)
7871 %{
7872 match(DivModI rax div);
7873 effect(KILL cr);
7874
7875 ins_cost(30*100+10*100); // XXX
7876 format %{ "cmpl rax, 0x80000000\t# idiv\n\t"
7877 "jne,s normal\n\t"
7878 "xorl rdx, rdx\n\t"
7879 "cmpl $div, -1\n\t"
7880 "je,s done\n"
7881 "normal: cdql\n\t"
7882 "idivl $div\n"
7883 "done:" %}
7884 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7885 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7886 ins_pipe(pipe_slow);
7887 %}
7888
7889 // Long DIVMOD with Register, both quotient and mod results
7890 instruct divModL_rReg_divmod(rax_RegL rax, rdx_RegL rdx, no_rax_rdx_RegL div,
7891 rFlagsReg cr)
7892 %{
7893 match(DivModL rax div);
7894 effect(KILL cr);
7895
7896 ins_cost(30*100+10*100); // XXX
7897 format %{ "movq rdx, 0x8000000000000000\t# ldiv\n\t"
7898 "cmpq rax, rdx\n\t"
7899 "jne,s normal\n\t"
7900 "xorl rdx, rdx\n\t"
7901 "cmpq $div, -1\n\t"
7902 "je,s done\n"
7903 "normal: cdqq\n\t"
7904 "idivq $div\n"
7905 "done:" %}
7906 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7907 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
7908 ins_pipe(pipe_slow);
7909 %}
7910
7911 //----------- DivL-By-Constant-Expansions--------------------------------------
7912 // DivI cases are handled by the compiler
7913
7914 // Magic constant, reciprocal of 10
7915 instruct loadConL_0x6666666666666667(rRegL dst)
7916 %{
7917 effect(DEF dst);
7918
7919 format %{ "movq $dst, #0x666666666666667\t# Used in div-by-10" %}
7920 ins_encode(load_immL(dst, 0x6666666666666667));
7921 ins_pipe(ialu_reg);
7922 %}
7923
7924 instruct mul_hi(rdx_RegL dst, no_rax_RegL src, rax_RegL rax, rFlagsReg cr)
7925 %{
7926 effect(DEF dst, USE src, USE_KILL rax, KILL cr);
7927
7928 format %{ "imulq rdx:rax, rax, $src\t# Used in div-by-10" %}
7929 opcode(0xF7, 0x5); /* Opcode F7 /5 */
7930 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src));
7931 ins_pipe(ialu_reg_reg_alu0);
7932 %}
7933
7934 instruct sarL_rReg_63(rRegL dst, rFlagsReg cr)
7935 %{
7936 effect(USE_DEF dst, KILL cr);
7937
7938 format %{ "sarq $dst, #63\t# Used in div-by-10" %}
7939 opcode(0xC1, 0x7); /* C1 /7 ib */
7940 ins_encode(reg_opc_imm_wide(dst, 0x3F));
7941 ins_pipe(ialu_reg);
7942 %}
7943
7944 instruct sarL_rReg_2(rRegL dst, rFlagsReg cr)
7945 %{
7946 effect(USE_DEF dst, KILL cr);
7947
7948 format %{ "sarq $dst, #2\t# Used in div-by-10" %}
7949 opcode(0xC1, 0x7); /* C1 /7 ib */
7950 ins_encode(reg_opc_imm_wide(dst, 0x2));
7951 ins_pipe(ialu_reg);
7952 %}
7953
7954 instruct divL_10(rdx_RegL dst, no_rax_RegL src, immL10 div)
7955 %{
7956 match(Set dst (DivL src div));
7957
7958 ins_cost((5+8)*100);
7959 expand %{
7960 rax_RegL rax; // Killed temp
7961 rFlagsReg cr; // Killed
7962 loadConL_0x6666666666666667(rax); // movq rax, 0x6666666666666667
7963 mul_hi(dst, src, rax, cr); // mulq rdx:rax <= rax * $src
7964 sarL_rReg_63(src, cr); // sarq src, 63
7965 sarL_rReg_2(dst, cr); // sarq rdx, 2
7966 subL_rReg(dst, src, cr); // subl rdx, src
7967 %}
7968 %}
7969
7970 //-----------------------------------------------------------------------------
7971
7972 instruct modI_rReg(rdx_RegI rdx, rax_RegI rax, no_rax_rdx_RegI div,
7973 rFlagsReg cr)
7974 %{
7975 match(Set rdx (ModI rax div));
7976 effect(KILL rax, KILL cr);
7977
7978 ins_cost(300); // XXX
7979 format %{ "cmpl rax, 0x80000000\t# irem\n\t"
7980 "jne,s normal\n\t"
7981 "xorl rdx, rdx\n\t"
7982 "cmpl $div, -1\n\t"
7983 "je,s done\n"
7984 "normal: cdql\n\t"
7985 "idivl $div\n"
7986 "done:" %}
7987 opcode(0xF7, 0x7); /* Opcode F7 /7 */
7988 ins_encode(cdql_enc(div), REX_reg(div), OpcP, reg_opc(div));
7989 ins_pipe(ialu_reg_reg_alu0);
7990 %}
7991
7992 instruct modL_rReg(rdx_RegL rdx, rax_RegL rax, no_rax_rdx_RegL div,
7993 rFlagsReg cr)
7994 %{
7995 match(Set rdx (ModL rax div));
7996 effect(KILL rax, KILL cr);
7997
7998 ins_cost(300); // XXX
7999 format %{ "movq rdx, 0x8000000000000000\t# lrem\n\t"
8000 "cmpq rax, rdx\n\t"
8001 "jne,s normal\n\t"
8002 "xorl rdx, rdx\n\t"
8003 "cmpq $div, -1\n\t"
8004 "je,s done\n"
8005 "normal: cdqq\n\t"
8006 "idivq $div\n"
8007 "done:" %}
8008 opcode(0xF7, 0x7); /* Opcode F7 /7 */
8009 ins_encode(cdqq_enc(div), REX_reg_wide(div), OpcP, reg_opc(div));
8010 ins_pipe(ialu_reg_reg_alu0);
8011 %}
8012
8013 // Integer Shift Instructions
8014 // Shift Left by one
8015 instruct salI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8016 %{
8017 match(Set dst (LShiftI dst shift));
8018 effect(KILL cr);
8019
8020 format %{ "sall $dst, $shift" %}
8021 opcode(0xD1, 0x4); /* D1 /4 */
8022 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8023 ins_pipe(ialu_reg);
8024 %}
8025
8026 // Shift Left by one
8027 instruct salI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8028 %{
8029 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8030 effect(KILL cr);
8031
8032 format %{ "sall $dst, $shift\t" %}
8033 opcode(0xD1, 0x4); /* D1 /4 */
8034 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8035 ins_pipe(ialu_mem_imm);
8036 %}
8037
8038 // Shift Left by 8-bit immediate
8039 instruct salI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8040 %{
8041 match(Set dst (LShiftI dst shift));
8042 effect(KILL cr);
8043
8044 format %{ "sall $dst, $shift" %}
8045 opcode(0xC1, 0x4); /* C1 /4 ib */
8046 ins_encode(reg_opc_imm(dst, shift));
8047 ins_pipe(ialu_reg);
8048 %}
8049
8050 // Shift Left by 8-bit immediate
8051 instruct salI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8052 %{
8053 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8054 effect(KILL cr);
8055
8056 format %{ "sall $dst, $shift" %}
8057 opcode(0xC1, 0x4); /* C1 /4 ib */
8058 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8059 ins_pipe(ialu_mem_imm);
8060 %}
8061
8062 // Shift Left by variable
8063 instruct salI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8064 %{
8065 match(Set dst (LShiftI dst shift));
8066 effect(KILL cr);
8067
8068 format %{ "sall $dst, $shift" %}
8069 opcode(0xD3, 0x4); /* D3 /4 */
8070 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8071 ins_pipe(ialu_reg_reg);
8072 %}
8073
8074 // Shift Left by variable
8075 instruct salI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8076 %{
8077 match(Set dst (StoreI dst (LShiftI (LoadI dst) shift)));
8078 effect(KILL cr);
8079
8080 format %{ "sall $dst, $shift" %}
8081 opcode(0xD3, 0x4); /* D3 /4 */
8082 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8083 ins_pipe(ialu_mem_reg);
8084 %}
8085
8086 // Arithmetic shift right by one
8087 instruct sarI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8088 %{
8089 match(Set dst (RShiftI dst shift));
8090 effect(KILL cr);
8091
8092 format %{ "sarl $dst, $shift" %}
8093 opcode(0xD1, 0x7); /* D1 /7 */
8094 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8095 ins_pipe(ialu_reg);
8096 %}
8097
8098 // Arithmetic shift right by one
8099 instruct sarI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8100 %{
8101 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8102 effect(KILL cr);
8103
8104 format %{ "sarl $dst, $shift" %}
8105 opcode(0xD1, 0x7); /* D1 /7 */
8106 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8107 ins_pipe(ialu_mem_imm);
8108 %}
8109
8110 // Arithmetic Shift Right by 8-bit immediate
8111 instruct sarI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8112 %{
8113 match(Set dst (RShiftI dst shift));
8114 effect(KILL cr);
8115
8116 format %{ "sarl $dst, $shift" %}
8117 opcode(0xC1, 0x7); /* C1 /7 ib */
8118 ins_encode(reg_opc_imm(dst, shift));
8119 ins_pipe(ialu_mem_imm);
8120 %}
8121
8122 // Arithmetic Shift Right by 8-bit immediate
8123 instruct sarI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8124 %{
8125 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8126 effect(KILL cr);
8127
8128 format %{ "sarl $dst, $shift" %}
8129 opcode(0xC1, 0x7); /* C1 /7 ib */
8130 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8131 ins_pipe(ialu_mem_imm);
8132 %}
8133
8134 // Arithmetic Shift Right by variable
8135 instruct sarI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8136 %{
8137 match(Set dst (RShiftI dst shift));
8138 effect(KILL cr);
8139
8140 format %{ "sarl $dst, $shift" %}
8141 opcode(0xD3, 0x7); /* D3 /7 */
8142 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8143 ins_pipe(ialu_reg_reg);
8144 %}
8145
8146 // Arithmetic Shift Right by variable
8147 instruct sarI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8148 %{
8149 match(Set dst (StoreI dst (RShiftI (LoadI dst) shift)));
8150 effect(KILL cr);
8151
8152 format %{ "sarl $dst, $shift" %}
8153 opcode(0xD3, 0x7); /* D3 /7 */
8154 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8155 ins_pipe(ialu_mem_reg);
8156 %}
8157
8158 // Logical shift right by one
8159 instruct shrI_rReg_1(rRegI dst, immI1 shift, rFlagsReg cr)
8160 %{
8161 match(Set dst (URShiftI dst shift));
8162 effect(KILL cr);
8163
8164 format %{ "shrl $dst, $shift" %}
8165 opcode(0xD1, 0x5); /* D1 /5 */
8166 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8167 ins_pipe(ialu_reg);
8168 %}
8169
8170 // Logical shift right by one
8171 instruct shrI_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8172 %{
8173 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8174 effect(KILL cr);
8175
8176 format %{ "shrl $dst, $shift" %}
8177 opcode(0xD1, 0x5); /* D1 /5 */
8178 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8179 ins_pipe(ialu_mem_imm);
8180 %}
8181
8182 // Logical Shift Right by 8-bit immediate
8183 instruct shrI_rReg_imm(rRegI dst, immI8 shift, rFlagsReg cr)
8184 %{
8185 match(Set dst (URShiftI dst shift));
8186 effect(KILL cr);
8187
8188 format %{ "shrl $dst, $shift" %}
8189 opcode(0xC1, 0x5); /* C1 /5 ib */
8190 ins_encode(reg_opc_imm(dst, shift));
8191 ins_pipe(ialu_reg);
8192 %}
8193
8194 // Logical Shift Right by 8-bit immediate
8195 instruct shrI_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8196 %{
8197 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8198 effect(KILL cr);
8199
8200 format %{ "shrl $dst, $shift" %}
8201 opcode(0xC1, 0x5); /* C1 /5 ib */
8202 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst), Con8or32(shift));
8203 ins_pipe(ialu_mem_imm);
8204 %}
8205
8206 // Logical Shift Right by variable
8207 instruct shrI_rReg_CL(rRegI dst, rcx_RegI shift, rFlagsReg cr)
8208 %{
8209 match(Set dst (URShiftI dst shift));
8210 effect(KILL cr);
8211
8212 format %{ "shrl $dst, $shift" %}
8213 opcode(0xD3, 0x5); /* D3 /5 */
8214 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8215 ins_pipe(ialu_reg_reg);
8216 %}
8217
8218 // Logical Shift Right by variable
8219 instruct shrI_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8220 %{
8221 match(Set dst (StoreI dst (URShiftI (LoadI dst) shift)));
8222 effect(KILL cr);
8223
8224 format %{ "shrl $dst, $shift" %}
8225 opcode(0xD3, 0x5); /* D3 /5 */
8226 ins_encode(REX_mem(dst), OpcP, RM_opc_mem(secondary, dst));
8227 ins_pipe(ialu_mem_reg);
8228 %}
8229
8230 // Long Shift Instructions
8231 // Shift Left by one
8232 instruct salL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8233 %{
8234 match(Set dst (LShiftL dst shift));
8235 effect(KILL cr);
8236
8237 format %{ "salq $dst, $shift" %}
8238 opcode(0xD1, 0x4); /* D1 /4 */
8239 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8240 ins_pipe(ialu_reg);
8241 %}
8242
8243 // Shift Left by one
8244 instruct salL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8245 %{
8246 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8247 effect(KILL cr);
8248
8249 format %{ "salq $dst, $shift" %}
8250 opcode(0xD1, 0x4); /* D1 /4 */
8251 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8252 ins_pipe(ialu_mem_imm);
8253 %}
8254
8255 // Shift Left by 8-bit immediate
8256 instruct salL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8257 %{
8258 match(Set dst (LShiftL dst shift));
8259 effect(KILL cr);
8260
8261 format %{ "salq $dst, $shift" %}
8262 opcode(0xC1, 0x4); /* C1 /4 ib */
8263 ins_encode(reg_opc_imm_wide(dst, shift));
8264 ins_pipe(ialu_reg);
8265 %}
8266
8267 // Shift Left by 8-bit immediate
8268 instruct salL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8269 %{
8270 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8271 effect(KILL cr);
8272
8273 format %{ "salq $dst, $shift" %}
8274 opcode(0xC1, 0x4); /* C1 /4 ib */
8275 ins_encode(REX_mem_wide(dst), OpcP,
8276 RM_opc_mem(secondary, dst), Con8or32(shift));
8277 ins_pipe(ialu_mem_imm);
8278 %}
8279
8280 // Shift Left by variable
8281 instruct salL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8282 %{
8283 match(Set dst (LShiftL dst shift));
8284 effect(KILL cr);
8285
8286 format %{ "salq $dst, $shift" %}
8287 opcode(0xD3, 0x4); /* D3 /4 */
8288 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8289 ins_pipe(ialu_reg_reg);
8290 %}
8291
8292 // Shift Left by variable
8293 instruct salL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8294 %{
8295 match(Set dst (StoreL dst (LShiftL (LoadL dst) shift)));
8296 effect(KILL cr);
8297
8298 format %{ "salq $dst, $shift" %}
8299 opcode(0xD3, 0x4); /* D3 /4 */
8300 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8301 ins_pipe(ialu_mem_reg);
8302 %}
8303
8304 // Arithmetic shift right by one
8305 instruct sarL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8306 %{
8307 match(Set dst (RShiftL dst shift));
8308 effect(KILL cr);
8309
8310 format %{ "sarq $dst, $shift" %}
8311 opcode(0xD1, 0x7); /* D1 /7 */
8312 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8313 ins_pipe(ialu_reg);
8314 %}
8315
8316 // Arithmetic shift right by one
8317 instruct sarL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8318 %{
8319 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8320 effect(KILL cr);
8321
8322 format %{ "sarq $dst, $shift" %}
8323 opcode(0xD1, 0x7); /* D1 /7 */
8324 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8325 ins_pipe(ialu_mem_imm);
8326 %}
8327
8328 // Arithmetic Shift Right by 8-bit immediate
8329 instruct sarL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8330 %{
8331 match(Set dst (RShiftL dst shift));
8332 effect(KILL cr);
8333
8334 format %{ "sarq $dst, $shift" %}
8335 opcode(0xC1, 0x7); /* C1 /7 ib */
8336 ins_encode(reg_opc_imm_wide(dst, shift));
8337 ins_pipe(ialu_mem_imm);
8338 %}
8339
8340 // Arithmetic Shift Right by 8-bit immediate
8341 instruct sarL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8342 %{
8343 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8344 effect(KILL cr);
8345
8346 format %{ "sarq $dst, $shift" %}
8347 opcode(0xC1, 0x7); /* C1 /7 ib */
8348 ins_encode(REX_mem_wide(dst), OpcP,
8349 RM_opc_mem(secondary, dst), Con8or32(shift));
8350 ins_pipe(ialu_mem_imm);
8351 %}
8352
8353 // Arithmetic Shift Right by variable
8354 instruct sarL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8355 %{
8356 match(Set dst (RShiftL dst shift));
8357 effect(KILL cr);
8358
8359 format %{ "sarq $dst, $shift" %}
8360 opcode(0xD3, 0x7); /* D3 /7 */
8361 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8362 ins_pipe(ialu_reg_reg);
8363 %}
8364
8365 // Arithmetic Shift Right by variable
8366 instruct sarL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8367 %{
8368 match(Set dst (StoreL dst (RShiftL (LoadL dst) shift)));
8369 effect(KILL cr);
8370
8371 format %{ "sarq $dst, $shift" %}
8372 opcode(0xD3, 0x7); /* D3 /7 */
8373 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8374 ins_pipe(ialu_mem_reg);
8375 %}
8376
8377 // Logical shift right by one
8378 instruct shrL_rReg_1(rRegL dst, immI1 shift, rFlagsReg cr)
8379 %{
8380 match(Set dst (URShiftL dst shift));
8381 effect(KILL cr);
8382
8383 format %{ "shrq $dst, $shift" %}
8384 opcode(0xD1, 0x5); /* D1 /5 */
8385 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst ));
8386 ins_pipe(ialu_reg);
8387 %}
8388
8389 // Logical shift right by one
8390 instruct shrL_mem_1(memory dst, immI1 shift, rFlagsReg cr)
8391 %{
8392 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8393 effect(KILL cr);
8394
8395 format %{ "shrq $dst, $shift" %}
8396 opcode(0xD1, 0x5); /* D1 /5 */
8397 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8398 ins_pipe(ialu_mem_imm);
8399 %}
8400
8401 // Logical Shift Right by 8-bit immediate
8402 instruct shrL_rReg_imm(rRegL dst, immI8 shift, rFlagsReg cr)
8403 %{
8404 match(Set dst (URShiftL dst shift));
8405 effect(KILL cr);
8406
8407 format %{ "shrq $dst, $shift" %}
8408 opcode(0xC1, 0x5); /* C1 /5 ib */
8409 ins_encode(reg_opc_imm_wide(dst, shift));
8410 ins_pipe(ialu_reg);
8411 %}
8412
8413
8414 // Logical Shift Right by 8-bit immediate
8415 instruct shrL_mem_imm(memory dst, immI8 shift, rFlagsReg cr)
8416 %{
8417 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8418 effect(KILL cr);
8419
8420 format %{ "shrq $dst, $shift" %}
8421 opcode(0xC1, 0x5); /* C1 /5 ib */
8422 ins_encode(REX_mem_wide(dst), OpcP,
8423 RM_opc_mem(secondary, dst), Con8or32(shift));
8424 ins_pipe(ialu_mem_imm);
8425 %}
8426
8427 // Logical Shift Right by variable
8428 instruct shrL_rReg_CL(rRegL dst, rcx_RegI shift, rFlagsReg cr)
8429 %{
8430 match(Set dst (URShiftL dst shift));
8431 effect(KILL cr);
8432
8433 format %{ "shrq $dst, $shift" %}
8434 opcode(0xD3, 0x5); /* D3 /5 */
8435 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8436 ins_pipe(ialu_reg_reg);
8437 %}
8438
8439 // Logical Shift Right by variable
8440 instruct shrL_mem_CL(memory dst, rcx_RegI shift, rFlagsReg cr)
8441 %{
8442 match(Set dst (StoreL dst (URShiftL (LoadL dst) shift)));
8443 effect(KILL cr);
8444
8445 format %{ "shrq $dst, $shift" %}
8446 opcode(0xD3, 0x5); /* D3 /5 */
8447 ins_encode(REX_mem_wide(dst), OpcP, RM_opc_mem(secondary, dst));
8448 ins_pipe(ialu_mem_reg);
8449 %}
8450
8451 // Logical Shift Right by 24, followed by Arithmetic Shift Left by 24.
8452 // This idiom is used by the compiler for the i2b bytecode.
8453 instruct i2b(rRegI dst, rRegI src, immI_24 twentyfour)
8454 %{
8455 match(Set dst (RShiftI (LShiftI src twentyfour) twentyfour));
8456
8457 format %{ "movsbl $dst, $src\t# i2b" %}
8458 opcode(0x0F, 0xBE);
8459 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8460 ins_pipe(ialu_reg_reg);
8461 %}
8462
8463 // Logical Shift Right by 16, followed by Arithmetic Shift Left by 16.
8464 // This idiom is used by the compiler the i2s bytecode.
8465 instruct i2s(rRegI dst, rRegI src, immI_16 sixteen)
8466 %{
8467 match(Set dst (RShiftI (LShiftI src sixteen) sixteen));
8468
8469 format %{ "movswl $dst, $src\t# i2s" %}
8470 opcode(0x0F, 0xBF);
8471 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8472 ins_pipe(ialu_reg_reg);
8473 %}
8474
8475 // ROL/ROR instructions
8476
8477 // ROL expand
8478 instruct rolI_rReg_imm1(rRegI dst, rFlagsReg cr) %{
8479 effect(KILL cr, USE_DEF dst);
8480
8481 format %{ "roll $dst" %}
8482 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8483 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8484 ins_pipe(ialu_reg);
8485 %}
8486
8487 instruct rolI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr) %{
8488 effect(USE_DEF dst, USE shift, KILL cr);
8489
8490 format %{ "roll $dst, $shift" %}
8491 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8492 ins_encode( reg_opc_imm(dst, shift) );
8493 ins_pipe(ialu_reg);
8494 %}
8495
8496 instruct rolI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8497 %{
8498 effect(USE_DEF dst, USE shift, KILL cr);
8499
8500 format %{ "roll $dst, $shift" %}
8501 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8502 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8503 ins_pipe(ialu_reg_reg);
8504 %}
8505 // end of ROL expand
8506
8507 // Rotate Left by one
8508 instruct rolI_rReg_i1(rRegI dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8509 %{
8510 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8511
8512 expand %{
8513 rolI_rReg_imm1(dst, cr);
8514 %}
8515 %}
8516
8517 // Rotate Left by 8-bit immediate
8518 instruct rolI_rReg_i8(rRegI dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8519 %{
8520 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8521 match(Set dst (OrI (LShiftI dst lshift) (URShiftI dst rshift)));
8522
8523 expand %{
8524 rolI_rReg_imm8(dst, lshift, cr);
8525 %}
8526 %}
8527
8528 // Rotate Left by variable
8529 instruct rolI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8530 %{
8531 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI zero shift))));
8532
8533 expand %{
8534 rolI_rReg_CL(dst, shift, cr);
8535 %}
8536 %}
8537
8538 // Rotate Left by variable
8539 instruct rolI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8540 %{
8541 match(Set dst (OrI (LShiftI dst shift) (URShiftI dst (SubI c32 shift))));
8542
8543 expand %{
8544 rolI_rReg_CL(dst, shift, cr);
8545 %}
8546 %}
8547
8548 // ROR expand
8549 instruct rorI_rReg_imm1(rRegI dst, rFlagsReg cr)
8550 %{
8551 effect(USE_DEF dst, KILL cr);
8552
8553 format %{ "rorl $dst" %}
8554 opcode(0xD1, 0x1); /* D1 /1 */
8555 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8556 ins_pipe(ialu_reg);
8557 %}
8558
8559 instruct rorI_rReg_imm8(rRegI dst, immI8 shift, rFlagsReg cr)
8560 %{
8561 effect(USE_DEF dst, USE shift, KILL cr);
8562
8563 format %{ "rorl $dst, $shift" %}
8564 opcode(0xC1, 0x1); /* C1 /1 ib */
8565 ins_encode(reg_opc_imm(dst, shift));
8566 ins_pipe(ialu_reg);
8567 %}
8568
8569 instruct rorI_rReg_CL(no_rcx_RegI dst, rcx_RegI shift, rFlagsReg cr)
8570 %{
8571 effect(USE_DEF dst, USE shift, KILL cr);
8572
8573 format %{ "rorl $dst, $shift" %}
8574 opcode(0xD3, 0x1); /* D3 /1 */
8575 ins_encode(REX_reg(dst), OpcP, reg_opc(dst));
8576 ins_pipe(ialu_reg_reg);
8577 %}
8578 // end of ROR expand
8579
8580 // Rotate Right by one
8581 instruct rorI_rReg_i1(rRegI dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8582 %{
8583 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8584
8585 expand %{
8586 rorI_rReg_imm1(dst, cr);
8587 %}
8588 %}
8589
8590 // Rotate Right by 8-bit immediate
8591 instruct rorI_rReg_i8(rRegI dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8592 %{
8593 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x1f));
8594 match(Set dst (OrI (URShiftI dst rshift) (LShiftI dst lshift)));
8595
8596 expand %{
8597 rorI_rReg_imm8(dst, rshift, cr);
8598 %}
8599 %}
8600
8601 // Rotate Right by variable
8602 instruct rorI_rReg_Var_C0(no_rcx_RegI dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8603 %{
8604 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI zero shift))));
8605
8606 expand %{
8607 rorI_rReg_CL(dst, shift, cr);
8608 %}
8609 %}
8610
8611 // Rotate Right by variable
8612 instruct rorI_rReg_Var_C32(no_rcx_RegI dst, rcx_RegI shift, immI_32 c32, rFlagsReg cr)
8613 %{
8614 match(Set dst (OrI (URShiftI dst shift) (LShiftI dst (SubI c32 shift))));
8615
8616 expand %{
8617 rorI_rReg_CL(dst, shift, cr);
8618 %}
8619 %}
8620
8621 // for long rotate
8622 // ROL expand
8623 instruct rolL_rReg_imm1(rRegL dst, rFlagsReg cr) %{
8624 effect(USE_DEF dst, KILL cr);
8625
8626 format %{ "rolq $dst" %}
8627 opcode(0xD1, 0x0); /* Opcode D1 /0 */
8628 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8629 ins_pipe(ialu_reg);
8630 %}
8631
8632 instruct rolL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr) %{
8633 effect(USE_DEF dst, USE shift, KILL cr);
8634
8635 format %{ "rolq $dst, $shift" %}
8636 opcode(0xC1, 0x0); /* Opcode C1 /0 ib */
8637 ins_encode( reg_opc_imm_wide(dst, shift) );
8638 ins_pipe(ialu_reg);
8639 %}
8640
8641 instruct rolL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8642 %{
8643 effect(USE_DEF dst, USE shift, KILL cr);
8644
8645 format %{ "rolq $dst, $shift" %}
8646 opcode(0xD3, 0x0); /* Opcode D3 /0 */
8647 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8648 ins_pipe(ialu_reg_reg);
8649 %}
8650 // end of ROL expand
8651
8652 // Rotate Left by one
8653 instruct rolL_rReg_i1(rRegL dst, immI1 lshift, immI_M1 rshift, rFlagsReg cr)
8654 %{
8655 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8656
8657 expand %{
8658 rolL_rReg_imm1(dst, cr);
8659 %}
8660 %}
8661
8662 // Rotate Left by 8-bit immediate
8663 instruct rolL_rReg_i8(rRegL dst, immI8 lshift, immI8 rshift, rFlagsReg cr)
8664 %{
8665 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8666 match(Set dst (OrL (LShiftL dst lshift) (URShiftL dst rshift)));
8667
8668 expand %{
8669 rolL_rReg_imm8(dst, lshift, cr);
8670 %}
8671 %}
8672
8673 // Rotate Left by variable
8674 instruct rolL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8675 %{
8676 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI zero shift))));
8677
8678 expand %{
8679 rolL_rReg_CL(dst, shift, cr);
8680 %}
8681 %}
8682
8683 // Rotate Left by variable
8684 instruct rolL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8685 %{
8686 match(Set dst (OrL (LShiftL dst shift) (URShiftL dst (SubI c64 shift))));
8687
8688 expand %{
8689 rolL_rReg_CL(dst, shift, cr);
8690 %}
8691 %}
8692
8693 // ROR expand
8694 instruct rorL_rReg_imm1(rRegL dst, rFlagsReg cr)
8695 %{
8696 effect(USE_DEF dst, KILL cr);
8697
8698 format %{ "rorq $dst" %}
8699 opcode(0xD1, 0x1); /* D1 /1 */
8700 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8701 ins_pipe(ialu_reg);
8702 %}
8703
8704 instruct rorL_rReg_imm8(rRegL dst, immI8 shift, rFlagsReg cr)
8705 %{
8706 effect(USE_DEF dst, USE shift, KILL cr);
8707
8708 format %{ "rorq $dst, $shift" %}
8709 opcode(0xC1, 0x1); /* C1 /1 ib */
8710 ins_encode(reg_opc_imm_wide(dst, shift));
8711 ins_pipe(ialu_reg);
8712 %}
8713
8714 instruct rorL_rReg_CL(no_rcx_RegL dst, rcx_RegI shift, rFlagsReg cr)
8715 %{
8716 effect(USE_DEF dst, USE shift, KILL cr);
8717
8718 format %{ "rorq $dst, $shift" %}
8719 opcode(0xD3, 0x1); /* D3 /1 */
8720 ins_encode(REX_reg_wide(dst), OpcP, reg_opc(dst));
8721 ins_pipe(ialu_reg_reg);
8722 %}
8723 // end of ROR expand
8724
8725 // Rotate Right by one
8726 instruct rorL_rReg_i1(rRegL dst, immI1 rshift, immI_M1 lshift, rFlagsReg cr)
8727 %{
8728 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8729
8730 expand %{
8731 rorL_rReg_imm1(dst, cr);
8732 %}
8733 %}
8734
8735 // Rotate Right by 8-bit immediate
8736 instruct rorL_rReg_i8(rRegL dst, immI8 rshift, immI8 lshift, rFlagsReg cr)
8737 %{
8738 predicate(0 == ((n->in(1)->in(2)->get_int() + n->in(2)->in(2)->get_int()) & 0x3f));
8739 match(Set dst (OrL (URShiftL dst rshift) (LShiftL dst lshift)));
8740
8741 expand %{
8742 rorL_rReg_imm8(dst, rshift, cr);
8743 %}
8744 %}
8745
8746 // Rotate Right by variable
8747 instruct rorL_rReg_Var_C0(no_rcx_RegL dst, rcx_RegI shift, immI0 zero, rFlagsReg cr)
8748 %{
8749 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI zero shift))));
8750
8751 expand %{
8752 rorL_rReg_CL(dst, shift, cr);
8753 %}
8754 %}
8755
8756 // Rotate Right by variable
8757 instruct rorL_rReg_Var_C64(no_rcx_RegL dst, rcx_RegI shift, immI_64 c64, rFlagsReg cr)
8758 %{
8759 match(Set dst (OrL (URShiftL dst shift) (LShiftL dst (SubI c64 shift))));
8760
8761 expand %{
8762 rorL_rReg_CL(dst, shift, cr);
8763 %}
8764 %}
8765
8766 // Logical Instructions
8767
8768 // Integer Logical Instructions
8769
8770 // And Instructions
8771 // And Register with Register
8772 instruct andI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8773 %{
8774 match(Set dst (AndI dst src));
8775 effect(KILL cr);
8776
8777 format %{ "andl $dst, $src\t# int" %}
8778 opcode(0x23);
8779 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
8780 ins_pipe(ialu_reg_reg);
8781 %}
8782
8783 // And Register with Immediate 255
8784 instruct andI_rReg_imm255(rRegI dst, immI_255 src)
8785 %{
8786 match(Set dst (AndI dst src));
8787
8788 format %{ "movzbl $dst, $dst\t# int & 0xFF" %}
8789 opcode(0x0F, 0xB6);
8790 ins_encode(REX_reg_breg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8791 ins_pipe(ialu_reg);
8792 %}
8793
8794 // And Register with Immediate 255 and promote to long
8795 instruct andI2L_rReg_imm255(rRegL dst, rRegI src, immI_255 mask)
8796 %{
8797 match(Set dst (ConvI2L (AndI src mask)));
8798
8799 format %{ "movzbl $dst, $src\t# int & 0xFF -> long" %}
8800 opcode(0x0F, 0xB6);
8801 ins_encode(REX_reg_breg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8802 ins_pipe(ialu_reg);
8803 %}
8804
8805 // And Register with Immediate 65535
8806 instruct andI_rReg_imm65535(rRegI dst, immI_65535 src)
8807 %{
8808 match(Set dst (AndI dst src));
8809
8810 format %{ "movzwl $dst, $dst\t# int & 0xFFFF" %}
8811 opcode(0x0F, 0xB7);
8812 ins_encode(REX_reg_reg(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
8813 ins_pipe(ialu_reg);
8814 %}
8815
8816 // And Register with Immediate 65535 and promote to long
8817 instruct andI2L_rReg_imm65535(rRegL dst, rRegI src, immI_65535 mask)
8818 %{
8819 match(Set dst (ConvI2L (AndI src mask)));
8820
8821 format %{ "movzwl $dst, $src\t# int & 0xFFFF -> long" %}
8822 opcode(0x0F, 0xB7);
8823 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
8824 ins_pipe(ialu_reg);
8825 %}
8826
8827 // And Register with Immediate
8828 instruct andI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
8829 %{
8830 match(Set dst (AndI dst src));
8831 effect(KILL cr);
8832
8833 format %{ "andl $dst, $src\t# int" %}
8834 opcode(0x81, 0x04); /* Opcode 81 /4 */
8835 ins_encode(OpcSErm(dst, src), Con8or32(src));
8836 ins_pipe(ialu_reg);
8837 %}
8838
8839 // And Register with Memory
8840 instruct andI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
8841 %{
8842 match(Set dst (AndI dst (LoadI src)));
8843 effect(KILL cr);
8844
8845 ins_cost(125);
8846 format %{ "andl $dst, $src\t# int" %}
8847 opcode(0x23);
8848 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
8849 ins_pipe(ialu_reg_mem);
8850 %}
8851
8852 // And Memory with Register
8853 instruct andI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
8854 %{
8855 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8856 effect(KILL cr);
8857
8858 ins_cost(150);
8859 format %{ "andl $dst, $src\t# int" %}
8860 opcode(0x21); /* Opcode 21 /r */
8861 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
8862 ins_pipe(ialu_mem_reg);
8863 %}
8864
8865 // And Memory with Immediate
8866 instruct andI_mem_imm(memory dst, immI src, rFlagsReg cr)
8867 %{
8868 match(Set dst (StoreI dst (AndI (LoadI dst) src)));
8869 effect(KILL cr);
8870
8871 ins_cost(125);
8872 format %{ "andl $dst, $src\t# int" %}
8873 opcode(0x81, 0x4); /* Opcode 81 /4 id */
8874 ins_encode(REX_mem(dst), OpcSE(src),
8875 RM_opc_mem(secondary, dst), Con8or32(src));
8876 ins_pipe(ialu_mem_imm);
8877 %}
8878
8879 // BMI1 instructions
8880 instruct andnI_rReg_rReg_mem(rRegI dst, rRegI src1, memory src2, immI_M1 minus_1, rFlagsReg cr) %{
8881 match(Set dst (AndI (XorI src1 minus_1) (LoadI src2)));
8882 predicate(UseBMI1Instructions);
8883 effect(KILL cr);
8884
8885 ins_cost(125);
8886 format %{ "andnl $dst, $src1, $src2" %}
8887
8888 ins_encode %{
8889 __ andnl($dst$$Register, $src1$$Register, $src2$$Address);
8890 %}
8891 ins_pipe(ialu_reg_mem);
8892 %}
8893
8894 instruct andnI_rReg_rReg_rReg(rRegI dst, rRegI src1, rRegI src2, immI_M1 minus_1, rFlagsReg cr) %{
8895 match(Set dst (AndI (XorI src1 minus_1) src2));
8896 predicate(UseBMI1Instructions);
8897 effect(KILL cr);
8898
8899 format %{ "andnl $dst, $src1, $src2" %}
8900
8901 ins_encode %{
8902 __ andnl($dst$$Register, $src1$$Register, $src2$$Register);
8903 %}
8904 ins_pipe(ialu_reg);
8905 %}
8906
8907 instruct blsiI_rReg_rReg(rRegI dst, rRegI src, immI0 imm_zero, rFlagsReg cr) %{
8908 match(Set dst (AndI (SubI imm_zero src) src));
8909 predicate(UseBMI1Instructions);
8910 effect(KILL cr);
8911
8912 format %{ "blsil $dst, $src" %}
8913
8914 ins_encode %{
8915 __ blsil($dst$$Register, $src$$Register);
8916 %}
8917 ins_pipe(ialu_reg);
8918 %}
8919
8920 instruct blsiI_rReg_mem(rRegI dst, memory src, immI0 imm_zero, rFlagsReg cr) %{
8921 match(Set dst (AndI (SubI imm_zero (LoadI src) ) (LoadI src) ));
8922 predicate(UseBMI1Instructions);
8923 effect(KILL cr);
8924
8925 ins_cost(125);
8926 format %{ "blsil $dst, $src" %}
8927
8928 ins_encode %{
8929 __ blsil($dst$$Register, $src$$Address);
8930 %}
8931 ins_pipe(ialu_reg_mem);
8932 %}
8933
8934 instruct blsmskI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8935 %{
8936 match(Set dst (XorI (AddI (LoadI src) minus_1) (LoadI src) ) );
8937 predicate(UseBMI1Instructions);
8938 effect(KILL cr);
8939
8940 ins_cost(125);
8941 format %{ "blsmskl $dst, $src" %}
8942
8943 ins_encode %{
8944 __ blsmskl($dst$$Register, $src$$Address);
8945 %}
8946 ins_pipe(ialu_reg_mem);
8947 %}
8948
8949 instruct blsmskI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8950 %{
8951 match(Set dst (XorI (AddI src minus_1) src));
8952 predicate(UseBMI1Instructions);
8953 effect(KILL cr);
8954
8955 format %{ "blsmskl $dst, $src" %}
8956
8957 ins_encode %{
8958 __ blsmskl($dst$$Register, $src$$Register);
8959 %}
8960
8961 ins_pipe(ialu_reg);
8962 %}
8963
8964 instruct blsrI_rReg_rReg(rRegI dst, rRegI src, immI_M1 minus_1, rFlagsReg cr)
8965 %{
8966 match(Set dst (AndI (AddI src minus_1) src) );
8967 predicate(UseBMI1Instructions);
8968 effect(KILL cr);
8969
8970 format %{ "blsrl $dst, $src" %}
8971
8972 ins_encode %{
8973 __ blsrl($dst$$Register, $src$$Register);
8974 %}
8975
8976 ins_pipe(ialu_reg_mem);
8977 %}
8978
8979 instruct blsrI_rReg_mem(rRegI dst, memory src, immI_M1 minus_1, rFlagsReg cr)
8980 %{
8981 match(Set dst (AndI (AddI (LoadI src) minus_1) (LoadI src) ) );
8982 predicate(UseBMI1Instructions);
8983 effect(KILL cr);
8984
8985 ins_cost(125);
8986 format %{ "blsrl $dst, $src" %}
8987
8988 ins_encode %{
8989 __ blsrl($dst$$Register, $src$$Address);
8990 %}
8991
8992 ins_pipe(ialu_reg);
8993 %}
8994
8995 // Or Instructions
8996 // Or Register with Register
8997 instruct orI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
8998 %{
8999 match(Set dst (OrI dst src));
9000 effect(KILL cr);
9001
9002 format %{ "orl $dst, $src\t# int" %}
9003 opcode(0x0B);
9004 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9005 ins_pipe(ialu_reg_reg);
9006 %}
9007
9008 // Or Register with Immediate
9009 instruct orI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9010 %{
9011 match(Set dst (OrI dst src));
9012 effect(KILL cr);
9013
9014 format %{ "orl $dst, $src\t# int" %}
9015 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9016 ins_encode(OpcSErm(dst, src), Con8or32(src));
9017 ins_pipe(ialu_reg);
9018 %}
9019
9020 // Or Register with Memory
9021 instruct orI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9022 %{
9023 match(Set dst (OrI dst (LoadI src)));
9024 effect(KILL cr);
9025
9026 ins_cost(125);
9027 format %{ "orl $dst, $src\t# int" %}
9028 opcode(0x0B);
9029 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9030 ins_pipe(ialu_reg_mem);
9031 %}
9032
9033 // Or Memory with Register
9034 instruct orI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9035 %{
9036 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9037 effect(KILL cr);
9038
9039 ins_cost(150);
9040 format %{ "orl $dst, $src\t# int" %}
9041 opcode(0x09); /* Opcode 09 /r */
9042 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9043 ins_pipe(ialu_mem_reg);
9044 %}
9045
9046 // Or Memory with Immediate
9047 instruct orI_mem_imm(memory dst, immI src, rFlagsReg cr)
9048 %{
9049 match(Set dst (StoreI dst (OrI (LoadI dst) src)));
9050 effect(KILL cr);
9051
9052 ins_cost(125);
9053 format %{ "orl $dst, $src\t# int" %}
9054 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9055 ins_encode(REX_mem(dst), OpcSE(src),
9056 RM_opc_mem(secondary, dst), Con8or32(src));
9057 ins_pipe(ialu_mem_imm);
9058 %}
9059
9060 // Xor Instructions
9061 // Xor Register with Register
9062 instruct xorI_rReg(rRegI dst, rRegI src, rFlagsReg cr)
9063 %{
9064 match(Set dst (XorI dst src));
9065 effect(KILL cr);
9066
9067 format %{ "xorl $dst, $src\t# int" %}
9068 opcode(0x33);
9069 ins_encode(REX_reg_reg(dst, src), OpcP, reg_reg(dst, src));
9070 ins_pipe(ialu_reg_reg);
9071 %}
9072
9073 // Xor Register with Immediate -1
9074 instruct xorI_rReg_im1(rRegI dst, immI_M1 imm) %{
9075 match(Set dst (XorI dst imm));
9076
9077 format %{ "not $dst" %}
9078 ins_encode %{
9079 __ notl($dst$$Register);
9080 %}
9081 ins_pipe(ialu_reg);
9082 %}
9083
9084 // Xor Register with Immediate
9085 instruct xorI_rReg_imm(rRegI dst, immI src, rFlagsReg cr)
9086 %{
9087 match(Set dst (XorI dst src));
9088 effect(KILL cr);
9089
9090 format %{ "xorl $dst, $src\t# int" %}
9091 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9092 ins_encode(OpcSErm(dst, src), Con8or32(src));
9093 ins_pipe(ialu_reg);
9094 %}
9095
9096 // Xor Register with Memory
9097 instruct xorI_rReg_mem(rRegI dst, memory src, rFlagsReg cr)
9098 %{
9099 match(Set dst (XorI dst (LoadI src)));
9100 effect(KILL cr);
9101
9102 ins_cost(125);
9103 format %{ "xorl $dst, $src\t# int" %}
9104 opcode(0x33);
9105 ins_encode(REX_reg_mem(dst, src), OpcP, reg_mem(dst, src));
9106 ins_pipe(ialu_reg_mem);
9107 %}
9108
9109 // Xor Memory with Register
9110 instruct xorI_mem_rReg(memory dst, rRegI src, rFlagsReg cr)
9111 %{
9112 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9113 effect(KILL cr);
9114
9115 ins_cost(150);
9116 format %{ "xorl $dst, $src\t# int" %}
9117 opcode(0x31); /* Opcode 31 /r */
9118 ins_encode(REX_reg_mem(src, dst), OpcP, reg_mem(src, dst));
9119 ins_pipe(ialu_mem_reg);
9120 %}
9121
9122 // Xor Memory with Immediate
9123 instruct xorI_mem_imm(memory dst, immI src, rFlagsReg cr)
9124 %{
9125 match(Set dst (StoreI dst (XorI (LoadI dst) src)));
9126 effect(KILL cr);
9127
9128 ins_cost(125);
9129 format %{ "xorl $dst, $src\t# int" %}
9130 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9131 ins_encode(REX_mem(dst), OpcSE(src),
9132 RM_opc_mem(secondary, dst), Con8or32(src));
9133 ins_pipe(ialu_mem_imm);
9134 %}
9135
9136
9137 // Long Logical Instructions
9138
9139 // And Instructions
9140 // And Register with Register
9141 instruct andL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9142 %{
9143 match(Set dst (AndL dst src));
9144 effect(KILL cr);
9145
9146 format %{ "andq $dst, $src\t# long" %}
9147 opcode(0x23);
9148 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9149 ins_pipe(ialu_reg_reg);
9150 %}
9151
9152 // And Register with Immediate 255
9153 instruct andL_rReg_imm255(rRegL dst, immL_255 src)
9154 %{
9155 match(Set dst (AndL dst src));
9156
9157 format %{ "movzbq $dst, $dst\t# long & 0xFF" %}
9158 opcode(0x0F, 0xB6);
9159 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9160 ins_pipe(ialu_reg);
9161 %}
9162
9163 // And Register with Immediate 65535
9164 instruct andL_rReg_imm65535(rRegL dst, immL_65535 src)
9165 %{
9166 match(Set dst (AndL dst src));
9167
9168 format %{ "movzwq $dst, $dst\t# long & 0xFFFF" %}
9169 opcode(0x0F, 0xB7);
9170 ins_encode(REX_reg_reg_wide(dst, dst), OpcP, OpcS, reg_reg(dst, dst));
9171 ins_pipe(ialu_reg);
9172 %}
9173
9174 // And Register with Immediate
9175 instruct andL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9176 %{
9177 match(Set dst (AndL dst src));
9178 effect(KILL cr);
9179
9180 format %{ "andq $dst, $src\t# long" %}
9181 opcode(0x81, 0x04); /* Opcode 81 /4 */
9182 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9183 ins_pipe(ialu_reg);
9184 %}
9185
9186 // And Register with Memory
9187 instruct andL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9188 %{
9189 match(Set dst (AndL dst (LoadL src)));
9190 effect(KILL cr);
9191
9192 ins_cost(125);
9193 format %{ "andq $dst, $src\t# long" %}
9194 opcode(0x23);
9195 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9196 ins_pipe(ialu_reg_mem);
9197 %}
9198
9199 // And Memory with Register
9200 instruct andL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9201 %{
9202 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9203 effect(KILL cr);
9204
9205 ins_cost(150);
9206 format %{ "andq $dst, $src\t# long" %}
9207 opcode(0x21); /* Opcode 21 /r */
9208 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9209 ins_pipe(ialu_mem_reg);
9210 %}
9211
9212 // And Memory with Immediate
9213 instruct andL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9214 %{
9215 match(Set dst (StoreL dst (AndL (LoadL dst) src)));
9216 effect(KILL cr);
9217
9218 ins_cost(125);
9219 format %{ "andq $dst, $src\t# long" %}
9220 opcode(0x81, 0x4); /* Opcode 81 /4 id */
9221 ins_encode(REX_mem_wide(dst), OpcSE(src),
9222 RM_opc_mem(secondary, dst), Con8or32(src));
9223 ins_pipe(ialu_mem_imm);
9224 %}
9225
9226 // BMI1 instructions
9227 instruct andnL_rReg_rReg_mem(rRegL dst, rRegL src1, memory src2, immL_M1 minus_1, rFlagsReg cr) %{
9228 match(Set dst (AndL (XorL src1 minus_1) (LoadL src2)));
9229 predicate(UseBMI1Instructions);
9230 effect(KILL cr);
9231
9232 ins_cost(125);
9233 format %{ "andnq $dst, $src1, $src2" %}
9234
9235 ins_encode %{
9236 __ andnq($dst$$Register, $src1$$Register, $src2$$Address);
9237 %}
9238 ins_pipe(ialu_reg_mem);
9239 %}
9240
9241 instruct andnL_rReg_rReg_rReg(rRegL dst, rRegL src1, rRegL src2, immL_M1 minus_1, rFlagsReg cr) %{
9242 match(Set dst (AndL (XorL src1 minus_1) src2));
9243 predicate(UseBMI1Instructions);
9244 effect(KILL cr);
9245
9246 format %{ "andnq $dst, $src1, $src2" %}
9247
9248 ins_encode %{
9249 __ andnq($dst$$Register, $src1$$Register, $src2$$Register);
9250 %}
9251 ins_pipe(ialu_reg_mem);
9252 %}
9253
9254 instruct blsiL_rReg_rReg(rRegL dst, rRegL src, immL0 imm_zero, rFlagsReg cr) %{
9255 match(Set dst (AndL (SubL imm_zero src) src));
9256 predicate(UseBMI1Instructions);
9257 effect(KILL cr);
9258
9259 format %{ "blsiq $dst, $src" %}
9260
9261 ins_encode %{
9262 __ blsiq($dst$$Register, $src$$Register);
9263 %}
9264 ins_pipe(ialu_reg);
9265 %}
9266
9267 instruct blsiL_rReg_mem(rRegL dst, memory src, immL0 imm_zero, rFlagsReg cr) %{
9268 match(Set dst (AndL (SubL imm_zero (LoadL src) ) (LoadL src) ));
9269 predicate(UseBMI1Instructions);
9270 effect(KILL cr);
9271
9272 ins_cost(125);
9273 format %{ "blsiq $dst, $src" %}
9274
9275 ins_encode %{
9276 __ blsiq($dst$$Register, $src$$Address);
9277 %}
9278 ins_pipe(ialu_reg_mem);
9279 %}
9280
9281 instruct blsmskL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9282 %{
9283 match(Set dst (XorL (AddL (LoadL src) minus_1) (LoadL src) ) );
9284 predicate(UseBMI1Instructions);
9285 effect(KILL cr);
9286
9287 ins_cost(125);
9288 format %{ "blsmskq $dst, $src" %}
9289
9290 ins_encode %{
9291 __ blsmskq($dst$$Register, $src$$Address);
9292 %}
9293 ins_pipe(ialu_reg_mem);
9294 %}
9295
9296 instruct blsmskL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9297 %{
9298 match(Set dst (XorL (AddL src minus_1) src));
9299 predicate(UseBMI1Instructions);
9300 effect(KILL cr);
9301
9302 format %{ "blsmskq $dst, $src" %}
9303
9304 ins_encode %{
9305 __ blsmskq($dst$$Register, $src$$Register);
9306 %}
9307
9308 ins_pipe(ialu_reg);
9309 %}
9310
9311 instruct blsrL_rReg_rReg(rRegL dst, rRegL src, immL_M1 minus_1, rFlagsReg cr)
9312 %{
9313 match(Set dst (AndL (AddL src minus_1) src) );
9314 predicate(UseBMI1Instructions);
9315 effect(KILL cr);
9316
9317 format %{ "blsrq $dst, $src" %}
9318
9319 ins_encode %{
9320 __ blsrq($dst$$Register, $src$$Register);
9321 %}
9322
9323 ins_pipe(ialu_reg);
9324 %}
9325
9326 instruct blsrL_rReg_mem(rRegL dst, memory src, immL_M1 minus_1, rFlagsReg cr)
9327 %{
9328 match(Set dst (AndL (AddL (LoadL src) minus_1) (LoadL src)) );
9329 predicate(UseBMI1Instructions);
9330 effect(KILL cr);
9331
9332 ins_cost(125);
9333 format %{ "blsrq $dst, $src" %}
9334
9335 ins_encode %{
9336 __ blsrq($dst$$Register, $src$$Address);
9337 %}
9338
9339 ins_pipe(ialu_reg);
9340 %}
9341
9342 // Or Instructions
9343 // Or Register with Register
9344 instruct orL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9345 %{
9346 match(Set dst (OrL dst src));
9347 effect(KILL cr);
9348
9349 format %{ "orq $dst, $src\t# long" %}
9350 opcode(0x0B);
9351 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9352 ins_pipe(ialu_reg_reg);
9353 %}
9354
9355 // Use any_RegP to match R15 (TLS register) without spilling.
9356 instruct orL_rReg_castP2X(rRegL dst, any_RegP src, rFlagsReg cr) %{
9357 match(Set dst (OrL dst (CastP2X src)));
9358 effect(KILL cr);
9359
9360 format %{ "orq $dst, $src\t# long" %}
9361 opcode(0x0B);
9362 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9363 ins_pipe(ialu_reg_reg);
9364 %}
9365
9366
9367 // Or Register with Immediate
9368 instruct orL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9369 %{
9370 match(Set dst (OrL dst src));
9371 effect(KILL cr);
9372
9373 format %{ "orq $dst, $src\t# long" %}
9374 opcode(0x81, 0x01); /* Opcode 81 /1 id */
9375 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9376 ins_pipe(ialu_reg);
9377 %}
9378
9379 // Or Register with Memory
9380 instruct orL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9381 %{
9382 match(Set dst (OrL dst (LoadL src)));
9383 effect(KILL cr);
9384
9385 ins_cost(125);
9386 format %{ "orq $dst, $src\t# long" %}
9387 opcode(0x0B);
9388 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9389 ins_pipe(ialu_reg_mem);
9390 %}
9391
9392 // Or Memory with Register
9393 instruct orL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9394 %{
9395 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9396 effect(KILL cr);
9397
9398 ins_cost(150);
9399 format %{ "orq $dst, $src\t# long" %}
9400 opcode(0x09); /* Opcode 09 /r */
9401 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9402 ins_pipe(ialu_mem_reg);
9403 %}
9404
9405 // Or Memory with Immediate
9406 instruct orL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9407 %{
9408 match(Set dst (StoreL dst (OrL (LoadL dst) src)));
9409 effect(KILL cr);
9410
9411 ins_cost(125);
9412 format %{ "orq $dst, $src\t# long" %}
9413 opcode(0x81, 0x1); /* Opcode 81 /1 id */
9414 ins_encode(REX_mem_wide(dst), OpcSE(src),
9415 RM_opc_mem(secondary, dst), Con8or32(src));
9416 ins_pipe(ialu_mem_imm);
9417 %}
9418
9419 // Xor Instructions
9420 // Xor Register with Register
9421 instruct xorL_rReg(rRegL dst, rRegL src, rFlagsReg cr)
9422 %{
9423 match(Set dst (XorL dst src));
9424 effect(KILL cr);
9425
9426 format %{ "xorq $dst, $src\t# long" %}
9427 opcode(0x33);
9428 ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst, src));
9429 ins_pipe(ialu_reg_reg);
9430 %}
9431
9432 // Xor Register with Immediate -1
9433 instruct xorL_rReg_im1(rRegL dst, immL_M1 imm) %{
9434 match(Set dst (XorL dst imm));
9435
9436 format %{ "notq $dst" %}
9437 ins_encode %{
9438 __ notq($dst$$Register);
9439 %}
9440 ins_pipe(ialu_reg);
9441 %}
9442
9443 // Xor Register with Immediate
9444 instruct xorL_rReg_imm(rRegL dst, immL32 src, rFlagsReg cr)
9445 %{
9446 match(Set dst (XorL dst src));
9447 effect(KILL cr);
9448
9449 format %{ "xorq $dst, $src\t# long" %}
9450 opcode(0x81, 0x06); /* Opcode 81 /6 id */
9451 ins_encode(OpcSErm_wide(dst, src), Con8or32(src));
9452 ins_pipe(ialu_reg);
9453 %}
9454
9455 // Xor Register with Memory
9456 instruct xorL_rReg_mem(rRegL dst, memory src, rFlagsReg cr)
9457 %{
9458 match(Set dst (XorL dst (LoadL src)));
9459 effect(KILL cr);
9460
9461 ins_cost(125);
9462 format %{ "xorq $dst, $src\t# long" %}
9463 opcode(0x33);
9464 ins_encode(REX_reg_mem_wide(dst, src), OpcP, reg_mem(dst, src));
9465 ins_pipe(ialu_reg_mem);
9466 %}
9467
9468 // Xor Memory with Register
9469 instruct xorL_mem_rReg(memory dst, rRegL src, rFlagsReg cr)
9470 %{
9471 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9472 effect(KILL cr);
9473
9474 ins_cost(150);
9475 format %{ "xorq $dst, $src\t# long" %}
9476 opcode(0x31); /* Opcode 31 /r */
9477 ins_encode(REX_reg_mem_wide(src, dst), OpcP, reg_mem(src, dst));
9478 ins_pipe(ialu_mem_reg);
9479 %}
9480
9481 // Xor Memory with Immediate
9482 instruct xorL_mem_imm(memory dst, immL32 src, rFlagsReg cr)
9483 %{
9484 match(Set dst (StoreL dst (XorL (LoadL dst) src)));
9485 effect(KILL cr);
9486
9487 ins_cost(125);
9488 format %{ "xorq $dst, $src\t# long" %}
9489 opcode(0x81, 0x6); /* Opcode 81 /6 id */
9490 ins_encode(REX_mem_wide(dst), OpcSE(src),
9491 RM_opc_mem(secondary, dst), Con8or32(src));
9492 ins_pipe(ialu_mem_imm);
9493 %}
9494
9495 // Convert Int to Boolean
9496 instruct convI2B(rRegI dst, rRegI src, rFlagsReg cr)
9497 %{
9498 match(Set dst (Conv2B src));
9499 effect(KILL cr);
9500
9501 format %{ "testl $src, $src\t# ci2b\n\t"
9502 "setnz $dst\n\t"
9503 "movzbl $dst, $dst" %}
9504 ins_encode(REX_reg_reg(src, src), opc_reg_reg(0x85, src, src), // testl
9505 setNZ_reg(dst),
9506 REX_reg_breg(dst, dst), // movzbl
9507 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9508 ins_pipe(pipe_slow); // XXX
9509 %}
9510
9511 // Convert Pointer to Boolean
9512 instruct convP2B(rRegI dst, rRegP src, rFlagsReg cr)
9513 %{
9514 match(Set dst (Conv2B src));
9515 effect(KILL cr);
9516
9517 format %{ "testq $src, $src\t# cp2b\n\t"
9518 "setnz $dst\n\t"
9519 "movzbl $dst, $dst" %}
9520 ins_encode(REX_reg_reg_wide(src, src), opc_reg_reg(0x85, src, src), // testq
9521 setNZ_reg(dst),
9522 REX_reg_breg(dst, dst), // movzbl
9523 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst));
9524 ins_pipe(pipe_slow); // XXX
9525 %}
9526
9527 instruct cmpLTMask(rRegI dst, rRegI p, rRegI q, rFlagsReg cr)
9528 %{
9529 match(Set dst (CmpLTMask p q));
9530 effect(KILL cr);
9531
9532 ins_cost(400);
9533 format %{ "cmpl $p, $q\t# cmpLTMask\n\t"
9534 "setlt $dst\n\t"
9535 "movzbl $dst, $dst\n\t"
9536 "negl $dst" %}
9537 ins_encode(REX_reg_reg(p, q), opc_reg_reg(0x3B, p, q), // cmpl
9538 setLT_reg(dst),
9539 REX_reg_breg(dst, dst), // movzbl
9540 Opcode(0x0F), Opcode(0xB6), reg_reg(dst, dst),
9541 neg_reg(dst));
9542 ins_pipe(pipe_slow);
9543 %}
9544
9545 instruct cmpLTMask0(rRegI dst, immI0 zero, rFlagsReg cr)
9546 %{
9547 match(Set dst (CmpLTMask dst zero));
9548 effect(KILL cr);
9549
9550 ins_cost(100);
9551 format %{ "sarl $dst, #31\t# cmpLTMask0" %}
9552 ins_encode %{
9553 __ sarl($dst$$Register, 31);
9554 %}
9555 ins_pipe(ialu_reg);
9556 %}
9557
9558 /* Better to save a register than avoid a branch */
9559 instruct cadd_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9560 %{
9561 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
9562 effect(KILL cr);
9563 ins_cost(300);
9564 format %{ "subl $p,$q\t# cadd_cmpLTMask\n\t"
9565 "jge done\n\t"
9566 "addl $p,$y\n"
9567 "done: " %}
9568 ins_encode %{
9569 Register Rp = $p$$Register;
9570 Register Rq = $q$$Register;
9571 Register Ry = $y$$Register;
9572 Label done;
9573 __ subl(Rp, Rq);
9574 __ jccb(Assembler::greaterEqual, done);
9575 __ addl(Rp, Ry);
9576 __ bind(done);
9577 %}
9578 ins_pipe(pipe_cmplt);
9579 %}
9580
9581 /* Better to save a register than avoid a branch */
9582 instruct and_cmpLTMask(rRegI p, rRegI q, rRegI y, rFlagsReg cr)
9583 %{
9584 match(Set y (AndI (CmpLTMask p q) y));
9585 effect(KILL cr);
9586
9587 ins_cost(300);
9588
9589 format %{ "cmpl $p, $q\t# and_cmpLTMask\n\t"
9590 "jlt done\n\t"
9591 "xorl $y, $y\n"
9592 "done: " %}
9593 ins_encode %{
9594 Register Rp = $p$$Register;
9595 Register Rq = $q$$Register;
9596 Register Ry = $y$$Register;
9597 Label done;
9598 __ cmpl(Rp, Rq);
9599 __ jccb(Assembler::less, done);
9600 __ xorl(Ry, Ry);
9601 __ bind(done);
9602 %}
9603 ins_pipe(pipe_cmplt);
9604 %}
9605
9606
9607 //---------- FP Instructions------------------------------------------------
9608
9609 instruct cmpF_cc_reg(rFlagsRegU cr, regF src1, regF src2)
9610 %{
9611 match(Set cr (CmpF src1 src2));
9612
9613 ins_cost(145);
9614 format %{ "ucomiss $src1, $src2\n\t"
9615 "jnp,s exit\n\t"
9616 "pushfq\t# saw NaN, set CF\n\t"
9617 "andq [rsp], #0xffffff2b\n\t"
9618 "popfq\n"
9619 "exit:" %}
9620 ins_encode %{
9621 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9622 emit_cmpfp_fixup(_masm);
9623 %}
9624 ins_pipe(pipe_slow);
9625 %}
9626
9627 instruct cmpF_cc_reg_CF(rFlagsRegUCF cr, regF src1, regF src2) %{
9628 match(Set cr (CmpF src1 src2));
9629
9630 ins_cost(100);
9631 format %{ "ucomiss $src1, $src2" %}
9632 ins_encode %{
9633 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9634 %}
9635 ins_pipe(pipe_slow);
9636 %}
9637
9638 instruct cmpF_cc_mem(rFlagsRegU cr, regF src1, memory src2)
9639 %{
9640 match(Set cr (CmpF src1 (LoadF src2)));
9641
9642 ins_cost(145);
9643 format %{ "ucomiss $src1, $src2\n\t"
9644 "jnp,s exit\n\t"
9645 "pushfq\t# saw NaN, set CF\n\t"
9646 "andq [rsp], #0xffffff2b\n\t"
9647 "popfq\n"
9648 "exit:" %}
9649 ins_encode %{
9650 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9651 emit_cmpfp_fixup(_masm);
9652 %}
9653 ins_pipe(pipe_slow);
9654 %}
9655
9656 instruct cmpF_cc_memCF(rFlagsRegUCF cr, regF src1, memory src2) %{
9657 match(Set cr (CmpF src1 (LoadF src2)));
9658
9659 ins_cost(100);
9660 format %{ "ucomiss $src1, $src2" %}
9661 ins_encode %{
9662 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9663 %}
9664 ins_pipe(pipe_slow);
9665 %}
9666
9667 instruct cmpF_cc_imm(rFlagsRegU cr, regF src, immF con) %{
9668 match(Set cr (CmpF src con));
9669
9670 ins_cost(145);
9671 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9672 "jnp,s exit\n\t"
9673 "pushfq\t# saw NaN, set CF\n\t"
9674 "andq [rsp], #0xffffff2b\n\t"
9675 "popfq\n"
9676 "exit:" %}
9677 ins_encode %{
9678 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9679 emit_cmpfp_fixup(_masm);
9680 %}
9681 ins_pipe(pipe_slow);
9682 %}
9683
9684 instruct cmpF_cc_immCF(rFlagsRegUCF cr, regF src, immF con) %{
9685 match(Set cr (CmpF src con));
9686 ins_cost(100);
9687 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con" %}
9688 ins_encode %{
9689 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9690 %}
9691 ins_pipe(pipe_slow);
9692 %}
9693
9694 instruct cmpD_cc_reg(rFlagsRegU cr, regD src1, regD src2)
9695 %{
9696 match(Set cr (CmpD src1 src2));
9697
9698 ins_cost(145);
9699 format %{ "ucomisd $src1, $src2\n\t"
9700 "jnp,s exit\n\t"
9701 "pushfq\t# saw NaN, set CF\n\t"
9702 "andq [rsp], #0xffffff2b\n\t"
9703 "popfq\n"
9704 "exit:" %}
9705 ins_encode %{
9706 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9707 emit_cmpfp_fixup(_masm);
9708 %}
9709 ins_pipe(pipe_slow);
9710 %}
9711
9712 instruct cmpD_cc_reg_CF(rFlagsRegUCF cr, regD src1, regD src2) %{
9713 match(Set cr (CmpD src1 src2));
9714
9715 ins_cost(100);
9716 format %{ "ucomisd $src1, $src2 test" %}
9717 ins_encode %{
9718 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9719 %}
9720 ins_pipe(pipe_slow);
9721 %}
9722
9723 instruct cmpD_cc_mem(rFlagsRegU cr, regD src1, memory src2)
9724 %{
9725 match(Set cr (CmpD src1 (LoadD src2)));
9726
9727 ins_cost(145);
9728 format %{ "ucomisd $src1, $src2\n\t"
9729 "jnp,s exit\n\t"
9730 "pushfq\t# saw NaN, set CF\n\t"
9731 "andq [rsp], #0xffffff2b\n\t"
9732 "popfq\n"
9733 "exit:" %}
9734 ins_encode %{
9735 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9736 emit_cmpfp_fixup(_masm);
9737 %}
9738 ins_pipe(pipe_slow);
9739 %}
9740
9741 instruct cmpD_cc_memCF(rFlagsRegUCF cr, regD src1, memory src2) %{
9742 match(Set cr (CmpD src1 (LoadD src2)));
9743
9744 ins_cost(100);
9745 format %{ "ucomisd $src1, $src2" %}
9746 ins_encode %{
9747 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9748 %}
9749 ins_pipe(pipe_slow);
9750 %}
9751
9752 instruct cmpD_cc_imm(rFlagsRegU cr, regD src, immD con) %{
9753 match(Set cr (CmpD src con));
9754
9755 ins_cost(145);
9756 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9757 "jnp,s exit\n\t"
9758 "pushfq\t# saw NaN, set CF\n\t"
9759 "andq [rsp], #0xffffff2b\n\t"
9760 "popfq\n"
9761 "exit:" %}
9762 ins_encode %{
9763 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9764 emit_cmpfp_fixup(_masm);
9765 %}
9766 ins_pipe(pipe_slow);
9767 %}
9768
9769 instruct cmpD_cc_immCF(rFlagsRegUCF cr, regD src, immD con) %{
9770 match(Set cr (CmpD src con));
9771 ins_cost(100);
9772 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con" %}
9773 ins_encode %{
9774 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9775 %}
9776 ins_pipe(pipe_slow);
9777 %}
9778
9779 // Compare into -1,0,1
9780 instruct cmpF_reg(rRegI dst, regF src1, regF src2, rFlagsReg cr)
9781 %{
9782 match(Set dst (CmpF3 src1 src2));
9783 effect(KILL cr);
9784
9785 ins_cost(275);
9786 format %{ "ucomiss $src1, $src2\n\t"
9787 "movl $dst, #-1\n\t"
9788 "jp,s done\n\t"
9789 "jb,s done\n\t"
9790 "setne $dst\n\t"
9791 "movzbl $dst, $dst\n"
9792 "done:" %}
9793 ins_encode %{
9794 __ ucomiss($src1$$XMMRegister, $src2$$XMMRegister);
9795 emit_cmpfp3(_masm, $dst$$Register);
9796 %}
9797 ins_pipe(pipe_slow);
9798 %}
9799
9800 // Compare into -1,0,1
9801 instruct cmpF_mem(rRegI dst, regF src1, memory src2, rFlagsReg cr)
9802 %{
9803 match(Set dst (CmpF3 src1 (LoadF src2)));
9804 effect(KILL cr);
9805
9806 ins_cost(275);
9807 format %{ "ucomiss $src1, $src2\n\t"
9808 "movl $dst, #-1\n\t"
9809 "jp,s done\n\t"
9810 "jb,s done\n\t"
9811 "setne $dst\n\t"
9812 "movzbl $dst, $dst\n"
9813 "done:" %}
9814 ins_encode %{
9815 __ ucomiss($src1$$XMMRegister, $src2$$Address);
9816 emit_cmpfp3(_masm, $dst$$Register);
9817 %}
9818 ins_pipe(pipe_slow);
9819 %}
9820
9821 // Compare into -1,0,1
9822 instruct cmpF_imm(rRegI dst, regF src, immF con, rFlagsReg cr) %{
9823 match(Set dst (CmpF3 src con));
9824 effect(KILL cr);
9825
9826 ins_cost(275);
9827 format %{ "ucomiss $src, [$constantaddress]\t# load from constant table: float=$con\n\t"
9828 "movl $dst, #-1\n\t"
9829 "jp,s done\n\t"
9830 "jb,s done\n\t"
9831 "setne $dst\n\t"
9832 "movzbl $dst, $dst\n"
9833 "done:" %}
9834 ins_encode %{
9835 __ ucomiss($src$$XMMRegister, $constantaddress($con));
9836 emit_cmpfp3(_masm, $dst$$Register);
9837 %}
9838 ins_pipe(pipe_slow);
9839 %}
9840
9841 // Compare into -1,0,1
9842 instruct cmpD_reg(rRegI dst, regD src1, regD src2, rFlagsReg cr)
9843 %{
9844 match(Set dst (CmpD3 src1 src2));
9845 effect(KILL cr);
9846
9847 ins_cost(275);
9848 format %{ "ucomisd $src1, $src2\n\t"
9849 "movl $dst, #-1\n\t"
9850 "jp,s done\n\t"
9851 "jb,s done\n\t"
9852 "setne $dst\n\t"
9853 "movzbl $dst, $dst\n"
9854 "done:" %}
9855 ins_encode %{
9856 __ ucomisd($src1$$XMMRegister, $src2$$XMMRegister);
9857 emit_cmpfp3(_masm, $dst$$Register);
9858 %}
9859 ins_pipe(pipe_slow);
9860 %}
9861
9862 // Compare into -1,0,1
9863 instruct cmpD_mem(rRegI dst, regD src1, memory src2, rFlagsReg cr)
9864 %{
9865 match(Set dst (CmpD3 src1 (LoadD src2)));
9866 effect(KILL cr);
9867
9868 ins_cost(275);
9869 format %{ "ucomisd $src1, $src2\n\t"
9870 "movl $dst, #-1\n\t"
9871 "jp,s done\n\t"
9872 "jb,s done\n\t"
9873 "setne $dst\n\t"
9874 "movzbl $dst, $dst\n"
9875 "done:" %}
9876 ins_encode %{
9877 __ ucomisd($src1$$XMMRegister, $src2$$Address);
9878 emit_cmpfp3(_masm, $dst$$Register);
9879 %}
9880 ins_pipe(pipe_slow);
9881 %}
9882
9883 // Compare into -1,0,1
9884 instruct cmpD_imm(rRegI dst, regD src, immD con, rFlagsReg cr) %{
9885 match(Set dst (CmpD3 src con));
9886 effect(KILL cr);
9887
9888 ins_cost(275);
9889 format %{ "ucomisd $src, [$constantaddress]\t# load from constant table: double=$con\n\t"
9890 "movl $dst, #-1\n\t"
9891 "jp,s done\n\t"
9892 "jb,s done\n\t"
9893 "setne $dst\n\t"
9894 "movzbl $dst, $dst\n"
9895 "done:" %}
9896 ins_encode %{
9897 __ ucomisd($src$$XMMRegister, $constantaddress($con));
9898 emit_cmpfp3(_masm, $dst$$Register);
9899 %}
9900 ins_pipe(pipe_slow);
9901 %}
9902
9903 // -----------Trig and Trancendental Instructions------------------------------
9904 instruct tanD_reg(regD dst) %{
9905 match(Set dst (TanD dst));
9906
9907 format %{ "dtan $dst\n\t" %}
9908 ins_encode( Push_SrcXD(dst),
9909 Opcode(0xD9), Opcode(0xF2), //fptan
9910 Opcode(0xDD), Opcode(0xD8), //fstp st
9911 Push_ResultXD(dst) );
9912 ins_pipe( pipe_slow );
9913 %}
9914
9915 instruct log10D_reg(regD dst) %{
9916 // The source and result Double operands in XMM registers
9917 match(Set dst (Log10D dst));
9918 // fldlg2 ; push log_10(2) on the FPU stack; full 80-bit number
9919 // fyl2x ; compute log_10(2) * log_2(x)
9920 format %{ "fldlg2\t\t\t#Log10\n\t"
9921 "fyl2x\t\t\t# Q=Log10*Log_2(x)\n\t"
9922 %}
9923 ins_encode(Opcode(0xD9), Opcode(0xEC), // fldlg2
9924 Push_SrcXD(dst),
9925 Opcode(0xD9), Opcode(0xF1), // fyl2x
9926 Push_ResultXD(dst));
9927
9928 ins_pipe( pipe_slow );
9929 %}
9930
9931 //----------Arithmetic Conversion Instructions---------------------------------
9932
9933 instruct roundFloat_nop(regF dst)
9934 %{
9935 match(Set dst (RoundFloat dst));
9936
9937 ins_cost(0);
9938 ins_encode();
9939 ins_pipe(empty);
9940 %}
9941
9942 instruct roundDouble_nop(regD dst)
9943 %{
9944 match(Set dst (RoundDouble dst));
9945
9946 ins_cost(0);
9947 ins_encode();
9948 ins_pipe(empty);
9949 %}
9950
9951 instruct convF2D_reg_reg(regD dst, regF src)
9952 %{
9953 match(Set dst (ConvF2D src));
9954
9955 format %{ "cvtss2sd $dst, $src" %}
9956 ins_encode %{
9957 __ cvtss2sd ($dst$$XMMRegister, $src$$XMMRegister);
9958 %}
9959 ins_pipe(pipe_slow); // XXX
9960 %}
9961
9962 instruct convF2D_reg_mem(regD dst, memory src)
9963 %{
9964 match(Set dst (ConvF2D (LoadF src)));
9965
9966 format %{ "cvtss2sd $dst, $src" %}
9967 ins_encode %{
9968 __ cvtss2sd ($dst$$XMMRegister, $src$$Address);
9969 %}
9970 ins_pipe(pipe_slow); // XXX
9971 %}
9972
9973 instruct convD2F_reg_reg(regF dst, regD src)
9974 %{
9975 match(Set dst (ConvD2F src));
9976
9977 format %{ "cvtsd2ss $dst, $src" %}
9978 ins_encode %{
9979 __ cvtsd2ss ($dst$$XMMRegister, $src$$XMMRegister);
9980 %}
9981 ins_pipe(pipe_slow); // XXX
9982 %}
9983
9984 instruct convD2F_reg_mem(regF dst, memory src)
9985 %{
9986 match(Set dst (ConvD2F (LoadD src)));
9987
9988 format %{ "cvtsd2ss $dst, $src" %}
9989 ins_encode %{
9990 __ cvtsd2ss ($dst$$XMMRegister, $src$$Address);
9991 %}
9992 ins_pipe(pipe_slow); // XXX
9993 %}
9994
9995 // XXX do mem variants
9996 instruct convF2I_reg_reg(rRegI dst, regF src, rFlagsReg cr)
9997 %{
9998 match(Set dst (ConvF2I src));
9999 effect(KILL cr);
10000
10001 format %{ "cvttss2sil $dst, $src\t# f2i\n\t"
10002 "cmpl $dst, #0x80000000\n\t"
10003 "jne,s done\n\t"
10004 "subq rsp, #8\n\t"
10005 "movss [rsp], $src\n\t"
10006 "call f2i_fixup\n\t"
10007 "popq $dst\n"
10008 "done: "%}
10009 ins_encode %{
10010 Label done;
10011 __ cvttss2sil($dst$$Register, $src$$XMMRegister);
10012 __ cmpl($dst$$Register, 0x80000000);
10013 __ jccb(Assembler::notEqual, done);
10014 __ subptr(rsp, 8);
10015 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10016 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2i_fixup())));
10017 __ pop($dst$$Register);
10018 __ bind(done);
10019 %}
10020 ins_pipe(pipe_slow);
10021 %}
10022
10023 instruct convF2L_reg_reg(rRegL dst, regF src, rFlagsReg cr)
10024 %{
10025 match(Set dst (ConvF2L src));
10026 effect(KILL cr);
10027
10028 format %{ "cvttss2siq $dst, $src\t# f2l\n\t"
10029 "cmpq $dst, [0x8000000000000000]\n\t"
10030 "jne,s done\n\t"
10031 "subq rsp, #8\n\t"
10032 "movss [rsp], $src\n\t"
10033 "call f2l_fixup\n\t"
10034 "popq $dst\n"
10035 "done: "%}
10036 ins_encode %{
10037 Label done;
10038 __ cvttss2siq($dst$$Register, $src$$XMMRegister);
10039 __ cmp64($dst$$Register,
10040 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10041 __ jccb(Assembler::notEqual, done);
10042 __ subptr(rsp, 8);
10043 __ movflt(Address(rsp, 0), $src$$XMMRegister);
10044 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::f2l_fixup())));
10045 __ pop($dst$$Register);
10046 __ bind(done);
10047 %}
10048 ins_pipe(pipe_slow);
10049 %}
10050
10051 instruct convD2I_reg_reg(rRegI dst, regD src, rFlagsReg cr)
10052 %{
10053 match(Set dst (ConvD2I src));
10054 effect(KILL cr);
10055
10056 format %{ "cvttsd2sil $dst, $src\t# d2i\n\t"
10057 "cmpl $dst, #0x80000000\n\t"
10058 "jne,s done\n\t"
10059 "subq rsp, #8\n\t"
10060 "movsd [rsp], $src\n\t"
10061 "call d2i_fixup\n\t"
10062 "popq $dst\n"
10063 "done: "%}
10064 ins_encode %{
10065 Label done;
10066 __ cvttsd2sil($dst$$Register, $src$$XMMRegister);
10067 __ cmpl($dst$$Register, 0x80000000);
10068 __ jccb(Assembler::notEqual, done);
10069 __ subptr(rsp, 8);
10070 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10071 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2i_fixup())));
10072 __ pop($dst$$Register);
10073 __ bind(done);
10074 %}
10075 ins_pipe(pipe_slow);
10076 %}
10077
10078 instruct convD2L_reg_reg(rRegL dst, regD src, rFlagsReg cr)
10079 %{
10080 match(Set dst (ConvD2L src));
10081 effect(KILL cr);
10082
10083 format %{ "cvttsd2siq $dst, $src\t# d2l\n\t"
10084 "cmpq $dst, [0x8000000000000000]\n\t"
10085 "jne,s done\n\t"
10086 "subq rsp, #8\n\t"
10087 "movsd [rsp], $src\n\t"
10088 "call d2l_fixup\n\t"
10089 "popq $dst\n"
10090 "done: "%}
10091 ins_encode %{
10092 Label done;
10093 __ cvttsd2siq($dst$$Register, $src$$XMMRegister);
10094 __ cmp64($dst$$Register,
10095 ExternalAddress((address) StubRoutines::x86::double_sign_flip()));
10096 __ jccb(Assembler::notEqual, done);
10097 __ subptr(rsp, 8);
10098 __ movdbl(Address(rsp, 0), $src$$XMMRegister);
10099 __ call(RuntimeAddress(CAST_FROM_FN_PTR(address, StubRoutines::x86::d2l_fixup())));
10100 __ pop($dst$$Register);
10101 __ bind(done);
10102 %}
10103 ins_pipe(pipe_slow);
10104 %}
10105
10106 instruct convI2F_reg_reg(regF dst, rRegI src)
10107 %{
10108 predicate(!UseXmmI2F);
10109 match(Set dst (ConvI2F src));
10110
10111 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10112 ins_encode %{
10113 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Register);
10114 %}
10115 ins_pipe(pipe_slow); // XXX
10116 %}
10117
10118 instruct convI2F_reg_mem(regF dst, memory src)
10119 %{
10120 match(Set dst (ConvI2F (LoadI src)));
10121
10122 format %{ "cvtsi2ssl $dst, $src\t# i2f" %}
10123 ins_encode %{
10124 __ cvtsi2ssl ($dst$$XMMRegister, $src$$Address);
10125 %}
10126 ins_pipe(pipe_slow); // XXX
10127 %}
10128
10129 instruct convI2D_reg_reg(regD dst, rRegI src)
10130 %{
10131 predicate(!UseXmmI2D);
10132 match(Set dst (ConvI2D src));
10133
10134 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10135 ins_encode %{
10136 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Register);
10137 %}
10138 ins_pipe(pipe_slow); // XXX
10139 %}
10140
10141 instruct convI2D_reg_mem(regD dst, memory src)
10142 %{
10143 match(Set dst (ConvI2D (LoadI src)));
10144
10145 format %{ "cvtsi2sdl $dst, $src\t# i2d" %}
10146 ins_encode %{
10147 __ cvtsi2sdl ($dst$$XMMRegister, $src$$Address);
10148 %}
10149 ins_pipe(pipe_slow); // XXX
10150 %}
10151
10152 instruct convXI2F_reg(regF dst, rRegI src)
10153 %{
10154 predicate(UseXmmI2F);
10155 match(Set dst (ConvI2F src));
10156
10157 format %{ "movdl $dst, $src\n\t"
10158 "cvtdq2psl $dst, $dst\t# i2f" %}
10159 ins_encode %{
10160 __ movdl($dst$$XMMRegister, $src$$Register);
10161 __ cvtdq2ps($dst$$XMMRegister, $dst$$XMMRegister);
10162 %}
10163 ins_pipe(pipe_slow); // XXX
10164 %}
10165
10166 instruct convXI2D_reg(regD dst, rRegI src)
10167 %{
10168 predicate(UseXmmI2D);
10169 match(Set dst (ConvI2D src));
10170
10171 format %{ "movdl $dst, $src\n\t"
10172 "cvtdq2pdl $dst, $dst\t# i2d" %}
10173 ins_encode %{
10174 __ movdl($dst$$XMMRegister, $src$$Register);
10175 __ cvtdq2pd($dst$$XMMRegister, $dst$$XMMRegister);
10176 %}
10177 ins_pipe(pipe_slow); // XXX
10178 %}
10179
10180 instruct convL2F_reg_reg(regF dst, rRegL src)
10181 %{
10182 match(Set dst (ConvL2F src));
10183
10184 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10185 ins_encode %{
10186 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Register);
10187 %}
10188 ins_pipe(pipe_slow); // XXX
10189 %}
10190
10191 instruct convL2F_reg_mem(regF dst, memory src)
10192 %{
10193 match(Set dst (ConvL2F (LoadL src)));
10194
10195 format %{ "cvtsi2ssq $dst, $src\t# l2f" %}
10196 ins_encode %{
10197 __ cvtsi2ssq ($dst$$XMMRegister, $src$$Address);
10198 %}
10199 ins_pipe(pipe_slow); // XXX
10200 %}
10201
10202 instruct convL2D_reg_reg(regD dst, rRegL src)
10203 %{
10204 match(Set dst (ConvL2D src));
10205
10206 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10207 ins_encode %{
10208 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Register);
10209 %}
10210 ins_pipe(pipe_slow); // XXX
10211 %}
10212
10213 instruct convL2D_reg_mem(regD dst, memory src)
10214 %{
10215 match(Set dst (ConvL2D (LoadL src)));
10216
10217 format %{ "cvtsi2sdq $dst, $src\t# l2d" %}
10218 ins_encode %{
10219 __ cvtsi2sdq ($dst$$XMMRegister, $src$$Address);
10220 %}
10221 ins_pipe(pipe_slow); // XXX
10222 %}
10223
10224 instruct convI2L_reg_reg(rRegL dst, rRegI src)
10225 %{
10226 match(Set dst (ConvI2L src));
10227
10228 ins_cost(125);
10229 format %{ "movslq $dst, $src\t# i2l" %}
10230 ins_encode %{
10231 __ movslq($dst$$Register, $src$$Register);
10232 %}
10233 ins_pipe(ialu_reg_reg);
10234 %}
10235
10236 // instruct convI2L_reg_reg_foo(rRegL dst, rRegI src)
10237 // %{
10238 // match(Set dst (ConvI2L src));
10239 // // predicate(_kids[0]->_leaf->as_Type()->type()->is_int()->_lo >= 0 &&
10240 // // _kids[0]->_leaf->as_Type()->type()->is_int()->_hi >= 0);
10241 // predicate(((const TypeNode*) n)->type()->is_long()->_hi ==
10242 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_hi &&
10243 // ((const TypeNode*) n)->type()->is_long()->_lo ==
10244 // (unsigned int) ((const TypeNode*) n)->type()->is_long()->_lo);
10245
10246 // format %{ "movl $dst, $src\t# unsigned i2l" %}
10247 // ins_encode(enc_copy(dst, src));
10248 // // opcode(0x63); // needs REX.W
10249 // // ins_encode(REX_reg_reg_wide(dst, src), OpcP, reg_reg(dst,src));
10250 // ins_pipe(ialu_reg_reg);
10251 // %}
10252
10253 // Zero-extend convert int to long
10254 instruct convI2L_reg_reg_zex(rRegL dst, rRegI src, immL_32bits mask)
10255 %{
10256 match(Set dst (AndL (ConvI2L src) mask));
10257
10258 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10259 ins_encode %{
10260 if ($dst$$reg != $src$$reg) {
10261 __ movl($dst$$Register, $src$$Register);
10262 }
10263 %}
10264 ins_pipe(ialu_reg_reg);
10265 %}
10266
10267 // Zero-extend convert int to long
10268 instruct convI2L_reg_mem_zex(rRegL dst, memory src, immL_32bits mask)
10269 %{
10270 match(Set dst (AndL (ConvI2L (LoadI src)) mask));
10271
10272 format %{ "movl $dst, $src\t# i2l zero-extend\n\t" %}
10273 ins_encode %{
10274 __ movl($dst$$Register, $src$$Address);
10275 %}
10276 ins_pipe(ialu_reg_mem);
10277 %}
10278
10279 instruct zerox_long_reg_reg(rRegL dst, rRegL src, immL_32bits mask)
10280 %{
10281 match(Set dst (AndL src mask));
10282
10283 format %{ "movl $dst, $src\t# zero-extend long" %}
10284 ins_encode %{
10285 __ movl($dst$$Register, $src$$Register);
10286 %}
10287 ins_pipe(ialu_reg_reg);
10288 %}
10289
10290 instruct convL2I_reg_reg(rRegI dst, rRegL src)
10291 %{
10292 match(Set dst (ConvL2I src));
10293
10294 format %{ "movl $dst, $src\t# l2i" %}
10295 ins_encode %{
10296 __ movl($dst$$Register, $src$$Register);
10297 %}
10298 ins_pipe(ialu_reg_reg);
10299 %}
10300
10301
10302 instruct MoveF2I_stack_reg(rRegI dst, stackSlotF src) %{
10303 match(Set dst (MoveF2I src));
10304 effect(DEF dst, USE src);
10305
10306 ins_cost(125);
10307 format %{ "movl $dst, $src\t# MoveF2I_stack_reg" %}
10308 ins_encode %{
10309 __ movl($dst$$Register, Address(rsp, $src$$disp));
10310 %}
10311 ins_pipe(ialu_reg_mem);
10312 %}
10313
10314 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
10315 match(Set dst (MoveI2F src));
10316 effect(DEF dst, USE src);
10317
10318 ins_cost(125);
10319 format %{ "movss $dst, $src\t# MoveI2F_stack_reg" %}
10320 ins_encode %{
10321 __ movflt($dst$$XMMRegister, Address(rsp, $src$$disp));
10322 %}
10323 ins_pipe(pipe_slow);
10324 %}
10325
10326 instruct MoveD2L_stack_reg(rRegL dst, stackSlotD src) %{
10327 match(Set dst (MoveD2L src));
10328 effect(DEF dst, USE src);
10329
10330 ins_cost(125);
10331 format %{ "movq $dst, $src\t# MoveD2L_stack_reg" %}
10332 ins_encode %{
10333 __ movq($dst$$Register, Address(rsp, $src$$disp));
10334 %}
10335 ins_pipe(ialu_reg_mem);
10336 %}
10337
10338 instruct MoveL2D_stack_reg_partial(regD dst, stackSlotL src) %{
10339 predicate(!UseXmmLoadAndClearUpper);
10340 match(Set dst (MoveL2D src));
10341 effect(DEF dst, USE src);
10342
10343 ins_cost(125);
10344 format %{ "movlpd $dst, $src\t# MoveL2D_stack_reg" %}
10345 ins_encode %{
10346 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10347 %}
10348 ins_pipe(pipe_slow);
10349 %}
10350
10351 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
10352 predicate(UseXmmLoadAndClearUpper);
10353 match(Set dst (MoveL2D src));
10354 effect(DEF dst, USE src);
10355
10356 ins_cost(125);
10357 format %{ "movsd $dst, $src\t# MoveL2D_stack_reg" %}
10358 ins_encode %{
10359 __ movdbl($dst$$XMMRegister, Address(rsp, $src$$disp));
10360 %}
10361 ins_pipe(pipe_slow);
10362 %}
10363
10364
10365 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
10366 match(Set dst (MoveF2I src));
10367 effect(DEF dst, USE src);
10368
10369 ins_cost(95); // XXX
10370 format %{ "movss $dst, $src\t# MoveF2I_reg_stack" %}
10371 ins_encode %{
10372 __ movflt(Address(rsp, $dst$$disp), $src$$XMMRegister);
10373 %}
10374 ins_pipe(pipe_slow);
10375 %}
10376
10377 instruct MoveI2F_reg_stack(stackSlotF dst, rRegI src) %{
10378 match(Set dst (MoveI2F src));
10379 effect(DEF dst, USE src);
10380
10381 ins_cost(100);
10382 format %{ "movl $dst, $src\t# MoveI2F_reg_stack" %}
10383 ins_encode %{
10384 __ movl(Address(rsp, $dst$$disp), $src$$Register);
10385 %}
10386 ins_pipe( ialu_mem_reg );
10387 %}
10388
10389 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
10390 match(Set dst (MoveD2L src));
10391 effect(DEF dst, USE src);
10392
10393 ins_cost(95); // XXX
10394 format %{ "movsd $dst, $src\t# MoveL2D_reg_stack" %}
10395 ins_encode %{
10396 __ movdbl(Address(rsp, $dst$$disp), $src$$XMMRegister);
10397 %}
10398 ins_pipe(pipe_slow);
10399 %}
10400
10401 instruct MoveL2D_reg_stack(stackSlotD dst, rRegL src) %{
10402 match(Set dst (MoveL2D src));
10403 effect(DEF dst, USE src);
10404
10405 ins_cost(100);
10406 format %{ "movq $dst, $src\t# MoveL2D_reg_stack" %}
10407 ins_encode %{
10408 __ movq(Address(rsp, $dst$$disp), $src$$Register);
10409 %}
10410 ins_pipe(ialu_mem_reg);
10411 %}
10412
10413 instruct MoveF2I_reg_reg(rRegI dst, regF src) %{
10414 match(Set dst (MoveF2I src));
10415 effect(DEF dst, USE src);
10416 ins_cost(85);
10417 format %{ "movd $dst,$src\t# MoveF2I" %}
10418 ins_encode %{
10419 __ movdl($dst$$Register, $src$$XMMRegister);
10420 %}
10421 ins_pipe( pipe_slow );
10422 %}
10423
10424 instruct MoveD2L_reg_reg(rRegL dst, regD src) %{
10425 match(Set dst (MoveD2L src));
10426 effect(DEF dst, USE src);
10427 ins_cost(85);
10428 format %{ "movd $dst,$src\t# MoveD2L" %}
10429 ins_encode %{
10430 __ movdq($dst$$Register, $src$$XMMRegister);
10431 %}
10432 ins_pipe( pipe_slow );
10433 %}
10434
10435 instruct MoveI2F_reg_reg(regF dst, rRegI src) %{
10436 match(Set dst (MoveI2F src));
10437 effect(DEF dst, USE src);
10438 ins_cost(100);
10439 format %{ "movd $dst,$src\t# MoveI2F" %}
10440 ins_encode %{
10441 __ movdl($dst$$XMMRegister, $src$$Register);
10442 %}
10443 ins_pipe( pipe_slow );
10444 %}
10445
10446 instruct MoveL2D_reg_reg(regD dst, rRegL src) %{
10447 match(Set dst (MoveL2D src));
10448 effect(DEF dst, USE src);
10449 ins_cost(100);
10450 format %{ "movd $dst,$src\t# MoveL2D" %}
10451 ins_encode %{
10452 __ movdq($dst$$XMMRegister, $src$$Register);
10453 %}
10454 ins_pipe( pipe_slow );
10455 %}
10456
10457
10458 // =======================================================================
10459 // fast clearing of an array
10460 instruct rep_stos(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10461 rFlagsReg cr)
10462 %{
10463 predicate(!UseFastStosb);
10464 match(Set dummy (ClearArray cnt base));
10465 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10466
10467 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10468 "rep stosq\t# Store rax to *rdi++ while rcx--" %}
10469 ins_encode %{
10470 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10471 %}
10472 ins_pipe(pipe_slow);
10473 %}
10474
10475 instruct rep_fast_stosb(rcx_RegL cnt, rdi_RegP base, rax_RegI zero, Universe dummy,
10476 rFlagsReg cr)
10477 %{
10478 predicate(UseFastStosb);
10479 match(Set dummy (ClearArray cnt base));
10480 effect(USE_KILL cnt, USE_KILL base, KILL zero, KILL cr);
10481 format %{ "xorq rax, rax\t# ClearArray:\n\t"
10482 "shlq rcx,3\t# Convert doublewords to bytes\n\t"
10483 "rep stosb\t# Store rax to *rdi++ while rcx--" %}
10484 ins_encode %{
10485 __ clear_mem($base$$Register, $cnt$$Register, $zero$$Register);
10486 %}
10487 ins_pipe( pipe_slow );
10488 %}
10489
10490 instruct string_compareL(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10491 rax_RegI result, regD tmp1, rFlagsReg cr)
10492 %{
10493 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LL);
10494 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10495 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10496
10497 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10498 ins_encode %{
10499 __ string_compare($str1$$Register, $str2$$Register,
10500 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10501 $tmp1$$XMMRegister, StrIntrinsicNode::LL);
10502 %}
10503 ins_pipe( pipe_slow );
10504 %}
10505
10506 instruct string_compareU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10507 rax_RegI result, regD tmp1, rFlagsReg cr)
10508 %{
10509 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UU);
10510 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10511 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10512
10513 format %{ "String Compare char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10514 ins_encode %{
10515 __ string_compare($str1$$Register, $str2$$Register,
10516 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10517 $tmp1$$XMMRegister, StrIntrinsicNode::UU);
10518 %}
10519 ins_pipe( pipe_slow );
10520 %}
10521
10522 instruct string_compareLU(rdi_RegP str1, rcx_RegI cnt1, rsi_RegP str2, rdx_RegI cnt2,
10523 rax_RegI result, regD tmp1, rFlagsReg cr)
10524 %{
10525 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::LU);
10526 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10527 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10528
10529 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10530 ins_encode %{
10531 __ string_compare($str1$$Register, $str2$$Register,
10532 $cnt1$$Register, $cnt2$$Register, $result$$Register,
10533 $tmp1$$XMMRegister, StrIntrinsicNode::LU);
10534 %}
10535 ins_pipe( pipe_slow );
10536 %}
10537
10538 instruct string_compareUL(rsi_RegP str1, rdx_RegI cnt1, rdi_RegP str2, rcx_RegI cnt2,
10539 rax_RegI result, regD tmp1, rFlagsReg cr)
10540 %{
10541 predicate(((StrCompNode*)n)->encoding() == StrIntrinsicNode::UL);
10542 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10543 effect(TEMP tmp1, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL cr);
10544
10545 format %{ "String Compare byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp1" %}
10546 ins_encode %{
10547 __ string_compare($str2$$Register, $str1$$Register,
10548 $cnt2$$Register, $cnt1$$Register, $result$$Register,
10549 $tmp1$$XMMRegister, StrIntrinsicNode::UL);
10550 %}
10551 ins_pipe( pipe_slow );
10552 %}
10553
10554 // fast search of substring with known size.
10555 instruct string_indexof_conL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10556 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10557 %{
10558 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10559 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10560 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10561
10562 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10563 ins_encode %{
10564 int icnt2 = (int)$int_cnt2$$constant;
10565 if (icnt2 >= 16) {
10566 // IndexOf for constant substrings with size >= 16 elements
10567 // which don't need to be loaded through stack.
10568 __ string_indexofC8($str1$$Register, $str2$$Register,
10569 $cnt1$$Register, $cnt2$$Register,
10570 icnt2, $result$$Register,
10571 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10572 } else {
10573 // Small strings are loaded through stack if they cross page boundary.
10574 __ string_indexof($str1$$Register, $str2$$Register,
10575 $cnt1$$Register, $cnt2$$Register,
10576 icnt2, $result$$Register,
10577 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10578 }
10579 %}
10580 ins_pipe( pipe_slow );
10581 %}
10582
10583 // fast search of substring with known size.
10584 instruct string_indexof_conU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10585 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10586 %{
10587 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10588 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10589 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10590
10591 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10592 ins_encode %{
10593 int icnt2 = (int)$int_cnt2$$constant;
10594 if (icnt2 >= 8) {
10595 // IndexOf for constant substrings with size >= 8 elements
10596 // which don't need to be loaded through stack.
10597 __ string_indexofC8($str1$$Register, $str2$$Register,
10598 $cnt1$$Register, $cnt2$$Register,
10599 icnt2, $result$$Register,
10600 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10601 } else {
10602 // Small strings are loaded through stack if they cross page boundary.
10603 __ string_indexof($str1$$Register, $str2$$Register,
10604 $cnt1$$Register, $cnt2$$Register,
10605 icnt2, $result$$Register,
10606 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10607 }
10608 %}
10609 ins_pipe( pipe_slow );
10610 %}
10611
10612 // fast search of substring with known size.
10613 instruct string_indexof_conUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, immI int_cnt2,
10614 rbx_RegI result, regD vec, rax_RegI cnt2, rcx_RegI tmp, rFlagsReg cr)
10615 %{
10616 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10617 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 int_cnt2)));
10618 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, KILL cnt2, KILL tmp, KILL cr);
10619
10620 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$int_cnt2 -> $result // KILL $vec, $cnt1, $cnt2, $tmp" %}
10621 ins_encode %{
10622 int icnt2 = (int)$int_cnt2$$constant;
10623 if (icnt2 >= 8) {
10624 // IndexOf for constant substrings with size >= 8 elements
10625 // which don't need to be loaded through stack.
10626 __ string_indexofC8($str1$$Register, $str2$$Register,
10627 $cnt1$$Register, $cnt2$$Register,
10628 icnt2, $result$$Register,
10629 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10630 } else {
10631 // Small strings are loaded through stack if they cross page boundary.
10632 __ string_indexof($str1$$Register, $str2$$Register,
10633 $cnt1$$Register, $cnt2$$Register,
10634 icnt2, $result$$Register,
10635 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10636 }
10637 %}
10638 ins_pipe( pipe_slow );
10639 %}
10640
10641 instruct string_indexofL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10642 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10643 %{
10644 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::LL));
10645 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10646 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10647
10648 format %{ "String IndexOf byte[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10649 ins_encode %{
10650 __ string_indexof($str1$$Register, $str2$$Register,
10651 $cnt1$$Register, $cnt2$$Register,
10652 (-1), $result$$Register,
10653 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::LL);
10654 %}
10655 ins_pipe( pipe_slow );
10656 %}
10657
10658 instruct string_indexofU(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10659 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10660 %{
10661 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UU));
10662 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10663 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10664
10665 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10666 ins_encode %{
10667 __ string_indexof($str1$$Register, $str2$$Register,
10668 $cnt1$$Register, $cnt2$$Register,
10669 (-1), $result$$Register,
10670 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UU);
10671 %}
10672 ins_pipe( pipe_slow );
10673 %}
10674
10675 instruct string_indexofUL(rdi_RegP str1, rdx_RegI cnt1, rsi_RegP str2, rax_RegI cnt2,
10676 rbx_RegI result, regD vec, rcx_RegI tmp, rFlagsReg cr)
10677 %{
10678 predicate(UseSSE42Intrinsics && (((StrIndexOfNode*)n)->encoding() == StrIntrinsicNode::UL));
10679 match(Set result (StrIndexOf (Binary str1 cnt1) (Binary str2 cnt2)));
10680 effect(TEMP vec, USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL tmp, KILL cr);
10681
10682 format %{ "String IndexOf char[] $str1,$cnt1,$str2,$cnt2 -> $result // KILL all" %}
10683 ins_encode %{
10684 __ string_indexof($str1$$Register, $str2$$Register,
10685 $cnt1$$Register, $cnt2$$Register,
10686 (-1), $result$$Register,
10687 $vec$$XMMRegister, $tmp$$Register, StrIntrinsicNode::UL);
10688 %}
10689 ins_pipe( pipe_slow );
10690 %}
10691
10692 instruct string_indexofU_char(rdi_RegP str1, rdx_RegI cnt1, rax_RegI ch,
10693 rbx_RegI result, regD vec1, regD vec2, regD vec3, rcx_RegI tmp, rFlagsReg cr)
10694 %{
10695 predicate(UseSSE42Intrinsics);
10696 match(Set result (StrIndexOfChar (Binary str1 cnt1) ch));
10697 effect(TEMP vec1, TEMP vec2, TEMP vec3, USE_KILL str1, USE_KILL cnt1, USE_KILL ch, TEMP tmp, KILL cr);
10698 format %{ "String IndexOf char[] $str1,$cnt1,$ch -> $result // KILL all" %}
10699 ins_encode %{
10700 __ string_indexof_char($str1$$Register, $cnt1$$Register, $ch$$Register, $result$$Register,
10701 $vec1$$XMMRegister, $vec2$$XMMRegister, $vec3$$XMMRegister, $tmp$$Register);
10702 %}
10703 ins_pipe( pipe_slow );
10704 %}
10705
10706 // fast string equals
10707 instruct string_equals(rdi_RegP str1, rsi_RegP str2, rcx_RegI cnt, rax_RegI result,
10708 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10709 %{
10710 match(Set result (StrEquals (Binary str1 str2) cnt));
10711 effect(TEMP tmp1, TEMP tmp2, USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp3, KILL cr);
10712
10713 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10714 ins_encode %{
10715 __ arrays_equals(false, $str1$$Register, $str2$$Register,
10716 $cnt$$Register, $result$$Register, $tmp3$$Register,
10717 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10718 %}
10719 ins_pipe( pipe_slow );
10720 %}
10721
10722 // fast array equals
10723 instruct array_equalsB(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10724 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10725 %{
10726 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::LL);
10727 match(Set result (AryEq ary1 ary2));
10728 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10729
10730 format %{ "Array Equals byte[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10731 ins_encode %{
10732 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10733 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10734 $tmp1$$XMMRegister, $tmp2$$XMMRegister, false /* char */);
10735 %}
10736 ins_pipe( pipe_slow );
10737 %}
10738
10739 instruct array_equalsC(rdi_RegP ary1, rsi_RegP ary2, rax_RegI result,
10740 regD tmp1, regD tmp2, rcx_RegI tmp3, rbx_RegI tmp4, rFlagsReg cr)
10741 %{
10742 predicate(((AryEqNode*)n)->encoding() == StrIntrinsicNode::UU);
10743 match(Set result (AryEq ary1 ary2));
10744 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL ary2, KILL tmp3, KILL tmp4, KILL cr);
10745
10746 format %{ "Array Equals char[] $ary1,$ary2 -> $result // KILL $tmp1, $tmp2, $tmp3, $tmp4" %}
10747 ins_encode %{
10748 __ arrays_equals(true, $ary1$$Register, $ary2$$Register,
10749 $tmp3$$Register, $result$$Register, $tmp4$$Register,
10750 $tmp1$$XMMRegister, $tmp2$$XMMRegister, true /* char */);
10751 %}
10752 ins_pipe( pipe_slow );
10753 %}
10754
10755 instruct has_negatives(rsi_RegP ary1, rcx_RegI len, rax_RegI result,
10756 regD tmp1, regD tmp2, rbx_RegI tmp3, rFlagsReg cr)
10757 %{
10758 match(Set result (HasNegatives ary1 len));
10759 effect(TEMP tmp1, TEMP tmp2, USE_KILL ary1, USE_KILL len, KILL tmp3, KILL cr);
10760
10761 format %{ "has negatives byte[] $ary1,$len -> $result // KILL $tmp1, $tmp2, $tmp3" %}
10762 ins_encode %{
10763 __ has_negatives($ary1$$Register, $len$$Register,
10764 $result$$Register, $tmp3$$Register,
10765 $tmp1$$XMMRegister, $tmp2$$XMMRegister);
10766 %}
10767 ins_pipe( pipe_slow );
10768 %}
10769
10770 // fast char[] to byte[] compression
10771 instruct string_compress(rsi_RegP src, rdi_RegP dst, rdx_RegI len, regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10772 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10773 match(Set result (StrCompressedCopy src (Binary dst len)));
10774 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10775
10776 format %{ "String Compress $src,$dst -> $result // KILL RAX, RCX, RDX" %}
10777 ins_encode %{
10778 __ char_array_compress($src$$Register, $dst$$Register, $len$$Register,
10779 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10780 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10781 %}
10782 ins_pipe( pipe_slow );
10783 %}
10784
10785 // fast byte[] to char[] inflation
10786 instruct string_inflate(Universe dummy, rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10787 regD tmp1, rcx_RegI tmp2, rFlagsReg cr) %{
10788 match(Set dummy (StrInflatedCopy src (Binary dst len)));
10789 effect(TEMP tmp1, TEMP tmp2, USE_KILL src, USE_KILL dst, USE_KILL len, KILL cr);
10790
10791 format %{ "String Inflate $src,$dst // KILL $tmp1, $tmp2" %}
10792 ins_encode %{
10793 __ byte_array_inflate($src$$Register, $dst$$Register, $len$$Register,
10794 $tmp1$$XMMRegister, $tmp2$$Register);
10795 %}
10796 ins_pipe( pipe_slow );
10797 %}
10798
10799 // encode char[] to byte[] in ISO_8859_1
10800 instruct encode_iso_array(rsi_RegP src, rdi_RegP dst, rdx_RegI len,
10801 regD tmp1, regD tmp2, regD tmp3, regD tmp4,
10802 rcx_RegI tmp5, rax_RegI result, rFlagsReg cr) %{
10803 match(Set result (EncodeISOArray src (Binary dst len)));
10804 effect(TEMP tmp1, TEMP tmp2, TEMP tmp3, TEMP tmp4, USE_KILL src, USE_KILL dst, USE_KILL len, KILL tmp5, KILL cr);
10805
10806 format %{ "Encode array $src,$dst,$len -> $result // KILL RCX, RDX, $tmp1, $tmp2, $tmp3, $tmp4, RSI, RDI " %}
10807 ins_encode %{
10808 __ encode_iso_array($src$$Register, $dst$$Register, $len$$Register,
10809 $tmp1$$XMMRegister, $tmp2$$XMMRegister, $tmp3$$XMMRegister,
10810 $tmp4$$XMMRegister, $tmp5$$Register, $result$$Register);
10811 %}
10812 ins_pipe( pipe_slow );
10813 %}
10814
10815 //----------Overflow Math Instructions-----------------------------------------
10816
10817 instruct overflowAddI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10818 %{
10819 match(Set cr (OverflowAddI op1 op2));
10820 effect(DEF cr, USE_KILL op1, USE op2);
10821
10822 format %{ "addl $op1, $op2\t# overflow check int" %}
10823
10824 ins_encode %{
10825 __ addl($op1$$Register, $op2$$Register);
10826 %}
10827 ins_pipe(ialu_reg_reg);
10828 %}
10829
10830 instruct overflowAddI_rReg_imm(rFlagsReg cr, rax_RegI op1, immI op2)
10831 %{
10832 match(Set cr (OverflowAddI op1 op2));
10833 effect(DEF cr, USE_KILL op1, USE op2);
10834
10835 format %{ "addl $op1, $op2\t# overflow check int" %}
10836
10837 ins_encode %{
10838 __ addl($op1$$Register, $op2$$constant);
10839 %}
10840 ins_pipe(ialu_reg_reg);
10841 %}
10842
10843 instruct overflowAddL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10844 %{
10845 match(Set cr (OverflowAddL op1 op2));
10846 effect(DEF cr, USE_KILL op1, USE op2);
10847
10848 format %{ "addq $op1, $op2\t# overflow check long" %}
10849 ins_encode %{
10850 __ addq($op1$$Register, $op2$$Register);
10851 %}
10852 ins_pipe(ialu_reg_reg);
10853 %}
10854
10855 instruct overflowAddL_rReg_imm(rFlagsReg cr, rax_RegL op1, immL32 op2)
10856 %{
10857 match(Set cr (OverflowAddL op1 op2));
10858 effect(DEF cr, USE_KILL op1, USE op2);
10859
10860 format %{ "addq $op1, $op2\t# overflow check long" %}
10861 ins_encode %{
10862 __ addq($op1$$Register, $op2$$constant);
10863 %}
10864 ins_pipe(ialu_reg_reg);
10865 %}
10866
10867 instruct overflowSubI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10868 %{
10869 match(Set cr (OverflowSubI op1 op2));
10870
10871 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10872 ins_encode %{
10873 __ cmpl($op1$$Register, $op2$$Register);
10874 %}
10875 ins_pipe(ialu_reg_reg);
10876 %}
10877
10878 instruct overflowSubI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
10879 %{
10880 match(Set cr (OverflowSubI op1 op2));
10881
10882 format %{ "cmpl $op1, $op2\t# overflow check int" %}
10883 ins_encode %{
10884 __ cmpl($op1$$Register, $op2$$constant);
10885 %}
10886 ins_pipe(ialu_reg_reg);
10887 %}
10888
10889 instruct overflowSubL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
10890 %{
10891 match(Set cr (OverflowSubL op1 op2));
10892
10893 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10894 ins_encode %{
10895 __ cmpq($op1$$Register, $op2$$Register);
10896 %}
10897 ins_pipe(ialu_reg_reg);
10898 %}
10899
10900 instruct overflowSubL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
10901 %{
10902 match(Set cr (OverflowSubL op1 op2));
10903
10904 format %{ "cmpq $op1, $op2\t# overflow check long" %}
10905 ins_encode %{
10906 __ cmpq($op1$$Register, $op2$$constant);
10907 %}
10908 ins_pipe(ialu_reg_reg);
10909 %}
10910
10911 instruct overflowNegI_rReg(rFlagsReg cr, immI0 zero, rax_RegI op2)
10912 %{
10913 match(Set cr (OverflowSubI zero op2));
10914 effect(DEF cr, USE_KILL op2);
10915
10916 format %{ "negl $op2\t# overflow check int" %}
10917 ins_encode %{
10918 __ negl($op2$$Register);
10919 %}
10920 ins_pipe(ialu_reg_reg);
10921 %}
10922
10923 instruct overflowNegL_rReg(rFlagsReg cr, immL0 zero, rax_RegL op2)
10924 %{
10925 match(Set cr (OverflowSubL zero op2));
10926 effect(DEF cr, USE_KILL op2);
10927
10928 format %{ "negq $op2\t# overflow check long" %}
10929 ins_encode %{
10930 __ negq($op2$$Register);
10931 %}
10932 ins_pipe(ialu_reg_reg);
10933 %}
10934
10935 instruct overflowMulI_rReg(rFlagsReg cr, rax_RegI op1, rRegI op2)
10936 %{
10937 match(Set cr (OverflowMulI op1 op2));
10938 effect(DEF cr, USE_KILL op1, USE op2);
10939
10940 format %{ "imull $op1, $op2\t# overflow check int" %}
10941 ins_encode %{
10942 __ imull($op1$$Register, $op2$$Register);
10943 %}
10944 ins_pipe(ialu_reg_reg_alu0);
10945 %}
10946
10947 instruct overflowMulI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2, rRegI tmp)
10948 %{
10949 match(Set cr (OverflowMulI op1 op2));
10950 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10951
10952 format %{ "imull $tmp, $op1, $op2\t# overflow check int" %}
10953 ins_encode %{
10954 __ imull($tmp$$Register, $op1$$Register, $op2$$constant);
10955 %}
10956 ins_pipe(ialu_reg_reg_alu0);
10957 %}
10958
10959 instruct overflowMulL_rReg(rFlagsReg cr, rax_RegL op1, rRegL op2)
10960 %{
10961 match(Set cr (OverflowMulL op1 op2));
10962 effect(DEF cr, USE_KILL op1, USE op2);
10963
10964 format %{ "imulq $op1, $op2\t# overflow check long" %}
10965 ins_encode %{
10966 __ imulq($op1$$Register, $op2$$Register);
10967 %}
10968 ins_pipe(ialu_reg_reg_alu0);
10969 %}
10970
10971 instruct overflowMulL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2, rRegL tmp)
10972 %{
10973 match(Set cr (OverflowMulL op1 op2));
10974 effect(DEF cr, TEMP tmp, USE op1, USE op2);
10975
10976 format %{ "imulq $tmp, $op1, $op2\t# overflow check long" %}
10977 ins_encode %{
10978 __ imulq($tmp$$Register, $op1$$Register, $op2$$constant);
10979 %}
10980 ins_pipe(ialu_reg_reg_alu0);
10981 %}
10982
10983
10984 //----------Control Flow Instructions------------------------------------------
10985 // Signed compare Instructions
10986
10987 // XXX more variants!!
10988 instruct compI_rReg(rFlagsReg cr, rRegI op1, rRegI op2)
10989 %{
10990 match(Set cr (CmpI op1 op2));
10991 effect(DEF cr, USE op1, USE op2);
10992
10993 format %{ "cmpl $op1, $op2" %}
10994 opcode(0x3B); /* Opcode 3B /r */
10995 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
10996 ins_pipe(ialu_cr_reg_reg);
10997 %}
10998
10999 instruct compI_rReg_imm(rFlagsReg cr, rRegI op1, immI op2)
11000 %{
11001 match(Set cr (CmpI op1 op2));
11002
11003 format %{ "cmpl $op1, $op2" %}
11004 opcode(0x81, 0x07); /* Opcode 81 /7 */
11005 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11006 ins_pipe(ialu_cr_reg_imm);
11007 %}
11008
11009 instruct compI_rReg_mem(rFlagsReg cr, rRegI op1, memory op2)
11010 %{
11011 match(Set cr (CmpI op1 (LoadI op2)));
11012
11013 ins_cost(500); // XXX
11014 format %{ "cmpl $op1, $op2" %}
11015 opcode(0x3B); /* Opcode 3B /r */
11016 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11017 ins_pipe(ialu_cr_reg_mem);
11018 %}
11019
11020 instruct testI_reg(rFlagsReg cr, rRegI src, immI0 zero)
11021 %{
11022 match(Set cr (CmpI src zero));
11023
11024 format %{ "testl $src, $src" %}
11025 opcode(0x85);
11026 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11027 ins_pipe(ialu_cr_reg_imm);
11028 %}
11029
11030 instruct testI_reg_imm(rFlagsReg cr, rRegI src, immI con, immI0 zero)
11031 %{
11032 match(Set cr (CmpI (AndI src con) zero));
11033
11034 format %{ "testl $src, $con" %}
11035 opcode(0xF7, 0x00);
11036 ins_encode(REX_reg(src), OpcP, reg_opc(src), Con32(con));
11037 ins_pipe(ialu_cr_reg_imm);
11038 %}
11039
11040 instruct testI_reg_mem(rFlagsReg cr, rRegI src, memory mem, immI0 zero)
11041 %{
11042 match(Set cr (CmpI (AndI src (LoadI mem)) zero));
11043
11044 format %{ "testl $src, $mem" %}
11045 opcode(0x85);
11046 ins_encode(REX_reg_mem(src, mem), OpcP, reg_mem(src, mem));
11047 ins_pipe(ialu_cr_reg_mem);
11048 %}
11049
11050 // Unsigned compare Instructions; really, same as signed except they
11051 // produce an rFlagsRegU instead of rFlagsReg.
11052 instruct compU_rReg(rFlagsRegU cr, rRegI op1, rRegI op2)
11053 %{
11054 match(Set cr (CmpU op1 op2));
11055
11056 format %{ "cmpl $op1, $op2\t# unsigned" %}
11057 opcode(0x3B); /* Opcode 3B /r */
11058 ins_encode(REX_reg_reg(op1, op2), OpcP, reg_reg(op1, op2));
11059 ins_pipe(ialu_cr_reg_reg);
11060 %}
11061
11062 instruct compU_rReg_imm(rFlagsRegU cr, rRegI op1, immI op2)
11063 %{
11064 match(Set cr (CmpU op1 op2));
11065
11066 format %{ "cmpl $op1, $op2\t# unsigned" %}
11067 opcode(0x81,0x07); /* Opcode 81 /7 */
11068 ins_encode(OpcSErm(op1, op2), Con8or32(op2));
11069 ins_pipe(ialu_cr_reg_imm);
11070 %}
11071
11072 instruct compU_rReg_mem(rFlagsRegU cr, rRegI op1, memory op2)
11073 %{
11074 match(Set cr (CmpU op1 (LoadI op2)));
11075
11076 ins_cost(500); // XXX
11077 format %{ "cmpl $op1, $op2\t# unsigned" %}
11078 opcode(0x3B); /* Opcode 3B /r */
11079 ins_encode(REX_reg_mem(op1, op2), OpcP, reg_mem(op1, op2));
11080 ins_pipe(ialu_cr_reg_mem);
11081 %}
11082
11083 // // // Cisc-spilled version of cmpU_rReg
11084 // //instruct compU_mem_rReg(rFlagsRegU cr, memory op1, rRegI op2)
11085 // //%{
11086 // // match(Set cr (CmpU (LoadI op1) op2));
11087 // //
11088 // // format %{ "CMPu $op1,$op2" %}
11089 // // ins_cost(500);
11090 // // opcode(0x39); /* Opcode 39 /r */
11091 // // ins_encode( OpcP, reg_mem( op1, op2) );
11092 // //%}
11093
11094 instruct testU_reg(rFlagsRegU cr, rRegI src, immI0 zero)
11095 %{
11096 match(Set cr (CmpU src zero));
11097
11098 format %{ "testl $src, $src\t# unsigned" %}
11099 opcode(0x85);
11100 ins_encode(REX_reg_reg(src, src), OpcP, reg_reg(src, src));
11101 ins_pipe(ialu_cr_reg_imm);
11102 %}
11103
11104 instruct compP_rReg(rFlagsRegU cr, rRegP op1, rRegP op2)
11105 %{
11106 match(Set cr (CmpP op1 op2));
11107
11108 format %{ "cmpq $op1, $op2\t# ptr" %}
11109 opcode(0x3B); /* Opcode 3B /r */
11110 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11111 ins_pipe(ialu_cr_reg_reg);
11112 %}
11113
11114 instruct compP_rReg_mem(rFlagsRegU cr, rRegP op1, memory op2)
11115 %{
11116 match(Set cr (CmpP op1 (LoadP op2)));
11117
11118 ins_cost(500); // XXX
11119 format %{ "cmpq $op1, $op2\t# ptr" %}
11120 opcode(0x3B); /* Opcode 3B /r */
11121 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11122 ins_pipe(ialu_cr_reg_mem);
11123 %}
11124
11125 // // // Cisc-spilled version of cmpP_rReg
11126 // //instruct compP_mem_rReg(rFlagsRegU cr, memory op1, rRegP op2)
11127 // //%{
11128 // // match(Set cr (CmpP (LoadP op1) op2));
11129 // //
11130 // // format %{ "CMPu $op1,$op2" %}
11131 // // ins_cost(500);
11132 // // opcode(0x39); /* Opcode 39 /r */
11133 // // ins_encode( OpcP, reg_mem( op1, op2) );
11134 // //%}
11135
11136 // XXX this is generalized by compP_rReg_mem???
11137 // Compare raw pointer (used in out-of-heap check).
11138 // Only works because non-oop pointers must be raw pointers
11139 // and raw pointers have no anti-dependencies.
11140 instruct compP_mem_rReg(rFlagsRegU cr, rRegP op1, memory op2)
11141 %{
11142 predicate(n->in(2)->in(2)->bottom_type()->reloc() == relocInfo::none);
11143 match(Set cr (CmpP op1 (LoadP op2)));
11144
11145 format %{ "cmpq $op1, $op2\t# raw ptr" %}
11146 opcode(0x3B); /* Opcode 3B /r */
11147 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11148 ins_pipe(ialu_cr_reg_mem);
11149 %}
11150
11151 // This will generate a signed flags result. This should be OK since
11152 // any compare to a zero should be eq/neq.
11153 instruct testP_reg(rFlagsReg cr, rRegP src, immP0 zero)
11154 %{
11155 match(Set cr (CmpP src zero));
11156
11157 format %{ "testq $src, $src\t# ptr" %}
11158 opcode(0x85);
11159 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11160 ins_pipe(ialu_cr_reg_imm);
11161 %}
11162
11163 // This will generate a signed flags result. This should be OK since
11164 // any compare to a zero should be eq/neq.
11165 instruct testP_mem(rFlagsReg cr, memory op, immP0 zero)
11166 %{
11167 predicate(!UseCompressedOops || (Universe::narrow_oop_base() != NULL));
11168 match(Set cr (CmpP (LoadP op) zero));
11169
11170 ins_cost(500); // XXX
11171 format %{ "testq $op, 0xffffffffffffffff\t# ptr" %}
11172 opcode(0xF7); /* Opcode F7 /0 */
11173 ins_encode(REX_mem_wide(op),
11174 OpcP, RM_opc_mem(0x00, op), Con_d32(0xFFFFFFFF));
11175 ins_pipe(ialu_cr_reg_imm);
11176 %}
11177
11178 instruct testP_mem_reg0(rFlagsReg cr, memory mem, immP0 zero)
11179 %{
11180 predicate(UseCompressedOops && (Universe::narrow_oop_base() == NULL) && (Universe::narrow_klass_base() == NULL));
11181 match(Set cr (CmpP (LoadP mem) zero));
11182
11183 format %{ "cmpq R12, $mem\t# ptr (R12_heapbase==0)" %}
11184 ins_encode %{
11185 __ cmpq(r12, $mem$$Address);
11186 %}
11187 ins_pipe(ialu_cr_reg_mem);
11188 %}
11189
11190 instruct compN_rReg(rFlagsRegU cr, rRegN op1, rRegN op2)
11191 %{
11192 match(Set cr (CmpN op1 op2));
11193
11194 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11195 ins_encode %{ __ cmpl($op1$$Register, $op2$$Register); %}
11196 ins_pipe(ialu_cr_reg_reg);
11197 %}
11198
11199 instruct compN_rReg_mem(rFlagsRegU cr, rRegN src, memory mem)
11200 %{
11201 match(Set cr (CmpN src (LoadN mem)));
11202
11203 format %{ "cmpl $src, $mem\t# compressed ptr" %}
11204 ins_encode %{
11205 __ cmpl($src$$Register, $mem$$Address);
11206 %}
11207 ins_pipe(ialu_cr_reg_mem);
11208 %}
11209
11210 instruct compN_rReg_imm(rFlagsRegU cr, rRegN op1, immN op2) %{
11211 match(Set cr (CmpN op1 op2));
11212
11213 format %{ "cmpl $op1, $op2\t# compressed ptr" %}
11214 ins_encode %{
11215 __ cmp_narrow_oop($op1$$Register, (jobject)$op2$$constant);
11216 %}
11217 ins_pipe(ialu_cr_reg_imm);
11218 %}
11219
11220 instruct compN_mem_imm(rFlagsRegU cr, memory mem, immN src)
11221 %{
11222 match(Set cr (CmpN src (LoadN mem)));
11223
11224 format %{ "cmpl $mem, $src\t# compressed ptr" %}
11225 ins_encode %{
11226 __ cmp_narrow_oop($mem$$Address, (jobject)$src$$constant);
11227 %}
11228 ins_pipe(ialu_cr_reg_mem);
11229 %}
11230
11231 instruct compN_rReg_imm_klass(rFlagsRegU cr, rRegN op1, immNKlass op2) %{
11232 match(Set cr (CmpN op1 op2));
11233
11234 format %{ "cmpl $op1, $op2\t# compressed klass ptr" %}
11235 ins_encode %{
11236 __ cmp_narrow_klass($op1$$Register, (Klass*)$op2$$constant);
11237 %}
11238 ins_pipe(ialu_cr_reg_imm);
11239 %}
11240
11241 instruct compN_mem_imm_klass(rFlagsRegU cr, memory mem, immNKlass src)
11242 %{
11243 match(Set cr (CmpN src (LoadNKlass mem)));
11244
11245 format %{ "cmpl $mem, $src\t# compressed klass ptr" %}
11246 ins_encode %{
11247 __ cmp_narrow_klass($mem$$Address, (Klass*)$src$$constant);
11248 %}
11249 ins_pipe(ialu_cr_reg_mem);
11250 %}
11251
11252 instruct testN_reg(rFlagsReg cr, rRegN src, immN0 zero) %{
11253 match(Set cr (CmpN src zero));
11254
11255 format %{ "testl $src, $src\t# compressed ptr" %}
11256 ins_encode %{ __ testl($src$$Register, $src$$Register); %}
11257 ins_pipe(ialu_cr_reg_imm);
11258 %}
11259
11260 instruct testN_mem(rFlagsReg cr, memory mem, immN0 zero)
11261 %{
11262 predicate(Universe::narrow_oop_base() != NULL);
11263 match(Set cr (CmpN (LoadN mem) zero));
11264
11265 ins_cost(500); // XXX
11266 format %{ "testl $mem, 0xffffffff\t# compressed ptr" %}
11267 ins_encode %{
11268 __ cmpl($mem$$Address, (int)0xFFFFFFFF);
11269 %}
11270 ins_pipe(ialu_cr_reg_mem);
11271 %}
11272
11273 instruct testN_mem_reg0(rFlagsReg cr, memory mem, immN0 zero)
11274 %{
11275 predicate(Universe::narrow_oop_base() == NULL && (Universe::narrow_klass_base() == NULL));
11276 match(Set cr (CmpN (LoadN mem) zero));
11277
11278 format %{ "cmpl R12, $mem\t# compressed ptr (R12_heapbase==0)" %}
11279 ins_encode %{
11280 __ cmpl(r12, $mem$$Address);
11281 %}
11282 ins_pipe(ialu_cr_reg_mem);
11283 %}
11284
11285 // Yanked all unsigned pointer compare operations.
11286 // Pointer compares are done with CmpP which is already unsigned.
11287
11288 instruct compL_rReg(rFlagsReg cr, rRegL op1, rRegL op2)
11289 %{
11290 match(Set cr (CmpL op1 op2));
11291
11292 format %{ "cmpq $op1, $op2" %}
11293 opcode(0x3B); /* Opcode 3B /r */
11294 ins_encode(REX_reg_reg_wide(op1, op2), OpcP, reg_reg(op1, op2));
11295 ins_pipe(ialu_cr_reg_reg);
11296 %}
11297
11298 instruct compL_rReg_imm(rFlagsReg cr, rRegL op1, immL32 op2)
11299 %{
11300 match(Set cr (CmpL op1 op2));
11301
11302 format %{ "cmpq $op1, $op2" %}
11303 opcode(0x81, 0x07); /* Opcode 81 /7 */
11304 ins_encode(OpcSErm_wide(op1, op2), Con8or32(op2));
11305 ins_pipe(ialu_cr_reg_imm);
11306 %}
11307
11308 instruct compL_rReg_mem(rFlagsReg cr, rRegL op1, memory op2)
11309 %{
11310 match(Set cr (CmpL op1 (LoadL op2)));
11311
11312 format %{ "cmpq $op1, $op2" %}
11313 opcode(0x3B); /* Opcode 3B /r */
11314 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11315 ins_pipe(ialu_cr_reg_mem);
11316 %}
11317
11318 instruct testL_reg(rFlagsReg cr, rRegL src, immL0 zero)
11319 %{
11320 match(Set cr (CmpL src zero));
11321
11322 format %{ "testq $src, $src" %}
11323 opcode(0x85);
11324 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11325 ins_pipe(ialu_cr_reg_imm);
11326 %}
11327
11328 instruct testL_reg_imm(rFlagsReg cr, rRegL src, immL32 con, immL0 zero)
11329 %{
11330 match(Set cr (CmpL (AndL src con) zero));
11331
11332 format %{ "testq $src, $con\t# long" %}
11333 opcode(0xF7, 0x00);
11334 ins_encode(REX_reg_wide(src), OpcP, reg_opc(src), Con32(con));
11335 ins_pipe(ialu_cr_reg_imm);
11336 %}
11337
11338 instruct testL_reg_mem(rFlagsReg cr, rRegL src, memory mem, immL0 zero)
11339 %{
11340 match(Set cr (CmpL (AndL src (LoadL mem)) zero));
11341
11342 format %{ "testq $src, $mem" %}
11343 opcode(0x85);
11344 ins_encode(REX_reg_mem_wide(src, mem), OpcP, reg_mem(src, mem));
11345 ins_pipe(ialu_cr_reg_mem);
11346 %}
11347
11348 // Manifest a CmpL result in an integer register. Very painful.
11349 // This is the test to avoid.
11350 instruct cmpL3_reg_reg(rRegI dst, rRegL src1, rRegL src2, rFlagsReg flags)
11351 %{
11352 match(Set dst (CmpL3 src1 src2));
11353 effect(KILL flags);
11354
11355 ins_cost(275); // XXX
11356 format %{ "cmpq $src1, $src2\t# CmpL3\n\t"
11357 "movl $dst, -1\n\t"
11358 "jl,s done\n\t"
11359 "setne $dst\n\t"
11360 "movzbl $dst, $dst\n\t"
11361 "done:" %}
11362 ins_encode(cmpl3_flag(src1, src2, dst));
11363 ins_pipe(pipe_slow);
11364 %}
11365
11366 //----------Max and Min--------------------------------------------------------
11367 // Min Instructions
11368
11369 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11370 %{
11371 effect(USE_DEF dst, USE src, USE cr);
11372
11373 format %{ "cmovlgt $dst, $src\t# min" %}
11374 opcode(0x0F, 0x4F);
11375 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11376 ins_pipe(pipe_cmov_reg);
11377 %}
11378
11379
11380 instruct minI_rReg(rRegI dst, rRegI src)
11381 %{
11382 match(Set dst (MinI dst src));
11383
11384 ins_cost(200);
11385 expand %{
11386 rFlagsReg cr;
11387 compI_rReg(cr, dst, src);
11388 cmovI_reg_g(dst, src, cr);
11389 %}
11390 %}
11391
11392 instruct cmovI_reg_l(rRegI dst, rRegI src, rFlagsReg cr)
11393 %{
11394 effect(USE_DEF dst, USE src, USE cr);
11395
11396 format %{ "cmovllt $dst, $src\t# max" %}
11397 opcode(0x0F, 0x4C);
11398 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11399 ins_pipe(pipe_cmov_reg);
11400 %}
11401
11402
11403 instruct maxI_rReg(rRegI dst, rRegI src)
11404 %{
11405 match(Set dst (MaxI dst src));
11406
11407 ins_cost(200);
11408 expand %{
11409 rFlagsReg cr;
11410 compI_rReg(cr, dst, src);
11411 cmovI_reg_l(dst, src, cr);
11412 %}
11413 %}
11414
11415 // ============================================================================
11416 // Branch Instructions
11417
11418 // Jump Direct - Label defines a relative address from JMP+1
11419 instruct jmpDir(label labl)
11420 %{
11421 match(Goto);
11422 effect(USE labl);
11423
11424 ins_cost(300);
11425 format %{ "jmp $labl" %}
11426 size(5);
11427 ins_encode %{
11428 Label* L = $labl$$label;
11429 __ jmp(*L, false); // Always long jump
11430 %}
11431 ins_pipe(pipe_jmp);
11432 %}
11433
11434 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11435 instruct jmpCon(cmpOp cop, rFlagsReg cr, label labl)
11436 %{
11437 match(If cop cr);
11438 effect(USE labl);
11439
11440 ins_cost(300);
11441 format %{ "j$cop $labl" %}
11442 size(6);
11443 ins_encode %{
11444 Label* L = $labl$$label;
11445 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11446 %}
11447 ins_pipe(pipe_jcc);
11448 %}
11449
11450 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11451 instruct jmpLoopEnd(cmpOp cop, rFlagsReg cr, label labl)
11452 %{
11453 match(CountedLoopEnd cop cr);
11454 effect(USE labl);
11455
11456 ins_cost(300);
11457 format %{ "j$cop $labl\t# loop end" %}
11458 size(6);
11459 ins_encode %{
11460 Label* L = $labl$$label;
11461 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11462 %}
11463 ins_pipe(pipe_jcc);
11464 %}
11465
11466 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11467 instruct jmpLoopEndU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11468 match(CountedLoopEnd cop cmp);
11469 effect(USE labl);
11470
11471 ins_cost(300);
11472 format %{ "j$cop,u $labl\t# loop end" %}
11473 size(6);
11474 ins_encode %{
11475 Label* L = $labl$$label;
11476 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11477 %}
11478 ins_pipe(pipe_jcc);
11479 %}
11480
11481 instruct jmpLoopEndUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11482 match(CountedLoopEnd cop cmp);
11483 effect(USE labl);
11484
11485 ins_cost(200);
11486 format %{ "j$cop,u $labl\t# loop end" %}
11487 size(6);
11488 ins_encode %{
11489 Label* L = $labl$$label;
11490 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11491 %}
11492 ins_pipe(pipe_jcc);
11493 %}
11494
11495 // Jump Direct Conditional - using unsigned comparison
11496 instruct jmpConU(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11497 match(If cop cmp);
11498 effect(USE labl);
11499
11500 ins_cost(300);
11501 format %{ "j$cop,u $labl" %}
11502 size(6);
11503 ins_encode %{
11504 Label* L = $labl$$label;
11505 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11506 %}
11507 ins_pipe(pipe_jcc);
11508 %}
11509
11510 instruct jmpConUCF(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11511 match(If cop cmp);
11512 effect(USE labl);
11513
11514 ins_cost(200);
11515 format %{ "j$cop,u $labl" %}
11516 size(6);
11517 ins_encode %{
11518 Label* L = $labl$$label;
11519 __ jcc((Assembler::Condition)($cop$$cmpcode), *L, false); // Always long jump
11520 %}
11521 ins_pipe(pipe_jcc);
11522 %}
11523
11524 instruct jmpConUCF2(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11525 match(If cop cmp);
11526 effect(USE labl);
11527
11528 ins_cost(200);
11529 format %{ $$template
11530 if ($cop$$cmpcode == Assembler::notEqual) {
11531 $$emit$$"jp,u $labl\n\t"
11532 $$emit$$"j$cop,u $labl"
11533 } else {
11534 $$emit$$"jp,u done\n\t"
11535 $$emit$$"j$cop,u $labl\n\t"
11536 $$emit$$"done:"
11537 }
11538 %}
11539 ins_encode %{
11540 Label* l = $labl$$label;
11541 if ($cop$$cmpcode == Assembler::notEqual) {
11542 __ jcc(Assembler::parity, *l, false);
11543 __ jcc(Assembler::notEqual, *l, false);
11544 } else if ($cop$$cmpcode == Assembler::equal) {
11545 Label done;
11546 __ jccb(Assembler::parity, done);
11547 __ jcc(Assembler::equal, *l, false);
11548 __ bind(done);
11549 } else {
11550 ShouldNotReachHere();
11551 }
11552 %}
11553 ins_pipe(pipe_jcc);
11554 %}
11555
11556 // ============================================================================
11557 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary
11558 // superklass array for an instance of the superklass. Set a hidden
11559 // internal cache on a hit (cache is checked with exposed code in
11560 // gen_subtype_check()). Return NZ for a miss or zero for a hit. The
11561 // encoding ALSO sets flags.
11562
11563 instruct partialSubtypeCheck(rdi_RegP result,
11564 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11565 rFlagsReg cr)
11566 %{
11567 match(Set result (PartialSubtypeCheck sub super));
11568 effect(KILL rcx, KILL cr);
11569
11570 ins_cost(1100); // slightly larger than the next version
11571 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11572 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11573 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11574 "repne scasq\t# Scan *rdi++ for a match with rax while rcx--\n\t"
11575 "jne,s miss\t\t# Missed: rdi not-zero\n\t"
11576 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11577 "xorq $result, $result\t\t Hit: rdi zero\n\t"
11578 "miss:\t" %}
11579
11580 opcode(0x1); // Force a XOR of RDI
11581 ins_encode(enc_PartialSubtypeCheck());
11582 ins_pipe(pipe_slow);
11583 %}
11584
11585 instruct partialSubtypeCheck_vs_Zero(rFlagsReg cr,
11586 rsi_RegP sub, rax_RegP super, rcx_RegI rcx,
11587 immP0 zero,
11588 rdi_RegP result)
11589 %{
11590 match(Set cr (CmpP (PartialSubtypeCheck sub super) zero));
11591 effect(KILL rcx, KILL result);
11592
11593 ins_cost(1000);
11594 format %{ "movq rdi, [$sub + in_bytes(Klass::secondary_supers_offset())]\n\t"
11595 "movl rcx, [rdi + Array<Klass*>::length_offset_in_bytes()]\t# length to scan\n\t"
11596 "addq rdi, Array<Klass*>::base_offset_in_bytes()\t# Skip to start of data; set NZ in case count is zero\n\t"
11597 "repne scasq\t# Scan *rdi++ for a match with rax while cx-- != 0\n\t"
11598 "jne,s miss\t\t# Missed: flags nz\n\t"
11599 "movq [$sub + in_bytes(Klass::secondary_super_cache_offset())], $super\t# Hit: update cache\n\t"
11600 "miss:\t" %}
11601
11602 opcode(0x0); // No need to XOR RDI
11603 ins_encode(enc_PartialSubtypeCheck());
11604 ins_pipe(pipe_slow);
11605 %}
11606
11607 // ============================================================================
11608 // Branch Instructions -- short offset versions
11609 //
11610 // These instructions are used to replace jumps of a long offset (the default
11611 // match) with jumps of a shorter offset. These instructions are all tagged
11612 // with the ins_short_branch attribute, which causes the ADLC to suppress the
11613 // match rules in general matching. Instead, the ADLC generates a conversion
11614 // method in the MachNode which can be used to do in-place replacement of the
11615 // long variant with the shorter variant. The compiler will determine if a
11616 // branch can be taken by the is_short_branch_offset() predicate in the machine
11617 // specific code section of the file.
11618
11619 // Jump Direct - Label defines a relative address from JMP+1
11620 instruct jmpDir_short(label labl) %{
11621 match(Goto);
11622 effect(USE labl);
11623
11624 ins_cost(300);
11625 format %{ "jmp,s $labl" %}
11626 size(2);
11627 ins_encode %{
11628 Label* L = $labl$$label;
11629 __ jmpb(*L);
11630 %}
11631 ins_pipe(pipe_jmp);
11632 ins_short_branch(1);
11633 %}
11634
11635 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11636 instruct jmpCon_short(cmpOp cop, rFlagsReg cr, label labl) %{
11637 match(If cop cr);
11638 effect(USE labl);
11639
11640 ins_cost(300);
11641 format %{ "j$cop,s $labl" %}
11642 size(2);
11643 ins_encode %{
11644 Label* L = $labl$$label;
11645 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11646 %}
11647 ins_pipe(pipe_jcc);
11648 ins_short_branch(1);
11649 %}
11650
11651 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11652 instruct jmpLoopEnd_short(cmpOp cop, rFlagsReg cr, label labl) %{
11653 match(CountedLoopEnd cop cr);
11654 effect(USE labl);
11655
11656 ins_cost(300);
11657 format %{ "j$cop,s $labl\t# loop end" %}
11658 size(2);
11659 ins_encode %{
11660 Label* L = $labl$$label;
11661 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11662 %}
11663 ins_pipe(pipe_jcc);
11664 ins_short_branch(1);
11665 %}
11666
11667 // Jump Direct Conditional - Label defines a relative address from Jcc+1
11668 instruct jmpLoopEndU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11669 match(CountedLoopEnd cop cmp);
11670 effect(USE labl);
11671
11672 ins_cost(300);
11673 format %{ "j$cop,us $labl\t# loop end" %}
11674 size(2);
11675 ins_encode %{
11676 Label* L = $labl$$label;
11677 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11678 %}
11679 ins_pipe(pipe_jcc);
11680 ins_short_branch(1);
11681 %}
11682
11683 instruct jmpLoopEndUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11684 match(CountedLoopEnd cop cmp);
11685 effect(USE labl);
11686
11687 ins_cost(300);
11688 format %{ "j$cop,us $labl\t# loop end" %}
11689 size(2);
11690 ins_encode %{
11691 Label* L = $labl$$label;
11692 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11693 %}
11694 ins_pipe(pipe_jcc);
11695 ins_short_branch(1);
11696 %}
11697
11698 // Jump Direct Conditional - using unsigned comparison
11699 instruct jmpConU_short(cmpOpU cop, rFlagsRegU cmp, label labl) %{
11700 match(If cop cmp);
11701 effect(USE labl);
11702
11703 ins_cost(300);
11704 format %{ "j$cop,us $labl" %}
11705 size(2);
11706 ins_encode %{
11707 Label* L = $labl$$label;
11708 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11709 %}
11710 ins_pipe(pipe_jcc);
11711 ins_short_branch(1);
11712 %}
11713
11714 instruct jmpConUCF_short(cmpOpUCF cop, rFlagsRegUCF cmp, label labl) %{
11715 match(If cop cmp);
11716 effect(USE labl);
11717
11718 ins_cost(300);
11719 format %{ "j$cop,us $labl" %}
11720 size(2);
11721 ins_encode %{
11722 Label* L = $labl$$label;
11723 __ jccb((Assembler::Condition)($cop$$cmpcode), *L);
11724 %}
11725 ins_pipe(pipe_jcc);
11726 ins_short_branch(1);
11727 %}
11728
11729 instruct jmpConUCF2_short(cmpOpUCF2 cop, rFlagsRegUCF cmp, label labl) %{
11730 match(If cop cmp);
11731 effect(USE labl);
11732
11733 ins_cost(300);
11734 format %{ $$template
11735 if ($cop$$cmpcode == Assembler::notEqual) {
11736 $$emit$$"jp,u,s $labl\n\t"
11737 $$emit$$"j$cop,u,s $labl"
11738 } else {
11739 $$emit$$"jp,u,s done\n\t"
11740 $$emit$$"j$cop,u,s $labl\n\t"
11741 $$emit$$"done:"
11742 }
11743 %}
11744 size(4);
11745 ins_encode %{
11746 Label* l = $labl$$label;
11747 if ($cop$$cmpcode == Assembler::notEqual) {
11748 __ jccb(Assembler::parity, *l);
11749 __ jccb(Assembler::notEqual, *l);
11750 } else if ($cop$$cmpcode == Assembler::equal) {
11751 Label done;
11752 __ jccb(Assembler::parity, done);
11753 __ jccb(Assembler::equal, *l);
11754 __ bind(done);
11755 } else {
11756 ShouldNotReachHere();
11757 }
11758 %}
11759 ins_pipe(pipe_jcc);
11760 ins_short_branch(1);
11761 %}
11762
11763 // ============================================================================
11764 // inlined locking and unlocking
11765
11766 instruct cmpFastLockRTM(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rdx_RegI scr, rRegI cx1, rRegI cx2) %{
11767 predicate(Compile::current()->use_rtm());
11768 match(Set cr (FastLock object box));
11769 effect(TEMP tmp, TEMP scr, TEMP cx1, TEMP cx2, USE_KILL box);
11770 ins_cost(300);
11771 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr,$cx1,$cx2" %}
11772 ins_encode %{
11773 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11774 $scr$$Register, $cx1$$Register, $cx2$$Register,
11775 _counters, _rtm_counters, _stack_rtm_counters,
11776 ((Method*)(ra_->C->method()->constant_encoding()))->method_data(),
11777 true, ra_->C->profile_rtm());
11778 %}
11779 ins_pipe(pipe_slow);
11780 %}
11781
11782 instruct cmpFastLock(rFlagsReg cr, rRegP object, rbx_RegP box, rax_RegI tmp, rRegP scr) %{
11783 predicate(!Compile::current()->use_rtm());
11784 match(Set cr (FastLock object box));
11785 effect(TEMP tmp, TEMP scr, USE_KILL box);
11786 ins_cost(300);
11787 format %{ "fastlock $object,$box\t! kills $box,$tmp,$scr" %}
11788 ins_encode %{
11789 __ fast_lock($object$$Register, $box$$Register, $tmp$$Register,
11790 $scr$$Register, noreg, noreg, _counters, NULL, NULL, NULL, false, false);
11791 %}
11792 ins_pipe(pipe_slow);
11793 %}
11794
11795 instruct cmpFastUnlock(rFlagsReg cr, rRegP object, rax_RegP box, rRegP tmp) %{
11796 match(Set cr (FastUnlock object box));
11797 effect(TEMP tmp, USE_KILL box);
11798 ins_cost(300);
11799 format %{ "fastunlock $object,$box\t! kills $box,$tmp" %}
11800 ins_encode %{
11801 __ fast_unlock($object$$Register, $box$$Register, $tmp$$Register, ra_->C->use_rtm());
11802 %}
11803 ins_pipe(pipe_slow);
11804 %}
11805
11806
11807 // ============================================================================
11808 // Safepoint Instructions
11809 instruct safePoint_poll(rFlagsReg cr)
11810 %{
11811 predicate(!Assembler::is_polling_page_far());
11812 match(SafePoint);
11813 effect(KILL cr);
11814
11815 format %{ "testl rax, [rip + #offset_to_poll_page]\t"
11816 "# Safepoint: poll for GC" %}
11817 ins_cost(125);
11818 ins_encode %{
11819 AddressLiteral addr(os::get_polling_page(), relocInfo::poll_type);
11820 __ testl(rax, addr);
11821 %}
11822 ins_pipe(ialu_reg_mem);
11823 %}
11824
11825 instruct safePoint_poll_far(rFlagsReg cr, rRegP poll)
11826 %{
11827 predicate(Assembler::is_polling_page_far());
11828 match(SafePoint poll);
11829 effect(KILL cr, USE poll);
11830
11831 format %{ "testl rax, [$poll]\t"
11832 "# Safepoint: poll for GC" %}
11833 ins_cost(125);
11834 ins_encode %{
11835 __ relocate(relocInfo::poll_type);
11836 __ testl(rax, Address($poll$$Register, 0));
11837 %}
11838 ins_pipe(ialu_reg_mem);
11839 %}
11840
11841 // ============================================================================
11842 // Procedure Call/Return Instructions
11843 // Call Java Static Instruction
11844 // Note: If this code changes, the corresponding ret_addr_offset() and
11845 // compute_padding() functions will have to be adjusted.
11846 instruct CallStaticJavaDirect(method meth) %{
11847 match(CallStaticJava);
11848 effect(USE meth);
11849
11850 ins_cost(300);
11851 format %{ "call,static " %}
11852 opcode(0xE8); /* E8 cd */
11853 ins_encode(clear_avx, Java_Static_Call(meth), call_epilog);
11854 ins_pipe(pipe_slow);
11855 ins_alignment(4);
11856 %}
11857
11858 // Call Java Dynamic Instruction
11859 // Note: If this code changes, the corresponding ret_addr_offset() and
11860 // compute_padding() functions will have to be adjusted.
11861 instruct CallDynamicJavaDirect(method meth)
11862 %{
11863 match(CallDynamicJava);
11864 effect(USE meth);
11865
11866 ins_cost(300);
11867 format %{ "movq rax, #Universe::non_oop_word()\n\t"
11868 "call,dynamic " %}
11869 ins_encode(clear_avx, Java_Dynamic_Call(meth), call_epilog);
11870 ins_pipe(pipe_slow);
11871 ins_alignment(4);
11872 %}
11873
11874 // Call Runtime Instruction
11875 instruct CallRuntimeDirect(method meth)
11876 %{
11877 match(CallRuntime);
11878 effect(USE meth);
11879
11880 ins_cost(300);
11881 format %{ "call,runtime " %}
11882 ins_encode(clear_avx, Java_To_Runtime(meth));
11883 ins_pipe(pipe_slow);
11884 %}
11885
11886 // Call runtime without safepoint
11887 instruct CallLeafDirect(method meth)
11888 %{
11889 match(CallLeaf);
11890 effect(USE meth);
11891
11892 ins_cost(300);
11893 format %{ "call_leaf,runtime " %}
11894 ins_encode(clear_avx, Java_To_Runtime(meth));
11895 ins_pipe(pipe_slow);
11896 %}
11897
11898 // Call runtime without safepoint
11899 instruct CallLeafNoFPDirect(method meth)
11900 %{
11901 match(CallLeafNoFP);
11902 effect(USE meth);
11903
11904 ins_cost(300);
11905 format %{ "call_leaf_nofp,runtime " %}
11906 ins_encode(Java_To_Runtime(meth));
11907 ins_pipe(pipe_slow);
11908 %}
11909
11910 // Return Instruction
11911 // Remove the return address & jump to it.
11912 // Notice: We always emit a nop after a ret to make sure there is room
11913 // for safepoint patching
11914 instruct Ret()
11915 %{
11916 match(Return);
11917
11918 format %{ "ret" %}
11919 opcode(0xC3);
11920 ins_encode(OpcP);
11921 ins_pipe(pipe_jmp);
11922 %}
11923
11924 // Tail Call; Jump from runtime stub to Java code.
11925 // Also known as an 'interprocedural jump'.
11926 // Target of jump will eventually return to caller.
11927 // TailJump below removes the return address.
11928 instruct TailCalljmpInd(no_rbp_RegP jump_target, rbx_RegP method_oop)
11929 %{
11930 match(TailCall jump_target method_oop);
11931
11932 ins_cost(300);
11933 format %{ "jmp $jump_target\t# rbx holds method oop" %}
11934 opcode(0xFF, 0x4); /* Opcode FF /4 */
11935 ins_encode(REX_reg(jump_target), OpcP, reg_opc(jump_target));
11936 ins_pipe(pipe_jmp);
11937 %}
11938
11939 // Tail Jump; remove the return address; jump to target.
11940 // TailCall above leaves the return address around.
11941 instruct tailjmpInd(no_rbp_RegP jump_target, rax_RegP ex_oop)
11942 %{
11943 match(TailJump jump_target ex_oop);
11944
11945 ins_cost(300);
11946 format %{ "popq rdx\t# pop return address\n\t"
11947 "jmp $jump_target" %}
11948 opcode(0xFF, 0x4); /* Opcode FF /4 */
11949 ins_encode(Opcode(0x5a), // popq rdx
11950 REX_reg(jump_target), OpcP, reg_opc(jump_target));
11951 ins_pipe(pipe_jmp);
11952 %}
11953
11954 // Create exception oop: created by stack-crawling runtime code.
11955 // Created exception is now available to this handler, and is setup
11956 // just prior to jumping to this handler. No code emitted.
11957 instruct CreateException(rax_RegP ex_oop)
11958 %{
11959 match(Set ex_oop (CreateEx));
11960
11961 size(0);
11962 // use the following format syntax
11963 format %{ "# exception oop is in rax; no code emitted" %}
11964 ins_encode();
11965 ins_pipe(empty);
11966 %}
11967
11968 // Rethrow exception:
11969 // The exception oop will come in the first argument position.
11970 // Then JUMP (not call) to the rethrow stub code.
11971 instruct RethrowException()
11972 %{
11973 match(Rethrow);
11974
11975 // use the following format syntax
11976 format %{ "jmp rethrow_stub" %}
11977 ins_encode(enc_rethrow);
11978 ins_pipe(pipe_jmp);
11979 %}
11980
11981
11982 // ============================================================================
11983 // This name is KNOWN by the ADLC and cannot be changed.
11984 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
11985 // for this guy.
11986 instruct tlsLoadP(r15_RegP dst) %{
11987 match(Set dst (ThreadLocal));
11988 effect(DEF dst);
11989
11990 size(0);
11991 format %{ "# TLS is in R15" %}
11992 ins_encode( /*empty encoding*/ );
11993 ins_pipe(ialu_reg_reg);
11994 %}
11995
11996
11997 //----------PEEPHOLE RULES-----------------------------------------------------
11998 // These must follow all instruction definitions as they use the names
11999 // defined in the instructions definitions.
12000 //
12001 // peepmatch ( root_instr_name [preceding_instruction]* );
12002 //
12003 // peepconstraint %{
12004 // (instruction_number.operand_name relational_op instruction_number.operand_name
12005 // [, ...] );
12006 // // instruction numbers are zero-based using left to right order in peepmatch
12007 //
12008 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
12009 // // provide an instruction_number.operand_name for each operand that appears
12010 // // in the replacement instruction's match rule
12011 //
12012 // ---------VM FLAGS---------------------------------------------------------
12013 //
12014 // All peephole optimizations can be turned off using -XX:-OptoPeephole
12015 //
12016 // Each peephole rule is given an identifying number starting with zero and
12017 // increasing by one in the order seen by the parser. An individual peephole
12018 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
12019 // on the command-line.
12020 //
12021 // ---------CURRENT LIMITATIONS----------------------------------------------
12022 //
12023 // Only match adjacent instructions in same basic block
12024 // Only equality constraints
12025 // Only constraints between operands, not (0.dest_reg == RAX_enc)
12026 // Only one replacement instruction
12027 //
12028 // ---------EXAMPLE----------------------------------------------------------
12029 //
12030 // // pertinent parts of existing instructions in architecture description
12031 // instruct movI(rRegI dst, rRegI src)
12032 // %{
12033 // match(Set dst (CopyI src));
12034 // %}
12035 //
12036 // instruct incI_rReg(rRegI dst, immI1 src, rFlagsReg cr)
12037 // %{
12038 // match(Set dst (AddI dst src));
12039 // effect(KILL cr);
12040 // %}
12041 //
12042 // // Change (inc mov) to lea
12043 // peephole %{
12044 // // increment preceeded by register-register move
12045 // peepmatch ( incI_rReg movI );
12046 // // require that the destination register of the increment
12047 // // match the destination register of the move
12048 // peepconstraint ( 0.dst == 1.dst );
12049 // // construct a replacement instruction that sets
12050 // // the destination to ( move's source register + one )
12051 // peepreplace ( leaI_rReg_immI( 0.dst 1.src 0.src ) );
12052 // %}
12053 //
12054
12055 // Implementation no longer uses movX instructions since
12056 // machine-independent system no longer uses CopyX nodes.
12057 //
12058 // peephole
12059 // %{
12060 // peepmatch (incI_rReg movI);
12061 // peepconstraint (0.dst == 1.dst);
12062 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12063 // %}
12064
12065 // peephole
12066 // %{
12067 // peepmatch (decI_rReg movI);
12068 // peepconstraint (0.dst == 1.dst);
12069 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12070 // %}
12071
12072 // peephole
12073 // %{
12074 // peepmatch (addI_rReg_imm movI);
12075 // peepconstraint (0.dst == 1.dst);
12076 // peepreplace (leaI_rReg_immI(0.dst 1.src 0.src));
12077 // %}
12078
12079 // peephole
12080 // %{
12081 // peepmatch (incL_rReg movL);
12082 // peepconstraint (0.dst == 1.dst);
12083 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12084 // %}
12085
12086 // peephole
12087 // %{
12088 // peepmatch (decL_rReg movL);
12089 // peepconstraint (0.dst == 1.dst);
12090 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12091 // %}
12092
12093 // peephole
12094 // %{
12095 // peepmatch (addL_rReg_imm movL);
12096 // peepconstraint (0.dst == 1.dst);
12097 // peepreplace (leaL_rReg_immL(0.dst 1.src 0.src));
12098 // %}
12099
12100 // peephole
12101 // %{
12102 // peepmatch (addP_rReg_imm movP);
12103 // peepconstraint (0.dst == 1.dst);
12104 // peepreplace (leaP_rReg_imm(0.dst 1.src 0.src));
12105 // %}
12106
12107 // // Change load of spilled value to only a spill
12108 // instruct storeI(memory mem, rRegI src)
12109 // %{
12110 // match(Set mem (StoreI mem src));
12111 // %}
12112 //
12113 // instruct loadI(rRegI dst, memory mem)
12114 // %{
12115 // match(Set dst (LoadI mem));
12116 // %}
12117 //
12118
12119 peephole
12120 %{
12121 peepmatch (loadI storeI);
12122 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12123 peepreplace (storeI(1.mem 1.mem 1.src));
12124 %}
12125
12126 peephole
12127 %{
12128 peepmatch (loadL storeL);
12129 peepconstraint (1.src == 0.dst, 1.mem == 0.mem);
12130 peepreplace (storeL(1.mem 1.mem 1.src));
12131 %}
12132
12133 //----------SMARTSPILL RULES---------------------------------------------------
12134 // These must follow all instruction definitions as they use the names
12135 // defined in the instructions definitions.