2120 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2121 29 - 16 + 1 + 2);
2122 return b;
2123 }
2124
2125 const bool Matcher::isSimpleConstant64(jlong value) {
2126 // Probably always true, even if a temp register is required.
2127 return true;
2128 }
2129 /* TODO: PPC port
2130 // Make a new machine dependent decode node (with its operands).
2131 MachTypeNode *Matcher::make_decode_node() {
2132 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2133 "This method is only implemented for unscaled cOops mode so far");
2134 MachTypeNode *decode = new decodeN_unscaledNode();
2135 decode->set_opnd_array(0, new iRegPdstOper());
2136 decode->set_opnd_array(1, new iRegNsrcOper());
2137 return decode;
2138 }
2139 */
2140 // Threshold size for cleararray.
2141 const int Matcher::init_array_short_size = 8 * BytesPerLong;
2142
2143 // false => size gets scaled to BytesPerLong, ok.
2144 const bool Matcher::init_array_count_is_in_bytes = false;
2145
2146 // Use conditional move (CMOVL) on Power7.
2147 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2148
2149 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2150 // fsel doesn't accept a condition register as input, so this would be slightly different.
2151 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2152
2153 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2154 const bool Matcher::require_postalloc_expand = true;
2155
2156 // Should the Matcher clone shifts on addressing modes, expecting them to
2157 // be subsumed into complex addressing expressions or compute them into
2158 // registers? True for Intel but false for most RISCs.
2159 const bool Matcher::clone_shift_expressions = false;
2160
2161 // Do we need to mask the count passed to shift instructions or does
|
2120 b = Assembler::is_simm((offset<0 ? offset-safety_zone : offset+safety_zone),
2121 29 - 16 + 1 + 2);
2122 return b;
2123 }
2124
2125 const bool Matcher::isSimpleConstant64(jlong value) {
2126 // Probably always true, even if a temp register is required.
2127 return true;
2128 }
2129 /* TODO: PPC port
2130 // Make a new machine dependent decode node (with its operands).
2131 MachTypeNode *Matcher::make_decode_node() {
2132 assert(Universe::narrow_oop_base() == NULL && Universe::narrow_oop_shift() == 0,
2133 "This method is only implemented for unscaled cOops mode so far");
2134 MachTypeNode *decode = new decodeN_unscaledNode();
2135 decode->set_opnd_array(0, new iRegPdstOper());
2136 decode->set_opnd_array(1, new iRegNsrcOper());
2137 return decode;
2138 }
2139 */
2140
2141 // false => size gets scaled to BytesPerLong, ok.
2142 const bool Matcher::init_array_count_is_in_bytes = false;
2143
2144 // Use conditional move (CMOVL) on Power7.
2145 const int Matcher::long_cmove_cost() { return 0; } // this only makes long cmoves more expensive than int cmoves
2146
2147 // Suppress CMOVF. Conditional move available (sort of) on PPC64 only from P7 onwards. Not exploited yet.
2148 // fsel doesn't accept a condition register as input, so this would be slightly different.
2149 const int Matcher::float_cmove_cost() { return ConditionalMoveLimit; }
2150
2151 // Power6 requires postalloc expand (see block.cpp for description of postalloc expand).
2152 const bool Matcher::require_postalloc_expand = true;
2153
2154 // Should the Matcher clone shifts on addressing modes, expecting them to
2155 // be subsumed into complex addressing expressions or compute them into
2156 // registers? True for Intel but false for most RISCs.
2157 const bool Matcher::clone_shift_expressions = false;
2158
2159 // Do we need to mask the count passed to shift instructions or does
|