1 /*
2 * Copyright (c) 2008, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.hpp"
27 #include "c1/c1_Defs.hpp"
28 #include "c1/c1_LIRAssembler.hpp"
29 #include "c1/c1_MacroAssembler.hpp"
30 #include "c1/c1_Runtime1.hpp"
31 #include "ci/ciUtilities.hpp"
32 #include "gc/shared/cardTable.hpp"
33 #include "gc/shared/cardTableModRefBS.hpp"
34 #include "interpreter/interpreter.hpp"
35 #include "nativeInst_arm.hpp"
36 #include "oops/compiledICHolder.hpp"
37 #include "oops/oop.inline.hpp"
38 #include "prims/jvmtiExport.hpp"
39 #include "register_arm.hpp"
40 #include "runtime/sharedRuntime.hpp"
41 #include "runtime/signature.hpp"
42 #include "runtime/vframeArray.hpp"
43 #include "utilities/align.hpp"
44 #include "vmreg_arm.inline.hpp"
45 #if INCLUDE_ALL_GCS
46 #include "gc/g1/g1BarrierSet.hpp"
47 #include "gc/g1/g1CardTable.hpp"
48 #endif
49
50 // Note: Rtemp usage is this file should not impact C2 and should be
51 // correct as long as it is not implicitly used in lower layers (the
52 // arm [macro]assembler) and used with care in the other C1 specific
53 // files.
54
55 // Implementation of StubAssembler
56
57 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, int args_size) {
58 mov(R0, Rthread);
59
60 int call_offset = set_last_Java_frame(SP, FP, false, Rtemp);
61
62 call(entry);
63 if (call_offset == -1) { // PC not saved
64 call_offset = offset();
65 }
66 reset_last_Java_frame(Rtemp);
67
68 assert(frame_size() != no_frame_size, "frame must be fixed");
69 if (_stub_id != Runtime1::forward_exception_id) {
70 ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
71 }
72
73 if (oop_result1->is_valid()) {
74 assert_different_registers(oop_result1, R3, Rtemp);
75 get_vm_result(oop_result1, Rtemp);
76 }
77 if (metadata_result->is_valid()) {
78 assert_different_registers(metadata_result, R3, Rtemp);
79 get_vm_result_2(metadata_result, Rtemp);
80 }
81
82 // Check for pending exception
83 // unpack_with_exception_in_tls path is taken through
84 // Runtime1::exception_handler_for_pc
85 if (_stub_id != Runtime1::forward_exception_id) {
86 assert(frame_size() != no_frame_size, "cannot directly call forward_exception_id");
87 #ifdef AARCH64
88 Label skip;
89 cbz(R3, skip);
90 jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp);
91 bind(skip);
92 #else
93 cmp(R3, 0);
94 jump(Runtime1::entry_for(Runtime1::forward_exception_id), relocInfo::runtime_call_type, Rtemp, ne);
95 #endif // AARCH64
96 } else {
97 #ifdef ASSERT
98 // Should not have pending exception in forward_exception stub
99 ldr(R3, Address(Rthread, Thread::pending_exception_offset()));
100 cmp(R3, 0);
101 breakpoint(ne);
102 #endif // ASSERT
103 }
104 return call_offset;
105 }
106
107
108 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1) {
109 if (arg1 != R1) {
110 mov(R1, arg1);
111 }
112 return call_RT(oop_result1, metadata_result, entry, 1);
113 }
114
115
116 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2) {
117 assert(arg1 == R1 && arg2 == R2, "cannot handle otherwise");
118 return call_RT(oop_result1, metadata_result, entry, 2);
119 }
120
121
122 int StubAssembler::call_RT(Register oop_result1, Register metadata_result, address entry, Register arg1, Register arg2, Register arg3) {
123 assert(arg1 == R1 && arg2 == R2 && arg3 == R3, "cannot handle otherwise");
124 return call_RT(oop_result1, metadata_result, entry, 3);
125 }
126
127
128 #define __ sasm->
129
130 // TODO: ARM - does this duplicate RegisterSaver in SharedRuntime?
131 #ifdef AARCH64
132
133 //
134 // On AArch64 registers save area has the following layout:
135 //
136 // |---------------------|
137 // | return address (LR) |
138 // | FP |
139 // |---------------------|
140 // | D31 |
141 // | ... |
142 // | D0 |
143 // |---------------------|
144 // | padding |
145 // |---------------------|
146 // | R28 |
147 // | ... |
148 // | R0 |
149 // |---------------------| <-- SP
150 //
151
152 enum RegisterLayout {
153 number_of_saved_gprs = 29,
154 number_of_saved_fprs = FloatRegisterImpl::number_of_registers,
155
156 R0_offset = 0,
157 D0_offset = R0_offset + number_of_saved_gprs + 1,
158 FP_offset = D0_offset + number_of_saved_fprs,
159 LR_offset = FP_offset + 1,
160
161 reg_save_size = LR_offset + 1,
162
163 arg1_offset = reg_save_size * wordSize,
164 arg2_offset = (reg_save_size + 1) * wordSize
165 };
166
167 #else
168
169 enum RegisterLayout {
170 fpu_save_size = pd_nof_fpu_regs_reg_alloc,
171 #ifndef __SOFTFP__
172 D0_offset = 0,
173 #endif
174 R0_offset = fpu_save_size,
175 R1_offset,
176 R2_offset,
177 R3_offset,
178 R4_offset,
179 R5_offset,
180 R6_offset,
181 #if (FP_REG_NUM != 7)
182 R7_offset,
183 #endif
184 R8_offset,
185 R9_offset,
186 R10_offset,
187 #if (FP_REG_NUM != 11)
188 R11_offset,
189 #endif
190 R12_offset,
191 FP_offset,
192 LR_offset,
193 reg_save_size,
194 arg1_offset = reg_save_size * wordSize,
195 arg2_offset = (reg_save_size + 1) * wordSize
196 };
197
198 #endif // AARCH64
199
200 static OopMap* generate_oop_map(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
201 sasm->set_frame_size(reg_save_size /* in words */);
202
203 // Record saved value locations in an OopMap.
204 // Locations are offsets from sp after runtime call.
205 OopMap* map = new OopMap(VMRegImpl::slots_per_word * reg_save_size, 0);
206
207 #ifdef AARCH64
208 for (int i = 0; i < number_of_saved_gprs; i++) {
209 map->set_callee_saved(VMRegImpl::stack2reg((R0_offset + i) * VMRegImpl::slots_per_word), as_Register(i)->as_VMReg());
210 }
211 map->set_callee_saved(VMRegImpl::stack2reg(FP_offset * VMRegImpl::slots_per_word), FP->as_VMReg());
212 map->set_callee_saved(VMRegImpl::stack2reg(LR_offset * VMRegImpl::slots_per_word), LR->as_VMReg());
213
214 if (save_fpu_registers) {
215 for (int i = 0; i < number_of_saved_fprs; i++) {
216 map->set_callee_saved(VMRegImpl::stack2reg((D0_offset + i) * VMRegImpl::slots_per_word), as_FloatRegister(i)->as_VMReg());
217 }
218 }
219 #else
220 int j=0;
221 for (int i = R0_offset; i < R10_offset; i++) {
222 if (j == FP_REG_NUM) {
223 // skip the FP register, saved below
224 j++;
225 }
226 map->set_callee_saved(VMRegImpl::stack2reg(i), as_Register(j)->as_VMReg());
227 j++;
228 }
229 assert(j == R10->encoding(), "must be");
230 #if (FP_REG_NUM != 11)
231 // add R11, if not saved as FP
232 map->set_callee_saved(VMRegImpl::stack2reg(R11_offset), R11->as_VMReg());
233 #endif
234 map->set_callee_saved(VMRegImpl::stack2reg(FP_offset), FP->as_VMReg());
235 map->set_callee_saved(VMRegImpl::stack2reg(LR_offset), LR->as_VMReg());
236
237 if (save_fpu_registers) {
238 for (int i = 0; i < fpu_save_size; i++) {
239 map->set_callee_saved(VMRegImpl::stack2reg(i), as_FloatRegister(i)->as_VMReg());
240 }
241 }
242 #endif // AARCH64
243
244 return map;
245 }
246
247 static OopMap* save_live_registers(StubAssembler* sasm, bool save_fpu_registers = HaveVFP) {
248 __ block_comment("save_live_registers");
249 sasm->set_frame_size(reg_save_size /* in words */);
250
251 #ifdef AARCH64
252 assert((reg_save_size * wordSize) % StackAlignmentInBytes == 0, "SP should be aligned");
253
254 __ raw_push(FP, LR);
255
256 __ sub(SP, SP, (reg_save_size - 2) * wordSize);
257
258 for (int i = 0; i < align_down((int)number_of_saved_gprs, 2); i += 2) {
259 __ stp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
260 }
261
262 if (is_odd(number_of_saved_gprs)) {
263 int i = number_of_saved_gprs - 1;
264 __ str(as_Register(i), Address(SP, (R0_offset + i) * wordSize));
265 }
266
267 if (save_fpu_registers) {
268 assert (is_even(number_of_saved_fprs), "adjust this code");
269 for (int i = 0; i < number_of_saved_fprs; i += 2) {
270 __ stp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
271 }
272 }
273 #else
274 __ push(RegisterSet(FP) | RegisterSet(LR));
275 __ push(RegisterSet(R0, R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
276 if (save_fpu_registers) {
277 __ fstmdbd(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
278 } else {
279 __ sub(SP, SP, fpu_save_size * wordSize);
280 }
281 #endif // AARCH64
282
283 return generate_oop_map(sasm, save_fpu_registers);
284 }
285
286
287 static void restore_live_registers(StubAssembler* sasm,
288 bool restore_R0,
289 bool restore_FP_LR,
290 bool do_return,
291 bool restore_fpu_registers = HaveVFP) {
292 __ block_comment("restore_live_registers");
293
294 #ifdef AARCH64
295 if (restore_R0) {
296 __ ldr(R0, Address(SP, R0_offset * wordSize));
297 }
298
299 assert(is_odd(number_of_saved_gprs), "adjust this code");
300 for (int i = 1; i < number_of_saved_gprs; i += 2) {
301 __ ldp(as_Register(i), as_Register(i+1), Address(SP, (R0_offset + i) * wordSize));
302 }
303
304 if (restore_fpu_registers) {
305 assert (is_even(number_of_saved_fprs), "adjust this code");
306 for (int i = 0; i < number_of_saved_fprs; i += 2) {
307 __ ldp_d(as_FloatRegister(i), as_FloatRegister(i+1), Address(SP, (D0_offset + i) * wordSize));
308 }
309 }
310
311 __ add(SP, SP, (reg_save_size - 2) * wordSize);
312
313 if (restore_FP_LR) {
314 __ raw_pop(FP, LR);
315 if (do_return) {
316 __ ret();
317 }
318 } else {
319 assert (!do_return, "return without restoring FP/LR");
320 }
321 #else
322 if (restore_fpu_registers) {
323 __ fldmiad(SP, FloatRegisterSet(D0, fpu_save_size / 2), writeback);
324 if (!restore_R0) {
325 __ add(SP, SP, (R1_offset - fpu_save_size) * wordSize);
326 }
327 } else {
328 __ add(SP, SP, (restore_R0 ? fpu_save_size : R1_offset) * wordSize);
329 }
330 __ pop(RegisterSet((restore_R0 ? R0 : R1), R6) | RegisterSet(R8, R10) | R12 | altFP_7_11);
331 if (restore_FP_LR) {
332 __ pop(RegisterSet(FP) | RegisterSet(do_return ? PC : LR));
333 } else {
334 assert (!do_return, "return without restoring FP/LR");
335 }
336 #endif // AARCH64
337 }
338
339
340 static void restore_live_registers_except_R0(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
341 restore_live_registers(sasm, false, true, true, restore_fpu_registers);
342 }
343
344 static void restore_live_registers(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
345 restore_live_registers(sasm, true, true, true, restore_fpu_registers);
346 }
347
348 #ifndef AARCH64
349 static void restore_live_registers_except_FP_LR(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
350 restore_live_registers(sasm, true, false, false, restore_fpu_registers);
351 }
352 #endif // !AARCH64
353
354 static void restore_live_registers_without_return(StubAssembler* sasm, bool restore_fpu_registers = HaveVFP) {
355 restore_live_registers(sasm, true, true, false, restore_fpu_registers);
356 }
357
358
359 void Runtime1::initialize_pd() {
360 }
361
362
363 OopMapSet* Runtime1::generate_exception_throw(StubAssembler* sasm, address target, bool has_argument) {
364 OopMap* oop_map = save_live_registers(sasm);
365
366 if (has_argument) {
367 __ ldr(R1, Address(SP, arg1_offset));
368 }
369
370 int call_offset = __ call_RT(noreg, noreg, target);
371 OopMapSet* oop_maps = new OopMapSet();
372 oop_maps->add_gc_map(call_offset, oop_map);
373
374 DEBUG_ONLY(STOP("generate_exception_throw");) // Should not reach here
375 return oop_maps;
376 }
377
378
379 static void restore_sp_for_method_handle(StubAssembler* sasm) {
380 // Restore SP from its saved reg (FP) if the exception PC is a MethodHandle call site.
381 __ ldr_s32(Rtemp, Address(Rthread, JavaThread::is_method_handle_return_offset()));
382 #ifdef AARCH64
383 Label skip;
384 __ cbz(Rtemp, skip);
385 __ mov(SP, Rmh_SP_save);
386 __ bind(skip);
387 #else
388 __ cmp(Rtemp, 0);
389 __ mov(SP, Rmh_SP_save, ne);
390 #endif // AARCH64
391 }
392
393
394 OopMapSet* Runtime1::generate_handle_exception(StubID id, StubAssembler* sasm) {
395 __ block_comment("generate_handle_exception");
396
397 bool save_fpu_registers = false;
398
399 // Save registers, if required.
400 OopMapSet* oop_maps = new OopMapSet();
401 OopMap* oop_map = NULL;
402
403 switch (id) {
404 case forward_exception_id: {
405 save_fpu_registers = HaveVFP;
406 oop_map = generate_oop_map(sasm);
407 __ ldr(Rexception_obj, Address(Rthread, Thread::pending_exception_offset()));
408 __ ldr(Rexception_pc, Address(SP, LR_offset * wordSize));
409 Register zero = __ zero_register(Rtemp);
410 __ str(zero, Address(Rthread, Thread::pending_exception_offset()));
411 break;
412 }
413 case handle_exception_id:
414 save_fpu_registers = HaveVFP;
415 // fall-through
416 case handle_exception_nofpu_id:
417 // At this point all registers MAY be live.
418 oop_map = save_live_registers(sasm, save_fpu_registers);
419 break;
420 case handle_exception_from_callee_id:
421 // At this point all registers except exception oop (R4/R19) and
422 // exception pc (R5/R20) are dead.
423 oop_map = save_live_registers(sasm); // TODO it's not required to save all registers
424 break;
425 default: ShouldNotReachHere();
426 }
427
428 __ str(Rexception_obj, Address(Rthread, JavaThread::exception_oop_offset()));
429 __ str(Rexception_pc, Address(Rthread, JavaThread::exception_pc_offset()));
430
431 __ str(Rexception_pc, Address(SP, LR_offset * wordSize)); // patch throwing pc into return address
432
433 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, exception_handler_for_pc));
434 oop_maps->add_gc_map(call_offset, oop_map);
435
436 // Exception handler found
437 __ str(R0, Address(SP, LR_offset * wordSize)); // patch the return address
438
439 // Restore the registers that were saved at the beginning, remove
440 // frame and jump to the exception handler.
441 switch (id) {
442 case forward_exception_id:
443 case handle_exception_nofpu_id:
444 case handle_exception_id:
445 restore_live_registers(sasm, save_fpu_registers);
446 // Note: the restore live registers includes the jump to LR (patched to R0)
447 break;
448 case handle_exception_from_callee_id:
449 restore_live_registers_without_return(sasm); // must not jump immediatly to handler
450 restore_sp_for_method_handle(sasm);
451 __ ret();
452 break;
453 default: ShouldNotReachHere();
454 }
455
456 DEBUG_ONLY(STOP("generate_handle_exception");) // Should not reach here
457
458 return oop_maps;
459 }
460
461
462 void Runtime1::generate_unwind_exception(StubAssembler* sasm) {
463 // FP no longer used to find the frame start
464 // on entry, remove_frame() has already been called (restoring FP and LR)
465
466 // search the exception handler address of the caller (using the return address)
467 __ mov(c_rarg0, Rthread);
468 __ mov(Rexception_pc, LR);
469 __ mov(c_rarg1, LR);
470 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::exception_handler_for_return_address), c_rarg0, c_rarg1);
471
472 // Exception oop should be still in Rexception_obj and pc in Rexception_pc
473 // Jump to handler
474 __ verify_not_null_oop(Rexception_obj);
475
476 // JSR292 extension
477 restore_sp_for_method_handle(sasm);
478
479 __ jump(R0);
480 }
481
482
483 OopMapSet* Runtime1::generate_patching(StubAssembler* sasm, address target) {
484 OopMap* oop_map = save_live_registers(sasm);
485
486 // call the runtime patching routine, returns non-zero if nmethod got deopted.
487 int call_offset = __ call_RT(noreg, noreg, target);
488 OopMapSet* oop_maps = new OopMapSet();
489 oop_maps->add_gc_map(call_offset, oop_map);
490
491 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
492 assert(deopt_blob != NULL, "deoptimization blob must have been created");
493
494 __ cmp_32(R0, 0);
495
496 #ifdef AARCH64
497 Label call_deopt;
498
499 restore_live_registers_without_return(sasm);
500 __ b(call_deopt, ne);
501 __ ret();
502
503 __ bind(call_deopt);
504 #else
505 restore_live_registers_except_FP_LR(sasm);
506 __ pop(RegisterSet(FP) | RegisterSet(PC), eq);
507
508 // Deoptimization needed
509 // TODO: ARM - no need to restore FP & LR because unpack_with_reexecution() stores them back
510 __ pop(RegisterSet(FP) | RegisterSet(LR));
511 #endif // AARCH64
512
513 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
514
515 DEBUG_ONLY(STOP("generate_patching");) // Should not reach here
516 return oop_maps;
517 }
518
519
520 OopMapSet* Runtime1::generate_code_for(StubID id, StubAssembler* sasm) {
521 const bool must_gc_arguments = true;
522 const bool dont_gc_arguments = false;
523
524 OopMapSet* oop_maps = NULL;
525 bool save_fpu_registers = HaveVFP;
526
527 switch (id) {
528 case forward_exception_id:
529 {
530 oop_maps = generate_handle_exception(id, sasm);
531 // does not return on ARM
532 }
533 break;
534
535 #if INCLUDE_ALL_GCS
536 case g1_pre_barrier_slow_id:
537 {
538 // Input:
539 // - pre_val pushed on the stack
540
541 __ set_info("g1_pre_barrier_slow_id", dont_gc_arguments);
542
543 BarrierSet* bs = Universe::heap()->barrier_set();
544 if (bs->kind() != BarrierSet::G1BarrierSet) {
545 __ mov(R0, (int)id);
546 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), R0);
547 __ should_not_reach_here();
548 break;
549 }
550
551 // save at least the registers that need saving if the runtime is called
552 #ifdef AARCH64
553 __ raw_push(R0, R1);
554 __ raw_push(R2, R3);
555 const int nb_saved_regs = 4;
556 #else // AARCH64
557 const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
558 const int nb_saved_regs = 6;
559 assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
560 __ push(saved_regs);
561 #endif // AARCH64
562
563 const Register r_pre_val_0 = R0; // must be R0, to be ready for the runtime call
564 const Register r_index_1 = R1;
565 const Register r_buffer_2 = R2;
566
567 Address queue_active(Rthread, in_bytes(JavaThread::satb_mark_queue_offset() +
568 SATBMarkQueue::byte_offset_of_active()));
569 Address queue_index(Rthread, in_bytes(JavaThread::satb_mark_queue_offset() +
570 SATBMarkQueue::byte_offset_of_index()));
571 Address buffer(Rthread, in_bytes(JavaThread::satb_mark_queue_offset() +
572 SATBMarkQueue::byte_offset_of_buf()));
573
574 Label done;
575 Label runtime;
576
577 // Is marking still active?
578 assert(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
579 __ ldrb(R1, queue_active);
580 __ cbz(R1, done);
581
582 __ ldr(r_index_1, queue_index);
583 __ ldr(r_pre_val_0, Address(SP, nb_saved_regs*wordSize));
584 __ ldr(r_buffer_2, buffer);
585
586 __ subs(r_index_1, r_index_1, wordSize);
587 __ b(runtime, lt);
588
589 __ str(r_index_1, queue_index);
590 __ str(r_pre_val_0, Address(r_buffer_2, r_index_1));
591
592 __ bind(done);
593
594 #ifdef AARCH64
595 __ raw_pop(R2, R3);
596 __ raw_pop(R0, R1);
597 #else // AARCH64
598 __ pop(saved_regs);
599 #endif // AARCH64
600
601 __ ret();
602
603 __ bind(runtime);
604
605 save_live_registers(sasm);
606
607 assert(r_pre_val_0 == c_rarg0, "pre_val should be in R0");
608 __ mov(c_rarg1, Rthread);
609 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), c_rarg0, c_rarg1);
610
611 restore_live_registers_without_return(sasm);
612
613 __ b(done);
614 }
615 break;
616 case g1_post_barrier_slow_id:
617 {
618 // Input:
619 // - store_addr, pushed on the stack
620
621 __ set_info("g1_post_barrier_slow_id", dont_gc_arguments);
622
623 BarrierSet* bs = Universe::heap()->barrier_set();
624 if (bs->kind() != BarrierSet::G1BarrierSet) {
625 __ mov(R0, (int)id);
626 __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, unimplemented_entry), R0);
627 __ should_not_reach_here();
628 break;
629 }
630
631 Label done;
632 Label recheck;
633 Label runtime;
634
635 Address queue_index(Rthread, in_bytes(JavaThread::dirty_card_queue_offset() +
636 DirtyCardQueue::byte_offset_of_index()));
637 Address buffer(Rthread, in_bytes(JavaThread::dirty_card_queue_offset() +
638 DirtyCardQueue::byte_offset_of_buf()));
639
640 AddressLiteral cardtable(ci_card_table_address_as<address>(), relocInfo::none);
641
642 // save at least the registers that need saving if the runtime is called
643 #ifdef AARCH64
644 __ raw_push(R0, R1);
645 __ raw_push(R2, R3);
646 const int nb_saved_regs = 4;
647 #else // AARCH64
648 const RegisterSet saved_regs = RegisterSet(R0,R3) | RegisterSet(R12) | RegisterSet(LR);
649 const int nb_saved_regs = 6;
650 assert(nb_saved_regs == saved_regs.size(), "fix nb_saved_regs");
651 __ push(saved_regs);
652 #endif // AARCH64
653
654 const Register r_card_addr_0 = R0; // must be R0 for the slow case
655 const Register r_obj_0 = R0;
656 const Register r_card_base_1 = R1;
657 const Register r_tmp2 = R2;
658 const Register r_index_2 = R2;
659 const Register r_buffer_3 = R3;
660 const Register tmp1 = Rtemp;
661
662 __ ldr(r_obj_0, Address(SP, nb_saved_regs*wordSize));
663 // Note: there is a comment in x86 code about not using
664 // ExternalAddress / lea, due to relocation not working
665 // properly for that address. Should be OK for arm, where we
666 // explicitly specify that 'cardtable' has a relocInfo::none
667 // type.
668 __ lea(r_card_base_1, cardtable);
669 __ add(r_card_addr_0, r_card_base_1, AsmOperand(r_obj_0, lsr, CardTable::card_shift));
670
671 // first quick check without barrier
672 __ ldrb(r_tmp2, Address(r_card_addr_0));
673
674 __ cmp(r_tmp2, (int)G1CardTable::g1_young_card_val());
675 __ b(recheck, ne);
676
677 __ bind(done);
678
679 #ifdef AARCH64
680 __ raw_pop(R2, R3);
681 __ raw_pop(R0, R1);
682 #else // AARCH64
683 __ pop(saved_regs);
684 #endif // AARCH64
685
686 __ ret();
687
688 __ bind(recheck);
689
690 __ membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad), tmp1);
691
692 // reload card state after the barrier that ensures the stored oop was visible
693 __ ldrb(r_tmp2, Address(r_card_addr_0));
694
695 assert(CardTable::dirty_card_val() == 0, "adjust this code");
696 __ cbz(r_tmp2, done);
697
698 // storing region crossing non-NULL, card is clean.
699 // dirty card and log.
700
701 assert(0 == (int)CardTable::dirty_card_val(), "adjust this code");
702 if ((ci_card_table_address_as<intptr_t>() & 0xff) == 0) {
703 // Card table is aligned so the lowest byte of the table address base is zero.
704 __ strb(r_card_base_1, Address(r_card_addr_0));
705 } else {
706 __ strb(__ zero_register(r_tmp2), Address(r_card_addr_0));
707 }
708
709 __ ldr(r_index_2, queue_index);
710 __ ldr(r_buffer_3, buffer);
711
712 __ subs(r_index_2, r_index_2, wordSize);
713 __ b(runtime, lt); // go to runtime if now negative
714
715 __ str(r_index_2, queue_index);
716
717 __ str(r_card_addr_0, Address(r_buffer_3, r_index_2));
718
719 __ b(done);
720
721 __ bind(runtime);
722
723 save_live_registers(sasm);
724
725 assert(r_card_addr_0 == c_rarg0, "card_addr should be in R0");
726 __ mov(c_rarg1, Rthread);
727 __ call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), c_rarg0, c_rarg1);
728
729 restore_live_registers_without_return(sasm);
730
731 __ b(done);
732 }
733 break;
734 #endif // INCLUDE_ALL_GCS
735 case new_instance_id:
736 case fast_new_instance_id:
737 case fast_new_instance_init_check_id:
738 {
739 const Register result = R0;
740 const Register klass = R1;
741
742 if (UseTLAB && Universe::heap()->supports_inline_contig_alloc() && id != new_instance_id) {
743 // We come here when TLAB allocation failed.
744 // In this case we try to allocate directly from eden.
745 Label slow_case, slow_case_no_pop;
746
747 // Make sure the class is fully initialized
748 if (id == fast_new_instance_init_check_id) {
749 __ ldrb(result, Address(klass, InstanceKlass::init_state_offset()));
750 __ cmp(result, InstanceKlass::fully_initialized);
751 __ b(slow_case_no_pop, ne);
752 }
753
754 // Free some temporary registers
755 const Register obj_size = R4;
756 const Register tmp1 = R5;
757 const Register tmp2 = LR;
758 const Register obj_end = Rtemp;
759
760 __ raw_push(R4, R5, LR);
761
762 __ ldr_u32(obj_size, Address(klass, Klass::layout_helper_offset()));
763 __ eden_allocate(result, obj_end, tmp1, tmp2, obj_size, slow_case); // initializes result and obj_end
764 __ incr_allocated_bytes(obj_size, tmp2);
765 __ initialize_object(result, obj_end, klass, noreg /* len */, tmp1, tmp2,
766 instanceOopDesc::header_size() * HeapWordSize, -1,
767 /* is_tlab_allocated */ false);
768 __ raw_pop_and_ret(R4, R5);
769
770 __ bind(slow_case);
771 __ raw_pop(R4, R5, LR);
772
773 __ bind(slow_case_no_pop);
774 }
775
776 OopMap* map = save_live_registers(sasm);
777 int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_instance), klass);
778 oop_maps = new OopMapSet();
779 oop_maps->add_gc_map(call_offset, map);
780
781 // MacroAssembler::StoreStore useless (included in the runtime exit path)
782
783 restore_live_registers_except_R0(sasm);
784 }
785 break;
786
787 case counter_overflow_id:
788 {
789 OopMap* oop_map = save_live_registers(sasm);
790 __ ldr(R1, Address(SP, arg1_offset));
791 __ ldr(R2, Address(SP, arg2_offset));
792 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, counter_overflow), R1, R2);
793 oop_maps = new OopMapSet();
794 oop_maps->add_gc_map(call_offset, oop_map);
795 restore_live_registers(sasm);
796 }
797 break;
798
799 case new_type_array_id:
800 case new_object_array_id:
801 {
802 if (id == new_type_array_id) {
803 __ set_info("new_type_array", dont_gc_arguments);
804 } else {
805 __ set_info("new_object_array", dont_gc_arguments);
806 }
807
808 const Register result = R0;
809 const Register klass = R1;
810 const Register length = R2;
811
812 if (UseTLAB && Universe::heap()->supports_inline_contig_alloc()) {
813 // We come here when TLAB allocation failed.
814 // In this case we try to allocate directly from eden.
815 Label slow_case, slow_case_no_pop;
816
817 #ifdef AARCH64
818 __ mov_slow(Rtemp, C1_MacroAssembler::max_array_allocation_length);
819 __ cmp_32(length, Rtemp);
820 #else
821 __ cmp_32(length, C1_MacroAssembler::max_array_allocation_length);
822 #endif // AARCH64
823 __ b(slow_case_no_pop, hs);
824
825 // Free some temporary registers
826 const Register arr_size = R4;
827 const Register tmp1 = R5;
828 const Register tmp2 = LR;
829 const Register tmp3 = Rtemp;
830 const Register obj_end = tmp3;
831
832 __ raw_push(R4, R5, LR);
833
834 // Get the allocation size: round_up((length << (layout_helper & 0xff)) + header_size)
835 __ ldr_u32(tmp1, Address(klass, Klass::layout_helper_offset()));
836 __ mov(arr_size, MinObjAlignmentInBytesMask);
837 __ and_32(tmp2, tmp1, (unsigned int)(Klass::_lh_header_size_mask << Klass::_lh_header_size_shift));
838
839 #ifdef AARCH64
840 __ lslv_w(tmp3, length, tmp1);
841 __ add(arr_size, arr_size, tmp3);
842 #else
843 __ add(arr_size, arr_size, AsmOperand(length, lsl, tmp1));
844 #endif // AARCH64
845
846 __ add(arr_size, arr_size, AsmOperand(tmp2, lsr, Klass::_lh_header_size_shift));
847 __ align_reg(arr_size, arr_size, MinObjAlignmentInBytes);
848
849 // eden_allocate destroys tmp2, so reload header_size after allocation
850 // eden_allocate initializes result and obj_end
851 __ eden_allocate(result, obj_end, tmp1, tmp2, arr_size, slow_case);
852 __ incr_allocated_bytes(arr_size, tmp2);
853 __ ldrb(tmp2, Address(klass, in_bytes(Klass::layout_helper_offset()) +
854 Klass::_lh_header_size_shift / BitsPerByte));
855 __ initialize_object(result, obj_end, klass, length, tmp1, tmp2, tmp2, -1, /* is_tlab_allocated */ false);
856 __ raw_pop_and_ret(R4, R5);
857
858 __ bind(slow_case);
859 __ raw_pop(R4, R5, LR);
860 __ bind(slow_case_no_pop);
861 }
862
863 OopMap* map = save_live_registers(sasm);
864 int call_offset;
865 if (id == new_type_array_id) {
866 call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_type_array), klass, length);
867 } else {
868 call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_object_array), klass, length);
869 }
870 oop_maps = new OopMapSet();
871 oop_maps->add_gc_map(call_offset, map);
872
873 // MacroAssembler::StoreStore useless (included in the runtime exit path)
874
875 restore_live_registers_except_R0(sasm);
876 }
877 break;
878
879 case new_multi_array_id:
880 {
881 __ set_info("new_multi_array", dont_gc_arguments);
882
883 // R0: klass
884 // R2: rank
885 // SP: address of 1st dimension
886 const Register result = R0;
887 OopMap* map = save_live_registers(sasm);
888
889 __ mov(R1, R0);
890 __ add(R3, SP, arg1_offset);
891 int call_offset = __ call_RT(result, noreg, CAST_FROM_FN_PTR(address, new_multi_array), R1, R2, R3);
892
893 oop_maps = new OopMapSet();
894 oop_maps->add_gc_map(call_offset, map);
895
896 // MacroAssembler::StoreStore useless (included in the runtime exit path)
897
898 restore_live_registers_except_R0(sasm);
899 }
900 break;
901
902 case register_finalizer_id:
903 {
904 __ set_info("register_finalizer", dont_gc_arguments);
905
906 // Do not call runtime if JVM_ACC_HAS_FINALIZER flag is not set
907 __ load_klass(Rtemp, R0);
908 __ ldr_u32(Rtemp, Address(Rtemp, Klass::access_flags_offset()));
909
910 #ifdef AARCH64
911 Label L;
912 __ tbnz(Rtemp, exact_log2(JVM_ACC_HAS_FINALIZER), L);
913 __ ret();
914 __ bind(L);
915 #else
916 __ tst(Rtemp, JVM_ACC_HAS_FINALIZER);
917 __ bx(LR, eq);
918 #endif // AARCH64
919
920 // Call VM
921 OopMap* map = save_live_registers(sasm);
922 oop_maps = new OopMapSet();
923 int call_offset = __ call_RT(noreg, noreg,
924 CAST_FROM_FN_PTR(address, SharedRuntime::register_finalizer), R0);
925 oop_maps->add_gc_map(call_offset, map);
926 restore_live_registers(sasm);
927 }
928 break;
929
930 case throw_range_check_failed_id:
931 {
932 __ set_info("range_check_failed", dont_gc_arguments);
933 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_range_check_exception), true);
934 }
935 break;
936
937 case throw_index_exception_id:
938 {
939 __ set_info("index_range_check_failed", dont_gc_arguments);
940 #ifdef AARCH64
941 __ NOT_TESTED();
942 #endif
943 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_index_exception), true);
944 }
945 break;
946
947 case throw_div0_exception_id:
948 {
949 __ set_info("throw_div0_exception", dont_gc_arguments);
950 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_div0_exception), false);
951 }
952 break;
953
954 case throw_null_pointer_exception_id:
955 {
956 __ set_info("throw_null_pointer_exception", dont_gc_arguments);
957 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_null_pointer_exception), false);
958 }
959 break;
960
961 case handle_exception_nofpu_id:
962 case handle_exception_id:
963 {
964 __ set_info("handle_exception", dont_gc_arguments);
965 oop_maps = generate_handle_exception(id, sasm);
966 }
967 break;
968
969 case handle_exception_from_callee_id:
970 {
971 __ set_info("handle_exception_from_callee", dont_gc_arguments);
972 oop_maps = generate_handle_exception(id, sasm);
973 }
974 break;
975
976 case unwind_exception_id:
977 {
978 __ set_info("unwind_exception", dont_gc_arguments);
979 generate_unwind_exception(sasm);
980 }
981 break;
982
983 case throw_array_store_exception_id:
984 {
985 __ set_info("throw_array_store_exception", dont_gc_arguments);
986 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_array_store_exception), true);
987 }
988 break;
989
990 case throw_class_cast_exception_id:
991 {
992 __ set_info("throw_class_cast_exception", dont_gc_arguments);
993 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_class_cast_exception), true);
994 }
995 break;
996
997 case throw_incompatible_class_change_error_id:
998 {
999 __ set_info("throw_incompatible_class_cast_exception", dont_gc_arguments);
1000 #ifdef AARCH64
1001 __ NOT_TESTED();
1002 #endif
1003 oop_maps = generate_exception_throw(sasm, CAST_FROM_FN_PTR(address, throw_incompatible_class_change_error), false);
1004 }
1005 break;
1006
1007 case slow_subtype_check_id:
1008 {
1009 // (in) R0 - sub, destroyed,
1010 // (in) R1 - super, not changed
1011 // (out) R0 - result: 1 if check passed, 0 otherwise
1012 __ raw_push(R2, R3, LR);
1013
1014 // Load an array of secondary_supers
1015 __ ldr(R2, Address(R0, Klass::secondary_supers_offset()));
1016 // Length goes to R3
1017 __ ldr_s32(R3, Address(R2, Array<Klass*>::length_offset_in_bytes()));
1018 __ add(R2, R2, Array<Klass*>::base_offset_in_bytes());
1019
1020 Label loop, miss;
1021 __ bind(loop);
1022 __ cbz(R3, miss);
1023 __ ldr(LR, Address(R2, wordSize, post_indexed));
1024 __ sub(R3, R3, 1);
1025 __ cmp(LR, R1);
1026 __ b(loop, ne);
1027
1028 // We get here if an equal cache entry is found
1029 __ str(R1, Address(R0, Klass::secondary_super_cache_offset()));
1030 __ mov(R0, 1);
1031 __ raw_pop_and_ret(R2, R3);
1032
1033 // A cache entry not found - return false
1034 __ bind(miss);
1035 __ mov(R0, 0);
1036 __ raw_pop_and_ret(R2, R3);
1037 }
1038 break;
1039
1040 case monitorenter_nofpu_id:
1041 save_fpu_registers = false;
1042 // fall through
1043 case monitorenter_id:
1044 {
1045 __ set_info("monitorenter", dont_gc_arguments);
1046 const Register obj = R1;
1047 const Register lock = R2;
1048 OopMap* map = save_live_registers(sasm, save_fpu_registers);
1049 __ ldr(obj, Address(SP, arg1_offset));
1050 __ ldr(lock, Address(SP, arg2_offset));
1051 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorenter), obj, lock);
1052 oop_maps = new OopMapSet();
1053 oop_maps->add_gc_map(call_offset, map);
1054 restore_live_registers(sasm, save_fpu_registers);
1055 }
1056 break;
1057
1058 case monitorexit_nofpu_id:
1059 save_fpu_registers = false;
1060 // fall through
1061 case monitorexit_id:
1062 {
1063 __ set_info("monitorexit", dont_gc_arguments);
1064 const Register lock = R1;
1065 OopMap* map = save_live_registers(sasm, save_fpu_registers);
1066 __ ldr(lock, Address(SP, arg1_offset));
1067 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, monitorexit), lock);
1068 oop_maps = new OopMapSet();
1069 oop_maps->add_gc_map(call_offset, map);
1070 restore_live_registers(sasm, save_fpu_registers);
1071 }
1072 break;
1073
1074 case deoptimize_id:
1075 {
1076 __ set_info("deoptimize", dont_gc_arguments);
1077 OopMap* oop_map = save_live_registers(sasm);
1078 const Register trap_request = R1;
1079 __ ldr(trap_request, Address(SP, arg1_offset));
1080 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, deoptimize), trap_request);
1081 oop_maps = new OopMapSet();
1082 oop_maps->add_gc_map(call_offset, oop_map);
1083 restore_live_registers_without_return(sasm);
1084 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1085 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1086 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, AARCH64_ONLY(Rtemp) NOT_AARCH64(noreg));
1087 }
1088 break;
1089
1090 case access_field_patching_id:
1091 {
1092 __ set_info("access_field_patching", dont_gc_arguments);
1093 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, access_field_patching));
1094 }
1095 break;
1096
1097 case load_klass_patching_id:
1098 {
1099 __ set_info("load_klass_patching", dont_gc_arguments);
1100 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_klass_patching));
1101 }
1102 break;
1103
1104 case load_appendix_patching_id:
1105 {
1106 __ set_info("load_appendix_patching", dont_gc_arguments);
1107 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_appendix_patching));
1108 }
1109 break;
1110
1111 case load_mirror_patching_id:
1112 {
1113 __ set_info("load_mirror_patching", dont_gc_arguments);
1114 oop_maps = generate_patching(sasm, CAST_FROM_FN_PTR(address, move_mirror_patching));
1115 }
1116 break;
1117
1118 case predicate_failed_trap_id:
1119 {
1120 __ set_info("predicate_failed_trap", dont_gc_arguments);
1121
1122 OopMap* oop_map = save_live_registers(sasm);
1123 int call_offset = __ call_RT(noreg, noreg, CAST_FROM_FN_PTR(address, predicate_failed_trap));
1124
1125 oop_maps = new OopMapSet();
1126 oop_maps->add_gc_map(call_offset, oop_map);
1127
1128 restore_live_registers_without_return(sasm);
1129
1130 DeoptimizationBlob* deopt_blob = SharedRuntime::deopt_blob();
1131 assert(deopt_blob != NULL, "deoptimization blob must have been created");
1132 __ jump(deopt_blob->unpack_with_reexecution(), relocInfo::runtime_call_type, Rtemp);
1133 }
1134 break;
1135
1136 default:
1137 {
1138 __ set_info("unimplemented entry", dont_gc_arguments);
1139 STOP("unimplemented entry");
1140 }
1141 break;
1142 }
1143 return oop_maps;
1144 }
1145
1146 #undef __
1147
1148 #ifdef __SOFTFP__
1149 const char *Runtime1::pd_name_for_address(address entry) {
1150
1151 #define FUNCTION_CASE(a, f) \
1152 if ((intptr_t)a == CAST_FROM_FN_PTR(intptr_t, f)) return #f
1153
1154 FUNCTION_CASE(entry, __aeabi_fadd_glibc);
1155 FUNCTION_CASE(entry, __aeabi_fmul);
1156 FUNCTION_CASE(entry, __aeabi_fsub_glibc);
1157 FUNCTION_CASE(entry, __aeabi_fdiv);
1158
1159 // __aeabi_XXXX_glibc: Imported code from glibc soft-fp bundle for calculation accuracy improvement. See CR 6757269.
1160 FUNCTION_CASE(entry, __aeabi_dadd_glibc);
1161 FUNCTION_CASE(entry, __aeabi_dmul);
1162 FUNCTION_CASE(entry, __aeabi_dsub_glibc);
1163 FUNCTION_CASE(entry, __aeabi_ddiv);
1164
1165 FUNCTION_CASE(entry, __aeabi_f2d);
1166 FUNCTION_CASE(entry, __aeabi_d2f);
1167 FUNCTION_CASE(entry, __aeabi_i2f);
1168 FUNCTION_CASE(entry, __aeabi_i2d);
1169 FUNCTION_CASE(entry, __aeabi_f2iz);
1170
1171 FUNCTION_CASE(entry, SharedRuntime::fcmpl);
1172 FUNCTION_CASE(entry, SharedRuntime::fcmpg);
1173 FUNCTION_CASE(entry, SharedRuntime::dcmpl);
1174 FUNCTION_CASE(entry, SharedRuntime::dcmpg);
1175
1176 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmplt);
1177 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmplt);
1178 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmple);
1179 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmple);
1180 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpge);
1181 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpge);
1182 FUNCTION_CASE(entry, SharedRuntime::unordered_fcmpgt);
1183 FUNCTION_CASE(entry, SharedRuntime::unordered_dcmpgt);
1184
1185 FUNCTION_CASE(entry, SharedRuntime::fneg);
1186 FUNCTION_CASE(entry, SharedRuntime::dneg);
1187
1188 FUNCTION_CASE(entry, __aeabi_fcmpeq);
1189 FUNCTION_CASE(entry, __aeabi_fcmplt);
1190 FUNCTION_CASE(entry, __aeabi_fcmple);
1191 FUNCTION_CASE(entry, __aeabi_fcmpge);
1192 FUNCTION_CASE(entry, __aeabi_fcmpgt);
1193
1194 FUNCTION_CASE(entry, __aeabi_dcmpeq);
1195 FUNCTION_CASE(entry, __aeabi_dcmplt);
1196 FUNCTION_CASE(entry, __aeabi_dcmple);
1197 FUNCTION_CASE(entry, __aeabi_dcmpge);
1198 FUNCTION_CASE(entry, __aeabi_dcmpgt);
1199 #undef FUNCTION_CASE
1200 return "";
1201 }
1202 #else // __SOFTFP__
1203 const char *Runtime1::pd_name_for_address(address entry) {
1204 return "<unknown function>";
1205 }
1206 #endif // __SOFTFP__