src/hotspot/cpu/x86/assembler_x86.cpp

rev 49225 : 8199603: Build failures after JDK-8199421 "Add support for vector popcount"
Reviewed-by: XXX

*** 3913,3922 ****
--- 3913,3931 ----
    emit_int8(0x0F);
    emit_int8((unsigned char)0xB8);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
+ void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
+   assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature");
+   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
+   attributes.set_is_evex_instruction();
+   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
+   emit_int8(0x55);
+   emit_int8((unsigned char)(0xC0 | encode));
+ }
+ 
  void Assembler::popf() {
    emit_int8((unsigned char)0x9D);
  }
  
  #ifndef _LP64 // no 32bit push/pop on amd64
*** 8707,8725 ****
    emit_int8((unsigned char)0x0F);
    emit_int8((unsigned char)0xB8);
    emit_int8((unsigned char)(0xC0 | encode));
  }
  
- void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
-   assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature");
-   InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
-   attributes.set_is_evex_instruction();
-   int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
-   emit_int8(0x55);
-   emit_int8((unsigned char)(0xC0 | encode));
- }
- 
  void Assembler::popq(Address dst) {
    InstructionMark im(this);
    prefixq(dst);
    emit_int8((unsigned char)0x8F);
    emit_operand(rax, dst);
--- 8716,8725 ----