389 b(update_cache, eq);
390
391 subs(supers_cnt, supers_cnt, 1);
392
393 #ifndef AARCH64
394 ldr(cur_super, Address(supers_arr, wordSize, pre_indexed), ne);
395 #endif // !AARCH64
396
397 b(loop, ne);
398
399 b(not_subtype);
400
401 bind(update_cache);
402 // Must be equal but missed in cache. Update cache.
403 str(Rsuper_klass, Address(Rsub_klass, Klass::secondary_super_cache_offset()));
404
405 bind(ok_is_subtype);
406 }
407
408
409 // The 1st part of the store check.
410 // Sets card_table_base register.
411 void InterpreterMacroAssembler::store_check_part1(Register card_table_base) {
412 // Check barrier set type (should be card table) and element size
413 BarrierSet* bs = BarrierSet::barrier_set();
414 assert(bs->kind() == BarrierSet::CardTableBarrierSet,
415 "Wrong barrier set kind");
416
417 CardTableBarrierSet* ctbs = barrier_set_cast<CardTableBarrierSet>(bs);
418 CardTable* ct = ctbs->card_table();
419 assert(sizeof(*ct->byte_map_base()) == sizeof(jbyte), "Adjust store check code");
420
421 // Load card table base address.
422
423 /* Performance note.
424
425 There is an alternative way of loading card table base address
426 from thread descriptor, which may look more efficient:
427
428 ldr(card_table_base, Address(Rthread, JavaThread::card_table_base_offset()));
429
430 However, performance measurements of micro benchmarks and specJVM98
431 showed that loading of card table base from thread descriptor is
432 7-18% slower compared to loading of literal embedded into the code.
433 Possible cause is a cache miss (card table base address resides in a
434 rarely accessed area of thread descriptor).
435 */
436 // TODO-AARCH64 Investigate if mov_slow is faster than ldr from Rthread on AArch64
437 mov_address(card_table_base, (address)ct->byte_map_base(), symbolic_Relocation::card_table_reference);
438 }
439
440 // The 2nd part of the store check.
441 void InterpreterMacroAssembler::store_check_part2(Register obj, Register card_table_base, Register tmp) {
442 assert_different_registers(obj, card_table_base, tmp);
443
444 assert(CardTable::dirty_card_val() == 0, "Dirty card value must be 0 due to optimizations.");
445 #ifdef AARCH64
446 add(card_table_base, card_table_base, AsmOperand(obj, lsr, CardTable::card_shift));
447 Address card_table_addr(card_table_base);
448 #else
449 Address card_table_addr(card_table_base, obj, lsr, CardTable::card_shift);
450 #endif
451
452 if (UseCondCardMark) {
453 #if INCLUDE_ALL_GCS
454 if (UseConcMarkSweepGC) {
455 membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreLoad), noreg);
456 }
457 #endif
458 Label already_dirty;
459
460 ldrb(tmp, card_table_addr);
461 cbz(tmp, already_dirty);
462
463 set_card(card_table_base, card_table_addr, tmp);
464 bind(already_dirty);
465
466 } else {
467 #if INCLUDE_ALL_GCS
468 if (UseConcMarkSweepGC && CMSPrecleaningEnabled) {
469 membar(MacroAssembler::Membar_mask_bits(MacroAssembler::StoreStore), noreg);
470 }
471 #endif
472 set_card(card_table_base, card_table_addr, tmp);
473 }
474 }
475
476 void InterpreterMacroAssembler::set_card(Register card_table_base, Address card_table_addr, Register tmp) {
477 #ifdef AARCH64
478 strb(ZR, card_table_addr);
479 #else
480 CardTableBarrierSet* ctbs = barrier_set_cast<CardTableBarrierSet>(BarrierSet::barrier_set());
481 CardTable* ct = ctbs->card_table();
482 if ((((uintptr_t)ct->byte_map_base() & 0xff) == 0)) {
483 // Card table is aligned so the lowest byte of the table address base is zero.
484 // This works only if the code is not saved for later use, possibly
485 // in a context where the base would no longer be aligned.
486 strb(card_table_base, card_table_addr);
487 } else {
488 mov(tmp, 0);
489 strb(tmp, card_table_addr);
490 }
491 #endif // AARCH64
492 }
493
494 //////////////////////////////////////////////////////////////////////////////////
495
496
497 // Java Expression Stack
498
499 void InterpreterMacroAssembler::pop_ptr(Register r) {
500 assert(r != Rstack_top, "unpredictable instruction");
501 ldr(r, Address(Rstack_top, wordSize, post_indexed));
502 }
503
504 void InterpreterMacroAssembler::pop_i(Register r) {
505 assert(r != Rstack_top, "unpredictable instruction");
506 ldr_s32(r, Address(Rstack_top, wordSize, post_indexed));
507 zap_high_non_significant_bits(r);
508 }
509
510 #ifdef AARCH64
511 void InterpreterMacroAssembler::pop_l(Register r) {
512 assert(r != Rstack_top, "unpredictable instruction");
513 ldr(r, Address(Rstack_top, 2*wordSize, post_indexed));
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389 b(update_cache, eq);
390
391 subs(supers_cnt, supers_cnt, 1);
392
393 #ifndef AARCH64
394 ldr(cur_super, Address(supers_arr, wordSize, pre_indexed), ne);
395 #endif // !AARCH64
396
397 b(loop, ne);
398
399 b(not_subtype);
400
401 bind(update_cache);
402 // Must be equal but missed in cache. Update cache.
403 str(Rsuper_klass, Address(Rsub_klass, Klass::secondary_super_cache_offset()));
404
405 bind(ok_is_subtype);
406 }
407
408
409 //////////////////////////////////////////////////////////////////////////////////
410
411
412 // Java Expression Stack
413
414 void InterpreterMacroAssembler::pop_ptr(Register r) {
415 assert(r != Rstack_top, "unpredictable instruction");
416 ldr(r, Address(Rstack_top, wordSize, post_indexed));
417 }
418
419 void InterpreterMacroAssembler::pop_i(Register r) {
420 assert(r != Rstack_top, "unpredictable instruction");
421 ldr_s32(r, Address(Rstack_top, wordSize, post_indexed));
422 zap_high_non_significant_bits(r);
423 }
424
425 #ifdef AARCH64
426 void InterpreterMacroAssembler::pop_l(Register r) {
427 assert(r != Rstack_top, "unpredictable instruction");
428 ldr(r, Address(Rstack_top, 2*wordSize, post_indexed));
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