19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_ARM_GC_SHARED_BARRIERSETASSEMBLER_ARM_HPP
26 #define CPU_ARM_GC_SHARED_BARRIERSETASSEMBLER_ARM_HPP
27
28 #include "asm/macroAssembler.hpp"
29 #include "memory/allocation.hpp"
30 #include "oops/access.hpp"
31
32 class BarrierSetAssembler: public CHeapObj<mtGC> {
33 public:
34 virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop,
35 Register addr, Register count, int callee_saved_regs) {}
36 virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop,
37 Register addr, Register count, Register tmp) {}
38
39 virtual void barrier_stubs_init() {}
40 };
41
42 #endif // CPU_ARM_GC_SHARED_BARRIERSETASSEMBLER_ARM_HPP
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19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_ARM_GC_SHARED_BARRIERSETASSEMBLER_ARM_HPP
26 #define CPU_ARM_GC_SHARED_BARRIERSETASSEMBLER_ARM_HPP
27
28 #include "asm/macroAssembler.hpp"
29 #include "memory/allocation.hpp"
30 #include "oops/access.hpp"
31
32 class BarrierSetAssembler: public CHeapObj<mtGC> {
33 public:
34 virtual void arraycopy_prologue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop,
35 Register addr, Register count, int callee_saved_regs) {}
36 virtual void arraycopy_epilogue(MacroAssembler* masm, DecoratorSet decorators, bool is_oop,
37 Register addr, Register count, Register tmp) {}
38
39 virtual void load_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
40 Register dst, Address src, Register tmp1, Register tmp2, Register tmp3);
41 virtual void store_at(MacroAssembler* masm, DecoratorSet decorators, BasicType type,
42 Address obj, Register new_val, Register tmp1, Register tmp2, Register tmp3, bool is_null);
43
44 virtual void barrier_stubs_init() {}
45 };
46
47 #endif // CPU_ARM_GC_SHARED_BARRIERSETASSEMBLER_ARM_HPP
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