2963 // Valid scale values for addressing modes
2964 operand immI2()
2965 %{
2966 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2967 match(ConI);
2968
2969 format %{ %}
2970 interface(CONST_INTER);
2971 %}
2972
2973 operand immI8()
2974 %{
2975 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2976 match(ConI);
2977
2978 op_cost(5);
2979 format %{ %}
2980 interface(CONST_INTER);
2981 %}
2982
2983 operand immI16()
2984 %{
2985 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2986 match(ConI);
2987
2988 op_cost(10);
2989 format %{ %}
2990 interface(CONST_INTER);
2991 %}
2992
2993 // Int Immediate non-negative
2994 operand immU31()
2995 %{
2996 predicate(n->get_int() >= 0);
2997 match(ConI);
2998
2999 op_cost(0);
3000 format %{ %}
3001 interface(CONST_INTER);
3002 %}
11578 %}
11579
11580 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
11581 %{
11582 match(Set cr (CmpUL op1 (LoadL op2)));
11583
11584 format %{ "cmpq $op1, $op2\t# unsigned" %}
11585 opcode(0x3B); /* Opcode 3B /r */
11586 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11587 ins_pipe(ialu_cr_reg_mem);
11588 %}
11589
11590 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
11591 %{
11592 match(Set cr (CmpUL src zero));
11593
11594 format %{ "testq $src, $src\t# unsigned" %}
11595 opcode(0x85);
11596 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11597 ins_pipe(ialu_cr_reg_imm);
11598 %}
11599
11600 //----------Max and Min--------------------------------------------------------
11601 // Min Instructions
11602
11603 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11604 %{
11605 effect(USE_DEF dst, USE src, USE cr);
11606
11607 format %{ "cmovlgt $dst, $src\t# min" %}
11608 opcode(0x0F, 0x4F);
11609 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11610 ins_pipe(pipe_cmov_reg);
11611 %}
11612
11613
11614 instruct minI_rReg(rRegI dst, rRegI src)
11615 %{
11616 match(Set dst (MinI dst src));
11617
|
2963 // Valid scale values for addressing modes
2964 operand immI2()
2965 %{
2966 predicate(0 <= n->get_int() && (n->get_int() <= 3));
2967 match(ConI);
2968
2969 format %{ %}
2970 interface(CONST_INTER);
2971 %}
2972
2973 operand immI8()
2974 %{
2975 predicate((-0x80 <= n->get_int()) && (n->get_int() < 0x80));
2976 match(ConI);
2977
2978 op_cost(5);
2979 format %{ %}
2980 interface(CONST_INTER);
2981 %}
2982
2983 operand immU8()
2984 %{
2985 predicate((0 <= n->get_int()) && (n->get_int() <= 255));
2986 match(ConI);
2987
2988 op_cost(5);
2989 format %{ %}
2990 interface(CONST_INTER);
2991 %}
2992
2993 operand immI16()
2994 %{
2995 predicate((-32768 <= n->get_int()) && (n->get_int() <= 32767));
2996 match(ConI);
2997
2998 op_cost(10);
2999 format %{ %}
3000 interface(CONST_INTER);
3001 %}
3002
3003 // Int Immediate non-negative
3004 operand immU31()
3005 %{
3006 predicate(n->get_int() >= 0);
3007 match(ConI);
3008
3009 op_cost(0);
3010 format %{ %}
3011 interface(CONST_INTER);
3012 %}
11588 %}
11589
11590 instruct compUL_rReg_mem(rFlagsRegU cr, rRegL op1, memory op2)
11591 %{
11592 match(Set cr (CmpUL op1 (LoadL op2)));
11593
11594 format %{ "cmpq $op1, $op2\t# unsigned" %}
11595 opcode(0x3B); /* Opcode 3B /r */
11596 ins_encode(REX_reg_mem_wide(op1, op2), OpcP, reg_mem(op1, op2));
11597 ins_pipe(ialu_cr_reg_mem);
11598 %}
11599
11600 instruct testUL_reg(rFlagsRegU cr, rRegL src, immL0 zero)
11601 %{
11602 match(Set cr (CmpUL src zero));
11603
11604 format %{ "testq $src, $src\t# unsigned" %}
11605 opcode(0x85);
11606 ins_encode(REX_reg_reg_wide(src, src), OpcP, reg_reg(src, src));
11607 ins_pipe(ialu_cr_reg_imm);
11608 %}
11609
11610 instruct compUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm)
11611 %{
11612 match(Set cr (CmpI (LoadUB mem) imm));
11613
11614 ins_cost(125);
11615 format %{ "cmpb $mem, $imm" %}
11616 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
11617 ins_pipe(ialu_cr_reg_mem);
11618 %}
11619
11620 instruct compB_mem_imm(rFlagsReg cr, memory mem, immI8 imm)
11621 %{
11622 match(Set cr (CmpI (LoadB mem) imm));
11623
11624 ins_cost(125);
11625 format %{ "cmpb $mem, $imm" %}
11626 ins_encode %{ __ cmpb($mem$$Address, $imm$$constant); %}
11627 ins_pipe(ialu_cr_reg_mem);
11628 %}
11629
11630 instruct testUB_mem_imm(rFlagsReg cr, memory mem, immU8 imm, immI0 zero)
11631 %{
11632 match(Set cr (CmpI (AndI (LoadUB mem) imm) zero));
11633
11634 ins_cost(125);
11635 format %{ "testb $mem, $imm" %}
11636 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
11637 ins_pipe(ialu_cr_reg_mem);
11638 %}
11639
11640 instruct testB_mem_imm(rFlagsReg cr, memory mem, immI8 imm, immI0 zero)
11641 %{
11642 match(Set cr (CmpI (AndI (LoadB mem) imm) zero));
11643
11644 ins_cost(125);
11645 format %{ "testb $mem, $imm" %}
11646 ins_encode %{ __ testb($mem$$Address, $imm$$constant); %}
11647 ins_pipe(ialu_cr_reg_mem);
11648 %}
11649
11650 //----------Max and Min--------------------------------------------------------
11651 // Min Instructions
11652
11653 instruct cmovI_reg_g(rRegI dst, rRegI src, rFlagsReg cr)
11654 %{
11655 effect(USE_DEF dst, USE src, USE cr);
11656
11657 format %{ "cmovlgt $dst, $src\t# min" %}
11658 opcode(0x0F, 0x4F);
11659 ins_encode(REX_reg_reg(dst, src), OpcP, OpcS, reg_reg(dst, src));
11660 ins_pipe(pipe_cmov_reg);
11661 %}
11662
11663
11664 instruct minI_rReg(rRegI dst, rRegI src)
11665 %{
11666 match(Set dst (MinI dst src));
11667
|