116     const Type *dt = phase->type(dividend);
 117     const TypeInt *dti = dt->isa_int();
 118     if (dti && dti->_lo >= 0) {
 119       // we don't need to round a positive dividend
 120       needs_rounding = false;
 121     } else if( dividend->Opcode() == Op_AndI ) {
 122       // An AND mask of sufficient size clears the low bits and
 123       // I can avoid rounding.
 124       const TypeInt *andconi_t = phase->type( dividend->in(2) )->isa_int();
 125       if( andconi_t && andconi_t->is_con() ) {
 126         jint andconi = andconi_t->get_con();
 127         if( andconi < 0 && is_power_of_2(-andconi) && (-andconi) >= d ) {
 128           if( (-andconi) == d ) // Remove AND if it clears bits which will be shifted
 129             dividend = dividend->in(1);
 130           needs_rounding = false;
 131         }
 132       }
 133     }
 134 
 135     // Add rounding to the shift to handle the sign bit
 136     int l = log2_intptr(d-1)+1;
 137     if (needs_rounding) {
 138       // Divide-by-power-of-2 can be made into a shift, but you have to do
 139       // more math for the rounding.  You need to add 0 for positive
 140       // numbers, and "i-1" for negative numbers.  Example: i=4, so the
 141       // shift is by 2.  You need to add 3 to negative dividends and 0 to
 142       // positive ones.  So (-7+3)>>2 becomes -1, (-4+3)>>2 becomes -1,
 143       // (-2+3)>>2 becomes 0, etc.
 144 
 145       // Compute 0 or -1, based on sign bit
 146       Node *sign = phase->transform(new RShiftINode(dividend, phase->intcon(N - 1)));
 147       // Mask sign bit to the low sign bits
 148       Node *round = phase->transform(new URShiftINode(sign, phase->intcon(N - l)));
 149       // Round up before shifting
 150       dividend = phase->transform(new AddINode(dividend, round));
 151     }
 152 
 153     // Shift for division
 154     q = new RShiftINode(dividend, phase->intcon(l));
 155 
 156     if (!d_pos) {

 116     const Type *dt = phase->type(dividend);
 117     const TypeInt *dti = dt->isa_int();
 118     if (dti && dti->_lo >= 0) {
 119       // we don't need to round a positive dividend
 120       needs_rounding = false;
 121     } else if( dividend->Opcode() == Op_AndI ) {
 122       // An AND mask of sufficient size clears the low bits and
 123       // I can avoid rounding.
 124       const TypeInt *andconi_t = phase->type( dividend->in(2) )->isa_int();
 125       if( andconi_t && andconi_t->is_con() ) {
 126         jint andconi = andconi_t->get_con();
 127         if( andconi < 0 && is_power_of_2(-andconi) && (-andconi) >= d ) {
 128           if( (-andconi) == d ) // Remove AND if it clears bits which will be shifted
 129             dividend = dividend->in(1);
 130           needs_rounding = false;
 131         }
 132       }
 133     }
 134 
 135     // Add rounding to the shift to handle the sign bit
 136     int l = log2_jint(d-1)+1;
 137     if (needs_rounding) {
 138       // Divide-by-power-of-2 can be made into a shift, but you have to do
 139       // more math for the rounding.  You need to add 0 for positive
 140       // numbers, and "i-1" for negative numbers.  Example: i=4, so the
 141       // shift is by 2.  You need to add 3 to negative dividends and 0 to
 142       // positive ones.  So (-7+3)>>2 becomes -1, (-4+3)>>2 becomes -1,
 143       // (-2+3)>>2 becomes 0, etc.
 144 
 145       // Compute 0 or -1, based on sign bit
 146       Node *sign = phase->transform(new RShiftINode(dividend, phase->intcon(N - 1)));
 147       // Mask sign bit to the low sign bits
 148       Node *round = phase->transform(new URShiftINode(sign, phase->intcon(N - l)));
 149       // Round up before shifting
 150       dividend = phase->transform(new AddINode(dividend, round));
 151     }
 152 
 153     // Shift for division
 154     q = new RShiftINode(dividend, phase->intcon(l));
 155 
 156     if (!d_pos) {