--- old/src/cpu/sparc/vm/vm_version_sparc.cpp	2017-07-20 12:26:13.579887000 +0530
+++ new/src/cpu/sparc/vm/vm_version_sparc.cpp	2017-07-20 12:26:13.451887351 +0530
@@ -140,10 +140,17 @@
     if (is_niagara_plus()) {
       if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
           FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
+        if (!has_sparc5_instr()) {
         // Use BIS instruction for TLAB allocation prefetch.
-        FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
-        if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
-          FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
+          // on Niagara plus processors other than those based on CoreS4
+          FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
+        } else {
+          // On CoreS4 processors use prefetch instruction
+          // to avoid partial RAW issue, also use prefetch style 3
+          FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
+          if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
+            FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
+          }
         }
         if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
           // Use smaller prefetch distance with BIS