1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/macroAssembler.inline.hpp"
27 #include "memory/resourceArea.hpp"
28 #include "runtime/java.hpp"
29 #include "runtime/stubCodeGenerator.hpp"
30 #include "vm_version_sparc.hpp"
31 #ifdef TARGET_OS_FAMILY_linux
32 # include "os_linux.inline.hpp"
33 #endif
34 #ifdef TARGET_OS_FAMILY_solaris
35 # include "os_solaris.inline.hpp"
36 #endif
37
38 int VM_Version::_features = VM_Version::unknown_m;
39 const char* VM_Version::_features_str = "";
40 unsigned int VM_Version::_L2_data_cache_line_size = 0;
41
42 void VM_Version::initialize() {
43
44 assert(_features != VM_Version::unknown_m, "System pre-initialization is not complete.");
45 guarantee(VM_Version::has_v9(), "only SPARC v9 is supported");
46
47 PrefetchCopyIntervalInBytes = prefetch_copy_interval_in_bytes();
48 PrefetchScanIntervalInBytes = prefetch_scan_interval_in_bytes();
49 PrefetchFieldsAhead = prefetch_fields_ahead();
50
51 assert(0 <= AllocatePrefetchInstr && AllocatePrefetchInstr <= 1, "invalid value");
52 if( AllocatePrefetchInstr < 0 ) AllocatePrefetchInstr = 0;
53 if( AllocatePrefetchInstr > 1 ) AllocatePrefetchInstr = 0;
54
55 // Allocation prefetch settings
56 intx cache_line_size = prefetch_data_size();
57 if( cache_line_size > AllocatePrefetchStepSize )
58 AllocatePrefetchStepSize = cache_line_size;
59
60 assert(AllocatePrefetchLines > 0, "invalid value");
61 if( AllocatePrefetchLines < 1 ) // set valid value in product VM
62 AllocatePrefetchLines = 3;
63 assert(AllocateInstancePrefetchLines > 0, "invalid value");
64 if( AllocateInstancePrefetchLines < 1 ) // set valid value in product VM
65 AllocateInstancePrefetchLines = 1;
66
67 AllocatePrefetchDistance = allocate_prefetch_distance();
68 AllocatePrefetchStyle = allocate_prefetch_style();
69
70 assert((AllocatePrefetchDistance % AllocatePrefetchStepSize) == 0 &&
71 (AllocatePrefetchDistance > 0), "invalid value");
72 if ((AllocatePrefetchDistance % AllocatePrefetchStepSize) != 0 ||
73 (AllocatePrefetchDistance <= 0)) {
74 AllocatePrefetchDistance = AllocatePrefetchStepSize;
75 }
76
77 if (AllocatePrefetchStyle == 3 && (!has_blk_init() || cache_line_size <= 0)) {
78 warning("BIS instructions are not available on this CPU");
79 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 1);
80 }
81
82 assert(ArraycopySrcPrefetchDistance < 4096, "invalid value");
83 if (ArraycopySrcPrefetchDistance >= 4096)
84 ArraycopySrcPrefetchDistance = 4064;
85 assert(ArraycopyDstPrefetchDistance < 4096, "invalid value");
86 if (ArraycopyDstPrefetchDistance >= 4096)
87 ArraycopyDstPrefetchDistance = 4064;
88
89 UseSSE = 0; // Only on x86 and x64
90
91 _supports_cx8 = has_v9();
92 _supports_atomic_getset4 = true; // swap instruction
93
94 // There are Fujitsu Sparc64 CPUs which support blk_init as well so
95 // we have to take this check out of the 'is_niagara()' block below.
96 if (has_blk_init()) {
97 // When using CMS or G1, we cannot use memset() in BOT updates
98 // because the sun4v/CMT version in libc_psr uses BIS which
99 // exposes "phantom zeros" to concurrent readers. See 6948537.
100 if (FLAG_IS_DEFAULT(UseMemSetInBOT) && (UseConcMarkSweepGC || UseG1GC)) {
101 FLAG_SET_DEFAULT(UseMemSetInBOT, false);
102 }
103 // Issue a stern warning if the user has explicitly set
104 // UseMemSetInBOT (it is known to cause issues), but allow
105 // use for experimentation and debugging.
106 if (UseConcMarkSweepGC || UseG1GC) {
107 if (UseMemSetInBOT) {
108 assert(!FLAG_IS_DEFAULT(UseMemSetInBOT), "Error");
109 warning("Experimental flag -XX:+UseMemSetInBOT is known to cause instability"
110 " on sun4v; please understand that you are using at your own risk!");
111 }
112 }
113 }
114
115 if (is_niagara()) {
116 // Indirect branch is the same cost as direct
117 if (FLAG_IS_DEFAULT(UseInlineCaches)) {
118 FLAG_SET_DEFAULT(UseInlineCaches, false);
119 }
120 // Align loops on a single instruction boundary.
121 if (FLAG_IS_DEFAULT(OptoLoopAlignment)) {
122 FLAG_SET_DEFAULT(OptoLoopAlignment, 4);
123 }
124 #ifdef _LP64
125 // 32-bit oops don't make sense for the 64-bit VM on sparc
126 // since the 32-bit VM has the same registers and smaller objects.
127 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
128 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
129 #endif // _LP64
130 #ifdef COMPILER2
131 // Indirect branch is the same cost as direct
132 if (FLAG_IS_DEFAULT(UseJumpTables)) {
133 FLAG_SET_DEFAULT(UseJumpTables, true);
134 }
135 // Single-issue, so entry and loop tops are
136 // aligned on a single instruction boundary
137 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
138 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
139 }
140 if (is_niagara_plus()) {
141 if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
142 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
143 if (!has_sparc5_instr()) {
144 // Use BIS instruction for TLAB allocation prefetch.
145 // on Niagara plus processors other than those based on CoreS4
146 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
147 } else {
148 // On CoreS4 processors use prefetch instruction
149 // to avoid partial RAW issue, also use prefetch style 3
150 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
151 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
152 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
153 }
154 }
155 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
156 // Use smaller prefetch distance with BIS
157 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
158 }
159 }
160 if (is_T4()) {
161 // Double number of prefetched cache lines on T4
162 // since L2 cache line size is smaller (32 bytes).
163 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
164 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
165 }
166 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
167 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
168 }
169 }
170 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
171 // Use different prefetch distance without BIS
172 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
173 }
174 if (AllocatePrefetchInstr == 1) {
175
176 // Use allocation prefetch style 3 because BIS instructions
177 // require aligned memory addresses.
178 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
179
180 // Need a space at the end of TLAB for BIS since it
181 // will fault when accessing memory outside of heap.
182
183 // +1 for rounding up to next cache line, +1 to be safe
184 int lines = AllocatePrefetchLines + 2;
185 int step_size = AllocatePrefetchStepSize;
186 int distance = AllocatePrefetchDistance;
187 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
188 }
189 }
190 #endif
191 }
192
193 // Use hardware population count instruction if available.
194 if (has_hardware_popc()) {
195 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
196 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
197 }
198 } else if (UsePopCountInstruction) {
199 warning("POPC instruction is not available on this CPU");
200 FLAG_SET_DEFAULT(UsePopCountInstruction, false);
201 }
202
203 // T4 and newer Sparc cpus have new compare and branch instruction.
204 if (has_cbcond()) {
205 if (FLAG_IS_DEFAULT(UseCBCond)) {
206 FLAG_SET_DEFAULT(UseCBCond, true);
207 }
208 } else if (UseCBCond) {
209 warning("CBCOND instruction is not available on this CPU");
210 FLAG_SET_DEFAULT(UseCBCond, false);
211 }
212
213 assert(BlockZeroingLowLimit > 0, "invalid value");
214 if (has_block_zeroing() && cache_line_size > 0) {
215 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
216 FLAG_SET_DEFAULT(UseBlockZeroing, true);
217 }
218 } else if (UseBlockZeroing) {
219 warning("BIS zeroing instructions are not available on this CPU");
220 FLAG_SET_DEFAULT(UseBlockZeroing, false);
221 }
222
223 assert(BlockCopyLowLimit > 0, "invalid value");
224 if (has_block_zeroing() && cache_line_size > 0) { // has_blk_init() && is_T4(): core's local L2 cache
225 if (FLAG_IS_DEFAULT(UseBlockCopy)) {
226 FLAG_SET_DEFAULT(UseBlockCopy, true);
227 }
228 } else if (UseBlockCopy) {
229 warning("BIS instructions are not available or expensive on this CPU");
230 FLAG_SET_DEFAULT(UseBlockCopy, false);
231 }
232
233 #ifdef COMPILER2
234 // T4 and newer Sparc cpus have fast RDPC.
235 if (has_fast_rdpc() && FLAG_IS_DEFAULT(UseRDPCForConstantTableBase)) {
236 FLAG_SET_DEFAULT(UseRDPCForConstantTableBase, true);
237 }
238
239 // Currently not supported anywhere.
240 FLAG_SET_DEFAULT(UseFPUForSpilling, false);
241
242 MaxVectorSize = 8;
243
244 assert((InteriorEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
245 #endif
246
247 assert((CodeEntryAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
248 assert((OptoLoopAlignment % relocInfo::addr_unit()) == 0, "alignment is not a multiple of NOP size");
249
250 char buf[512];
251 jio_snprintf(buf, sizeof(buf), "%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s%s",
252 (has_v9() ? ", v9" : (has_v8() ? ", v8" : "")),
253 (has_hardware_popc() ? ", popc" : ""),
254 (has_vis1() ? ", vis1" : ""),
255 (has_vis2() ? ", vis2" : ""),
256 (has_vis3() ? ", vis3" : ""),
257 (has_blk_init() ? ", blk_init" : ""),
258 (has_cbcond() ? ", cbcond" : ""),
259 (has_aes() ? ", aes" : ""),
260 (has_sha1() ? ", sha1" : ""),
261 (has_sha256() ? ", sha256" : ""),
262 (has_sha512() ? ", sha512" : ""),
263 (is_ultra3() ? ", ultra3" : ""),
264 (has_sparc5_instr() ? ", sparc5" : ""),
265 (is_sun4v() ? ", sun4v" : ""),
266 (is_niagara_plus() ? ", niagara_plus" : (is_niagara() ? ", niagara" : "")),
267 (is_sparc64() ? ", sparc64" : ""),
268 (!has_hardware_mul32() ? ", no-mul32" : ""),
269 (!has_hardware_div32() ? ", no-div32" : ""),
270 (!has_hardware_fsmuld() ? ", no-fsmuld" : ""));
271
272 // buf is started with ", " or is empty
273 _features_str = strdup(strlen(buf) > 2 ? buf + 2 : buf);
274
275 // UseVIS is set to the smallest of what hardware supports and what
276 // the command line requires. I.e., you cannot set UseVIS to 3 on
277 // older UltraSparc which do not support it.
278 if (UseVIS > 3) UseVIS=3;
279 if (UseVIS < 0) UseVIS=0;
280 if (!has_vis3()) // Drop to 2 if no VIS3 support
281 UseVIS = MIN2((intx)2,UseVIS);
282 if (!has_vis2()) // Drop to 1 if no VIS2 support
283 UseVIS = MIN2((intx)1,UseVIS);
284 if (!has_vis1()) // Drop to 0 if no VIS1 support
285 UseVIS = 0;
286
287 // SPARC T4 and above should have support for AES instructions
288 if (has_aes()) {
289 if (UseVIS > 2) { // AES intrinsics use MOVxTOd/MOVdTOx which are VIS3
290 if (FLAG_IS_DEFAULT(UseAES)) {
291 FLAG_SET_DEFAULT(UseAES, true);
292 }
293 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
294 FLAG_SET_DEFAULT(UseAESIntrinsics, true);
295 }
296 // we disable both the AES flags if either of them is disabled on the command line
297 if (!UseAES || !UseAESIntrinsics) {
298 FLAG_SET_DEFAULT(UseAES, false);
299 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
300 }
301 } else {
302 if (UseAES || UseAESIntrinsics) {
303 warning("SPARC AES intrinsics require VIS3 instruction support. Intrinsics will be disabled.");
304 if (UseAES) {
305 FLAG_SET_DEFAULT(UseAES, false);
306 }
307 if (UseAESIntrinsics) {
308 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
309 }
310 }
311 }
312 } else if (UseAES || UseAESIntrinsics) {
313 warning("AES instructions are not available on this CPU");
314 if (UseAES) {
315 FLAG_SET_DEFAULT(UseAES, false);
316 }
317 if (UseAESIntrinsics) {
318 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
319 }
320 }
321
322 // SHA1, SHA256, and SHA512 instructions were added to SPARC T-series at different times
323 if (has_sha1() || has_sha256() || has_sha512()) {
324 if (UseVIS > 0) { // SHA intrinsics use VIS1 instructions
325 if (FLAG_IS_DEFAULT(UseSHA)) {
326 FLAG_SET_DEFAULT(UseSHA, true);
327 }
328 } else {
329 if (UseSHA) {
330 warning("SPARC SHA intrinsics require VIS1 instruction support. Intrinsics will be disabled.");
331 FLAG_SET_DEFAULT(UseSHA, false);
332 }
333 }
334 } else if (UseSHA) {
335 warning("SHA instructions are not available on this CPU");
336 FLAG_SET_DEFAULT(UseSHA, false);
337 }
338
339 if (!UseSHA) {
340 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
341 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
342 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
343 } else {
344 if (has_sha1()) {
345 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
346 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
347 }
348 } else if (UseSHA1Intrinsics) {
349 warning("SHA1 instruction is not available on this CPU.");
350 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
351 }
352 if (has_sha256()) {
353 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
354 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
355 }
356 } else if (UseSHA256Intrinsics) {
357 warning("SHA256 instruction (for SHA-224 and SHA-256) is not available on this CPU.");
358 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
359 }
360
361 if (has_sha512()) {
362 if (FLAG_IS_DEFAULT(UseSHA512Intrinsics)) {
363 FLAG_SET_DEFAULT(UseSHA512Intrinsics, true);
364 }
365 } else if (UseSHA512Intrinsics) {
366 warning("SHA512 instruction (for SHA-384 and SHA-512) is not available on this CPU.");
367 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
368 }
369 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
370 FLAG_SET_DEFAULT(UseSHA, false);
371 }
372 }
373
374 if (FLAG_IS_DEFAULT(ContendedPaddingWidth) &&
375 (cache_line_size > ContendedPaddingWidth))
376 ContendedPaddingWidth = cache_line_size;
377
378 #ifndef PRODUCT
379 if (PrintMiscellaneous && Verbose) {
380 tty->print_cr("L1 data cache line size: %u", L1_data_cache_line_size());
381 tty->print_cr("L2 data cache line size: %u", L2_data_cache_line_size());
382 tty->print("Allocation");
383 if (AllocatePrefetchStyle <= 0) {
384 tty->print_cr(": no prefetching");
385 } else {
386 tty->print(" prefetching: ");
387 if (AllocatePrefetchInstr == 0) {
388 tty->print("PREFETCH");
389 } else if (AllocatePrefetchInstr == 1) {
390 tty->print("BIS");
391 }
392 if (AllocatePrefetchLines > 1) {
393 tty->print_cr(" at distance %d, %d lines of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchLines, (int) AllocatePrefetchStepSize);
394 } else {
395 tty->print_cr(" at distance %d, one line of %d bytes", (int) AllocatePrefetchDistance, (int) AllocatePrefetchStepSize);
396 }
397 }
398 if (PrefetchCopyIntervalInBytes > 0) {
399 tty->print_cr("PrefetchCopyIntervalInBytes %d", (int) PrefetchCopyIntervalInBytes);
400 }
401 if (PrefetchScanIntervalInBytes > 0) {
402 tty->print_cr("PrefetchScanIntervalInBytes %d", (int) PrefetchScanIntervalInBytes);
403 }
404 if (PrefetchFieldsAhead > 0) {
405 tty->print_cr("PrefetchFieldsAhead %d", (int) PrefetchFieldsAhead);
406 }
407 if (ContendedPaddingWidth > 0) {
408 tty->print_cr("ContendedPaddingWidth %d", (int) ContendedPaddingWidth);
409 }
410 }
411 #endif // PRODUCT
412 }
413
414 void VM_Version::print_features() {
415 tty->print_cr("Version:%s", cpu_features());
416 }
417
418 int VM_Version::determine_features() {
419 if (UseV8InstrsOnly) {
420 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-V8");)
421 return generic_v8_m;
422 }
423
424 int features = platform_features(unknown_m); // platform_features() is os_arch specific
425
426 if (features == unknown_m) {
427 features = generic_v9_m;
428 warning("Cannot recognize SPARC version. Default to V9");
429 }
430
431 assert(is_T_family(features) == is_niagara(features), "Niagara should be T series");
432 if (UseNiagaraInstrs) { // Force code generation for Niagara
433 if (is_T_family(features)) {
434 // Happy to accomodate...
435 } else {
436 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Niagara");)
437 features |= T_family_m;
438 }
439 } else {
440 if (is_T_family(features) && !FLAG_IS_DEFAULT(UseNiagaraInstrs)) {
441 NOT_PRODUCT(if (PrintMiscellaneous && Verbose) tty->print_cr("Version is Forced-Not-Niagara");)
442 features &= ~(T_family_m | T1_model_m);
443 } else {
444 // Happy to accomodate...
445 }
446 }
447
448 return features;
449 }
450
451 static int saved_features = 0;
452
453 void VM_Version::allow_all() {
454 saved_features = _features;
455 _features = all_features_m;
456 }
457
458 void VM_Version::revert() {
459 _features = saved_features;
460 }
461
462 unsigned int VM_Version::calc_parallel_worker_threads() {
463 unsigned int result;
464 if (is_M_series() || is_S_series()) {
465 // for now, use same gc thread calculation for M-series and S-series as for
466 // niagara-plus. In future, we may want to tweak parameters for
467 // nof_parallel_worker_thread
468 result = nof_parallel_worker_threads(5, 16, 8);
469 } else if (is_niagara_plus()) {
470 result = nof_parallel_worker_threads(5, 16, 8);
471 } else {
472 result = nof_parallel_worker_threads(5, 8, 8);
473 }
474 return result;
475 }
476
477
478 int VM_Version::parse_features(const char* implementation) {
479 int features = unknown_m;
480 // Convert to UPPER case before compare.
481 char* impl = os::strdup(implementation);
482
483 for (int i = 0; impl[i] != 0; i++)
484 impl[i] = (char)toupper((uint)impl[i]);
485
486 if (strstr(impl, "SPARC64") != NULL) {
487 features |= sparc64_family_m;
488 } else if (strstr(impl, "SPARC-M") != NULL) {
489 // M-series SPARC is based on T-series.
490 features |= (M_family_m | T_family_m);
491 } else if (strstr(impl, "SPARC-S") != NULL) {
492 // S-series SPARC is based on T-series.
493 features |= (S_family_m | T_family_m);
494 } else if (strstr(impl, "SPARC-T") != NULL) {
495 features |= T_family_m;
496 if (strstr(impl, "SPARC-T1") != NULL) {
497 features |= T1_model_m;
498 }
499 } else if (strstr(impl, "SUN4V-CPU") != NULL) {
500 // Generic or migration class LDOM
501 features |= T_family_m;
502 } else {
503 #ifndef PRODUCT
504 warning("Failed to parse CPU implementation = '%s'", impl);
505 #endif
506 }
507 os::free((void*)impl);
508 return features;
509 }