src/share/vm/opto/macro.cpp

*** 1773,1783 ****
        needgc_false = pf_region;
        contended_phi_rawmem = pf_phi_rawmem;
        i_o = pf_phi_abio;
     } else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
        // Insert a prefetch for each allocation.
!       // This code is used for Sparc with BIS.
        Node *pf_region = new (C) RegionNode(3);
        Node *pf_phi_rawmem = new (C) PhiNode( pf_region, Type::MEMORY,
                                               TypeRawPtr::BOTTOM );
  
        // Generate several prefetch instructions.
--- 1773,1783 ----
        needgc_false = pf_region;
        contended_phi_rawmem = pf_phi_rawmem;
        i_o = pf_phi_abio;
     } else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
        // Insert a prefetch for each allocation.
!       // This code is used to generate 1 prefetch instruction per cache line.
        Node *pf_region = new (C) RegionNode(3);
        Node *pf_phi_rawmem = new (C) PhiNode( pf_region, Type::MEMORY,
                                               TypeRawPtr::BOTTOM );
  
        // Generate several prefetch instructions.
*** 1789,1798 ****
--- 1789,1800 ----
        Node *cache_adr = new (C) AddPNode(old_eden_top, old_eden_top,
                                              _igvn.MakeConX(distance));
        transform_later(cache_adr);
        cache_adr = new (C) CastP2XNode(needgc_false, cache_adr);
        transform_later(cache_adr);
+       // Address is aligned to execute prefetch to the beginning of cache line size
+       // (it is important when BIS instruction is used on SPARC as prefetch).
        Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1));
        cache_adr = new (C) AndXNode(cache_adr, mask);
        transform_later(cache_adr);
        cache_adr = new (C) CastX2PNode(cache_adr);
        transform_later(cache_adr);