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src/share/vm/opto/macro.cpp

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1758         distance += step_size;
1759         i_o = prefetch;
1760       }
1761       pf_phi_abio->set_req( pf_path, i_o );
1762 
1763       pf_region->init_req( fall_in_path, need_pf_false );
1764       pf_region->init_req( pf_path, need_pf_true );
1765 
1766       pf_phi_rawmem->init_req( fall_in_path, contended_phi_rawmem );
1767       pf_phi_rawmem->init_req( pf_path, store_new_wmt );
1768 
1769       transform_later(pf_region);
1770       transform_later(pf_phi_rawmem);
1771       transform_later(pf_phi_abio);
1772 
1773       needgc_false = pf_region;
1774       contended_phi_rawmem = pf_phi_rawmem;
1775       i_o = pf_phi_abio;
1776    } else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
1777       // Insert a prefetch for each allocation.
1778       // This code is used for Sparc with BIS.
1779       Node *pf_region = new (C) RegionNode(3);
1780       Node *pf_phi_rawmem = new (C) PhiNode( pf_region, Type::MEMORY,
1781                                              TypeRawPtr::BOTTOM );
1782 
1783       // Generate several prefetch instructions.
1784       uint lines = (length != NULL) ? AllocatePrefetchLines : AllocateInstancePrefetchLines;
1785       uint step_size = AllocatePrefetchStepSize;
1786       uint distance = AllocatePrefetchDistance;
1787 
1788       // Next cache address.
1789       Node *cache_adr = new (C) AddPNode(old_eden_top, old_eden_top,
1790                                             _igvn.MakeConX(distance));
1791       transform_later(cache_adr);
1792       cache_adr = new (C) CastP2XNode(needgc_false, cache_adr);
1793       transform_later(cache_adr);


1794       Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1));
1795       cache_adr = new (C) AndXNode(cache_adr, mask);
1796       transform_later(cache_adr);
1797       cache_adr = new (C) CastX2PNode(cache_adr);
1798       transform_later(cache_adr);
1799 
1800       // Prefetch
1801       Node *prefetch = new (C) PrefetchAllocationNode( contended_phi_rawmem, cache_adr );
1802       prefetch->set_req(0, needgc_false);
1803       transform_later(prefetch);
1804       contended_phi_rawmem = prefetch;
1805       Node *prefetch_adr;
1806       distance = step_size;
1807       for ( uint i = 1; i < lines; i++ ) {
1808         prefetch_adr = new (C) AddPNode( cache_adr, cache_adr,
1809                                             _igvn.MakeConX(distance) );
1810         transform_later(prefetch_adr);
1811         prefetch = new (C) PrefetchAllocationNode( contended_phi_rawmem, prefetch_adr );
1812         transform_later(prefetch);
1813         distance += step_size;




1758         distance += step_size;
1759         i_o = prefetch;
1760       }
1761       pf_phi_abio->set_req( pf_path, i_o );
1762 
1763       pf_region->init_req( fall_in_path, need_pf_false );
1764       pf_region->init_req( pf_path, need_pf_true );
1765 
1766       pf_phi_rawmem->init_req( fall_in_path, contended_phi_rawmem );
1767       pf_phi_rawmem->init_req( pf_path, store_new_wmt );
1768 
1769       transform_later(pf_region);
1770       transform_later(pf_phi_rawmem);
1771       transform_later(pf_phi_abio);
1772 
1773       needgc_false = pf_region;
1774       contended_phi_rawmem = pf_phi_rawmem;
1775       i_o = pf_phi_abio;
1776    } else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
1777       // Insert a prefetch for each allocation.
1778       // This code is used to generate 1 prefetch instruction per cache line.
1779       Node *pf_region = new (C) RegionNode(3);
1780       Node *pf_phi_rawmem = new (C) PhiNode( pf_region, Type::MEMORY,
1781                                              TypeRawPtr::BOTTOM );
1782 
1783       // Generate several prefetch instructions.
1784       uint lines = (length != NULL) ? AllocatePrefetchLines : AllocateInstancePrefetchLines;
1785       uint step_size = AllocatePrefetchStepSize;
1786       uint distance = AllocatePrefetchDistance;
1787 
1788       // Next cache address.
1789       Node *cache_adr = new (C) AddPNode(old_eden_top, old_eden_top,
1790                                             _igvn.MakeConX(distance));
1791       transform_later(cache_adr);
1792       cache_adr = new (C) CastP2XNode(needgc_false, cache_adr);
1793       transform_later(cache_adr);
1794       // Address is aligned to execute prefetch to the beginning of cache line size
1795       // (it is important when BIS instruction is used on SPARC as prefetch).
1796       Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1));
1797       cache_adr = new (C) AndXNode(cache_adr, mask);
1798       transform_later(cache_adr);
1799       cache_adr = new (C) CastX2PNode(cache_adr);
1800       transform_later(cache_adr);
1801 
1802       // Prefetch
1803       Node *prefetch = new (C) PrefetchAllocationNode( contended_phi_rawmem, cache_adr );
1804       prefetch->set_req(0, needgc_false);
1805       transform_later(prefetch);
1806       contended_phi_rawmem = prefetch;
1807       Node *prefetch_adr;
1808       distance = step_size;
1809       for ( uint i = 1; i < lines; i++ ) {
1810         prefetch_adr = new (C) AddPNode( cache_adr, cache_adr,
1811                                             _igvn.MakeConX(distance) );
1812         transform_later(prefetch_adr);
1813         prefetch = new (C) PrefetchAllocationNode( contended_phi_rawmem, prefetch_adr );
1814         transform_later(prefetch);
1815         distance += step_size;


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