src/cpu/sparc/vm/vm_version_sparc.cpp

*** 1,7 ****
  /*
!  * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
--- 1,7 ----
  /*
!  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
*** 138,151 ****
        FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
      }
      if (is_niagara_plus()) {
        if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
            FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
!         // Use BIS instruction for TLAB allocation prefetch.
!         FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
          if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
!           FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
          }
          if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
            // Use smaller prefetch distance with BIS
            FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
          }
--- 138,158 ----
        FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
      }
      if (is_niagara_plus()) {
        if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
            FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
!         if (!has_sparc5_instr()) {
!           // Use BIS instruction for TLAB allocation prefetch
!           // on Niagara plus processors other than those based on CoreS4.
!           FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
!         } else {
!           // On CoreS4 processors use prefetch instruction
!           // to avoid partial RAW issue, also use prefetch style 3
!           FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
            if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
!             FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
!           }
          }
          if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
            // Use smaller prefetch distance with BIS
            FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
          }
*** 163,172 ****
--- 170,184 ----
        if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
          // Use different prefetch distance without BIS
          FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
        }
        if (AllocatePrefetchInstr == 1) {
+ 
+         // Use allocation prefetch style 3 because BIS instructions
+         // require aligned memory addresses.
+         FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
+ 
          // Need a space at the end of TLAB for BIS since it
          // will fault when accessing memory outside of heap.
  
          // +1 for rounding up to next cache line, +1 to be safe
          int lines = AllocatePrefetchLines + 2;