1 /*
2 * Copyright (c) 1997, 2014, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
123 }
124 #ifdef _LP64
125 // 32-bit oops don't make sense for the 64-bit VM on sparc
126 // since the 32-bit VM has the same registers and smaller objects.
127 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
128 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
129 #endif // _LP64
130 #ifdef COMPILER2
131 // Indirect branch is the same cost as direct
132 if (FLAG_IS_DEFAULT(UseJumpTables)) {
133 FLAG_SET_DEFAULT(UseJumpTables, true);
134 }
135 // Single-issue, so entry and loop tops are
136 // aligned on a single instruction boundary
137 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
138 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
139 }
140 if (is_niagara_plus()) {
141 if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
142 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
143 // Use BIS instruction for TLAB allocation prefetch.
144 FLAG_SET_ERGO(intx, AllocatePrefetchInstr, 1);
145 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
146 FLAG_SET_ERGO(intx, AllocatePrefetchStyle, 3);
147 }
148 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
149 // Use smaller prefetch distance with BIS
150 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
151 }
152 }
153 if (is_T4()) {
154 // Double number of prefetched cache lines on T4
155 // since L2 cache line size is smaller (32 bytes).
156 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
157 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
158 }
159 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
160 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
161 }
162 }
163 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
164 // Use different prefetch distance without BIS
165 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
166 }
167 if (AllocatePrefetchInstr == 1) {
168 // Need a space at the end of TLAB for BIS since it
169 // will fault when accessing memory outside of heap.
170
171 // +1 for rounding up to next cache line, +1 to be safe
172 int lines = AllocatePrefetchLines + 2;
173 int step_size = AllocatePrefetchStepSize;
174 int distance = AllocatePrefetchDistance;
175 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
176 }
177 }
178 #endif
179 }
180
181 // Use hardware population count instruction if available.
182 if (has_hardware_popc()) {
183 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
184 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
185 }
186 } else if (UsePopCountInstruction) {
187 warning("POPC instruction is not available on this CPU");
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1 /*
2 * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
123 }
124 #ifdef _LP64
125 // 32-bit oops don't make sense for the 64-bit VM on sparc
126 // since the 32-bit VM has the same registers and smaller objects.
127 Universe::set_narrow_oop_shift(LogMinObjAlignmentInBytes);
128 Universe::set_narrow_klass_shift(LogKlassAlignmentInBytes);
129 #endif // _LP64
130 #ifdef COMPILER2
131 // Indirect branch is the same cost as direct
132 if (FLAG_IS_DEFAULT(UseJumpTables)) {
133 FLAG_SET_DEFAULT(UseJumpTables, true);
134 }
135 // Single-issue, so entry and loop tops are
136 // aligned on a single instruction boundary
137 if (FLAG_IS_DEFAULT(InteriorEntryAlignment)) {
138 FLAG_SET_DEFAULT(InteriorEntryAlignment, 4);
139 }
140 if (is_niagara_plus()) {
141 if (has_blk_init() && (cache_line_size > 0) && UseTLAB &&
142 FLAG_IS_DEFAULT(AllocatePrefetchInstr)) {
143 if (!has_sparc5_instr()) {
144 // Use BIS instruction for TLAB allocation prefetch
145 // on Niagara plus processors other than those based on CoreS4.
146 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 1);
147 } else {
148 // On CoreS4 processors use prefetch instruction
149 // to avoid partial RAW issue, also use prefetch style 3
150 FLAG_SET_DEFAULT(AllocatePrefetchInstr, 0);
151 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) {
152 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
153 }
154 }
155 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
156 // Use smaller prefetch distance with BIS
157 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 64);
158 }
159 }
160 if (is_T4()) {
161 // Double number of prefetched cache lines on T4
162 // since L2 cache line size is smaller (32 bytes).
163 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) {
164 FLAG_SET_ERGO(intx, AllocatePrefetchLines, AllocatePrefetchLines*2);
165 }
166 if (FLAG_IS_DEFAULT(AllocateInstancePrefetchLines)) {
167 FLAG_SET_ERGO(intx, AllocateInstancePrefetchLines, AllocateInstancePrefetchLines*2);
168 }
169 }
170 if (AllocatePrefetchStyle != 3 && FLAG_IS_DEFAULT(AllocatePrefetchDistance)) {
171 // Use different prefetch distance without BIS
172 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
173 }
174 if (AllocatePrefetchInstr == 1) {
175
176 // Use allocation prefetch style 3 because BIS instructions
177 // require aligned memory addresses.
178 FLAG_SET_DEFAULT(AllocatePrefetchStyle, 3);
179
180 // Need a space at the end of TLAB for BIS since it
181 // will fault when accessing memory outside of heap.
182
183 // +1 for rounding up to next cache line, +1 to be safe
184 int lines = AllocatePrefetchLines + 2;
185 int step_size = AllocatePrefetchStepSize;
186 int distance = AllocatePrefetchDistance;
187 _reserve_for_allocation_prefetch = (distance + step_size*lines)/(int)HeapWordSize;
188 }
189 }
190 #endif
191 }
192
193 // Use hardware population count instruction if available.
194 if (has_hardware_popc()) {
195 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
196 FLAG_SET_DEFAULT(UsePopCountInstruction, true);
197 }
198 } else if (UsePopCountInstruction) {
199 warning("POPC instruction is not available on this CPU");
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