src/share/vm/opto/macro.cpp

@@ -1,7 +1,7 @@
 /*
- * Copyright (c) 2005, 2015, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 2005, 2017, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 only, as
  * published by the Free Software Foundation.

@@ -1773,11 +1773,11 @@
       needgc_false = pf_region;
       contended_phi_rawmem = pf_phi_rawmem;
       i_o = pf_phi_abio;
    } else if( UseTLAB && AllocatePrefetchStyle == 3 ) {
       // Insert a prefetch for each allocation.
-      // This code is used for Sparc with BIS.
+      // This code is used to generate 1 prefetch instruction per cache line.
       Node *pf_region = new (C) RegionNode(3);
       Node *pf_phi_rawmem = new (C) PhiNode( pf_region, Type::MEMORY,
                                              TypeRawPtr::BOTTOM );
 
       // Generate several prefetch instructions.

@@ -1789,10 +1789,12 @@
       Node *cache_adr = new (C) AddPNode(old_eden_top, old_eden_top,
                                             _igvn.MakeConX(distance));
       transform_later(cache_adr);
       cache_adr = new (C) CastP2XNode(needgc_false, cache_adr);
       transform_later(cache_adr);
+      // Address is aligned to execute prefetch to the beginning of cache line size
+      // (it is important when BIS instruction is used on SPARC as prefetch).
       Node* mask = _igvn.MakeConX(~(intptr_t)(step_size-1));
       cache_adr = new (C) AndXNode(cache_adr, mask);
       transform_later(cache_adr);
       cache_adr = new (C) CastX2PNode(cache_adr);
       transform_later(cache_adr);