1 //
2 // Copyright (c) 1998, 2015, Oracle and/or its affiliates. All rights reserved.
3 // DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 //
5 // This code is free software; you can redistribute it and/or modify it
6 // under the terms of the GNU General Public License version 2 only, as
7 // published by the Free Software Foundation.
8 //
9 // This code is distributed in the hope that it will be useful, but WITHOUT
10 // ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 // FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 // version 2 for more details (a copy is included in the LICENSE file that
13 // accompanied this code).
14 //
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20 // or visit www.oracle.com if you need additional information or have any
21 // questions.
22 //
23 //
24
25 // SPARC Architecture Description File
26
27 //----------REGISTER DEFINITION BLOCK------------------------------------------
28 // This information is used by the matcher and the register allocator to
29 // describe individual registers and classes of registers within the target
30 // archtecture.
31 register %{
32 //----------Architecture Description Register Definitions----------------------
33 // General Registers
34 // "reg_def" name ( register save type, C convention save type,
35 // ideal register type, encoding, vm name );
36 // Register Save Types:
37 //
38 // NS = No-Save: The register allocator assumes that these registers
39 // can be used without saving upon entry to the method, &
40 // that they do not need to be saved at call sites.
41 //
42 // SOC = Save-On-Call: The register allocator assumes that these registers
43 // can be used without saving upon entry to the method,
44 // but that they must be saved at call sites.
45 //
46 // SOE = Save-On-Entry: The register allocator assumes that these registers
47 // must be saved before using them upon entry to the
48 // method, but they do not need to be saved at call
49 // sites.
50 //
51 // AS = Always-Save: The register allocator assumes that these registers
52 // must be saved before using them upon entry to the
53 // method, & that they must be saved at call sites.
54 //
55 // Ideal Register Type is used to determine how to save & restore a
56 // register. Op_RegI will get spilled with LoadI/StoreI, Op_RegP will get
57 // spilled with LoadP/StoreP. If the register supports both, use Op_RegI.
58 //
59 // The encoding number is the actual bit-pattern placed into the opcodes.
60
61
62 // ----------------------------
63 // Integer/Long Registers
64 // ----------------------------
65
66 // Need to expose the hi/lo aspect of 64-bit registers
67 // This register set is used for both the 64-bit build and
68 // the 32-bit build with 1-register longs.
69
70 // Global Registers 0-7
71 reg_def R_G0H( NS, NS, Op_RegI,128, G0->as_VMReg()->next());
72 reg_def R_G0 ( NS, NS, Op_RegI, 0, G0->as_VMReg());
73 reg_def R_G1H(SOC, SOC, Op_RegI,129, G1->as_VMReg()->next());
74 reg_def R_G1 (SOC, SOC, Op_RegI, 1, G1->as_VMReg());
75 reg_def R_G2H( NS, NS, Op_RegI,130, G2->as_VMReg()->next());
76 reg_def R_G2 ( NS, NS, Op_RegI, 2, G2->as_VMReg());
77 reg_def R_G3H(SOC, SOC, Op_RegI,131, G3->as_VMReg()->next());
78 reg_def R_G3 (SOC, SOC, Op_RegI, 3, G3->as_VMReg());
79 reg_def R_G4H(SOC, SOC, Op_RegI,132, G4->as_VMReg()->next());
80 reg_def R_G4 (SOC, SOC, Op_RegI, 4, G4->as_VMReg());
81 reg_def R_G5H(SOC, SOC, Op_RegI,133, G5->as_VMReg()->next());
82 reg_def R_G5 (SOC, SOC, Op_RegI, 5, G5->as_VMReg());
83 reg_def R_G6H( NS, NS, Op_RegI,134, G6->as_VMReg()->next());
84 reg_def R_G6 ( NS, NS, Op_RegI, 6, G6->as_VMReg());
85 reg_def R_G7H( NS, NS, Op_RegI,135, G7->as_VMReg()->next());
86 reg_def R_G7 ( NS, NS, Op_RegI, 7, G7->as_VMReg());
87
88 // Output Registers 0-7
89 reg_def R_O0H(SOC, SOC, Op_RegI,136, O0->as_VMReg()->next());
90 reg_def R_O0 (SOC, SOC, Op_RegI, 8, O0->as_VMReg());
91 reg_def R_O1H(SOC, SOC, Op_RegI,137, O1->as_VMReg()->next());
92 reg_def R_O1 (SOC, SOC, Op_RegI, 9, O1->as_VMReg());
93 reg_def R_O2H(SOC, SOC, Op_RegI,138, O2->as_VMReg()->next());
94 reg_def R_O2 (SOC, SOC, Op_RegI, 10, O2->as_VMReg());
95 reg_def R_O3H(SOC, SOC, Op_RegI,139, O3->as_VMReg()->next());
96 reg_def R_O3 (SOC, SOC, Op_RegI, 11, O3->as_VMReg());
97 reg_def R_O4H(SOC, SOC, Op_RegI,140, O4->as_VMReg()->next());
98 reg_def R_O4 (SOC, SOC, Op_RegI, 12, O4->as_VMReg());
99 reg_def R_O5H(SOC, SOC, Op_RegI,141, O5->as_VMReg()->next());
100 reg_def R_O5 (SOC, SOC, Op_RegI, 13, O5->as_VMReg());
101 reg_def R_SPH( NS, NS, Op_RegI,142, SP->as_VMReg()->next());
102 reg_def R_SP ( NS, NS, Op_RegI, 14, SP->as_VMReg());
103 reg_def R_O7H(SOC, SOC, Op_RegI,143, O7->as_VMReg()->next());
104 reg_def R_O7 (SOC, SOC, Op_RegI, 15, O7->as_VMReg());
105
106 // Local Registers 0-7
107 reg_def R_L0H( NS, NS, Op_RegI,144, L0->as_VMReg()->next());
108 reg_def R_L0 ( NS, NS, Op_RegI, 16, L0->as_VMReg());
109 reg_def R_L1H( NS, NS, Op_RegI,145, L1->as_VMReg()->next());
110 reg_def R_L1 ( NS, NS, Op_RegI, 17, L1->as_VMReg());
111 reg_def R_L2H( NS, NS, Op_RegI,146, L2->as_VMReg()->next());
112 reg_def R_L2 ( NS, NS, Op_RegI, 18, L2->as_VMReg());
113 reg_def R_L3H( NS, NS, Op_RegI,147, L3->as_VMReg()->next());
114 reg_def R_L3 ( NS, NS, Op_RegI, 19, L3->as_VMReg());
115 reg_def R_L4H( NS, NS, Op_RegI,148, L4->as_VMReg()->next());
116 reg_def R_L4 ( NS, NS, Op_RegI, 20, L4->as_VMReg());
117 reg_def R_L5H( NS, NS, Op_RegI,149, L5->as_VMReg()->next());
118 reg_def R_L5 ( NS, NS, Op_RegI, 21, L5->as_VMReg());
119 reg_def R_L6H( NS, NS, Op_RegI,150, L6->as_VMReg()->next());
120 reg_def R_L6 ( NS, NS, Op_RegI, 22, L6->as_VMReg());
121 reg_def R_L7H( NS, NS, Op_RegI,151, L7->as_VMReg()->next());
122 reg_def R_L7 ( NS, NS, Op_RegI, 23, L7->as_VMReg());
123
124 // Input Registers 0-7
125 reg_def R_I0H( NS, NS, Op_RegI,152, I0->as_VMReg()->next());
126 reg_def R_I0 ( NS, NS, Op_RegI, 24, I0->as_VMReg());
127 reg_def R_I1H( NS, NS, Op_RegI,153, I1->as_VMReg()->next());
128 reg_def R_I1 ( NS, NS, Op_RegI, 25, I1->as_VMReg());
129 reg_def R_I2H( NS, NS, Op_RegI,154, I2->as_VMReg()->next());
130 reg_def R_I2 ( NS, NS, Op_RegI, 26, I2->as_VMReg());
131 reg_def R_I3H( NS, NS, Op_RegI,155, I3->as_VMReg()->next());
132 reg_def R_I3 ( NS, NS, Op_RegI, 27, I3->as_VMReg());
133 reg_def R_I4H( NS, NS, Op_RegI,156, I4->as_VMReg()->next());
134 reg_def R_I4 ( NS, NS, Op_RegI, 28, I4->as_VMReg());
135 reg_def R_I5H( NS, NS, Op_RegI,157, I5->as_VMReg()->next());
136 reg_def R_I5 ( NS, NS, Op_RegI, 29, I5->as_VMReg());
137 reg_def R_FPH( NS, NS, Op_RegI,158, FP->as_VMReg()->next());
138 reg_def R_FP ( NS, NS, Op_RegI, 30, FP->as_VMReg());
139 reg_def R_I7H( NS, NS, Op_RegI,159, I7->as_VMReg()->next());
140 reg_def R_I7 ( NS, NS, Op_RegI, 31, I7->as_VMReg());
141
142 // ----------------------------
143 // Float/Double Registers
144 // ----------------------------
145
146 // Float Registers
147 reg_def R_F0 ( SOC, SOC, Op_RegF, 0, F0->as_VMReg());
148 reg_def R_F1 ( SOC, SOC, Op_RegF, 1, F1->as_VMReg());
149 reg_def R_F2 ( SOC, SOC, Op_RegF, 2, F2->as_VMReg());
150 reg_def R_F3 ( SOC, SOC, Op_RegF, 3, F3->as_VMReg());
151 reg_def R_F4 ( SOC, SOC, Op_RegF, 4, F4->as_VMReg());
152 reg_def R_F5 ( SOC, SOC, Op_RegF, 5, F5->as_VMReg());
153 reg_def R_F6 ( SOC, SOC, Op_RegF, 6, F6->as_VMReg());
154 reg_def R_F7 ( SOC, SOC, Op_RegF, 7, F7->as_VMReg());
155 reg_def R_F8 ( SOC, SOC, Op_RegF, 8, F8->as_VMReg());
156 reg_def R_F9 ( SOC, SOC, Op_RegF, 9, F9->as_VMReg());
157 reg_def R_F10( SOC, SOC, Op_RegF, 10, F10->as_VMReg());
158 reg_def R_F11( SOC, SOC, Op_RegF, 11, F11->as_VMReg());
159 reg_def R_F12( SOC, SOC, Op_RegF, 12, F12->as_VMReg());
160 reg_def R_F13( SOC, SOC, Op_RegF, 13, F13->as_VMReg());
161 reg_def R_F14( SOC, SOC, Op_RegF, 14, F14->as_VMReg());
162 reg_def R_F15( SOC, SOC, Op_RegF, 15, F15->as_VMReg());
163 reg_def R_F16( SOC, SOC, Op_RegF, 16, F16->as_VMReg());
164 reg_def R_F17( SOC, SOC, Op_RegF, 17, F17->as_VMReg());
165 reg_def R_F18( SOC, SOC, Op_RegF, 18, F18->as_VMReg());
166 reg_def R_F19( SOC, SOC, Op_RegF, 19, F19->as_VMReg());
167 reg_def R_F20( SOC, SOC, Op_RegF, 20, F20->as_VMReg());
168 reg_def R_F21( SOC, SOC, Op_RegF, 21, F21->as_VMReg());
169 reg_def R_F22( SOC, SOC, Op_RegF, 22, F22->as_VMReg());
170 reg_def R_F23( SOC, SOC, Op_RegF, 23, F23->as_VMReg());
171 reg_def R_F24( SOC, SOC, Op_RegF, 24, F24->as_VMReg());
172 reg_def R_F25( SOC, SOC, Op_RegF, 25, F25->as_VMReg());
173 reg_def R_F26( SOC, SOC, Op_RegF, 26, F26->as_VMReg());
174 reg_def R_F27( SOC, SOC, Op_RegF, 27, F27->as_VMReg());
175 reg_def R_F28( SOC, SOC, Op_RegF, 28, F28->as_VMReg());
176 reg_def R_F29( SOC, SOC, Op_RegF, 29, F29->as_VMReg());
177 reg_def R_F30( SOC, SOC, Op_RegF, 30, F30->as_VMReg());
178 reg_def R_F31( SOC, SOC, Op_RegF, 31, F31->as_VMReg());
179
180 // Double Registers
181 // The rules of ADL require that double registers be defined in pairs.
182 // Each pair must be two 32-bit values, but not necessarily a pair of
183 // single float registers. In each pair, ADLC-assigned register numbers
184 // must be adjacent, with the lower number even. Finally, when the
185 // CPU stores such a register pair to memory, the word associated with
186 // the lower ADLC-assigned number must be stored to the lower address.
187
188 // These definitions specify the actual bit encodings of the sparc
189 // double fp register numbers. FloatRegisterImpl in register_sparc.hpp
190 // wants 0-63, so we have to convert every time we want to use fp regs
191 // with the macroassembler, using reg_to_DoubleFloatRegister_object().
192 // 255 is a flag meaning "don't go here".
193 // I believe we can't handle callee-save doubles D32 and up until
194 // the place in the sparc stack crawler that asserts on the 255 is
195 // fixed up.
196 reg_def R_D32 (SOC, SOC, Op_RegD, 1, F32->as_VMReg());
197 reg_def R_D32x(SOC, SOC, Op_RegD,255, F32->as_VMReg()->next());
198 reg_def R_D34 (SOC, SOC, Op_RegD, 3, F34->as_VMReg());
199 reg_def R_D34x(SOC, SOC, Op_RegD,255, F34->as_VMReg()->next());
200 reg_def R_D36 (SOC, SOC, Op_RegD, 5, F36->as_VMReg());
201 reg_def R_D36x(SOC, SOC, Op_RegD,255, F36->as_VMReg()->next());
202 reg_def R_D38 (SOC, SOC, Op_RegD, 7, F38->as_VMReg());
203 reg_def R_D38x(SOC, SOC, Op_RegD,255, F38->as_VMReg()->next());
204 reg_def R_D40 (SOC, SOC, Op_RegD, 9, F40->as_VMReg());
205 reg_def R_D40x(SOC, SOC, Op_RegD,255, F40->as_VMReg()->next());
206 reg_def R_D42 (SOC, SOC, Op_RegD, 11, F42->as_VMReg());
207 reg_def R_D42x(SOC, SOC, Op_RegD,255, F42->as_VMReg()->next());
208 reg_def R_D44 (SOC, SOC, Op_RegD, 13, F44->as_VMReg());
209 reg_def R_D44x(SOC, SOC, Op_RegD,255, F44->as_VMReg()->next());
210 reg_def R_D46 (SOC, SOC, Op_RegD, 15, F46->as_VMReg());
211 reg_def R_D46x(SOC, SOC, Op_RegD,255, F46->as_VMReg()->next());
212 reg_def R_D48 (SOC, SOC, Op_RegD, 17, F48->as_VMReg());
213 reg_def R_D48x(SOC, SOC, Op_RegD,255, F48->as_VMReg()->next());
214 reg_def R_D50 (SOC, SOC, Op_RegD, 19, F50->as_VMReg());
215 reg_def R_D50x(SOC, SOC, Op_RegD,255, F50->as_VMReg()->next());
216 reg_def R_D52 (SOC, SOC, Op_RegD, 21, F52->as_VMReg());
217 reg_def R_D52x(SOC, SOC, Op_RegD,255, F52->as_VMReg()->next());
218 reg_def R_D54 (SOC, SOC, Op_RegD, 23, F54->as_VMReg());
219 reg_def R_D54x(SOC, SOC, Op_RegD,255, F54->as_VMReg()->next());
220 reg_def R_D56 (SOC, SOC, Op_RegD, 25, F56->as_VMReg());
221 reg_def R_D56x(SOC, SOC, Op_RegD,255, F56->as_VMReg()->next());
222 reg_def R_D58 (SOC, SOC, Op_RegD, 27, F58->as_VMReg());
223 reg_def R_D58x(SOC, SOC, Op_RegD,255, F58->as_VMReg()->next());
224 reg_def R_D60 (SOC, SOC, Op_RegD, 29, F60->as_VMReg());
225 reg_def R_D60x(SOC, SOC, Op_RegD,255, F60->as_VMReg()->next());
226 reg_def R_D62 (SOC, SOC, Op_RegD, 31, F62->as_VMReg());
227 reg_def R_D62x(SOC, SOC, Op_RegD,255, F62->as_VMReg()->next());
228
229
230 // ----------------------------
231 // Special Registers
232 // Condition Codes Flag Registers
233 // I tried to break out ICC and XCC but it's not very pretty.
234 // Every Sparc instruction which defs/kills one also kills the other.
235 // Hence every compare instruction which defs one kind of flags ends
236 // up needing a kill of the other.
237 reg_def CCR (SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
238
239 reg_def FCC0(SOC, SOC, Op_RegFlags, 0, VMRegImpl::Bad());
240 reg_def FCC1(SOC, SOC, Op_RegFlags, 1, VMRegImpl::Bad());
241 reg_def FCC2(SOC, SOC, Op_RegFlags, 2, VMRegImpl::Bad());
242 reg_def FCC3(SOC, SOC, Op_RegFlags, 3, VMRegImpl::Bad());
243
244 // ----------------------------
245 // Specify the enum values for the registers. These enums are only used by the
246 // OptoReg "class". We can convert these enum values at will to VMReg when needed
247 // for visibility to the rest of the vm. The order of this enum influences the
248 // register allocator so having the freedom to set this order and not be stuck
249 // with the order that is natural for the rest of the vm is worth it.
250 alloc_class chunk0(
251 R_L0,R_L0H, R_L1,R_L1H, R_L2,R_L2H, R_L3,R_L3H, R_L4,R_L4H, R_L5,R_L5H, R_L6,R_L6H, R_L7,R_L7H,
252 R_G0,R_G0H, R_G1,R_G1H, R_G2,R_G2H, R_G3,R_G3H, R_G4,R_G4H, R_G5,R_G5H, R_G6,R_G6H, R_G7,R_G7H,
253 R_O7,R_O7H, R_SP,R_SPH, R_O0,R_O0H, R_O1,R_O1H, R_O2,R_O2H, R_O3,R_O3H, R_O4,R_O4H, R_O5,R_O5H,
254 R_I0,R_I0H, R_I1,R_I1H, R_I2,R_I2H, R_I3,R_I3H, R_I4,R_I4H, R_I5,R_I5H, R_FP,R_FPH, R_I7,R_I7H);
255
256 // Note that a register is not allocatable unless it is also mentioned
257 // in a widely-used reg_class below. Thus, R_G7 and R_G0 are outside i_reg.
258
259 alloc_class chunk1(
260 // The first registers listed here are those most likely to be used
261 // as temporaries. We move F0..F7 away from the front of the list,
262 // to reduce the likelihood of interferences with parameters and
263 // return values. Likewise, we avoid using F0/F1 for parameters,
264 // since they are used for return values.
265 // This FPU fine-tuning is worth about 1% on the SPEC geomean.
266 R_F8 ,R_F9 ,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
267 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,
268 R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,R_F30,R_F31,
269 R_F0 ,R_F1 ,R_F2 ,R_F3 ,R_F4 ,R_F5 ,R_F6 ,R_F7 , // used for arguments and return values
270 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,
271 R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
272 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,
273 R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x);
274
275 alloc_class chunk2(CCR, FCC0, FCC1, FCC2, FCC3);
276
277 //----------Architecture Description Register Classes--------------------------
278 // Several register classes are automatically defined based upon information in
279 // this architecture description.
280 // 1) reg_class inline_cache_reg ( as defined in frame section )
281 // 2) reg_class interpreter_method_oop_reg ( as defined in frame section )
282 // 3) reg_class stack_slots( /* one chunk of stack-based "registers" */ )
283 //
284
285 // G0 is not included in integer class since it has special meaning.
286 reg_class g0_reg(R_G0);
287
288 // ----------------------------
289 // Integer Register Classes
290 // ----------------------------
291 // Exclusions from i_reg:
292 // R_G0: hardwired zero
293 // R_G2: reserved by HotSpot to the TLS register (invariant within Java)
294 // R_G6: reserved by Solaris ABI to tools
295 // R_G7: reserved by Solaris ABI to libthread
296 // R_O7: Used as a temp in many encodings
297 reg_class int_reg(R_G1,R_G3,R_G4,R_G5,R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
298
299 // Class for all integer registers, except the G registers. This is used for
300 // encodings which use G registers as temps. The regular inputs to such
301 // instructions use a "notemp_" prefix, as a hack to ensure that the allocator
302 // will not put an input into a temp register.
303 reg_class notemp_int_reg(R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
304
305 reg_class g1_regI(R_G1);
306 reg_class g3_regI(R_G3);
307 reg_class g4_regI(R_G4);
308 reg_class o0_regI(R_O0);
309 reg_class o7_regI(R_O7);
310
311 // ----------------------------
312 // Pointer Register Classes
313 // ----------------------------
314 #ifdef _LP64
315 // 64-bit build means 64-bit pointers means hi/lo pairs
316 reg_class ptr_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
317 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
318 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
319 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
320 // Lock encodings use G3 and G4 internally
321 reg_class lock_ptr_reg( R_G1H,R_G1, R_G5H,R_G5,
322 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5,
323 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
324 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5 );
325 // Special class for storeP instructions, which can store SP or RPC to TLS.
326 // It is also used for memory addressing, allowing direct TLS addressing.
327 reg_class sp_ptr_reg( R_G1H,R_G1, R_G2H,R_G2, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5,
328 R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5, R_SPH,R_SP,
329 R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7,
330 R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5, R_FPH,R_FP );
331 // R_L7 is the lowest-priority callee-save (i.e., NS) register
332 // We use it to save R_G2 across calls out of Java.
333 reg_class l7_regP(R_L7H,R_L7);
334
335 // Other special pointer regs
336 reg_class g1_regP(R_G1H,R_G1);
337 reg_class g2_regP(R_G2H,R_G2);
338 reg_class g3_regP(R_G3H,R_G3);
339 reg_class g4_regP(R_G4H,R_G4);
340 reg_class g5_regP(R_G5H,R_G5);
341 reg_class i0_regP(R_I0H,R_I0);
342 reg_class o0_regP(R_O0H,R_O0);
343 reg_class o1_regP(R_O1H,R_O1);
344 reg_class o2_regP(R_O2H,R_O2);
345 reg_class o7_regP(R_O7H,R_O7);
346
347 #else // _LP64
348 // 32-bit build means 32-bit pointers means 1 register.
349 reg_class ptr_reg( R_G1, R_G3,R_G4,R_G5,
350 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
351 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
352 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
353 // Lock encodings use G3 and G4 internally
354 reg_class lock_ptr_reg(R_G1, R_G5,
355 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,
356 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
357 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5);
358 // Special class for storeP instructions, which can store SP or RPC to TLS.
359 // It is also used for memory addressing, allowing direct TLS addressing.
360 reg_class sp_ptr_reg( R_G1,R_G2,R_G3,R_G4,R_G5,
361 R_O0,R_O1,R_O2,R_O3,R_O4,R_O5,R_SP,
362 R_L0,R_L1,R_L2,R_L3,R_L4,R_L5,R_L6,R_L7,
363 R_I0,R_I1,R_I2,R_I3,R_I4,R_I5,R_FP);
364 // R_L7 is the lowest-priority callee-save (i.e., NS) register
365 // We use it to save R_G2 across calls out of Java.
366 reg_class l7_regP(R_L7);
367
368 // Other special pointer regs
369 reg_class g1_regP(R_G1);
370 reg_class g2_regP(R_G2);
371 reg_class g3_regP(R_G3);
372 reg_class g4_regP(R_G4);
373 reg_class g5_regP(R_G5);
374 reg_class i0_regP(R_I0);
375 reg_class o0_regP(R_O0);
376 reg_class o1_regP(R_O1);
377 reg_class o2_regP(R_O2);
378 reg_class o7_regP(R_O7);
379 #endif // _LP64
380
381
382 // ----------------------------
383 // Long Register Classes
384 // ----------------------------
385 // Longs in 1 register. Aligned adjacent hi/lo pairs.
386 // Note: O7 is never in this class; it is sometimes used as an encoding temp.
387 reg_class long_reg( R_G1H,R_G1, R_G3H,R_G3, R_G4H,R_G4, R_G5H,R_G5
388 ,R_O0H,R_O0, R_O1H,R_O1, R_O2H,R_O2, R_O3H,R_O3, R_O4H,R_O4, R_O5H,R_O5
389 #ifdef _LP64
390 // 64-bit, longs in 1 register: use all 64-bit integer registers
391 // 32-bit, longs in 1 register: cannot use I's and L's. Restrict to O's and G's.
392 ,R_L0H,R_L0, R_L1H,R_L1, R_L2H,R_L2, R_L3H,R_L3, R_L4H,R_L4, R_L5H,R_L5, R_L6H,R_L6, R_L7H,R_L7
393 ,R_I0H,R_I0, R_I1H,R_I1, R_I2H,R_I2, R_I3H,R_I3, R_I4H,R_I4, R_I5H,R_I5
394 #endif // _LP64
395 );
396
397 reg_class g1_regL(R_G1H,R_G1);
398 reg_class g3_regL(R_G3H,R_G3);
399 reg_class o2_regL(R_O2H,R_O2);
400 reg_class o7_regL(R_O7H,R_O7);
401
402 // ----------------------------
403 // Special Class for Condition Code Flags Register
404 reg_class int_flags(CCR);
405 reg_class float_flags(FCC0,FCC1,FCC2,FCC3);
406 reg_class float_flag0(FCC0);
407
408
409 // ----------------------------
410 // Float Point Register Classes
411 // ----------------------------
412 // Skip F30/F31, they are reserved for mem-mem copies
413 reg_class sflt_reg(R_F0,R_F1,R_F2,R_F3,R_F4,R_F5,R_F6,R_F7,R_F8,R_F9,R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
414
415 // Paired floating point registers--they show up in the same order as the floats,
416 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
417 reg_class dflt_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
418 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29,
419 /* Use extra V9 double registers; this AD file does not support V8 */
420 R_D32,R_D32x,R_D34,R_D34x,R_D36,R_D36x,R_D38,R_D38x,R_D40,R_D40x,R_D42,R_D42x,R_D44,R_D44x,R_D46,R_D46x,
421 R_D48,R_D48x,R_D50,R_D50x,R_D52,R_D52x,R_D54,R_D54x,R_D56,R_D56x,R_D58,R_D58x,R_D60,R_D60x,R_D62,R_D62x
422 );
423
424 // Paired floating point registers--they show up in the same order as the floats,
425 // but they are used with the "Op_RegD" type, and always occur in even/odd pairs.
426 // This class is usable for mis-aligned loads as happen in I2C adapters.
427 reg_class dflt_low_reg(R_F0, R_F1, R_F2, R_F3, R_F4, R_F5, R_F6, R_F7, R_F8, R_F9, R_F10,R_F11,R_F12,R_F13,R_F14,R_F15,
428 R_F16,R_F17,R_F18,R_F19,R_F20,R_F21,R_F22,R_F23,R_F24,R_F25,R_F26,R_F27,R_F28,R_F29);
429 %}
430
431 //----------DEFINITION BLOCK---------------------------------------------------
432 // Define name --> value mappings to inform the ADLC of an integer valued name
433 // Current support includes integer values in the range [0, 0x7FFFFFFF]
434 // Format:
435 // int_def <name> ( <int_value>, <expression>);
436 // Generated Code in ad_<arch>.hpp
437 // #define <name> (<expression>)
438 // // value == <int_value>
439 // Generated code in ad_<arch>.cpp adlc_verification()
440 // assert( <name> == <int_value>, "Expect (<expression>) to equal <int_value>");
441 //
442 definitions %{
443 // The default cost (of an ALU instruction).
444 int_def DEFAULT_COST ( 100, 100);
445 int_def HUGE_COST (1000000, 1000000);
446
447 // Memory refs are twice as expensive as run-of-the-mill.
448 int_def MEMORY_REF_COST ( 200, DEFAULT_COST * 2);
449
450 // Branches are even more expensive.
451 int_def BRANCH_COST ( 300, DEFAULT_COST * 3);
452 int_def CALL_COST ( 300, DEFAULT_COST * 3);
453 %}
454
455
456 //----------SOURCE BLOCK-------------------------------------------------------
457 // This is a block of C++ code which provides values, functions, and
458 // definitions necessary in the rest of the architecture description
459 source_hpp %{
460 // Header information of the source block.
461 // Method declarations/definitions which are used outside
462 // the ad-scope can conveniently be defined here.
463 //
464 // To keep related declarations/definitions/uses close together,
465 // we switch between source %{ }% and source_hpp %{ }% freely as needed.
466
467 // Must be visible to the DFA in dfa_sparc.cpp
468 extern bool can_branch_register( Node *bol, Node *cmp );
469
470 extern bool use_block_zeroing(Node* count);
471
472 // Macros to extract hi & lo halves from a long pair.
473 // G0 is not part of any long pair, so assert on that.
474 // Prevents accidentally using G1 instead of G0.
475 #define LONG_HI_REG(x) (x)
476 #define LONG_LO_REG(x) (x)
477
478 class CallStubImpl {
479
480 //--------------------------------------------------------------
481 //---< Used for optimization in Compile::Shorten_branches >---
482 //--------------------------------------------------------------
483
484 public:
485 // Size of call trampoline stub.
486 static uint size_call_trampoline() {
487 return 0; // no call trampolines on this platform
488 }
489
490 // number of relocations needed by a call trampoline stub
491 static uint reloc_call_trampoline() {
492 return 0; // no call trampolines on this platform
493 }
494 };
495
496 class HandlerImpl {
497
498 public:
499
500 static int emit_exception_handler(CodeBuffer &cbuf);
501 static int emit_deopt_handler(CodeBuffer& cbuf);
502
503 static uint size_exception_handler() {
504 if (TraceJumps) {
505 return (400); // just a guess
506 }
507 return ( NativeJump::instruction_size ); // sethi;jmp;nop
508 }
509
510 static uint size_deopt_handler() {
511 if (TraceJumps) {
512 return (400); // just a guess
513 }
514 return ( 4+ NativeJump::instruction_size ); // save;sethi;jmp;restore
515 }
516 };
517
518 %}
519
520 source %{
521 #define __ _masm.
522
523 // tertiary op of a LoadP or StoreP encoding
524 #define REGP_OP true
525
526 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding);
527 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding);
528 static Register reg_to_register_object(int register_encoding);
529
530 // Used by the DFA in dfa_sparc.cpp.
531 // Check for being able to use a V9 branch-on-register. Requires a
532 // compare-vs-zero, equal/not-equal, of a value which was zero- or sign-
533 // extended. Doesn't work following an integer ADD, for example, because of
534 // overflow (-1 incremented yields 0 plus a carry in the high-order word). On
535 // 32-bit V9 systems, interrupts currently blow away the high-order 32 bits and
536 // replace them with zero, which could become sign-extension in a different OS
537 // release. There's no obvious reason why an interrupt will ever fill these
538 // bits with non-zero junk (the registers are reloaded with standard LD
539 // instructions which either zero-fill or sign-fill).
540 bool can_branch_register( Node *bol, Node *cmp ) {
541 if( !BranchOnRegister ) return false;
542 #ifdef _LP64
543 if( cmp->Opcode() == Op_CmpP )
544 return true; // No problems with pointer compares
545 #endif
546 if( cmp->Opcode() == Op_CmpL )
547 return true; // No problems with long compares
548
549 if( !SparcV9RegsHiBitsZero ) return false;
550 if( bol->as_Bool()->_test._test != BoolTest::ne &&
551 bol->as_Bool()->_test._test != BoolTest::eq )
552 return false;
553
554 // Check for comparing against a 'safe' value. Any operation which
555 // clears out the high word is safe. Thus, loads and certain shifts
556 // are safe, as are non-negative constants. Any operation which
557 // preserves zero bits in the high word is safe as long as each of its
558 // inputs are safe. Thus, phis and bitwise booleans are safe if their
559 // inputs are safe. At present, the only important case to recognize
560 // seems to be loads. Constants should fold away, and shifts &
561 // logicals can use the 'cc' forms.
562 Node *x = cmp->in(1);
563 if( x->is_Load() ) return true;
564 if( x->is_Phi() ) {
565 for( uint i = 1; i < x->req(); i++ )
566 if( !x->in(i)->is_Load() )
567 return false;
568 return true;
569 }
570 return false;
571 }
572
573 bool use_block_zeroing(Node* count) {
574 // Use BIS for zeroing if count is not constant
575 // or it is >= BlockZeroingLowLimit.
576 return UseBlockZeroing && (count->find_intptr_t_con(BlockZeroingLowLimit) >= BlockZeroingLowLimit);
577 }
578
579 // ****************************************************************************
580
581 // REQUIRED FUNCTIONALITY
582
583 // !!!!! Special hack to get all type of calls to specify the byte offset
584 // from the start of the call to the point where the return address
585 // will point.
586 // The "return address" is the address of the call instruction, plus 8.
587
588 int MachCallStaticJavaNode::ret_addr_offset() {
589 int offset = NativeCall::instruction_size; // call; delay slot
590 if (_method_handle_invoke)
591 offset += 4; // restore SP
592 return offset;
593 }
594
595 int MachCallDynamicJavaNode::ret_addr_offset() {
596 int vtable_index = this->_vtable_index;
597 if (vtable_index < 0) {
598 // must be invalid_vtable_index, not nonvirtual_vtable_index
599 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
600 return (NativeMovConstReg::instruction_size +
601 NativeCall::instruction_size); // sethi; setlo; call; delay slot
602 } else {
603 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
604 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
605 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
606 int klass_load_size;
607 if (UseCompressedClassPointers) {
608 assert(Universe::heap() != NULL, "java heap should be initialized");
609 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
610 } else {
611 klass_load_size = 1*BytesPerInstWord;
612 }
613 if (Assembler::is_simm13(v_off)) {
614 return klass_load_size +
615 (2*BytesPerInstWord + // ld_ptr, ld_ptr
616 NativeCall::instruction_size); // call; delay slot
617 } else {
618 return klass_load_size +
619 (4*BytesPerInstWord + // set_hi, set, ld_ptr, ld_ptr
620 NativeCall::instruction_size); // call; delay slot
621 }
622 }
623 }
624
625 int MachCallRuntimeNode::ret_addr_offset() {
626 #ifdef _LP64
627 if (MacroAssembler::is_far_target(entry_point())) {
628 return NativeFarCall::instruction_size;
629 } else {
630 return NativeCall::instruction_size;
631 }
632 #else
633 return NativeCall::instruction_size; // call; delay slot
634 #endif
635 }
636
637 // Indicate if the safepoint node needs the polling page as an input.
638 // Since Sparc does not have absolute addressing, it does.
639 bool SafePointNode::needs_polling_address_input() {
640 return true;
641 }
642
643 // emit an interrupt that is caught by the debugger (for debugging compiler)
644 void emit_break(CodeBuffer &cbuf) {
645 MacroAssembler _masm(&cbuf);
646 __ breakpoint_trap();
647 }
648
649 #ifndef PRODUCT
650 void MachBreakpointNode::format( PhaseRegAlloc *, outputStream *st ) const {
651 st->print("TA");
652 }
653 #endif
654
655 void MachBreakpointNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
656 emit_break(cbuf);
657 }
658
659 uint MachBreakpointNode::size(PhaseRegAlloc *ra_) const {
660 return MachNode::size(ra_);
661 }
662
663 // Traceable jump
664 void emit_jmpl(CodeBuffer &cbuf, int jump_target) {
665 MacroAssembler _masm(&cbuf);
666 Register rdest = reg_to_register_object(jump_target);
667 __ JMP(rdest, 0);
668 __ delayed()->nop();
669 }
670
671 // Traceable jump and set exception pc
672 void emit_jmpl_set_exception_pc(CodeBuffer &cbuf, int jump_target) {
673 MacroAssembler _masm(&cbuf);
674 Register rdest = reg_to_register_object(jump_target);
675 __ JMP(rdest, 0);
676 __ delayed()->add(O7, frame::pc_return_offset, Oissuing_pc );
677 }
678
679 void emit_nop(CodeBuffer &cbuf) {
680 MacroAssembler _masm(&cbuf);
681 __ nop();
682 }
683
684 void emit_illtrap(CodeBuffer &cbuf) {
685 MacroAssembler _masm(&cbuf);
686 __ illtrap(0);
687 }
688
689
690 intptr_t get_offset_from_base(const MachNode* n, const TypePtr* atype, int disp32) {
691 assert(n->rule() != loadUB_rule, "");
692
693 intptr_t offset = 0;
694 const TypePtr *adr_type = TYPE_PTR_SENTINAL; // Check for base==RegI, disp==immP
695 const Node* addr = n->get_base_and_disp(offset, adr_type);
696 assert(adr_type == (const TypePtr*)-1, "VerifyOops: no support for sparc operands with base==RegI, disp==immP");
697 assert(addr != NULL && addr != (Node*)-1, "invalid addr");
698 assert(addr->bottom_type()->isa_oopptr() == atype, "");
699 atype = atype->add_offset(offset);
700 assert(disp32 == offset, "wrong disp32");
701 return atype->_offset;
702 }
703
704
705 intptr_t get_offset_from_base_2(const MachNode* n, const TypePtr* atype, int disp32) {
706 assert(n->rule() != loadUB_rule, "");
707
708 intptr_t offset = 0;
709 Node* addr = n->in(2);
710 assert(addr->bottom_type()->isa_oopptr() == atype, "");
711 if (addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP) {
712 Node* a = addr->in(2/*AddPNode::Address*/);
713 Node* o = addr->in(3/*AddPNode::Offset*/);
714 offset = o->is_Con() ? o->bottom_type()->is_intptr_t()->get_con() : Type::OffsetBot;
715 atype = a->bottom_type()->is_ptr()->add_offset(offset);
716 assert(atype->isa_oop_ptr(), "still an oop");
717 }
718 offset = atype->is_ptr()->_offset;
719 if (offset != Type::OffsetBot) offset += disp32;
720 return offset;
721 }
722
723 static inline jdouble replicate_immI(int con, int count, int width) {
724 // Load a constant replicated "count" times with width "width"
725 assert(count*width == 8 && width <= 4, "sanity");
726 int bit_width = width * 8;
727 jlong val = con;
728 val &= (((jlong) 1) << bit_width) - 1; // mask off sign bits
729 for (int i = 0; i < count - 1; i++) {
730 val |= (val << bit_width);
731 }
732 jdouble dval = *((jdouble*) &val); // coerce to double type
733 return dval;
734 }
735
736 static inline jdouble replicate_immF(float con) {
737 // Replicate float con 2 times and pack into vector.
738 int val = *((int*)&con);
739 jlong lval = val;
740 lval = (lval << 32) | (lval & 0xFFFFFFFFl);
741 jdouble dval = *((jdouble*) &lval); // coerce to double type
742 return dval;
743 }
744
745 // Standard Sparc opcode form2 field breakdown
746 static inline void emit2_19(CodeBuffer &cbuf, int f30, int f29, int f25, int f22, int f20, int f19, int f0 ) {
747 f0 &= (1<<19)-1; // Mask displacement to 19 bits
748 int op = (f30 << 30) |
749 (f29 << 29) |
750 (f25 << 25) |
751 (f22 << 22) |
752 (f20 << 20) |
753 (f19 << 19) |
754 (f0 << 0);
755 cbuf.insts()->emit_int32(op);
756 }
757
758 // Standard Sparc opcode form2 field breakdown
759 static inline void emit2_22(CodeBuffer &cbuf, int f30, int f25, int f22, int f0 ) {
760 f0 >>= 10; // Drop 10 bits
761 f0 &= (1<<22)-1; // Mask displacement to 22 bits
762 int op = (f30 << 30) |
763 (f25 << 25) |
764 (f22 << 22) |
765 (f0 << 0);
766 cbuf.insts()->emit_int32(op);
767 }
768
769 // Standard Sparc opcode form3 field breakdown
770 static inline void emit3(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int f5, int f0 ) {
771 int op = (f30 << 30) |
772 (f25 << 25) |
773 (f19 << 19) |
774 (f14 << 14) |
775 (f5 << 5) |
776 (f0 << 0);
777 cbuf.insts()->emit_int32(op);
778 }
779
780 // Standard Sparc opcode form3 field breakdown
781 static inline void emit3_simm13(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm13 ) {
782 simm13 &= (1<<13)-1; // Mask to 13 bits
783 int op = (f30 << 30) |
784 (f25 << 25) |
785 (f19 << 19) |
786 (f14 << 14) |
787 (1 << 13) | // bit to indicate immediate-mode
788 (simm13<<0);
789 cbuf.insts()->emit_int32(op);
790 }
791
792 static inline void emit3_simm10(CodeBuffer &cbuf, int f30, int f25, int f19, int f14, int simm10 ) {
793 simm10 &= (1<<10)-1; // Mask to 10 bits
794 emit3_simm13(cbuf,f30,f25,f19,f14,simm10);
795 }
796
797 #ifdef ASSERT
798 // Helper function for VerifyOops in emit_form3_mem_reg
799 void verify_oops_warning(const MachNode *n, int ideal_op, int mem_op) {
800 warning("VerifyOops encountered unexpected instruction:");
801 n->dump(2);
802 warning("Instruction has ideal_Opcode==Op_%s and op_ld==Op_%s \n", NodeClassNames[ideal_op], NodeClassNames[mem_op]);
803 }
804 #endif
805
806
807 void emit_form3_mem_reg(CodeBuffer &cbuf, PhaseRegAlloc* ra, const MachNode* n, int primary, int tertiary,
808 int src1_enc, int disp32, int src2_enc, int dst_enc) {
809
810 #ifdef ASSERT
811 // The following code implements the +VerifyOops feature.
812 // It verifies oop values which are loaded into or stored out of
813 // the current method activation. +VerifyOops complements techniques
814 // like ScavengeALot, because it eagerly inspects oops in transit,
815 // as they enter or leave the stack, as opposed to ScavengeALot,
816 // which inspects oops "at rest", in the stack or heap, at safepoints.
817 // For this reason, +VerifyOops can sometimes detect bugs very close
818 // to their point of creation. It can also serve as a cross-check
819 // on the validity of oop maps, when used toegether with ScavengeALot.
820
821 // It would be good to verify oops at other points, especially
822 // when an oop is used as a base pointer for a load or store.
823 // This is presently difficult, because it is hard to know when
824 // a base address is biased or not. (If we had such information,
825 // it would be easy and useful to make a two-argument version of
826 // verify_oop which unbiases the base, and performs verification.)
827
828 assert((uint)tertiary == 0xFFFFFFFF || tertiary == REGP_OP, "valid tertiary");
829 bool is_verified_oop_base = false;
830 bool is_verified_oop_load = false;
831 bool is_verified_oop_store = false;
832 int tmp_enc = -1;
833 if (VerifyOops && src1_enc != R_SP_enc) {
834 // classify the op, mainly for an assert check
835 int st_op = 0, ld_op = 0;
836 switch (primary) {
837 case Assembler::stb_op3: st_op = Op_StoreB; break;
838 case Assembler::sth_op3: st_op = Op_StoreC; break;
839 case Assembler::stx_op3: // may become StoreP or stay StoreI or StoreD0
840 case Assembler::stw_op3: st_op = Op_StoreI; break;
841 case Assembler::std_op3: st_op = Op_StoreL; break;
842 case Assembler::stf_op3: st_op = Op_StoreF; break;
843 case Assembler::stdf_op3: st_op = Op_StoreD; break;
844
845 case Assembler::ldsb_op3: ld_op = Op_LoadB; break;
846 case Assembler::ldub_op3: ld_op = Op_LoadUB; break;
847 case Assembler::lduh_op3: ld_op = Op_LoadUS; break;
848 case Assembler::ldsh_op3: ld_op = Op_LoadS; break;
849 case Assembler::ldx_op3: // may become LoadP or stay LoadI
850 case Assembler::ldsw_op3: // may become LoadP or stay LoadI
851 case Assembler::lduw_op3: ld_op = Op_LoadI; break;
852 case Assembler::ldd_op3: ld_op = Op_LoadL; break;
853 case Assembler::ldf_op3: ld_op = Op_LoadF; break;
854 case Assembler::lddf_op3: ld_op = Op_LoadD; break;
855 case Assembler::prefetch_op3: ld_op = Op_LoadI; break;
856
857 default: ShouldNotReachHere();
858 }
859 if (tertiary == REGP_OP) {
860 if (st_op == Op_StoreI) st_op = Op_StoreP;
861 else if (ld_op == Op_LoadI) ld_op = Op_LoadP;
862 else ShouldNotReachHere();
863 if (st_op) {
864 // a store
865 // inputs are (0:control, 1:memory, 2:address, 3:value)
866 Node* n2 = n->in(3);
867 if (n2 != NULL) {
868 const Type* t = n2->bottom_type();
869 is_verified_oop_store = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
870 }
871 } else {
872 // a load
873 const Type* t = n->bottom_type();
874 is_verified_oop_load = t->isa_oop_ptr() ? (t->is_ptr()->_offset==0) : false;
875 }
876 }
877
878 if (ld_op) {
879 // a Load
880 // inputs are (0:control, 1:memory, 2:address)
881 if (!(n->ideal_Opcode()==ld_op) && // Following are special cases
882 !(n->ideal_Opcode()==Op_LoadPLocked && ld_op==Op_LoadP) &&
883 !(n->ideal_Opcode()==Op_LoadI && ld_op==Op_LoadF) &&
884 !(n->ideal_Opcode()==Op_LoadF && ld_op==Op_LoadI) &&
885 !(n->ideal_Opcode()==Op_LoadRange && ld_op==Op_LoadI) &&
886 !(n->ideal_Opcode()==Op_LoadKlass && ld_op==Op_LoadP) &&
887 !(n->ideal_Opcode()==Op_LoadL && ld_op==Op_LoadI) &&
888 !(n->ideal_Opcode()==Op_LoadL_unaligned && ld_op==Op_LoadI) &&
889 !(n->ideal_Opcode()==Op_LoadD_unaligned && ld_op==Op_LoadF) &&
890 !(n->ideal_Opcode()==Op_ConvI2F && ld_op==Op_LoadF) &&
891 !(n->ideal_Opcode()==Op_ConvI2D && ld_op==Op_LoadF) &&
892 !(n->ideal_Opcode()==Op_PrefetchAllocation && ld_op==Op_LoadI) &&
893 !(n->ideal_Opcode()==Op_LoadVector && ld_op==Op_LoadD) &&
894 !(n->rule() == loadUB_rule)) {
895 verify_oops_warning(n, n->ideal_Opcode(), ld_op);
896 }
897 } else if (st_op) {
898 // a Store
899 // inputs are (0:control, 1:memory, 2:address, 3:value)
900 if (!(n->ideal_Opcode()==st_op) && // Following are special cases
901 !(n->ideal_Opcode()==Op_StoreCM && st_op==Op_StoreB) &&
902 !(n->ideal_Opcode()==Op_StoreI && st_op==Op_StoreF) &&
903 !(n->ideal_Opcode()==Op_StoreF && st_op==Op_StoreI) &&
904 !(n->ideal_Opcode()==Op_StoreL && st_op==Op_StoreI) &&
905 !(n->ideal_Opcode()==Op_StoreVector && st_op==Op_StoreD) &&
906 !(n->ideal_Opcode()==Op_StoreD && st_op==Op_StoreI && n->rule() == storeD0_rule)) {
907 verify_oops_warning(n, n->ideal_Opcode(), st_op);
908 }
909 }
910
911 if (src2_enc == R_G0_enc && n->rule() != loadUB_rule && n->ideal_Opcode() != Op_StoreCM ) {
912 Node* addr = n->in(2);
913 if (!(addr->is_Mach() && addr->as_Mach()->ideal_Opcode() == Op_AddP)) {
914 const TypeOopPtr* atype = addr->bottom_type()->isa_instptr(); // %%% oopptr?
915 if (atype != NULL) {
916 intptr_t offset = get_offset_from_base(n, atype, disp32);
917 intptr_t offset_2 = get_offset_from_base_2(n, atype, disp32);
918 if (offset != offset_2) {
919 get_offset_from_base(n, atype, disp32);
920 get_offset_from_base_2(n, atype, disp32);
921 }
922 assert(offset == offset_2, "different offsets");
923 if (offset == disp32) {
924 // we now know that src1 is a true oop pointer
925 is_verified_oop_base = true;
926 if (ld_op && src1_enc == dst_enc && ld_op != Op_LoadF && ld_op != Op_LoadD) {
927 if( primary == Assembler::ldd_op3 ) {
928 is_verified_oop_base = false; // Cannot 'ldd' into O7
929 } else {
930 tmp_enc = dst_enc;
931 dst_enc = R_O7_enc; // Load into O7; preserve source oop
932 assert(src1_enc != dst_enc, "");
933 }
934 }
935 }
936 if (st_op && (( offset == oopDesc::klass_offset_in_bytes())
937 || offset == oopDesc::mark_offset_in_bytes())) {
938 // loading the mark should not be allowed either, but
939 // we don't check this since it conflicts with InlineObjectHash
940 // usage of LoadINode to get the mark. We could keep the
941 // check if we create a new LoadMarkNode
942 // but do not verify the object before its header is initialized
943 ShouldNotReachHere();
944 }
945 }
946 }
947 }
948 }
949 #endif
950
951 uint instr;
952 instr = (Assembler::ldst_op << 30)
953 | (dst_enc << 25)
954 | (primary << 19)
955 | (src1_enc << 14);
956
957 uint index = src2_enc;
958 int disp = disp32;
959
960 if (src1_enc == R_SP_enc || src1_enc == R_FP_enc) {
961 disp += STACK_BIAS;
962 // Quick fix for JDK-8029668: check that stack offset fits, bailout if not
963 if (!Assembler::is_simm13(disp)) {
964 ra->C->record_method_not_compilable("unable to handle large constant offsets");
965 return;
966 }
967 }
968
969 // We should have a compiler bailout here rather than a guarantee.
970 // Better yet would be some mechanism to handle variable-size matches correctly.
971 guarantee(Assembler::is_simm13(disp), "Do not match large constant offsets" );
972
973 if( disp == 0 ) {
974 // use reg-reg form
975 // bit 13 is already zero
976 instr |= index;
977 } else {
978 // use reg-imm form
979 instr |= 0x00002000; // set bit 13 to one
980 instr |= disp & 0x1FFF;
981 }
982
983 cbuf.insts()->emit_int32(instr);
984
985 #ifdef ASSERT
986 {
987 MacroAssembler _masm(&cbuf);
988 if (is_verified_oop_base) {
989 __ verify_oop(reg_to_register_object(src1_enc));
990 }
991 if (is_verified_oop_store) {
992 __ verify_oop(reg_to_register_object(dst_enc));
993 }
994 if (tmp_enc != -1) {
995 __ mov(O7, reg_to_register_object(tmp_enc));
996 }
997 if (is_verified_oop_load) {
998 __ verify_oop(reg_to_register_object(dst_enc));
999 }
1000 }
1001 #endif
1002 }
1003
1004 void emit_call_reloc(CodeBuffer &cbuf, intptr_t entry_point, relocInfo::relocType rtype, bool preserve_g2 = false) {
1005 // The method which records debug information at every safepoint
1006 // expects the call to be the first instruction in the snippet as
1007 // it creates a PcDesc structure which tracks the offset of a call
1008 // from the start of the codeBlob. This offset is computed as
1009 // code_end() - code_begin() of the code which has been emitted
1010 // so far.
1011 // In this particular case we have skirted around the problem by
1012 // putting the "mov" instruction in the delay slot but the problem
1013 // may bite us again at some other point and a cleaner/generic
1014 // solution using relocations would be needed.
1015 MacroAssembler _masm(&cbuf);
1016 __ set_inst_mark();
1017
1018 // We flush the current window just so that there is a valid stack copy
1019 // the fact that the current window becomes active again instantly is
1020 // not a problem there is nothing live in it.
1021
1022 #ifdef ASSERT
1023 int startpos = __ offset();
1024 #endif /* ASSERT */
1025
1026 __ call((address)entry_point, rtype);
1027
1028 if (preserve_g2) __ delayed()->mov(G2, L7);
1029 else __ delayed()->nop();
1030
1031 if (preserve_g2) __ mov(L7, G2);
1032
1033 #ifdef ASSERT
1034 if (preserve_g2 && (VerifyCompiledCode || VerifyOops)) {
1035 #ifdef _LP64
1036 // Trash argument dump slots.
1037 __ set(0xb0b8ac0db0b8ac0d, G1);
1038 __ mov(G1, G5);
1039 __ stx(G1, SP, STACK_BIAS + 0x80);
1040 __ stx(G1, SP, STACK_BIAS + 0x88);
1041 __ stx(G1, SP, STACK_BIAS + 0x90);
1042 __ stx(G1, SP, STACK_BIAS + 0x98);
1043 __ stx(G1, SP, STACK_BIAS + 0xA0);
1044 __ stx(G1, SP, STACK_BIAS + 0xA8);
1045 #else // _LP64
1046 // this is also a native call, so smash the first 7 stack locations,
1047 // and the various registers
1048
1049 // Note: [SP+0x40] is sp[callee_aggregate_return_pointer_sp_offset],
1050 // while [SP+0x44..0x58] are the argument dump slots.
1051 __ set((intptr_t)0xbaadf00d, G1);
1052 __ mov(G1, G5);
1053 __ sllx(G1, 32, G1);
1054 __ or3(G1, G5, G1);
1055 __ mov(G1, G5);
1056 __ stx(G1, SP, 0x40);
1057 __ stx(G1, SP, 0x48);
1058 __ stx(G1, SP, 0x50);
1059 __ stw(G1, SP, 0x58); // Do not trash [SP+0x5C] which is a usable spill slot
1060 #endif // _LP64
1061 }
1062 #endif /*ASSERT*/
1063 }
1064
1065 //=============================================================================
1066 // REQUIRED FUNCTIONALITY for encoding
1067 void emit_lo(CodeBuffer &cbuf, int val) { }
1068 void emit_hi(CodeBuffer &cbuf, int val) { }
1069
1070
1071 //=============================================================================
1072 const RegMask& MachConstantBaseNode::_out_RegMask = PTR_REG_mask();
1073
1074 int Compile::ConstantTable::calculate_table_base_offset() const {
1075 if (UseRDPCForConstantTableBase) {
1076 // The table base offset might be less but then it fits into
1077 // simm13 anyway and we are good (cf. MachConstantBaseNode::emit).
1078 return Assembler::min_simm13();
1079 } else {
1080 int offset = -(size() / 2);
1081 if (!Assembler::is_simm13(offset)) {
1082 offset = Assembler::min_simm13();
1083 }
1084 return offset;
1085 }
1086 }
1087
1088 bool MachConstantBaseNode::requires_postalloc_expand() const { return false; }
1089 void MachConstantBaseNode::postalloc_expand(GrowableArray <Node *> *nodes, PhaseRegAlloc *ra_) {
1090 ShouldNotReachHere();
1091 }
1092
1093 void MachConstantBaseNode::emit(CodeBuffer& cbuf, PhaseRegAlloc* ra_) const {
1094 Compile* C = ra_->C;
1095 Compile::ConstantTable& constant_table = C->constant_table();
1096 MacroAssembler _masm(&cbuf);
1097
1098 Register r = as_Register(ra_->get_encode(this));
1099 CodeSection* consts_section = __ code()->consts();
1100 int consts_size = consts_section->align_at_start(consts_section->size());
1101 assert(constant_table.size() == consts_size, err_msg("must be: %d == %d", constant_table.size(), consts_size));
1102
1103 if (UseRDPCForConstantTableBase) {
1104 // For the following RDPC logic to work correctly the consts
1105 // section must be allocated right before the insts section. This
1106 // assert checks for that. The layout and the SECT_* constants
1107 // are defined in src/share/vm/asm/codeBuffer.hpp.
1108 assert(CodeBuffer::SECT_CONSTS + 1 == CodeBuffer::SECT_INSTS, "must be");
1109 int insts_offset = __ offset();
1110
1111 // Layout:
1112 //
1113 // |----------- consts section ------------|----------- insts section -----------...
1114 // |------ constant table -----|- padding -|------------------x----
1115 // \ current PC (RDPC instruction)
1116 // |<------------- consts_size ----------->|<- insts_offset ->|
1117 // \ table base
1118 // The table base offset is later added to the load displacement
1119 // so it has to be negative.
1120 int table_base_offset = -(consts_size + insts_offset);
1121 int disp;
1122
1123 // If the displacement from the current PC to the constant table
1124 // base fits into simm13 we set the constant table base to the
1125 // current PC.
1126 if (Assembler::is_simm13(table_base_offset)) {
1127 constant_table.set_table_base_offset(table_base_offset);
1128 disp = 0;
1129 } else {
1130 // Otherwise we set the constant table base offset to the
1131 // maximum negative displacement of load instructions to keep
1132 // the disp as small as possible:
1133 //
1134 // |<------------- consts_size ----------->|<- insts_offset ->|
1135 // |<--------- min_simm13 --------->|<-------- disp --------->|
1136 // \ table base
1137 table_base_offset = Assembler::min_simm13();
1138 constant_table.set_table_base_offset(table_base_offset);
1139 disp = (consts_size + insts_offset) + table_base_offset;
1140 }
1141
1142 __ rdpc(r);
1143
1144 if (disp != 0) {
1145 assert(r != O7, "need temporary");
1146 __ sub(r, __ ensure_simm13_or_reg(disp, O7), r);
1147 }
1148 }
1149 else {
1150 // Materialize the constant table base.
1151 address baseaddr = consts_section->start() + -(constant_table.table_base_offset());
1152 RelocationHolder rspec = internal_word_Relocation::spec(baseaddr);
1153 AddressLiteral base(baseaddr, rspec);
1154 __ set(base, r);
1155 }
1156 }
1157
1158 uint MachConstantBaseNode::size(PhaseRegAlloc*) const {
1159 if (UseRDPCForConstantTableBase) {
1160 // This is really the worst case but generally it's only 1 instruction.
1161 return (1 /*rdpc*/ + 1 /*sub*/ + MacroAssembler::worst_case_insts_for_set()) * BytesPerInstWord;
1162 } else {
1163 return MacroAssembler::worst_case_insts_for_set() * BytesPerInstWord;
1164 }
1165 }
1166
1167 #ifndef PRODUCT
1168 void MachConstantBaseNode::format(PhaseRegAlloc* ra_, outputStream* st) const {
1169 char reg[128];
1170 ra_->dump_register(this, reg);
1171 if (UseRDPCForConstantTableBase) {
1172 st->print("RDPC %s\t! constant table base", reg);
1173 } else {
1174 st->print("SET &constanttable,%s\t! constant table base", reg);
1175 }
1176 }
1177 #endif
1178
1179
1180 //=============================================================================
1181
1182 #ifndef PRODUCT
1183 void MachPrologNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1184 Compile* C = ra_->C;
1185
1186 for (int i = 0; i < OptoPrologueNops; i++) {
1187 st->print_cr("NOP"); st->print("\t");
1188 }
1189
1190 if( VerifyThread ) {
1191 st->print_cr("Verify_Thread"); st->print("\t");
1192 }
1193
1194 size_t framesize = C->frame_size_in_bytes();
1195 int bangsize = C->bang_size_in_bytes();
1196
1197 // Calls to C2R adapters often do not accept exceptional returns.
1198 // We require that their callers must bang for them. But be careful, because
1199 // some VM calls (such as call site linkage) can use several kilobytes of
1200 // stack. But the stack safety zone should account for that.
1201 // See bugs 4446381, 4468289, 4497237.
1202 if (C->need_stack_bang(bangsize)) {
1203 st->print_cr("! stack bang (%d bytes)", bangsize); st->print("\t");
1204 }
1205
1206 if (Assembler::is_simm13(-framesize)) {
1207 st->print ("SAVE R_SP,-" SIZE_FORMAT ",R_SP",framesize);
1208 } else {
1209 st->print_cr("SETHI R_SP,hi%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1210 st->print_cr("ADD R_G3,lo%%(-" SIZE_FORMAT "),R_G3",framesize); st->print("\t");
1211 st->print ("SAVE R_SP,R_G3,R_SP");
1212 }
1213
1214 }
1215 #endif
1216
1217 void MachPrologNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1218 Compile* C = ra_->C;
1219 MacroAssembler _masm(&cbuf);
1220
1221 for (int i = 0; i < OptoPrologueNops; i++) {
1222 __ nop();
1223 }
1224
1225 __ verify_thread();
1226
1227 size_t framesize = C->frame_size_in_bytes();
1228 assert(framesize >= 16*wordSize, "must have room for reg. save area");
1229 assert(framesize%(2*wordSize) == 0, "must preserve 2*wordSize alignment");
1230 int bangsize = C->bang_size_in_bytes();
1231
1232 // Calls to C2R adapters often do not accept exceptional returns.
1233 // We require that their callers must bang for them. But be careful, because
1234 // some VM calls (such as call site linkage) can use several kilobytes of
1235 // stack. But the stack safety zone should account for that.
1236 // See bugs 4446381, 4468289, 4497237.
1237 if (C->need_stack_bang(bangsize)) {
1238 __ generate_stack_overflow_check(bangsize);
1239 }
1240
1241 if (Assembler::is_simm13(-framesize)) {
1242 __ save(SP, -framesize, SP);
1243 } else {
1244 __ sethi(-framesize & ~0x3ff, G3);
1245 __ add(G3, -framesize & 0x3ff, G3);
1246 __ save(SP, G3, SP);
1247 }
1248 C->set_frame_complete( __ offset() );
1249
1250 if (!UseRDPCForConstantTableBase && C->has_mach_constant_base_node()) {
1251 // NOTE: We set the table base offset here because users might be
1252 // emitted before MachConstantBaseNode.
1253 Compile::ConstantTable& constant_table = C->constant_table();
1254 constant_table.set_table_base_offset(constant_table.calculate_table_base_offset());
1255 }
1256 }
1257
1258 uint MachPrologNode::size(PhaseRegAlloc *ra_) const {
1259 return MachNode::size(ra_);
1260 }
1261
1262 int MachPrologNode::reloc() const {
1263 return 10; // a large enough number
1264 }
1265
1266 //=============================================================================
1267 #ifndef PRODUCT
1268 void MachEpilogNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1269 Compile* C = ra_->C;
1270
1271 if(do_polling() && ra_->C->is_method_compilation()) {
1272 st->print("SETHI #PollAddr,L0\t! Load Polling address\n\t");
1273 #ifdef _LP64
1274 st->print("LDX [L0],G0\t!Poll for Safepointing\n\t");
1275 #else
1276 st->print("LDUW [L0],G0\t!Poll for Safepointing\n\t");
1277 #endif
1278 }
1279
1280 if(do_polling()) {
1281 if (UseCBCond && !ra_->C->is_method_compilation()) {
1282 st->print("NOP\n\t");
1283 }
1284 st->print("RET\n\t");
1285 }
1286
1287 st->print("RESTORE");
1288 }
1289 #endif
1290
1291 void MachEpilogNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1292 MacroAssembler _masm(&cbuf);
1293 Compile* C = ra_->C;
1294
1295 __ verify_thread();
1296
1297 // If this does safepoint polling, then do it here
1298 if(do_polling() && ra_->C->is_method_compilation()) {
1299 AddressLiteral polling_page(os::get_polling_page());
1300 __ sethi(polling_page, L0);
1301 __ relocate(relocInfo::poll_return_type);
1302 __ ld_ptr(L0, 0, G0);
1303 }
1304
1305 // If this is a return, then stuff the restore in the delay slot
1306 if(do_polling()) {
1307 if (UseCBCond && !ra_->C->is_method_compilation()) {
1308 // Insert extra padding for the case when the epilogue is preceded by
1309 // a cbcond jump, which can't be followed by a CTI instruction
1310 __ nop();
1311 }
1312 __ ret();
1313 __ delayed()->restore();
1314 } else {
1315 __ restore();
1316 }
1317 }
1318
1319 uint MachEpilogNode::size(PhaseRegAlloc *ra_) const {
1320 return MachNode::size(ra_);
1321 }
1322
1323 int MachEpilogNode::reloc() const {
1324 return 16; // a large enough number
1325 }
1326
1327 const Pipeline * MachEpilogNode::pipeline() const {
1328 return MachNode::pipeline_class();
1329 }
1330
1331 int MachEpilogNode::safepoint_offset() const {
1332 assert( do_polling(), "no return for this epilog node");
1333 return MacroAssembler::insts_for_sethi(os::get_polling_page()) * BytesPerInstWord;
1334 }
1335
1336 //=============================================================================
1337
1338 // Figure out which register class each belongs in: rc_int, rc_float, rc_stack
1339 enum RC { rc_bad, rc_int, rc_float, rc_stack };
1340 static enum RC rc_class( OptoReg::Name reg ) {
1341 if( !OptoReg::is_valid(reg) ) return rc_bad;
1342 if (OptoReg::is_stack(reg)) return rc_stack;
1343 VMReg r = OptoReg::as_VMReg(reg);
1344 if (r->is_Register()) return rc_int;
1345 assert(r->is_FloatRegister(), "must be");
1346 return rc_float;
1347 }
1348
1349 static int impl_helper(const MachNode* mach, CodeBuffer* cbuf, PhaseRegAlloc* ra, bool do_size, bool is_load, int offset, int reg, int opcode, const char *op_str, int size, outputStream* st ) {
1350 if (cbuf) {
1351 emit_form3_mem_reg(*cbuf, ra, mach, opcode, -1, R_SP_enc, offset, 0, Matcher::_regEncode[reg]);
1352 }
1353 #ifndef PRODUCT
1354 else if (!do_size) {
1355 if (size != 0) st->print("\n\t");
1356 if (is_load) st->print("%s [R_SP + #%d],R_%s\t! spill",op_str,offset,OptoReg::regname(reg));
1357 else st->print("%s R_%s,[R_SP + #%d]\t! spill",op_str,OptoReg::regname(reg),offset);
1358 }
1359 #endif
1360 return size+4;
1361 }
1362
1363 static int impl_mov_helper( CodeBuffer *cbuf, bool do_size, int src, int dst, int op1, int op2, const char *op_str, int size, outputStream* st ) {
1364 if( cbuf ) emit3( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst], op1, 0, op2, Matcher::_regEncode[src] );
1365 #ifndef PRODUCT
1366 else if( !do_size ) {
1367 if( size != 0 ) st->print("\n\t");
1368 st->print("%s R_%s,R_%s\t! spill",op_str,OptoReg::regname(src),OptoReg::regname(dst));
1369 }
1370 #endif
1371 return size+4;
1372 }
1373
1374 uint MachSpillCopyNode::implementation( CodeBuffer *cbuf,
1375 PhaseRegAlloc *ra_,
1376 bool do_size,
1377 outputStream* st ) const {
1378 // Get registers to move
1379 OptoReg::Name src_second = ra_->get_reg_second(in(1));
1380 OptoReg::Name src_first = ra_->get_reg_first(in(1));
1381 OptoReg::Name dst_second = ra_->get_reg_second(this );
1382 OptoReg::Name dst_first = ra_->get_reg_first(this );
1383
1384 enum RC src_second_rc = rc_class(src_second);
1385 enum RC src_first_rc = rc_class(src_first);
1386 enum RC dst_second_rc = rc_class(dst_second);
1387 enum RC dst_first_rc = rc_class(dst_first);
1388
1389 assert( OptoReg::is_valid(src_first) && OptoReg::is_valid(dst_first), "must move at least 1 register" );
1390
1391 // Generate spill code!
1392 int size = 0;
1393
1394 if( src_first == dst_first && src_second == dst_second )
1395 return size; // Self copy, no move
1396
1397 // --------------------------------------
1398 // Check for mem-mem move. Load into unused float registers and fall into
1399 // the float-store case.
1400 if( src_first_rc == rc_stack && dst_first_rc == rc_stack ) {
1401 int offset = ra_->reg2offset(src_first);
1402 // Further check for aligned-adjacent pair, so we can use a double load
1403 if( (src_first&1)==0 && src_first+1 == src_second ) {
1404 src_second = OptoReg::Name(R_F31_num);
1405 src_second_rc = rc_float;
1406 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::lddf_op3,"LDDF",size, st);
1407 } else {
1408 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F30_num,Assembler::ldf_op3 ,"LDF ",size, st);
1409 }
1410 src_first = OptoReg::Name(R_F30_num);
1411 src_first_rc = rc_float;
1412 }
1413
1414 if( src_second_rc == rc_stack && dst_second_rc == rc_stack ) {
1415 int offset = ra_->reg2offset(src_second);
1416 size = impl_helper(this,cbuf,ra_,do_size,true,offset,R_F31_num,Assembler::ldf_op3,"LDF ",size, st);
1417 src_second = OptoReg::Name(R_F31_num);
1418 src_second_rc = rc_float;
1419 }
1420
1421 // --------------------------------------
1422 // Check for float->int copy; requires a trip through memory
1423 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS < 3) {
1424 int offset = frame::register_save_words*wordSize;
1425 if (cbuf) {
1426 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::sub_op3, R_SP_enc, 16 );
1427 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1428 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1429 emit3_simm13( *cbuf, Assembler::arith_op, R_SP_enc, Assembler::add_op3, R_SP_enc, 16 );
1430 }
1431 #ifndef PRODUCT
1432 else if (!do_size) {
1433 if (size != 0) st->print("\n\t");
1434 st->print( "SUB R_SP,16,R_SP\n");
1435 impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1436 impl_helper(this,cbuf,ra_,do_size,true ,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1437 st->print("\tADD R_SP,16,R_SP\n");
1438 }
1439 #endif
1440 size += 16;
1441 }
1442
1443 // Check for float->int copy on T4
1444 if (src_first_rc == rc_float && dst_first_rc == rc_int && UseVIS >= 3) {
1445 // Further check for aligned-adjacent pair, so we can use a double move
1446 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1447 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mdtox_opf,"MOVDTOX",size, st);
1448 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mstouw_opf,"MOVSTOUW",size, st);
1449 }
1450 // Check for int->float copy on T4
1451 if (src_first_rc == rc_int && dst_first_rc == rc_float && UseVIS >= 3) {
1452 // Further check for aligned-adjacent pair, so we can use a double move
1453 if ((src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second)
1454 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mxtod_opf,"MOVXTOD",size, st);
1455 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::mftoi_op3,Assembler::mwtos_opf,"MOVWTOS",size, st);
1456 }
1457
1458 // --------------------------------------
1459 // In the 32-bit 1-reg-longs build ONLY, I see mis-aligned long destinations.
1460 // In such cases, I have to do the big-endian swap. For aligned targets, the
1461 // hardware does the flop for me. Doubles are always aligned, so no problem
1462 // there. Misaligned sources only come from native-long-returns (handled
1463 // special below).
1464 #ifndef _LP64
1465 if( src_first_rc == rc_int && // source is already big-endian
1466 src_second_rc != rc_bad && // 64-bit move
1467 ((dst_first&1)!=0 || dst_second != dst_first+1) ) { // misaligned dst
1468 assert( (src_first&1)==0 && src_second == src_first+1, "source must be aligned" );
1469 // Do the big-endian flop.
1470 OptoReg::Name tmp = dst_first ; dst_first = dst_second ; dst_second = tmp ;
1471 enum RC tmp_rc = dst_first_rc; dst_first_rc = dst_second_rc; dst_second_rc = tmp_rc;
1472 }
1473 #endif
1474
1475 // --------------------------------------
1476 // Check for integer reg-reg copy
1477 if( src_first_rc == rc_int && dst_first_rc == rc_int ) {
1478 #ifndef _LP64
1479 if( src_first == R_O0_num && src_second == R_O1_num ) { // Check for the evil O0/O1 native long-return case
1480 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1481 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1482 // operand contains the least significant word of the 64-bit value and vice versa.
1483 OptoReg::Name tmp = OptoReg::Name(R_O7_num);
1484 assert( (dst_first&1)==0 && dst_second == dst_first+1, "return a native O0/O1 long to an aligned-adjacent 64-bit reg" );
1485 // Shift O0 left in-place, zero-extend O1, then OR them into the dst
1486 if( cbuf ) {
1487 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tmp], Assembler::sllx_op3, Matcher::_regEncode[src_first], 0x1020 );
1488 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[src_second], Assembler::srl_op3, Matcher::_regEncode[src_second], 0x0000 );
1489 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler:: or_op3, Matcher::_regEncode[tmp], 0, Matcher::_regEncode[src_second] );
1490 #ifndef PRODUCT
1491 } else if( !do_size ) {
1492 if( size != 0 ) st->print("\n\t");
1493 st->print("SLLX R_%s,32,R_%s\t! Move O0-first to O7-high\n\t", OptoReg::regname(src_first), OptoReg::regname(tmp));
1494 st->print("SRL R_%s, 0,R_%s\t! Zero-extend O1\n\t", OptoReg::regname(src_second), OptoReg::regname(src_second));
1495 st->print("OR R_%s,R_%s,R_%s\t! spill",OptoReg::regname(tmp), OptoReg::regname(src_second), OptoReg::regname(dst_first));
1496 #endif
1497 }
1498 return size+12;
1499 }
1500 else if( dst_first == R_I0_num && dst_second == R_I1_num ) {
1501 // returning a long value in I0/I1
1502 // a SpillCopy must be able to target a return instruction's reg_class
1503 // Note: The _first and _second suffixes refer to the addresses of the the 2 halves of the 64-bit value
1504 // as stored in memory. On a big-endian machine like SPARC, this means that the _second
1505 // operand contains the least significant word of the 64-bit value and vice versa.
1506 OptoReg::Name tdest = dst_first;
1507
1508 if (src_first == dst_first) {
1509 tdest = OptoReg::Name(R_O7_num);
1510 size += 4;
1511 }
1512
1513 if( cbuf ) {
1514 assert( (src_first&1) == 0 && (src_first+1) == src_second, "return value was in an aligned-adjacent 64-bit reg");
1515 // Shift value in upper 32-bits of src to lower 32-bits of I0; move lower 32-bits to I1
1516 // ShrL_reg_imm6
1517 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[tdest], Assembler::srlx_op3, Matcher::_regEncode[src_second], 32 | 0x1000 );
1518 // ShrR_reg_imm6 src, 0, dst
1519 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srl_op3, Matcher::_regEncode[src_first], 0x0000 );
1520 if (tdest != dst_first) {
1521 emit3 ( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_first], Assembler::or_op3, 0/*G0*/, 0/*op2*/, Matcher::_regEncode[tdest] );
1522 }
1523 }
1524 #ifndef PRODUCT
1525 else if( !do_size ) {
1526 if( size != 0 ) st->print("\n\t"); // %%%%% !!!!!
1527 st->print("SRLX R_%s,32,R_%s\t! Extract MSW\n\t",OptoReg::regname(src_second),OptoReg::regname(tdest));
1528 st->print("SRL R_%s, 0,R_%s\t! Extract LSW\n\t",OptoReg::regname(src_first),OptoReg::regname(dst_second));
1529 if (tdest != dst_first) {
1530 st->print("MOV R_%s,R_%s\t! spill\n\t", OptoReg::regname(tdest), OptoReg::regname(dst_first));
1531 }
1532 }
1533 #endif // PRODUCT
1534 return size+8;
1535 }
1536 #endif // !_LP64
1537 // Else normal reg-reg copy
1538 assert( src_second != dst_first, "smashed second before evacuating it" );
1539 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::or_op3,0,"MOV ",size, st);
1540 assert( (src_first&1) == 0 && (dst_first&1) == 0, "never move second-halves of int registers" );
1541 // This moves an aligned adjacent pair.
1542 // See if we are done.
1543 if( src_first+1 == src_second && dst_first+1 == dst_second )
1544 return size;
1545 }
1546
1547 // Check for integer store
1548 if( src_first_rc == rc_int && dst_first_rc == rc_stack ) {
1549 int offset = ra_->reg2offset(dst_first);
1550 // Further check for aligned-adjacent pair, so we can use a double store
1551 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1552 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stx_op3,"STX ",size, st);
1553 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stw_op3,"STW ",size, st);
1554 }
1555
1556 // Check for integer load
1557 if( dst_first_rc == rc_int && src_first_rc == rc_stack ) {
1558 int offset = ra_->reg2offset(src_first);
1559 // Further check for aligned-adjacent pair, so we can use a double load
1560 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1561 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldx_op3 ,"LDX ",size, st);
1562 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lduw_op3,"LDUW",size, st);
1563 }
1564
1565 // Check for float reg-reg copy
1566 if( src_first_rc == rc_float && dst_first_rc == rc_float ) {
1567 // Further check for aligned-adjacent pair, so we can use a double move
1568 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1569 return impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovd_opf,"FMOVD",size, st);
1570 size = impl_mov_helper(cbuf,do_size,src_first,dst_first,Assembler::fpop1_op3,Assembler::fmovs_opf,"FMOVS",size, st);
1571 }
1572
1573 // Check for float store
1574 if( src_first_rc == rc_float && dst_first_rc == rc_stack ) {
1575 int offset = ra_->reg2offset(dst_first);
1576 // Further check for aligned-adjacent pair, so we can use a double store
1577 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1578 return impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stdf_op3,"STDF",size, st);
1579 size = impl_helper(this,cbuf,ra_,do_size,false,offset,src_first,Assembler::stf_op3 ,"STF ",size, st);
1580 }
1581
1582 // Check for float load
1583 if( dst_first_rc == rc_float && src_first_rc == rc_stack ) {
1584 int offset = ra_->reg2offset(src_first);
1585 // Further check for aligned-adjacent pair, so we can use a double load
1586 if( (src_first&1)==0 && src_first+1 == src_second && (dst_first&1)==0 && dst_first+1 == dst_second )
1587 return impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::lddf_op3,"LDDF",size, st);
1588 size = impl_helper(this,cbuf,ra_,do_size,true,offset,dst_first,Assembler::ldf_op3 ,"LDF ",size, st);
1589 }
1590
1591 // --------------------------------------------------------------------
1592 // Check for hi bits still needing moving. Only happens for misaligned
1593 // arguments to native calls.
1594 if( src_second == dst_second )
1595 return size; // Self copy; no move
1596 assert( src_second_rc != rc_bad && dst_second_rc != rc_bad, "src_second & dst_second cannot be Bad" );
1597
1598 #ifndef _LP64
1599 // In the LP64 build, all registers can be moved as aligned/adjacent
1600 // pairs, so there's never any need to move the high bits separately.
1601 // The 32-bit builds have to deal with the 32-bit ABI which can force
1602 // all sorts of silly alignment problems.
1603
1604 // Check for integer reg-reg copy. Hi bits are stuck up in the top
1605 // 32-bits of a 64-bit register, but are needed in low bits of another
1606 // register (else it's a hi-bits-to-hi-bits copy which should have
1607 // happened already as part of a 64-bit move)
1608 if( src_second_rc == rc_int && dst_second_rc == rc_int ) {
1609 assert( (src_second&1)==1, "its the evil O0/O1 native return case" );
1610 assert( (dst_second&1)==0, "should have moved with 1 64-bit move" );
1611 // Shift src_second down to dst_second's low bits.
1612 if( cbuf ) {
1613 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[dst_second], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1614 #ifndef PRODUCT
1615 } else if( !do_size ) {
1616 if( size != 0 ) st->print("\n\t");
1617 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(dst_second));
1618 #endif
1619 }
1620 return size+4;
1621 }
1622
1623 // Check for high word integer store. Must down-shift the hi bits
1624 // into a temp register, then fall into the case of storing int bits.
1625 if( src_second_rc == rc_int && dst_second_rc == rc_stack && (src_second&1)==1 ) {
1626 // Shift src_second down to dst_second's low bits.
1627 if( cbuf ) {
1628 emit3_simm13( *cbuf, Assembler::arith_op, Matcher::_regEncode[R_O7_num], Assembler::srlx_op3, Matcher::_regEncode[src_second-1], 0x1020 );
1629 #ifndef PRODUCT
1630 } else if( !do_size ) {
1631 if( size != 0 ) st->print("\n\t");
1632 st->print("SRLX R_%s,32,R_%s\t! spill: Move high bits down low",OptoReg::regname(src_second-1),OptoReg::regname(R_O7_num));
1633 #endif
1634 }
1635 size+=4;
1636 src_second = OptoReg::Name(R_O7_num); // Not R_O7H_num!
1637 }
1638
1639 // Check for high word integer load
1640 if( dst_second_rc == rc_int && src_second_rc == rc_stack )
1641 return impl_helper(this,cbuf,ra_,do_size,true ,ra_->reg2offset(src_second),dst_second,Assembler::lduw_op3,"LDUW",size, st);
1642
1643 // Check for high word integer store
1644 if( src_second_rc == rc_int && dst_second_rc == rc_stack )
1645 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stw_op3 ,"STW ",size, st);
1646
1647 // Check for high word float store
1648 if( src_second_rc == rc_float && dst_second_rc == rc_stack )
1649 return impl_helper(this,cbuf,ra_,do_size,false,ra_->reg2offset(dst_second),src_second,Assembler::stf_op3 ,"STF ",size, st);
1650
1651 #endif // !_LP64
1652
1653 Unimplemented();
1654 }
1655
1656 #ifndef PRODUCT
1657 void MachSpillCopyNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1658 implementation( NULL, ra_, false, st );
1659 }
1660 #endif
1661
1662 void MachSpillCopyNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1663 implementation( &cbuf, ra_, false, NULL );
1664 }
1665
1666 uint MachSpillCopyNode::size(PhaseRegAlloc *ra_) const {
1667 return implementation( NULL, ra_, true, NULL );
1668 }
1669
1670 //=============================================================================
1671 #ifndef PRODUCT
1672 void MachNopNode::format( PhaseRegAlloc *, outputStream *st ) const {
1673 st->print("NOP \t# %d bytes pad for loops and calls", 4 * _count);
1674 }
1675 #endif
1676
1677 void MachNopNode::emit(CodeBuffer &cbuf, PhaseRegAlloc * ) const {
1678 MacroAssembler _masm(&cbuf);
1679 for(int i = 0; i < _count; i += 1) {
1680 __ nop();
1681 }
1682 }
1683
1684 uint MachNopNode::size(PhaseRegAlloc *ra_) const {
1685 return 4 * _count;
1686 }
1687
1688
1689 //=============================================================================
1690 #ifndef PRODUCT
1691 void BoxLockNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1692 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem());
1693 int reg = ra_->get_reg_first(this);
1694 st->print("LEA [R_SP+#%d+BIAS],%s",offset,Matcher::regName[reg]);
1695 }
1696 #endif
1697
1698 void BoxLockNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1699 MacroAssembler _masm(&cbuf);
1700 int offset = ra_->reg2offset(in_RegMask(0).find_first_elem()) + STACK_BIAS;
1701 int reg = ra_->get_encode(this);
1702
1703 if (Assembler::is_simm13(offset)) {
1704 __ add(SP, offset, reg_to_register_object(reg));
1705 } else {
1706 __ set(offset, O7);
1707 __ add(SP, O7, reg_to_register_object(reg));
1708 }
1709 }
1710
1711 uint BoxLockNode::size(PhaseRegAlloc *ra_) const {
1712 // BoxLockNode is not a MachNode, so we can't just call MachNode::size(ra_)
1713 assert(ra_ == ra_->C->regalloc(), "sanity");
1714 return ra_->C->scratch_emit_size(this);
1715 }
1716
1717 //=============================================================================
1718 #ifndef PRODUCT
1719 void MachUEPNode::format( PhaseRegAlloc *ra_, outputStream *st ) const {
1720 st->print_cr("\nUEP:");
1721 #ifdef _LP64
1722 if (UseCompressedClassPointers) {
1723 assert(Universe::heap() != NULL, "java heap should be initialized");
1724 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check - compressed klass");
1725 if (Universe::narrow_klass_base() != 0) {
1726 st->print_cr("\tSET Universe::narrow_klass_base,R_G6_heap_base");
1727 if (Universe::narrow_klass_shift() != 0) {
1728 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1729 }
1730 st->print_cr("\tADD R_G5,R_G6_heap_base,R_G5");
1731 st->print_cr("\tSET Universe::narrow_ptrs_base,R_G6_heap_base");
1732 } else {
1733 st->print_cr("\tSLL R_G5,Universe::narrow_klass_shift,R_G5");
1734 }
1735 } else {
1736 st->print_cr("\tLDX [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1737 }
1738 st->print_cr("\tCMP R_G5,R_G3" );
1739 st->print ("\tTne xcc,R_G0+ST_RESERVED_FOR_USER_0+2");
1740 #else // _LP64
1741 st->print_cr("\tLDUW [R_O0 + oopDesc::klass_offset_in_bytes],R_G5\t! Inline cache check");
1742 st->print_cr("\tCMP R_G5,R_G3" );
1743 st->print ("\tTne icc,R_G0+ST_RESERVED_FOR_USER_0+2");
1744 #endif // _LP64
1745 }
1746 #endif
1747
1748 void MachUEPNode::emit(CodeBuffer &cbuf, PhaseRegAlloc *ra_) const {
1749 MacroAssembler _masm(&cbuf);
1750 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
1751 Register temp_reg = G3;
1752 assert( G5_ic_reg != temp_reg, "conflicting registers" );
1753
1754 // Load klass from receiver
1755 __ load_klass(O0, temp_reg);
1756 // Compare against expected klass
1757 __ cmp(temp_reg, G5_ic_reg);
1758 // Branch to miss code, checks xcc or icc depending
1759 __ trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2);
1760 }
1761
1762 uint MachUEPNode::size(PhaseRegAlloc *ra_) const {
1763 return MachNode::size(ra_);
1764 }
1765
1766
1767 //=============================================================================
1768
1769
1770 // Emit exception handler code.
1771 int HandlerImpl::emit_exception_handler(CodeBuffer& cbuf) {
1772 Register temp_reg = G3;
1773 AddressLiteral exception_blob(OptoRuntime::exception_blob()->entry_point());
1774 MacroAssembler _masm(&cbuf);
1775
1776 address base =
1777 __ start_a_stub(size_exception_handler());
1778 if (base == NULL) return 0; // CodeBuffer::expand failed
1779
1780 int offset = __ offset();
1781
1782 __ JUMP(exception_blob, temp_reg, 0); // sethi;jmp
1783 __ delayed()->nop();
1784
1785 assert(__ offset() - offset <= (int) size_exception_handler(), "overflow");
1786
1787 __ end_a_stub();
1788
1789 return offset;
1790 }
1791
1792 int HandlerImpl::emit_deopt_handler(CodeBuffer& cbuf) {
1793 // Can't use any of the current frame's registers as we may have deopted
1794 // at a poll and everything (including G3) can be live.
1795 Register temp_reg = L0;
1796 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack());
1797 MacroAssembler _masm(&cbuf);
1798
1799 address base =
1800 __ start_a_stub(size_deopt_handler());
1801 if (base == NULL) return 0; // CodeBuffer::expand failed
1802
1803 int offset = __ offset();
1804 __ save_frame(0);
1805 __ JUMP(deopt_blob, temp_reg, 0); // sethi;jmp
1806 __ delayed()->restore();
1807
1808 assert(__ offset() - offset <= (int) size_deopt_handler(), "overflow");
1809
1810 __ end_a_stub();
1811 return offset;
1812
1813 }
1814
1815 // Given a register encoding, produce a Integer Register object
1816 static Register reg_to_register_object(int register_encoding) {
1817 assert(L5->encoding() == R_L5_enc && G1->encoding() == R_G1_enc, "right coding");
1818 return as_Register(register_encoding);
1819 }
1820
1821 // Given a register encoding, produce a single-precision Float Register object
1822 static FloatRegister reg_to_SingleFloatRegister_object(int register_encoding) {
1823 assert(F5->encoding(FloatRegisterImpl::S) == R_F5_enc && F12->encoding(FloatRegisterImpl::S) == R_F12_enc, "right coding");
1824 return as_SingleFloatRegister(register_encoding);
1825 }
1826
1827 // Given a register encoding, produce a double-precision Float Register object
1828 static FloatRegister reg_to_DoubleFloatRegister_object(int register_encoding) {
1829 assert(F4->encoding(FloatRegisterImpl::D) == R_F4_enc, "right coding");
1830 assert(F32->encoding(FloatRegisterImpl::D) == R_D32_enc, "right coding");
1831 return as_DoubleFloatRegister(register_encoding);
1832 }
1833
1834 const bool Matcher::match_rule_supported(int opcode) {
1835 if (!has_match_rule(opcode))
1836 return false;
1837
1838 switch (opcode) {
1839 case Op_CountLeadingZerosI:
1840 case Op_CountLeadingZerosL:
1841 case Op_CountTrailingZerosI:
1842 case Op_CountTrailingZerosL:
1843 case Op_PopCountI:
1844 case Op_PopCountL:
1845 if (!UsePopCountInstruction)
1846 return false;
1847 case Op_CompareAndSwapL:
1848 #ifdef _LP64
1849 case Op_CompareAndSwapP:
1850 #endif
1851 if (!VM_Version::supports_cx8())
1852 return false;
1853 break;
1854 }
1855
1856 return true; // Per default match rules are supported.
1857 }
1858
1859 int Matcher::regnum_to_fpu_offset(int regnum) {
1860 return regnum - 32; // The FP registers are in the second chunk
1861 }
1862
1863 #ifdef ASSERT
1864 address last_rethrow = NULL; // debugging aid for Rethrow encoding
1865 #endif
1866
1867 // Vector width in bytes
1868 const int Matcher::vector_width_in_bytes(BasicType bt) {
1869 assert(MaxVectorSize == 8, "");
1870 return 8;
1871 }
1872
1873 // Vector ideal reg
1874 const int Matcher::vector_ideal_reg(int size) {
1875 assert(MaxVectorSize == 8, "");
1876 return Op_RegD;
1877 }
1878
1879 const int Matcher::vector_shift_count_ideal_reg(int size) {
1880 fatal("vector shift is not supported");
1881 return Node::NotAMachineReg;
1882 }
1883
1884 // Limits on vector size (number of elements) loaded into vector.
1885 const int Matcher::max_vector_size(const BasicType bt) {
1886 assert(is_java_primitive(bt), "only primitive type vectors");
1887 return vector_width_in_bytes(bt)/type2aelembytes(bt);
1888 }
1889
1890 const int Matcher::min_vector_size(const BasicType bt) {
1891 return max_vector_size(bt); // Same as max.
1892 }
1893
1894 // SPARC doesn't support misaligned vectors store/load.
1895 const bool Matcher::misaligned_vectors_ok() {
1896 return false;
1897 }
1898
1899 // Current (2013) SPARC platforms need to read original key
1900 // to construct decryption expanded key
1901 const bool Matcher::pass_original_key_for_aes() {
1902 return true;
1903 }
1904
1905 // USII supports fxtof through the whole range of number, USIII doesn't
1906 const bool Matcher::convL2FSupported(void) {
1907 return VM_Version::has_fast_fxtof();
1908 }
1909
1910 // Is this branch offset short enough that a short branch can be used?
1911 //
1912 // NOTE: If the platform does not provide any short branch variants, then
1913 // this method should return false for offset 0.
1914 bool Matcher::is_short_branch_offset(int rule, int br_size, int offset) {
1915 // The passed offset is relative to address of the branch.
1916 // Don't need to adjust the offset.
1917 return UseCBCond && Assembler::is_simm12(offset);
1918 }
1919
1920 const bool Matcher::isSimpleConstant64(jlong value) {
1921 // Will one (StoreL ConL) be cheaper than two (StoreI ConI)?.
1922 // Depends on optimizations in MacroAssembler::setx.
1923 int hi = (int)(value >> 32);
1924 int lo = (int)(value & ~0);
1925 return (hi == 0) || (hi == -1) || (lo == 0);
1926 }
1927
1928 // No scaling for the parameter the ClearArray node.
1929 const bool Matcher::init_array_count_is_in_bytes = true;
1930
1931 // Threshold size for cleararray.
1932 const int Matcher::init_array_short_size = 8 * BytesPerLong;
1933
1934 // No additional cost for CMOVL.
1935 const int Matcher::long_cmove_cost() { return 0; }
1936
1937 // CMOVF/CMOVD are expensive on T4 and on SPARC64.
1938 const int Matcher::float_cmove_cost() {
1939 return (VM_Version::is_T4() || VM_Version::is_sparc64()) ? ConditionalMoveLimit : 0;
1940 }
1941
1942 // Does the CPU require late expand (see block.cpp for description of late expand)?
1943 const bool Matcher::require_postalloc_expand = false;
1944
1945 // Should the Matcher clone shifts on addressing modes, expecting them to
1946 // be subsumed into complex addressing expressions or compute them into
1947 // registers? True for Intel but false for most RISCs
1948 const bool Matcher::clone_shift_expressions = false;
1949
1950 // Do we need to mask the count passed to shift instructions or does
1951 // the cpu only look at the lower 5/6 bits anyway?
1952 const bool Matcher::need_masked_shift_count = false;
1953
1954 bool Matcher::narrow_oop_use_complex_address() {
1955 NOT_LP64(ShouldNotCallThis());
1956 assert(UseCompressedOops, "only for compressed oops code");
1957 return false;
1958 }
1959
1960 bool Matcher::narrow_klass_use_complex_address() {
1961 NOT_LP64(ShouldNotCallThis());
1962 assert(UseCompressedClassPointers, "only for compressed klass code");
1963 return false;
1964 }
1965
1966 // Is it better to copy float constants, or load them directly from memory?
1967 // Intel can load a float constant from a direct address, requiring no
1968 // extra registers. Most RISCs will have to materialize an address into a
1969 // register first, so they would do better to copy the constant from stack.
1970 const bool Matcher::rematerialize_float_constants = false;
1971
1972 // If CPU can load and store mis-aligned doubles directly then no fixup is
1973 // needed. Else we split the double into 2 integer pieces and move it
1974 // piece-by-piece. Only happens when passing doubles into C code as the
1975 // Java calling convention forces doubles to be aligned.
1976 #ifdef _LP64
1977 const bool Matcher::misaligned_doubles_ok = true;
1978 #else
1979 const bool Matcher::misaligned_doubles_ok = false;
1980 #endif
1981
1982 // No-op on SPARC.
1983 void Matcher::pd_implicit_null_fixup(MachNode *node, uint idx) {
1984 }
1985
1986 // Advertise here if the CPU requires explicit rounding operations
1987 // to implement the UseStrictFP mode.
1988 const bool Matcher::strict_fp_requires_explicit_rounding = false;
1989
1990 // Are floats converted to double when stored to stack during deoptimization?
1991 // Sparc does not handle callee-save floats.
1992 bool Matcher::float_in_double() { return false; }
1993
1994 // Do ints take an entire long register or just half?
1995 // Note that we if-def off of _LP64.
1996 // The relevant question is how the int is callee-saved. In _LP64
1997 // the whole long is written but de-opt'ing will have to extract
1998 // the relevant 32 bits, in not-_LP64 only the low 32 bits is written.
1999 #ifdef _LP64
2000 const bool Matcher::int_in_long = true;
2001 #else
2002 const bool Matcher::int_in_long = false;
2003 #endif
2004
2005 // Return whether or not this register is ever used as an argument. This
2006 // function is used on startup to build the trampoline stubs in generateOptoStub.
2007 // Registers not mentioned will be killed by the VM call in the trampoline, and
2008 // arguments in those registers not be available to the callee.
2009 bool Matcher::can_be_java_arg( int reg ) {
2010 // Standard sparc 6 args in registers
2011 if( reg == R_I0_num ||
2012 reg == R_I1_num ||
2013 reg == R_I2_num ||
2014 reg == R_I3_num ||
2015 reg == R_I4_num ||
2016 reg == R_I5_num ) return true;
2017 #ifdef _LP64
2018 // 64-bit builds can pass 64-bit pointers and longs in
2019 // the high I registers
2020 if( reg == R_I0H_num ||
2021 reg == R_I1H_num ||
2022 reg == R_I2H_num ||
2023 reg == R_I3H_num ||
2024 reg == R_I4H_num ||
2025 reg == R_I5H_num ) return true;
2026
2027 if ((UseCompressedOops) && (reg == R_G6_num || reg == R_G6H_num)) {
2028 return true;
2029 }
2030
2031 #else
2032 // 32-bit builds with longs-in-one-entry pass longs in G1 & G4.
2033 // Longs cannot be passed in O regs, because O regs become I regs
2034 // after a 'save' and I regs get their high bits chopped off on
2035 // interrupt.
2036 if( reg == R_G1H_num || reg == R_G1_num ) return true;
2037 if( reg == R_G4H_num || reg == R_G4_num ) return true;
2038 #endif
2039 // A few float args in registers
2040 if( reg >= R_F0_num && reg <= R_F7_num ) return true;
2041
2042 return false;
2043 }
2044
2045 bool Matcher::is_spillable_arg( int reg ) {
2046 return can_be_java_arg(reg);
2047 }
2048
2049 bool Matcher::use_asm_for_ldiv_by_con( jlong divisor ) {
2050 // Use hardware SDIVX instruction when it is
2051 // faster than a code which use multiply.
2052 return VM_Version::has_fast_idiv();
2053 }
2054
2055 // Register for DIVI projection of divmodI
2056 RegMask Matcher::divI_proj_mask() {
2057 ShouldNotReachHere();
2058 return RegMask();
2059 }
2060
2061 // Register for MODI projection of divmodI
2062 RegMask Matcher::modI_proj_mask() {
2063 ShouldNotReachHere();
2064 return RegMask();
2065 }
2066
2067 // Register for DIVL projection of divmodL
2068 RegMask Matcher::divL_proj_mask() {
2069 ShouldNotReachHere();
2070 return RegMask();
2071 }
2072
2073 // Register for MODL projection of divmodL
2074 RegMask Matcher::modL_proj_mask() {
2075 ShouldNotReachHere();
2076 return RegMask();
2077 }
2078
2079 const RegMask Matcher::method_handle_invoke_SP_save_mask() {
2080 return L7_REGP_mask();
2081 }
2082
2083 %}
2084
2085
2086 // The intptr_t operand types, defined by textual substitution.
2087 // (Cf. opto/type.hpp. This lets us avoid many, many other ifdefs.)
2088 #ifdef _LP64
2089 #define immX immL
2090 #define immX13 immL13
2091 #define immX13m7 immL13m7
2092 #define iRegX iRegL
2093 #define g1RegX g1RegL
2094 #else
2095 #define immX immI
2096 #define immX13 immI13
2097 #define immX13m7 immI13m7
2098 #define iRegX iRegI
2099 #define g1RegX g1RegI
2100 #endif
2101
2102 //----------ENCODING BLOCK-----------------------------------------------------
2103 // This block specifies the encoding classes used by the compiler to output
2104 // byte streams. Encoding classes are parameterized macros used by
2105 // Machine Instruction Nodes in order to generate the bit encoding of the
2106 // instruction. Operands specify their base encoding interface with the
2107 // interface keyword. There are currently supported four interfaces,
2108 // REG_INTER, CONST_INTER, MEMORY_INTER, & COND_INTER. REG_INTER causes an
2109 // operand to generate a function which returns its register number when
2110 // queried. CONST_INTER causes an operand to generate a function which
2111 // returns the value of the constant when queried. MEMORY_INTER causes an
2112 // operand to generate four functions which return the Base Register, the
2113 // Index Register, the Scale Value, and the Offset Value of the operand when
2114 // queried. COND_INTER causes an operand to generate six functions which
2115 // return the encoding code (ie - encoding bits for the instruction)
2116 // associated with each basic boolean condition for a conditional instruction.
2117 //
2118 // Instructions specify two basic values for encoding. Again, a function
2119 // is available to check if the constant displacement is an oop. They use the
2120 // ins_encode keyword to specify their encoding classes (which must be
2121 // a sequence of enc_class names, and their parameters, specified in
2122 // the encoding block), and they use the
2123 // opcode keyword to specify, in order, their primary, secondary, and
2124 // tertiary opcode. Only the opcode sections which a particular instruction
2125 // needs for encoding need to be specified.
2126 encode %{
2127 enc_class enc_untested %{
2128 #ifdef ASSERT
2129 MacroAssembler _masm(&cbuf);
2130 __ untested("encoding");
2131 #endif
2132 %}
2133
2134 enc_class form3_mem_reg( memory mem, iRegI dst ) %{
2135 emit_form3_mem_reg(cbuf, ra_, this, $primary, $tertiary,
2136 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2137 %}
2138
2139 enc_class simple_form3_mem_reg( memory mem, iRegI dst ) %{
2140 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2141 $mem$$base, $mem$$disp, $mem$$index, $dst$$reg);
2142 %}
2143
2144 enc_class form3_mem_prefetch_read( memory mem ) %{
2145 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2146 $mem$$base, $mem$$disp, $mem$$index, 0/*prefetch function many-reads*/);
2147 %}
2148
2149 enc_class form3_mem_prefetch_write( memory mem ) %{
2150 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1,
2151 $mem$$base, $mem$$disp, $mem$$index, 2/*prefetch function many-writes*/);
2152 %}
2153
2154 enc_class form3_mem_reg_long_unaligned_marshal( memory mem, iRegL reg ) %{
2155 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2156 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2157 guarantee($mem$$index == R_G0_enc, "double index?");
2158 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, R_O7_enc );
2159 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg );
2160 emit3_simm13( cbuf, Assembler::arith_op, $reg$$reg, Assembler::sllx_op3, $reg$$reg, 0x1020 );
2161 emit3( cbuf, Assembler::arith_op, $reg$$reg, Assembler::or_op3, $reg$$reg, 0, R_O7_enc );
2162 %}
2163
2164 enc_class form3_mem_reg_double_unaligned( memory mem, RegD_low reg ) %{
2165 assert(Assembler::is_simm13($mem$$disp ), "need disp and disp+4");
2166 assert(Assembler::is_simm13($mem$$disp+4), "need disp and disp+4");
2167 guarantee($mem$$index == R_G0_enc, "double index?");
2168 // Load long with 2 instructions
2169 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp, R_G0_enc, $reg$$reg+0 );
2170 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp+4, R_G0_enc, $reg$$reg+1 );
2171 %}
2172
2173 //%%% form3_mem_plus_4_reg is a hack--get rid of it
2174 enc_class form3_mem_plus_4_reg( memory mem, iRegI dst ) %{
2175 guarantee($mem$$disp, "cannot offset a reg-reg operand by 4");
2176 emit_form3_mem_reg(cbuf, ra_, this, $primary, -1, $mem$$base, $mem$$disp + 4, $mem$$index, $dst$$reg);
2177 %}
2178
2179 enc_class form3_g0_rs2_rd_move( iRegI rs2, iRegI rd ) %{
2180 // Encode a reg-reg copy. If it is useless, then empty encoding.
2181 if( $rs2$$reg != $rd$$reg )
2182 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, $rs2$$reg );
2183 %}
2184
2185 // Target lo half of long
2186 enc_class form3_g0_rs2_rd_move_lo( iRegI rs2, iRegL rd ) %{
2187 // Encode a reg-reg copy. If it is useless, then empty encoding.
2188 if( $rs2$$reg != LONG_LO_REG($rd$$reg) )
2189 emit3( cbuf, Assembler::arith_op, LONG_LO_REG($rd$$reg), Assembler::or_op3, 0, 0, $rs2$$reg );
2190 %}
2191
2192 // Source lo half of long
2193 enc_class form3_g0_rs2_rd_move_lo2( iRegL rs2, iRegI rd ) %{
2194 // Encode a reg-reg copy. If it is useless, then empty encoding.
2195 if( LONG_LO_REG($rs2$$reg) != $rd$$reg )
2196 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_LO_REG($rs2$$reg) );
2197 %}
2198
2199 // Target hi half of long
2200 enc_class form3_rs1_rd_copysign_hi( iRegI rs1, iRegL rd ) %{
2201 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 31 );
2202 %}
2203
2204 // Source lo half of long, and leave it sign extended.
2205 enc_class form3_rs1_rd_signextend_lo1( iRegL rs1, iRegI rd ) %{
2206 // Sign extend low half
2207 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::sra_op3, $rs1$$reg, 0, 0 );
2208 %}
2209
2210 // Source hi half of long, and leave it sign extended.
2211 enc_class form3_rs1_rd_copy_hi1( iRegL rs1, iRegI rd ) %{
2212 // Shift high half to low half
2213 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::srlx_op3, $rs1$$reg, 32 );
2214 %}
2215
2216 // Source hi half of long
2217 enc_class form3_g0_rs2_rd_move_hi2( iRegL rs2, iRegI rd ) %{
2218 // Encode a reg-reg copy. If it is useless, then empty encoding.
2219 if( LONG_HI_REG($rs2$$reg) != $rd$$reg )
2220 emit3( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, 0, LONG_HI_REG($rs2$$reg) );
2221 %}
2222
2223 enc_class form3_rs1_rs2_rd( iRegI rs1, iRegI rs2, iRegI rd ) %{
2224 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0, $rs2$$reg );
2225 %}
2226
2227 enc_class enc_to_bool( iRegI src, iRegI dst ) %{
2228 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, 0, 0, $src$$reg );
2229 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::addc_op3 , 0, 0 );
2230 %}
2231
2232 enc_class enc_ltmask( iRegI p, iRegI q, iRegI dst ) %{
2233 emit3 ( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $p$$reg, 0, $q$$reg );
2234 // clear if nothing else is happening
2235 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 0 );
2236 // blt,a,pn done
2237 emit2_19 ( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less, Assembler::bp_op2, Assembler::icc, 0/*predict not taken*/, 2 );
2238 // mov dst,-1 in delay slot
2239 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2240 %}
2241
2242 enc_class form3_rs1_imm5_rd( iRegI rs1, immU5 imm5, iRegI rd ) %{
2243 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $imm5$$constant & 0x1F );
2244 %}
2245
2246 enc_class form3_sd_rs1_imm6_rd( iRegL rs1, immU6 imm6, iRegL rd ) %{
2247 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, ($imm6$$constant & 0x3F) | 0x1000 );
2248 %}
2249
2250 enc_class form3_sd_rs1_rs2_rd( iRegL rs1, iRegI rs2, iRegL rd ) %{
2251 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, 0x80, $rs2$$reg );
2252 %}
2253
2254 enc_class form3_rs1_simm13_rd( iRegI rs1, immI13 simm13, iRegI rd ) %{
2255 emit3_simm13( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $simm13$$constant );
2256 %}
2257
2258 enc_class move_return_pc_to_o1() %{
2259 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::add_op3, R_O7_enc, frame::pc_return_offset );
2260 %}
2261
2262 #ifdef _LP64
2263 /* %%% merge with enc_to_bool */
2264 enc_class enc_convP2B( iRegI dst, iRegP src ) %{
2265 MacroAssembler _masm(&cbuf);
2266
2267 Register src_reg = reg_to_register_object($src$$reg);
2268 Register dst_reg = reg_to_register_object($dst$$reg);
2269 __ movr(Assembler::rc_nz, src_reg, 1, dst_reg);
2270 %}
2271 #endif
2272
2273 enc_class enc_cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp ) %{
2274 // (Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)))
2275 MacroAssembler _masm(&cbuf);
2276
2277 Register p_reg = reg_to_register_object($p$$reg);
2278 Register q_reg = reg_to_register_object($q$$reg);
2279 Register y_reg = reg_to_register_object($y$$reg);
2280 Register tmp_reg = reg_to_register_object($tmp$$reg);
2281
2282 __ subcc( p_reg, q_reg, p_reg );
2283 __ add ( p_reg, y_reg, tmp_reg );
2284 __ movcc( Assembler::less, false, Assembler::icc, tmp_reg, p_reg );
2285 %}
2286
2287 enc_class form_d2i_helper(regD src, regF dst) %{
2288 // fcmp %fcc0,$src,$src
2289 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2290 // branch %fcc0 not-nan, predict taken
2291 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2292 // fdtoi $src,$dst
2293 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtoi_opf, $src$$reg );
2294 // fitos $dst,$dst (if nan)
2295 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2296 // clear $dst (if nan)
2297 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2298 // carry on here...
2299 %}
2300
2301 enc_class form_d2l_helper(regD src, regD dst) %{
2302 // fcmp %fcc0,$src,$src check for NAN
2303 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmpd_opf, $src$$reg );
2304 // branch %fcc0 not-nan, predict taken
2305 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2306 // fdtox $src,$dst convert in delay slot
2307 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fdtox_opf, $src$$reg );
2308 // fxtod $dst,$dst (if nan)
2309 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2310 // clear $dst (if nan)
2311 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2312 // carry on here...
2313 %}
2314
2315 enc_class form_f2i_helper(regF src, regF dst) %{
2316 // fcmps %fcc0,$src,$src
2317 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2318 // branch %fcc0 not-nan, predict taken
2319 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2320 // fstoi $src,$dst
2321 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstoi_opf, $src$$reg );
2322 // fitos $dst,$dst (if nan)
2323 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fitos_opf, $dst$$reg );
2324 // clear $dst (if nan)
2325 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubs_opf, $dst$$reg );
2326 // carry on here...
2327 %}
2328
2329 enc_class form_f2l_helper(regF src, regD dst) %{
2330 // fcmps %fcc0,$src,$src
2331 emit3( cbuf, Assembler::arith_op , Assembler::fcc0, Assembler::fpop2_op3, $src$$reg, Assembler::fcmps_opf, $src$$reg );
2332 // branch %fcc0 not-nan, predict taken
2333 emit2_19( cbuf, Assembler::branch_op, 0/*annul*/, Assembler::f_ordered, Assembler::fbp_op2, Assembler::fcc0, 1/*predict taken*/, 4 );
2334 // fstox $src,$dst
2335 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fstox_opf, $src$$reg );
2336 // fxtod $dst,$dst (if nan)
2337 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, 0, Assembler::fxtod_opf, $dst$$reg );
2338 // clear $dst (if nan)
2339 emit3( cbuf, Assembler::arith_op , $dst$$reg, Assembler::fpop1_op3, $dst$$reg, Assembler::fsubd_opf, $dst$$reg );
2340 // carry on here...
2341 %}
2342
2343 enc_class form3_opf_rs2F_rdF(regF rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2344 enc_class form3_opf_rs2F_rdD(regF rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2345 enc_class form3_opf_rs2D_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2346 enc_class form3_opf_rs2D_rdD(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2347
2348 enc_class form3_opf_rs2D_lo_rdF(regD rs2, regF rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg+1); %}
2349
2350 enc_class form3_opf_rs2D_hi_rdD_hi(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg,$primary,0,$tertiary,$rs2$$reg); %}
2351 enc_class form3_opf_rs2D_lo_rdD_lo(regD rs2, regD rd) %{ emit3(cbuf,$secondary,$rd$$reg+1,$primary,0,$tertiary,$rs2$$reg+1); %}
2352
2353 enc_class form3_opf_rs1F_rs2F_rdF( regF rs1, regF rs2, regF rd ) %{
2354 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2355 %}
2356
2357 enc_class form3_opf_rs1D_rs2D_rdD( regD rs1, regD rs2, regD rd ) %{
2358 emit3( cbuf, $secondary, $rd$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2359 %}
2360
2361 enc_class form3_opf_rs1F_rs2F_fcc( regF rs1, regF rs2, flagsRegF fcc ) %{
2362 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2363 %}
2364
2365 enc_class form3_opf_rs1D_rs2D_fcc( regD rs1, regD rs2, flagsRegF fcc ) %{
2366 emit3( cbuf, $secondary, $fcc$$reg, $primary, $rs1$$reg, $tertiary, $rs2$$reg );
2367 %}
2368
2369 enc_class form3_convI2F(regF rs2, regF rd) %{
2370 emit3(cbuf,Assembler::arith_op,$rd$$reg,Assembler::fpop1_op3,0,$secondary,$rs2$$reg);
2371 %}
2372
2373 // Encloding class for traceable jumps
2374 enc_class form_jmpl(g3RegP dest) %{
2375 emit_jmpl(cbuf, $dest$$reg);
2376 %}
2377
2378 enc_class form_jmpl_set_exception_pc(g1RegP dest) %{
2379 emit_jmpl_set_exception_pc(cbuf, $dest$$reg);
2380 %}
2381
2382 enc_class form2_nop() %{
2383 emit_nop(cbuf);
2384 %}
2385
2386 enc_class form2_illtrap() %{
2387 emit_illtrap(cbuf);
2388 %}
2389
2390
2391 // Compare longs and convert into -1, 0, 1.
2392 enc_class cmpl_flag( iRegL src1, iRegL src2, iRegI dst ) %{
2393 // CMP $src1,$src2
2394 emit3( cbuf, Assembler::arith_op, 0, Assembler::subcc_op3, $src1$$reg, 0, $src2$$reg );
2395 // blt,a,pn done
2396 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::less , Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 5 );
2397 // mov dst,-1 in delay slot
2398 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, -1 );
2399 // bgt,a,pn done
2400 emit2_19( cbuf, Assembler::branch_op, 1/*annul*/, Assembler::greater, Assembler::bp_op2, Assembler::xcc, 0/*predict not taken*/, 3 );
2401 // mov dst,1 in delay slot
2402 emit3_simm13( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3, 0, 1 );
2403 // CLR $dst
2404 emit3( cbuf, Assembler::arith_op, $dst$$reg, Assembler::or_op3 , 0, 0, 0 );
2405 %}
2406
2407 enc_class enc_PartialSubtypeCheck() %{
2408 MacroAssembler _masm(&cbuf);
2409 __ call(StubRoutines::Sparc::partial_subtype_check(), relocInfo::runtime_call_type);
2410 __ delayed()->nop();
2411 %}
2412
2413 enc_class enc_bp( label labl, cmpOp cmp, flagsReg cc ) %{
2414 MacroAssembler _masm(&cbuf);
2415 Label* L = $labl$$label;
2416 Assembler::Predict predict_taken =
2417 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2418
2419 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
2420 __ delayed()->nop();
2421 %}
2422
2423 enc_class enc_bpr( label labl, cmpOp_reg cmp, iRegI op1 ) %{
2424 MacroAssembler _masm(&cbuf);
2425 Label* L = $labl$$label;
2426 Assembler::Predict predict_taken =
2427 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
2428
2429 __ bpr( (Assembler::RCondition)($cmp$$cmpcode), false, predict_taken, as_Register($op1$$reg), *L);
2430 __ delayed()->nop();
2431 %}
2432
2433 enc_class enc_cmov_reg( cmpOp cmp, iRegI dst, iRegI src, immI pcc) %{
2434 int op = (Assembler::arith_op << 30) |
2435 ($dst$$reg << 25) |
2436 (Assembler::movcc_op3 << 19) |
2437 (1 << 18) | // cc2 bit for 'icc'
2438 ($cmp$$cmpcode << 14) |
2439 (0 << 13) | // select register move
2440 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc' or 'xcc'
2441 ($src$$reg << 0);
2442 cbuf.insts()->emit_int32(op);
2443 %}
2444
2445 enc_class enc_cmov_imm( cmpOp cmp, iRegI dst, immI11 src, immI pcc ) %{
2446 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2447 int op = (Assembler::arith_op << 30) |
2448 ($dst$$reg << 25) |
2449 (Assembler::movcc_op3 << 19) |
2450 (1 << 18) | // cc2 bit for 'icc'
2451 ($cmp$$cmpcode << 14) |
2452 (1 << 13) | // select immediate move
2453 ($pcc$$constant << 11) | // cc1, cc0 bits for 'icc'
2454 (simm11 << 0);
2455 cbuf.insts()->emit_int32(op);
2456 %}
2457
2458 enc_class enc_cmov_reg_f( cmpOpF cmp, iRegI dst, iRegI src, flagsRegF fcc ) %{
2459 int op = (Assembler::arith_op << 30) |
2460 ($dst$$reg << 25) |
2461 (Assembler::movcc_op3 << 19) |
2462 (0 << 18) | // cc2 bit for 'fccX'
2463 ($cmp$$cmpcode << 14) |
2464 (0 << 13) | // select register move
2465 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2466 ($src$$reg << 0);
2467 cbuf.insts()->emit_int32(op);
2468 %}
2469
2470 enc_class enc_cmov_imm_f( cmpOp cmp, iRegI dst, immI11 src, flagsRegF fcc ) %{
2471 int simm11 = $src$$constant & ((1<<11)-1); // Mask to 11 bits
2472 int op = (Assembler::arith_op << 30) |
2473 ($dst$$reg << 25) |
2474 (Assembler::movcc_op3 << 19) |
2475 (0 << 18) | // cc2 bit for 'fccX'
2476 ($cmp$$cmpcode << 14) |
2477 (1 << 13) | // select immediate move
2478 ($fcc$$reg << 11) | // cc1, cc0 bits for fcc0-fcc3
2479 (simm11 << 0);
2480 cbuf.insts()->emit_int32(op);
2481 %}
2482
2483 enc_class enc_cmovf_reg( cmpOp cmp, regD dst, regD src, immI pcc ) %{
2484 int op = (Assembler::arith_op << 30) |
2485 ($dst$$reg << 25) |
2486 (Assembler::fpop2_op3 << 19) |
2487 (0 << 18) |
2488 ($cmp$$cmpcode << 14) |
2489 (1 << 13) | // select register move
2490 ($pcc$$constant << 11) | // cc1-cc0 bits for 'icc' or 'xcc'
2491 ($primary << 5) | // select single, double or quad
2492 ($src$$reg << 0);
2493 cbuf.insts()->emit_int32(op);
2494 %}
2495
2496 enc_class enc_cmovff_reg( cmpOpF cmp, flagsRegF fcc, regD dst, regD src ) %{
2497 int op = (Assembler::arith_op << 30) |
2498 ($dst$$reg << 25) |
2499 (Assembler::fpop2_op3 << 19) |
2500 (0 << 18) |
2501 ($cmp$$cmpcode << 14) |
2502 ($fcc$$reg << 11) | // cc2-cc0 bits for 'fccX'
2503 ($primary << 5) | // select single, double or quad
2504 ($src$$reg << 0);
2505 cbuf.insts()->emit_int32(op);
2506 %}
2507
2508 // Used by the MIN/MAX encodings. Same as a CMOV, but
2509 // the condition comes from opcode-field instead of an argument.
2510 enc_class enc_cmov_reg_minmax( iRegI dst, iRegI src ) %{
2511 int op = (Assembler::arith_op << 30) |
2512 ($dst$$reg << 25) |
2513 (Assembler::movcc_op3 << 19) |
2514 (1 << 18) | // cc2 bit for 'icc'
2515 ($primary << 14) |
2516 (0 << 13) | // select register move
2517 (0 << 11) | // cc1, cc0 bits for 'icc'
2518 ($src$$reg << 0);
2519 cbuf.insts()->emit_int32(op);
2520 %}
2521
2522 enc_class enc_cmov_reg_minmax_long( iRegL dst, iRegL src ) %{
2523 int op = (Assembler::arith_op << 30) |
2524 ($dst$$reg << 25) |
2525 (Assembler::movcc_op3 << 19) |
2526 (6 << 16) | // cc2 bit for 'xcc'
2527 ($primary << 14) |
2528 (0 << 13) | // select register move
2529 (0 << 11) | // cc1, cc0 bits for 'icc'
2530 ($src$$reg << 0);
2531 cbuf.insts()->emit_int32(op);
2532 %}
2533
2534 enc_class Set13( immI13 src, iRegI rd ) %{
2535 emit3_simm13( cbuf, Assembler::arith_op, $rd$$reg, Assembler::or_op3, 0, $src$$constant );
2536 %}
2537
2538 enc_class SetHi22( immI src, iRegI rd ) %{
2539 emit2_22( cbuf, Assembler::branch_op, $rd$$reg, Assembler::sethi_op2, $src$$constant );
2540 %}
2541
2542 enc_class Set32( immI src, iRegI rd ) %{
2543 MacroAssembler _masm(&cbuf);
2544 __ set($src$$constant, reg_to_register_object($rd$$reg));
2545 %}
2546
2547 enc_class call_epilog %{
2548 if( VerifyStackAtCalls ) {
2549 MacroAssembler _masm(&cbuf);
2550 int framesize = ra_->C->frame_size_in_bytes();
2551 Register temp_reg = G3;
2552 __ add(SP, framesize, temp_reg);
2553 __ cmp(temp_reg, FP);
2554 __ breakpoint_trap(Assembler::notEqual, Assembler::ptr_cc);
2555 }
2556 %}
2557
2558 // Long values come back from native calls in O0:O1 in the 32-bit VM, copy the value
2559 // to G1 so the register allocator will not have to deal with the misaligned register
2560 // pair.
2561 enc_class adjust_long_from_native_call %{
2562 #ifndef _LP64
2563 if (returns_long()) {
2564 // sllx O0,32,O0
2565 emit3_simm13( cbuf, Assembler::arith_op, R_O0_enc, Assembler::sllx_op3, R_O0_enc, 0x1020 );
2566 // srl O1,0,O1
2567 emit3_simm13( cbuf, Assembler::arith_op, R_O1_enc, Assembler::srl_op3, R_O1_enc, 0x0000 );
2568 // or O0,O1,G1
2569 emit3 ( cbuf, Assembler::arith_op, R_G1_enc, Assembler:: or_op3, R_O0_enc, 0, R_O1_enc );
2570 }
2571 #endif
2572 %}
2573
2574 enc_class Java_To_Runtime (method meth) %{ // CALL Java_To_Runtime
2575 // CALL directly to the runtime
2576 // The user of this is responsible for ensuring that R_L7 is empty (killed).
2577 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type,
2578 /*preserve_g2=*/true);
2579 %}
2580
2581 enc_class preserve_SP %{
2582 MacroAssembler _masm(&cbuf);
2583 __ mov(SP, L7_mh_SP_save);
2584 %}
2585
2586 enc_class restore_SP %{
2587 MacroAssembler _masm(&cbuf);
2588 __ mov(L7_mh_SP_save, SP);
2589 %}
2590
2591 enc_class Java_Static_Call (method meth) %{ // JAVA STATIC CALL
2592 // CALL to fixup routine. Fixup routine uses ScopeDesc info to determine
2593 // who we intended to call.
2594 if (!_method) {
2595 emit_call_reloc(cbuf, $meth$$method, relocInfo::runtime_call_type);
2596 } else if (_optimized_virtual) {
2597 emit_call_reloc(cbuf, $meth$$method, relocInfo::opt_virtual_call_type);
2598 } else {
2599 emit_call_reloc(cbuf, $meth$$method, relocInfo::static_call_type);
2600 }
2601 if (_method) { // Emit stub for static call.
2602 CompiledStaticCall::emit_to_interp_stub(cbuf);
2603 }
2604 %}
2605
2606 enc_class Java_Dynamic_Call (method meth) %{ // JAVA DYNAMIC CALL
2607 MacroAssembler _masm(&cbuf);
2608 __ set_inst_mark();
2609 int vtable_index = this->_vtable_index;
2610 // MachCallDynamicJavaNode::ret_addr_offset uses this same test
2611 if (vtable_index < 0) {
2612 // must be invalid_vtable_index, not nonvirtual_vtable_index
2613 assert(vtable_index == Method::invalid_vtable_index, "correct sentinel value");
2614 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2615 assert(G5_ic_reg == G5_inline_cache_reg, "G5_inline_cache_reg used in assemble_ic_buffer_code()");
2616 assert(G5_ic_reg == G5_megamorphic_method, "G5_megamorphic_method used in megamorphic call stub");
2617 __ ic_call((address)$meth$$method);
2618 } else {
2619 assert(!UseInlineCaches, "expect vtable calls only if not using ICs");
2620 // Just go thru the vtable
2621 // get receiver klass (receiver already checked for non-null)
2622 // If we end up going thru a c2i adapter interpreter expects method in G5
2623 int off = __ offset();
2624 __ load_klass(O0, G3_scratch);
2625 int klass_load_size;
2626 if (UseCompressedClassPointers) {
2627 assert(Universe::heap() != NULL, "java heap should be initialized");
2628 klass_load_size = MacroAssembler::instr_size_for_decode_klass_not_null() + 1*BytesPerInstWord;
2629 } else {
2630 klass_load_size = 1*BytesPerInstWord;
2631 }
2632 int entry_offset = InstanceKlass::vtable_start_offset() + vtable_index*vtableEntry::size();
2633 int v_off = entry_offset*wordSize + vtableEntry::method_offset_in_bytes();
2634 if (Assembler::is_simm13(v_off)) {
2635 __ ld_ptr(G3, v_off, G5_method);
2636 } else {
2637 // Generate 2 instructions
2638 __ Assembler::sethi(v_off & ~0x3ff, G5_method);
2639 __ or3(G5_method, v_off & 0x3ff, G5_method);
2640 // ld_ptr, set_hi, set
2641 assert(__ offset() - off == klass_load_size + 2*BytesPerInstWord,
2642 "Unexpected instruction size(s)");
2643 __ ld_ptr(G3, G5_method, G5_method);
2644 }
2645 // NOTE: for vtable dispatches, the vtable entry will never be null.
2646 // However it may very well end up in handle_wrong_method if the
2647 // method is abstract for the particular class.
2648 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3_scratch);
2649 // jump to target (either compiled code or c2iadapter)
2650 __ jmpl(G3_scratch, G0, O7);
2651 __ delayed()->nop();
2652 }
2653 %}
2654
2655 enc_class Java_Compiled_Call (method meth) %{ // JAVA COMPILED CALL
2656 MacroAssembler _masm(&cbuf);
2657
2658 Register G5_ic_reg = reg_to_register_object(Matcher::inline_cache_reg_encode());
2659 Register temp_reg = G3; // caller must kill G3! We cannot reuse G5_ic_reg here because
2660 // we might be calling a C2I adapter which needs it.
2661
2662 assert(temp_reg != G5_ic_reg, "conflicting registers");
2663 // Load nmethod
2664 __ ld_ptr(G5_ic_reg, in_bytes(Method::from_compiled_offset()), temp_reg);
2665
2666 // CALL to compiled java, indirect the contents of G3
2667 __ set_inst_mark();
2668 __ callr(temp_reg, G0);
2669 __ delayed()->nop();
2670 %}
2671
2672 enc_class idiv_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst) %{
2673 MacroAssembler _masm(&cbuf);
2674 Register Rdividend = reg_to_register_object($src1$$reg);
2675 Register Rdivisor = reg_to_register_object($src2$$reg);
2676 Register Rresult = reg_to_register_object($dst$$reg);
2677
2678 __ sra(Rdivisor, 0, Rdivisor);
2679 __ sra(Rdividend, 0, Rdividend);
2680 __ sdivx(Rdividend, Rdivisor, Rresult);
2681 %}
2682
2683 enc_class idiv_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst) %{
2684 MacroAssembler _masm(&cbuf);
2685
2686 Register Rdividend = reg_to_register_object($src1$$reg);
2687 int divisor = $imm$$constant;
2688 Register Rresult = reg_to_register_object($dst$$reg);
2689
2690 __ sra(Rdividend, 0, Rdividend);
2691 __ sdivx(Rdividend, divisor, Rresult);
2692 %}
2693
2694 enc_class enc_mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2) %{
2695 MacroAssembler _masm(&cbuf);
2696 Register Rsrc1 = reg_to_register_object($src1$$reg);
2697 Register Rsrc2 = reg_to_register_object($src2$$reg);
2698 Register Rdst = reg_to_register_object($dst$$reg);
2699
2700 __ sra( Rsrc1, 0, Rsrc1 );
2701 __ sra( Rsrc2, 0, Rsrc2 );
2702 __ mulx( Rsrc1, Rsrc2, Rdst );
2703 __ srlx( Rdst, 32, Rdst );
2704 %}
2705
2706 enc_class irem_reg(iRegIsafe src1, iRegIsafe src2, iRegIsafe dst, o7RegL scratch) %{
2707 MacroAssembler _masm(&cbuf);
2708 Register Rdividend = reg_to_register_object($src1$$reg);
2709 Register Rdivisor = reg_to_register_object($src2$$reg);
2710 Register Rresult = reg_to_register_object($dst$$reg);
2711 Register Rscratch = reg_to_register_object($scratch$$reg);
2712
2713 assert(Rdividend != Rscratch, "");
2714 assert(Rdivisor != Rscratch, "");
2715
2716 __ sra(Rdividend, 0, Rdividend);
2717 __ sra(Rdivisor, 0, Rdivisor);
2718 __ sdivx(Rdividend, Rdivisor, Rscratch);
2719 __ mulx(Rscratch, Rdivisor, Rscratch);
2720 __ sub(Rdividend, Rscratch, Rresult);
2721 %}
2722
2723 enc_class irem_imm(iRegIsafe src1, immI13 imm, iRegIsafe dst, o7RegL scratch) %{
2724 MacroAssembler _masm(&cbuf);
2725
2726 Register Rdividend = reg_to_register_object($src1$$reg);
2727 int divisor = $imm$$constant;
2728 Register Rresult = reg_to_register_object($dst$$reg);
2729 Register Rscratch = reg_to_register_object($scratch$$reg);
2730
2731 assert(Rdividend != Rscratch, "");
2732
2733 __ sra(Rdividend, 0, Rdividend);
2734 __ sdivx(Rdividend, divisor, Rscratch);
2735 __ mulx(Rscratch, divisor, Rscratch);
2736 __ sub(Rdividend, Rscratch, Rresult);
2737 %}
2738
2739 enc_class fabss (sflt_reg dst, sflt_reg src) %{
2740 MacroAssembler _masm(&cbuf);
2741
2742 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2743 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2744
2745 __ fabs(FloatRegisterImpl::S, Fsrc, Fdst);
2746 %}
2747
2748 enc_class fabsd (dflt_reg dst, dflt_reg src) %{
2749 MacroAssembler _masm(&cbuf);
2750
2751 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2752 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2753
2754 __ fabs(FloatRegisterImpl::D, Fsrc, Fdst);
2755 %}
2756
2757 enc_class fnegd (dflt_reg dst, dflt_reg src) %{
2758 MacroAssembler _masm(&cbuf);
2759
2760 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2761 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2762
2763 __ fneg(FloatRegisterImpl::D, Fsrc, Fdst);
2764 %}
2765
2766 enc_class fsqrts (sflt_reg dst, sflt_reg src) %{
2767 MacroAssembler _masm(&cbuf);
2768
2769 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2770 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2771
2772 __ fsqrt(FloatRegisterImpl::S, Fsrc, Fdst);
2773 %}
2774
2775 enc_class fsqrtd (dflt_reg dst, dflt_reg src) %{
2776 MacroAssembler _masm(&cbuf);
2777
2778 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2779 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2780
2781 __ fsqrt(FloatRegisterImpl::D, Fsrc, Fdst);
2782 %}
2783
2784 enc_class fmovs (dflt_reg dst, dflt_reg src) %{
2785 MacroAssembler _masm(&cbuf);
2786
2787 FloatRegister Fdst = reg_to_SingleFloatRegister_object($dst$$reg);
2788 FloatRegister Fsrc = reg_to_SingleFloatRegister_object($src$$reg);
2789
2790 __ fmov(FloatRegisterImpl::S, Fsrc, Fdst);
2791 %}
2792
2793 enc_class fmovd (dflt_reg dst, dflt_reg src) %{
2794 MacroAssembler _masm(&cbuf);
2795
2796 FloatRegister Fdst = reg_to_DoubleFloatRegister_object($dst$$reg);
2797 FloatRegister Fsrc = reg_to_DoubleFloatRegister_object($src$$reg);
2798
2799 __ fmov(FloatRegisterImpl::D, Fsrc, Fdst);
2800 %}
2801
2802 enc_class Fast_Lock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2803 MacroAssembler _masm(&cbuf);
2804
2805 Register Roop = reg_to_register_object($oop$$reg);
2806 Register Rbox = reg_to_register_object($box$$reg);
2807 Register Rscratch = reg_to_register_object($scratch$$reg);
2808 Register Rmark = reg_to_register_object($scratch2$$reg);
2809
2810 assert(Roop != Rscratch, "");
2811 assert(Roop != Rmark, "");
2812 assert(Rbox != Rscratch, "");
2813 assert(Rbox != Rmark, "");
2814
2815 __ compiler_lock_object(Roop, Rmark, Rbox, Rscratch, _counters, UseBiasedLocking && !UseOptoBiasInlining);
2816 %}
2817
2818 enc_class Fast_Unlock(iRegP oop, iRegP box, o7RegP scratch, iRegP scratch2) %{
2819 MacroAssembler _masm(&cbuf);
2820
2821 Register Roop = reg_to_register_object($oop$$reg);
2822 Register Rbox = reg_to_register_object($box$$reg);
2823 Register Rscratch = reg_to_register_object($scratch$$reg);
2824 Register Rmark = reg_to_register_object($scratch2$$reg);
2825
2826 assert(Roop != Rscratch, "");
2827 assert(Roop != Rmark, "");
2828 assert(Rbox != Rscratch, "");
2829 assert(Rbox != Rmark, "");
2830
2831 __ compiler_unlock_object(Roop, Rmark, Rbox, Rscratch, UseBiasedLocking && !UseOptoBiasInlining);
2832 %}
2833
2834 enc_class enc_cas( iRegP mem, iRegP old, iRegP new ) %{
2835 MacroAssembler _masm(&cbuf);
2836 Register Rmem = reg_to_register_object($mem$$reg);
2837 Register Rold = reg_to_register_object($old$$reg);
2838 Register Rnew = reg_to_register_object($new$$reg);
2839
2840 __ cas_ptr(Rmem, Rold, Rnew); // Swap(*Rmem,Rnew) if *Rmem == Rold
2841 __ cmp( Rold, Rnew );
2842 %}
2843
2844 enc_class enc_casx( iRegP mem, iRegL old, iRegL new) %{
2845 Register Rmem = reg_to_register_object($mem$$reg);
2846 Register Rold = reg_to_register_object($old$$reg);
2847 Register Rnew = reg_to_register_object($new$$reg);
2848
2849 MacroAssembler _masm(&cbuf);
2850 __ mov(Rnew, O7);
2851 __ casx(Rmem, Rold, O7);
2852 __ cmp( Rold, O7 );
2853 %}
2854
2855 // raw int cas, used for compareAndSwap
2856 enc_class enc_casi( iRegP mem, iRegL old, iRegL new) %{
2857 Register Rmem = reg_to_register_object($mem$$reg);
2858 Register Rold = reg_to_register_object($old$$reg);
2859 Register Rnew = reg_to_register_object($new$$reg);
2860
2861 MacroAssembler _masm(&cbuf);
2862 __ mov(Rnew, O7);
2863 __ cas(Rmem, Rold, O7);
2864 __ cmp( Rold, O7 );
2865 %}
2866
2867 enc_class enc_lflags_ne_to_boolean( iRegI res ) %{
2868 Register Rres = reg_to_register_object($res$$reg);
2869
2870 MacroAssembler _masm(&cbuf);
2871 __ mov(1, Rres);
2872 __ movcc( Assembler::notEqual, false, Assembler::xcc, G0, Rres );
2873 %}
2874
2875 enc_class enc_iflags_ne_to_boolean( iRegI res ) %{
2876 Register Rres = reg_to_register_object($res$$reg);
2877
2878 MacroAssembler _masm(&cbuf);
2879 __ mov(1, Rres);
2880 __ movcc( Assembler::notEqual, false, Assembler::icc, G0, Rres );
2881 %}
2882
2883 enc_class floating_cmp ( iRegP dst, regF src1, regF src2 ) %{
2884 MacroAssembler _masm(&cbuf);
2885 Register Rdst = reg_to_register_object($dst$$reg);
2886 FloatRegister Fsrc1 = $primary ? reg_to_SingleFloatRegister_object($src1$$reg)
2887 : reg_to_DoubleFloatRegister_object($src1$$reg);
2888 FloatRegister Fsrc2 = $primary ? reg_to_SingleFloatRegister_object($src2$$reg)
2889 : reg_to_DoubleFloatRegister_object($src2$$reg);
2890
2891 // Convert condition code fcc0 into -1,0,1; unordered reports less-than (-1)
2892 __ float_cmp( $primary, -1, Fsrc1, Fsrc2, Rdst);
2893 %}
2894
2895
2896 enc_class enc_String_Compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result) %{
2897 Label Ldone, Lloop;
2898 MacroAssembler _masm(&cbuf);
2899
2900 Register str1_reg = reg_to_register_object($str1$$reg);
2901 Register str2_reg = reg_to_register_object($str2$$reg);
2902 Register cnt1_reg = reg_to_register_object($cnt1$$reg);
2903 Register cnt2_reg = reg_to_register_object($cnt2$$reg);
2904 Register result_reg = reg_to_register_object($result$$reg);
2905
2906 assert(result_reg != str1_reg &&
2907 result_reg != str2_reg &&
2908 result_reg != cnt1_reg &&
2909 result_reg != cnt2_reg ,
2910 "need different registers");
2911
2912 // Compute the minimum of the string lengths(str1_reg) and the
2913 // difference of the string lengths (stack)
2914
2915 // See if the lengths are different, and calculate min in str1_reg.
2916 // Stash diff in O7 in case we need it for a tie-breaker.
2917 Label Lskip;
2918 __ subcc(cnt1_reg, cnt2_reg, O7);
2919 __ sll(cnt1_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2920 __ br(Assembler::greater, true, Assembler::pt, Lskip);
2921 // cnt2 is shorter, so use its count:
2922 __ delayed()->sll(cnt2_reg, exact_log2(sizeof(jchar)), cnt1_reg); // scale the limit
2923 __ bind(Lskip);
2924
2925 // reallocate cnt1_reg, cnt2_reg, result_reg
2926 // Note: limit_reg holds the string length pre-scaled by 2
2927 Register limit_reg = cnt1_reg;
2928 Register chr2_reg = cnt2_reg;
2929 Register chr1_reg = result_reg;
2930 // str{12} are the base pointers
2931
2932 // Is the minimum length zero?
2933 __ cmp(limit_reg, (int)(0 * sizeof(jchar))); // use cast to resolve overloading ambiguity
2934 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2935 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2936
2937 // Load first characters
2938 __ lduh(str1_reg, 0, chr1_reg);
2939 __ lduh(str2_reg, 0, chr2_reg);
2940
2941 // Compare first characters
2942 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2943 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2944 assert(chr1_reg == result_reg, "result must be pre-placed");
2945 __ delayed()->nop();
2946
2947 {
2948 // Check after comparing first character to see if strings are equivalent
2949 Label LSkip2;
2950 // Check if the strings start at same location
2951 __ cmp(str1_reg, str2_reg);
2952 __ brx(Assembler::notEqual, true, Assembler::pt, LSkip2);
2953 __ delayed()->nop();
2954
2955 // Check if the length difference is zero (in O7)
2956 __ cmp(G0, O7);
2957 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2958 __ delayed()->mov(G0, result_reg); // result is zero
2959
2960 // Strings might not be equal
2961 __ bind(LSkip2);
2962 }
2963
2964 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
2965 __ signx(limit_reg);
2966
2967 __ subcc(limit_reg, 1 * sizeof(jchar), chr1_reg);
2968 __ br(Assembler::equal, true, Assembler::pn, Ldone);
2969 __ delayed()->mov(O7, result_reg); // result is difference in lengths
2970
2971 // Shift str1_reg and str2_reg to the end of the arrays, negate limit
2972 __ add(str1_reg, limit_reg, str1_reg);
2973 __ add(str2_reg, limit_reg, str2_reg);
2974 __ neg(chr1_reg, limit_reg); // limit = -(limit-2)
2975
2976 // Compare the rest of the characters
2977 __ lduh(str1_reg, limit_reg, chr1_reg);
2978 __ bind(Lloop);
2979 // __ lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2980 __ lduh(str2_reg, limit_reg, chr2_reg);
2981 __ subcc(chr1_reg, chr2_reg, chr1_reg);
2982 __ br(Assembler::notZero, false, Assembler::pt, Ldone);
2983 assert(chr1_reg == result_reg, "result must be pre-placed");
2984 __ delayed()->inccc(limit_reg, sizeof(jchar));
2985 // annul LDUH if branch is not taken to prevent access past end of string
2986 __ br(Assembler::notZero, true, Assembler::pt, Lloop);
2987 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
2988
2989 // If strings are equal up to min length, return the length difference.
2990 __ mov(O7, result_reg);
2991
2992 // Otherwise, return the difference between the first mismatched chars.
2993 __ bind(Ldone);
2994 %}
2995
2996 enc_class enc_String_Equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result) %{
2997 Label Lchar, Lchar_loop, Ldone;
2998 MacroAssembler _masm(&cbuf);
2999
3000 Register str1_reg = reg_to_register_object($str1$$reg);
3001 Register str2_reg = reg_to_register_object($str2$$reg);
3002 Register cnt_reg = reg_to_register_object($cnt$$reg);
3003 Register tmp1_reg = O7;
3004 Register result_reg = reg_to_register_object($result$$reg);
3005
3006 assert(result_reg != str1_reg &&
3007 result_reg != str2_reg &&
3008 result_reg != cnt_reg &&
3009 result_reg != tmp1_reg ,
3010 "need different registers");
3011
3012 __ cmp(str1_reg, str2_reg); //same char[] ?
3013 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3014 __ delayed()->add(G0, 1, result_reg);
3015
3016 __ cmp_zero_and_br(Assembler::zero, cnt_reg, Ldone, true, Assembler::pn);
3017 __ delayed()->add(G0, 1, result_reg); // count == 0
3018
3019 //rename registers
3020 Register limit_reg = cnt_reg;
3021 Register chr1_reg = result_reg;
3022 Register chr2_reg = tmp1_reg;
3023
3024 // We have no guarantee that on 64 bit the higher half of limit_reg is 0
3025 __ signx(limit_reg);
3026
3027 //check for alignment and position the pointers to the ends
3028 __ or3(str1_reg, str2_reg, chr1_reg);
3029 __ andcc(chr1_reg, 0x3, chr1_reg);
3030 // notZero means at least one not 4-byte aligned.
3031 // We could optimize the case when both arrays are not aligned
3032 // but it is not frequent case and it requires additional checks.
3033 __ br(Assembler::notZero, false, Assembler::pn, Lchar); // char by char compare
3034 __ delayed()->sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg); // set byte count
3035
3036 // Compare char[] arrays aligned to 4 bytes.
3037 __ char_arrays_equals(str1_reg, str2_reg, limit_reg, result_reg,
3038 chr1_reg, chr2_reg, Ldone);
3039 __ ba(Ldone);
3040 __ delayed()->add(G0, 1, result_reg);
3041
3042 // char by char compare
3043 __ bind(Lchar);
3044 __ add(str1_reg, limit_reg, str1_reg);
3045 __ add(str2_reg, limit_reg, str2_reg);
3046 __ neg(limit_reg); //negate count
3047
3048 __ lduh(str1_reg, limit_reg, chr1_reg);
3049 // Lchar_loop
3050 __ bind(Lchar_loop);
3051 __ lduh(str2_reg, limit_reg, chr2_reg);
3052 __ cmp(chr1_reg, chr2_reg);
3053 __ br(Assembler::notEqual, true, Assembler::pt, Ldone);
3054 __ delayed()->mov(G0, result_reg); //not equal
3055 __ inccc(limit_reg, sizeof(jchar));
3056 // annul LDUH if branch is not taken to prevent access past end of string
3057 __ br(Assembler::notZero, true, Assembler::pt, Lchar_loop);
3058 __ delayed()->lduh(str1_reg, limit_reg, chr1_reg); // hoisted
3059
3060 __ add(G0, 1, result_reg); //equal
3061
3062 __ bind(Ldone);
3063 %}
3064
3065 enc_class enc_Array_Equals(o0RegP ary1, o1RegP ary2, g3RegP tmp1, notemp_iRegI result) %{
3066 Label Lvector, Ldone, Lloop;
3067 MacroAssembler _masm(&cbuf);
3068
3069 Register ary1_reg = reg_to_register_object($ary1$$reg);
3070 Register ary2_reg = reg_to_register_object($ary2$$reg);
3071 Register tmp1_reg = reg_to_register_object($tmp1$$reg);
3072 Register tmp2_reg = O7;
3073 Register result_reg = reg_to_register_object($result$$reg);
3074
3075 int length_offset = arrayOopDesc::length_offset_in_bytes();
3076 int base_offset = arrayOopDesc::base_offset_in_bytes(T_CHAR);
3077
3078 // return true if the same array
3079 __ cmp(ary1_reg, ary2_reg);
3080 __ brx(Assembler::equal, true, Assembler::pn, Ldone);
3081 __ delayed()->add(G0, 1, result_reg); // equal
3082
3083 __ br_null(ary1_reg, true, Assembler::pn, Ldone);
3084 __ delayed()->mov(G0, result_reg); // not equal
3085
3086 __ br_null(ary2_reg, true, Assembler::pn, Ldone);
3087 __ delayed()->mov(G0, result_reg); // not equal
3088
3089 //load the lengths of arrays
3090 __ ld(Address(ary1_reg, length_offset), tmp1_reg);
3091 __ ld(Address(ary2_reg, length_offset), tmp2_reg);
3092
3093 // return false if the two arrays are not equal length
3094 __ cmp(tmp1_reg, tmp2_reg);
3095 __ br(Assembler::notEqual, true, Assembler::pn, Ldone);
3096 __ delayed()->mov(G0, result_reg); // not equal
3097
3098 __ cmp_zero_and_br(Assembler::zero, tmp1_reg, Ldone, true, Assembler::pn);
3099 __ delayed()->add(G0, 1, result_reg); // zero-length arrays are equal
3100
3101 // load array addresses
3102 __ add(ary1_reg, base_offset, ary1_reg);
3103 __ add(ary2_reg, base_offset, ary2_reg);
3104
3105 // renaming registers
3106 Register chr1_reg = result_reg; // for characters in ary1
3107 Register chr2_reg = tmp2_reg; // for characters in ary2
3108 Register limit_reg = tmp1_reg; // length
3109
3110 // set byte count
3111 __ sll(limit_reg, exact_log2(sizeof(jchar)), limit_reg);
3112
3113 // Compare char[] arrays aligned to 4 bytes.
3114 __ char_arrays_equals(ary1_reg, ary2_reg, limit_reg, result_reg,
3115 chr1_reg, chr2_reg, Ldone);
3116 __ add(G0, 1, result_reg); // equals
3117
3118 __ bind(Ldone);
3119 %}
3120
3121 enc_class enc_rethrow() %{
3122 cbuf.set_insts_mark();
3123 Register temp_reg = G3;
3124 AddressLiteral rethrow_stub(OptoRuntime::rethrow_stub());
3125 assert(temp_reg != reg_to_register_object(R_I0_num), "temp must not break oop_reg");
3126 MacroAssembler _masm(&cbuf);
3127 #ifdef ASSERT
3128 __ save_frame(0);
3129 AddressLiteral last_rethrow_addrlit(&last_rethrow);
3130 __ sethi(last_rethrow_addrlit, L1);
3131 Address addr(L1, last_rethrow_addrlit.low10());
3132 __ rdpc(L2);
3133 __ inc(L2, 3 * BytesPerInstWord); // skip this & 2 more insns to point at jump_to
3134 __ st_ptr(L2, addr);
3135 __ restore();
3136 #endif
3137 __ JUMP(rethrow_stub, temp_reg, 0); // sethi;jmp
3138 __ delayed()->nop();
3139 %}
3140
3141 enc_class emit_mem_nop() %{
3142 // Generates the instruction LDUXA [o6,g0],#0x82,g0
3143 cbuf.insts()->emit_int32((unsigned int) 0xc0839040);
3144 %}
3145
3146 enc_class emit_fadd_nop() %{
3147 // Generates the instruction FMOVS f31,f31
3148 cbuf.insts()->emit_int32((unsigned int) 0xbfa0003f);
3149 %}
3150
3151 enc_class emit_br_nop() %{
3152 // Generates the instruction BPN,PN .
3153 cbuf.insts()->emit_int32((unsigned int) 0x00400000);
3154 %}
3155
3156 enc_class enc_membar_acquire %{
3157 MacroAssembler _masm(&cbuf);
3158 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::LoadLoad) );
3159 %}
3160
3161 enc_class enc_membar_release %{
3162 MacroAssembler _masm(&cbuf);
3163 __ membar( Assembler::Membar_mask_bits(Assembler::LoadStore | Assembler::StoreStore) );
3164 %}
3165
3166 enc_class enc_membar_volatile %{
3167 MacroAssembler _masm(&cbuf);
3168 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) );
3169 %}
3170
3171 %}
3172
3173 //----------FRAME--------------------------------------------------------------
3174 // Definition of frame structure and management information.
3175 //
3176 // S T A C K L A Y O U T Allocators stack-slot number
3177 // | (to get allocators register number
3178 // G Owned by | | v add VMRegImpl::stack0)
3179 // r CALLER | |
3180 // o | +--------+ pad to even-align allocators stack-slot
3181 // w V | pad0 | numbers; owned by CALLER
3182 // t -----------+--------+----> Matcher::_in_arg_limit, unaligned
3183 // h ^ | in | 5
3184 // | | args | 4 Holes in incoming args owned by SELF
3185 // | | | | 3
3186 // | | +--------+
3187 // V | | old out| Empty on Intel, window on Sparc
3188 // | old |preserve| Must be even aligned.
3189 // | SP-+--------+----> Matcher::_old_SP, 8 (or 16 in LP64)-byte aligned
3190 // | | in | 3 area for Intel ret address
3191 // Owned by |preserve| Empty on Sparc.
3192 // SELF +--------+
3193 // | | pad2 | 2 pad to align old SP
3194 // | +--------+ 1
3195 // | | locks | 0
3196 // | +--------+----> VMRegImpl::stack0, 8 (or 16 in LP64)-byte aligned
3197 // | | pad1 | 11 pad to align new SP
3198 // | +--------+
3199 // | | | 10
3200 // | | spills | 9 spills
3201 // V | | 8 (pad0 slot for callee)
3202 // -----------+--------+----> Matcher::_out_arg_limit, unaligned
3203 // ^ | out | 7
3204 // | | args | 6 Holes in outgoing args owned by CALLEE
3205 // Owned by +--------+
3206 // CALLEE | new out| 6 Empty on Intel, window on Sparc
3207 // | new |preserve| Must be even-aligned.
3208 // | SP-+--------+----> Matcher::_new_SP, even aligned
3209 // | | |
3210 //
3211 // Note 1: Only region 8-11 is determined by the allocator. Region 0-5 is
3212 // known from SELF's arguments and the Java calling convention.
3213 // Region 6-7 is determined per call site.
3214 // Note 2: If the calling convention leaves holes in the incoming argument
3215 // area, those holes are owned by SELF. Holes in the outgoing area
3216 // are owned by the CALLEE. Holes should not be nessecary in the
3217 // incoming area, as the Java calling convention is completely under
3218 // the control of the AD file. Doubles can be sorted and packed to
3219 // avoid holes. Holes in the outgoing arguments may be necessary for
3220 // varargs C calling conventions.
3221 // Note 3: Region 0-3 is even aligned, with pad2 as needed. Region 3-5 is
3222 // even aligned with pad0 as needed.
3223 // Region 6 is even aligned. Region 6-7 is NOT even aligned;
3224 // region 6-11 is even aligned; it may be padded out more so that
3225 // the region from SP to FP meets the minimum stack alignment.
3226
3227 frame %{
3228 // What direction does stack grow in (assumed to be same for native & Java)
3229 stack_direction(TOWARDS_LOW);
3230
3231 // These two registers define part of the calling convention
3232 // between compiled code and the interpreter.
3233 inline_cache_reg(R_G5); // Inline Cache Register or Method* for I2C
3234 interpreter_method_oop_reg(R_G5); // Method Oop Register when calling interpreter
3235
3236 // Optional: name the operand used by cisc-spilling to access [stack_pointer + offset]
3237 cisc_spilling_operand_name(indOffset);
3238
3239 // Number of stack slots consumed by a Monitor enter
3240 #ifdef _LP64
3241 sync_stack_slots(2);
3242 #else
3243 sync_stack_slots(1);
3244 #endif
3245
3246 // Compiled code's Frame Pointer
3247 frame_pointer(R_SP);
3248
3249 // Stack alignment requirement
3250 stack_alignment(StackAlignmentInBytes);
3251 // LP64: Alignment size in bytes (128-bit -> 16 bytes)
3252 // !LP64: Alignment size in bytes (64-bit -> 8 bytes)
3253
3254 // Number of stack slots between incoming argument block and the start of
3255 // a new frame. The PROLOG must add this many slots to the stack. The
3256 // EPILOG must remove this many slots.
3257 in_preserve_stack_slots(0);
3258
3259 // Number of outgoing stack slots killed above the out_preserve_stack_slots
3260 // for calls to C. Supports the var-args backing area for register parms.
3261 // ADLC doesn't support parsing expressions, so I folded the math by hand.
3262 #ifdef _LP64
3263 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (0)) * 2-stack-slots-per-word
3264 varargs_C_out_slots_killed(12);
3265 #else
3266 // (callee_register_argument_save_area_words (6) + callee_aggregate_return_pointer_words (1)) * 1-stack-slots-per-word
3267 varargs_C_out_slots_killed( 7);
3268 #endif
3269
3270 // The after-PROLOG location of the return address. Location of
3271 // return address specifies a type (REG or STACK) and a number
3272 // representing the register number (i.e. - use a register name) or
3273 // stack slot.
3274 return_addr(REG R_I7); // Ret Addr is in register I7
3275
3276 // Body of function which returns an OptoRegs array locating
3277 // arguments either in registers or in stack slots for calling
3278 // java
3279 calling_convention %{
3280 (void) SharedRuntime::java_calling_convention(sig_bt, regs, length, is_outgoing);
3281
3282 %}
3283
3284 // Body of function which returns an OptoRegs array locating
3285 // arguments either in registers or in stack slots for calling
3286 // C.
3287 c_calling_convention %{
3288 // This is obviously always outgoing
3289 (void) SharedRuntime::c_calling_convention(sig_bt, regs, /*regs2=*/NULL, length);
3290 %}
3291
3292 // Location of native (C/C++) and interpreter return values. This is specified to
3293 // be the same as Java. In the 32-bit VM, long values are actually returned from
3294 // native calls in O0:O1 and returned to the interpreter in I0:I1. The copying
3295 // to and from the register pairs is done by the appropriate call and epilog
3296 // opcodes. This simplifies the register allocator.
3297 c_return_value %{
3298 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3299 #ifdef _LP64
3300 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3301 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3302 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3303 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3304 #else // !_LP64
3305 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3306 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3307 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3308 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num };
3309 #endif
3310 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3311 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3312 %}
3313
3314 // Location of compiled Java return values. Same as C
3315 return_value %{
3316 assert( ideal_reg >= Op_RegI && ideal_reg <= Op_RegL, "only return normal values" );
3317 #ifdef _LP64
3318 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_O0_num };
3319 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_O0H_num, OptoReg::Bad, R_F1_num, R_O0H_num};
3320 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_I0_num };
3321 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_I0H_num, OptoReg::Bad, R_F1_num, R_I0H_num};
3322 #else // !_LP64
3323 static int lo_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_O0_num, R_O0_num, R_O0_num, R_F0_num, R_F0_num, R_G1_num };
3324 static int hi_out[Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3325 static int lo_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, R_I0_num, R_I0_num, R_I0_num, R_F0_num, R_F0_num, R_G1_num };
3326 static int hi_in [Op_RegL+1] = { OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, OptoReg::Bad, R_F1_num, R_G1H_num};
3327 #endif
3328 return OptoRegPair( (is_outgoing?hi_out:hi_in)[ideal_reg],
3329 (is_outgoing?lo_out:lo_in)[ideal_reg] );
3330 %}
3331
3332 %}
3333
3334
3335 //----------ATTRIBUTES---------------------------------------------------------
3336 //----------Operand Attributes-------------------------------------------------
3337 op_attrib op_cost(1); // Required cost attribute
3338
3339 //----------Instruction Attributes---------------------------------------------
3340 ins_attrib ins_cost(DEFAULT_COST); // Required cost attribute
3341 ins_attrib ins_size(32); // Required size attribute (in bits)
3342
3343 // avoid_back_to_back attribute is an expression that must return
3344 // one of the following values defined in MachNode:
3345 // AVOID_NONE - instruction can be placed anywhere
3346 // AVOID_BEFORE - instruction cannot be placed after an
3347 // instruction with MachNode::AVOID_AFTER
3348 // AVOID_AFTER - the next instruction cannot be the one
3349 // with MachNode::AVOID_BEFORE
3350 // AVOID_BEFORE_AND_AFTER - BEFORE and AFTER attributes at
3351 // the same time
3352 ins_attrib ins_avoid_back_to_back(MachNode::AVOID_NONE);
3353
3354 ins_attrib ins_short_branch(0); // Required flag: is this instruction a
3355 // non-matching short branch variant of some
3356 // long branch?
3357
3358 //----------OPERANDS-----------------------------------------------------------
3359 // Operand definitions must precede instruction definitions for correct parsing
3360 // in the ADLC because operands constitute user defined types which are used in
3361 // instruction definitions.
3362
3363 //----------Simple Operands----------------------------------------------------
3364 // Immediate Operands
3365 // Integer Immediate: 32-bit
3366 operand immI() %{
3367 match(ConI);
3368
3369 op_cost(0);
3370 // formats are generated automatically for constants and base registers
3371 format %{ %}
3372 interface(CONST_INTER);
3373 %}
3374
3375 // Integer Immediate: 8-bit
3376 operand immI8() %{
3377 predicate(Assembler::is_simm8(n->get_int()));
3378 match(ConI);
3379 op_cost(0);
3380 format %{ %}
3381 interface(CONST_INTER);
3382 %}
3383
3384 // Integer Immediate: 13-bit
3385 operand immI13() %{
3386 predicate(Assembler::is_simm13(n->get_int()));
3387 match(ConI);
3388 op_cost(0);
3389
3390 format %{ %}
3391 interface(CONST_INTER);
3392 %}
3393
3394 // Integer Immediate: 13-bit minus 7
3395 operand immI13m7() %{
3396 predicate((-4096 < n->get_int()) && ((n->get_int() + 7) <= 4095));
3397 match(ConI);
3398 op_cost(0);
3399
3400 format %{ %}
3401 interface(CONST_INTER);
3402 %}
3403
3404 // Integer Immediate: 16-bit
3405 operand immI16() %{
3406 predicate(Assembler::is_simm16(n->get_int()));
3407 match(ConI);
3408 op_cost(0);
3409 format %{ %}
3410 interface(CONST_INTER);
3411 %}
3412
3413 // Unsigned Integer Immediate: 12-bit (non-negative that fits in simm13)
3414 operand immU12() %{
3415 predicate((0 <= n->get_int()) && Assembler::is_simm13(n->get_int()));
3416 match(ConI);
3417 op_cost(0);
3418
3419 format %{ %}
3420 interface(CONST_INTER);
3421 %}
3422
3423 // Integer Immediate: 6-bit
3424 operand immU6() %{
3425 predicate(n->get_int() >= 0 && n->get_int() <= 63);
3426 match(ConI);
3427 op_cost(0);
3428 format %{ %}
3429 interface(CONST_INTER);
3430 %}
3431
3432 // Integer Immediate: 11-bit
3433 operand immI11() %{
3434 predicate(Assembler::is_simm11(n->get_int()));
3435 match(ConI);
3436 op_cost(0);
3437 format %{ %}
3438 interface(CONST_INTER);
3439 %}
3440
3441 // Integer Immediate: 5-bit
3442 operand immI5() %{
3443 predicate(Assembler::is_simm5(n->get_int()));
3444 match(ConI);
3445 op_cost(0);
3446 format %{ %}
3447 interface(CONST_INTER);
3448 %}
3449
3450 // Int Immediate non-negative
3451 operand immU31()
3452 %{
3453 predicate(n->get_int() >= 0);
3454 match(ConI);
3455
3456 op_cost(0);
3457 format %{ %}
3458 interface(CONST_INTER);
3459 %}
3460
3461 // Integer Immediate: 0-bit
3462 operand immI0() %{
3463 predicate(n->get_int() == 0);
3464 match(ConI);
3465 op_cost(0);
3466
3467 format %{ %}
3468 interface(CONST_INTER);
3469 %}
3470
3471 // Integer Immediate: the value 10
3472 operand immI10() %{
3473 predicate(n->get_int() == 10);
3474 match(ConI);
3475 op_cost(0);
3476
3477 format %{ %}
3478 interface(CONST_INTER);
3479 %}
3480
3481 // Integer Immediate: the values 0-31
3482 operand immU5() %{
3483 predicate(n->get_int() >= 0 && n->get_int() <= 31);
3484 match(ConI);
3485 op_cost(0);
3486
3487 format %{ %}
3488 interface(CONST_INTER);
3489 %}
3490
3491 // Integer Immediate: the values 1-31
3492 operand immI_1_31() %{
3493 predicate(n->get_int() >= 1 && n->get_int() <= 31);
3494 match(ConI);
3495 op_cost(0);
3496
3497 format %{ %}
3498 interface(CONST_INTER);
3499 %}
3500
3501 // Integer Immediate: the values 32-63
3502 operand immI_32_63() %{
3503 predicate(n->get_int() >= 32 && n->get_int() <= 63);
3504 match(ConI);
3505 op_cost(0);
3506
3507 format %{ %}
3508 interface(CONST_INTER);
3509 %}
3510
3511 // Immediates for special shifts (sign extend)
3512
3513 // Integer Immediate: the value 16
3514 operand immI_16() %{
3515 predicate(n->get_int() == 16);
3516 match(ConI);
3517 op_cost(0);
3518
3519 format %{ %}
3520 interface(CONST_INTER);
3521 %}
3522
3523 // Integer Immediate: the value 24
3524 operand immI_24() %{
3525 predicate(n->get_int() == 24);
3526 match(ConI);
3527 op_cost(0);
3528
3529 format %{ %}
3530 interface(CONST_INTER);
3531 %}
3532
3533 // Integer Immediate: the value 255
3534 operand immI_255() %{
3535 predicate( n->get_int() == 255 );
3536 match(ConI);
3537 op_cost(0);
3538
3539 format %{ %}
3540 interface(CONST_INTER);
3541 %}
3542
3543 // Integer Immediate: the value 65535
3544 operand immI_65535() %{
3545 predicate(n->get_int() == 65535);
3546 match(ConI);
3547 op_cost(0);
3548
3549 format %{ %}
3550 interface(CONST_INTER);
3551 %}
3552
3553 // Long Immediate: the value FF
3554 operand immL_FF() %{
3555 predicate( n->get_long() == 0xFFL );
3556 match(ConL);
3557 op_cost(0);
3558
3559 format %{ %}
3560 interface(CONST_INTER);
3561 %}
3562
3563 // Long Immediate: the value FFFF
3564 operand immL_FFFF() %{
3565 predicate( n->get_long() == 0xFFFFL );
3566 match(ConL);
3567 op_cost(0);
3568
3569 format %{ %}
3570 interface(CONST_INTER);
3571 %}
3572
3573 // Pointer Immediate: 32 or 64-bit
3574 operand immP() %{
3575 match(ConP);
3576
3577 op_cost(5);
3578 // formats are generated automatically for constants and base registers
3579 format %{ %}
3580 interface(CONST_INTER);
3581 %}
3582
3583 #ifdef _LP64
3584 // Pointer Immediate: 64-bit
3585 operand immP_set() %{
3586 predicate(!VM_Version::is_niagara_plus());
3587 match(ConP);
3588
3589 op_cost(5);
3590 // formats are generated automatically for constants and base registers
3591 format %{ %}
3592 interface(CONST_INTER);
3593 %}
3594
3595 // Pointer Immediate: 64-bit
3596 // From Niagara2 processors on a load should be better than materializing.
3597 operand immP_load() %{
3598 predicate(VM_Version::is_niagara_plus() && (n->bottom_type()->isa_oop_ptr() || (MacroAssembler::insts_for_set(n->get_ptr()) > 3)));
3599 match(ConP);
3600
3601 op_cost(5);
3602 // formats are generated automatically for constants and base registers
3603 format %{ %}
3604 interface(CONST_INTER);
3605 %}
3606
3607 // Pointer Immediate: 64-bit
3608 operand immP_no_oop_cheap() %{
3609 predicate(VM_Version::is_niagara_plus() && !n->bottom_type()->isa_oop_ptr() && (MacroAssembler::insts_for_set(n->get_ptr()) <= 3));
3610 match(ConP);
3611
3612 op_cost(5);
3613 // formats are generated automatically for constants and base registers
3614 format %{ %}
3615 interface(CONST_INTER);
3616 %}
3617 #endif
3618
3619 operand immP13() %{
3620 predicate((-4096 < n->get_ptr()) && (n->get_ptr() <= 4095));
3621 match(ConP);
3622 op_cost(0);
3623
3624 format %{ %}
3625 interface(CONST_INTER);
3626 %}
3627
3628 operand immP0() %{
3629 predicate(n->get_ptr() == 0);
3630 match(ConP);
3631 op_cost(0);
3632
3633 format %{ %}
3634 interface(CONST_INTER);
3635 %}
3636
3637 operand immP_poll() %{
3638 predicate(n->get_ptr() != 0 && n->get_ptr() == (intptr_t)os::get_polling_page());
3639 match(ConP);
3640
3641 // formats are generated automatically for constants and base registers
3642 format %{ %}
3643 interface(CONST_INTER);
3644 %}
3645
3646 // Pointer Immediate
3647 operand immN()
3648 %{
3649 match(ConN);
3650
3651 op_cost(10);
3652 format %{ %}
3653 interface(CONST_INTER);
3654 %}
3655
3656 operand immNKlass()
3657 %{
3658 match(ConNKlass);
3659
3660 op_cost(10);
3661 format %{ %}
3662 interface(CONST_INTER);
3663 %}
3664
3665 // NULL Pointer Immediate
3666 operand immN0()
3667 %{
3668 predicate(n->get_narrowcon() == 0);
3669 match(ConN);
3670
3671 op_cost(0);
3672 format %{ %}
3673 interface(CONST_INTER);
3674 %}
3675
3676 operand immL() %{
3677 match(ConL);
3678 op_cost(40);
3679 // formats are generated automatically for constants and base registers
3680 format %{ %}
3681 interface(CONST_INTER);
3682 %}
3683
3684 operand immL0() %{
3685 predicate(n->get_long() == 0L);
3686 match(ConL);
3687 op_cost(0);
3688 // formats are generated automatically for constants and base registers
3689 format %{ %}
3690 interface(CONST_INTER);
3691 %}
3692
3693 // Integer Immediate: 5-bit
3694 operand immL5() %{
3695 predicate(n->get_long() == (int)n->get_long() && Assembler::is_simm5((int)n->get_long()));
3696 match(ConL);
3697 op_cost(0);
3698 format %{ %}
3699 interface(CONST_INTER);
3700 %}
3701
3702 // Long Immediate: 13-bit
3703 operand immL13() %{
3704 predicate((-4096L < n->get_long()) && (n->get_long() <= 4095L));
3705 match(ConL);
3706 op_cost(0);
3707
3708 format %{ %}
3709 interface(CONST_INTER);
3710 %}
3711
3712 // Long Immediate: 13-bit minus 7
3713 operand immL13m7() %{
3714 predicate((-4096L < n->get_long()) && ((n->get_long() + 7L) <= 4095L));
3715 match(ConL);
3716 op_cost(0);
3717
3718 format %{ %}
3719 interface(CONST_INTER);
3720 %}
3721
3722 // Long Immediate: low 32-bit mask
3723 operand immL_32bits() %{
3724 predicate(n->get_long() == 0xFFFFFFFFL);
3725 match(ConL);
3726 op_cost(0);
3727
3728 format %{ %}
3729 interface(CONST_INTER);
3730 %}
3731
3732 // Long Immediate: cheap (materialize in <= 3 instructions)
3733 operand immL_cheap() %{
3734 predicate(!VM_Version::is_niagara_plus() || MacroAssembler::insts_for_set64(n->get_long()) <= 3);
3735 match(ConL);
3736 op_cost(0);
3737
3738 format %{ %}
3739 interface(CONST_INTER);
3740 %}
3741
3742 // Long Immediate: expensive (materialize in > 3 instructions)
3743 operand immL_expensive() %{
3744 predicate(VM_Version::is_niagara_plus() && MacroAssembler::insts_for_set64(n->get_long()) > 3);
3745 match(ConL);
3746 op_cost(0);
3747
3748 format %{ %}
3749 interface(CONST_INTER);
3750 %}
3751
3752 // Double Immediate
3753 operand immD() %{
3754 match(ConD);
3755
3756 op_cost(40);
3757 format %{ %}
3758 interface(CONST_INTER);
3759 %}
3760
3761 operand immD0() %{
3762 #ifdef _LP64
3763 // on 64-bit architectures this comparision is faster
3764 predicate(jlong_cast(n->getd()) == 0);
3765 #else
3766 predicate((n->getd() == 0) && (fpclass(n->getd()) == FP_PZERO));
3767 #endif
3768 match(ConD);
3769
3770 op_cost(0);
3771 format %{ %}
3772 interface(CONST_INTER);
3773 %}
3774
3775 // Float Immediate
3776 operand immF() %{
3777 match(ConF);
3778
3779 op_cost(20);
3780 format %{ %}
3781 interface(CONST_INTER);
3782 %}
3783
3784 // Float Immediate: 0
3785 operand immF0() %{
3786 predicate((n->getf() == 0) && (fpclass(n->getf()) == FP_PZERO));
3787 match(ConF);
3788
3789 op_cost(0);
3790 format %{ %}
3791 interface(CONST_INTER);
3792 %}
3793
3794 // Integer Register Operands
3795 // Integer Register
3796 operand iRegI() %{
3797 constraint(ALLOC_IN_RC(int_reg));
3798 match(RegI);
3799
3800 match(notemp_iRegI);
3801 match(g1RegI);
3802 match(o0RegI);
3803 match(iRegIsafe);
3804
3805 format %{ %}
3806 interface(REG_INTER);
3807 %}
3808
3809 operand notemp_iRegI() %{
3810 constraint(ALLOC_IN_RC(notemp_int_reg));
3811 match(RegI);
3812
3813 match(o0RegI);
3814
3815 format %{ %}
3816 interface(REG_INTER);
3817 %}
3818
3819 operand o0RegI() %{
3820 constraint(ALLOC_IN_RC(o0_regI));
3821 match(iRegI);
3822
3823 format %{ %}
3824 interface(REG_INTER);
3825 %}
3826
3827 // Pointer Register
3828 operand iRegP() %{
3829 constraint(ALLOC_IN_RC(ptr_reg));
3830 match(RegP);
3831
3832 match(lock_ptr_RegP);
3833 match(g1RegP);
3834 match(g2RegP);
3835 match(g3RegP);
3836 match(g4RegP);
3837 match(i0RegP);
3838 match(o0RegP);
3839 match(o1RegP);
3840 match(l7RegP);
3841
3842 format %{ %}
3843 interface(REG_INTER);
3844 %}
3845
3846 operand sp_ptr_RegP() %{
3847 constraint(ALLOC_IN_RC(sp_ptr_reg));
3848 match(RegP);
3849 match(iRegP);
3850
3851 format %{ %}
3852 interface(REG_INTER);
3853 %}
3854
3855 operand lock_ptr_RegP() %{
3856 constraint(ALLOC_IN_RC(lock_ptr_reg));
3857 match(RegP);
3858 match(i0RegP);
3859 match(o0RegP);
3860 match(o1RegP);
3861 match(l7RegP);
3862
3863 format %{ %}
3864 interface(REG_INTER);
3865 %}
3866
3867 operand g1RegP() %{
3868 constraint(ALLOC_IN_RC(g1_regP));
3869 match(iRegP);
3870
3871 format %{ %}
3872 interface(REG_INTER);
3873 %}
3874
3875 operand g2RegP() %{
3876 constraint(ALLOC_IN_RC(g2_regP));
3877 match(iRegP);
3878
3879 format %{ %}
3880 interface(REG_INTER);
3881 %}
3882
3883 operand g3RegP() %{
3884 constraint(ALLOC_IN_RC(g3_regP));
3885 match(iRegP);
3886
3887 format %{ %}
3888 interface(REG_INTER);
3889 %}
3890
3891 operand g1RegI() %{
3892 constraint(ALLOC_IN_RC(g1_regI));
3893 match(iRegI);
3894
3895 format %{ %}
3896 interface(REG_INTER);
3897 %}
3898
3899 operand g3RegI() %{
3900 constraint(ALLOC_IN_RC(g3_regI));
3901 match(iRegI);
3902
3903 format %{ %}
3904 interface(REG_INTER);
3905 %}
3906
3907 operand g4RegI() %{
3908 constraint(ALLOC_IN_RC(g4_regI));
3909 match(iRegI);
3910
3911 format %{ %}
3912 interface(REG_INTER);
3913 %}
3914
3915 operand g4RegP() %{
3916 constraint(ALLOC_IN_RC(g4_regP));
3917 match(iRegP);
3918
3919 format %{ %}
3920 interface(REG_INTER);
3921 %}
3922
3923 operand i0RegP() %{
3924 constraint(ALLOC_IN_RC(i0_regP));
3925 match(iRegP);
3926
3927 format %{ %}
3928 interface(REG_INTER);
3929 %}
3930
3931 operand o0RegP() %{
3932 constraint(ALLOC_IN_RC(o0_regP));
3933 match(iRegP);
3934
3935 format %{ %}
3936 interface(REG_INTER);
3937 %}
3938
3939 operand o1RegP() %{
3940 constraint(ALLOC_IN_RC(o1_regP));
3941 match(iRegP);
3942
3943 format %{ %}
3944 interface(REG_INTER);
3945 %}
3946
3947 operand o2RegP() %{
3948 constraint(ALLOC_IN_RC(o2_regP));
3949 match(iRegP);
3950
3951 format %{ %}
3952 interface(REG_INTER);
3953 %}
3954
3955 operand o7RegP() %{
3956 constraint(ALLOC_IN_RC(o7_regP));
3957 match(iRegP);
3958
3959 format %{ %}
3960 interface(REG_INTER);
3961 %}
3962
3963 operand l7RegP() %{
3964 constraint(ALLOC_IN_RC(l7_regP));
3965 match(iRegP);
3966
3967 format %{ %}
3968 interface(REG_INTER);
3969 %}
3970
3971 operand o7RegI() %{
3972 constraint(ALLOC_IN_RC(o7_regI));
3973 match(iRegI);
3974
3975 format %{ %}
3976 interface(REG_INTER);
3977 %}
3978
3979 operand iRegN() %{
3980 constraint(ALLOC_IN_RC(int_reg));
3981 match(RegN);
3982
3983 format %{ %}
3984 interface(REG_INTER);
3985 %}
3986
3987 // Long Register
3988 operand iRegL() %{
3989 constraint(ALLOC_IN_RC(long_reg));
3990 match(RegL);
3991
3992 format %{ %}
3993 interface(REG_INTER);
3994 %}
3995
3996 operand o2RegL() %{
3997 constraint(ALLOC_IN_RC(o2_regL));
3998 match(iRegL);
3999
4000 format %{ %}
4001 interface(REG_INTER);
4002 %}
4003
4004 operand o7RegL() %{
4005 constraint(ALLOC_IN_RC(o7_regL));
4006 match(iRegL);
4007
4008 format %{ %}
4009 interface(REG_INTER);
4010 %}
4011
4012 operand g1RegL() %{
4013 constraint(ALLOC_IN_RC(g1_regL));
4014 match(iRegL);
4015
4016 format %{ %}
4017 interface(REG_INTER);
4018 %}
4019
4020 operand g3RegL() %{
4021 constraint(ALLOC_IN_RC(g3_regL));
4022 match(iRegL);
4023
4024 format %{ %}
4025 interface(REG_INTER);
4026 %}
4027
4028 // Int Register safe
4029 // This is 64bit safe
4030 operand iRegIsafe() %{
4031 constraint(ALLOC_IN_RC(long_reg));
4032
4033 match(iRegI);
4034
4035 format %{ %}
4036 interface(REG_INTER);
4037 %}
4038
4039 // Condition Code Flag Register
4040 operand flagsReg() %{
4041 constraint(ALLOC_IN_RC(int_flags));
4042 match(RegFlags);
4043
4044 format %{ "ccr" %} // both ICC and XCC
4045 interface(REG_INTER);
4046 %}
4047
4048 // Condition Code Register, unsigned comparisons.
4049 operand flagsRegU() %{
4050 constraint(ALLOC_IN_RC(int_flags));
4051 match(RegFlags);
4052
4053 format %{ "icc_U" %}
4054 interface(REG_INTER);
4055 %}
4056
4057 // Condition Code Register, pointer comparisons.
4058 operand flagsRegP() %{
4059 constraint(ALLOC_IN_RC(int_flags));
4060 match(RegFlags);
4061
4062 #ifdef _LP64
4063 format %{ "xcc_P" %}
4064 #else
4065 format %{ "icc_P" %}
4066 #endif
4067 interface(REG_INTER);
4068 %}
4069
4070 // Condition Code Register, long comparisons.
4071 operand flagsRegL() %{
4072 constraint(ALLOC_IN_RC(int_flags));
4073 match(RegFlags);
4074
4075 format %{ "xcc_L" %}
4076 interface(REG_INTER);
4077 %}
4078
4079 // Condition Code Register, floating comparisons, unordered same as "less".
4080 operand flagsRegF() %{
4081 constraint(ALLOC_IN_RC(float_flags));
4082 match(RegFlags);
4083 match(flagsRegF0);
4084
4085 format %{ %}
4086 interface(REG_INTER);
4087 %}
4088
4089 operand flagsRegF0() %{
4090 constraint(ALLOC_IN_RC(float_flag0));
4091 match(RegFlags);
4092
4093 format %{ %}
4094 interface(REG_INTER);
4095 %}
4096
4097
4098 // Condition Code Flag Register used by long compare
4099 operand flagsReg_long_LTGE() %{
4100 constraint(ALLOC_IN_RC(int_flags));
4101 match(RegFlags);
4102 format %{ "icc_LTGE" %}
4103 interface(REG_INTER);
4104 %}
4105 operand flagsReg_long_EQNE() %{
4106 constraint(ALLOC_IN_RC(int_flags));
4107 match(RegFlags);
4108 format %{ "icc_EQNE" %}
4109 interface(REG_INTER);
4110 %}
4111 operand flagsReg_long_LEGT() %{
4112 constraint(ALLOC_IN_RC(int_flags));
4113 match(RegFlags);
4114 format %{ "icc_LEGT" %}
4115 interface(REG_INTER);
4116 %}
4117
4118
4119 operand regD() %{
4120 constraint(ALLOC_IN_RC(dflt_reg));
4121 match(RegD);
4122
4123 match(regD_low);
4124
4125 format %{ %}
4126 interface(REG_INTER);
4127 %}
4128
4129 operand regF() %{
4130 constraint(ALLOC_IN_RC(sflt_reg));
4131 match(RegF);
4132
4133 format %{ %}
4134 interface(REG_INTER);
4135 %}
4136
4137 operand regD_low() %{
4138 constraint(ALLOC_IN_RC(dflt_low_reg));
4139 match(regD);
4140
4141 format %{ %}
4142 interface(REG_INTER);
4143 %}
4144
4145 // Special Registers
4146
4147 // Method Register
4148 operand inline_cache_regP(iRegP reg) %{
4149 constraint(ALLOC_IN_RC(g5_regP)); // G5=inline_cache_reg but uses 2 bits instead of 1
4150 match(reg);
4151 format %{ %}
4152 interface(REG_INTER);
4153 %}
4154
4155 operand interpreter_method_oop_regP(iRegP reg) %{
4156 constraint(ALLOC_IN_RC(g5_regP)); // G5=interpreter_method_oop_reg but uses 2 bits instead of 1
4157 match(reg);
4158 format %{ %}
4159 interface(REG_INTER);
4160 %}
4161
4162
4163 //----------Complex Operands---------------------------------------------------
4164 // Indirect Memory Reference
4165 operand indirect(sp_ptr_RegP reg) %{
4166 constraint(ALLOC_IN_RC(sp_ptr_reg));
4167 match(reg);
4168
4169 op_cost(100);
4170 format %{ "[$reg]" %}
4171 interface(MEMORY_INTER) %{
4172 base($reg);
4173 index(0x0);
4174 scale(0x0);
4175 disp(0x0);
4176 %}
4177 %}
4178
4179 // Indirect with simm13 Offset
4180 operand indOffset13(sp_ptr_RegP reg, immX13 offset) %{
4181 constraint(ALLOC_IN_RC(sp_ptr_reg));
4182 match(AddP reg offset);
4183
4184 op_cost(100);
4185 format %{ "[$reg + $offset]" %}
4186 interface(MEMORY_INTER) %{
4187 base($reg);
4188 index(0x0);
4189 scale(0x0);
4190 disp($offset);
4191 %}
4192 %}
4193
4194 // Indirect with simm13 Offset minus 7
4195 operand indOffset13m7(sp_ptr_RegP reg, immX13m7 offset) %{
4196 constraint(ALLOC_IN_RC(sp_ptr_reg));
4197 match(AddP reg offset);
4198
4199 op_cost(100);
4200 format %{ "[$reg + $offset]" %}
4201 interface(MEMORY_INTER) %{
4202 base($reg);
4203 index(0x0);
4204 scale(0x0);
4205 disp($offset);
4206 %}
4207 %}
4208
4209 // Note: Intel has a swapped version also, like this:
4210 //operand indOffsetX(iRegI reg, immP offset) %{
4211 // constraint(ALLOC_IN_RC(int_reg));
4212 // match(AddP offset reg);
4213 //
4214 // op_cost(100);
4215 // format %{ "[$reg + $offset]" %}
4216 // interface(MEMORY_INTER) %{
4217 // base($reg);
4218 // index(0x0);
4219 // scale(0x0);
4220 // disp($offset);
4221 // %}
4222 //%}
4223 //// However, it doesn't make sense for SPARC, since
4224 // we have no particularly good way to embed oops in
4225 // single instructions.
4226
4227 // Indirect with Register Index
4228 operand indIndex(iRegP addr, iRegX index) %{
4229 constraint(ALLOC_IN_RC(ptr_reg));
4230 match(AddP addr index);
4231
4232 op_cost(100);
4233 format %{ "[$addr + $index]" %}
4234 interface(MEMORY_INTER) %{
4235 base($addr);
4236 index($index);
4237 scale(0x0);
4238 disp(0x0);
4239 %}
4240 %}
4241
4242 //----------Special Memory Operands--------------------------------------------
4243 // Stack Slot Operand - This operand is used for loading and storing temporary
4244 // values on the stack where a match requires a value to
4245 // flow through memory.
4246 operand stackSlotI(sRegI reg) %{
4247 constraint(ALLOC_IN_RC(stack_slots));
4248 op_cost(100);
4249 //match(RegI);
4250 format %{ "[$reg]" %}
4251 interface(MEMORY_INTER) %{
4252 base(0xE); // R_SP
4253 index(0x0);
4254 scale(0x0);
4255 disp($reg); // Stack Offset
4256 %}
4257 %}
4258
4259 operand stackSlotP(sRegP reg) %{
4260 constraint(ALLOC_IN_RC(stack_slots));
4261 op_cost(100);
4262 //match(RegP);
4263 format %{ "[$reg]" %}
4264 interface(MEMORY_INTER) %{
4265 base(0xE); // R_SP
4266 index(0x0);
4267 scale(0x0);
4268 disp($reg); // Stack Offset
4269 %}
4270 %}
4271
4272 operand stackSlotF(sRegF reg) %{
4273 constraint(ALLOC_IN_RC(stack_slots));
4274 op_cost(100);
4275 //match(RegF);
4276 format %{ "[$reg]" %}
4277 interface(MEMORY_INTER) %{
4278 base(0xE); // R_SP
4279 index(0x0);
4280 scale(0x0);
4281 disp($reg); // Stack Offset
4282 %}
4283 %}
4284 operand stackSlotD(sRegD reg) %{
4285 constraint(ALLOC_IN_RC(stack_slots));
4286 op_cost(100);
4287 //match(RegD);
4288 format %{ "[$reg]" %}
4289 interface(MEMORY_INTER) %{
4290 base(0xE); // R_SP
4291 index(0x0);
4292 scale(0x0);
4293 disp($reg); // Stack Offset
4294 %}
4295 %}
4296 operand stackSlotL(sRegL reg) %{
4297 constraint(ALLOC_IN_RC(stack_slots));
4298 op_cost(100);
4299 //match(RegL);
4300 format %{ "[$reg]" %}
4301 interface(MEMORY_INTER) %{
4302 base(0xE); // R_SP
4303 index(0x0);
4304 scale(0x0);
4305 disp($reg); // Stack Offset
4306 %}
4307 %}
4308
4309 // Operands for expressing Control Flow
4310 // NOTE: Label is a predefined operand which should not be redefined in
4311 // the AD file. It is generically handled within the ADLC.
4312
4313 //----------Conditional Branch Operands----------------------------------------
4314 // Comparison Op - This is the operation of the comparison, and is limited to
4315 // the following set of codes:
4316 // L (<), LE (<=), G (>), GE (>=), E (==), NE (!=)
4317 //
4318 // Other attributes of the comparison, such as unsignedness, are specified
4319 // by the comparison instruction that sets a condition code flags register.
4320 // That result is represented by a flags operand whose subtype is appropriate
4321 // to the unsignedness (etc.) of the comparison.
4322 //
4323 // Later, the instruction which matches both the Comparison Op (a Bool) and
4324 // the flags (produced by the Cmp) specifies the coding of the comparison op
4325 // by matching a specific subtype of Bool operand below, such as cmpOpU.
4326
4327 operand cmpOp() %{
4328 match(Bool);
4329
4330 format %{ "" %}
4331 interface(COND_INTER) %{
4332 equal(0x1);
4333 not_equal(0x9);
4334 less(0x3);
4335 greater_equal(0xB);
4336 less_equal(0x2);
4337 greater(0xA);
4338 overflow(0x7);
4339 no_overflow(0xF);
4340 %}
4341 %}
4342
4343 // Comparison Op, unsigned
4344 operand cmpOpU() %{
4345 match(Bool);
4346 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4347 n->as_Bool()->_test._test != BoolTest::no_overflow);
4348
4349 format %{ "u" %}
4350 interface(COND_INTER) %{
4351 equal(0x1);
4352 not_equal(0x9);
4353 less(0x5);
4354 greater_equal(0xD);
4355 less_equal(0x4);
4356 greater(0xC);
4357 overflow(0x7);
4358 no_overflow(0xF);
4359 %}
4360 %}
4361
4362 // Comparison Op, pointer (same as unsigned)
4363 operand cmpOpP() %{
4364 match(Bool);
4365 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4366 n->as_Bool()->_test._test != BoolTest::no_overflow);
4367
4368 format %{ "p" %}
4369 interface(COND_INTER) %{
4370 equal(0x1);
4371 not_equal(0x9);
4372 less(0x5);
4373 greater_equal(0xD);
4374 less_equal(0x4);
4375 greater(0xC);
4376 overflow(0x7);
4377 no_overflow(0xF);
4378 %}
4379 %}
4380
4381 // Comparison Op, branch-register encoding
4382 operand cmpOp_reg() %{
4383 match(Bool);
4384 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4385 n->as_Bool()->_test._test != BoolTest::no_overflow);
4386
4387 format %{ "" %}
4388 interface(COND_INTER) %{
4389 equal (0x1);
4390 not_equal (0x5);
4391 less (0x3);
4392 greater_equal(0x7);
4393 less_equal (0x2);
4394 greater (0x6);
4395 overflow(0x7); // not supported
4396 no_overflow(0xF); // not supported
4397 %}
4398 %}
4399
4400 // Comparison Code, floating, unordered same as less
4401 operand cmpOpF() %{
4402 match(Bool);
4403 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4404 n->as_Bool()->_test._test != BoolTest::no_overflow);
4405
4406 format %{ "fl" %}
4407 interface(COND_INTER) %{
4408 equal(0x9);
4409 not_equal(0x1);
4410 less(0x3);
4411 greater_equal(0xB);
4412 less_equal(0xE);
4413 greater(0x6);
4414
4415 overflow(0x7); // not supported
4416 no_overflow(0xF); // not supported
4417 %}
4418 %}
4419
4420 // Used by long compare
4421 operand cmpOp_commute() %{
4422 match(Bool);
4423 predicate(n->as_Bool()->_test._test != BoolTest::overflow &&
4424 n->as_Bool()->_test._test != BoolTest::no_overflow);
4425
4426 format %{ "" %}
4427 interface(COND_INTER) %{
4428 equal(0x1);
4429 not_equal(0x9);
4430 less(0xA);
4431 greater_equal(0x2);
4432 less_equal(0xB);
4433 greater(0x3);
4434 overflow(0x7);
4435 no_overflow(0xF);
4436 %}
4437 %}
4438
4439 //----------OPERAND CLASSES----------------------------------------------------
4440 // Operand Classes are groups of operands that are used to simplify
4441 // instruction definitions by not requiring the AD writer to specify separate
4442 // instructions for every form of operand when the instruction accepts
4443 // multiple operand types with the same basic encoding and format. The classic
4444 // case of this is memory operands.
4445 opclass memory( indirect, indOffset13, indIndex );
4446 opclass indIndexMemory( indIndex );
4447
4448 //----------PIPELINE-----------------------------------------------------------
4449 pipeline %{
4450
4451 //----------ATTRIBUTES---------------------------------------------------------
4452 attributes %{
4453 fixed_size_instructions; // Fixed size instructions
4454 branch_has_delay_slot; // Branch has delay slot following
4455 max_instructions_per_bundle = 4; // Up to 4 instructions per bundle
4456 instruction_unit_size = 4; // An instruction is 4 bytes long
4457 instruction_fetch_unit_size = 16; // The processor fetches one line
4458 instruction_fetch_units = 1; // of 16 bytes
4459
4460 // List of nop instructions
4461 nops( Nop_A0, Nop_A1, Nop_MS, Nop_FA, Nop_BR );
4462 %}
4463
4464 //----------RESOURCES----------------------------------------------------------
4465 // Resources are the functional units available to the machine
4466 resources(A0, A1, MS, BR, FA, FM, IDIV, FDIV, IALU = A0 | A1);
4467
4468 //----------PIPELINE DESCRIPTION-----------------------------------------------
4469 // Pipeline Description specifies the stages in the machine's pipeline
4470
4471 pipe_desc(A, P, F, B, I, J, S, R, E, C, M, W, X, T, D);
4472
4473 //----------PIPELINE CLASSES---------------------------------------------------
4474 // Pipeline Classes describe the stages in which input and output are
4475 // referenced by the hardware pipeline.
4476
4477 // Integer ALU reg-reg operation
4478 pipe_class ialu_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4479 single_instruction;
4480 dst : E(write);
4481 src1 : R(read);
4482 src2 : R(read);
4483 IALU : R;
4484 %}
4485
4486 // Integer ALU reg-reg long operation
4487 pipe_class ialu_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
4488 instruction_count(2);
4489 dst : E(write);
4490 src1 : R(read);
4491 src2 : R(read);
4492 IALU : R;
4493 IALU : R;
4494 %}
4495
4496 // Integer ALU reg-reg long dependent operation
4497 pipe_class ialu_reg_reg_2_dep(iRegL dst, iRegL src1, iRegL src2, flagsReg cr) %{
4498 instruction_count(1); multiple_bundles;
4499 dst : E(write);
4500 src1 : R(read);
4501 src2 : R(read);
4502 cr : E(write);
4503 IALU : R(2);
4504 %}
4505
4506 // Integer ALU reg-imm operaion
4507 pipe_class ialu_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4508 single_instruction;
4509 dst : E(write);
4510 src1 : R(read);
4511 IALU : R;
4512 %}
4513
4514 // Integer ALU reg-reg operation with condition code
4515 pipe_class ialu_cc_reg_reg(iRegI dst, iRegI src1, iRegI src2, flagsReg cr) %{
4516 single_instruction;
4517 dst : E(write);
4518 cr : E(write);
4519 src1 : R(read);
4520 src2 : R(read);
4521 IALU : R;
4522 %}
4523
4524 // Integer ALU reg-imm operation with condition code
4525 pipe_class ialu_cc_reg_imm(iRegI dst, iRegI src1, immI13 src2, flagsReg cr) %{
4526 single_instruction;
4527 dst : E(write);
4528 cr : E(write);
4529 src1 : R(read);
4530 IALU : R;
4531 %}
4532
4533 // Integer ALU zero-reg operation
4534 pipe_class ialu_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
4535 single_instruction;
4536 dst : E(write);
4537 src2 : R(read);
4538 IALU : R;
4539 %}
4540
4541 // Integer ALU zero-reg operation with condition code only
4542 pipe_class ialu_cconly_zero_reg(flagsReg cr, iRegI src) %{
4543 single_instruction;
4544 cr : E(write);
4545 src : R(read);
4546 IALU : R;
4547 %}
4548
4549 // Integer ALU reg-reg operation with condition code only
4550 pipe_class ialu_cconly_reg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4551 single_instruction;
4552 cr : E(write);
4553 src1 : R(read);
4554 src2 : R(read);
4555 IALU : R;
4556 %}
4557
4558 // Integer ALU reg-imm operation with condition code only
4559 pipe_class ialu_cconly_reg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4560 single_instruction;
4561 cr : E(write);
4562 src1 : R(read);
4563 IALU : R;
4564 %}
4565
4566 // Integer ALU reg-reg-zero operation with condition code only
4567 pipe_class ialu_cconly_reg_reg_zero(flagsReg cr, iRegI src1, iRegI src2, immI0 zero) %{
4568 single_instruction;
4569 cr : E(write);
4570 src1 : R(read);
4571 src2 : R(read);
4572 IALU : R;
4573 %}
4574
4575 // Integer ALU reg-imm-zero operation with condition code only
4576 pipe_class ialu_cconly_reg_imm_zero(flagsReg cr, iRegI src1, immI13 src2, immI0 zero) %{
4577 single_instruction;
4578 cr : E(write);
4579 src1 : R(read);
4580 IALU : R;
4581 %}
4582
4583 // Integer ALU reg-reg operation with condition code, src1 modified
4584 pipe_class ialu_cc_rwreg_reg(flagsReg cr, iRegI src1, iRegI src2) %{
4585 single_instruction;
4586 cr : E(write);
4587 src1 : E(write);
4588 src1 : R(read);
4589 src2 : R(read);
4590 IALU : R;
4591 %}
4592
4593 // Integer ALU reg-imm operation with condition code, src1 modified
4594 pipe_class ialu_cc_rwreg_imm(flagsReg cr, iRegI src1, immI13 src2) %{
4595 single_instruction;
4596 cr : E(write);
4597 src1 : E(write);
4598 src1 : R(read);
4599 IALU : R;
4600 %}
4601
4602 pipe_class cmpL_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg cr ) %{
4603 multiple_bundles;
4604 dst : E(write)+4;
4605 cr : E(write);
4606 src1 : R(read);
4607 src2 : R(read);
4608 IALU : R(3);
4609 BR : R(2);
4610 %}
4611
4612 // Integer ALU operation
4613 pipe_class ialu_none(iRegI dst) %{
4614 single_instruction;
4615 dst : E(write);
4616 IALU : R;
4617 %}
4618
4619 // Integer ALU reg operation
4620 pipe_class ialu_reg(iRegI dst, iRegI src) %{
4621 single_instruction; may_have_no_code;
4622 dst : E(write);
4623 src : R(read);
4624 IALU : R;
4625 %}
4626
4627 // Integer ALU reg conditional operation
4628 // This instruction has a 1 cycle stall, and cannot execute
4629 // in the same cycle as the instruction setting the condition
4630 // code. We kludge this by pretending to read the condition code
4631 // 1 cycle earlier, and by marking the functional units as busy
4632 // for 2 cycles with the result available 1 cycle later than
4633 // is really the case.
4634 pipe_class ialu_reg_flags( iRegI op2_out, iRegI op2_in, iRegI op1, flagsReg cr ) %{
4635 single_instruction;
4636 op2_out : C(write);
4637 op1 : R(read);
4638 cr : R(read); // This is really E, with a 1 cycle stall
4639 BR : R(2);
4640 MS : R(2);
4641 %}
4642
4643 #ifdef _LP64
4644 pipe_class ialu_clr_and_mover( iRegI dst, iRegP src ) %{
4645 instruction_count(1); multiple_bundles;
4646 dst : C(write)+1;
4647 src : R(read)+1;
4648 IALU : R(1);
4649 BR : E(2);
4650 MS : E(2);
4651 %}
4652 #endif
4653
4654 // Integer ALU reg operation
4655 pipe_class ialu_move_reg_L_to_I(iRegI dst, iRegL src) %{
4656 single_instruction; may_have_no_code;
4657 dst : E(write);
4658 src : R(read);
4659 IALU : R;
4660 %}
4661 pipe_class ialu_move_reg_I_to_L(iRegL dst, iRegI src) %{
4662 single_instruction; may_have_no_code;
4663 dst : E(write);
4664 src : R(read);
4665 IALU : R;
4666 %}
4667
4668 // Two integer ALU reg operations
4669 pipe_class ialu_reg_2(iRegL dst, iRegL src) %{
4670 instruction_count(2);
4671 dst : E(write);
4672 src : R(read);
4673 A0 : R;
4674 A1 : R;
4675 %}
4676
4677 // Two integer ALU reg operations
4678 pipe_class ialu_move_reg_L_to_L(iRegL dst, iRegL src) %{
4679 instruction_count(2); may_have_no_code;
4680 dst : E(write);
4681 src : R(read);
4682 A0 : R;
4683 A1 : R;
4684 %}
4685
4686 // Integer ALU imm operation
4687 pipe_class ialu_imm(iRegI dst, immI13 src) %{
4688 single_instruction;
4689 dst : E(write);
4690 IALU : R;
4691 %}
4692
4693 // Integer ALU reg-reg with carry operation
4694 pipe_class ialu_reg_reg_cy(iRegI dst, iRegI src1, iRegI src2, iRegI cy) %{
4695 single_instruction;
4696 dst : E(write);
4697 src1 : R(read);
4698 src2 : R(read);
4699 IALU : R;
4700 %}
4701
4702 // Integer ALU cc operation
4703 pipe_class ialu_cc(iRegI dst, flagsReg cc) %{
4704 single_instruction;
4705 dst : E(write);
4706 cc : R(read);
4707 IALU : R;
4708 %}
4709
4710 // Integer ALU cc / second IALU operation
4711 pipe_class ialu_reg_ialu( iRegI dst, iRegI src ) %{
4712 instruction_count(1); multiple_bundles;
4713 dst : E(write)+1;
4714 src : R(read);
4715 IALU : R;
4716 %}
4717
4718 // Integer ALU cc / second IALU operation
4719 pipe_class ialu_reg_reg_ialu( iRegI dst, iRegI p, iRegI q ) %{
4720 instruction_count(1); multiple_bundles;
4721 dst : E(write)+1;
4722 p : R(read);
4723 q : R(read);
4724 IALU : R;
4725 %}
4726
4727 // Integer ALU hi-lo-reg operation
4728 pipe_class ialu_hi_lo_reg(iRegI dst, immI src) %{
4729 instruction_count(1); multiple_bundles;
4730 dst : E(write)+1;
4731 IALU : R(2);
4732 %}
4733
4734 // Float ALU hi-lo-reg operation (with temp)
4735 pipe_class ialu_hi_lo_reg_temp(regF dst, immF src, g3RegP tmp) %{
4736 instruction_count(1); multiple_bundles;
4737 dst : E(write)+1;
4738 IALU : R(2);
4739 %}
4740
4741 // Long Constant
4742 pipe_class loadConL( iRegL dst, immL src ) %{
4743 instruction_count(2); multiple_bundles;
4744 dst : E(write)+1;
4745 IALU : R(2);
4746 IALU : R(2);
4747 %}
4748
4749 // Pointer Constant
4750 pipe_class loadConP( iRegP dst, immP src ) %{
4751 instruction_count(0); multiple_bundles;
4752 fixed_latency(6);
4753 %}
4754
4755 // Polling Address
4756 pipe_class loadConP_poll( iRegP dst, immP_poll src ) %{
4757 #ifdef _LP64
4758 instruction_count(0); multiple_bundles;
4759 fixed_latency(6);
4760 #else
4761 dst : E(write);
4762 IALU : R;
4763 #endif
4764 %}
4765
4766 // Long Constant small
4767 pipe_class loadConLlo( iRegL dst, immL src ) %{
4768 instruction_count(2);
4769 dst : E(write);
4770 IALU : R;
4771 IALU : R;
4772 %}
4773
4774 // [PHH] This is wrong for 64-bit. See LdImmF/D.
4775 pipe_class loadConFD(regF dst, immF src, g3RegP tmp) %{
4776 instruction_count(1); multiple_bundles;
4777 src : R(read);
4778 dst : M(write)+1;
4779 IALU : R;
4780 MS : E;
4781 %}
4782
4783 // Integer ALU nop operation
4784 pipe_class ialu_nop() %{
4785 single_instruction;
4786 IALU : R;
4787 %}
4788
4789 // Integer ALU nop operation
4790 pipe_class ialu_nop_A0() %{
4791 single_instruction;
4792 A0 : R;
4793 %}
4794
4795 // Integer ALU nop operation
4796 pipe_class ialu_nop_A1() %{
4797 single_instruction;
4798 A1 : R;
4799 %}
4800
4801 // Integer Multiply reg-reg operation
4802 pipe_class imul_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
4803 single_instruction;
4804 dst : E(write);
4805 src1 : R(read);
4806 src2 : R(read);
4807 MS : R(5);
4808 %}
4809
4810 // Integer Multiply reg-imm operation
4811 pipe_class imul_reg_imm(iRegI dst, iRegI src1, immI13 src2) %{
4812 single_instruction;
4813 dst : E(write);
4814 src1 : R(read);
4815 MS : R(5);
4816 %}
4817
4818 pipe_class mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4819 single_instruction;
4820 dst : E(write)+4;
4821 src1 : R(read);
4822 src2 : R(read);
4823 MS : R(6);
4824 %}
4825
4826 pipe_class mulL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4827 single_instruction;
4828 dst : E(write)+4;
4829 src1 : R(read);
4830 MS : R(6);
4831 %}
4832
4833 // Integer Divide reg-reg
4834 pipe_class sdiv_reg_reg(iRegI dst, iRegI src1, iRegI src2, iRegI temp, flagsReg cr) %{
4835 instruction_count(1); multiple_bundles;
4836 dst : E(write);
4837 temp : E(write);
4838 src1 : R(read);
4839 src2 : R(read);
4840 temp : R(read);
4841 MS : R(38);
4842 %}
4843
4844 // Integer Divide reg-imm
4845 pipe_class sdiv_reg_imm(iRegI dst, iRegI src1, immI13 src2, iRegI temp, flagsReg cr) %{
4846 instruction_count(1); multiple_bundles;
4847 dst : E(write);
4848 temp : E(write);
4849 src1 : R(read);
4850 temp : R(read);
4851 MS : R(38);
4852 %}
4853
4854 // Long Divide
4855 pipe_class divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
4856 dst : E(write)+71;
4857 src1 : R(read);
4858 src2 : R(read)+1;
4859 MS : R(70);
4860 %}
4861
4862 pipe_class divL_reg_imm(iRegL dst, iRegL src1, immL13 src2) %{
4863 dst : E(write)+71;
4864 src1 : R(read);
4865 MS : R(70);
4866 %}
4867
4868 // Floating Point Add Float
4869 pipe_class faddF_reg_reg(regF dst, regF src1, regF src2) %{
4870 single_instruction;
4871 dst : X(write);
4872 src1 : E(read);
4873 src2 : E(read);
4874 FA : R;
4875 %}
4876
4877 // Floating Point Add Double
4878 pipe_class faddD_reg_reg(regD dst, regD src1, regD src2) %{
4879 single_instruction;
4880 dst : X(write);
4881 src1 : E(read);
4882 src2 : E(read);
4883 FA : R;
4884 %}
4885
4886 // Floating Point Conditional Move based on integer flags
4887 pipe_class int_conditional_float_move (cmpOp cmp, flagsReg cr, regF dst, regF src) %{
4888 single_instruction;
4889 dst : X(write);
4890 src : E(read);
4891 cr : R(read);
4892 FA : R(2);
4893 BR : R(2);
4894 %}
4895
4896 // Floating Point Conditional Move based on integer flags
4897 pipe_class int_conditional_double_move (cmpOp cmp, flagsReg cr, regD dst, regD src) %{
4898 single_instruction;
4899 dst : X(write);
4900 src : E(read);
4901 cr : R(read);
4902 FA : R(2);
4903 BR : R(2);
4904 %}
4905
4906 // Floating Point Multiply Float
4907 pipe_class fmulF_reg_reg(regF dst, regF src1, regF src2) %{
4908 single_instruction;
4909 dst : X(write);
4910 src1 : E(read);
4911 src2 : E(read);
4912 FM : R;
4913 %}
4914
4915 // Floating Point Multiply Double
4916 pipe_class fmulD_reg_reg(regD dst, regD src1, regD src2) %{
4917 single_instruction;
4918 dst : X(write);
4919 src1 : E(read);
4920 src2 : E(read);
4921 FM : R;
4922 %}
4923
4924 // Floating Point Divide Float
4925 pipe_class fdivF_reg_reg(regF dst, regF src1, regF src2) %{
4926 single_instruction;
4927 dst : X(write);
4928 src1 : E(read);
4929 src2 : E(read);
4930 FM : R;
4931 FDIV : C(14);
4932 %}
4933
4934 // Floating Point Divide Double
4935 pipe_class fdivD_reg_reg(regD dst, regD src1, regD src2) %{
4936 single_instruction;
4937 dst : X(write);
4938 src1 : E(read);
4939 src2 : E(read);
4940 FM : R;
4941 FDIV : C(17);
4942 %}
4943
4944 // Floating Point Move/Negate/Abs Float
4945 pipe_class faddF_reg(regF dst, regF src) %{
4946 single_instruction;
4947 dst : W(write);
4948 src : E(read);
4949 FA : R(1);
4950 %}
4951
4952 // Floating Point Move/Negate/Abs Double
4953 pipe_class faddD_reg(regD dst, regD src) %{
4954 single_instruction;
4955 dst : W(write);
4956 src : E(read);
4957 FA : R;
4958 %}
4959
4960 // Floating Point Convert F->D
4961 pipe_class fcvtF2D(regD dst, regF src) %{
4962 single_instruction;
4963 dst : X(write);
4964 src : E(read);
4965 FA : R;
4966 %}
4967
4968 // Floating Point Convert I->D
4969 pipe_class fcvtI2D(regD dst, regF src) %{
4970 single_instruction;
4971 dst : X(write);
4972 src : E(read);
4973 FA : R;
4974 %}
4975
4976 // Floating Point Convert LHi->D
4977 pipe_class fcvtLHi2D(regD dst, regD src) %{
4978 single_instruction;
4979 dst : X(write);
4980 src : E(read);
4981 FA : R;
4982 %}
4983
4984 // Floating Point Convert L->D
4985 pipe_class fcvtL2D(regD dst, regF src) %{
4986 single_instruction;
4987 dst : X(write);
4988 src : E(read);
4989 FA : R;
4990 %}
4991
4992 // Floating Point Convert L->F
4993 pipe_class fcvtL2F(regD dst, regF src) %{
4994 single_instruction;
4995 dst : X(write);
4996 src : E(read);
4997 FA : R;
4998 %}
4999
5000 // Floating Point Convert D->F
5001 pipe_class fcvtD2F(regD dst, regF src) %{
5002 single_instruction;
5003 dst : X(write);
5004 src : E(read);
5005 FA : R;
5006 %}
5007
5008 // Floating Point Convert I->L
5009 pipe_class fcvtI2L(regD dst, regF src) %{
5010 single_instruction;
5011 dst : X(write);
5012 src : E(read);
5013 FA : R;
5014 %}
5015
5016 // Floating Point Convert D->F
5017 pipe_class fcvtD2I(regF dst, regD src, flagsReg cr) %{
5018 instruction_count(1); multiple_bundles;
5019 dst : X(write)+6;
5020 src : E(read);
5021 FA : R;
5022 %}
5023
5024 // Floating Point Convert D->L
5025 pipe_class fcvtD2L(regD dst, regD src, flagsReg cr) %{
5026 instruction_count(1); multiple_bundles;
5027 dst : X(write)+6;
5028 src : E(read);
5029 FA : R;
5030 %}
5031
5032 // Floating Point Convert F->I
5033 pipe_class fcvtF2I(regF dst, regF src, flagsReg cr) %{
5034 instruction_count(1); multiple_bundles;
5035 dst : X(write)+6;
5036 src : E(read);
5037 FA : R;
5038 %}
5039
5040 // Floating Point Convert F->L
5041 pipe_class fcvtF2L(regD dst, regF src, flagsReg cr) %{
5042 instruction_count(1); multiple_bundles;
5043 dst : X(write)+6;
5044 src : E(read);
5045 FA : R;
5046 %}
5047
5048 // Floating Point Convert I->F
5049 pipe_class fcvtI2F(regF dst, regF src) %{
5050 single_instruction;
5051 dst : X(write);
5052 src : E(read);
5053 FA : R;
5054 %}
5055
5056 // Floating Point Compare
5057 pipe_class faddF_fcc_reg_reg_zero(flagsRegF cr, regF src1, regF src2, immI0 zero) %{
5058 single_instruction;
5059 cr : X(write);
5060 src1 : E(read);
5061 src2 : E(read);
5062 FA : R;
5063 %}
5064
5065 // Floating Point Compare
5066 pipe_class faddD_fcc_reg_reg_zero(flagsRegF cr, regD src1, regD src2, immI0 zero) %{
5067 single_instruction;
5068 cr : X(write);
5069 src1 : E(read);
5070 src2 : E(read);
5071 FA : R;
5072 %}
5073
5074 // Floating Add Nop
5075 pipe_class fadd_nop() %{
5076 single_instruction;
5077 FA : R;
5078 %}
5079
5080 // Integer Store to Memory
5081 pipe_class istore_mem_reg(memory mem, iRegI src) %{
5082 single_instruction;
5083 mem : R(read);
5084 src : C(read);
5085 MS : R;
5086 %}
5087
5088 // Integer Store to Memory
5089 pipe_class istore_mem_spORreg(memory mem, sp_ptr_RegP src) %{
5090 single_instruction;
5091 mem : R(read);
5092 src : C(read);
5093 MS : R;
5094 %}
5095
5096 // Integer Store Zero to Memory
5097 pipe_class istore_mem_zero(memory mem, immI0 src) %{
5098 single_instruction;
5099 mem : R(read);
5100 MS : R;
5101 %}
5102
5103 // Special Stack Slot Store
5104 pipe_class istore_stk_reg(stackSlotI stkSlot, iRegI src) %{
5105 single_instruction;
5106 stkSlot : R(read);
5107 src : C(read);
5108 MS : R;
5109 %}
5110
5111 // Special Stack Slot Store
5112 pipe_class lstoreI_stk_reg(stackSlotL stkSlot, iRegI src) %{
5113 instruction_count(2); multiple_bundles;
5114 stkSlot : R(read);
5115 src : C(read);
5116 MS : R(2);
5117 %}
5118
5119 // Float Store
5120 pipe_class fstoreF_mem_reg(memory mem, RegF src) %{
5121 single_instruction;
5122 mem : R(read);
5123 src : C(read);
5124 MS : R;
5125 %}
5126
5127 // Float Store
5128 pipe_class fstoreF_mem_zero(memory mem, immF0 src) %{
5129 single_instruction;
5130 mem : R(read);
5131 MS : R;
5132 %}
5133
5134 // Double Store
5135 pipe_class fstoreD_mem_reg(memory mem, RegD src) %{
5136 instruction_count(1);
5137 mem : R(read);
5138 src : C(read);
5139 MS : R;
5140 %}
5141
5142 // Double Store
5143 pipe_class fstoreD_mem_zero(memory mem, immD0 src) %{
5144 single_instruction;
5145 mem : R(read);
5146 MS : R;
5147 %}
5148
5149 // Special Stack Slot Float Store
5150 pipe_class fstoreF_stk_reg(stackSlotI stkSlot, RegF src) %{
5151 single_instruction;
5152 stkSlot : R(read);
5153 src : C(read);
5154 MS : R;
5155 %}
5156
5157 // Special Stack Slot Double Store
5158 pipe_class fstoreD_stk_reg(stackSlotI stkSlot, RegD src) %{
5159 single_instruction;
5160 stkSlot : R(read);
5161 src : C(read);
5162 MS : R;
5163 %}
5164
5165 // Integer Load (when sign bit propagation not needed)
5166 pipe_class iload_mem(iRegI dst, memory mem) %{
5167 single_instruction;
5168 mem : R(read);
5169 dst : C(write);
5170 MS : R;
5171 %}
5172
5173 // Integer Load from stack operand
5174 pipe_class iload_stkD(iRegI dst, stackSlotD mem ) %{
5175 single_instruction;
5176 mem : R(read);
5177 dst : C(write);
5178 MS : R;
5179 %}
5180
5181 // Integer Load (when sign bit propagation or masking is needed)
5182 pipe_class iload_mask_mem(iRegI dst, memory mem) %{
5183 single_instruction;
5184 mem : R(read);
5185 dst : M(write);
5186 MS : R;
5187 %}
5188
5189 // Float Load
5190 pipe_class floadF_mem(regF dst, memory mem) %{
5191 single_instruction;
5192 mem : R(read);
5193 dst : M(write);
5194 MS : R;
5195 %}
5196
5197 // Float Load
5198 pipe_class floadD_mem(regD dst, memory mem) %{
5199 instruction_count(1); multiple_bundles; // Again, unaligned argument is only multiple case
5200 mem : R(read);
5201 dst : M(write);
5202 MS : R;
5203 %}
5204
5205 // Float Load
5206 pipe_class floadF_stk(regF dst, stackSlotI stkSlot) %{
5207 single_instruction;
5208 stkSlot : R(read);
5209 dst : M(write);
5210 MS : R;
5211 %}
5212
5213 // Float Load
5214 pipe_class floadD_stk(regD dst, stackSlotI stkSlot) %{
5215 single_instruction;
5216 stkSlot : R(read);
5217 dst : M(write);
5218 MS : R;
5219 %}
5220
5221 // Memory Nop
5222 pipe_class mem_nop() %{
5223 single_instruction;
5224 MS : R;
5225 %}
5226
5227 pipe_class sethi(iRegP dst, immI src) %{
5228 single_instruction;
5229 dst : E(write);
5230 IALU : R;
5231 %}
5232
5233 pipe_class loadPollP(iRegP poll) %{
5234 single_instruction;
5235 poll : R(read);
5236 MS : R;
5237 %}
5238
5239 pipe_class br(Universe br, label labl) %{
5240 single_instruction_with_delay_slot;
5241 BR : R;
5242 %}
5243
5244 pipe_class br_cc(Universe br, cmpOp cmp, flagsReg cr, label labl) %{
5245 single_instruction_with_delay_slot;
5246 cr : E(read);
5247 BR : R;
5248 %}
5249
5250 pipe_class br_reg(Universe br, cmpOp cmp, iRegI op1, label labl) %{
5251 single_instruction_with_delay_slot;
5252 op1 : E(read);
5253 BR : R;
5254 MS : R;
5255 %}
5256
5257 // Compare and branch
5258 pipe_class cmp_br_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl, flagsReg cr) %{
5259 instruction_count(2); has_delay_slot;
5260 cr : E(write);
5261 src1 : R(read);
5262 src2 : R(read);
5263 IALU : R;
5264 BR : R;
5265 %}
5266
5267 // Compare and branch
5268 pipe_class cmp_br_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI13 src2, label labl, flagsReg cr) %{
5269 instruction_count(2); has_delay_slot;
5270 cr : E(write);
5271 src1 : R(read);
5272 IALU : R;
5273 BR : R;
5274 %}
5275
5276 // Compare and branch using cbcond
5277 pipe_class cbcond_reg_reg(Universe br, cmpOp cmp, iRegI src1, iRegI src2, label labl) %{
5278 single_instruction;
5279 src1 : E(read);
5280 src2 : E(read);
5281 IALU : R;
5282 BR : R;
5283 %}
5284
5285 // Compare and branch using cbcond
5286 pipe_class cbcond_reg_imm(Universe br, cmpOp cmp, iRegI src1, immI5 src2, label labl) %{
5287 single_instruction;
5288 src1 : E(read);
5289 IALU : R;
5290 BR : R;
5291 %}
5292
5293 pipe_class br_fcc(Universe br, cmpOpF cc, flagsReg cr, label labl) %{
5294 single_instruction_with_delay_slot;
5295 cr : E(read);
5296 BR : R;
5297 %}
5298
5299 pipe_class br_nop() %{
5300 single_instruction;
5301 BR : R;
5302 %}
5303
5304 pipe_class simple_call(method meth) %{
5305 instruction_count(2); multiple_bundles; force_serialization;
5306 fixed_latency(100);
5307 BR : R(1);
5308 MS : R(1);
5309 A0 : R(1);
5310 %}
5311
5312 pipe_class compiled_call(method meth) %{
5313 instruction_count(1); multiple_bundles; force_serialization;
5314 fixed_latency(100);
5315 MS : R(1);
5316 %}
5317
5318 pipe_class call(method meth) %{
5319 instruction_count(0); multiple_bundles; force_serialization;
5320 fixed_latency(100);
5321 %}
5322
5323 pipe_class tail_call(Universe ignore, label labl) %{
5324 single_instruction; has_delay_slot;
5325 fixed_latency(100);
5326 BR : R(1);
5327 MS : R(1);
5328 %}
5329
5330 pipe_class ret(Universe ignore) %{
5331 single_instruction; has_delay_slot;
5332 BR : R(1);
5333 MS : R(1);
5334 %}
5335
5336 pipe_class ret_poll(g3RegP poll) %{
5337 instruction_count(3); has_delay_slot;
5338 poll : E(read);
5339 MS : R;
5340 %}
5341
5342 // The real do-nothing guy
5343 pipe_class empty( ) %{
5344 instruction_count(0);
5345 %}
5346
5347 pipe_class long_memory_op() %{
5348 instruction_count(0); multiple_bundles; force_serialization;
5349 fixed_latency(25);
5350 MS : R(1);
5351 %}
5352
5353 // Check-cast
5354 pipe_class partial_subtype_check_pipe(Universe ignore, iRegP array, iRegP match ) %{
5355 array : R(read);
5356 match : R(read);
5357 IALU : R(2);
5358 BR : R(2);
5359 MS : R;
5360 %}
5361
5362 // Convert FPU flags into +1,0,-1
5363 pipe_class floating_cmp( iRegI dst, regF src1, regF src2 ) %{
5364 src1 : E(read);
5365 src2 : E(read);
5366 dst : E(write);
5367 FA : R;
5368 MS : R(2);
5369 BR : R(2);
5370 %}
5371
5372 // Compare for p < q, and conditionally add y
5373 pipe_class cadd_cmpltmask( iRegI p, iRegI q, iRegI y ) %{
5374 p : E(read);
5375 q : E(read);
5376 y : E(read);
5377 IALU : R(3)
5378 %}
5379
5380 // Perform a compare, then move conditionally in a branch delay slot.
5381 pipe_class min_max( iRegI src2, iRegI srcdst ) %{
5382 src2 : E(read);
5383 srcdst : E(read);
5384 IALU : R;
5385 BR : R;
5386 %}
5387
5388 // Define the class for the Nop node
5389 define %{
5390 MachNop = ialu_nop;
5391 %}
5392
5393 %}
5394
5395 //----------INSTRUCTIONS-------------------------------------------------------
5396
5397 //------------Special Stack Slot instructions - no match rules-----------------
5398 instruct stkI_to_regF(regF dst, stackSlotI src) %{
5399 // No match rule to avoid chain rule match.
5400 effect(DEF dst, USE src);
5401 ins_cost(MEMORY_REF_COST);
5402 size(4);
5403 format %{ "LDF $src,$dst\t! stkI to regF" %}
5404 opcode(Assembler::ldf_op3);
5405 ins_encode(simple_form3_mem_reg(src, dst));
5406 ins_pipe(floadF_stk);
5407 %}
5408
5409 instruct stkL_to_regD(regD dst, stackSlotL src) %{
5410 // No match rule to avoid chain rule match.
5411 effect(DEF dst, USE src);
5412 ins_cost(MEMORY_REF_COST);
5413 size(4);
5414 format %{ "LDDF $src,$dst\t! stkL to regD" %}
5415 opcode(Assembler::lddf_op3);
5416 ins_encode(simple_form3_mem_reg(src, dst));
5417 ins_pipe(floadD_stk);
5418 %}
5419
5420 instruct regF_to_stkI(stackSlotI dst, regF src) %{
5421 // No match rule to avoid chain rule match.
5422 effect(DEF dst, USE src);
5423 ins_cost(MEMORY_REF_COST);
5424 size(4);
5425 format %{ "STF $src,$dst\t! regF to stkI" %}
5426 opcode(Assembler::stf_op3);
5427 ins_encode(simple_form3_mem_reg(dst, src));
5428 ins_pipe(fstoreF_stk_reg);
5429 %}
5430
5431 instruct regD_to_stkL(stackSlotL dst, regD src) %{
5432 // No match rule to avoid chain rule match.
5433 effect(DEF dst, USE src);
5434 ins_cost(MEMORY_REF_COST);
5435 size(4);
5436 format %{ "STDF $src,$dst\t! regD to stkL" %}
5437 opcode(Assembler::stdf_op3);
5438 ins_encode(simple_form3_mem_reg(dst, src));
5439 ins_pipe(fstoreD_stk_reg);
5440 %}
5441
5442 instruct regI_to_stkLHi(stackSlotL dst, iRegI src) %{
5443 effect(DEF dst, USE src);
5444 ins_cost(MEMORY_REF_COST*2);
5445 size(8);
5446 format %{ "STW $src,$dst.hi\t! long\n\t"
5447 "STW R_G0,$dst.lo" %}
5448 opcode(Assembler::stw_op3);
5449 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, R_G0));
5450 ins_pipe(lstoreI_stk_reg);
5451 %}
5452
5453 instruct regL_to_stkD(stackSlotD dst, iRegL src) %{
5454 // No match rule to avoid chain rule match.
5455 effect(DEF dst, USE src);
5456 ins_cost(MEMORY_REF_COST);
5457 size(4);
5458 format %{ "STX $src,$dst\t! regL to stkD" %}
5459 opcode(Assembler::stx_op3);
5460 ins_encode(simple_form3_mem_reg( dst, src ) );
5461 ins_pipe(istore_stk_reg);
5462 %}
5463
5464 //---------- Chain stack slots between similar types --------
5465
5466 // Load integer from stack slot
5467 instruct stkI_to_regI( iRegI dst, stackSlotI src ) %{
5468 match(Set dst src);
5469 ins_cost(MEMORY_REF_COST);
5470
5471 size(4);
5472 format %{ "LDUW $src,$dst\t!stk" %}
5473 opcode(Assembler::lduw_op3);
5474 ins_encode(simple_form3_mem_reg( src, dst ) );
5475 ins_pipe(iload_mem);
5476 %}
5477
5478 // Store integer to stack slot
5479 instruct regI_to_stkI( stackSlotI dst, iRegI src ) %{
5480 match(Set dst src);
5481 ins_cost(MEMORY_REF_COST);
5482
5483 size(4);
5484 format %{ "STW $src,$dst\t!stk" %}
5485 opcode(Assembler::stw_op3);
5486 ins_encode(simple_form3_mem_reg( dst, src ) );
5487 ins_pipe(istore_mem_reg);
5488 %}
5489
5490 // Load long from stack slot
5491 instruct stkL_to_regL( iRegL dst, stackSlotL src ) %{
5492 match(Set dst src);
5493
5494 ins_cost(MEMORY_REF_COST);
5495 size(4);
5496 format %{ "LDX $src,$dst\t! long" %}
5497 opcode(Assembler::ldx_op3);
5498 ins_encode(simple_form3_mem_reg( src, dst ) );
5499 ins_pipe(iload_mem);
5500 %}
5501
5502 // Store long to stack slot
5503 instruct regL_to_stkL(stackSlotL dst, iRegL src) %{
5504 match(Set dst src);
5505
5506 ins_cost(MEMORY_REF_COST);
5507 size(4);
5508 format %{ "STX $src,$dst\t! long" %}
5509 opcode(Assembler::stx_op3);
5510 ins_encode(simple_form3_mem_reg( dst, src ) );
5511 ins_pipe(istore_mem_reg);
5512 %}
5513
5514 #ifdef _LP64
5515 // Load pointer from stack slot, 64-bit encoding
5516 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5517 match(Set dst src);
5518 ins_cost(MEMORY_REF_COST);
5519 size(4);
5520 format %{ "LDX $src,$dst\t!ptr" %}
5521 opcode(Assembler::ldx_op3);
5522 ins_encode(simple_form3_mem_reg( src, dst ) );
5523 ins_pipe(iload_mem);
5524 %}
5525
5526 // Store pointer to stack slot
5527 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5528 match(Set dst src);
5529 ins_cost(MEMORY_REF_COST);
5530 size(4);
5531 format %{ "STX $src,$dst\t!ptr" %}
5532 opcode(Assembler::stx_op3);
5533 ins_encode(simple_form3_mem_reg( dst, src ) );
5534 ins_pipe(istore_mem_reg);
5535 %}
5536 #else // _LP64
5537 // Load pointer from stack slot, 32-bit encoding
5538 instruct stkP_to_regP( iRegP dst, stackSlotP src ) %{
5539 match(Set dst src);
5540 ins_cost(MEMORY_REF_COST);
5541 format %{ "LDUW $src,$dst\t!ptr" %}
5542 opcode(Assembler::lduw_op3, Assembler::ldst_op);
5543 ins_encode(simple_form3_mem_reg( src, dst ) );
5544 ins_pipe(iload_mem);
5545 %}
5546
5547 // Store pointer to stack slot
5548 instruct regP_to_stkP(stackSlotP dst, iRegP src) %{
5549 match(Set dst src);
5550 ins_cost(MEMORY_REF_COST);
5551 format %{ "STW $src,$dst\t!ptr" %}
5552 opcode(Assembler::stw_op3, Assembler::ldst_op);
5553 ins_encode(simple_form3_mem_reg( dst, src ) );
5554 ins_pipe(istore_mem_reg);
5555 %}
5556 #endif // _LP64
5557
5558 //------------Special Nop instructions for bundling - no match rules-----------
5559 // Nop using the A0 functional unit
5560 instruct Nop_A0() %{
5561 ins_cost(0);
5562
5563 format %{ "NOP ! Alu Pipeline" %}
5564 opcode(Assembler::or_op3, Assembler::arith_op);
5565 ins_encode( form2_nop() );
5566 ins_pipe(ialu_nop_A0);
5567 %}
5568
5569 // Nop using the A1 functional unit
5570 instruct Nop_A1( ) %{
5571 ins_cost(0);
5572
5573 format %{ "NOP ! Alu Pipeline" %}
5574 opcode(Assembler::or_op3, Assembler::arith_op);
5575 ins_encode( form2_nop() );
5576 ins_pipe(ialu_nop_A1);
5577 %}
5578
5579 // Nop using the memory functional unit
5580 instruct Nop_MS( ) %{
5581 ins_cost(0);
5582
5583 format %{ "NOP ! Memory Pipeline" %}
5584 ins_encode( emit_mem_nop );
5585 ins_pipe(mem_nop);
5586 %}
5587
5588 // Nop using the floating add functional unit
5589 instruct Nop_FA( ) %{
5590 ins_cost(0);
5591
5592 format %{ "NOP ! Floating Add Pipeline" %}
5593 ins_encode( emit_fadd_nop );
5594 ins_pipe(fadd_nop);
5595 %}
5596
5597 // Nop using the branch functional unit
5598 instruct Nop_BR( ) %{
5599 ins_cost(0);
5600
5601 format %{ "NOP ! Branch Pipeline" %}
5602 ins_encode( emit_br_nop );
5603 ins_pipe(br_nop);
5604 %}
5605
5606 //----------Load/Store/Move Instructions---------------------------------------
5607 //----------Load Instructions--------------------------------------------------
5608 // Load Byte (8bit signed)
5609 instruct loadB(iRegI dst, memory mem) %{
5610 match(Set dst (LoadB mem));
5611 ins_cost(MEMORY_REF_COST);
5612
5613 size(4);
5614 format %{ "LDSB $mem,$dst\t! byte" %}
5615 ins_encode %{
5616 __ ldsb($mem$$Address, $dst$$Register);
5617 %}
5618 ins_pipe(iload_mask_mem);
5619 %}
5620
5621 // Load Byte (8bit signed) into a Long Register
5622 instruct loadB2L(iRegL dst, memory mem) %{
5623 match(Set dst (ConvI2L (LoadB mem)));
5624 ins_cost(MEMORY_REF_COST);
5625
5626 size(4);
5627 format %{ "LDSB $mem,$dst\t! byte -> long" %}
5628 ins_encode %{
5629 __ ldsb($mem$$Address, $dst$$Register);
5630 %}
5631 ins_pipe(iload_mask_mem);
5632 %}
5633
5634 // Load Unsigned Byte (8bit UNsigned) into an int reg
5635 instruct loadUB(iRegI dst, memory mem) %{
5636 match(Set dst (LoadUB mem));
5637 ins_cost(MEMORY_REF_COST);
5638
5639 size(4);
5640 format %{ "LDUB $mem,$dst\t! ubyte" %}
5641 ins_encode %{
5642 __ ldub($mem$$Address, $dst$$Register);
5643 %}
5644 ins_pipe(iload_mem);
5645 %}
5646
5647 // Load Unsigned Byte (8bit UNsigned) into a Long Register
5648 instruct loadUB2L(iRegL dst, memory mem) %{
5649 match(Set dst (ConvI2L (LoadUB mem)));
5650 ins_cost(MEMORY_REF_COST);
5651
5652 size(4);
5653 format %{ "LDUB $mem,$dst\t! ubyte -> long" %}
5654 ins_encode %{
5655 __ ldub($mem$$Address, $dst$$Register);
5656 %}
5657 ins_pipe(iload_mem);
5658 %}
5659
5660 // Load Unsigned Byte (8 bit UNsigned) with 8-bit mask into Long Register
5661 instruct loadUB2L_immI8(iRegL dst, memory mem, immI8 mask) %{
5662 match(Set dst (ConvI2L (AndI (LoadUB mem) mask)));
5663 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5664
5665 size(2*4);
5666 format %{ "LDUB $mem,$dst\t# ubyte & 8-bit mask -> long\n\t"
5667 "AND $dst,$mask,$dst" %}
5668 ins_encode %{
5669 __ ldub($mem$$Address, $dst$$Register);
5670 __ and3($dst$$Register, $mask$$constant, $dst$$Register);
5671 %}
5672 ins_pipe(iload_mem);
5673 %}
5674
5675 // Load Short (16bit signed)
5676 instruct loadS(iRegI dst, memory mem) %{
5677 match(Set dst (LoadS mem));
5678 ins_cost(MEMORY_REF_COST);
5679
5680 size(4);
5681 format %{ "LDSH $mem,$dst\t! short" %}
5682 ins_encode %{
5683 __ ldsh($mem$$Address, $dst$$Register);
5684 %}
5685 ins_pipe(iload_mask_mem);
5686 %}
5687
5688 // Load Short (16 bit signed) to Byte (8 bit signed)
5689 instruct loadS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5690 match(Set dst (RShiftI (LShiftI (LoadS mem) twentyfour) twentyfour));
5691 ins_cost(MEMORY_REF_COST);
5692
5693 size(4);
5694
5695 format %{ "LDSB $mem+1,$dst\t! short -> byte" %}
5696 ins_encode %{
5697 __ ldsb($mem$$Address, $dst$$Register, 1);
5698 %}
5699 ins_pipe(iload_mask_mem);
5700 %}
5701
5702 // Load Short (16bit signed) into a Long Register
5703 instruct loadS2L(iRegL dst, memory mem) %{
5704 match(Set dst (ConvI2L (LoadS mem)));
5705 ins_cost(MEMORY_REF_COST);
5706
5707 size(4);
5708 format %{ "LDSH $mem,$dst\t! short -> long" %}
5709 ins_encode %{
5710 __ ldsh($mem$$Address, $dst$$Register);
5711 %}
5712 ins_pipe(iload_mask_mem);
5713 %}
5714
5715 // Load Unsigned Short/Char (16bit UNsigned)
5716 instruct loadUS(iRegI dst, memory mem) %{
5717 match(Set dst (LoadUS mem));
5718 ins_cost(MEMORY_REF_COST);
5719
5720 size(4);
5721 format %{ "LDUH $mem,$dst\t! ushort/char" %}
5722 ins_encode %{
5723 __ lduh($mem$$Address, $dst$$Register);
5724 %}
5725 ins_pipe(iload_mem);
5726 %}
5727
5728 // Load Unsigned Short/Char (16 bit UNsigned) to Byte (8 bit signed)
5729 instruct loadUS2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5730 match(Set dst (RShiftI (LShiftI (LoadUS mem) twentyfour) twentyfour));
5731 ins_cost(MEMORY_REF_COST);
5732
5733 size(4);
5734 format %{ "LDSB $mem+1,$dst\t! ushort -> byte" %}
5735 ins_encode %{
5736 __ ldsb($mem$$Address, $dst$$Register, 1);
5737 %}
5738 ins_pipe(iload_mask_mem);
5739 %}
5740
5741 // Load Unsigned Short/Char (16bit UNsigned) into a Long Register
5742 instruct loadUS2L(iRegL dst, memory mem) %{
5743 match(Set dst (ConvI2L (LoadUS mem)));
5744 ins_cost(MEMORY_REF_COST);
5745
5746 size(4);
5747 format %{ "LDUH $mem,$dst\t! ushort/char -> long" %}
5748 ins_encode %{
5749 __ lduh($mem$$Address, $dst$$Register);
5750 %}
5751 ins_pipe(iload_mem);
5752 %}
5753
5754 // Load Unsigned Short/Char (16bit UNsigned) with mask 0xFF into a Long Register
5755 instruct loadUS2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5756 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5757 ins_cost(MEMORY_REF_COST);
5758
5759 size(4);
5760 format %{ "LDUB $mem+1,$dst\t! ushort/char & 0xFF -> long" %}
5761 ins_encode %{
5762 __ ldub($mem$$Address, $dst$$Register, 1); // LSB is index+1 on BE
5763 %}
5764 ins_pipe(iload_mem);
5765 %}
5766
5767 // Load Unsigned Short/Char (16bit UNsigned) with a 13-bit mask into a Long Register
5768 instruct loadUS2L_immI13(iRegL dst, memory mem, immI13 mask) %{
5769 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5770 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5771
5772 size(2*4);
5773 format %{ "LDUH $mem,$dst\t! ushort/char & 13-bit mask -> long\n\t"
5774 "AND $dst,$mask,$dst" %}
5775 ins_encode %{
5776 Register Rdst = $dst$$Register;
5777 __ lduh($mem$$Address, Rdst);
5778 __ and3(Rdst, $mask$$constant, Rdst);
5779 %}
5780 ins_pipe(iload_mem);
5781 %}
5782
5783 // Load Unsigned Short/Char (16bit UNsigned) with a 16-bit mask into a Long Register
5784 instruct loadUS2L_immI16(iRegL dst, memory mem, immI16 mask, iRegL tmp) %{
5785 match(Set dst (ConvI2L (AndI (LoadUS mem) mask)));
5786 effect(TEMP dst, TEMP tmp);
5787 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5788
5789 format %{ "LDUH $mem,$dst\t! ushort/char & 16-bit mask -> long\n\t"
5790 "SET $mask,$tmp\n\t"
5791 "AND $dst,$tmp,$dst" %}
5792 ins_encode %{
5793 Register Rdst = $dst$$Register;
5794 Register Rtmp = $tmp$$Register;
5795 __ lduh($mem$$Address, Rdst);
5796 __ set($mask$$constant, Rtmp);
5797 __ and3(Rdst, Rtmp, Rdst);
5798 %}
5799 ins_pipe(iload_mem);
5800 %}
5801
5802 // Load Integer
5803 instruct loadI(iRegI dst, memory mem) %{
5804 match(Set dst (LoadI mem));
5805 ins_cost(MEMORY_REF_COST);
5806
5807 size(4);
5808 format %{ "LDUW $mem,$dst\t! int" %}
5809 ins_encode %{
5810 __ lduw($mem$$Address, $dst$$Register);
5811 %}
5812 ins_pipe(iload_mem);
5813 %}
5814
5815 // Load Integer to Byte (8 bit signed)
5816 instruct loadI2B(iRegI dst, indOffset13m7 mem, immI_24 twentyfour) %{
5817 match(Set dst (RShiftI (LShiftI (LoadI mem) twentyfour) twentyfour));
5818 ins_cost(MEMORY_REF_COST);
5819
5820 size(4);
5821
5822 format %{ "LDSB $mem+3,$dst\t! int -> byte" %}
5823 ins_encode %{
5824 __ ldsb($mem$$Address, $dst$$Register, 3);
5825 %}
5826 ins_pipe(iload_mask_mem);
5827 %}
5828
5829 // Load Integer to Unsigned Byte (8 bit UNsigned)
5830 instruct loadI2UB(iRegI dst, indOffset13m7 mem, immI_255 mask) %{
5831 match(Set dst (AndI (LoadI mem) mask));
5832 ins_cost(MEMORY_REF_COST);
5833
5834 size(4);
5835
5836 format %{ "LDUB $mem+3,$dst\t! int -> ubyte" %}
5837 ins_encode %{
5838 __ ldub($mem$$Address, $dst$$Register, 3);
5839 %}
5840 ins_pipe(iload_mask_mem);
5841 %}
5842
5843 // Load Integer to Short (16 bit signed)
5844 instruct loadI2S(iRegI dst, indOffset13m7 mem, immI_16 sixteen) %{
5845 match(Set dst (RShiftI (LShiftI (LoadI mem) sixteen) sixteen));
5846 ins_cost(MEMORY_REF_COST);
5847
5848 size(4);
5849
5850 format %{ "LDSH $mem+2,$dst\t! int -> short" %}
5851 ins_encode %{
5852 __ ldsh($mem$$Address, $dst$$Register, 2);
5853 %}
5854 ins_pipe(iload_mask_mem);
5855 %}
5856
5857 // Load Integer to Unsigned Short (16 bit UNsigned)
5858 instruct loadI2US(iRegI dst, indOffset13m7 mem, immI_65535 mask) %{
5859 match(Set dst (AndI (LoadI mem) mask));
5860 ins_cost(MEMORY_REF_COST);
5861
5862 size(4);
5863
5864 format %{ "LDUH $mem+2,$dst\t! int -> ushort/char" %}
5865 ins_encode %{
5866 __ lduh($mem$$Address, $dst$$Register, 2);
5867 %}
5868 ins_pipe(iload_mask_mem);
5869 %}
5870
5871 // Load Integer into a Long Register
5872 instruct loadI2L(iRegL dst, memory mem) %{
5873 match(Set dst (ConvI2L (LoadI mem)));
5874 ins_cost(MEMORY_REF_COST);
5875
5876 size(4);
5877 format %{ "LDSW $mem,$dst\t! int -> long" %}
5878 ins_encode %{
5879 __ ldsw($mem$$Address, $dst$$Register);
5880 %}
5881 ins_pipe(iload_mask_mem);
5882 %}
5883
5884 // Load Integer with mask 0xFF into a Long Register
5885 instruct loadI2L_immI_255(iRegL dst, indOffset13m7 mem, immI_255 mask) %{
5886 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5887 ins_cost(MEMORY_REF_COST);
5888
5889 size(4);
5890 format %{ "LDUB $mem+3,$dst\t! int & 0xFF -> long" %}
5891 ins_encode %{
5892 __ ldub($mem$$Address, $dst$$Register, 3); // LSB is index+3 on BE
5893 %}
5894 ins_pipe(iload_mem);
5895 %}
5896
5897 // Load Integer with mask 0xFFFF into a Long Register
5898 instruct loadI2L_immI_65535(iRegL dst, indOffset13m7 mem, immI_65535 mask) %{
5899 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5900 ins_cost(MEMORY_REF_COST);
5901
5902 size(4);
5903 format %{ "LDUH $mem+2,$dst\t! int & 0xFFFF -> long" %}
5904 ins_encode %{
5905 __ lduh($mem$$Address, $dst$$Register, 2); // LSW is index+2 on BE
5906 %}
5907 ins_pipe(iload_mem);
5908 %}
5909
5910 // Load Integer with a 12-bit mask into a Long Register
5911 instruct loadI2L_immU12(iRegL dst, memory mem, immU12 mask) %{
5912 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5913 ins_cost(MEMORY_REF_COST + DEFAULT_COST);
5914
5915 size(2*4);
5916 format %{ "LDUW $mem,$dst\t! int & 12-bit mask -> long\n\t"
5917 "AND $dst,$mask,$dst" %}
5918 ins_encode %{
5919 Register Rdst = $dst$$Register;
5920 __ lduw($mem$$Address, Rdst);
5921 __ and3(Rdst, $mask$$constant, Rdst);
5922 %}
5923 ins_pipe(iload_mem);
5924 %}
5925
5926 // Load Integer with a 31-bit mask into a Long Register
5927 instruct loadI2L_immU31(iRegL dst, memory mem, immU31 mask, iRegL tmp) %{
5928 match(Set dst (ConvI2L (AndI (LoadI mem) mask)));
5929 effect(TEMP dst, TEMP tmp);
5930 ins_cost(MEMORY_REF_COST + 2*DEFAULT_COST);
5931
5932 format %{ "LDUW $mem,$dst\t! int & 31-bit mask -> long\n\t"
5933 "SET $mask,$tmp\n\t"
5934 "AND $dst,$tmp,$dst" %}
5935 ins_encode %{
5936 Register Rdst = $dst$$Register;
5937 Register Rtmp = $tmp$$Register;
5938 __ lduw($mem$$Address, Rdst);
5939 __ set($mask$$constant, Rtmp);
5940 __ and3(Rdst, Rtmp, Rdst);
5941 %}
5942 ins_pipe(iload_mem);
5943 %}
5944
5945 // Load Unsigned Integer into a Long Register
5946 instruct loadUI2L(iRegL dst, memory mem, immL_32bits mask) %{
5947 match(Set dst (AndL (ConvI2L (LoadI mem)) mask));
5948 ins_cost(MEMORY_REF_COST);
5949
5950 size(4);
5951 format %{ "LDUW $mem,$dst\t! uint -> long" %}
5952 ins_encode %{
5953 __ lduw($mem$$Address, $dst$$Register);
5954 %}
5955 ins_pipe(iload_mem);
5956 %}
5957
5958 // Load Long - aligned
5959 instruct loadL(iRegL dst, memory mem ) %{
5960 match(Set dst (LoadL mem));
5961 ins_cost(MEMORY_REF_COST);
5962
5963 size(4);
5964 format %{ "LDX $mem,$dst\t! long" %}
5965 ins_encode %{
5966 __ ldx($mem$$Address, $dst$$Register);
5967 %}
5968 ins_pipe(iload_mem);
5969 %}
5970
5971 // Load Long - UNaligned
5972 instruct loadL_unaligned(iRegL dst, memory mem, o7RegI tmp) %{
5973 match(Set dst (LoadL_unaligned mem));
5974 effect(KILL tmp);
5975 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
5976 size(16);
5977 format %{ "LDUW $mem+4,R_O7\t! misaligned long\n"
5978 "\tLDUW $mem ,$dst\n"
5979 "\tSLLX #32, $dst, $dst\n"
5980 "\tOR $dst, R_O7, $dst" %}
5981 opcode(Assembler::lduw_op3);
5982 ins_encode(form3_mem_reg_long_unaligned_marshal( mem, dst ));
5983 ins_pipe(iload_mem);
5984 %}
5985
5986 // Load Range
5987 instruct loadRange(iRegI dst, memory mem) %{
5988 match(Set dst (LoadRange mem));
5989 ins_cost(MEMORY_REF_COST);
5990
5991 size(4);
5992 format %{ "LDUW $mem,$dst\t! range" %}
5993 opcode(Assembler::lduw_op3);
5994 ins_encode(simple_form3_mem_reg( mem, dst ) );
5995 ins_pipe(iload_mem);
5996 %}
5997
5998 // Load Integer into %f register (for fitos/fitod)
5999 instruct loadI_freg(regF dst, memory mem) %{
6000 match(Set dst (LoadI mem));
6001 ins_cost(MEMORY_REF_COST);
6002 size(4);
6003
6004 format %{ "LDF $mem,$dst\t! for fitos/fitod" %}
6005 opcode(Assembler::ldf_op3);
6006 ins_encode(simple_form3_mem_reg( mem, dst ) );
6007 ins_pipe(floadF_mem);
6008 %}
6009
6010 // Load Pointer
6011 instruct loadP(iRegP dst, memory mem) %{
6012 match(Set dst (LoadP mem));
6013 ins_cost(MEMORY_REF_COST);
6014 size(4);
6015
6016 #ifndef _LP64
6017 format %{ "LDUW $mem,$dst\t! ptr" %}
6018 ins_encode %{
6019 __ lduw($mem$$Address, $dst$$Register);
6020 %}
6021 #else
6022 format %{ "LDX $mem,$dst\t! ptr" %}
6023 ins_encode %{
6024 __ ldx($mem$$Address, $dst$$Register);
6025 %}
6026 #endif
6027 ins_pipe(iload_mem);
6028 %}
6029
6030 // Load Compressed Pointer
6031 instruct loadN(iRegN dst, memory mem) %{
6032 match(Set dst (LoadN mem));
6033 ins_cost(MEMORY_REF_COST);
6034 size(4);
6035
6036 format %{ "LDUW $mem,$dst\t! compressed ptr" %}
6037 ins_encode %{
6038 __ lduw($mem$$Address, $dst$$Register);
6039 %}
6040 ins_pipe(iload_mem);
6041 %}
6042
6043 // Load Klass Pointer
6044 instruct loadKlass(iRegP dst, memory mem) %{
6045 match(Set dst (LoadKlass mem));
6046 ins_cost(MEMORY_REF_COST);
6047 size(4);
6048
6049 #ifndef _LP64
6050 format %{ "LDUW $mem,$dst\t! klass ptr" %}
6051 ins_encode %{
6052 __ lduw($mem$$Address, $dst$$Register);
6053 %}
6054 #else
6055 format %{ "LDX $mem,$dst\t! klass ptr" %}
6056 ins_encode %{
6057 __ ldx($mem$$Address, $dst$$Register);
6058 %}
6059 #endif
6060 ins_pipe(iload_mem);
6061 %}
6062
6063 // Load narrow Klass Pointer
6064 instruct loadNKlass(iRegN dst, memory mem) %{
6065 match(Set dst (LoadNKlass mem));
6066 ins_cost(MEMORY_REF_COST);
6067 size(4);
6068
6069 format %{ "LDUW $mem,$dst\t! compressed klass ptr" %}
6070 ins_encode %{
6071 __ lduw($mem$$Address, $dst$$Register);
6072 %}
6073 ins_pipe(iload_mem);
6074 %}
6075
6076 // Load Double
6077 instruct loadD(regD dst, memory mem) %{
6078 match(Set dst (LoadD mem));
6079 ins_cost(MEMORY_REF_COST);
6080
6081 size(4);
6082 format %{ "LDDF $mem,$dst" %}
6083 opcode(Assembler::lddf_op3);
6084 ins_encode(simple_form3_mem_reg( mem, dst ) );
6085 ins_pipe(floadD_mem);
6086 %}
6087
6088 // Load Double - UNaligned
6089 instruct loadD_unaligned(regD_low dst, memory mem ) %{
6090 match(Set dst (LoadD_unaligned mem));
6091 ins_cost(MEMORY_REF_COST*2+DEFAULT_COST);
6092 size(8);
6093 format %{ "LDF $mem ,$dst.hi\t! misaligned double\n"
6094 "\tLDF $mem+4,$dst.lo\t!" %}
6095 opcode(Assembler::ldf_op3);
6096 ins_encode( form3_mem_reg_double_unaligned( mem, dst ));
6097 ins_pipe(iload_mem);
6098 %}
6099
6100 // Load Float
6101 instruct loadF(regF dst, memory mem) %{
6102 match(Set dst (LoadF mem));
6103 ins_cost(MEMORY_REF_COST);
6104
6105 size(4);
6106 format %{ "LDF $mem,$dst" %}
6107 opcode(Assembler::ldf_op3);
6108 ins_encode(simple_form3_mem_reg( mem, dst ) );
6109 ins_pipe(floadF_mem);
6110 %}
6111
6112 // Load Constant
6113 instruct loadConI( iRegI dst, immI src ) %{
6114 match(Set dst src);
6115 ins_cost(DEFAULT_COST * 3/2);
6116 format %{ "SET $src,$dst" %}
6117 ins_encode( Set32(src, dst) );
6118 ins_pipe(ialu_hi_lo_reg);
6119 %}
6120
6121 instruct loadConI13( iRegI dst, immI13 src ) %{
6122 match(Set dst src);
6123
6124 size(4);
6125 format %{ "MOV $src,$dst" %}
6126 ins_encode( Set13( src, dst ) );
6127 ins_pipe(ialu_imm);
6128 %}
6129
6130 #ifndef _LP64
6131 instruct loadConP(iRegP dst, immP con) %{
6132 match(Set dst con);
6133 ins_cost(DEFAULT_COST * 3/2);
6134 format %{ "SET $con,$dst\t!ptr" %}
6135 ins_encode %{
6136 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6137 intptr_t val = $con$$constant;
6138 if (constant_reloc == relocInfo::oop_type) {
6139 __ set_oop_constant((jobject) val, $dst$$Register);
6140 } else if (constant_reloc == relocInfo::metadata_type) {
6141 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6142 } else { // non-oop pointers, e.g. card mark base, heap top
6143 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6144 __ set(val, $dst$$Register);
6145 }
6146 %}
6147 ins_pipe(loadConP);
6148 %}
6149 #else
6150 instruct loadConP_set(iRegP dst, immP_set con) %{
6151 match(Set dst con);
6152 ins_cost(DEFAULT_COST * 3/2);
6153 format %{ "SET $con,$dst\t! ptr" %}
6154 ins_encode %{
6155 relocInfo::relocType constant_reloc = _opnds[1]->constant_reloc();
6156 intptr_t val = $con$$constant;
6157 if (constant_reloc == relocInfo::oop_type) {
6158 __ set_oop_constant((jobject) val, $dst$$Register);
6159 } else if (constant_reloc == relocInfo::metadata_type) {
6160 __ set_metadata_constant((Metadata*)val, $dst$$Register);
6161 } else { // non-oop pointers, e.g. card mark base, heap top
6162 assert(constant_reloc == relocInfo::none, "unexpected reloc type");
6163 __ set(val, $dst$$Register);
6164 }
6165 %}
6166 ins_pipe(loadConP);
6167 %}
6168
6169 instruct loadConP_load(iRegP dst, immP_load con) %{
6170 match(Set dst con);
6171 ins_cost(MEMORY_REF_COST);
6172 format %{ "LD [$constanttablebase + $constantoffset],$dst\t! load from constant table: ptr=$con" %}
6173 ins_encode %{
6174 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6175 __ ld_ptr($constanttablebase, con_offset, $dst$$Register);
6176 %}
6177 ins_pipe(loadConP);
6178 %}
6179
6180 instruct loadConP_no_oop_cheap(iRegP dst, immP_no_oop_cheap con) %{
6181 match(Set dst con);
6182 ins_cost(DEFAULT_COST * 3/2);
6183 format %{ "SET $con,$dst\t! non-oop ptr" %}
6184 ins_encode %{
6185 if (_opnds[1]->constant_reloc() == relocInfo::metadata_type) {
6186 __ set_metadata_constant((Metadata*)$con$$constant, $dst$$Register);
6187 } else {
6188 __ set($con$$constant, $dst$$Register);
6189 }
6190 %}
6191 ins_pipe(loadConP);
6192 %}
6193 #endif // _LP64
6194
6195 instruct loadConP0(iRegP dst, immP0 src) %{
6196 match(Set dst src);
6197
6198 size(4);
6199 format %{ "CLR $dst\t!ptr" %}
6200 ins_encode %{
6201 __ clr($dst$$Register);
6202 %}
6203 ins_pipe(ialu_imm);
6204 %}
6205
6206 instruct loadConP_poll(iRegP dst, immP_poll src) %{
6207 match(Set dst src);
6208 ins_cost(DEFAULT_COST);
6209 format %{ "SET $src,$dst\t!ptr" %}
6210 ins_encode %{
6211 AddressLiteral polling_page(os::get_polling_page());
6212 __ sethi(polling_page, reg_to_register_object($dst$$reg));
6213 %}
6214 ins_pipe(loadConP_poll);
6215 %}
6216
6217 instruct loadConN0(iRegN dst, immN0 src) %{
6218 match(Set dst src);
6219
6220 size(4);
6221 format %{ "CLR $dst\t! compressed NULL ptr" %}
6222 ins_encode %{
6223 __ clr($dst$$Register);
6224 %}
6225 ins_pipe(ialu_imm);
6226 %}
6227
6228 instruct loadConN(iRegN dst, immN src) %{
6229 match(Set dst src);
6230 ins_cost(DEFAULT_COST * 3/2);
6231 format %{ "SET $src,$dst\t! compressed ptr" %}
6232 ins_encode %{
6233 Register dst = $dst$$Register;
6234 __ set_narrow_oop((jobject)$src$$constant, dst);
6235 %}
6236 ins_pipe(ialu_hi_lo_reg);
6237 %}
6238
6239 instruct loadConNKlass(iRegN dst, immNKlass src) %{
6240 match(Set dst src);
6241 ins_cost(DEFAULT_COST * 3/2);
6242 format %{ "SET $src,$dst\t! compressed klass ptr" %}
6243 ins_encode %{
6244 Register dst = $dst$$Register;
6245 __ set_narrow_klass((Klass*)$src$$constant, dst);
6246 %}
6247 ins_pipe(ialu_hi_lo_reg);
6248 %}
6249
6250 // Materialize long value (predicated by immL_cheap).
6251 instruct loadConL_set64(iRegL dst, immL_cheap con, o7RegL tmp) %{
6252 match(Set dst con);
6253 effect(KILL tmp);
6254 ins_cost(DEFAULT_COST * 3);
6255 format %{ "SET64 $con,$dst KILL $tmp\t! cheap long" %}
6256 ins_encode %{
6257 __ set64($con$$constant, $dst$$Register, $tmp$$Register);
6258 %}
6259 ins_pipe(loadConL);
6260 %}
6261
6262 // Load long value from constant table (predicated by immL_expensive).
6263 instruct loadConL_ldx(iRegL dst, immL_expensive con) %{
6264 match(Set dst con);
6265 ins_cost(MEMORY_REF_COST);
6266 format %{ "LDX [$constanttablebase + $constantoffset],$dst\t! load from constant table: long=$con" %}
6267 ins_encode %{
6268 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $dst$$Register);
6269 __ ldx($constanttablebase, con_offset, $dst$$Register);
6270 %}
6271 ins_pipe(loadConL);
6272 %}
6273
6274 instruct loadConL0( iRegL dst, immL0 src ) %{
6275 match(Set dst src);
6276 ins_cost(DEFAULT_COST);
6277 size(4);
6278 format %{ "CLR $dst\t! long" %}
6279 ins_encode( Set13( src, dst ) );
6280 ins_pipe(ialu_imm);
6281 %}
6282
6283 instruct loadConL13( iRegL dst, immL13 src ) %{
6284 match(Set dst src);
6285 ins_cost(DEFAULT_COST * 2);
6286
6287 size(4);
6288 format %{ "MOV $src,$dst\t! long" %}
6289 ins_encode( Set13( src, dst ) );
6290 ins_pipe(ialu_imm);
6291 %}
6292
6293 instruct loadConF(regF dst, immF con, o7RegI tmp) %{
6294 match(Set dst con);
6295 effect(KILL tmp);
6296 format %{ "LDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: float=$con" %}
6297 ins_encode %{
6298 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6299 __ ldf(FloatRegisterImpl::S, $constanttablebase, con_offset, $dst$$FloatRegister);
6300 %}
6301 ins_pipe(loadConFD);
6302 %}
6303
6304 instruct loadConD(regD dst, immD con, o7RegI tmp) %{
6305 match(Set dst con);
6306 effect(KILL tmp);
6307 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: double=$con" %}
6308 ins_encode %{
6309 // XXX This is a quick fix for 6833573.
6310 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset($con), $dst$$FloatRegister);
6311 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset($con), $tmp$$Register);
6312 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
6313 %}
6314 ins_pipe(loadConFD);
6315 %}
6316
6317 // Prefetch instructions for allocation.
6318 // Must be safe to execute with invalid address (cannot fault).
6319
6320 instruct prefetchAlloc( memory mem ) %{
6321 predicate(AllocatePrefetchInstr == 0);
6322 match( PrefetchAllocation mem );
6323 ins_cost(MEMORY_REF_COST);
6324 size(4);
6325
6326 format %{ "PREFETCH $mem,2\t! Prefetch allocation" %}
6327 opcode(Assembler::prefetch_op3);
6328 ins_encode( form3_mem_prefetch_write( mem ) );
6329 ins_pipe(iload_mem);
6330 %}
6331
6332 // Use BIS instruction to prefetch for allocation.
6333 // Could fault, need space at the end of TLAB.
6334 instruct prefetchAlloc_bis( iRegP dst ) %{
6335 predicate(AllocatePrefetchInstr == 1);
6336 match( PrefetchAllocation dst );
6337 ins_cost(MEMORY_REF_COST);
6338 size(4);
6339
6340 format %{ "STXA [$dst]\t! // Prefetch allocation using BIS" %}
6341 ins_encode %{
6342 __ stxa(G0, $dst$$Register, G0, Assembler::ASI_ST_BLKINIT_PRIMARY);
6343 %}
6344 ins_pipe(istore_mem_reg);
6345 %}
6346
6347 // Next code is used for finding next cache line address to prefetch.
6348 #ifndef _LP64
6349 instruct cacheLineAdr( iRegP dst, iRegP src, immI13 mask ) %{
6350 match(Set dst (CastX2P (AndI (CastP2X src) mask)));
6351 ins_cost(DEFAULT_COST);
6352 size(4);
6353
6354 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6355 ins_encode %{
6356 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6357 %}
6358 ins_pipe(ialu_reg_imm);
6359 %}
6360 #else
6361 instruct cacheLineAdr( iRegP dst, iRegP src, immL13 mask ) %{
6362 match(Set dst (CastX2P (AndL (CastP2X src) mask)));
6363 ins_cost(DEFAULT_COST);
6364 size(4);
6365
6366 format %{ "AND $src,$mask,$dst\t! next cache line address" %}
6367 ins_encode %{
6368 __ and3($src$$Register, $mask$$constant, $dst$$Register);
6369 %}
6370 ins_pipe(ialu_reg_imm);
6371 %}
6372 #endif
6373
6374 //----------Store Instructions-------------------------------------------------
6375 // Store Byte
6376 instruct storeB(memory mem, iRegI src) %{
6377 match(Set mem (StoreB mem src));
6378 ins_cost(MEMORY_REF_COST);
6379
6380 size(4);
6381 format %{ "STB $src,$mem\t! byte" %}
6382 opcode(Assembler::stb_op3);
6383 ins_encode(simple_form3_mem_reg( mem, src ) );
6384 ins_pipe(istore_mem_reg);
6385 %}
6386
6387 instruct storeB0(memory mem, immI0 src) %{
6388 match(Set mem (StoreB mem src));
6389 ins_cost(MEMORY_REF_COST);
6390
6391 size(4);
6392 format %{ "STB $src,$mem\t! byte" %}
6393 opcode(Assembler::stb_op3);
6394 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6395 ins_pipe(istore_mem_zero);
6396 %}
6397
6398 instruct storeCM0(memory mem, immI0 src) %{
6399 match(Set mem (StoreCM mem src));
6400 ins_cost(MEMORY_REF_COST);
6401
6402 size(4);
6403 format %{ "STB $src,$mem\t! CMS card-mark byte 0" %}
6404 opcode(Assembler::stb_op3);
6405 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6406 ins_pipe(istore_mem_zero);
6407 %}
6408
6409 // Store Char/Short
6410 instruct storeC(memory mem, iRegI src) %{
6411 match(Set mem (StoreC mem src));
6412 ins_cost(MEMORY_REF_COST);
6413
6414 size(4);
6415 format %{ "STH $src,$mem\t! short" %}
6416 opcode(Assembler::sth_op3);
6417 ins_encode(simple_form3_mem_reg( mem, src ) );
6418 ins_pipe(istore_mem_reg);
6419 %}
6420
6421 instruct storeC0(memory mem, immI0 src) %{
6422 match(Set mem (StoreC mem src));
6423 ins_cost(MEMORY_REF_COST);
6424
6425 size(4);
6426 format %{ "STH $src,$mem\t! short" %}
6427 opcode(Assembler::sth_op3);
6428 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6429 ins_pipe(istore_mem_zero);
6430 %}
6431
6432 // Store Integer
6433 instruct storeI(memory mem, iRegI src) %{
6434 match(Set mem (StoreI mem src));
6435 ins_cost(MEMORY_REF_COST);
6436
6437 size(4);
6438 format %{ "STW $src,$mem" %}
6439 opcode(Assembler::stw_op3);
6440 ins_encode(simple_form3_mem_reg( mem, src ) );
6441 ins_pipe(istore_mem_reg);
6442 %}
6443
6444 // Store Long
6445 instruct storeL(memory mem, iRegL src) %{
6446 match(Set mem (StoreL mem src));
6447 ins_cost(MEMORY_REF_COST);
6448 size(4);
6449 format %{ "STX $src,$mem\t! long" %}
6450 opcode(Assembler::stx_op3);
6451 ins_encode(simple_form3_mem_reg( mem, src ) );
6452 ins_pipe(istore_mem_reg);
6453 %}
6454
6455 instruct storeI0(memory mem, immI0 src) %{
6456 match(Set mem (StoreI mem src));
6457 ins_cost(MEMORY_REF_COST);
6458
6459 size(4);
6460 format %{ "STW $src,$mem" %}
6461 opcode(Assembler::stw_op3);
6462 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6463 ins_pipe(istore_mem_zero);
6464 %}
6465
6466 instruct storeL0(memory mem, immL0 src) %{
6467 match(Set mem (StoreL mem src));
6468 ins_cost(MEMORY_REF_COST);
6469
6470 size(4);
6471 format %{ "STX $src,$mem" %}
6472 opcode(Assembler::stx_op3);
6473 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6474 ins_pipe(istore_mem_zero);
6475 %}
6476
6477 // Store Integer from float register (used after fstoi)
6478 instruct storeI_Freg(memory mem, regF src) %{
6479 match(Set mem (StoreI mem src));
6480 ins_cost(MEMORY_REF_COST);
6481
6482 size(4);
6483 format %{ "STF $src,$mem\t! after fstoi/fdtoi" %}
6484 opcode(Assembler::stf_op3);
6485 ins_encode(simple_form3_mem_reg( mem, src ) );
6486 ins_pipe(fstoreF_mem_reg);
6487 %}
6488
6489 // Store Pointer
6490 instruct storeP(memory dst, sp_ptr_RegP src) %{
6491 match(Set dst (StoreP dst src));
6492 ins_cost(MEMORY_REF_COST);
6493 size(4);
6494
6495 #ifndef _LP64
6496 format %{ "STW $src,$dst\t! ptr" %}
6497 opcode(Assembler::stw_op3, 0, REGP_OP);
6498 #else
6499 format %{ "STX $src,$dst\t! ptr" %}
6500 opcode(Assembler::stx_op3, 0, REGP_OP);
6501 #endif
6502 ins_encode( form3_mem_reg( dst, src ) );
6503 ins_pipe(istore_mem_spORreg);
6504 %}
6505
6506 instruct storeP0(memory dst, immP0 src) %{
6507 match(Set dst (StoreP dst src));
6508 ins_cost(MEMORY_REF_COST);
6509 size(4);
6510
6511 #ifndef _LP64
6512 format %{ "STW $src,$dst\t! ptr" %}
6513 opcode(Assembler::stw_op3, 0, REGP_OP);
6514 #else
6515 format %{ "STX $src,$dst\t! ptr" %}
6516 opcode(Assembler::stx_op3, 0, REGP_OP);
6517 #endif
6518 ins_encode( form3_mem_reg( dst, R_G0 ) );
6519 ins_pipe(istore_mem_zero);
6520 %}
6521
6522 // Store Compressed Pointer
6523 instruct storeN(memory dst, iRegN src) %{
6524 match(Set dst (StoreN dst src));
6525 ins_cost(MEMORY_REF_COST);
6526 size(4);
6527
6528 format %{ "STW $src,$dst\t! compressed ptr" %}
6529 ins_encode %{
6530 Register base = as_Register($dst$$base);
6531 Register index = as_Register($dst$$index);
6532 Register src = $src$$Register;
6533 if (index != G0) {
6534 __ stw(src, base, index);
6535 } else {
6536 __ stw(src, base, $dst$$disp);
6537 }
6538 %}
6539 ins_pipe(istore_mem_spORreg);
6540 %}
6541
6542 instruct storeNKlass(memory dst, iRegN src) %{
6543 match(Set dst (StoreNKlass dst src));
6544 ins_cost(MEMORY_REF_COST);
6545 size(4);
6546
6547 format %{ "STW $src,$dst\t! compressed klass ptr" %}
6548 ins_encode %{
6549 Register base = as_Register($dst$$base);
6550 Register index = as_Register($dst$$index);
6551 Register src = $src$$Register;
6552 if (index != G0) {
6553 __ stw(src, base, index);
6554 } else {
6555 __ stw(src, base, $dst$$disp);
6556 }
6557 %}
6558 ins_pipe(istore_mem_spORreg);
6559 %}
6560
6561 instruct storeN0(memory dst, immN0 src) %{
6562 match(Set dst (StoreN dst src));
6563 ins_cost(MEMORY_REF_COST);
6564 size(4);
6565
6566 format %{ "STW $src,$dst\t! compressed ptr" %}
6567 ins_encode %{
6568 Register base = as_Register($dst$$base);
6569 Register index = as_Register($dst$$index);
6570 if (index != G0) {
6571 __ stw(0, base, index);
6572 } else {
6573 __ stw(0, base, $dst$$disp);
6574 }
6575 %}
6576 ins_pipe(istore_mem_zero);
6577 %}
6578
6579 // Store Double
6580 instruct storeD( memory mem, regD src) %{
6581 match(Set mem (StoreD mem src));
6582 ins_cost(MEMORY_REF_COST);
6583
6584 size(4);
6585 format %{ "STDF $src,$mem" %}
6586 opcode(Assembler::stdf_op3);
6587 ins_encode(simple_form3_mem_reg( mem, src ) );
6588 ins_pipe(fstoreD_mem_reg);
6589 %}
6590
6591 instruct storeD0( memory mem, immD0 src) %{
6592 match(Set mem (StoreD mem src));
6593 ins_cost(MEMORY_REF_COST);
6594
6595 size(4);
6596 format %{ "STX $src,$mem" %}
6597 opcode(Assembler::stx_op3);
6598 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6599 ins_pipe(fstoreD_mem_zero);
6600 %}
6601
6602 // Store Float
6603 instruct storeF( memory mem, regF src) %{
6604 match(Set mem (StoreF mem src));
6605 ins_cost(MEMORY_REF_COST);
6606
6607 size(4);
6608 format %{ "STF $src,$mem" %}
6609 opcode(Assembler::stf_op3);
6610 ins_encode(simple_form3_mem_reg( mem, src ) );
6611 ins_pipe(fstoreF_mem_reg);
6612 %}
6613
6614 instruct storeF0( memory mem, immF0 src) %{
6615 match(Set mem (StoreF mem src));
6616 ins_cost(MEMORY_REF_COST);
6617
6618 size(4);
6619 format %{ "STW $src,$mem\t! storeF0" %}
6620 opcode(Assembler::stw_op3);
6621 ins_encode(simple_form3_mem_reg( mem, R_G0 ) );
6622 ins_pipe(fstoreF_mem_zero);
6623 %}
6624
6625 // Convert oop pointer into compressed form
6626 instruct encodeHeapOop(iRegN dst, iRegP src) %{
6627 predicate(n->bottom_type()->make_ptr()->ptr() != TypePtr::NotNull);
6628 match(Set dst (EncodeP src));
6629 format %{ "encode_heap_oop $src, $dst" %}
6630 ins_encode %{
6631 __ encode_heap_oop($src$$Register, $dst$$Register);
6632 %}
6633 ins_avoid_back_to_back(Universe::narrow_oop_base() == NULL ? AVOID_NONE : AVOID_BEFORE);
6634 ins_pipe(ialu_reg);
6635 %}
6636
6637 instruct encodeHeapOop_not_null(iRegN dst, iRegP src) %{
6638 predicate(n->bottom_type()->make_ptr()->ptr() == TypePtr::NotNull);
6639 match(Set dst (EncodeP src));
6640 format %{ "encode_heap_oop_not_null $src, $dst" %}
6641 ins_encode %{
6642 __ encode_heap_oop_not_null($src$$Register, $dst$$Register);
6643 %}
6644 ins_pipe(ialu_reg);
6645 %}
6646
6647 instruct decodeHeapOop(iRegP dst, iRegN src) %{
6648 predicate(n->bottom_type()->is_oopptr()->ptr() != TypePtr::NotNull &&
6649 n->bottom_type()->is_oopptr()->ptr() != TypePtr::Constant);
6650 match(Set dst (DecodeN src));
6651 format %{ "decode_heap_oop $src, $dst" %}
6652 ins_encode %{
6653 __ decode_heap_oop($src$$Register, $dst$$Register);
6654 %}
6655 ins_pipe(ialu_reg);
6656 %}
6657
6658 instruct decodeHeapOop_not_null(iRegP dst, iRegN src) %{
6659 predicate(n->bottom_type()->is_oopptr()->ptr() == TypePtr::NotNull ||
6660 n->bottom_type()->is_oopptr()->ptr() == TypePtr::Constant);
6661 match(Set dst (DecodeN src));
6662 format %{ "decode_heap_oop_not_null $src, $dst" %}
6663 ins_encode %{
6664 __ decode_heap_oop_not_null($src$$Register, $dst$$Register);
6665 %}
6666 ins_pipe(ialu_reg);
6667 %}
6668
6669 instruct encodeKlass_not_null(iRegN dst, iRegP src) %{
6670 match(Set dst (EncodePKlass src));
6671 format %{ "encode_klass_not_null $src, $dst" %}
6672 ins_encode %{
6673 __ encode_klass_not_null($src$$Register, $dst$$Register);
6674 %}
6675 ins_pipe(ialu_reg);
6676 %}
6677
6678 instruct decodeKlass_not_null(iRegP dst, iRegN src) %{
6679 match(Set dst (DecodeNKlass src));
6680 format %{ "decode_klass_not_null $src, $dst" %}
6681 ins_encode %{
6682 __ decode_klass_not_null($src$$Register, $dst$$Register);
6683 %}
6684 ins_pipe(ialu_reg);
6685 %}
6686
6687 //----------MemBar Instructions-----------------------------------------------
6688 // Memory barrier flavors
6689
6690 instruct membar_acquire() %{
6691 match(MemBarAcquire);
6692 match(LoadFence);
6693 ins_cost(4*MEMORY_REF_COST);
6694
6695 size(0);
6696 format %{ "MEMBAR-acquire" %}
6697 ins_encode( enc_membar_acquire );
6698 ins_pipe(long_memory_op);
6699 %}
6700
6701 instruct membar_acquire_lock() %{
6702 match(MemBarAcquireLock);
6703 ins_cost(0);
6704
6705 size(0);
6706 format %{ "!MEMBAR-acquire (CAS in prior FastLock so empty encoding)" %}
6707 ins_encode( );
6708 ins_pipe(empty);
6709 %}
6710
6711 instruct membar_release() %{
6712 match(MemBarRelease);
6713 match(StoreFence);
6714 ins_cost(4*MEMORY_REF_COST);
6715
6716 size(0);
6717 format %{ "MEMBAR-release" %}
6718 ins_encode( enc_membar_release );
6719 ins_pipe(long_memory_op);
6720 %}
6721
6722 instruct membar_release_lock() %{
6723 match(MemBarReleaseLock);
6724 ins_cost(0);
6725
6726 size(0);
6727 format %{ "!MEMBAR-release (CAS in succeeding FastUnlock so empty encoding)" %}
6728 ins_encode( );
6729 ins_pipe(empty);
6730 %}
6731
6732 instruct membar_volatile() %{
6733 match(MemBarVolatile);
6734 ins_cost(4*MEMORY_REF_COST);
6735
6736 size(4);
6737 format %{ "MEMBAR-volatile" %}
6738 ins_encode( enc_membar_volatile );
6739 ins_pipe(long_memory_op);
6740 %}
6741
6742 instruct unnecessary_membar_volatile() %{
6743 match(MemBarVolatile);
6744 predicate(Matcher::post_store_load_barrier(n));
6745 ins_cost(0);
6746
6747 size(0);
6748 format %{ "!MEMBAR-volatile (unnecessary so empty encoding)" %}
6749 ins_encode( );
6750 ins_pipe(empty);
6751 %}
6752
6753 instruct membar_storestore() %{
6754 match(MemBarStoreStore);
6755 ins_cost(0);
6756
6757 size(0);
6758 format %{ "!MEMBAR-storestore (empty encoding)" %}
6759 ins_encode( );
6760 ins_pipe(empty);
6761 %}
6762
6763 //----------Register Move Instructions-----------------------------------------
6764 instruct roundDouble_nop(regD dst) %{
6765 match(Set dst (RoundDouble dst));
6766 ins_cost(0);
6767 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6768 ins_encode( );
6769 ins_pipe(empty);
6770 %}
6771
6772
6773 instruct roundFloat_nop(regF dst) %{
6774 match(Set dst (RoundFloat dst));
6775 ins_cost(0);
6776 // SPARC results are already "rounded" (i.e., normal-format IEEE)
6777 ins_encode( );
6778 ins_pipe(empty);
6779 %}
6780
6781
6782 // Cast Index to Pointer for unsafe natives
6783 instruct castX2P(iRegX src, iRegP dst) %{
6784 match(Set dst (CastX2P src));
6785
6786 format %{ "MOV $src,$dst\t! IntX->Ptr" %}
6787 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6788 ins_pipe(ialu_reg);
6789 %}
6790
6791 // Cast Pointer to Index for unsafe natives
6792 instruct castP2X(iRegP src, iRegX dst) %{
6793 match(Set dst (CastP2X src));
6794
6795 format %{ "MOV $src,$dst\t! Ptr->IntX" %}
6796 ins_encode( form3_g0_rs2_rd_move( src, dst ) );
6797 ins_pipe(ialu_reg);
6798 %}
6799
6800 instruct stfSSD(stackSlotD stkSlot, regD src) %{
6801 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6802 match(Set stkSlot src); // chain rule
6803 ins_cost(MEMORY_REF_COST);
6804 format %{ "STDF $src,$stkSlot\t!stk" %}
6805 opcode(Assembler::stdf_op3);
6806 ins_encode(simple_form3_mem_reg(stkSlot, src));
6807 ins_pipe(fstoreD_stk_reg);
6808 %}
6809
6810 instruct ldfSSD(regD dst, stackSlotD stkSlot) %{
6811 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6812 match(Set dst stkSlot); // chain rule
6813 ins_cost(MEMORY_REF_COST);
6814 format %{ "LDDF $stkSlot,$dst\t!stk" %}
6815 opcode(Assembler::lddf_op3);
6816 ins_encode(simple_form3_mem_reg(stkSlot, dst));
6817 ins_pipe(floadD_stk);
6818 %}
6819
6820 instruct stfSSF(stackSlotF stkSlot, regF src) %{
6821 // %%%% TO DO: Tell the coalescer that this kind of node is a copy!
6822 match(Set stkSlot src); // chain rule
6823 ins_cost(MEMORY_REF_COST);
6824 format %{ "STF $src,$stkSlot\t!stk" %}
6825 opcode(Assembler::stf_op3);
6826 ins_encode(simple_form3_mem_reg(stkSlot, src));
6827 ins_pipe(fstoreF_stk_reg);
6828 %}
6829
6830 //----------Conditional Move---------------------------------------------------
6831 // Conditional move
6832 instruct cmovIP_reg(cmpOpP cmp, flagsRegP pcc, iRegI dst, iRegI src) %{
6833 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6834 ins_cost(150);
6835 format %{ "MOV$cmp $pcc,$src,$dst" %}
6836 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6837 ins_pipe(ialu_reg);
6838 %}
6839
6840 instruct cmovIP_imm(cmpOpP cmp, flagsRegP pcc, iRegI dst, immI11 src) %{
6841 match(Set dst (CMoveI (Binary cmp pcc) (Binary dst src)));
6842 ins_cost(140);
6843 format %{ "MOV$cmp $pcc,$src,$dst" %}
6844 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6845 ins_pipe(ialu_imm);
6846 %}
6847
6848 instruct cmovII_reg(cmpOp cmp, flagsReg icc, iRegI dst, iRegI src) %{
6849 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6850 ins_cost(150);
6851 size(4);
6852 format %{ "MOV$cmp $icc,$src,$dst" %}
6853 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6854 ins_pipe(ialu_reg);
6855 %}
6856
6857 instruct cmovII_imm(cmpOp cmp, flagsReg icc, iRegI dst, immI11 src) %{
6858 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6859 ins_cost(140);
6860 size(4);
6861 format %{ "MOV$cmp $icc,$src,$dst" %}
6862 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6863 ins_pipe(ialu_imm);
6864 %}
6865
6866 instruct cmovIIu_reg(cmpOpU cmp, flagsRegU icc, iRegI dst, iRegI src) %{
6867 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6868 ins_cost(150);
6869 size(4);
6870 format %{ "MOV$cmp $icc,$src,$dst" %}
6871 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6872 ins_pipe(ialu_reg);
6873 %}
6874
6875 instruct cmovIIu_imm(cmpOpU cmp, flagsRegU icc, iRegI dst, immI11 src) %{
6876 match(Set dst (CMoveI (Binary cmp icc) (Binary dst src)));
6877 ins_cost(140);
6878 size(4);
6879 format %{ "MOV$cmp $icc,$src,$dst" %}
6880 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6881 ins_pipe(ialu_imm);
6882 %}
6883
6884 instruct cmovIF_reg(cmpOpF cmp, flagsRegF fcc, iRegI dst, iRegI src) %{
6885 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6886 ins_cost(150);
6887 size(4);
6888 format %{ "MOV$cmp $fcc,$src,$dst" %}
6889 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6890 ins_pipe(ialu_reg);
6891 %}
6892
6893 instruct cmovIF_imm(cmpOpF cmp, flagsRegF fcc, iRegI dst, immI11 src) %{
6894 match(Set dst (CMoveI (Binary cmp fcc) (Binary dst src)));
6895 ins_cost(140);
6896 size(4);
6897 format %{ "MOV$cmp $fcc,$src,$dst" %}
6898 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
6899 ins_pipe(ialu_imm);
6900 %}
6901
6902 // Conditional move for RegN. Only cmov(reg,reg).
6903 instruct cmovNP_reg(cmpOpP cmp, flagsRegP pcc, iRegN dst, iRegN src) %{
6904 match(Set dst (CMoveN (Binary cmp pcc) (Binary dst src)));
6905 ins_cost(150);
6906 format %{ "MOV$cmp $pcc,$src,$dst" %}
6907 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6908 ins_pipe(ialu_reg);
6909 %}
6910
6911 // This instruction also works with CmpN so we don't need cmovNN_reg.
6912 instruct cmovNI_reg(cmpOp cmp, flagsReg icc, iRegN dst, iRegN src) %{
6913 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6914 ins_cost(150);
6915 size(4);
6916 format %{ "MOV$cmp $icc,$src,$dst" %}
6917 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6918 ins_pipe(ialu_reg);
6919 %}
6920
6921 // This instruction also works with CmpN so we don't need cmovNN_reg.
6922 instruct cmovNIu_reg(cmpOpU cmp, flagsRegU icc, iRegN dst, iRegN src) %{
6923 match(Set dst (CMoveN (Binary cmp icc) (Binary dst src)));
6924 ins_cost(150);
6925 size(4);
6926 format %{ "MOV$cmp $icc,$src,$dst" %}
6927 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6928 ins_pipe(ialu_reg);
6929 %}
6930
6931 instruct cmovNF_reg(cmpOpF cmp, flagsRegF fcc, iRegN dst, iRegN src) %{
6932 match(Set dst (CMoveN (Binary cmp fcc) (Binary dst src)));
6933 ins_cost(150);
6934 size(4);
6935 format %{ "MOV$cmp $fcc,$src,$dst" %}
6936 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
6937 ins_pipe(ialu_reg);
6938 %}
6939
6940 // Conditional move
6941 instruct cmovPP_reg(cmpOpP cmp, flagsRegP pcc, iRegP dst, iRegP src) %{
6942 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6943 ins_cost(150);
6944 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6945 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
6946 ins_pipe(ialu_reg);
6947 %}
6948
6949 instruct cmovPP_imm(cmpOpP cmp, flagsRegP pcc, iRegP dst, immP0 src) %{
6950 match(Set dst (CMoveP (Binary cmp pcc) (Binary dst src)));
6951 ins_cost(140);
6952 format %{ "MOV$cmp $pcc,$src,$dst\t! ptr" %}
6953 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
6954 ins_pipe(ialu_imm);
6955 %}
6956
6957 // This instruction also works with CmpN so we don't need cmovPN_reg.
6958 instruct cmovPI_reg(cmpOp cmp, flagsReg icc, iRegP dst, iRegP src) %{
6959 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6960 ins_cost(150);
6961
6962 size(4);
6963 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6964 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6965 ins_pipe(ialu_reg);
6966 %}
6967
6968 instruct cmovPIu_reg(cmpOpU cmp, flagsRegU icc, iRegP dst, iRegP src) %{
6969 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6970 ins_cost(150);
6971
6972 size(4);
6973 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6974 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
6975 ins_pipe(ialu_reg);
6976 %}
6977
6978 instruct cmovPI_imm(cmpOp cmp, flagsReg icc, iRegP dst, immP0 src) %{
6979 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6980 ins_cost(140);
6981
6982 size(4);
6983 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6984 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6985 ins_pipe(ialu_imm);
6986 %}
6987
6988 instruct cmovPIu_imm(cmpOpU cmp, flagsRegU icc, iRegP dst, immP0 src) %{
6989 match(Set dst (CMoveP (Binary cmp icc) (Binary dst src)));
6990 ins_cost(140);
6991
6992 size(4);
6993 format %{ "MOV$cmp $icc,$src,$dst\t! ptr" %}
6994 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::icc)) );
6995 ins_pipe(ialu_imm);
6996 %}
6997
6998 instruct cmovPF_reg(cmpOpF cmp, flagsRegF fcc, iRegP dst, iRegP src) %{
6999 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
7000 ins_cost(150);
7001 size(4);
7002 format %{ "MOV$cmp $fcc,$src,$dst" %}
7003 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7004 ins_pipe(ialu_imm);
7005 %}
7006
7007 instruct cmovPF_imm(cmpOpF cmp, flagsRegF fcc, iRegP dst, immP0 src) %{
7008 match(Set dst (CMoveP (Binary cmp fcc) (Binary dst src)));
7009 ins_cost(140);
7010 size(4);
7011 format %{ "MOV$cmp $fcc,$src,$dst" %}
7012 ins_encode( enc_cmov_imm_f(cmp,dst,src, fcc) );
7013 ins_pipe(ialu_imm);
7014 %}
7015
7016 // Conditional move
7017 instruct cmovFP_reg(cmpOpP cmp, flagsRegP pcc, regF dst, regF src) %{
7018 match(Set dst (CMoveF (Binary cmp pcc) (Binary dst src)));
7019 ins_cost(150);
7020 opcode(0x101);
7021 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7022 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7023 ins_pipe(int_conditional_float_move);
7024 %}
7025
7026 instruct cmovFI_reg(cmpOp cmp, flagsReg icc, regF dst, regF src) %{
7027 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7028 ins_cost(150);
7029
7030 size(4);
7031 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7032 opcode(0x101);
7033 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7034 ins_pipe(int_conditional_float_move);
7035 %}
7036
7037 instruct cmovFIu_reg(cmpOpU cmp, flagsRegU icc, regF dst, regF src) %{
7038 match(Set dst (CMoveF (Binary cmp icc) (Binary dst src)));
7039 ins_cost(150);
7040
7041 size(4);
7042 format %{ "FMOVS$cmp $icc,$src,$dst" %}
7043 opcode(0x101);
7044 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7045 ins_pipe(int_conditional_float_move);
7046 %}
7047
7048 // Conditional move,
7049 instruct cmovFF_reg(cmpOpF cmp, flagsRegF fcc, regF dst, regF src) %{
7050 match(Set dst (CMoveF (Binary cmp fcc) (Binary dst src)));
7051 ins_cost(150);
7052 size(4);
7053 format %{ "FMOVF$cmp $fcc,$src,$dst" %}
7054 opcode(0x1);
7055 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7056 ins_pipe(int_conditional_double_move);
7057 %}
7058
7059 // Conditional move
7060 instruct cmovDP_reg(cmpOpP cmp, flagsRegP pcc, regD dst, regD src) %{
7061 match(Set dst (CMoveD (Binary cmp pcc) (Binary dst src)));
7062 ins_cost(150);
7063 size(4);
7064 opcode(0x102);
7065 format %{ "FMOVD$cmp $pcc,$src,$dst" %}
7066 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7067 ins_pipe(int_conditional_double_move);
7068 %}
7069
7070 instruct cmovDI_reg(cmpOp cmp, flagsReg icc, regD dst, regD src) %{
7071 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7072 ins_cost(150);
7073
7074 size(4);
7075 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7076 opcode(0x102);
7077 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7078 ins_pipe(int_conditional_double_move);
7079 %}
7080
7081 instruct cmovDIu_reg(cmpOpU cmp, flagsRegU icc, regD dst, regD src) %{
7082 match(Set dst (CMoveD (Binary cmp icc) (Binary dst src)));
7083 ins_cost(150);
7084
7085 size(4);
7086 format %{ "FMOVD$cmp $icc,$src,$dst" %}
7087 opcode(0x102);
7088 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::icc)) );
7089 ins_pipe(int_conditional_double_move);
7090 %}
7091
7092 // Conditional move,
7093 instruct cmovDF_reg(cmpOpF cmp, flagsRegF fcc, regD dst, regD src) %{
7094 match(Set dst (CMoveD (Binary cmp fcc) (Binary dst src)));
7095 ins_cost(150);
7096 size(4);
7097 format %{ "FMOVD$cmp $fcc,$src,$dst" %}
7098 opcode(0x2);
7099 ins_encode( enc_cmovff_reg(cmp,fcc,dst,src) );
7100 ins_pipe(int_conditional_double_move);
7101 %}
7102
7103 // Conditional move
7104 instruct cmovLP_reg(cmpOpP cmp, flagsRegP pcc, iRegL dst, iRegL src) %{
7105 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7106 ins_cost(150);
7107 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7108 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::ptr_cc)) );
7109 ins_pipe(ialu_reg);
7110 %}
7111
7112 instruct cmovLP_imm(cmpOpP cmp, flagsRegP pcc, iRegL dst, immI11 src) %{
7113 match(Set dst (CMoveL (Binary cmp pcc) (Binary dst src)));
7114 ins_cost(140);
7115 format %{ "MOV$cmp $pcc,$src,$dst\t! long" %}
7116 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::ptr_cc)) );
7117 ins_pipe(ialu_imm);
7118 %}
7119
7120 instruct cmovLI_reg(cmpOp cmp, flagsReg icc, iRegL dst, iRegL src) %{
7121 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7122 ins_cost(150);
7123
7124 size(4);
7125 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7126 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7127 ins_pipe(ialu_reg);
7128 %}
7129
7130
7131 instruct cmovLIu_reg(cmpOpU cmp, flagsRegU icc, iRegL dst, iRegL src) %{
7132 match(Set dst (CMoveL (Binary cmp icc) (Binary dst src)));
7133 ins_cost(150);
7134
7135 size(4);
7136 format %{ "MOV$cmp $icc,$src,$dst\t! long" %}
7137 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::icc)) );
7138 ins_pipe(ialu_reg);
7139 %}
7140
7141
7142 instruct cmovLF_reg(cmpOpF cmp, flagsRegF fcc, iRegL dst, iRegL src) %{
7143 match(Set dst (CMoveL (Binary cmp fcc) (Binary dst src)));
7144 ins_cost(150);
7145
7146 size(4);
7147 format %{ "MOV$cmp $fcc,$src,$dst\t! long" %}
7148 ins_encode( enc_cmov_reg_f(cmp,dst,src, fcc) );
7149 ins_pipe(ialu_reg);
7150 %}
7151
7152
7153
7154 //----------OS and Locking Instructions----------------------------------------
7155
7156 // This name is KNOWN by the ADLC and cannot be changed.
7157 // The ADLC forces a 'TypeRawPtr::BOTTOM' output type
7158 // for this guy.
7159 instruct tlsLoadP(g2RegP dst) %{
7160 match(Set dst (ThreadLocal));
7161
7162 size(0);
7163 ins_cost(0);
7164 format %{ "# TLS is in G2" %}
7165 ins_encode( /*empty encoding*/ );
7166 ins_pipe(ialu_none);
7167 %}
7168
7169 instruct checkCastPP( iRegP dst ) %{
7170 match(Set dst (CheckCastPP dst));
7171
7172 size(0);
7173 format %{ "# checkcastPP of $dst" %}
7174 ins_encode( /*empty encoding*/ );
7175 ins_pipe(empty);
7176 %}
7177
7178
7179 instruct castPP( iRegP dst ) %{
7180 match(Set dst (CastPP dst));
7181 format %{ "# castPP of $dst" %}
7182 ins_encode( /*empty encoding*/ );
7183 ins_pipe(empty);
7184 %}
7185
7186 instruct castII( iRegI dst ) %{
7187 match(Set dst (CastII dst));
7188 format %{ "# castII of $dst" %}
7189 ins_encode( /*empty encoding*/ );
7190 ins_cost(0);
7191 ins_pipe(empty);
7192 %}
7193
7194 //----------Arithmetic Instructions--------------------------------------------
7195 // Addition Instructions
7196 // Register Addition
7197 instruct addI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7198 match(Set dst (AddI src1 src2));
7199
7200 size(4);
7201 format %{ "ADD $src1,$src2,$dst" %}
7202 ins_encode %{
7203 __ add($src1$$Register, $src2$$Register, $dst$$Register);
7204 %}
7205 ins_pipe(ialu_reg_reg);
7206 %}
7207
7208 // Immediate Addition
7209 instruct addI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7210 match(Set dst (AddI src1 src2));
7211
7212 size(4);
7213 format %{ "ADD $src1,$src2,$dst" %}
7214 opcode(Assembler::add_op3, Assembler::arith_op);
7215 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7216 ins_pipe(ialu_reg_imm);
7217 %}
7218
7219 // Pointer Register Addition
7220 instruct addP_reg_reg(iRegP dst, iRegP src1, iRegX src2) %{
7221 match(Set dst (AddP src1 src2));
7222
7223 size(4);
7224 format %{ "ADD $src1,$src2,$dst" %}
7225 opcode(Assembler::add_op3, Assembler::arith_op);
7226 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7227 ins_pipe(ialu_reg_reg);
7228 %}
7229
7230 // Pointer Immediate Addition
7231 instruct addP_reg_imm13(iRegP dst, iRegP src1, immX13 src2) %{
7232 match(Set dst (AddP src1 src2));
7233
7234 size(4);
7235 format %{ "ADD $src1,$src2,$dst" %}
7236 opcode(Assembler::add_op3, Assembler::arith_op);
7237 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7238 ins_pipe(ialu_reg_imm);
7239 %}
7240
7241 // Long Addition
7242 instruct addL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7243 match(Set dst (AddL src1 src2));
7244
7245 size(4);
7246 format %{ "ADD $src1,$src2,$dst\t! long" %}
7247 opcode(Assembler::add_op3, Assembler::arith_op);
7248 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7249 ins_pipe(ialu_reg_reg);
7250 %}
7251
7252 instruct addL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7253 match(Set dst (AddL src1 con));
7254
7255 size(4);
7256 format %{ "ADD $src1,$con,$dst" %}
7257 opcode(Assembler::add_op3, Assembler::arith_op);
7258 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7259 ins_pipe(ialu_reg_imm);
7260 %}
7261
7262 //----------Conditional_store--------------------------------------------------
7263 // Conditional-store of the updated heap-top.
7264 // Used during allocation of the shared heap.
7265 // Sets flags (EQ) on success. Implemented with a CASA on Sparc.
7266
7267 // LoadP-locked. Same as a regular pointer load when used with a compare-swap
7268 instruct loadPLocked(iRegP dst, memory mem) %{
7269 match(Set dst (LoadPLocked mem));
7270 ins_cost(MEMORY_REF_COST);
7271
7272 #ifndef _LP64
7273 size(4);
7274 format %{ "LDUW $mem,$dst\t! ptr" %}
7275 opcode(Assembler::lduw_op3, 0, REGP_OP);
7276 #else
7277 format %{ "LDX $mem,$dst\t! ptr" %}
7278 opcode(Assembler::ldx_op3, 0, REGP_OP);
7279 #endif
7280 ins_encode( form3_mem_reg( mem, dst ) );
7281 ins_pipe(iload_mem);
7282 %}
7283
7284 instruct storePConditional( iRegP heap_top_ptr, iRegP oldval, g3RegP newval, flagsRegP pcc ) %{
7285 match(Set pcc (StorePConditional heap_top_ptr (Binary oldval newval)));
7286 effect( KILL newval );
7287 format %{ "CASA [$heap_top_ptr],$oldval,R_G3\t! If $oldval==[$heap_top_ptr] Then store R_G3 into [$heap_top_ptr], set R_G3=[$heap_top_ptr] in any case\n\t"
7288 "CMP R_G3,$oldval\t\t! See if we made progress" %}
7289 ins_encode( enc_cas(heap_top_ptr,oldval,newval) );
7290 ins_pipe( long_memory_op );
7291 %}
7292
7293 // Conditional-store of an int value.
7294 instruct storeIConditional( iRegP mem_ptr, iRegI oldval, g3RegI newval, flagsReg icc ) %{
7295 match(Set icc (StoreIConditional mem_ptr (Binary oldval newval)));
7296 effect( KILL newval );
7297 format %{ "CASA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7298 "CMP $oldval,$newval\t\t! See if we made progress" %}
7299 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7300 ins_pipe( long_memory_op );
7301 %}
7302
7303 // Conditional-store of a long value.
7304 instruct storeLConditional( iRegP mem_ptr, iRegL oldval, g3RegL newval, flagsRegL xcc ) %{
7305 match(Set xcc (StoreLConditional mem_ptr (Binary oldval newval)));
7306 effect( KILL newval );
7307 format %{ "CASXA [$mem_ptr],$oldval,$newval\t! If $oldval==[$mem_ptr] Then store $newval into [$mem_ptr], set $newval=[$mem_ptr] in any case\n\t"
7308 "CMP $oldval,$newval\t\t! See if we made progress" %}
7309 ins_encode( enc_cas(mem_ptr,oldval,newval) );
7310 ins_pipe( long_memory_op );
7311 %}
7312
7313 // No flag versions for CompareAndSwap{P,I,L} because matcher can't match them
7314
7315 instruct compareAndSwapL_bool(iRegP mem_ptr, iRegL oldval, iRegL newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7316 predicate(VM_Version::supports_cx8());
7317 match(Set res (CompareAndSwapL mem_ptr (Binary oldval newval)));
7318 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7319 format %{
7320 "MOV $newval,O7\n\t"
7321 "CASXA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7322 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7323 "MOV 1,$res\n\t"
7324 "MOVne xcc,R_G0,$res"
7325 %}
7326 ins_encode( enc_casx(mem_ptr, oldval, newval),
7327 enc_lflags_ne_to_boolean(res) );
7328 ins_pipe( long_memory_op );
7329 %}
7330
7331
7332 instruct compareAndSwapI_bool(iRegP mem_ptr, iRegI oldval, iRegI newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7333 match(Set res (CompareAndSwapI mem_ptr (Binary oldval newval)));
7334 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7335 format %{
7336 "MOV $newval,O7\n\t"
7337 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7338 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7339 "MOV 1,$res\n\t"
7340 "MOVne icc,R_G0,$res"
7341 %}
7342 ins_encode( enc_casi(mem_ptr, oldval, newval),
7343 enc_iflags_ne_to_boolean(res) );
7344 ins_pipe( long_memory_op );
7345 %}
7346
7347 instruct compareAndSwapP_bool(iRegP mem_ptr, iRegP oldval, iRegP newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7348 #ifdef _LP64
7349 predicate(VM_Version::supports_cx8());
7350 #endif
7351 match(Set res (CompareAndSwapP mem_ptr (Binary oldval newval)));
7352 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7353 format %{
7354 "MOV $newval,O7\n\t"
7355 "CASA_PTR [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7356 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7357 "MOV 1,$res\n\t"
7358 "MOVne xcc,R_G0,$res"
7359 %}
7360 #ifdef _LP64
7361 ins_encode( enc_casx(mem_ptr, oldval, newval),
7362 enc_lflags_ne_to_boolean(res) );
7363 #else
7364 ins_encode( enc_casi(mem_ptr, oldval, newval),
7365 enc_iflags_ne_to_boolean(res) );
7366 #endif
7367 ins_pipe( long_memory_op );
7368 %}
7369
7370 instruct compareAndSwapN_bool(iRegP mem_ptr, iRegN oldval, iRegN newval, iRegI res, o7RegI tmp1, flagsReg ccr ) %{
7371 match(Set res (CompareAndSwapN mem_ptr (Binary oldval newval)));
7372 effect( USE mem_ptr, KILL ccr, KILL tmp1);
7373 format %{
7374 "MOV $newval,O7\n\t"
7375 "CASA [$mem_ptr],$oldval,O7\t! If $oldval==[$mem_ptr] Then store O7 into [$mem_ptr], set O7=[$mem_ptr] in any case\n\t"
7376 "CMP $oldval,O7\t\t! See if we made progress\n\t"
7377 "MOV 1,$res\n\t"
7378 "MOVne icc,R_G0,$res"
7379 %}
7380 ins_encode( enc_casi(mem_ptr, oldval, newval),
7381 enc_iflags_ne_to_boolean(res) );
7382 ins_pipe( long_memory_op );
7383 %}
7384
7385 instruct xchgI( memory mem, iRegI newval) %{
7386 match(Set newval (GetAndSetI mem newval));
7387 format %{ "SWAP [$mem],$newval" %}
7388 size(4);
7389 ins_encode %{
7390 __ swap($mem$$Address, $newval$$Register);
7391 %}
7392 ins_pipe( long_memory_op );
7393 %}
7394
7395 #ifndef _LP64
7396 instruct xchgP( memory mem, iRegP newval) %{
7397 match(Set newval (GetAndSetP mem newval));
7398 format %{ "SWAP [$mem],$newval" %}
7399 size(4);
7400 ins_encode %{
7401 __ swap($mem$$Address, $newval$$Register);
7402 %}
7403 ins_pipe( long_memory_op );
7404 %}
7405 #endif
7406
7407 instruct xchgN( memory mem, iRegN newval) %{
7408 match(Set newval (GetAndSetN mem newval));
7409 format %{ "SWAP [$mem],$newval" %}
7410 size(4);
7411 ins_encode %{
7412 __ swap($mem$$Address, $newval$$Register);
7413 %}
7414 ins_pipe( long_memory_op );
7415 %}
7416
7417 //---------------------
7418 // Subtraction Instructions
7419 // Register Subtraction
7420 instruct subI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7421 match(Set dst (SubI src1 src2));
7422
7423 size(4);
7424 format %{ "SUB $src1,$src2,$dst" %}
7425 opcode(Assembler::sub_op3, Assembler::arith_op);
7426 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7427 ins_pipe(ialu_reg_reg);
7428 %}
7429
7430 // Immediate Subtraction
7431 instruct subI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7432 match(Set dst (SubI src1 src2));
7433
7434 size(4);
7435 format %{ "SUB $src1,$src2,$dst" %}
7436 opcode(Assembler::sub_op3, Assembler::arith_op);
7437 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7438 ins_pipe(ialu_reg_imm);
7439 %}
7440
7441 instruct subI_zero_reg(iRegI dst, immI0 zero, iRegI src2) %{
7442 match(Set dst (SubI zero src2));
7443
7444 size(4);
7445 format %{ "NEG $src2,$dst" %}
7446 opcode(Assembler::sub_op3, Assembler::arith_op);
7447 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7448 ins_pipe(ialu_zero_reg);
7449 %}
7450
7451 // Long subtraction
7452 instruct subL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7453 match(Set dst (SubL src1 src2));
7454
7455 size(4);
7456 format %{ "SUB $src1,$src2,$dst\t! long" %}
7457 opcode(Assembler::sub_op3, Assembler::arith_op);
7458 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7459 ins_pipe(ialu_reg_reg);
7460 %}
7461
7462 // Immediate Subtraction
7463 instruct subL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
7464 match(Set dst (SubL src1 con));
7465
7466 size(4);
7467 format %{ "SUB $src1,$con,$dst\t! long" %}
7468 opcode(Assembler::sub_op3, Assembler::arith_op);
7469 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
7470 ins_pipe(ialu_reg_imm);
7471 %}
7472
7473 // Long negation
7474 instruct negL_reg_reg(iRegL dst, immL0 zero, iRegL src2) %{
7475 match(Set dst (SubL zero src2));
7476
7477 size(4);
7478 format %{ "NEG $src2,$dst\t! long" %}
7479 opcode(Assembler::sub_op3, Assembler::arith_op);
7480 ins_encode( form3_rs1_rs2_rd( R_G0, src2, dst ) );
7481 ins_pipe(ialu_zero_reg);
7482 %}
7483
7484 // Multiplication Instructions
7485 // Integer Multiplication
7486 // Register Multiplication
7487 instruct mulI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7488 match(Set dst (MulI src1 src2));
7489
7490 size(4);
7491 format %{ "MULX $src1,$src2,$dst" %}
7492 opcode(Assembler::mulx_op3, Assembler::arith_op);
7493 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7494 ins_pipe(imul_reg_reg);
7495 %}
7496
7497 // Immediate Multiplication
7498 instruct mulI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
7499 match(Set dst (MulI src1 src2));
7500
7501 size(4);
7502 format %{ "MULX $src1,$src2,$dst" %}
7503 opcode(Assembler::mulx_op3, Assembler::arith_op);
7504 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7505 ins_pipe(imul_reg_imm);
7506 %}
7507
7508 instruct mulL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7509 match(Set dst (MulL src1 src2));
7510 ins_cost(DEFAULT_COST * 5);
7511 size(4);
7512 format %{ "MULX $src1,$src2,$dst\t! long" %}
7513 opcode(Assembler::mulx_op3, Assembler::arith_op);
7514 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7515 ins_pipe(mulL_reg_reg);
7516 %}
7517
7518 // Immediate Multiplication
7519 instruct mulL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7520 match(Set dst (MulL src1 src2));
7521 ins_cost(DEFAULT_COST * 5);
7522 size(4);
7523 format %{ "MULX $src1,$src2,$dst" %}
7524 opcode(Assembler::mulx_op3, Assembler::arith_op);
7525 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7526 ins_pipe(mulL_reg_imm);
7527 %}
7528
7529 // Integer Division
7530 // Register Division
7531 instruct divI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2) %{
7532 match(Set dst (DivI src1 src2));
7533 ins_cost((2+71)*DEFAULT_COST);
7534
7535 format %{ "SRA $src2,0,$src2\n\t"
7536 "SRA $src1,0,$src1\n\t"
7537 "SDIVX $src1,$src2,$dst" %}
7538 ins_encode( idiv_reg( src1, src2, dst ) );
7539 ins_pipe(sdiv_reg_reg);
7540 %}
7541
7542 // Immediate Division
7543 instruct divI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2) %{
7544 match(Set dst (DivI src1 src2));
7545 ins_cost((2+71)*DEFAULT_COST);
7546
7547 format %{ "SRA $src1,0,$src1\n\t"
7548 "SDIVX $src1,$src2,$dst" %}
7549 ins_encode( idiv_imm( src1, src2, dst ) );
7550 ins_pipe(sdiv_reg_imm);
7551 %}
7552
7553 //----------Div-By-10-Expansion------------------------------------------------
7554 // Extract hi bits of a 32x32->64 bit multiply.
7555 // Expand rule only, not matched
7556 instruct mul_hi(iRegIsafe dst, iRegIsafe src1, iRegIsafe src2 ) %{
7557 effect( DEF dst, USE src1, USE src2 );
7558 format %{ "MULX $src1,$src2,$dst\t! Used in div-by-10\n\t"
7559 "SRLX $dst,#32,$dst\t\t! Extract only hi word of result" %}
7560 ins_encode( enc_mul_hi(dst,src1,src2));
7561 ins_pipe(sdiv_reg_reg);
7562 %}
7563
7564 // Magic constant, reciprocal of 10
7565 instruct loadConI_x66666667(iRegIsafe dst) %{
7566 effect( DEF dst );
7567
7568 size(8);
7569 format %{ "SET 0x66666667,$dst\t! Used in div-by-10" %}
7570 ins_encode( Set32(0x66666667, dst) );
7571 ins_pipe(ialu_hi_lo_reg);
7572 %}
7573
7574 // Register Shift Right Arithmetic Long by 32-63
7575 instruct sra_31( iRegI dst, iRegI src ) %{
7576 effect( DEF dst, USE src );
7577 format %{ "SRA $src,31,$dst\t! Used in div-by-10" %}
7578 ins_encode( form3_rs1_rd_copysign_hi(src,dst) );
7579 ins_pipe(ialu_reg_reg);
7580 %}
7581
7582 // Arithmetic Shift Right by 8-bit immediate
7583 instruct sra_reg_2( iRegI dst, iRegI src ) %{
7584 effect( DEF dst, USE src );
7585 format %{ "SRA $src,2,$dst\t! Used in div-by-10" %}
7586 opcode(Assembler::sra_op3, Assembler::arith_op);
7587 ins_encode( form3_rs1_simm13_rd( src, 0x2, dst ) );
7588 ins_pipe(ialu_reg_imm);
7589 %}
7590
7591 // Integer DIV with 10
7592 instruct divI_10( iRegI dst, iRegIsafe src, immI10 div ) %{
7593 match(Set dst (DivI src div));
7594 ins_cost((6+6)*DEFAULT_COST);
7595 expand %{
7596 iRegIsafe tmp1; // Killed temps;
7597 iRegIsafe tmp2; // Killed temps;
7598 iRegI tmp3; // Killed temps;
7599 iRegI tmp4; // Killed temps;
7600 loadConI_x66666667( tmp1 ); // SET 0x66666667 -> tmp1
7601 mul_hi( tmp2, src, tmp1 ); // MUL hibits(src * tmp1) -> tmp2
7602 sra_31( tmp3, src ); // SRA src,31 -> tmp3
7603 sra_reg_2( tmp4, tmp2 ); // SRA tmp2,2 -> tmp4
7604 subI_reg_reg( dst,tmp4,tmp3); // SUB tmp4 - tmp3 -> dst
7605 %}
7606 %}
7607
7608 // Register Long Division
7609 instruct divL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7610 match(Set dst (DivL src1 src2));
7611 ins_cost(DEFAULT_COST*71);
7612 size(4);
7613 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7614 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7615 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7616 ins_pipe(divL_reg_reg);
7617 %}
7618
7619 // Register Long Division
7620 instruct divL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7621 match(Set dst (DivL src1 src2));
7622 ins_cost(DEFAULT_COST*71);
7623 size(4);
7624 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7625 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7626 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7627 ins_pipe(divL_reg_imm);
7628 %}
7629
7630 // Integer Remainder
7631 // Register Remainder
7632 instruct modI_reg_reg(iRegI dst, iRegIsafe src1, iRegIsafe src2, o7RegP temp, flagsReg ccr ) %{
7633 match(Set dst (ModI src1 src2));
7634 effect( KILL ccr, KILL temp);
7635
7636 format %{ "SREM $src1,$src2,$dst" %}
7637 ins_encode( irem_reg(src1, src2, dst, temp) );
7638 ins_pipe(sdiv_reg_reg);
7639 %}
7640
7641 // Immediate Remainder
7642 instruct modI_reg_imm13(iRegI dst, iRegIsafe src1, immI13 src2, o7RegP temp, flagsReg ccr ) %{
7643 match(Set dst (ModI src1 src2));
7644 effect( KILL ccr, KILL temp);
7645
7646 format %{ "SREM $src1,$src2,$dst" %}
7647 ins_encode( irem_imm(src1, src2, dst, temp) );
7648 ins_pipe(sdiv_reg_imm);
7649 %}
7650
7651 // Register Long Remainder
7652 instruct divL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7653 effect(DEF dst, USE src1, USE src2);
7654 size(4);
7655 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7656 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7657 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7658 ins_pipe(divL_reg_reg);
7659 %}
7660
7661 // Register Long Division
7662 instruct divL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7663 effect(DEF dst, USE src1, USE src2);
7664 size(4);
7665 format %{ "SDIVX $src1,$src2,$dst\t! long" %}
7666 opcode(Assembler::sdivx_op3, Assembler::arith_op);
7667 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7668 ins_pipe(divL_reg_imm);
7669 %}
7670
7671 instruct mulL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7672 effect(DEF dst, USE src1, USE src2);
7673 size(4);
7674 format %{ "MULX $src1,$src2,$dst\t! long" %}
7675 opcode(Assembler::mulx_op3, Assembler::arith_op);
7676 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7677 ins_pipe(mulL_reg_reg);
7678 %}
7679
7680 // Immediate Multiplication
7681 instruct mulL_reg_imm13_1(iRegL dst, iRegL src1, immL13 src2) %{
7682 effect(DEF dst, USE src1, USE src2);
7683 size(4);
7684 format %{ "MULX $src1,$src2,$dst" %}
7685 opcode(Assembler::mulx_op3, Assembler::arith_op);
7686 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
7687 ins_pipe(mulL_reg_imm);
7688 %}
7689
7690 instruct subL_reg_reg_1(iRegL dst, iRegL src1, iRegL src2) %{
7691 effect(DEF dst, USE src1, USE src2);
7692 size(4);
7693 format %{ "SUB $src1,$src2,$dst\t! long" %}
7694 opcode(Assembler::sub_op3, Assembler::arith_op);
7695 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7696 ins_pipe(ialu_reg_reg);
7697 %}
7698
7699 instruct subL_reg_reg_2(iRegL dst, iRegL src1, iRegL src2) %{
7700 effect(DEF dst, USE src1, USE src2);
7701 size(4);
7702 format %{ "SUB $src1,$src2,$dst\t! long" %}
7703 opcode(Assembler::sub_op3, Assembler::arith_op);
7704 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7705 ins_pipe(ialu_reg_reg);
7706 %}
7707
7708 // Register Long Remainder
7709 instruct modL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
7710 match(Set dst (ModL src1 src2));
7711 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7712 expand %{
7713 iRegL tmp1;
7714 iRegL tmp2;
7715 divL_reg_reg_1(tmp1, src1, src2);
7716 mulL_reg_reg_1(tmp2, tmp1, src2);
7717 subL_reg_reg_1(dst, src1, tmp2);
7718 %}
7719 %}
7720
7721 // Register Long Remainder
7722 instruct modL_reg_imm13(iRegL dst, iRegL src1, immL13 src2) %{
7723 match(Set dst (ModL src1 src2));
7724 ins_cost(DEFAULT_COST*(71 + 6 + 1));
7725 expand %{
7726 iRegL tmp1;
7727 iRegL tmp2;
7728 divL_reg_imm13_1(tmp1, src1, src2);
7729 mulL_reg_imm13_1(tmp2, tmp1, src2);
7730 subL_reg_reg_2 (dst, src1, tmp2);
7731 %}
7732 %}
7733
7734 // Integer Shift Instructions
7735 // Register Shift Left
7736 instruct shlI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7737 match(Set dst (LShiftI src1 src2));
7738
7739 size(4);
7740 format %{ "SLL $src1,$src2,$dst" %}
7741 opcode(Assembler::sll_op3, Assembler::arith_op);
7742 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7743 ins_pipe(ialu_reg_reg);
7744 %}
7745
7746 // Register Shift Left Immediate
7747 instruct shlI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7748 match(Set dst (LShiftI src1 src2));
7749
7750 size(4);
7751 format %{ "SLL $src1,$src2,$dst" %}
7752 opcode(Assembler::sll_op3, Assembler::arith_op);
7753 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7754 ins_pipe(ialu_reg_imm);
7755 %}
7756
7757 // Register Shift Left
7758 instruct shlL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7759 match(Set dst (LShiftL src1 src2));
7760
7761 size(4);
7762 format %{ "SLLX $src1,$src2,$dst" %}
7763 opcode(Assembler::sllx_op3, Assembler::arith_op);
7764 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7765 ins_pipe(ialu_reg_reg);
7766 %}
7767
7768 // Register Shift Left Immediate
7769 instruct shlL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7770 match(Set dst (LShiftL src1 src2));
7771
7772 size(4);
7773 format %{ "SLLX $src1,$src2,$dst" %}
7774 opcode(Assembler::sllx_op3, Assembler::arith_op);
7775 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7776 ins_pipe(ialu_reg_imm);
7777 %}
7778
7779 // Register Arithmetic Shift Right
7780 instruct sarI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7781 match(Set dst (RShiftI src1 src2));
7782 size(4);
7783 format %{ "SRA $src1,$src2,$dst" %}
7784 opcode(Assembler::sra_op3, Assembler::arith_op);
7785 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7786 ins_pipe(ialu_reg_reg);
7787 %}
7788
7789 // Register Arithmetic Shift Right Immediate
7790 instruct sarI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7791 match(Set dst (RShiftI src1 src2));
7792
7793 size(4);
7794 format %{ "SRA $src1,$src2,$dst" %}
7795 opcode(Assembler::sra_op3, Assembler::arith_op);
7796 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7797 ins_pipe(ialu_reg_imm);
7798 %}
7799
7800 // Register Shift Right Arithmatic Long
7801 instruct sarL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7802 match(Set dst (RShiftL src1 src2));
7803
7804 size(4);
7805 format %{ "SRAX $src1,$src2,$dst" %}
7806 opcode(Assembler::srax_op3, Assembler::arith_op);
7807 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7808 ins_pipe(ialu_reg_reg);
7809 %}
7810
7811 // Register Shift Left Immediate
7812 instruct sarL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7813 match(Set dst (RShiftL src1 src2));
7814
7815 size(4);
7816 format %{ "SRAX $src1,$src2,$dst" %}
7817 opcode(Assembler::srax_op3, Assembler::arith_op);
7818 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7819 ins_pipe(ialu_reg_imm);
7820 %}
7821
7822 // Register Shift Right
7823 instruct shrI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
7824 match(Set dst (URShiftI src1 src2));
7825
7826 size(4);
7827 format %{ "SRL $src1,$src2,$dst" %}
7828 opcode(Assembler::srl_op3, Assembler::arith_op);
7829 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
7830 ins_pipe(ialu_reg_reg);
7831 %}
7832
7833 // Register Shift Right Immediate
7834 instruct shrI_reg_imm5(iRegI dst, iRegI src1, immU5 src2) %{
7835 match(Set dst (URShiftI src1 src2));
7836
7837 size(4);
7838 format %{ "SRL $src1,$src2,$dst" %}
7839 opcode(Assembler::srl_op3, Assembler::arith_op);
7840 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7841 ins_pipe(ialu_reg_imm);
7842 %}
7843
7844 // Register Shift Right
7845 instruct shrL_reg_reg(iRegL dst, iRegL src1, iRegI src2) %{
7846 match(Set dst (URShiftL src1 src2));
7847
7848 size(4);
7849 format %{ "SRLX $src1,$src2,$dst" %}
7850 opcode(Assembler::srlx_op3, Assembler::arith_op);
7851 ins_encode( form3_sd_rs1_rs2_rd( src1, src2, dst ) );
7852 ins_pipe(ialu_reg_reg);
7853 %}
7854
7855 // Register Shift Right Immediate
7856 instruct shrL_reg_imm6(iRegL dst, iRegL src1, immU6 src2) %{
7857 match(Set dst (URShiftL src1 src2));
7858
7859 size(4);
7860 format %{ "SRLX $src1,$src2,$dst" %}
7861 opcode(Assembler::srlx_op3, Assembler::arith_op);
7862 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7863 ins_pipe(ialu_reg_imm);
7864 %}
7865
7866 // Register Shift Right Immediate with a CastP2X
7867 #ifdef _LP64
7868 instruct shrP_reg_imm6(iRegL dst, iRegP src1, immU6 src2) %{
7869 match(Set dst (URShiftL (CastP2X src1) src2));
7870 size(4);
7871 format %{ "SRLX $src1,$src2,$dst\t! Cast ptr $src1 to long and shift" %}
7872 opcode(Assembler::srlx_op3, Assembler::arith_op);
7873 ins_encode( form3_sd_rs1_imm6_rd( src1, src2, dst ) );
7874 ins_pipe(ialu_reg_imm);
7875 %}
7876 #else
7877 instruct shrP_reg_imm5(iRegI dst, iRegP src1, immU5 src2) %{
7878 match(Set dst (URShiftI (CastP2X src1) src2));
7879 size(4);
7880 format %{ "SRL $src1,$src2,$dst\t! Cast ptr $src1 to int and shift" %}
7881 opcode(Assembler::srl_op3, Assembler::arith_op);
7882 ins_encode( form3_rs1_imm5_rd( src1, src2, dst ) );
7883 ins_pipe(ialu_reg_imm);
7884 %}
7885 #endif
7886
7887
7888 //----------Floating Point Arithmetic Instructions-----------------------------
7889
7890 // Add float single precision
7891 instruct addF_reg_reg(regF dst, regF src1, regF src2) %{
7892 match(Set dst (AddF src1 src2));
7893
7894 size(4);
7895 format %{ "FADDS $src1,$src2,$dst" %}
7896 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fadds_opf);
7897 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7898 ins_pipe(faddF_reg_reg);
7899 %}
7900
7901 // Add float double precision
7902 instruct addD_reg_reg(regD dst, regD src1, regD src2) %{
7903 match(Set dst (AddD src1 src2));
7904
7905 size(4);
7906 format %{ "FADDD $src1,$src2,$dst" %}
7907 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
7908 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7909 ins_pipe(faddD_reg_reg);
7910 %}
7911
7912 // Sub float single precision
7913 instruct subF_reg_reg(regF dst, regF src1, regF src2) %{
7914 match(Set dst (SubF src1 src2));
7915
7916 size(4);
7917 format %{ "FSUBS $src1,$src2,$dst" %}
7918 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubs_opf);
7919 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7920 ins_pipe(faddF_reg_reg);
7921 %}
7922
7923 // Sub float double precision
7924 instruct subD_reg_reg(regD dst, regD src1, regD src2) %{
7925 match(Set dst (SubD src1 src2));
7926
7927 size(4);
7928 format %{ "FSUBD $src1,$src2,$dst" %}
7929 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
7930 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7931 ins_pipe(faddD_reg_reg);
7932 %}
7933
7934 // Mul float single precision
7935 instruct mulF_reg_reg(regF dst, regF src1, regF src2) %{
7936 match(Set dst (MulF src1 src2));
7937
7938 size(4);
7939 format %{ "FMULS $src1,$src2,$dst" %}
7940 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuls_opf);
7941 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7942 ins_pipe(fmulF_reg_reg);
7943 %}
7944
7945 // Mul float double precision
7946 instruct mulD_reg_reg(regD dst, regD src1, regD src2) %{
7947 match(Set dst (MulD src1 src2));
7948
7949 size(4);
7950 format %{ "FMULD $src1,$src2,$dst" %}
7951 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
7952 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7953 ins_pipe(fmulD_reg_reg);
7954 %}
7955
7956 // Div float single precision
7957 instruct divF_reg_reg(regF dst, regF src1, regF src2) %{
7958 match(Set dst (DivF src1 src2));
7959
7960 size(4);
7961 format %{ "FDIVS $src1,$src2,$dst" %}
7962 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivs_opf);
7963 ins_encode(form3_opf_rs1F_rs2F_rdF(src1, src2, dst));
7964 ins_pipe(fdivF_reg_reg);
7965 %}
7966
7967 // Div float double precision
7968 instruct divD_reg_reg(regD dst, regD src1, regD src2) %{
7969 match(Set dst (DivD src1 src2));
7970
7971 size(4);
7972 format %{ "FDIVD $src1,$src2,$dst" %}
7973 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdivd_opf);
7974 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
7975 ins_pipe(fdivD_reg_reg);
7976 %}
7977
7978 // Absolute float double precision
7979 instruct absD_reg(regD dst, regD src) %{
7980 match(Set dst (AbsD src));
7981
7982 format %{ "FABSd $src,$dst" %}
7983 ins_encode(fabsd(dst, src));
7984 ins_pipe(faddD_reg);
7985 %}
7986
7987 // Absolute float single precision
7988 instruct absF_reg(regF dst, regF src) %{
7989 match(Set dst (AbsF src));
7990
7991 format %{ "FABSs $src,$dst" %}
7992 ins_encode(fabss(dst, src));
7993 ins_pipe(faddF_reg);
7994 %}
7995
7996 instruct negF_reg(regF dst, regF src) %{
7997 match(Set dst (NegF src));
7998
7999 size(4);
8000 format %{ "FNEGs $src,$dst" %}
8001 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fnegs_opf);
8002 ins_encode(form3_opf_rs2F_rdF(src, dst));
8003 ins_pipe(faddF_reg);
8004 %}
8005
8006 instruct negD_reg(regD dst, regD src) %{
8007 match(Set dst (NegD src));
8008
8009 format %{ "FNEGd $src,$dst" %}
8010 ins_encode(fnegd(dst, src));
8011 ins_pipe(faddD_reg);
8012 %}
8013
8014 // Sqrt float double precision
8015 instruct sqrtF_reg_reg(regF dst, regF src) %{
8016 match(Set dst (ConvD2F (SqrtD (ConvF2D src))));
8017
8018 size(4);
8019 format %{ "FSQRTS $src,$dst" %}
8020 ins_encode(fsqrts(dst, src));
8021 ins_pipe(fdivF_reg_reg);
8022 %}
8023
8024 // Sqrt float double precision
8025 instruct sqrtD_reg_reg(regD dst, regD src) %{
8026 match(Set dst (SqrtD src));
8027
8028 size(4);
8029 format %{ "FSQRTD $src,$dst" %}
8030 ins_encode(fsqrtd(dst, src));
8031 ins_pipe(fdivD_reg_reg);
8032 %}
8033
8034 //----------Logical Instructions-----------------------------------------------
8035 // And Instructions
8036 // Register And
8037 instruct andI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8038 match(Set dst (AndI src1 src2));
8039
8040 size(4);
8041 format %{ "AND $src1,$src2,$dst" %}
8042 opcode(Assembler::and_op3, Assembler::arith_op);
8043 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8044 ins_pipe(ialu_reg_reg);
8045 %}
8046
8047 // Immediate And
8048 instruct andI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8049 match(Set dst (AndI src1 src2));
8050
8051 size(4);
8052 format %{ "AND $src1,$src2,$dst" %}
8053 opcode(Assembler::and_op3, Assembler::arith_op);
8054 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8055 ins_pipe(ialu_reg_imm);
8056 %}
8057
8058 // Register And Long
8059 instruct andL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8060 match(Set dst (AndL src1 src2));
8061
8062 ins_cost(DEFAULT_COST);
8063 size(4);
8064 format %{ "AND $src1,$src2,$dst\t! long" %}
8065 opcode(Assembler::and_op3, Assembler::arith_op);
8066 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8067 ins_pipe(ialu_reg_reg);
8068 %}
8069
8070 instruct andL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8071 match(Set dst (AndL src1 con));
8072
8073 ins_cost(DEFAULT_COST);
8074 size(4);
8075 format %{ "AND $src1,$con,$dst\t! long" %}
8076 opcode(Assembler::and_op3, Assembler::arith_op);
8077 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8078 ins_pipe(ialu_reg_imm);
8079 %}
8080
8081 // Or Instructions
8082 // Register Or
8083 instruct orI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8084 match(Set dst (OrI src1 src2));
8085
8086 size(4);
8087 format %{ "OR $src1,$src2,$dst" %}
8088 opcode(Assembler::or_op3, Assembler::arith_op);
8089 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8090 ins_pipe(ialu_reg_reg);
8091 %}
8092
8093 // Immediate Or
8094 instruct orI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8095 match(Set dst (OrI src1 src2));
8096
8097 size(4);
8098 format %{ "OR $src1,$src2,$dst" %}
8099 opcode(Assembler::or_op3, Assembler::arith_op);
8100 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8101 ins_pipe(ialu_reg_imm);
8102 %}
8103
8104 // Register Or Long
8105 instruct orL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8106 match(Set dst (OrL src1 src2));
8107
8108 ins_cost(DEFAULT_COST);
8109 size(4);
8110 format %{ "OR $src1,$src2,$dst\t! long" %}
8111 opcode(Assembler::or_op3, Assembler::arith_op);
8112 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8113 ins_pipe(ialu_reg_reg);
8114 %}
8115
8116 instruct orL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8117 match(Set dst (OrL src1 con));
8118 ins_cost(DEFAULT_COST*2);
8119
8120 ins_cost(DEFAULT_COST);
8121 size(4);
8122 format %{ "OR $src1,$con,$dst\t! long" %}
8123 opcode(Assembler::or_op3, Assembler::arith_op);
8124 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8125 ins_pipe(ialu_reg_imm);
8126 %}
8127
8128 #ifndef _LP64
8129
8130 // Use sp_ptr_RegP to match G2 (TLS register) without spilling.
8131 instruct orI_reg_castP2X(iRegI dst, iRegI src1, sp_ptr_RegP src2) %{
8132 match(Set dst (OrI src1 (CastP2X src2)));
8133
8134 size(4);
8135 format %{ "OR $src1,$src2,$dst" %}
8136 opcode(Assembler::or_op3, Assembler::arith_op);
8137 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8138 ins_pipe(ialu_reg_reg);
8139 %}
8140
8141 #else
8142
8143 instruct orL_reg_castP2X(iRegL dst, iRegL src1, sp_ptr_RegP src2) %{
8144 match(Set dst (OrL src1 (CastP2X src2)));
8145
8146 ins_cost(DEFAULT_COST);
8147 size(4);
8148 format %{ "OR $src1,$src2,$dst\t! long" %}
8149 opcode(Assembler::or_op3, Assembler::arith_op);
8150 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8151 ins_pipe(ialu_reg_reg);
8152 %}
8153
8154 #endif
8155
8156 // Xor Instructions
8157 // Register Xor
8158 instruct xorI_reg_reg(iRegI dst, iRegI src1, iRegI src2) %{
8159 match(Set dst (XorI src1 src2));
8160
8161 size(4);
8162 format %{ "XOR $src1,$src2,$dst" %}
8163 opcode(Assembler::xor_op3, Assembler::arith_op);
8164 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8165 ins_pipe(ialu_reg_reg);
8166 %}
8167
8168 // Immediate Xor
8169 instruct xorI_reg_imm13(iRegI dst, iRegI src1, immI13 src2) %{
8170 match(Set dst (XorI src1 src2));
8171
8172 size(4);
8173 format %{ "XOR $src1,$src2,$dst" %}
8174 opcode(Assembler::xor_op3, Assembler::arith_op);
8175 ins_encode( form3_rs1_simm13_rd( src1, src2, dst ) );
8176 ins_pipe(ialu_reg_imm);
8177 %}
8178
8179 // Register Xor Long
8180 instruct xorL_reg_reg(iRegL dst, iRegL src1, iRegL src2) %{
8181 match(Set dst (XorL src1 src2));
8182
8183 ins_cost(DEFAULT_COST);
8184 size(4);
8185 format %{ "XOR $src1,$src2,$dst\t! long" %}
8186 opcode(Assembler::xor_op3, Assembler::arith_op);
8187 ins_encode( form3_rs1_rs2_rd( src1, src2, dst ) );
8188 ins_pipe(ialu_reg_reg);
8189 %}
8190
8191 instruct xorL_reg_imm13(iRegL dst, iRegL src1, immL13 con) %{
8192 match(Set dst (XorL src1 con));
8193
8194 ins_cost(DEFAULT_COST);
8195 size(4);
8196 format %{ "XOR $src1,$con,$dst\t! long" %}
8197 opcode(Assembler::xor_op3, Assembler::arith_op);
8198 ins_encode( form3_rs1_simm13_rd( src1, con, dst ) );
8199 ins_pipe(ialu_reg_imm);
8200 %}
8201
8202 //----------Convert to Boolean-------------------------------------------------
8203 // Nice hack for 32-bit tests but doesn't work for
8204 // 64-bit pointers.
8205 instruct convI2B( iRegI dst, iRegI src, flagsReg ccr ) %{
8206 match(Set dst (Conv2B src));
8207 effect( KILL ccr );
8208 ins_cost(DEFAULT_COST*2);
8209 format %{ "CMP R_G0,$src\n\t"
8210 "ADDX R_G0,0,$dst" %}
8211 ins_encode( enc_to_bool( src, dst ) );
8212 ins_pipe(ialu_reg_ialu);
8213 %}
8214
8215 #ifndef _LP64
8216 instruct convP2B( iRegI dst, iRegP src, flagsReg ccr ) %{
8217 match(Set dst (Conv2B src));
8218 effect( KILL ccr );
8219 ins_cost(DEFAULT_COST*2);
8220 format %{ "CMP R_G0,$src\n\t"
8221 "ADDX R_G0,0,$dst" %}
8222 ins_encode( enc_to_bool( src, dst ) );
8223 ins_pipe(ialu_reg_ialu);
8224 %}
8225 #else
8226 instruct convP2B( iRegI dst, iRegP src ) %{
8227 match(Set dst (Conv2B src));
8228 ins_cost(DEFAULT_COST*2);
8229 format %{ "MOV $src,$dst\n\t"
8230 "MOVRNZ $src,1,$dst" %}
8231 ins_encode( form3_g0_rs2_rd_move( src, dst ), enc_convP2B( dst, src ) );
8232 ins_pipe(ialu_clr_and_mover);
8233 %}
8234 #endif
8235
8236 instruct cmpLTMask0( iRegI dst, iRegI src, immI0 zero, flagsReg ccr ) %{
8237 match(Set dst (CmpLTMask src zero));
8238 effect(KILL ccr);
8239 size(4);
8240 format %{ "SRA $src,#31,$dst\t# cmpLTMask0" %}
8241 ins_encode %{
8242 __ sra($src$$Register, 31, $dst$$Register);
8243 %}
8244 ins_pipe(ialu_reg_imm);
8245 %}
8246
8247 instruct cmpLTMask_reg_reg( iRegI dst, iRegI p, iRegI q, flagsReg ccr ) %{
8248 match(Set dst (CmpLTMask p q));
8249 effect( KILL ccr );
8250 ins_cost(DEFAULT_COST*4);
8251 format %{ "CMP $p,$q\n\t"
8252 "MOV #0,$dst\n\t"
8253 "BLT,a .+8\n\t"
8254 "MOV #-1,$dst" %}
8255 ins_encode( enc_ltmask(p,q,dst) );
8256 ins_pipe(ialu_reg_reg_ialu);
8257 %}
8258
8259 instruct cadd_cmpLTMask( iRegI p, iRegI q, iRegI y, iRegI tmp, flagsReg ccr ) %{
8260 match(Set p (AddI (AndI (CmpLTMask p q) y) (SubI p q)));
8261 effect(KILL ccr, TEMP tmp);
8262 ins_cost(DEFAULT_COST*3);
8263
8264 format %{ "SUBcc $p,$q,$p\t! p' = p-q\n\t"
8265 "ADD $p,$y,$tmp\t! g3=p-q+y\n\t"
8266 "MOVlt $tmp,$p\t! p' < 0 ? p'+y : p'" %}
8267 ins_encode(enc_cadd_cmpLTMask(p, q, y, tmp));
8268 ins_pipe(cadd_cmpltmask);
8269 %}
8270
8271 instruct and_cmpLTMask(iRegI p, iRegI q, iRegI y, flagsReg ccr) %{
8272 match(Set p (AndI (CmpLTMask p q) y));
8273 effect(KILL ccr);
8274 ins_cost(DEFAULT_COST*3);
8275
8276 format %{ "CMP $p,$q\n\t"
8277 "MOV $y,$p\n\t"
8278 "MOVge G0,$p" %}
8279 ins_encode %{
8280 __ cmp($p$$Register, $q$$Register);
8281 __ mov($y$$Register, $p$$Register);
8282 __ movcc(Assembler::greaterEqual, false, Assembler::icc, G0, $p$$Register);
8283 %}
8284 ins_pipe(ialu_reg_reg_ialu);
8285 %}
8286
8287 //-----------------------------------------------------------------
8288 // Direct raw moves between float and general registers using VIS3.
8289
8290 // ins_pipe(faddF_reg);
8291 instruct MoveF2I_reg_reg(iRegI dst, regF src) %{
8292 predicate(UseVIS >= 3);
8293 match(Set dst (MoveF2I src));
8294
8295 format %{ "MOVSTOUW $src,$dst\t! MoveF2I" %}
8296 ins_encode %{
8297 __ movstouw($src$$FloatRegister, $dst$$Register);
8298 %}
8299 ins_pipe(ialu_reg_reg);
8300 %}
8301
8302 instruct MoveI2F_reg_reg(regF dst, iRegI src) %{
8303 predicate(UseVIS >= 3);
8304 match(Set dst (MoveI2F src));
8305
8306 format %{ "MOVWTOS $src,$dst\t! MoveI2F" %}
8307 ins_encode %{
8308 __ movwtos($src$$Register, $dst$$FloatRegister);
8309 %}
8310 ins_pipe(ialu_reg_reg);
8311 %}
8312
8313 instruct MoveD2L_reg_reg(iRegL dst, regD src) %{
8314 predicate(UseVIS >= 3);
8315 match(Set dst (MoveD2L src));
8316
8317 format %{ "MOVDTOX $src,$dst\t! MoveD2L" %}
8318 ins_encode %{
8319 __ movdtox(as_DoubleFloatRegister($src$$reg), $dst$$Register);
8320 %}
8321 ins_pipe(ialu_reg_reg);
8322 %}
8323
8324 instruct MoveL2D_reg_reg(regD dst, iRegL src) %{
8325 predicate(UseVIS >= 3);
8326 match(Set dst (MoveL2D src));
8327
8328 format %{ "MOVXTOD $src,$dst\t! MoveL2D" %}
8329 ins_encode %{
8330 __ movxtod($src$$Register, as_DoubleFloatRegister($dst$$reg));
8331 %}
8332 ins_pipe(ialu_reg_reg);
8333 %}
8334
8335
8336 // Raw moves between float and general registers using stack.
8337
8338 instruct MoveF2I_stack_reg(iRegI dst, stackSlotF src) %{
8339 match(Set dst (MoveF2I src));
8340 effect(DEF dst, USE src);
8341 ins_cost(MEMORY_REF_COST);
8342
8343 size(4);
8344 format %{ "LDUW $src,$dst\t! MoveF2I" %}
8345 opcode(Assembler::lduw_op3);
8346 ins_encode(simple_form3_mem_reg( src, dst ) );
8347 ins_pipe(iload_mem);
8348 %}
8349
8350 instruct MoveI2F_stack_reg(regF dst, stackSlotI src) %{
8351 match(Set dst (MoveI2F src));
8352 effect(DEF dst, USE src);
8353 ins_cost(MEMORY_REF_COST);
8354
8355 size(4);
8356 format %{ "LDF $src,$dst\t! MoveI2F" %}
8357 opcode(Assembler::ldf_op3);
8358 ins_encode(simple_form3_mem_reg(src, dst));
8359 ins_pipe(floadF_stk);
8360 %}
8361
8362 instruct MoveD2L_stack_reg(iRegL dst, stackSlotD src) %{
8363 match(Set dst (MoveD2L src));
8364 effect(DEF dst, USE src);
8365 ins_cost(MEMORY_REF_COST);
8366
8367 size(4);
8368 format %{ "LDX $src,$dst\t! MoveD2L" %}
8369 opcode(Assembler::ldx_op3);
8370 ins_encode(simple_form3_mem_reg( src, dst ) );
8371 ins_pipe(iload_mem);
8372 %}
8373
8374 instruct MoveL2D_stack_reg(regD dst, stackSlotL src) %{
8375 match(Set dst (MoveL2D src));
8376 effect(DEF dst, USE src);
8377 ins_cost(MEMORY_REF_COST);
8378
8379 size(4);
8380 format %{ "LDDF $src,$dst\t! MoveL2D" %}
8381 opcode(Assembler::lddf_op3);
8382 ins_encode(simple_form3_mem_reg(src, dst));
8383 ins_pipe(floadD_stk);
8384 %}
8385
8386 instruct MoveF2I_reg_stack(stackSlotI dst, regF src) %{
8387 match(Set dst (MoveF2I src));
8388 effect(DEF dst, USE src);
8389 ins_cost(MEMORY_REF_COST);
8390
8391 size(4);
8392 format %{ "STF $src,$dst\t! MoveF2I" %}
8393 opcode(Assembler::stf_op3);
8394 ins_encode(simple_form3_mem_reg(dst, src));
8395 ins_pipe(fstoreF_stk_reg);
8396 %}
8397
8398 instruct MoveI2F_reg_stack(stackSlotF dst, iRegI src) %{
8399 match(Set dst (MoveI2F src));
8400 effect(DEF dst, USE src);
8401 ins_cost(MEMORY_REF_COST);
8402
8403 size(4);
8404 format %{ "STW $src,$dst\t! MoveI2F" %}
8405 opcode(Assembler::stw_op3);
8406 ins_encode(simple_form3_mem_reg( dst, src ) );
8407 ins_pipe(istore_mem_reg);
8408 %}
8409
8410 instruct MoveD2L_reg_stack(stackSlotL dst, regD src) %{
8411 match(Set dst (MoveD2L src));
8412 effect(DEF dst, USE src);
8413 ins_cost(MEMORY_REF_COST);
8414
8415 size(4);
8416 format %{ "STDF $src,$dst\t! MoveD2L" %}
8417 opcode(Assembler::stdf_op3);
8418 ins_encode(simple_form3_mem_reg(dst, src));
8419 ins_pipe(fstoreD_stk_reg);
8420 %}
8421
8422 instruct MoveL2D_reg_stack(stackSlotD dst, iRegL src) %{
8423 match(Set dst (MoveL2D src));
8424 effect(DEF dst, USE src);
8425 ins_cost(MEMORY_REF_COST);
8426
8427 size(4);
8428 format %{ "STX $src,$dst\t! MoveL2D" %}
8429 opcode(Assembler::stx_op3);
8430 ins_encode(simple_form3_mem_reg( dst, src ) );
8431 ins_pipe(istore_mem_reg);
8432 %}
8433
8434
8435 //----------Arithmetic Conversion Instructions---------------------------------
8436 // The conversions operations are all Alpha sorted. Please keep it that way!
8437
8438 instruct convD2F_reg(regF dst, regD src) %{
8439 match(Set dst (ConvD2F src));
8440 size(4);
8441 format %{ "FDTOS $src,$dst" %}
8442 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fdtos_opf);
8443 ins_encode(form3_opf_rs2D_rdF(src, dst));
8444 ins_pipe(fcvtD2F);
8445 %}
8446
8447
8448 // Convert a double to an int in a float register.
8449 // If the double is a NAN, stuff a zero in instead.
8450 instruct convD2I_helper(regF dst, regD src, flagsRegF0 fcc0) %{
8451 effect(DEF dst, USE src, KILL fcc0);
8452 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8453 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8454 "FDTOI $src,$dst\t! convert in delay slot\n\t"
8455 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8456 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8457 "skip:" %}
8458 ins_encode(form_d2i_helper(src,dst));
8459 ins_pipe(fcvtD2I);
8460 %}
8461
8462 instruct convD2I_stk(stackSlotI dst, regD src) %{
8463 match(Set dst (ConvD2I src));
8464 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8465 expand %{
8466 regF tmp;
8467 convD2I_helper(tmp, src);
8468 regF_to_stkI(dst, tmp);
8469 %}
8470 %}
8471
8472 instruct convD2I_reg(iRegI dst, regD src) %{
8473 predicate(UseVIS >= 3);
8474 match(Set dst (ConvD2I src));
8475 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8476 expand %{
8477 regF tmp;
8478 convD2I_helper(tmp, src);
8479 MoveF2I_reg_reg(dst, tmp);
8480 %}
8481 %}
8482
8483
8484 // Convert a double to a long in a double register.
8485 // If the double is a NAN, stuff a zero in instead.
8486 instruct convD2L_helper(regD dst, regD src, flagsRegF0 fcc0) %{
8487 effect(DEF dst, USE src, KILL fcc0);
8488 format %{ "FCMPd fcc0,$src,$src\t! check for NAN\n\t"
8489 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8490 "FDTOX $src,$dst\t! convert in delay slot\n\t"
8491 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8492 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8493 "skip:" %}
8494 ins_encode(form_d2l_helper(src,dst));
8495 ins_pipe(fcvtD2L);
8496 %}
8497
8498 instruct convD2L_stk(stackSlotL dst, regD src) %{
8499 match(Set dst (ConvD2L src));
8500 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8501 expand %{
8502 regD tmp;
8503 convD2L_helper(tmp, src);
8504 regD_to_stkL(dst, tmp);
8505 %}
8506 %}
8507
8508 instruct convD2L_reg(iRegL dst, regD src) %{
8509 predicate(UseVIS >= 3);
8510 match(Set dst (ConvD2L src));
8511 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8512 expand %{
8513 regD tmp;
8514 convD2L_helper(tmp, src);
8515 MoveD2L_reg_reg(dst, tmp);
8516 %}
8517 %}
8518
8519
8520 instruct convF2D_reg(regD dst, regF src) %{
8521 match(Set dst (ConvF2D src));
8522 format %{ "FSTOD $src,$dst" %}
8523 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fstod_opf);
8524 ins_encode(form3_opf_rs2F_rdD(src, dst));
8525 ins_pipe(fcvtF2D);
8526 %}
8527
8528
8529 // Convert a float to an int in a float register.
8530 // If the float is a NAN, stuff a zero in instead.
8531 instruct convF2I_helper(regF dst, regF src, flagsRegF0 fcc0) %{
8532 effect(DEF dst, USE src, KILL fcc0);
8533 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8534 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8535 "FSTOI $src,$dst\t! convert in delay slot\n\t"
8536 "FITOS $dst,$dst\t! change NaN/max-int to valid float\n\t"
8537 "FSUBs $dst,$dst,$dst\t! cleared only if nan\n"
8538 "skip:" %}
8539 ins_encode(form_f2i_helper(src,dst));
8540 ins_pipe(fcvtF2I);
8541 %}
8542
8543 instruct convF2I_stk(stackSlotI dst, regF src) %{
8544 match(Set dst (ConvF2I src));
8545 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8546 expand %{
8547 regF tmp;
8548 convF2I_helper(tmp, src);
8549 regF_to_stkI(dst, tmp);
8550 %}
8551 %}
8552
8553 instruct convF2I_reg(iRegI dst, regF src) %{
8554 predicate(UseVIS >= 3);
8555 match(Set dst (ConvF2I src));
8556 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8557 expand %{
8558 regF tmp;
8559 convF2I_helper(tmp, src);
8560 MoveF2I_reg_reg(dst, tmp);
8561 %}
8562 %}
8563
8564
8565 // Convert a float to a long in a float register.
8566 // If the float is a NAN, stuff a zero in instead.
8567 instruct convF2L_helper(regD dst, regF src, flagsRegF0 fcc0) %{
8568 effect(DEF dst, USE src, KILL fcc0);
8569 format %{ "FCMPs fcc0,$src,$src\t! check for NAN\n\t"
8570 "FBO,pt fcc0,skip\t! branch on ordered, predict taken\n\t"
8571 "FSTOX $src,$dst\t! convert in delay slot\n\t"
8572 "FXTOD $dst,$dst\t! change NaN/max-long to valid double\n\t"
8573 "FSUBd $dst,$dst,$dst\t! cleared only if nan\n"
8574 "skip:" %}
8575 ins_encode(form_f2l_helper(src,dst));
8576 ins_pipe(fcvtF2L);
8577 %}
8578
8579 instruct convF2L_stk(stackSlotL dst, regF src) %{
8580 match(Set dst (ConvF2L src));
8581 ins_cost(DEFAULT_COST*2 + MEMORY_REF_COST*2 + BRANCH_COST);
8582 expand %{
8583 regD tmp;
8584 convF2L_helper(tmp, src);
8585 regD_to_stkL(dst, tmp);
8586 %}
8587 %}
8588
8589 instruct convF2L_reg(iRegL dst, regF src) %{
8590 predicate(UseVIS >= 3);
8591 match(Set dst (ConvF2L src));
8592 ins_cost(DEFAULT_COST*2 + BRANCH_COST);
8593 expand %{
8594 regD tmp;
8595 convF2L_helper(tmp, src);
8596 MoveD2L_reg_reg(dst, tmp);
8597 %}
8598 %}
8599
8600
8601 instruct convI2D_helper(regD dst, regF tmp) %{
8602 effect(USE tmp, DEF dst);
8603 format %{ "FITOD $tmp,$dst" %}
8604 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8605 ins_encode(form3_opf_rs2F_rdD(tmp, dst));
8606 ins_pipe(fcvtI2D);
8607 %}
8608
8609 instruct convI2D_stk(stackSlotI src, regD dst) %{
8610 match(Set dst (ConvI2D src));
8611 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8612 expand %{
8613 regF tmp;
8614 stkI_to_regF(tmp, src);
8615 convI2D_helper(dst, tmp);
8616 %}
8617 %}
8618
8619 instruct convI2D_reg(regD_low dst, iRegI src) %{
8620 predicate(UseVIS >= 3);
8621 match(Set dst (ConvI2D src));
8622 expand %{
8623 regF tmp;
8624 MoveI2F_reg_reg(tmp, src);
8625 convI2D_helper(dst, tmp);
8626 %}
8627 %}
8628
8629 instruct convI2D_mem(regD_low dst, memory mem) %{
8630 match(Set dst (ConvI2D (LoadI mem)));
8631 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8632 size(8);
8633 format %{ "LDF $mem,$dst\n\t"
8634 "FITOD $dst,$dst" %}
8635 opcode(Assembler::ldf_op3, Assembler::fitod_opf);
8636 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8637 ins_pipe(floadF_mem);
8638 %}
8639
8640
8641 instruct convI2F_helper(regF dst, regF tmp) %{
8642 effect(DEF dst, USE tmp);
8643 format %{ "FITOS $tmp,$dst" %}
8644 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitos_opf);
8645 ins_encode(form3_opf_rs2F_rdF(tmp, dst));
8646 ins_pipe(fcvtI2F);
8647 %}
8648
8649 instruct convI2F_stk(regF dst, stackSlotI src) %{
8650 match(Set dst (ConvI2F src));
8651 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8652 expand %{
8653 regF tmp;
8654 stkI_to_regF(tmp,src);
8655 convI2F_helper(dst, tmp);
8656 %}
8657 %}
8658
8659 instruct convI2F_reg(regF dst, iRegI src) %{
8660 predicate(UseVIS >= 3);
8661 match(Set dst (ConvI2F src));
8662 ins_cost(DEFAULT_COST);
8663 expand %{
8664 regF tmp;
8665 MoveI2F_reg_reg(tmp, src);
8666 convI2F_helper(dst, tmp);
8667 %}
8668 %}
8669
8670 instruct convI2F_mem( regF dst, memory mem ) %{
8671 match(Set dst (ConvI2F (LoadI mem)));
8672 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8673 size(8);
8674 format %{ "LDF $mem,$dst\n\t"
8675 "FITOS $dst,$dst" %}
8676 opcode(Assembler::ldf_op3, Assembler::fitos_opf);
8677 ins_encode(simple_form3_mem_reg( mem, dst ), form3_convI2F(dst, dst));
8678 ins_pipe(floadF_mem);
8679 %}
8680
8681
8682 instruct convI2L_reg(iRegL dst, iRegI src) %{
8683 match(Set dst (ConvI2L src));
8684 size(4);
8685 format %{ "SRA $src,0,$dst\t! int->long" %}
8686 opcode(Assembler::sra_op3, Assembler::arith_op);
8687 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8688 ins_pipe(ialu_reg_reg);
8689 %}
8690
8691 // Zero-extend convert int to long
8692 instruct convI2L_reg_zex(iRegL dst, iRegI src, immL_32bits mask ) %{
8693 match(Set dst (AndL (ConvI2L src) mask) );
8694 size(4);
8695 format %{ "SRL $src,0,$dst\t! zero-extend int to long" %}
8696 opcode(Assembler::srl_op3, Assembler::arith_op);
8697 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8698 ins_pipe(ialu_reg_reg);
8699 %}
8700
8701 // Zero-extend long
8702 instruct zerox_long(iRegL dst, iRegL src, immL_32bits mask ) %{
8703 match(Set dst (AndL src mask) );
8704 size(4);
8705 format %{ "SRL $src,0,$dst\t! zero-extend long" %}
8706 opcode(Assembler::srl_op3, Assembler::arith_op);
8707 ins_encode( form3_rs1_rs2_rd( src, R_G0, dst ) );
8708 ins_pipe(ialu_reg_reg);
8709 %}
8710
8711
8712 //-----------
8713 // Long to Double conversion using V8 opcodes.
8714 // Still useful because cheetah traps and becomes
8715 // amazingly slow for some common numbers.
8716
8717 // Magic constant, 0x43300000
8718 instruct loadConI_x43300000(iRegI dst) %{
8719 effect(DEF dst);
8720 size(4);
8721 format %{ "SETHI HI(0x43300000),$dst\t! 2^52" %}
8722 ins_encode(SetHi22(0x43300000, dst));
8723 ins_pipe(ialu_none);
8724 %}
8725
8726 // Magic constant, 0x41f00000
8727 instruct loadConI_x41f00000(iRegI dst) %{
8728 effect(DEF dst);
8729 size(4);
8730 format %{ "SETHI HI(0x41f00000),$dst\t! 2^32" %}
8731 ins_encode(SetHi22(0x41f00000, dst));
8732 ins_pipe(ialu_none);
8733 %}
8734
8735 // Construct a double from two float halves
8736 instruct regDHi_regDLo_to_regD(regD_low dst, regD_low src1, regD_low src2) %{
8737 effect(DEF dst, USE src1, USE src2);
8738 size(8);
8739 format %{ "FMOVS $src1.hi,$dst.hi\n\t"
8740 "FMOVS $src2.lo,$dst.lo" %}
8741 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmovs_opf);
8742 ins_encode(form3_opf_rs2D_hi_rdD_hi(src1, dst), form3_opf_rs2D_lo_rdD_lo(src2, dst));
8743 ins_pipe(faddD_reg_reg);
8744 %}
8745
8746 // Convert integer in high half of a double register (in the lower half of
8747 // the double register file) to double
8748 instruct convI2D_regDHi_regD(regD dst, regD_low src) %{
8749 effect(DEF dst, USE src);
8750 size(4);
8751 format %{ "FITOD $src,$dst" %}
8752 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fitod_opf);
8753 ins_encode(form3_opf_rs2D_rdD(src, dst));
8754 ins_pipe(fcvtLHi2D);
8755 %}
8756
8757 // Add float double precision
8758 instruct addD_regD_regD(regD dst, regD src1, regD src2) %{
8759 effect(DEF dst, USE src1, USE src2);
8760 size(4);
8761 format %{ "FADDD $src1,$src2,$dst" %}
8762 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::faddd_opf);
8763 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8764 ins_pipe(faddD_reg_reg);
8765 %}
8766
8767 // Sub float double precision
8768 instruct subD_regD_regD(regD dst, regD src1, regD src2) %{
8769 effect(DEF dst, USE src1, USE src2);
8770 size(4);
8771 format %{ "FSUBD $src1,$src2,$dst" %}
8772 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fsubd_opf);
8773 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8774 ins_pipe(faddD_reg_reg);
8775 %}
8776
8777 // Mul float double precision
8778 instruct mulD_regD_regD(regD dst, regD src1, regD src2) %{
8779 effect(DEF dst, USE src1, USE src2);
8780 size(4);
8781 format %{ "FMULD $src1,$src2,$dst" %}
8782 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fmuld_opf);
8783 ins_encode(form3_opf_rs1D_rs2D_rdD(src1, src2, dst));
8784 ins_pipe(fmulD_reg_reg);
8785 %}
8786
8787 instruct convL2D_reg_slow_fxtof(regD dst, stackSlotL src) %{
8788 match(Set dst (ConvL2D src));
8789 ins_cost(DEFAULT_COST*8 + MEMORY_REF_COST*6);
8790
8791 expand %{
8792 regD_low tmpsrc;
8793 iRegI ix43300000;
8794 iRegI ix41f00000;
8795 stackSlotL lx43300000;
8796 stackSlotL lx41f00000;
8797 regD_low dx43300000;
8798 regD dx41f00000;
8799 regD tmp1;
8800 regD_low tmp2;
8801 regD tmp3;
8802 regD tmp4;
8803
8804 stkL_to_regD(tmpsrc, src);
8805
8806 loadConI_x43300000(ix43300000);
8807 loadConI_x41f00000(ix41f00000);
8808 regI_to_stkLHi(lx43300000, ix43300000);
8809 regI_to_stkLHi(lx41f00000, ix41f00000);
8810 stkL_to_regD(dx43300000, lx43300000);
8811 stkL_to_regD(dx41f00000, lx41f00000);
8812
8813 convI2D_regDHi_regD(tmp1, tmpsrc);
8814 regDHi_regDLo_to_regD(tmp2, dx43300000, tmpsrc);
8815 subD_regD_regD(tmp3, tmp2, dx43300000);
8816 mulD_regD_regD(tmp4, tmp1, dx41f00000);
8817 addD_regD_regD(dst, tmp3, tmp4);
8818 %}
8819 %}
8820
8821 // Long to Double conversion using fast fxtof
8822 instruct convL2D_helper(regD dst, regD tmp) %{
8823 effect(DEF dst, USE tmp);
8824 size(4);
8825 format %{ "FXTOD $tmp,$dst" %}
8826 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtod_opf);
8827 ins_encode(form3_opf_rs2D_rdD(tmp, dst));
8828 ins_pipe(fcvtL2D);
8829 %}
8830
8831 instruct convL2D_stk_fast_fxtof(regD dst, stackSlotL src) %{
8832 predicate(VM_Version::has_fast_fxtof());
8833 match(Set dst (ConvL2D src));
8834 ins_cost(DEFAULT_COST + 3 * MEMORY_REF_COST);
8835 expand %{
8836 regD tmp;
8837 stkL_to_regD(tmp, src);
8838 convL2D_helper(dst, tmp);
8839 %}
8840 %}
8841
8842 instruct convL2D_reg(regD dst, iRegL src) %{
8843 predicate(UseVIS >= 3);
8844 match(Set dst (ConvL2D src));
8845 expand %{
8846 regD tmp;
8847 MoveL2D_reg_reg(tmp, src);
8848 convL2D_helper(dst, tmp);
8849 %}
8850 %}
8851
8852 // Long to Float conversion using fast fxtof
8853 instruct convL2F_helper(regF dst, regD tmp) %{
8854 effect(DEF dst, USE tmp);
8855 size(4);
8856 format %{ "FXTOS $tmp,$dst" %}
8857 opcode(Assembler::fpop1_op3, Assembler::arith_op, Assembler::fxtos_opf);
8858 ins_encode(form3_opf_rs2D_rdF(tmp, dst));
8859 ins_pipe(fcvtL2F);
8860 %}
8861
8862 instruct convL2F_stk_fast_fxtof(regF dst, stackSlotL src) %{
8863 match(Set dst (ConvL2F src));
8864 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
8865 expand %{
8866 regD tmp;
8867 stkL_to_regD(tmp, src);
8868 convL2F_helper(dst, tmp);
8869 %}
8870 %}
8871
8872 instruct convL2F_reg(regF dst, iRegL src) %{
8873 predicate(UseVIS >= 3);
8874 match(Set dst (ConvL2F src));
8875 ins_cost(DEFAULT_COST);
8876 expand %{
8877 regD tmp;
8878 MoveL2D_reg_reg(tmp, src);
8879 convL2F_helper(dst, tmp);
8880 %}
8881 %}
8882
8883 //-----------
8884
8885 instruct convL2I_reg(iRegI dst, iRegL src) %{
8886 match(Set dst (ConvL2I src));
8887 #ifndef _LP64
8888 format %{ "MOV $src.lo,$dst\t! long->int" %}
8889 ins_encode( form3_g0_rs2_rd_move_lo2( src, dst ) );
8890 ins_pipe(ialu_move_reg_I_to_L);
8891 #else
8892 size(4);
8893 format %{ "SRA $src,R_G0,$dst\t! long->int" %}
8894 ins_encode( form3_rs1_rd_signextend_lo1( src, dst ) );
8895 ins_pipe(ialu_reg);
8896 #endif
8897 %}
8898
8899 // Register Shift Right Immediate
8900 instruct shrL_reg_imm6_L2I(iRegI dst, iRegL src, immI_32_63 cnt) %{
8901 match(Set dst (ConvL2I (RShiftL src cnt)));
8902
8903 size(4);
8904 format %{ "SRAX $src,$cnt,$dst" %}
8905 opcode(Assembler::srax_op3, Assembler::arith_op);
8906 ins_encode( form3_sd_rs1_imm6_rd( src, cnt, dst ) );
8907 ins_pipe(ialu_reg_imm);
8908 %}
8909
8910 //----------Control Flow Instructions------------------------------------------
8911 // Compare Instructions
8912 // Compare Integers
8913 instruct compI_iReg(flagsReg icc, iRegI op1, iRegI op2) %{
8914 match(Set icc (CmpI op1 op2));
8915 effect( DEF icc, USE op1, USE op2 );
8916
8917 size(4);
8918 format %{ "CMP $op1,$op2" %}
8919 opcode(Assembler::subcc_op3, Assembler::arith_op);
8920 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8921 ins_pipe(ialu_cconly_reg_reg);
8922 %}
8923
8924 instruct compU_iReg(flagsRegU icc, iRegI op1, iRegI op2) %{
8925 match(Set icc (CmpU op1 op2));
8926
8927 size(4);
8928 format %{ "CMP $op1,$op2\t! unsigned" %}
8929 opcode(Assembler::subcc_op3, Assembler::arith_op);
8930 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8931 ins_pipe(ialu_cconly_reg_reg);
8932 %}
8933
8934 instruct compI_iReg_imm13(flagsReg icc, iRegI op1, immI13 op2) %{
8935 match(Set icc (CmpI op1 op2));
8936 effect( DEF icc, USE op1 );
8937
8938 size(4);
8939 format %{ "CMP $op1,$op2" %}
8940 opcode(Assembler::subcc_op3, Assembler::arith_op);
8941 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8942 ins_pipe(ialu_cconly_reg_imm);
8943 %}
8944
8945 instruct testI_reg_reg( flagsReg icc, iRegI op1, iRegI op2, immI0 zero ) %{
8946 match(Set icc (CmpI (AndI op1 op2) zero));
8947
8948 size(4);
8949 format %{ "BTST $op2,$op1" %}
8950 opcode(Assembler::andcc_op3, Assembler::arith_op);
8951 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8952 ins_pipe(ialu_cconly_reg_reg_zero);
8953 %}
8954
8955 instruct testI_reg_imm( flagsReg icc, iRegI op1, immI13 op2, immI0 zero ) %{
8956 match(Set icc (CmpI (AndI op1 op2) zero));
8957
8958 size(4);
8959 format %{ "BTST $op2,$op1" %}
8960 opcode(Assembler::andcc_op3, Assembler::arith_op);
8961 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
8962 ins_pipe(ialu_cconly_reg_imm_zero);
8963 %}
8964
8965 instruct compL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2 ) %{
8966 match(Set xcc (CmpL op1 op2));
8967 effect( DEF xcc, USE op1, USE op2 );
8968
8969 size(4);
8970 format %{ "CMP $op1,$op2\t\t! long" %}
8971 opcode(Assembler::subcc_op3, Assembler::arith_op);
8972 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8973 ins_pipe(ialu_cconly_reg_reg);
8974 %}
8975
8976 instruct compL_reg_con(flagsRegL xcc, iRegL op1, immL13 con) %{
8977 match(Set xcc (CmpL op1 con));
8978 effect( DEF xcc, USE op1, USE con );
8979
8980 size(4);
8981 format %{ "CMP $op1,$con\t\t! long" %}
8982 opcode(Assembler::subcc_op3, Assembler::arith_op);
8983 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
8984 ins_pipe(ialu_cconly_reg_reg);
8985 %}
8986
8987 instruct testL_reg_reg(flagsRegL xcc, iRegL op1, iRegL op2, immL0 zero) %{
8988 match(Set xcc (CmpL (AndL op1 op2) zero));
8989 effect( DEF xcc, USE op1, USE op2 );
8990
8991 size(4);
8992 format %{ "BTST $op1,$op2\t\t! long" %}
8993 opcode(Assembler::andcc_op3, Assembler::arith_op);
8994 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
8995 ins_pipe(ialu_cconly_reg_reg);
8996 %}
8997
8998 // useful for checking the alignment of a pointer:
8999 instruct testL_reg_con(flagsRegL xcc, iRegL op1, immL13 con, immL0 zero) %{
9000 match(Set xcc (CmpL (AndL op1 con) zero));
9001 effect( DEF xcc, USE op1, USE con );
9002
9003 size(4);
9004 format %{ "BTST $op1,$con\t\t! long" %}
9005 opcode(Assembler::andcc_op3, Assembler::arith_op);
9006 ins_encode( form3_rs1_simm13_rd( op1, con, R_G0 ) );
9007 ins_pipe(ialu_cconly_reg_reg);
9008 %}
9009
9010 instruct compU_iReg_imm13(flagsRegU icc, iRegI op1, immU12 op2 ) %{
9011 match(Set icc (CmpU op1 op2));
9012
9013 size(4);
9014 format %{ "CMP $op1,$op2\t! unsigned" %}
9015 opcode(Assembler::subcc_op3, Assembler::arith_op);
9016 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9017 ins_pipe(ialu_cconly_reg_imm);
9018 %}
9019
9020 // Compare Pointers
9021 instruct compP_iRegP(flagsRegP pcc, iRegP op1, iRegP op2 ) %{
9022 match(Set pcc (CmpP op1 op2));
9023
9024 size(4);
9025 format %{ "CMP $op1,$op2\t! ptr" %}
9026 opcode(Assembler::subcc_op3, Assembler::arith_op);
9027 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9028 ins_pipe(ialu_cconly_reg_reg);
9029 %}
9030
9031 instruct compP_iRegP_imm13(flagsRegP pcc, iRegP op1, immP13 op2 ) %{
9032 match(Set pcc (CmpP op1 op2));
9033
9034 size(4);
9035 format %{ "CMP $op1,$op2\t! ptr" %}
9036 opcode(Assembler::subcc_op3, Assembler::arith_op);
9037 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9038 ins_pipe(ialu_cconly_reg_imm);
9039 %}
9040
9041 // Compare Narrow oops
9042 instruct compN_iRegN(flagsReg icc, iRegN op1, iRegN op2 ) %{
9043 match(Set icc (CmpN op1 op2));
9044
9045 size(4);
9046 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9047 opcode(Assembler::subcc_op3, Assembler::arith_op);
9048 ins_encode( form3_rs1_rs2_rd( op1, op2, R_G0 ) );
9049 ins_pipe(ialu_cconly_reg_reg);
9050 %}
9051
9052 instruct compN_iRegN_immN0(flagsReg icc, iRegN op1, immN0 op2 ) %{
9053 match(Set icc (CmpN op1 op2));
9054
9055 size(4);
9056 format %{ "CMP $op1,$op2\t! compressed ptr" %}
9057 opcode(Assembler::subcc_op3, Assembler::arith_op);
9058 ins_encode( form3_rs1_simm13_rd( op1, op2, R_G0 ) );
9059 ins_pipe(ialu_cconly_reg_imm);
9060 %}
9061
9062 //----------Max and Min--------------------------------------------------------
9063 // Min Instructions
9064 // Conditional move for min
9065 instruct cmovI_reg_lt( iRegI op2, iRegI op1, flagsReg icc ) %{
9066 effect( USE_DEF op2, USE op1, USE icc );
9067
9068 size(4);
9069 format %{ "MOVlt icc,$op1,$op2\t! min" %}
9070 opcode(Assembler::less);
9071 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9072 ins_pipe(ialu_reg_flags);
9073 %}
9074
9075 // Min Register with Register.
9076 instruct minI_eReg(iRegI op1, iRegI op2) %{
9077 match(Set op2 (MinI op1 op2));
9078 ins_cost(DEFAULT_COST*2);
9079 expand %{
9080 flagsReg icc;
9081 compI_iReg(icc,op1,op2);
9082 cmovI_reg_lt(op2,op1,icc);
9083 %}
9084 %}
9085
9086 // Max Instructions
9087 // Conditional move for max
9088 instruct cmovI_reg_gt( iRegI op2, iRegI op1, flagsReg icc ) %{
9089 effect( USE_DEF op2, USE op1, USE icc );
9090 format %{ "MOVgt icc,$op1,$op2\t! max" %}
9091 opcode(Assembler::greater);
9092 ins_encode( enc_cmov_reg_minmax(op2,op1) );
9093 ins_pipe(ialu_reg_flags);
9094 %}
9095
9096 // Max Register with Register
9097 instruct maxI_eReg(iRegI op1, iRegI op2) %{
9098 match(Set op2 (MaxI op1 op2));
9099 ins_cost(DEFAULT_COST*2);
9100 expand %{
9101 flagsReg icc;
9102 compI_iReg(icc,op1,op2);
9103 cmovI_reg_gt(op2,op1,icc);
9104 %}
9105 %}
9106
9107
9108 //----------Float Compares----------------------------------------------------
9109 // Compare floating, generate condition code
9110 instruct cmpF_cc(flagsRegF fcc, regF src1, regF src2) %{
9111 match(Set fcc (CmpF src1 src2));
9112
9113 size(4);
9114 format %{ "FCMPs $fcc,$src1,$src2" %}
9115 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmps_opf);
9116 ins_encode( form3_opf_rs1F_rs2F_fcc( src1, src2, fcc ) );
9117 ins_pipe(faddF_fcc_reg_reg_zero);
9118 %}
9119
9120 instruct cmpD_cc(flagsRegF fcc, regD src1, regD src2) %{
9121 match(Set fcc (CmpD src1 src2));
9122
9123 size(4);
9124 format %{ "FCMPd $fcc,$src1,$src2" %}
9125 opcode(Assembler::fpop2_op3, Assembler::arith_op, Assembler::fcmpd_opf);
9126 ins_encode( form3_opf_rs1D_rs2D_fcc( src1, src2, fcc ) );
9127 ins_pipe(faddD_fcc_reg_reg_zero);
9128 %}
9129
9130
9131 // Compare floating, generate -1,0,1
9132 instruct cmpF_reg(iRegI dst, regF src1, regF src2, flagsRegF0 fcc0) %{
9133 match(Set dst (CmpF3 src1 src2));
9134 effect(KILL fcc0);
9135 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9136 format %{ "fcmpl $dst,$src1,$src2" %}
9137 // Primary = float
9138 opcode( true );
9139 ins_encode( floating_cmp( dst, src1, src2 ) );
9140 ins_pipe( floating_cmp );
9141 %}
9142
9143 instruct cmpD_reg(iRegI dst, regD src1, regD src2, flagsRegF0 fcc0) %{
9144 match(Set dst (CmpD3 src1 src2));
9145 effect(KILL fcc0);
9146 ins_cost(DEFAULT_COST*3+BRANCH_COST*3);
9147 format %{ "dcmpl $dst,$src1,$src2" %}
9148 // Primary = double (not float)
9149 opcode( false );
9150 ins_encode( floating_cmp( dst, src1, src2 ) );
9151 ins_pipe( floating_cmp );
9152 %}
9153
9154 //----------Branches---------------------------------------------------------
9155 // Jump
9156 // (compare 'operand indIndex' and 'instruct addP_reg_reg' above)
9157 instruct jumpXtnd(iRegX switch_val, o7RegI table) %{
9158 match(Jump switch_val);
9159 effect(TEMP table);
9160
9161 ins_cost(350);
9162
9163 format %{ "ADD $constanttablebase, $constantoffset, O7\n\t"
9164 "LD [O7 + $switch_val], O7\n\t"
9165 "JUMP O7" %}
9166 ins_encode %{
9167 // Calculate table address into a register.
9168 Register table_reg;
9169 Register label_reg = O7;
9170 // If we are calculating the size of this instruction don't trust
9171 // zero offsets because they might change when
9172 // MachConstantBaseNode decides to optimize the constant table
9173 // base.
9174 if ((constant_offset() == 0) && !Compile::current()->in_scratch_emit_size()) {
9175 table_reg = $constanttablebase;
9176 } else {
9177 table_reg = O7;
9178 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset, O7);
9179 __ add($constanttablebase, con_offset, table_reg);
9180 }
9181
9182 // Jump to base address + switch value
9183 __ ld_ptr(table_reg, $switch_val$$Register, label_reg);
9184 __ jmp(label_reg, G0);
9185 __ delayed()->nop();
9186 %}
9187 ins_pipe(ialu_reg_reg);
9188 %}
9189
9190 // Direct Branch. Use V8 version with longer range.
9191 instruct branch(label labl) %{
9192 match(Goto);
9193 effect(USE labl);
9194
9195 size(8);
9196 ins_cost(BRANCH_COST);
9197 format %{ "BA $labl" %}
9198 ins_encode %{
9199 Label* L = $labl$$label;
9200 __ ba(*L);
9201 __ delayed()->nop();
9202 %}
9203 ins_avoid_back_to_back(AVOID_BEFORE);
9204 ins_pipe(br);
9205 %}
9206
9207 // Direct Branch, short with no delay slot
9208 instruct branch_short(label labl) %{
9209 match(Goto);
9210 predicate(UseCBCond);
9211 effect(USE labl);
9212
9213 size(4);
9214 ins_cost(BRANCH_COST);
9215 format %{ "BA $labl\t! short branch" %}
9216 ins_encode %{
9217 Label* L = $labl$$label;
9218 assert(__ use_cbcond(*L), "back to back cbcond");
9219 __ ba_short(*L);
9220 %}
9221 ins_short_branch(1);
9222 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9223 ins_pipe(cbcond_reg_imm);
9224 %}
9225
9226 // Conditional Direct Branch
9227 instruct branchCon(cmpOp cmp, flagsReg icc, label labl) %{
9228 match(If cmp icc);
9229 effect(USE labl);
9230
9231 size(8);
9232 ins_cost(BRANCH_COST);
9233 format %{ "BP$cmp $icc,$labl" %}
9234 // Prim = bits 24-22, Secnd = bits 31-30
9235 ins_encode( enc_bp( labl, cmp, icc ) );
9236 ins_avoid_back_to_back(AVOID_BEFORE);
9237 ins_pipe(br_cc);
9238 %}
9239
9240 instruct branchConU(cmpOpU cmp, flagsRegU icc, label labl) %{
9241 match(If cmp icc);
9242 effect(USE labl);
9243
9244 ins_cost(BRANCH_COST);
9245 format %{ "BP$cmp $icc,$labl" %}
9246 // Prim = bits 24-22, Secnd = bits 31-30
9247 ins_encode( enc_bp( labl, cmp, icc ) );
9248 ins_avoid_back_to_back(AVOID_BEFORE);
9249 ins_pipe(br_cc);
9250 %}
9251
9252 instruct branchConP(cmpOpP cmp, flagsRegP pcc, label labl) %{
9253 match(If cmp pcc);
9254 effect(USE labl);
9255
9256 size(8);
9257 ins_cost(BRANCH_COST);
9258 format %{ "BP$cmp $pcc,$labl" %}
9259 ins_encode %{
9260 Label* L = $labl$$label;
9261 Assembler::Predict predict_taken =
9262 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9263
9264 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9265 __ delayed()->nop();
9266 %}
9267 ins_avoid_back_to_back(AVOID_BEFORE);
9268 ins_pipe(br_cc);
9269 %}
9270
9271 instruct branchConF(cmpOpF cmp, flagsRegF fcc, label labl) %{
9272 match(If cmp fcc);
9273 effect(USE labl);
9274
9275 size(8);
9276 ins_cost(BRANCH_COST);
9277 format %{ "FBP$cmp $fcc,$labl" %}
9278 ins_encode %{
9279 Label* L = $labl$$label;
9280 Assembler::Predict predict_taken =
9281 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9282
9283 __ fbp( (Assembler::Condition)($cmp$$cmpcode), false, (Assembler::CC)($fcc$$reg), predict_taken, *L);
9284 __ delayed()->nop();
9285 %}
9286 ins_avoid_back_to_back(AVOID_BEFORE);
9287 ins_pipe(br_fcc);
9288 %}
9289
9290 instruct branchLoopEnd(cmpOp cmp, flagsReg icc, label labl) %{
9291 match(CountedLoopEnd cmp icc);
9292 effect(USE labl);
9293
9294 size(8);
9295 ins_cost(BRANCH_COST);
9296 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9297 // Prim = bits 24-22, Secnd = bits 31-30
9298 ins_encode( enc_bp( labl, cmp, icc ) );
9299 ins_avoid_back_to_back(AVOID_BEFORE);
9300 ins_pipe(br_cc);
9301 %}
9302
9303 instruct branchLoopEndU(cmpOpU cmp, flagsRegU icc, label labl) %{
9304 match(CountedLoopEnd cmp icc);
9305 effect(USE labl);
9306
9307 size(8);
9308 ins_cost(BRANCH_COST);
9309 format %{ "BP$cmp $icc,$labl\t! Loop end" %}
9310 // Prim = bits 24-22, Secnd = bits 31-30
9311 ins_encode( enc_bp( labl, cmp, icc ) );
9312 ins_avoid_back_to_back(AVOID_BEFORE);
9313 ins_pipe(br_cc);
9314 %}
9315
9316 // Compare and branch instructions
9317 instruct cmpI_reg_branch(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9318 match(If cmp (CmpI op1 op2));
9319 effect(USE labl, KILL icc);
9320
9321 size(12);
9322 ins_cost(BRANCH_COST);
9323 format %{ "CMP $op1,$op2\t! int\n\t"
9324 "BP$cmp $labl" %}
9325 ins_encode %{
9326 Label* L = $labl$$label;
9327 Assembler::Predict predict_taken =
9328 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9329 __ cmp($op1$$Register, $op2$$Register);
9330 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9331 __ delayed()->nop();
9332 %}
9333 ins_pipe(cmp_br_reg_reg);
9334 %}
9335
9336 instruct cmpI_imm_branch(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9337 match(If cmp (CmpI op1 op2));
9338 effect(USE labl, KILL icc);
9339
9340 size(12);
9341 ins_cost(BRANCH_COST);
9342 format %{ "CMP $op1,$op2\t! int\n\t"
9343 "BP$cmp $labl" %}
9344 ins_encode %{
9345 Label* L = $labl$$label;
9346 Assembler::Predict predict_taken =
9347 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9348 __ cmp($op1$$Register, $op2$$constant);
9349 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9350 __ delayed()->nop();
9351 %}
9352 ins_pipe(cmp_br_reg_imm);
9353 %}
9354
9355 instruct cmpU_reg_branch(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9356 match(If cmp (CmpU op1 op2));
9357 effect(USE labl, KILL icc);
9358
9359 size(12);
9360 ins_cost(BRANCH_COST);
9361 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9362 "BP$cmp $labl" %}
9363 ins_encode %{
9364 Label* L = $labl$$label;
9365 Assembler::Predict predict_taken =
9366 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9367 __ cmp($op1$$Register, $op2$$Register);
9368 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9369 __ delayed()->nop();
9370 %}
9371 ins_pipe(cmp_br_reg_reg);
9372 %}
9373
9374 instruct cmpU_imm_branch(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9375 match(If cmp (CmpU op1 op2));
9376 effect(USE labl, KILL icc);
9377
9378 size(12);
9379 ins_cost(BRANCH_COST);
9380 format %{ "CMP $op1,$op2\t! unsigned\n\t"
9381 "BP$cmp $labl" %}
9382 ins_encode %{
9383 Label* L = $labl$$label;
9384 Assembler::Predict predict_taken =
9385 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9386 __ cmp($op1$$Register, $op2$$constant);
9387 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9388 __ delayed()->nop();
9389 %}
9390 ins_pipe(cmp_br_reg_imm);
9391 %}
9392
9393 instruct cmpL_reg_branch(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9394 match(If cmp (CmpL op1 op2));
9395 effect(USE labl, KILL xcc);
9396
9397 size(12);
9398 ins_cost(BRANCH_COST);
9399 format %{ "CMP $op1,$op2\t! long\n\t"
9400 "BP$cmp $labl" %}
9401 ins_encode %{
9402 Label* L = $labl$$label;
9403 Assembler::Predict predict_taken =
9404 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9405 __ cmp($op1$$Register, $op2$$Register);
9406 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9407 __ delayed()->nop();
9408 %}
9409 ins_pipe(cmp_br_reg_reg);
9410 %}
9411
9412 instruct cmpL_imm_branch(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9413 match(If cmp (CmpL op1 op2));
9414 effect(USE labl, KILL xcc);
9415
9416 size(12);
9417 ins_cost(BRANCH_COST);
9418 format %{ "CMP $op1,$op2\t! long\n\t"
9419 "BP$cmp $labl" %}
9420 ins_encode %{
9421 Label* L = $labl$$label;
9422 Assembler::Predict predict_taken =
9423 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9424 __ cmp($op1$$Register, $op2$$constant);
9425 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9426 __ delayed()->nop();
9427 %}
9428 ins_pipe(cmp_br_reg_imm);
9429 %}
9430
9431 // Compare Pointers and branch
9432 instruct cmpP_reg_branch(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9433 match(If cmp (CmpP op1 op2));
9434 effect(USE labl, KILL pcc);
9435
9436 size(12);
9437 ins_cost(BRANCH_COST);
9438 format %{ "CMP $op1,$op2\t! ptr\n\t"
9439 "B$cmp $labl" %}
9440 ins_encode %{
9441 Label* L = $labl$$label;
9442 Assembler::Predict predict_taken =
9443 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9444 __ cmp($op1$$Register, $op2$$Register);
9445 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9446 __ delayed()->nop();
9447 %}
9448 ins_pipe(cmp_br_reg_reg);
9449 %}
9450
9451 instruct cmpP_null_branch(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9452 match(If cmp (CmpP op1 null));
9453 effect(USE labl, KILL pcc);
9454
9455 size(12);
9456 ins_cost(BRANCH_COST);
9457 format %{ "CMP $op1,0\t! ptr\n\t"
9458 "B$cmp $labl" %}
9459 ins_encode %{
9460 Label* L = $labl$$label;
9461 Assembler::Predict predict_taken =
9462 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9463 __ cmp($op1$$Register, G0);
9464 // bpr() is not used here since it has shorter distance.
9465 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::ptr_cc, predict_taken, *L);
9466 __ delayed()->nop();
9467 %}
9468 ins_pipe(cmp_br_reg_reg);
9469 %}
9470
9471 instruct cmpN_reg_branch(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9472 match(If cmp (CmpN op1 op2));
9473 effect(USE labl, KILL icc);
9474
9475 size(12);
9476 ins_cost(BRANCH_COST);
9477 format %{ "CMP $op1,$op2\t! compressed ptr\n\t"
9478 "BP$cmp $labl" %}
9479 ins_encode %{
9480 Label* L = $labl$$label;
9481 Assembler::Predict predict_taken =
9482 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9483 __ cmp($op1$$Register, $op2$$Register);
9484 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9485 __ delayed()->nop();
9486 %}
9487 ins_pipe(cmp_br_reg_reg);
9488 %}
9489
9490 instruct cmpN_null_branch(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9491 match(If cmp (CmpN op1 null));
9492 effect(USE labl, KILL icc);
9493
9494 size(12);
9495 ins_cost(BRANCH_COST);
9496 format %{ "CMP $op1,0\t! compressed ptr\n\t"
9497 "BP$cmp $labl" %}
9498 ins_encode %{
9499 Label* L = $labl$$label;
9500 Assembler::Predict predict_taken =
9501 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9502 __ cmp($op1$$Register, G0);
9503 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9504 __ delayed()->nop();
9505 %}
9506 ins_pipe(cmp_br_reg_reg);
9507 %}
9508
9509 // Loop back branch
9510 instruct cmpI_reg_branchLoopEnd(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9511 match(CountedLoopEnd cmp (CmpI op1 op2));
9512 effect(USE labl, KILL icc);
9513
9514 size(12);
9515 ins_cost(BRANCH_COST);
9516 format %{ "CMP $op1,$op2\t! int\n\t"
9517 "BP$cmp $labl\t! Loop end" %}
9518 ins_encode %{
9519 Label* L = $labl$$label;
9520 Assembler::Predict predict_taken =
9521 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9522 __ cmp($op1$$Register, $op2$$Register);
9523 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9524 __ delayed()->nop();
9525 %}
9526 ins_pipe(cmp_br_reg_reg);
9527 %}
9528
9529 instruct cmpI_imm_branchLoopEnd(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9530 match(CountedLoopEnd cmp (CmpI op1 op2));
9531 effect(USE labl, KILL icc);
9532
9533 size(12);
9534 ins_cost(BRANCH_COST);
9535 format %{ "CMP $op1,$op2\t! int\n\t"
9536 "BP$cmp $labl\t! Loop end" %}
9537 ins_encode %{
9538 Label* L = $labl$$label;
9539 Assembler::Predict predict_taken =
9540 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9541 __ cmp($op1$$Register, $op2$$constant);
9542 __ bp((Assembler::Condition)($cmp$$cmpcode), false, Assembler::icc, predict_taken, *L);
9543 __ delayed()->nop();
9544 %}
9545 ins_pipe(cmp_br_reg_imm);
9546 %}
9547
9548 // Short compare and branch instructions
9549 instruct cmpI_reg_branch_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9550 match(If cmp (CmpI op1 op2));
9551 predicate(UseCBCond);
9552 effect(USE labl, KILL icc);
9553
9554 size(4);
9555 ins_cost(BRANCH_COST);
9556 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9557 ins_encode %{
9558 Label* L = $labl$$label;
9559 assert(__ use_cbcond(*L), "back to back cbcond");
9560 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9561 %}
9562 ins_short_branch(1);
9563 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9564 ins_pipe(cbcond_reg_reg);
9565 %}
9566
9567 instruct cmpI_imm_branch_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9568 match(If cmp (CmpI op1 op2));
9569 predicate(UseCBCond);
9570 effect(USE labl, KILL icc);
9571
9572 size(4);
9573 ins_cost(BRANCH_COST);
9574 format %{ "CWB$cmp $op1,$op2,$labl\t! int" %}
9575 ins_encode %{
9576 Label* L = $labl$$label;
9577 assert(__ use_cbcond(*L), "back to back cbcond");
9578 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9579 %}
9580 ins_short_branch(1);
9581 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9582 ins_pipe(cbcond_reg_imm);
9583 %}
9584
9585 instruct cmpU_reg_branch_short(cmpOpU cmp, iRegI op1, iRegI op2, label labl, flagsRegU icc) %{
9586 match(If cmp (CmpU op1 op2));
9587 predicate(UseCBCond);
9588 effect(USE labl, KILL icc);
9589
9590 size(4);
9591 ins_cost(BRANCH_COST);
9592 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9593 ins_encode %{
9594 Label* L = $labl$$label;
9595 assert(__ use_cbcond(*L), "back to back cbcond");
9596 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9597 %}
9598 ins_short_branch(1);
9599 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9600 ins_pipe(cbcond_reg_reg);
9601 %}
9602
9603 instruct cmpU_imm_branch_short(cmpOpU cmp, iRegI op1, immI5 op2, label labl, flagsRegU icc) %{
9604 match(If cmp (CmpU op1 op2));
9605 predicate(UseCBCond);
9606 effect(USE labl, KILL icc);
9607
9608 size(4);
9609 ins_cost(BRANCH_COST);
9610 format %{ "CWB$cmp $op1,$op2,$labl\t! unsigned" %}
9611 ins_encode %{
9612 Label* L = $labl$$label;
9613 assert(__ use_cbcond(*L), "back to back cbcond");
9614 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9615 %}
9616 ins_short_branch(1);
9617 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9618 ins_pipe(cbcond_reg_imm);
9619 %}
9620
9621 instruct cmpL_reg_branch_short(cmpOp cmp, iRegL op1, iRegL op2, label labl, flagsRegL xcc) %{
9622 match(If cmp (CmpL op1 op2));
9623 predicate(UseCBCond);
9624 effect(USE labl, KILL xcc);
9625
9626 size(4);
9627 ins_cost(BRANCH_COST);
9628 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9629 ins_encode %{
9630 Label* L = $labl$$label;
9631 assert(__ use_cbcond(*L), "back to back cbcond");
9632 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$Register, *L);
9633 %}
9634 ins_short_branch(1);
9635 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9636 ins_pipe(cbcond_reg_reg);
9637 %}
9638
9639 instruct cmpL_imm_branch_short(cmpOp cmp, iRegL op1, immL5 op2, label labl, flagsRegL xcc) %{
9640 match(If cmp (CmpL op1 op2));
9641 predicate(UseCBCond);
9642 effect(USE labl, KILL xcc);
9643
9644 size(4);
9645 ins_cost(BRANCH_COST);
9646 format %{ "CXB$cmp $op1,$op2,$labl\t! long" %}
9647 ins_encode %{
9648 Label* L = $labl$$label;
9649 assert(__ use_cbcond(*L), "back to back cbcond");
9650 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::xcc, $op1$$Register, $op2$$constant, *L);
9651 %}
9652 ins_short_branch(1);
9653 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9654 ins_pipe(cbcond_reg_imm);
9655 %}
9656
9657 // Compare Pointers and branch
9658 instruct cmpP_reg_branch_short(cmpOpP cmp, iRegP op1, iRegP op2, label labl, flagsRegP pcc) %{
9659 match(If cmp (CmpP op1 op2));
9660 predicate(UseCBCond);
9661 effect(USE labl, KILL pcc);
9662
9663 size(4);
9664 ins_cost(BRANCH_COST);
9665 #ifdef _LP64
9666 format %{ "CXB$cmp $op1,$op2,$labl\t! ptr" %}
9667 #else
9668 format %{ "CWB$cmp $op1,$op2,$labl\t! ptr" %}
9669 #endif
9670 ins_encode %{
9671 Label* L = $labl$$label;
9672 assert(__ use_cbcond(*L), "back to back cbcond");
9673 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, $op2$$Register, *L);
9674 %}
9675 ins_short_branch(1);
9676 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9677 ins_pipe(cbcond_reg_reg);
9678 %}
9679
9680 instruct cmpP_null_branch_short(cmpOpP cmp, iRegP op1, immP0 null, label labl, flagsRegP pcc) %{
9681 match(If cmp (CmpP op1 null));
9682 predicate(UseCBCond);
9683 effect(USE labl, KILL pcc);
9684
9685 size(4);
9686 ins_cost(BRANCH_COST);
9687 #ifdef _LP64
9688 format %{ "CXB$cmp $op1,0,$labl\t! ptr" %}
9689 #else
9690 format %{ "CWB$cmp $op1,0,$labl\t! ptr" %}
9691 #endif
9692 ins_encode %{
9693 Label* L = $labl$$label;
9694 assert(__ use_cbcond(*L), "back to back cbcond");
9695 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::ptr_cc, $op1$$Register, G0, *L);
9696 %}
9697 ins_short_branch(1);
9698 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9699 ins_pipe(cbcond_reg_reg);
9700 %}
9701
9702 instruct cmpN_reg_branch_short(cmpOp cmp, iRegN op1, iRegN op2, label labl, flagsReg icc) %{
9703 match(If cmp (CmpN op1 op2));
9704 predicate(UseCBCond);
9705 effect(USE labl, KILL icc);
9706
9707 size(4);
9708 ins_cost(BRANCH_COST);
9709 format %{ "CWB$cmp $op1,$op2,$labl\t! compressed ptr" %}
9710 ins_encode %{
9711 Label* L = $labl$$label;
9712 assert(__ use_cbcond(*L), "back to back cbcond");
9713 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9714 %}
9715 ins_short_branch(1);
9716 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9717 ins_pipe(cbcond_reg_reg);
9718 %}
9719
9720 instruct cmpN_null_branch_short(cmpOp cmp, iRegN op1, immN0 null, label labl, flagsReg icc) %{
9721 match(If cmp (CmpN op1 null));
9722 predicate(UseCBCond);
9723 effect(USE labl, KILL icc);
9724
9725 size(4);
9726 ins_cost(BRANCH_COST);
9727 format %{ "CWB$cmp $op1,0,$labl\t! compressed ptr" %}
9728 ins_encode %{
9729 Label* L = $labl$$label;
9730 assert(__ use_cbcond(*L), "back to back cbcond");
9731 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, G0, *L);
9732 %}
9733 ins_short_branch(1);
9734 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9735 ins_pipe(cbcond_reg_reg);
9736 %}
9737
9738 // Loop back branch
9739 instruct cmpI_reg_branchLoopEnd_short(cmpOp cmp, iRegI op1, iRegI op2, label labl, flagsReg icc) %{
9740 match(CountedLoopEnd cmp (CmpI op1 op2));
9741 predicate(UseCBCond);
9742 effect(USE labl, KILL icc);
9743
9744 size(4);
9745 ins_cost(BRANCH_COST);
9746 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9747 ins_encode %{
9748 Label* L = $labl$$label;
9749 assert(__ use_cbcond(*L), "back to back cbcond");
9750 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$Register, *L);
9751 %}
9752 ins_short_branch(1);
9753 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9754 ins_pipe(cbcond_reg_reg);
9755 %}
9756
9757 instruct cmpI_imm_branchLoopEnd_short(cmpOp cmp, iRegI op1, immI5 op2, label labl, flagsReg icc) %{
9758 match(CountedLoopEnd cmp (CmpI op1 op2));
9759 predicate(UseCBCond);
9760 effect(USE labl, KILL icc);
9761
9762 size(4);
9763 ins_cost(BRANCH_COST);
9764 format %{ "CWB$cmp $op1,$op2,$labl\t! Loop end" %}
9765 ins_encode %{
9766 Label* L = $labl$$label;
9767 assert(__ use_cbcond(*L), "back to back cbcond");
9768 __ cbcond((Assembler::Condition)($cmp$$cmpcode), Assembler::icc, $op1$$Register, $op2$$constant, *L);
9769 %}
9770 ins_short_branch(1);
9771 ins_avoid_back_to_back(AVOID_BEFORE_AND_AFTER);
9772 ins_pipe(cbcond_reg_imm);
9773 %}
9774
9775 // Branch-on-register tests all 64 bits. We assume that values
9776 // in 64-bit registers always remains zero or sign extended
9777 // unless our code munges the high bits. Interrupts can chop
9778 // the high order bits to zero or sign at any time.
9779 instruct branchCon_regI(cmpOp_reg cmp, iRegI op1, immI0 zero, label labl) %{
9780 match(If cmp (CmpI op1 zero));
9781 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9782 effect(USE labl);
9783
9784 size(8);
9785 ins_cost(BRANCH_COST);
9786 format %{ "BR$cmp $op1,$labl" %}
9787 ins_encode( enc_bpr( labl, cmp, op1 ) );
9788 ins_avoid_back_to_back(AVOID_BEFORE);
9789 ins_pipe(br_reg);
9790 %}
9791
9792 instruct branchCon_regP(cmpOp_reg cmp, iRegP op1, immP0 null, label labl) %{
9793 match(If cmp (CmpP op1 null));
9794 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9795 effect(USE labl);
9796
9797 size(8);
9798 ins_cost(BRANCH_COST);
9799 format %{ "BR$cmp $op1,$labl" %}
9800 ins_encode( enc_bpr( labl, cmp, op1 ) );
9801 ins_avoid_back_to_back(AVOID_BEFORE);
9802 ins_pipe(br_reg);
9803 %}
9804
9805 instruct branchCon_regL(cmpOp_reg cmp, iRegL op1, immL0 zero, label labl) %{
9806 match(If cmp (CmpL op1 zero));
9807 predicate(can_branch_register(_kids[0]->_leaf, _kids[1]->_leaf));
9808 effect(USE labl);
9809
9810 size(8);
9811 ins_cost(BRANCH_COST);
9812 format %{ "BR$cmp $op1,$labl" %}
9813 ins_encode( enc_bpr( labl, cmp, op1 ) );
9814 ins_avoid_back_to_back(AVOID_BEFORE);
9815 ins_pipe(br_reg);
9816 %}
9817
9818
9819 // ============================================================================
9820 // Long Compare
9821 //
9822 // Currently we hold longs in 2 registers. Comparing such values efficiently
9823 // is tricky. The flavor of compare used depends on whether we are testing
9824 // for LT, LE, or EQ. For a simple LT test we can check just the sign bit.
9825 // The GE test is the negated LT test. The LE test can be had by commuting
9826 // the operands (yielding a GE test) and then negating; negate again for the
9827 // GT test. The EQ test is done by ORcc'ing the high and low halves, and the
9828 // NE test is negated from that.
9829
9830 // Due to a shortcoming in the ADLC, it mixes up expressions like:
9831 // (foo (CmpI (CmpL X Y) 0)) and (bar (CmpI (CmpL X 0L) 0)). Note the
9832 // difference between 'Y' and '0L'. The tree-matches for the CmpI sections
9833 // are collapsed internally in the ADLC's dfa-gen code. The match for
9834 // (CmpI (CmpL X Y) 0) is silently replaced with (CmpI (CmpL X 0L) 0) and the
9835 // foo match ends up with the wrong leaf. One fix is to not match both
9836 // reg-reg and reg-zero forms of long-compare. This is unfortunate because
9837 // both forms beat the trinary form of long-compare and both are very useful
9838 // on Intel which has so few registers.
9839
9840 instruct branchCon_long(cmpOp cmp, flagsRegL xcc, label labl) %{
9841 match(If cmp xcc);
9842 effect(USE labl);
9843
9844 size(8);
9845 ins_cost(BRANCH_COST);
9846 format %{ "BP$cmp $xcc,$labl" %}
9847 ins_encode %{
9848 Label* L = $labl$$label;
9849 Assembler::Predict predict_taken =
9850 cbuf.is_backward_branch(*L) ? Assembler::pt : Assembler::pn;
9851
9852 __ bp( (Assembler::Condition)($cmp$$cmpcode), false, Assembler::xcc, predict_taken, *L);
9853 __ delayed()->nop();
9854 %}
9855 ins_avoid_back_to_back(AVOID_BEFORE);
9856 ins_pipe(br_cc);
9857 %}
9858
9859 // Manifest a CmpL3 result in an integer register. Very painful.
9860 // This is the test to avoid.
9861 instruct cmpL3_reg_reg(iRegI dst, iRegL src1, iRegL src2, flagsReg ccr ) %{
9862 match(Set dst (CmpL3 src1 src2) );
9863 effect( KILL ccr );
9864 ins_cost(6*DEFAULT_COST);
9865 size(24);
9866 format %{ "CMP $src1,$src2\t\t! long\n"
9867 "\tBLT,a,pn done\n"
9868 "\tMOV -1,$dst\t! delay slot\n"
9869 "\tBGT,a,pn done\n"
9870 "\tMOV 1,$dst\t! delay slot\n"
9871 "\tCLR $dst\n"
9872 "done:" %}
9873 ins_encode( cmpl_flag(src1,src2,dst) );
9874 ins_pipe(cmpL_reg);
9875 %}
9876
9877 // Conditional move
9878 instruct cmovLL_reg(cmpOp cmp, flagsRegL xcc, iRegL dst, iRegL src) %{
9879 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9880 ins_cost(150);
9881 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9882 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9883 ins_pipe(ialu_reg);
9884 %}
9885
9886 instruct cmovLL_imm(cmpOp cmp, flagsRegL xcc, iRegL dst, immL0 src) %{
9887 match(Set dst (CMoveL (Binary cmp xcc) (Binary dst src)));
9888 ins_cost(140);
9889 format %{ "MOV$cmp $xcc,$src,$dst\t! long" %}
9890 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9891 ins_pipe(ialu_imm);
9892 %}
9893
9894 instruct cmovIL_reg(cmpOp cmp, flagsRegL xcc, iRegI dst, iRegI src) %{
9895 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9896 ins_cost(150);
9897 format %{ "MOV$cmp $xcc,$src,$dst" %}
9898 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9899 ins_pipe(ialu_reg);
9900 %}
9901
9902 instruct cmovIL_imm(cmpOp cmp, flagsRegL xcc, iRegI dst, immI11 src) %{
9903 match(Set dst (CMoveI (Binary cmp xcc) (Binary dst src)));
9904 ins_cost(140);
9905 format %{ "MOV$cmp $xcc,$src,$dst" %}
9906 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9907 ins_pipe(ialu_imm);
9908 %}
9909
9910 instruct cmovNL_reg(cmpOp cmp, flagsRegL xcc, iRegN dst, iRegN src) %{
9911 match(Set dst (CMoveN (Binary cmp xcc) (Binary dst src)));
9912 ins_cost(150);
9913 format %{ "MOV$cmp $xcc,$src,$dst" %}
9914 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9915 ins_pipe(ialu_reg);
9916 %}
9917
9918 instruct cmovPL_reg(cmpOp cmp, flagsRegL xcc, iRegP dst, iRegP src) %{
9919 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9920 ins_cost(150);
9921 format %{ "MOV$cmp $xcc,$src,$dst" %}
9922 ins_encode( enc_cmov_reg(cmp,dst,src, (Assembler::xcc)) );
9923 ins_pipe(ialu_reg);
9924 %}
9925
9926 instruct cmovPL_imm(cmpOp cmp, flagsRegL xcc, iRegP dst, immP0 src) %{
9927 match(Set dst (CMoveP (Binary cmp xcc) (Binary dst src)));
9928 ins_cost(140);
9929 format %{ "MOV$cmp $xcc,$src,$dst" %}
9930 ins_encode( enc_cmov_imm(cmp,dst,src, (Assembler::xcc)) );
9931 ins_pipe(ialu_imm);
9932 %}
9933
9934 instruct cmovFL_reg(cmpOp cmp, flagsRegL xcc, regF dst, regF src) %{
9935 match(Set dst (CMoveF (Binary cmp xcc) (Binary dst src)));
9936 ins_cost(150);
9937 opcode(0x101);
9938 format %{ "FMOVS$cmp $xcc,$src,$dst" %}
9939 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9940 ins_pipe(int_conditional_float_move);
9941 %}
9942
9943 instruct cmovDL_reg(cmpOp cmp, flagsRegL xcc, regD dst, regD src) %{
9944 match(Set dst (CMoveD (Binary cmp xcc) (Binary dst src)));
9945 ins_cost(150);
9946 opcode(0x102);
9947 format %{ "FMOVD$cmp $xcc,$src,$dst" %}
9948 ins_encode( enc_cmovf_reg(cmp,dst,src, (Assembler::xcc)) );
9949 ins_pipe(int_conditional_float_move);
9950 %}
9951
9952 // ============================================================================
9953 // Safepoint Instruction
9954 instruct safePoint_poll(iRegP poll) %{
9955 match(SafePoint poll);
9956 effect(USE poll);
9957
9958 size(4);
9959 #ifdef _LP64
9960 format %{ "LDX [$poll],R_G0\t! Safepoint: poll for GC" %}
9961 #else
9962 format %{ "LDUW [$poll],R_G0\t! Safepoint: poll for GC" %}
9963 #endif
9964 ins_encode %{
9965 __ relocate(relocInfo::poll_type);
9966 __ ld_ptr($poll$$Register, 0, G0);
9967 %}
9968 ins_pipe(loadPollP);
9969 %}
9970
9971 // ============================================================================
9972 // Call Instructions
9973 // Call Java Static Instruction
9974 instruct CallStaticJavaDirect( method meth ) %{
9975 match(CallStaticJava);
9976 predicate(! ((CallStaticJavaNode*)n)->is_method_handle_invoke());
9977 effect(USE meth);
9978
9979 size(8);
9980 ins_cost(CALL_COST);
9981 format %{ "CALL,static ; NOP ==> " %}
9982 ins_encode( Java_Static_Call( meth ), call_epilog );
9983 ins_avoid_back_to_back(AVOID_BEFORE);
9984 ins_pipe(simple_call);
9985 %}
9986
9987 // Call Java Static Instruction (method handle version)
9988 instruct CallStaticJavaHandle(method meth, l7RegP l7_mh_SP_save) %{
9989 match(CallStaticJava);
9990 predicate(((CallStaticJavaNode*)n)->is_method_handle_invoke());
9991 effect(USE meth, KILL l7_mh_SP_save);
9992
9993 size(16);
9994 ins_cost(CALL_COST);
9995 format %{ "CALL,static/MethodHandle" %}
9996 ins_encode(preserve_SP, Java_Static_Call(meth), restore_SP, call_epilog);
9997 ins_pipe(simple_call);
9998 %}
9999
10000 // Call Java Dynamic Instruction
10001 instruct CallDynamicJavaDirect( method meth ) %{
10002 match(CallDynamicJava);
10003 effect(USE meth);
10004
10005 ins_cost(CALL_COST);
10006 format %{ "SET (empty),R_G5\n\t"
10007 "CALL,dynamic ; NOP ==> " %}
10008 ins_encode( Java_Dynamic_Call( meth ), call_epilog );
10009 ins_pipe(call);
10010 %}
10011
10012 // Call Runtime Instruction
10013 instruct CallRuntimeDirect(method meth, l7RegP l7) %{
10014 match(CallRuntime);
10015 effect(USE meth, KILL l7);
10016 ins_cost(CALL_COST);
10017 format %{ "CALL,runtime" %}
10018 ins_encode( Java_To_Runtime( meth ),
10019 call_epilog, adjust_long_from_native_call );
10020 ins_avoid_back_to_back(AVOID_BEFORE);
10021 ins_pipe(simple_call);
10022 %}
10023
10024 // Call runtime without safepoint - same as CallRuntime
10025 instruct CallLeafDirect(method meth, l7RegP l7) %{
10026 match(CallLeaf);
10027 effect(USE meth, KILL l7);
10028 ins_cost(CALL_COST);
10029 format %{ "CALL,runtime leaf" %}
10030 ins_encode( Java_To_Runtime( meth ),
10031 call_epilog,
10032 adjust_long_from_native_call );
10033 ins_avoid_back_to_back(AVOID_BEFORE);
10034 ins_pipe(simple_call);
10035 %}
10036
10037 // Call runtime without safepoint - same as CallLeaf
10038 instruct CallLeafNoFPDirect(method meth, l7RegP l7) %{
10039 match(CallLeafNoFP);
10040 effect(USE meth, KILL l7);
10041 ins_cost(CALL_COST);
10042 format %{ "CALL,runtime leaf nofp" %}
10043 ins_encode( Java_To_Runtime( meth ),
10044 call_epilog,
10045 adjust_long_from_native_call );
10046 ins_avoid_back_to_back(AVOID_BEFORE);
10047 ins_pipe(simple_call);
10048 %}
10049
10050 // Tail Call; Jump from runtime stub to Java code.
10051 // Also known as an 'interprocedural jump'.
10052 // Target of jump will eventually return to caller.
10053 // TailJump below removes the return address.
10054 instruct TailCalljmpInd(g3RegP jump_target, inline_cache_regP method_oop) %{
10055 match(TailCall jump_target method_oop );
10056
10057 ins_cost(CALL_COST);
10058 format %{ "Jmp $jump_target ; NOP \t! $method_oop holds method oop" %}
10059 ins_encode(form_jmpl(jump_target));
10060 ins_avoid_back_to_back(AVOID_BEFORE);
10061 ins_pipe(tail_call);
10062 %}
10063
10064
10065 // Return Instruction
10066 instruct Ret() %{
10067 match(Return);
10068
10069 // The epilogue node did the ret already.
10070 size(0);
10071 format %{ "! return" %}
10072 ins_encode();
10073 ins_pipe(empty);
10074 %}
10075
10076
10077 // Tail Jump; remove the return address; jump to target.
10078 // TailCall above leaves the return address around.
10079 // TailJump is used in only one place, the rethrow_Java stub (fancy_jump=2).
10080 // ex_oop (Exception Oop) is needed in %o0 at the jump. As there would be a
10081 // "restore" before this instruction (in Epilogue), we need to materialize it
10082 // in %i0.
10083 instruct tailjmpInd(g1RegP jump_target, i0RegP ex_oop) %{
10084 match( TailJump jump_target ex_oop );
10085 ins_cost(CALL_COST);
10086 format %{ "! discard R_O7\n\t"
10087 "Jmp $jump_target ; ADD O7,8,O1 \t! $ex_oop holds exc. oop" %}
10088 ins_encode(form_jmpl_set_exception_pc(jump_target));
10089 // opcode(Assembler::jmpl_op3, Assembler::arith_op);
10090 // The hack duplicates the exception oop into G3, so that CreateEx can use it there.
10091 // ins_encode( form3_rs1_simm13_rd( jump_target, 0x00, R_G0 ), move_return_pc_to_o1() );
10092 ins_avoid_back_to_back(AVOID_BEFORE);
10093 ins_pipe(tail_call);
10094 %}
10095
10096 // Create exception oop: created by stack-crawling runtime code.
10097 // Created exception is now available to this handler, and is setup
10098 // just prior to jumping to this handler. No code emitted.
10099 instruct CreateException( o0RegP ex_oop )
10100 %{
10101 match(Set ex_oop (CreateEx));
10102 ins_cost(0);
10103
10104 size(0);
10105 // use the following format syntax
10106 format %{ "! exception oop is in R_O0; no code emitted" %}
10107 ins_encode();
10108 ins_pipe(empty);
10109 %}
10110
10111
10112 // Rethrow exception:
10113 // The exception oop will come in the first argument position.
10114 // Then JUMP (not call) to the rethrow stub code.
10115 instruct RethrowException()
10116 %{
10117 match(Rethrow);
10118 ins_cost(CALL_COST);
10119
10120 // use the following format syntax
10121 format %{ "Jmp rethrow_stub" %}
10122 ins_encode(enc_rethrow);
10123 ins_avoid_back_to_back(AVOID_BEFORE);
10124 ins_pipe(tail_call);
10125 %}
10126
10127
10128 // Die now
10129 instruct ShouldNotReachHere( )
10130 %{
10131 match(Halt);
10132 ins_cost(CALL_COST);
10133
10134 size(4);
10135 // Use the following format syntax
10136 format %{ "ILLTRAP ; ShouldNotReachHere" %}
10137 ins_encode( form2_illtrap() );
10138 ins_pipe(tail_call);
10139 %}
10140
10141 // ============================================================================
10142 // The 2nd slow-half of a subtype check. Scan the subklass's 2ndary superklass
10143 // array for an instance of the superklass. Set a hidden internal cache on a
10144 // hit (cache is checked with exposed code in gen_subtype_check()). Return
10145 // not zero for a miss or zero for a hit. The encoding ALSO sets flags.
10146 instruct partialSubtypeCheck( o0RegP index, o1RegP sub, o2RegP super, flagsRegP pcc, o7RegP o7 ) %{
10147 match(Set index (PartialSubtypeCheck sub super));
10148 effect( KILL pcc, KILL o7 );
10149 ins_cost(DEFAULT_COST*10);
10150 format %{ "CALL PartialSubtypeCheck\n\tNOP" %}
10151 ins_encode( enc_PartialSubtypeCheck() );
10152 ins_avoid_back_to_back(AVOID_BEFORE);
10153 ins_pipe(partial_subtype_check_pipe);
10154 %}
10155
10156 instruct partialSubtypeCheck_vs_zero( flagsRegP pcc, o1RegP sub, o2RegP super, immP0 zero, o0RegP idx, o7RegP o7 ) %{
10157 match(Set pcc (CmpP (PartialSubtypeCheck sub super) zero));
10158 effect( KILL idx, KILL o7 );
10159 ins_cost(DEFAULT_COST*10);
10160 format %{ "CALL PartialSubtypeCheck\n\tNOP\t# (sets condition codes)" %}
10161 ins_encode( enc_PartialSubtypeCheck() );
10162 ins_avoid_back_to_back(AVOID_BEFORE);
10163 ins_pipe(partial_subtype_check_pipe);
10164 %}
10165
10166
10167 // ============================================================================
10168 // inlined locking and unlocking
10169
10170 instruct cmpFastLock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10171 match(Set pcc (FastLock object box));
10172
10173 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10174 ins_cost(100);
10175
10176 format %{ "FASTLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10177 ins_encode( Fast_Lock(object, box, scratch, scratch2) );
10178 ins_pipe(long_memory_op);
10179 %}
10180
10181
10182 instruct cmpFastUnlock(flagsRegP pcc, iRegP object, o1RegP box, iRegP scratch2, o7RegP scratch ) %{
10183 match(Set pcc (FastUnlock object box));
10184 effect(TEMP scratch2, USE_KILL box, KILL scratch);
10185 ins_cost(100);
10186
10187 format %{ "FASTUNLOCK $object,$box\t! kills $box,$scratch,$scratch2" %}
10188 ins_encode( Fast_Unlock(object, box, scratch, scratch2) );
10189 ins_pipe(long_memory_op);
10190 %}
10191
10192 // The encodings are generic.
10193 instruct clear_array(iRegX cnt, iRegP base, iRegX temp, Universe dummy, flagsReg ccr) %{
10194 predicate(!use_block_zeroing(n->in(2)) );
10195 match(Set dummy (ClearArray cnt base));
10196 effect(TEMP temp, KILL ccr);
10197 ins_cost(300);
10198 format %{ "MOV $cnt,$temp\n"
10199 "loop: SUBcc $temp,8,$temp\t! Count down a dword of bytes\n"
10200 " BRge loop\t\t! Clearing loop\n"
10201 " STX G0,[$base+$temp]\t! delay slot" %}
10202
10203 ins_encode %{
10204 // Compiler ensures base is doubleword aligned and cnt is count of doublewords
10205 Register nof_bytes_arg = $cnt$$Register;
10206 Register nof_bytes_tmp = $temp$$Register;
10207 Register base_pointer_arg = $base$$Register;
10208
10209 Label loop;
10210 __ mov(nof_bytes_arg, nof_bytes_tmp);
10211
10212 // Loop and clear, walking backwards through the array.
10213 // nof_bytes_tmp (if >0) is always the number of bytes to zero
10214 __ bind(loop);
10215 __ deccc(nof_bytes_tmp, 8);
10216 __ br(Assembler::greaterEqual, true, Assembler::pt, loop);
10217 __ delayed()-> stx(G0, base_pointer_arg, nof_bytes_tmp);
10218 // %%%% this mini-loop must not cross a cache boundary!
10219 %}
10220 ins_pipe(long_memory_op);
10221 %}
10222
10223 instruct clear_array_bis(g1RegX cnt, o0RegP base, Universe dummy, flagsReg ccr) %{
10224 predicate(use_block_zeroing(n->in(2)));
10225 match(Set dummy (ClearArray cnt base));
10226 effect(USE_KILL cnt, USE_KILL base, KILL ccr);
10227 ins_cost(300);
10228 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10229
10230 ins_encode %{
10231
10232 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10233 Register to = $base$$Register;
10234 Register count = $cnt$$Register;
10235
10236 Label Ldone;
10237 __ nop(); // Separate short branches
10238 // Use BIS for zeroing (temp is not used).
10239 __ bis_zeroing(to, count, G0, Ldone);
10240 __ bind(Ldone);
10241
10242 %}
10243 ins_pipe(long_memory_op);
10244 %}
10245
10246 instruct clear_array_bis_2(g1RegX cnt, o0RegP base, iRegX tmp, Universe dummy, flagsReg ccr) %{
10247 predicate(use_block_zeroing(n->in(2)) && !Assembler::is_simm13((int)BlockZeroingLowLimit));
10248 match(Set dummy (ClearArray cnt base));
10249 effect(TEMP tmp, USE_KILL cnt, USE_KILL base, KILL ccr);
10250 ins_cost(300);
10251 format %{ "CLEAR [$base, $cnt]\t! ClearArray" %}
10252
10253 ins_encode %{
10254
10255 assert(MinObjAlignmentInBytes >= BytesPerLong, "need alternate implementation");
10256 Register to = $base$$Register;
10257 Register count = $cnt$$Register;
10258 Register temp = $tmp$$Register;
10259
10260 Label Ldone;
10261 __ nop(); // Separate short branches
10262 // Use BIS for zeroing
10263 __ bis_zeroing(to, count, temp, Ldone);
10264 __ bind(Ldone);
10265
10266 %}
10267 ins_pipe(long_memory_op);
10268 %}
10269
10270 instruct string_compare(o0RegP str1, o1RegP str2, g3RegI cnt1, g4RegI cnt2, notemp_iRegI result,
10271 o7RegI tmp, flagsReg ccr) %{
10272 match(Set result (StrComp (Binary str1 cnt1) (Binary str2 cnt2)));
10273 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt1, USE_KILL cnt2, KILL ccr, KILL tmp);
10274 ins_cost(300);
10275 format %{ "String Compare $str1,$cnt1,$str2,$cnt2 -> $result // KILL $tmp" %}
10276 ins_encode( enc_String_Compare(str1, str2, cnt1, cnt2, result) );
10277 ins_pipe(long_memory_op);
10278 %}
10279
10280 instruct string_equals(o0RegP str1, o1RegP str2, g3RegI cnt, notemp_iRegI result,
10281 o7RegI tmp, flagsReg ccr) %{
10282 match(Set result (StrEquals (Binary str1 str2) cnt));
10283 effect(USE_KILL str1, USE_KILL str2, USE_KILL cnt, KILL tmp, KILL ccr);
10284 ins_cost(300);
10285 format %{ "String Equals $str1,$str2,$cnt -> $result // KILL $tmp" %}
10286 ins_encode( enc_String_Equals(str1, str2, cnt, result) );
10287 ins_pipe(long_memory_op);
10288 %}
10289
10290 instruct array_equals(o0RegP ary1, o1RegP ary2, g3RegI tmp1, notemp_iRegI result,
10291 o7RegI tmp2, flagsReg ccr) %{
10292 match(Set result (AryEq ary1 ary2));
10293 effect(USE_KILL ary1, USE_KILL ary2, KILL tmp1, KILL tmp2, KILL ccr);
10294 ins_cost(300);
10295 format %{ "Array Equals $ary1,$ary2 -> $result // KILL $tmp1,$tmp2" %}
10296 ins_encode( enc_Array_Equals(ary1, ary2, tmp1, result));
10297 ins_pipe(long_memory_op);
10298 %}
10299
10300
10301 //---------- Zeros Count Instructions ------------------------------------------
10302
10303 instruct countLeadingZerosI(iRegIsafe dst, iRegI src, iRegI tmp, flagsReg cr) %{
10304 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10305 match(Set dst (CountLeadingZerosI src));
10306 effect(TEMP dst, TEMP tmp, KILL cr);
10307
10308 // x |= (x >> 1);
10309 // x |= (x >> 2);
10310 // x |= (x >> 4);
10311 // x |= (x >> 8);
10312 // x |= (x >> 16);
10313 // return (WORDBITS - popc(x));
10314 format %{ "SRL $src,1,$tmp\t! count leading zeros (int)\n\t"
10315 "SRL $src,0,$dst\t! 32-bit zero extend\n\t"
10316 "OR $dst,$tmp,$dst\n\t"
10317 "SRL $dst,2,$tmp\n\t"
10318 "OR $dst,$tmp,$dst\n\t"
10319 "SRL $dst,4,$tmp\n\t"
10320 "OR $dst,$tmp,$dst\n\t"
10321 "SRL $dst,8,$tmp\n\t"
10322 "OR $dst,$tmp,$dst\n\t"
10323 "SRL $dst,16,$tmp\n\t"
10324 "OR $dst,$tmp,$dst\n\t"
10325 "POPC $dst,$dst\n\t"
10326 "MOV 32,$tmp\n\t"
10327 "SUB $tmp,$dst,$dst" %}
10328 ins_encode %{
10329 Register Rdst = $dst$$Register;
10330 Register Rsrc = $src$$Register;
10331 Register Rtmp = $tmp$$Register;
10332 __ srl(Rsrc, 1, Rtmp);
10333 __ srl(Rsrc, 0, Rdst);
10334 __ or3(Rdst, Rtmp, Rdst);
10335 __ srl(Rdst, 2, Rtmp);
10336 __ or3(Rdst, Rtmp, Rdst);
10337 __ srl(Rdst, 4, Rtmp);
10338 __ or3(Rdst, Rtmp, Rdst);
10339 __ srl(Rdst, 8, Rtmp);
10340 __ or3(Rdst, Rtmp, Rdst);
10341 __ srl(Rdst, 16, Rtmp);
10342 __ or3(Rdst, Rtmp, Rdst);
10343 __ popc(Rdst, Rdst);
10344 __ mov(BitsPerInt, Rtmp);
10345 __ sub(Rtmp, Rdst, Rdst);
10346 %}
10347 ins_pipe(ialu_reg);
10348 %}
10349
10350 instruct countLeadingZerosL(iRegIsafe dst, iRegL src, iRegL tmp, flagsReg cr) %{
10351 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10352 match(Set dst (CountLeadingZerosL src));
10353 effect(TEMP dst, TEMP tmp, KILL cr);
10354
10355 // x |= (x >> 1);
10356 // x |= (x >> 2);
10357 // x |= (x >> 4);
10358 // x |= (x >> 8);
10359 // x |= (x >> 16);
10360 // x |= (x >> 32);
10361 // return (WORDBITS - popc(x));
10362 format %{ "SRLX $src,1,$tmp\t! count leading zeros (long)\n\t"
10363 "OR $src,$tmp,$dst\n\t"
10364 "SRLX $dst,2,$tmp\n\t"
10365 "OR $dst,$tmp,$dst\n\t"
10366 "SRLX $dst,4,$tmp\n\t"
10367 "OR $dst,$tmp,$dst\n\t"
10368 "SRLX $dst,8,$tmp\n\t"
10369 "OR $dst,$tmp,$dst\n\t"
10370 "SRLX $dst,16,$tmp\n\t"
10371 "OR $dst,$tmp,$dst\n\t"
10372 "SRLX $dst,32,$tmp\n\t"
10373 "OR $dst,$tmp,$dst\n\t"
10374 "POPC $dst,$dst\n\t"
10375 "MOV 64,$tmp\n\t"
10376 "SUB $tmp,$dst,$dst" %}
10377 ins_encode %{
10378 Register Rdst = $dst$$Register;
10379 Register Rsrc = $src$$Register;
10380 Register Rtmp = $tmp$$Register;
10381 __ srlx(Rsrc, 1, Rtmp);
10382 __ or3( Rsrc, Rtmp, Rdst);
10383 __ srlx(Rdst, 2, Rtmp);
10384 __ or3( Rdst, Rtmp, Rdst);
10385 __ srlx(Rdst, 4, Rtmp);
10386 __ or3( Rdst, Rtmp, Rdst);
10387 __ srlx(Rdst, 8, Rtmp);
10388 __ or3( Rdst, Rtmp, Rdst);
10389 __ srlx(Rdst, 16, Rtmp);
10390 __ or3( Rdst, Rtmp, Rdst);
10391 __ srlx(Rdst, 32, Rtmp);
10392 __ or3( Rdst, Rtmp, Rdst);
10393 __ popc(Rdst, Rdst);
10394 __ mov(BitsPerLong, Rtmp);
10395 __ sub(Rtmp, Rdst, Rdst);
10396 %}
10397 ins_pipe(ialu_reg);
10398 %}
10399
10400 instruct countTrailingZerosI(iRegIsafe dst, iRegI src, flagsReg cr) %{
10401 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10402 match(Set dst (CountTrailingZerosI src));
10403 effect(TEMP dst, KILL cr);
10404
10405 // return popc(~x & (x - 1));
10406 format %{ "SUB $src,1,$dst\t! count trailing zeros (int)\n\t"
10407 "ANDN $dst,$src,$dst\n\t"
10408 "SRL $dst,R_G0,$dst\n\t"
10409 "POPC $dst,$dst" %}
10410 ins_encode %{
10411 Register Rdst = $dst$$Register;
10412 Register Rsrc = $src$$Register;
10413 __ sub(Rsrc, 1, Rdst);
10414 __ andn(Rdst, Rsrc, Rdst);
10415 __ srl(Rdst, G0, Rdst);
10416 __ popc(Rdst, Rdst);
10417 %}
10418 ins_pipe(ialu_reg);
10419 %}
10420
10421 instruct countTrailingZerosL(iRegIsafe dst, iRegL src, flagsReg cr) %{
10422 predicate(UsePopCountInstruction); // See Matcher::match_rule_supported
10423 match(Set dst (CountTrailingZerosL src));
10424 effect(TEMP dst, KILL cr);
10425
10426 // return popc(~x & (x - 1));
10427 format %{ "SUB $src,1,$dst\t! count trailing zeros (long)\n\t"
10428 "ANDN $dst,$src,$dst\n\t"
10429 "POPC $dst,$dst" %}
10430 ins_encode %{
10431 Register Rdst = $dst$$Register;
10432 Register Rsrc = $src$$Register;
10433 __ sub(Rsrc, 1, Rdst);
10434 __ andn(Rdst, Rsrc, Rdst);
10435 __ popc(Rdst, Rdst);
10436 %}
10437 ins_pipe(ialu_reg);
10438 %}
10439
10440
10441 //---------- Population Count Instructions -------------------------------------
10442
10443 instruct popCountI(iRegIsafe dst, iRegI src) %{
10444 predicate(UsePopCountInstruction);
10445 match(Set dst (PopCountI src));
10446
10447 format %{ "SRL $src, G0, $dst\t! clear upper word for 64 bit POPC\n\t"
10448 "POPC $dst, $dst" %}
10449 ins_encode %{
10450 __ srl($src$$Register, G0, $dst$$Register);
10451 __ popc($dst$$Register, $dst$$Register);
10452 %}
10453 ins_pipe(ialu_reg);
10454 %}
10455
10456 // Note: Long.bitCount(long) returns an int.
10457 instruct popCountL(iRegIsafe dst, iRegL src) %{
10458 predicate(UsePopCountInstruction);
10459 match(Set dst (PopCountL src));
10460
10461 format %{ "POPC $src, $dst" %}
10462 ins_encode %{
10463 __ popc($src$$Register, $dst$$Register);
10464 %}
10465 ins_pipe(ialu_reg);
10466 %}
10467
10468
10469 // ============================================================================
10470 //------------Bytes reverse--------------------------------------------------
10471
10472 instruct bytes_reverse_int(iRegI dst, stackSlotI src) %{
10473 match(Set dst (ReverseBytesI src));
10474
10475 // Op cost is artificially doubled to make sure that load or store
10476 // instructions are preferred over this one which requires a spill
10477 // onto a stack slot.
10478 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10479 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10480
10481 ins_encode %{
10482 __ set($src$$disp + STACK_BIAS, O7);
10483 __ lduwa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10484 %}
10485 ins_pipe( iload_mem );
10486 %}
10487
10488 instruct bytes_reverse_long(iRegL dst, stackSlotL src) %{
10489 match(Set dst (ReverseBytesL src));
10490
10491 // Op cost is artificially doubled to make sure that load or store
10492 // instructions are preferred over this one which requires a spill
10493 // onto a stack slot.
10494 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10495 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10496
10497 ins_encode %{
10498 __ set($src$$disp + STACK_BIAS, O7);
10499 __ ldxa($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10500 %}
10501 ins_pipe( iload_mem );
10502 %}
10503
10504 instruct bytes_reverse_unsigned_short(iRegI dst, stackSlotI src) %{
10505 match(Set dst (ReverseBytesUS src));
10506
10507 // Op cost is artificially doubled to make sure that load or store
10508 // instructions are preferred over this one which requires a spill
10509 // onto a stack slot.
10510 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10511 format %{ "LDUHA $src, $dst\t!asi=primary_little\n\t" %}
10512
10513 ins_encode %{
10514 // the value was spilled as an int so bias the load
10515 __ set($src$$disp + STACK_BIAS + 2, O7);
10516 __ lduha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10517 %}
10518 ins_pipe( iload_mem );
10519 %}
10520
10521 instruct bytes_reverse_short(iRegI dst, stackSlotI src) %{
10522 match(Set dst (ReverseBytesS src));
10523
10524 // Op cost is artificially doubled to make sure that load or store
10525 // instructions are preferred over this one which requires a spill
10526 // onto a stack slot.
10527 ins_cost(2*DEFAULT_COST + MEMORY_REF_COST);
10528 format %{ "LDSHA $src, $dst\t!asi=primary_little\n\t" %}
10529
10530 ins_encode %{
10531 // the value was spilled as an int so bias the load
10532 __ set($src$$disp + STACK_BIAS + 2, O7);
10533 __ ldsha($src$$base$$Register, O7, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10534 %}
10535 ins_pipe( iload_mem );
10536 %}
10537
10538 // Load Integer reversed byte order
10539 instruct loadI_reversed(iRegI dst, indIndexMemory src) %{
10540 match(Set dst (ReverseBytesI (LoadI src)));
10541
10542 ins_cost(DEFAULT_COST + MEMORY_REF_COST);
10543 size(4);
10544 format %{ "LDUWA $src, $dst\t!asi=primary_little" %}
10545
10546 ins_encode %{
10547 __ lduwa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10548 %}
10549 ins_pipe(iload_mem);
10550 %}
10551
10552 // Load Long - aligned and reversed
10553 instruct loadL_reversed(iRegL dst, indIndexMemory src) %{
10554 match(Set dst (ReverseBytesL (LoadL src)));
10555
10556 ins_cost(MEMORY_REF_COST);
10557 size(4);
10558 format %{ "LDXA $src, $dst\t!asi=primary_little" %}
10559
10560 ins_encode %{
10561 __ ldxa($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10562 %}
10563 ins_pipe(iload_mem);
10564 %}
10565
10566 // Load unsigned short / char reversed byte order
10567 instruct loadUS_reversed(iRegI dst, indIndexMemory src) %{
10568 match(Set dst (ReverseBytesUS (LoadUS src)));
10569
10570 ins_cost(MEMORY_REF_COST);
10571 size(4);
10572 format %{ "LDUHA $src, $dst\t!asi=primary_little" %}
10573
10574 ins_encode %{
10575 __ lduha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10576 %}
10577 ins_pipe(iload_mem);
10578 %}
10579
10580 // Load short reversed byte order
10581 instruct loadS_reversed(iRegI dst, indIndexMemory src) %{
10582 match(Set dst (ReverseBytesS (LoadS src)));
10583
10584 ins_cost(MEMORY_REF_COST);
10585 size(4);
10586 format %{ "LDSHA $src, $dst\t!asi=primary_little" %}
10587
10588 ins_encode %{
10589 __ ldsha($src$$base$$Register, $src$$index$$Register, Assembler::ASI_PRIMARY_LITTLE, $dst$$Register);
10590 %}
10591 ins_pipe(iload_mem);
10592 %}
10593
10594 // Store Integer reversed byte order
10595 instruct storeI_reversed(indIndexMemory dst, iRegI src) %{
10596 match(Set dst (StoreI dst (ReverseBytesI src)));
10597
10598 ins_cost(MEMORY_REF_COST);
10599 size(4);
10600 format %{ "STWA $src, $dst\t!asi=primary_little" %}
10601
10602 ins_encode %{
10603 __ stwa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10604 %}
10605 ins_pipe(istore_mem_reg);
10606 %}
10607
10608 // Store Long reversed byte order
10609 instruct storeL_reversed(indIndexMemory dst, iRegL src) %{
10610 match(Set dst (StoreL dst (ReverseBytesL src)));
10611
10612 ins_cost(MEMORY_REF_COST);
10613 size(4);
10614 format %{ "STXA $src, $dst\t!asi=primary_little" %}
10615
10616 ins_encode %{
10617 __ stxa($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10618 %}
10619 ins_pipe(istore_mem_reg);
10620 %}
10621
10622 // Store unsighed short/char reversed byte order
10623 instruct storeUS_reversed(indIndexMemory dst, iRegI src) %{
10624 match(Set dst (StoreC dst (ReverseBytesUS src)));
10625
10626 ins_cost(MEMORY_REF_COST);
10627 size(4);
10628 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10629
10630 ins_encode %{
10631 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10632 %}
10633 ins_pipe(istore_mem_reg);
10634 %}
10635
10636 // Store short reversed byte order
10637 instruct storeS_reversed(indIndexMemory dst, iRegI src) %{
10638 match(Set dst (StoreC dst (ReverseBytesS src)));
10639
10640 ins_cost(MEMORY_REF_COST);
10641 size(4);
10642 format %{ "STHA $src, $dst\t!asi=primary_little" %}
10643
10644 ins_encode %{
10645 __ stha($src$$Register, $dst$$base$$Register, $dst$$index$$Register, Assembler::ASI_PRIMARY_LITTLE);
10646 %}
10647 ins_pipe(istore_mem_reg);
10648 %}
10649
10650 // ====================VECTOR INSTRUCTIONS=====================================
10651
10652 // Load Aligned Packed values into a Double Register
10653 instruct loadV8(regD dst, memory mem) %{
10654 predicate(n->as_LoadVector()->memory_size() == 8);
10655 match(Set dst (LoadVector mem));
10656 ins_cost(MEMORY_REF_COST);
10657 size(4);
10658 format %{ "LDDF $mem,$dst\t! load vector (8 bytes)" %}
10659 ins_encode %{
10660 __ ldf(FloatRegisterImpl::D, $mem$$Address, as_DoubleFloatRegister($dst$$reg));
10661 %}
10662 ins_pipe(floadD_mem);
10663 %}
10664
10665 // Store Vector in Double register to memory
10666 instruct storeV8(memory mem, regD src) %{
10667 predicate(n->as_StoreVector()->memory_size() == 8);
10668 match(Set mem (StoreVector mem src));
10669 ins_cost(MEMORY_REF_COST);
10670 size(4);
10671 format %{ "STDF $src,$mem\t! store vector (8 bytes)" %}
10672 ins_encode %{
10673 __ stf(FloatRegisterImpl::D, as_DoubleFloatRegister($src$$reg), $mem$$Address);
10674 %}
10675 ins_pipe(fstoreD_mem_reg);
10676 %}
10677
10678 // Store Zero into vector in memory
10679 instruct storeV8B_zero(memory mem, immI0 zero) %{
10680 predicate(n->as_StoreVector()->memory_size() == 8);
10681 match(Set mem (StoreVector mem (ReplicateB zero)));
10682 ins_cost(MEMORY_REF_COST);
10683 size(4);
10684 format %{ "STX $zero,$mem\t! store zero vector (8 bytes)" %}
10685 ins_encode %{
10686 __ stx(G0, $mem$$Address);
10687 %}
10688 ins_pipe(fstoreD_mem_zero);
10689 %}
10690
10691 instruct storeV4S_zero(memory mem, immI0 zero) %{
10692 predicate(n->as_StoreVector()->memory_size() == 8);
10693 match(Set mem (StoreVector mem (ReplicateS zero)));
10694 ins_cost(MEMORY_REF_COST);
10695 size(4);
10696 format %{ "STX $zero,$mem\t! store zero vector (4 shorts)" %}
10697 ins_encode %{
10698 __ stx(G0, $mem$$Address);
10699 %}
10700 ins_pipe(fstoreD_mem_zero);
10701 %}
10702
10703 instruct storeV2I_zero(memory mem, immI0 zero) %{
10704 predicate(n->as_StoreVector()->memory_size() == 8);
10705 match(Set mem (StoreVector mem (ReplicateI zero)));
10706 ins_cost(MEMORY_REF_COST);
10707 size(4);
10708 format %{ "STX $zero,$mem\t! store zero vector (2 ints)" %}
10709 ins_encode %{
10710 __ stx(G0, $mem$$Address);
10711 %}
10712 ins_pipe(fstoreD_mem_zero);
10713 %}
10714
10715 instruct storeV2F_zero(memory mem, immF0 zero) %{
10716 predicate(n->as_StoreVector()->memory_size() == 8);
10717 match(Set mem (StoreVector mem (ReplicateF zero)));
10718 ins_cost(MEMORY_REF_COST);
10719 size(4);
10720 format %{ "STX $zero,$mem\t! store zero vector (2 floats)" %}
10721 ins_encode %{
10722 __ stx(G0, $mem$$Address);
10723 %}
10724 ins_pipe(fstoreD_mem_zero);
10725 %}
10726
10727 // Replicate scalar to packed byte values into Double register
10728 instruct Repl8B_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10729 predicate(n->as_Vector()->length() == 8 && UseVIS >= 3);
10730 match(Set dst (ReplicateB src));
10731 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10732 format %{ "SLLX $src,56,$tmp\n\t"
10733 "SRLX $tmp, 8,$tmp2\n\t"
10734 "OR $tmp,$tmp2,$tmp\n\t"
10735 "SRLX $tmp,16,$tmp2\n\t"
10736 "OR $tmp,$tmp2,$tmp\n\t"
10737 "SRLX $tmp,32,$tmp2\n\t"
10738 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10739 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10740 ins_encode %{
10741 Register Rsrc = $src$$Register;
10742 Register Rtmp = $tmp$$Register;
10743 Register Rtmp2 = $tmp2$$Register;
10744 __ sllx(Rsrc, 56, Rtmp);
10745 __ srlx(Rtmp, 8, Rtmp2);
10746 __ or3 (Rtmp, Rtmp2, Rtmp);
10747 __ srlx(Rtmp, 16, Rtmp2);
10748 __ or3 (Rtmp, Rtmp2, Rtmp);
10749 __ srlx(Rtmp, 32, Rtmp2);
10750 __ or3 (Rtmp, Rtmp2, Rtmp);
10751 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10752 %}
10753 ins_pipe(ialu_reg);
10754 %}
10755
10756 // Replicate scalar to packed byte values into Double stack
10757 instruct Repl8B_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10758 predicate(n->as_Vector()->length() == 8 && UseVIS < 3);
10759 match(Set dst (ReplicateB src));
10760 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10761 format %{ "SLLX $src,56,$tmp\n\t"
10762 "SRLX $tmp, 8,$tmp2\n\t"
10763 "OR $tmp,$tmp2,$tmp\n\t"
10764 "SRLX $tmp,16,$tmp2\n\t"
10765 "OR $tmp,$tmp2,$tmp\n\t"
10766 "SRLX $tmp,32,$tmp2\n\t"
10767 "OR $tmp,$tmp2,$tmp\t! replicate8B\n\t"
10768 "STX $tmp,$dst\t! regL to stkD" %}
10769 ins_encode %{
10770 Register Rsrc = $src$$Register;
10771 Register Rtmp = $tmp$$Register;
10772 Register Rtmp2 = $tmp2$$Register;
10773 __ sllx(Rsrc, 56, Rtmp);
10774 __ srlx(Rtmp, 8, Rtmp2);
10775 __ or3 (Rtmp, Rtmp2, Rtmp);
10776 __ srlx(Rtmp, 16, Rtmp2);
10777 __ or3 (Rtmp, Rtmp2, Rtmp);
10778 __ srlx(Rtmp, 32, Rtmp2);
10779 __ or3 (Rtmp, Rtmp2, Rtmp);
10780 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10781 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10782 %}
10783 ins_pipe(ialu_reg);
10784 %}
10785
10786 // Replicate scalar constant to packed byte values in Double register
10787 instruct Repl8B_immI(regD dst, immI13 con, o7RegI tmp) %{
10788 predicate(n->as_Vector()->length() == 8);
10789 match(Set dst (ReplicateB con));
10790 effect(KILL tmp);
10791 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl8B($con)" %}
10792 ins_encode %{
10793 // XXX This is a quick fix for 6833573.
10794 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 8, 1)), $dst$$FloatRegister);
10795 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 8, 1)), $tmp$$Register);
10796 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10797 %}
10798 ins_pipe(loadConFD);
10799 %}
10800
10801 // Replicate scalar to packed char/short values into Double register
10802 instruct Repl4S_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10803 predicate(n->as_Vector()->length() == 4 && UseVIS >= 3);
10804 match(Set dst (ReplicateS src));
10805 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10806 format %{ "SLLX $src,48,$tmp\n\t"
10807 "SRLX $tmp,16,$tmp2\n\t"
10808 "OR $tmp,$tmp2,$tmp\n\t"
10809 "SRLX $tmp,32,$tmp2\n\t"
10810 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10811 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10812 ins_encode %{
10813 Register Rsrc = $src$$Register;
10814 Register Rtmp = $tmp$$Register;
10815 Register Rtmp2 = $tmp2$$Register;
10816 __ sllx(Rsrc, 48, Rtmp);
10817 __ srlx(Rtmp, 16, Rtmp2);
10818 __ or3 (Rtmp, Rtmp2, Rtmp);
10819 __ srlx(Rtmp, 32, Rtmp2);
10820 __ or3 (Rtmp, Rtmp2, Rtmp);
10821 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10822 %}
10823 ins_pipe(ialu_reg);
10824 %}
10825
10826 // Replicate scalar to packed char/short values into Double stack
10827 instruct Repl4S_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10828 predicate(n->as_Vector()->length() == 4 && UseVIS < 3);
10829 match(Set dst (ReplicateS src));
10830 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10831 format %{ "SLLX $src,48,$tmp\n\t"
10832 "SRLX $tmp,16,$tmp2\n\t"
10833 "OR $tmp,$tmp2,$tmp\n\t"
10834 "SRLX $tmp,32,$tmp2\n\t"
10835 "OR $tmp,$tmp2,$tmp\t! replicate4S\n\t"
10836 "STX $tmp,$dst\t! regL to stkD" %}
10837 ins_encode %{
10838 Register Rsrc = $src$$Register;
10839 Register Rtmp = $tmp$$Register;
10840 Register Rtmp2 = $tmp2$$Register;
10841 __ sllx(Rsrc, 48, Rtmp);
10842 __ srlx(Rtmp, 16, Rtmp2);
10843 __ or3 (Rtmp, Rtmp2, Rtmp);
10844 __ srlx(Rtmp, 32, Rtmp2);
10845 __ or3 (Rtmp, Rtmp2, Rtmp);
10846 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10847 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10848 %}
10849 ins_pipe(ialu_reg);
10850 %}
10851
10852 // Replicate scalar constant to packed char/short values in Double register
10853 instruct Repl4S_immI(regD dst, immI con, o7RegI tmp) %{
10854 predicate(n->as_Vector()->length() == 4);
10855 match(Set dst (ReplicateS con));
10856 effect(KILL tmp);
10857 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl4S($con)" %}
10858 ins_encode %{
10859 // XXX This is a quick fix for 6833573.
10860 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 4, 2)), $dst$$FloatRegister);
10861 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 4, 2)), $tmp$$Register);
10862 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10863 %}
10864 ins_pipe(loadConFD);
10865 %}
10866
10867 // Replicate scalar to packed int values into Double register
10868 instruct Repl2I_reg(regD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10869 predicate(n->as_Vector()->length() == 2 && UseVIS >= 3);
10870 match(Set dst (ReplicateI src));
10871 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10872 format %{ "SLLX $src,32,$tmp\n\t"
10873 "SRLX $tmp,32,$tmp2\n\t"
10874 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10875 "MOVXTOD $tmp,$dst\t! MoveL2D" %}
10876 ins_encode %{
10877 Register Rsrc = $src$$Register;
10878 Register Rtmp = $tmp$$Register;
10879 Register Rtmp2 = $tmp2$$Register;
10880 __ sllx(Rsrc, 32, Rtmp);
10881 __ srlx(Rtmp, 32, Rtmp2);
10882 __ or3 (Rtmp, Rtmp2, Rtmp);
10883 __ movxtod(Rtmp, as_DoubleFloatRegister($dst$$reg));
10884 %}
10885 ins_pipe(ialu_reg);
10886 %}
10887
10888 // Replicate scalar to packed int values into Double stack
10889 instruct Repl2I_stk(stackSlotD dst, iRegI src, iRegL tmp, o7RegL tmp2) %{
10890 predicate(n->as_Vector()->length() == 2 && UseVIS < 3);
10891 match(Set dst (ReplicateI src));
10892 effect(DEF dst, USE src, TEMP tmp, KILL tmp2);
10893 format %{ "SLLX $src,32,$tmp\n\t"
10894 "SRLX $tmp,32,$tmp2\n\t"
10895 "OR $tmp,$tmp2,$tmp\t! replicate2I\n\t"
10896 "STX $tmp,$dst\t! regL to stkD" %}
10897 ins_encode %{
10898 Register Rsrc = $src$$Register;
10899 Register Rtmp = $tmp$$Register;
10900 Register Rtmp2 = $tmp2$$Register;
10901 __ sllx(Rsrc, 32, Rtmp);
10902 __ srlx(Rtmp, 32, Rtmp2);
10903 __ or3 (Rtmp, Rtmp2, Rtmp);
10904 __ set ($dst$$disp + STACK_BIAS, Rtmp2);
10905 __ stx (Rtmp, Rtmp2, $dst$$base$$Register);
10906 %}
10907 ins_pipe(ialu_reg);
10908 %}
10909
10910 // Replicate scalar zero constant to packed int values in Double register
10911 instruct Repl2I_immI(regD dst, immI con, o7RegI tmp) %{
10912 predicate(n->as_Vector()->length() == 2);
10913 match(Set dst (ReplicateI con));
10914 effect(KILL tmp);
10915 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2I($con)" %}
10916 ins_encode %{
10917 // XXX This is a quick fix for 6833573.
10918 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immI($con$$constant, 2, 4)), $dst$$FloatRegister);
10919 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immI($con$$constant, 2, 4)), $tmp$$Register);
10920 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10921 %}
10922 ins_pipe(loadConFD);
10923 %}
10924
10925 // Replicate scalar to packed float values into Double stack
10926 instruct Repl2F_stk(stackSlotD dst, regF src) %{
10927 predicate(n->as_Vector()->length() == 2);
10928 match(Set dst (ReplicateF src));
10929 ins_cost(MEMORY_REF_COST*2);
10930 format %{ "STF $src,$dst.hi\t! packed2F\n\t"
10931 "STF $src,$dst.lo" %}
10932 opcode(Assembler::stf_op3);
10933 ins_encode(simple_form3_mem_reg(dst, src), form3_mem_plus_4_reg(dst, src));
10934 ins_pipe(fstoreF_stk_reg);
10935 %}
10936
10937 // Replicate scalar zero constant to packed float values in Double register
10938 instruct Repl2F_immF(regD dst, immF con, o7RegI tmp) %{
10939 predicate(n->as_Vector()->length() == 2);
10940 match(Set dst (ReplicateF con));
10941 effect(KILL tmp);
10942 format %{ "LDDF [$constanttablebase + $constantoffset],$dst\t! load from constant table: Repl2F($con)" %}
10943 ins_encode %{
10944 // XXX This is a quick fix for 6833573.
10945 //__ ldf(FloatRegisterImpl::D, $constanttablebase, $constantoffset(replicate_immF($con$$constant)), $dst$$FloatRegister);
10946 RegisterOrConstant con_offset = __ ensure_simm13_or_reg($constantoffset(replicate_immF($con$$constant)), $tmp$$Register);
10947 __ ldf(FloatRegisterImpl::D, $constanttablebase, con_offset, as_DoubleFloatRegister($dst$$reg));
10948 %}
10949 ins_pipe(loadConFD);
10950 %}
10951
10952 //----------PEEPHOLE RULES-----------------------------------------------------
10953 // These must follow all instruction definitions as they use the names
10954 // defined in the instructions definitions.
10955 //
10956 // peepmatch ( root_instr_name [preceding_instruction]* );
10957 //
10958 // peepconstraint %{
10959 // (instruction_number.operand_name relational_op instruction_number.operand_name
10960 // [, ...] );
10961 // // instruction numbers are zero-based using left to right order in peepmatch
10962 //
10963 // peepreplace ( instr_name ( [instruction_number.operand_name]* ) );
10964 // // provide an instruction_number.operand_name for each operand that appears
10965 // // in the replacement instruction's match rule
10966 //
10967 // ---------VM FLAGS---------------------------------------------------------
10968 //
10969 // All peephole optimizations can be turned off using -XX:-OptoPeephole
10970 //
10971 // Each peephole rule is given an identifying number starting with zero and
10972 // increasing by one in the order seen by the parser. An individual peephole
10973 // can be enabled, and all others disabled, by using -XX:OptoPeepholeAt=#
10974 // on the command-line.
10975 //
10976 // ---------CURRENT LIMITATIONS----------------------------------------------
10977 //
10978 // Only match adjacent instructions in same basic block
10979 // Only equality constraints
10980 // Only constraints between operands, not (0.dest_reg == EAX_enc)
10981 // Only one replacement instruction
10982 //
10983 // ---------EXAMPLE----------------------------------------------------------
10984 //
10985 // // pertinent parts of existing instructions in architecture description
10986 // instruct movI(eRegI dst, eRegI src) %{
10987 // match(Set dst (CopyI src));
10988 // %}
10989 //
10990 // instruct incI_eReg(eRegI dst, immI1 src, eFlagsReg cr) %{
10991 // match(Set dst (AddI dst src));
10992 // effect(KILL cr);
10993 // %}
10994 //
10995 // // Change (inc mov) to lea
10996 // peephole %{
10997 // // increment preceeded by register-register move
10998 // peepmatch ( incI_eReg movI );
10999 // // require that the destination register of the increment
11000 // // match the destination register of the move
11001 // peepconstraint ( 0.dst == 1.dst );
11002 // // construct a replacement instruction that sets
11003 // // the destination to ( move's source register + one )
11004 // peepreplace ( incI_eReg_immI1( 0.dst 1.src 0.src ) );
11005 // %}
11006 //
11007
11008 // // Change load of spilled value to only a spill
11009 // instruct storeI(memory mem, eRegI src) %{
11010 // match(Set mem (StoreI mem src));
11011 // %}
11012 //
11013 // instruct loadI(eRegI dst, memory mem) %{
11014 // match(Set dst (LoadI mem));
11015 // %}
11016 //
11017 // peephole %{
11018 // peepmatch ( loadI storeI );
11019 // peepconstraint ( 1.src == 0.dst, 1.mem == 0.mem );
11020 // peepreplace ( storeI( 1.mem 1.mem 1.src ) );
11021 // %}
11022
11023 //----------SMARTSPILL RULES---------------------------------------------------
11024 // These must follow all instruction definitions as they use the names
11025 // defined in the instructions definitions.
11026 //
11027 // SPARC will probably not have any of these rules due to RISC instruction set.
11028
11029 //----------PIPELINE-----------------------------------------------------------
11030 // Rules which define the behavior of the target architectures pipeline.