1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright 2012, 2015 SAP AG. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "compiler/disassembler.hpp"
30 #include "memory/resourceArea.hpp"
31 #include "runtime/java.hpp"
32 #include "runtime/os.hpp"
33 #include "runtime/stubCodeGenerator.hpp"
34 #include "utilities/defaultStream.hpp"
35 #include "utilities/globalDefinitions.hpp"
36 #include "vm_version_ppc.hpp"
37
38 # include <sys/sysinfo.h>
39
40 int VM_Version::_features = VM_Version::unknown_m;
41 int VM_Version::_measured_cache_line_size = 32; // pessimistic init value
42 const char* VM_Version::_features_str = "";
43 bool VM_Version::_is_determine_features_test_running = false;
44
45
46 #define MSG(flag) \
47 if (flag && !FLAG_IS_DEFAULT(flag)) \
48 jio_fprintf(defaultStream::error_stream(), \
49 "warning: -XX:+" #flag " requires -XX:+UseSIGTRAP\n" \
50 " -XX:+" #flag " will be disabled!\n");
51
52 void VM_Version::initialize() {
53
54 // Test which instructions are supported and measure cache line size.
55 determine_features();
56
57 // If PowerArchitecturePPC64 hasn't been specified explicitly determine from features.
58 if (FLAG_IS_DEFAULT(PowerArchitecturePPC64)) {
59 if (VM_Version::has_lqarx()) {
60 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 8);
61 } else if (VM_Version::has_popcntw()) {
62 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 7);
63 } else if (VM_Version::has_cmpb()) {
64 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 6);
65 } else if (VM_Version::has_popcntb()) {
66 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 5);
67 } else {
68 FLAG_SET_ERGO(uintx, PowerArchitecturePPC64, 0);
69 }
70 }
71 guarantee(PowerArchitecturePPC64 == 0 || PowerArchitecturePPC64 == 5 ||
72 PowerArchitecturePPC64 == 6 || PowerArchitecturePPC64 == 7 ||
73 PowerArchitecturePPC64 == 8,
74 "PowerArchitecturePPC64 should be 0, 5, 6, 7, or 8");
75
76 // Power 8: Configure Data Stream Control Register.
77 if (PowerArchitecturePPC64 >= 8) {
78 config_dscr();
79 }
80
81 if (!UseSIGTRAP) {
82 MSG(TrapBasedICMissChecks);
83 MSG(TrapBasedNotEntrantChecks);
84 MSG(TrapBasedNullChecks);
85 FLAG_SET_ERGO(bool, TrapBasedNotEntrantChecks, false);
86 FLAG_SET_ERGO(bool, TrapBasedNullChecks, false);
87 FLAG_SET_ERGO(bool, TrapBasedICMissChecks, false);
88 }
89
90 #ifdef COMPILER2
91 if (!UseSIGTRAP) {
92 MSG(TrapBasedRangeChecks);
93 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
94 }
95
96 // On Power6 test for section size.
97 if (PowerArchitecturePPC64 == 6) {
98 determine_section_size();
99 // TODO: PPC port } else {
100 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
101 }
102
103 MaxVectorSize = 8;
104 #endif
105
106 // Create and print feature-string.
107 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
108 jio_snprintf(buf, sizeof(buf),
109 "ppc64%s%s%s%s%s%s%s%s%s%s%s%s",
110 (has_fsqrt() ? " fsqrt" : ""),
111 (has_isel() ? " isel" : ""),
112 (has_lxarxeh() ? " lxarxeh" : ""),
113 (has_cmpb() ? " cmpb" : ""),
114 //(has_mftgpr()? " mftgpr" : ""),
115 (has_popcntb() ? " popcntb" : ""),
116 (has_popcntw() ? " popcntw" : ""),
117 (has_fcfids() ? " fcfids" : ""),
118 (has_vand() ? " vand" : ""),
119 (has_lqarx() ? " lqarx" : ""),
120 (has_vcipher() ? " vcipher" : ""),
121 (has_vpmsumb() ? " vpmsumb" : ""),
122 (has_tcheck() ? " tcheck" : "")
123 // Make sure number of %s matches num_features!
124 );
125 _features_str = os::strdup(buf);
126 if (Verbose) {
127 print_features();
128 }
129
130 // PPC64 supports 8-byte compare-exchange operations (see
131 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
132 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
133 _supports_cx8 = true;
134
135 UseSSE = 0; // Only on x86 and x64
136
137 intx cache_line_size = _measured_cache_line_size;
138
139 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
140
141 if (AllocatePrefetchStyle == 4) {
142 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
143 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
144 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
145 } else {
146 if (cache_line_size > AllocatePrefetchStepSize) AllocatePrefetchStepSize = cache_line_size;
147 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 3; // Optimistic value.
148 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 3*cache_line_size; // Default is not defined?
149 }
150
151 assert(AllocatePrefetchLines > 0, "invalid value");
152 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
153 AllocatePrefetchLines = 1; // Conservative value.
154 }
155
156 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
157 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
158 }
159
160 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
161
162 if (UseCRC32Intrinsics) {
163 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
164 warning("CRC32 intrinsics are not available on this CPU");
165 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
166 }
167
168 // The AES intrinsic stubs require AES instruction support.
169 if (UseAES) {
170 warning("AES instructions are not available on this CPU");
171 FLAG_SET_DEFAULT(UseAES, false);
172 }
173 if (UseAESIntrinsics) {
174 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
175 warning("AES intrinsics are not available on this CPU");
176 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
177 }
178
179 if (UseSHA) {
180 warning("SHA instructions are not available on this CPU");
181 FLAG_SET_DEFAULT(UseSHA, false);
182 }
183 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
184 warning("SHA intrinsics are not available on this CPU");
185 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
186 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
187 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
188 }
189 // Adjust RTM (Restricted Transactional Memory) flags.
190 if (!has_tcheck() && UseRTMLocking) {
191 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
192 // setting during arguments processing. See use_biased_locking().
193 // VM_Version_init() is executed after UseBiasedLocking is used
194 // in Thread::allocate().
195 vm_exit_during_initialization("RTM instructions are not available on this CPU");
196 }
197
198 if (UseRTMLocking) {
199 #if INCLUDE_RTM_OPT
200 if (!UnlockExperimentalVMOptions) {
201 vm_exit_during_initialization("UseRTMLocking is only available as experimental option on this platform. "
202 "It must be enabled via -XX:+UnlockExperimentalVMOptions flag.");
203 } else {
204 warning("UseRTMLocking is only available as experimental option on this platform.");
205 }
206 if (!FLAG_IS_CMDLINE(UseRTMLocking)) {
207 // RTM locking should be used only for applications with
208 // high lock contention. For now we do not use it by default.
209 vm_exit_during_initialization("UseRTMLocking flag should be only set on command line");
210 }
211 if (!is_power_of_2(RTMTotalCountIncrRate)) {
212 warning("RTMTotalCountIncrRate must be a power of 2, resetting it to 64");
213 FLAG_SET_DEFAULT(RTMTotalCountIncrRate, 64);
214 }
215 if (RTMAbortRatio < 0 || RTMAbortRatio > 100) {
216 warning("RTMAbortRatio must be in the range 0 to 100, resetting it to 50");
217 FLAG_SET_DEFAULT(RTMAbortRatio, 50);
218 }
219 FLAG_SET_ERGO(bool, UseNewFastLockPPC64, false); // Does not implement TM.
220 guarantee(RTMSpinLoopCount > 0, "unsupported");
221 #else
222 // Only C2 does RTM locking optimization.
223 // Can't continue because UseRTMLocking affects UseBiasedLocking flag
224 // setting during arguments processing. See use_biased_locking().
225 vm_exit_during_initialization("RTM locking optimization is not supported in this VM");
226 #endif
227 } else { // !UseRTMLocking
228 if (UseRTMForStackLocks) {
229 if (!FLAG_IS_DEFAULT(UseRTMForStackLocks)) {
230 warning("UseRTMForStackLocks flag should be off when UseRTMLocking flag is off");
231 }
232 FLAG_SET_DEFAULT(UseRTMForStackLocks, false);
233 }
234 if (UseRTMDeopt) {
235 FLAG_SET_DEFAULT(UseRTMDeopt, false);
236 }
237 if (PrintPreciseRTMLockingStatistics) {
238 FLAG_SET_DEFAULT(PrintPreciseRTMLockingStatistics, false);
239 }
240 }
241
242 // This machine does not allow unaligned memory accesses
243 if (UseUnalignedAccesses) {
244 if (!FLAG_IS_DEFAULT(UseUnalignedAccesses))
245 warning("Unaligned memory access is not available on this CPU");
246 FLAG_SET_DEFAULT(UseUnalignedAccesses, false);
247 }
248 }
249
250 bool VM_Version::use_biased_locking() {
251 #if INCLUDE_RTM_OPT
252 // RTM locking is most useful when there is high lock contention and
253 // low data contention. With high lock contention the lock is usually
254 // inflated and biased locking is not suitable for that case.
255 // RTM locking code requires that biased locking is off.
256 // Note: we can't switch off UseBiasedLocking in get_processor_features()
257 // because it is used by Thread::allocate() which is called before
258 // VM_Version::initialize().
259 if (UseRTMLocking && UseBiasedLocking) {
260 if (FLAG_IS_DEFAULT(UseBiasedLocking)) {
261 FLAG_SET_DEFAULT(UseBiasedLocking, false);
262 } else {
263 warning("Biased locking is not supported with RTM locking; ignoring UseBiasedLocking flag." );
264 UseBiasedLocking = false;
265 }
266 }
267 #endif
268 return UseBiasedLocking;
269 }
270
271 void VM_Version::print_features() {
272 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size());
273 }
274
275 #ifdef COMPILER2
276 // Determine section size on power6: If section size is 8 instructions,
277 // there should be a difference between the two testloops of ~15 %. If
278 // no difference is detected the section is assumed to be 32 instructions.
279 void VM_Version::determine_section_size() {
280
281 int unroll = 80;
282
283 const int code_size = (2* unroll * 32 + 100)*BytesPerInstWord;
284
285 // Allocate space for the code.
286 ResourceMark rm;
287 CodeBuffer cb("detect_section_size", code_size, 0);
288 MacroAssembler* a = new MacroAssembler(&cb);
289
290 uint32_t *code = (uint32_t *)a->pc();
291 // Emit code.
292 void (*test1)() = (void(*)())(void *)a->function_entry();
293
294 Label l1;
295
296 a->li(R4, 1);
297 a->sldi(R4, R4, 28);
298 a->b(l1);
299 a->align(CodeEntryAlignment);
300
301 a->bind(l1);
302
303 for (int i = 0; i < unroll; i++) {
304 // Schleife 1
305 // ------- sector 0 ------------
306 // ;; 0
307 a->nop(); // 1
308 a->fpnop0(); // 2
309 a->fpnop1(); // 3
310 a->addi(R4,R4, -1); // 4
311
312 // ;; 1
313 a->nop(); // 5
314 a->fmr(F6, F6); // 6
315 a->fmr(F7, F7); // 7
316 a->endgroup(); // 8
317 // ------- sector 8 ------------
318
319 // ;; 2
320 a->nop(); // 9
321 a->nop(); // 10
322 a->fmr(F8, F8); // 11
323 a->fmr(F9, F9); // 12
324
325 // ;; 3
326 a->nop(); // 13
327 a->fmr(F10, F10); // 14
328 a->fmr(F11, F11); // 15
329 a->endgroup(); // 16
330 // -------- sector 16 -------------
331
332 // ;; 4
333 a->nop(); // 17
334 a->nop(); // 18
335 a->fmr(F15, F15); // 19
336 a->fmr(F16, F16); // 20
337
338 // ;; 5
339 a->nop(); // 21
340 a->fmr(F17, F17); // 22
341 a->fmr(F18, F18); // 23
342 a->endgroup(); // 24
343 // ------- sector 24 ------------
344
345 // ;; 6
346 a->nop(); // 25
347 a->nop(); // 26
348 a->fmr(F19, F19); // 27
349 a->fmr(F20, F20); // 28
350
351 // ;; 7
352 a->nop(); // 29
353 a->fmr(F21, F21); // 30
354 a->fmr(F22, F22); // 31
355 a->brnop0(); // 32
356
357 // ------- sector 32 ------------
358 }
359
360 // ;; 8
361 a->cmpdi(CCR0, R4, unroll); // 33
362 a->bge(CCR0, l1); // 34
363 a->blr();
364
365 // Emit code.
366 void (*test2)() = (void(*)())(void *)a->function_entry();
367 // uint32_t *code = (uint32_t *)a->pc();
368
369 Label l2;
370
371 a->li(R4, 1);
372 a->sldi(R4, R4, 28);
373 a->b(l2);
374 a->align(CodeEntryAlignment);
375
376 a->bind(l2);
377
378 for (int i = 0; i < unroll; i++) {
379 // Schleife 2
380 // ------- sector 0 ------------
381 // ;; 0
382 a->brnop0(); // 1
383 a->nop(); // 2
384 //a->cmpdi(CCR0, R4, unroll);
385 a->fpnop0(); // 3
386 a->fpnop1(); // 4
387 a->addi(R4,R4, -1); // 5
388
389 // ;; 1
390
391 a->nop(); // 6
392 a->fmr(F6, F6); // 7
393 a->fmr(F7, F7); // 8
394 // ------- sector 8 ---------------
395
396 // ;; 2
397 a->endgroup(); // 9
398
399 // ;; 3
400 a->nop(); // 10
401 a->nop(); // 11
402 a->fmr(F8, F8); // 12
403
404 // ;; 4
405 a->fmr(F9, F9); // 13
406 a->nop(); // 14
407 a->fmr(F10, F10); // 15
408
409 // ;; 5
410 a->fmr(F11, F11); // 16
411 // -------- sector 16 -------------
412
413 // ;; 6
414 a->endgroup(); // 17
415
416 // ;; 7
417 a->nop(); // 18
418 a->nop(); // 19
419 a->fmr(F15, F15); // 20
420
421 // ;; 8
422 a->fmr(F16, F16); // 21
423 a->nop(); // 22
424 a->fmr(F17, F17); // 23
425
426 // ;; 9
427 a->fmr(F18, F18); // 24
428 // -------- sector 24 -------------
429
430 // ;; 10
431 a->endgroup(); // 25
432
433 // ;; 11
434 a->nop(); // 26
435 a->nop(); // 27
436 a->fmr(F19, F19); // 28
437
438 // ;; 12
439 a->fmr(F20, F20); // 29
440 a->nop(); // 30
441 a->fmr(F21, F21); // 31
442
443 // ;; 13
444 a->fmr(F22, F22); // 32
445 }
446
447 // -------- sector 32 -------------
448 // ;; 14
449 a->cmpdi(CCR0, R4, unroll); // 33
450 a->bge(CCR0, l2); // 34
451
452 a->blr();
453 uint32_t *code_end = (uint32_t *)a->pc();
454 a->flush();
455
456 double loop1_seconds,loop2_seconds, rel_diff;
457 uint64_t start1, stop1;
458
459 start1 = os::current_thread_cpu_time(false);
460 (*test1)();
461 stop1 = os::current_thread_cpu_time(false);
462 loop1_seconds = (stop1- start1) / (1000 *1000 *1000.0);
463
464
465 start1 = os::current_thread_cpu_time(false);
466 (*test2)();
467 stop1 = os::current_thread_cpu_time(false);
468
469 loop2_seconds = (stop1 - start1) / (1000 *1000 *1000.0);
470
471 rel_diff = (loop2_seconds - loop1_seconds) / loop1_seconds *100;
472
473 if (PrintAssembly) {
474 ttyLocker ttyl;
475 tty->print_cr("Decoding section size detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
476 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
477 tty->print_cr("Time loop1 :%f", loop1_seconds);
478 tty->print_cr("Time loop2 :%f", loop2_seconds);
479 tty->print_cr("(time2 - time1) / time1 = %f %%", rel_diff);
480
481 if (rel_diff > 12.0) {
482 tty->print_cr("Section Size 8 Instructions");
483 } else{
484 tty->print_cr("Section Size 32 Instructions or Power5");
485 }
486 }
487
488 #if 0 // TODO: PPC port
489 // Set sector size (if not set explicitly).
490 if (FLAG_IS_DEFAULT(Power6SectorSize128PPC64)) {
491 if (rel_diff > 12.0) {
492 PdScheduling::power6SectorSize = 0x20;
493 } else {
494 PdScheduling::power6SectorSize = 0x80;
495 }
496 } else if (Power6SectorSize128PPC64) {
497 PdScheduling::power6SectorSize = 0x80;
498 } else {
499 PdScheduling::power6SectorSize = 0x20;
500 }
501 #endif
502 if (UsePower6SchedulerPPC64) Unimplemented();
503 }
504 #endif // COMPILER2
505
506 void VM_Version::determine_features() {
507 #if defined(ABI_ELFv2)
508 const int code_size = (num_features+1+2*7)*BytesPerInstWord; // TODO(asmundak): calculation is incorrect.
509 #else
510 // 7 InstWords for each call (function descriptor + blr instruction).
511 const int code_size = (num_features+1+2*7)*BytesPerInstWord;
512 #endif
513 int features = 0;
514
515 // create test area
516 enum { BUFFER_SIZE = 2*4*K }; // Needs to be >=2* max cache line size (cache line size can't exceed min page size).
517 char test_area[BUFFER_SIZE];
518 char *mid_of_test_area = &test_area[BUFFER_SIZE>>1];
519
520 // Allocate space for the code.
521 ResourceMark rm;
522 CodeBuffer cb("detect_cpu_features", code_size, 0);
523 MacroAssembler* a = new MacroAssembler(&cb);
524
525 // Must be set to true so we can generate the test code.
526 _features = VM_Version::all_features_m;
527
528 // Emit code.
529 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
530 uint32_t *code = (uint32_t *)a->pc();
531 // Don't use R0 in ldarx.
532 // Keep R3_ARG1 unmodified, it contains &field (see below).
533 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
534 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
535 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
536 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
537 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
538 a->cmpb(R7, R5, R6); // code[4] -> cmpb
539 a->popcntb(R7, R5); // code[5] -> popcntb
540 a->popcntw(R7, R5); // code[6] -> popcntw
541 a->fcfids(F3, F4); // code[7] -> fcfids
542 a->vand(VR0, VR0, VR0); // code[8] -> vand
543 a->lqarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[9] -> lqarx_m
544 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
545 a->vpmsumb(VR0, VR1, VR2); // code[11] -> vpmsumb
546 a->tcheck(0); // code[12] -> tcheck
547 a->blr();
548
549 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
550 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
551 a->dcbz(R3_ARG1); // R3_ARG1 = addr
552 a->blr();
553
554 uint32_t *code_end = (uint32_t *)a->pc();
555 a->flush();
556 _features = VM_Version::unknown_m;
557
558 // Print the detection code.
559 if (PrintAssembly) {
560 ttyLocker ttyl;
561 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
562 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
563 }
564
565 // Measure cache line size.
566 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
567 (*zero_cacheline_func_ptr)(mid_of_test_area); // Call function which executes dcbz to the middle.
568 int count = 0; // count zeroed bytes
569 for (int i = 0; i < BUFFER_SIZE; i++) if (test_area[i] == 0) count++;
570 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
571 _measured_cache_line_size = count;
572
573 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
574 VM_Version::_is_determine_features_test_running = true;
575 (*test)((address)mid_of_test_area, (uint64_t)0);
576 VM_Version::_is_determine_features_test_running = false;
577
578 // determine which instructions are legal.
579 int feature_cntr = 0;
580 if (code[feature_cntr++]) features |= fsqrt_m;
581 if (code[feature_cntr++]) features |= fsqrts_m;
582 if (code[feature_cntr++]) features |= isel_m;
583 if (code[feature_cntr++]) features |= lxarxeh_m;
584 if (code[feature_cntr++]) features |= cmpb_m;
585 if (code[feature_cntr++]) features |= popcntb_m;
586 if (code[feature_cntr++]) features |= popcntw_m;
587 if (code[feature_cntr++]) features |= fcfids_m;
588 if (code[feature_cntr++]) features |= vand_m;
589 if (code[feature_cntr++]) features |= lqarx_m;
590 if (code[feature_cntr++]) features |= vcipher_m;
591 if (code[feature_cntr++]) features |= vpmsumb_m;
592 if (code[feature_cntr++]) features |= tcheck_m;
593
594 // Print the detection code.
595 if (PrintAssembly) {
596 ttyLocker ttyl;
597 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
598 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
599 }
600
601 _features = features;
602 }
603
604 // Power 8: Configure Data Stream Control Register.
605 void VM_Version::config_dscr() {
606 assert(has_tcheck(), "Only execute on Power 8 or later!");
607
608 // 7 InstWords for each call (function descriptor + blr instruction).
609 const int code_size = (2+2*7)*BytesPerInstWord;
610
611 // Allocate space for the code.
612 ResourceMark rm;
613 CodeBuffer cb("config_dscr", code_size, 0);
614 MacroAssembler* a = new MacroAssembler(&cb);
615
616 // Emit code.
617 uint64_t (*get_dscr)() = (uint64_t(*)())(void *)a->emit_fd();
618 uint32_t *code = (uint32_t *)a->pc();
619 a->mfdscr(R3);
620 a->blr();
621
622 void (*set_dscr)(long) = (void(*)(long))(void *)a->emit_fd();
623 a->mtdscr(R3);
624 a->blr();
625
626 uint32_t *code_end = (uint32_t *)a->pc();
627 a->flush();
628
629 // Print the detection code.
630 if (PrintAssembly) {
631 ttyLocker ttyl;
632 tty->print_cr("Decoding dscr configuration stub at " INTPTR_FORMAT " before execution:", p2i(code));
633 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
634 }
635
636 // Apply the configuration if needed.
637 uint64_t dscr_val = (*get_dscr)();
638 if (Verbose) {
639 tty->print_cr("dscr value was 0x%lx" , dscr_val);
640 }
641 bool change_requested = false;
642 if (DSCR_PPC64 != (uintx)-1) {
643 dscr_val = DSCR_PPC64;
644 change_requested = true;
645 }
646 if (DSCR_DPFD_PPC64 <= 7) {
647 uint64_t mask = 0x7;
648 if ((dscr_val & mask) != DSCR_DPFD_PPC64) {
649 dscr_val = (dscr_val & ~mask) | (DSCR_DPFD_PPC64);
650 change_requested = true;
651 }
652 }
653 if (DSCR_URG_PPC64 <= 7) {
654 uint64_t mask = 0x7 << 6;
655 if ((dscr_val & mask) != DSCR_DPFD_PPC64 << 6) {
656 dscr_val = (dscr_val & ~mask) | (DSCR_URG_PPC64 << 6);
657 change_requested = true;
658 }
659 }
660 if (change_requested) {
661 (*set_dscr)(dscr_val);
662 if (Verbose) {
663 tty->print_cr("dscr was set to 0x%lx" , (*get_dscr)());
664 }
665 }
666 }
667
668 static int saved_features = 0;
669
670 void VM_Version::allow_all() {
671 saved_features = _features;
672 _features = all_features_m;
673 }
674
675 void VM_Version::revert() {
676 _features = saved_features;
677 }