38 emit_int32(x);
39 }
40
41 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
42 relocate(rtype);
43 emit_int32(x);
44 }
45
46 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
47 relocate(rspec);
48 emit_int32(x);
49 }
50
51 // Emit an address
52 inline address Assembler::emit_addr(const address addr) {
53 address start = pc();
54 emit_address(addr);
55 return start;
56 }
57
58 #if !defined(ABI_ELFv2)
59 // Emit a function descriptor with the specified entry point, TOC, and
60 // ENV. If the entry point is NULL, the descriptor will point just
61 // past the descriptor.
62 inline address Assembler::emit_fd(address entry, address toc, address env) {
63 FunctionDescriptor* fd = (FunctionDescriptor*)pc();
64
65 assert(sizeof(FunctionDescriptor) == 3*sizeof(address), "function descriptor size");
66
67 (void)emit_addr();
68 (void)emit_addr();
69 (void)emit_addr();
70
71 fd->set_entry(entry == NULL ? pc() : entry);
72 fd->set_toc(toc);
73 fd->set_env(env);
74
75 return (address)fd;
76 }
77 #endif
78
79 // Issue an illegal instruction. 0 is guaranteed to be an illegal instruction.
80 inline void Assembler::illtrap() { Assembler::emit_int32(0); }
81 inline bool Assembler::is_illtrap(int x) { return x == 0; }
82
83 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
84 inline void Assembler::addi( Register d, Register a, int si16) { assert(a != R0, "r0 not allowed"); addi_r0ok( d, a, si16); }
85 inline void Assembler::addis( Register d, Register a, int si16) { assert(a != R0, "r0 not allowed"); addis_r0ok(d, a, si16); }
86 inline void Assembler::addi_r0ok(Register d,Register a,int si16) { emit_int32(ADDI_OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
87 inline void Assembler::addis_r0ok(Register d,Register a,int si16) { emit_int32(ADDIS_OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
88 inline void Assembler::addic_( Register d, Register a, int si16) { emit_int32(ADDIC__OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
89 inline void Assembler::subfic( Register d, Register a, int si16) { emit_int32(SUBFIC_OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
90 inline void Assembler::add( Register d, Register a, Register b) { emit_int32(ADD_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
91 inline void Assembler::add_( Register d, Register a, Register b) { emit_int32(ADD_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
92 inline void Assembler::subf( Register d, Register a, Register b) { emit_int32(SUBF_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
93 inline void Assembler::sub( Register d, Register a, Register b) { subf(d, b, a); }
94 inline void Assembler::subf_( Register d, Register a, Register b) { emit_int32(SUBF_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
95 inline void Assembler::addc( Register d, Register a, Register b) { emit_int32(ADDC_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
96 inline void Assembler::addc_( Register d, Register a, Register b) { emit_int32(ADDC_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
97 inline void Assembler::subfc( Register d, Register a, Register b) { emit_int32(SUBFC_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
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38 emit_int32(x);
39 }
40
41 inline void Assembler::emit_data(int x, relocInfo::relocType rtype) {
42 relocate(rtype);
43 emit_int32(x);
44 }
45
46 inline void Assembler::emit_data(int x, RelocationHolder const& rspec) {
47 relocate(rspec);
48 emit_int32(x);
49 }
50
51 // Emit an address
52 inline address Assembler::emit_addr(const address addr) {
53 address start = pc();
54 emit_address(addr);
55 return start;
56 }
57
58 // Emit a function descriptor with the specified entry point, TOC, and
59 // ENV. If the entry point is NULL, the descriptor will point just
60 // past the descriptor.
61 // If we are running in a little-endian environment (i.e. if ABI_ELFv2 is
62 // defined) this function will emit no code and simply return the current PC)
63 inline address Assembler::emit_fd(address entry, address toc, address env) {
64 FunctionDescriptor* fd = (FunctionDescriptor*)pc();
65
66 #if !defined(ABI_ELFv2)
67 assert(sizeof(FunctionDescriptor) == 3*sizeof(address), "function descriptor size");
68
69 (void)emit_addr();
70 (void)emit_addr();
71 (void)emit_addr();
72
73 fd->set_entry(entry == NULL ? pc() : entry);
74 fd->set_toc(toc);
75 fd->set_env(env);
76 #endif
77
78 return (address)fd;
79 }
80
81 // Issue an illegal instruction. 0 is guaranteed to be an illegal instruction.
82 inline void Assembler::illtrap() { Assembler::emit_int32(0); }
83 inline bool Assembler::is_illtrap(int x) { return x == 0; }
84
85 // PPC 1, section 3.3.8, Fixed-Point Arithmetic Instructions
86 inline void Assembler::addi( Register d, Register a, int si16) { assert(a != R0, "r0 not allowed"); addi_r0ok( d, a, si16); }
87 inline void Assembler::addis( Register d, Register a, int si16) { assert(a != R0, "r0 not allowed"); addis_r0ok(d, a, si16); }
88 inline void Assembler::addi_r0ok(Register d,Register a,int si16) { emit_int32(ADDI_OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
89 inline void Assembler::addis_r0ok(Register d,Register a,int si16) { emit_int32(ADDIS_OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
90 inline void Assembler::addic_( Register d, Register a, int si16) { emit_int32(ADDIC__OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
91 inline void Assembler::subfic( Register d, Register a, int si16) { emit_int32(SUBFIC_OPCODE | rt(d) | ra(a) | simm(si16, 16)); }
92 inline void Assembler::add( Register d, Register a, Register b) { emit_int32(ADD_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
93 inline void Assembler::add_( Register d, Register a, Register b) { emit_int32(ADD_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
94 inline void Assembler::subf( Register d, Register a, Register b) { emit_int32(SUBF_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
95 inline void Assembler::sub( Register d, Register a, Register b) { subf(d, b, a); }
96 inline void Assembler::subf_( Register d, Register a, Register b) { emit_int32(SUBF_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
97 inline void Assembler::addc( Register d, Register a, Register b) { emit_int32(ADDC_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
98 inline void Assembler::addc_( Register d, Register a, Register b) { emit_int32(ADDC_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(1)); }
99 inline void Assembler::subfc( Register d, Register a, Register b) { emit_int32(SUBFC_OPCODE | rt(d) | ra(a) | rb(b) | oe(0) | rc(0)); }
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