1 /*
   2  * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/macroAssembler.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "memory/resourceArea.hpp"
  30 #include "runtime/java.hpp"
  31 #include "runtime/stubCodeGenerator.hpp"
  32 #include "vm_version_aarch64.hpp"
  33 #ifdef TARGET_OS_FAMILY_linux
  34 # include "os_linux.inline.hpp"
  35 #endif
  36 
  37 #ifndef BUILTIN_SIM
  38 #include <sys/auxv.h>
  39 #include <asm/hwcap.h>
  40 #else
  41 #define getauxval(hwcap) 0
  42 #endif
  43 
  44 #ifndef HWCAP_AES
  45 #define HWCAP_AES   (1<<3)
  46 #endif
  47 
  48 #ifndef HWCAP_PMULL
  49 #define HWCAP_PMULL (1<<4)
  50 #endif
  51 
  52 #ifndef HWCAP_SHA1
  53 #define HWCAP_SHA1  (1<<5)
  54 #endif
  55 
  56 #ifndef HWCAP_SHA2
  57 #define HWCAP_SHA2  (1<<6)
  58 #endif
  59 
  60 #ifndef HWCAP_CRC32
  61 #define HWCAP_CRC32 (1<<7)
  62 #endif
  63 
  64 int VM_Version::_cpu;
  65 int VM_Version::_model;
  66 int VM_Version::_model2;
  67 int VM_Version::_variant;
  68 int VM_Version::_revision;
  69 int VM_Version::_stepping;
  70 
  71 static BufferBlob* stub_blob;
  72 static const int stub_size = 550;
  73 
  74 extern "C" {
  75   typedef void (*getPsrInfo_stub_t)(void*);
  76 }
  77 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
  78 
  79 
  80 class VM_Version_StubGenerator: public StubCodeGenerator {
  81  public:
  82 
  83   VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
  84 
  85   address generate_getPsrInfo() {
  86     StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
  87 #   define __ _masm->
  88     address start = __ pc();
  89 
  90 #ifdef BUILTIN_SIM
  91     __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void);
  92 #endif
  93 
  94     // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
  95 
  96     address entry = __ pc();
  97 
  98     // TODO : redefine fields in CpuidInfo and generate
  99     // code to fill them in
 100 
 101     __ ret(lr);
 102 
 103 #   undef __
 104 
 105     return start;
 106   }
 107 };
 108 
 109 
 110 void VM_Version::get_processor_features() {
 111   _supports_cx8 = true;
 112   _supports_atomic_getset4 = true;
 113   _supports_atomic_getadd4 = true;
 114   _supports_atomic_getset8 = true;
 115   _supports_atomic_getadd8 = true;
 116 
 117   if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
 118     FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
 119   if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
 120     FLAG_SET_DEFAULT(AllocatePrefetchStepSize, 64);
 121   FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 256);
 122   FLAG_SET_DEFAULT(PrefetchFieldsAhead, 256);
 123   FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 256);
 124   FLAG_SET_DEFAULT(UseSSE42Intrinsics, true);
 125 
 126   unsigned long auxv = getauxval(AT_HWCAP);
 127 
 128   char buf[512];
 129 
 130   _features = auxv;
 131 
 132   int cpu_lines = 0;
 133   if (FILE *f = fopen("/proc/cpuinfo", "r")) {
 134     char buf[128], *p;
 135     while (fgets(buf, sizeof (buf), f) != NULL) {
 136       if (p = strchr(buf, ':')) {
 137         long v = strtol(p+1, NULL, 0);
 138         if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
 139           _cpu = v;
 140           cpu_lines++;
 141         } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
 142           _variant = v;
 143         } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
 144           if (_model != v)  _model2 = _model;
 145           _model = v;
 146         } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
 147           _revision = v;
 148         }
 149       }
 150     }
 151     fclose(f);
 152   }
 153 
 154   // Enable vendor specific features
 155   if (_cpu == CPU_CAVIUM && _variant == 0) _features |= CPU_DMB_ATOMICS;
 156   if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) _features |= CPU_A53MAC;
 157   // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
 158   // we assume the worst and assume we could be on a big little system and have
 159   // undisclosed A53 cores which we could be swapped to at any stage
 160   if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
 161 
 162   sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
 163   if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
 164   if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
 165   if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
 166   if (auxv & HWCAP_AES)   strcat(buf, ", aes");
 167   if (auxv & HWCAP_SHA1)  strcat(buf, ", sha1");
 168   if (auxv & HWCAP_SHA2)  strcat(buf, ", sha256");
 169 
 170   _features_string = os::strdup(buf);
 171 
 172   if (FLAG_IS_DEFAULT(UseCRC32)) {
 173     UseCRC32 = (auxv & HWCAP_CRC32) != 0;
 174   }
 175   if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
 176     warning("UseCRC32 specified, but not supported on this CPU");
 177   }
 178 
 179   if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
 180     FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
 181   }
 182 
 183   if (UseVectorizedMismatchIntrinsic) {
 184     warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
 185     FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
 186   }
 187 
 188   if (auxv & HWCAP_AES) {
 189     UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
 190     UseAESIntrinsics =
 191         UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
 192     if (UseAESIntrinsics && !UseAES) {
 193       warning("UseAESIntrinsics enabled, but UseAES not, enabling");
 194       UseAES = true;
 195     }
 196   } else {
 197     if (UseAES) {
 198       warning("UseAES specified, but not supported on this CPU");
 199     }
 200     if (UseAESIntrinsics) {
 201       warning("UseAESIntrinsics specified, but not supported on this CPU");
 202     }
 203   }
 204 
 205   if (UseAESCTRIntrinsics) {
 206     warning("AES/CTR intrinsics are not available on this CPU");
 207     FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
 208   }
 209 
 210   if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
 211     UseCRC32Intrinsics = true;
 212   }
 213 
 214   if (auxv & HWCAP_CRC32) {
 215     if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
 216       FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
 217     }
 218   } else if (UseCRC32CIntrinsics) {
 219     warning("CRC32C is not available on the CPU");
 220     FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
 221   }
 222 
 223   if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
 224     if (FLAG_IS_DEFAULT(UseSHA)) {
 225       FLAG_SET_DEFAULT(UseSHA, true);
 226     }
 227   } else if (UseSHA) {
 228     warning("SHA instructions are not available on this CPU");
 229     FLAG_SET_DEFAULT(UseSHA, false);
 230   }
 231 
 232   if (UseSHA && (auxv & HWCAP_SHA1)) {
 233     if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
 234       FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
 235     }
 236   } else if (UseSHA1Intrinsics) {
 237     warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
 238     FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
 239   }
 240 
 241   if (UseSHA && (auxv & HWCAP_SHA2)) {
 242     if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
 243       FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
 244     }
 245   } else if (UseSHA256Intrinsics) {
 246     warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
 247     FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
 248   }
 249 
 250   if (UseSHA512Intrinsics) {
 251     warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
 252     FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
 253   }
 254 
 255   if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
 256     FLAG_SET_DEFAULT(UseSHA, false);
 257   }
 258 
 259   if (auxv & HWCAP_PMULL) {
 260     if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
 261       FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
 262     }
 263   } else if (UseGHASHIntrinsics) {
 264     warning("GHASH intrinsics are not available on this CPU");
 265     FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
 266   }
 267 
 268   // This machine allows unaligned memory accesses
 269   if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
 270     FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
 271   }
 272 
 273   if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
 274     UseMultiplyToLenIntrinsic = true;
 275   }
 276 
 277   if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
 278     UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
 279   }
 280 
 281   if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
 282     UsePopCountInstruction = true;
 283   }
 284 
 285   if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
 286     UseMontgomeryMultiplyIntrinsic = true;
 287   }
 288   if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
 289     UseMontgomerySquareIntrinsic = true;
 290   }
 291 
 292 #ifdef COMPILER2
 293   if (FLAG_IS_DEFAULT(OptoScheduling)) {
 294     OptoScheduling = true;
 295   }
 296 #endif
 297 }
 298 
 299 void VM_Version::initialize() {
 300   ResourceMark rm;
 301 
 302   stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
 303   if (stub_blob == NULL) {
 304     vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
 305   }
 306 
 307   CodeBuffer c(stub_blob);
 308   VM_Version_StubGenerator g(&c);
 309   getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
 310                                    g.generate_getPsrInfo());
 311 
 312   get_processor_features();
 313 }