1 /*
2 * Copyright (c) 1997, 2015, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "vm_version_aarch64.hpp"
33 #ifdef TARGET_OS_FAMILY_linux
34 # include "os_linux.inline.hpp"
35 #endif
36
37 #ifndef BUILTIN_SIM
38 #include <sys/auxv.h>
39 #include <asm/hwcap.h>
40 #else
41 #define getauxval(hwcap) 0
42 #endif
43
44 #ifndef HWCAP_AES
45 #define HWCAP_AES (1<<3)
46 #endif
47
48 #ifndef HWCAP_PMULL
49 #define HWCAP_PMULL (1<<4)
50 #endif
51
52 #ifndef HWCAP_SHA1
53 #define HWCAP_SHA1 (1<<5)
54 #endif
55
56 #ifndef HWCAP_SHA2
57 #define HWCAP_SHA2 (1<<6)
58 #endif
59
60 #ifndef HWCAP_CRC32
61 #define HWCAP_CRC32 (1<<7)
62 #endif
63
64 int VM_Version::_cpu;
65 int VM_Version::_model;
66 int VM_Version::_model2;
67 int VM_Version::_variant;
68 int VM_Version::_revision;
69 int VM_Version::_stepping;
70
71 static BufferBlob* stub_blob;
72 static const int stub_size = 550;
73
74 extern "C" {
75 typedef void (*getPsrInfo_stub_t)(void*);
76 }
77 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
78
79
80 class VM_Version_StubGenerator: public StubCodeGenerator {
81 public:
82
83 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
84
85 address generate_getPsrInfo() {
86 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
87 # define __ _masm->
88 address start = __ pc();
89
90 #ifdef BUILTIN_SIM
91 __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void);
92 #endif
93
94 // void getPsrInfo(VM_Version::CpuidInfo* cpuid_info);
95
96 address entry = __ pc();
97
98 // TODO : redefine fields in CpuidInfo and generate
99 // code to fill them in
100
101 __ ret(lr);
102
103 # undef __
104
105 return start;
106 }
107 };
108
109
110 void VM_Version::get_processor_features() {
111 _supports_cx8 = true;
112 _supports_atomic_getset4 = true;
113 _supports_atomic_getadd4 = true;
114 _supports_atomic_getset8 = true;
115 _supports_atomic_getadd8 = true;
116
117 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
118 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 256);
119 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
120 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, 64);
121 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 256);
122 FLAG_SET_DEFAULT(PrefetchFieldsAhead, 256);
123 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 256);
124
125 unsigned long auxv = getauxval(AT_HWCAP);
126
127 char buf[512];
128
129 _features = auxv;
130
131 int cpu_lines = 0;
132 if (FILE *f = fopen("/proc/cpuinfo", "r")) {
133 char buf[128], *p;
134 while (fgets(buf, sizeof (buf), f) != NULL) {
135 if (p = strchr(buf, ':')) {
136 long v = strtol(p+1, NULL, 0);
137 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
138 _cpu = v;
139 cpu_lines++;
140 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
141 _variant = v;
142 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
143 if (_model != v) _model2 = _model;
144 _model = v;
145 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
146 _revision = v;
147 }
148 }
149 }
150 fclose(f);
151 }
152
153 // Enable vendor specific features
154 if (_cpu == CPU_CAVIUM && _variant == 0) _features |= CPU_DMB_ATOMICS;
155 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) _features |= CPU_A53MAC;
156 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
157 // we assume the worst and assume we could be on a big little system and have
158 // undisclosed A53 cores which we could be swapped to at any stage
159 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
160
161 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
162 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
163 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
164 if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
165 if (auxv & HWCAP_AES) strcat(buf, ", aes");
166 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
167 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
168
169 _features_string = os::strdup(buf);
170
171 if (FLAG_IS_DEFAULT(UseCRC32)) {
172 UseCRC32 = (auxv & HWCAP_CRC32) != 0;
173 }
174 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
175 warning("UseCRC32 specified, but not supported on this CPU");
176 }
177
178 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
179 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
180 }
181
182 if (UseVectorizedMismatchIntrinsic) {
183 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
184 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
185 }
186
187 if (auxv & HWCAP_AES) {
188 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
189 UseAESIntrinsics =
190 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
191 if (UseAESIntrinsics && !UseAES) {
192 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
193 UseAES = true;
194 }
195 } else {
196 if (UseAES) {
197 warning("UseAES specified, but not supported on this CPU");
198 }
199 if (UseAESIntrinsics) {
200 warning("UseAESIntrinsics specified, but not supported on this CPU");
201 }
202 }
203
204 if (UseAESCTRIntrinsics) {
205 warning("AES/CTR intrinsics are not available on this CPU");
206 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
207 }
208
209 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
210 UseCRC32Intrinsics = true;
211 }
212
213 if (auxv & HWCAP_CRC32) {
214 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
215 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
216 }
217 } else if (UseCRC32CIntrinsics) {
218 warning("CRC32C is not available on the CPU");
219 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
220 }
221
222 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
223 if (FLAG_IS_DEFAULT(UseSHA)) {
224 FLAG_SET_DEFAULT(UseSHA, true);
225 }
226 } else if (UseSHA) {
227 warning("SHA instructions are not available on this CPU");
228 FLAG_SET_DEFAULT(UseSHA, false);
229 }
230
231 if (UseSHA && (auxv & HWCAP_SHA1)) {
232 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
233 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
234 }
235 } else if (UseSHA1Intrinsics) {
236 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
237 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
238 }
239
240 if (UseSHA && (auxv & HWCAP_SHA2)) {
241 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
242 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
243 }
244 } else if (UseSHA256Intrinsics) {
245 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
246 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
247 }
248
249 if (UseSHA512Intrinsics) {
250 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
251 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
252 }
253
254 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
255 FLAG_SET_DEFAULT(UseSHA, false);
256 }
257
258 if (auxv & HWCAP_PMULL) {
259 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
260 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
261 }
262 } else if (UseGHASHIntrinsics) {
263 warning("GHASH intrinsics are not available on this CPU");
264 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
265 }
266
267 // This machine allows unaligned memory accesses
268 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
269 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
270 }
271
272 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
273 UseMultiplyToLenIntrinsic = true;
274 }
275
276 if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
277 UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
278 }
279
280 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
281 UsePopCountInstruction = true;
282 }
283
284 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
285 UseMontgomeryMultiplyIntrinsic = true;
286 }
287 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
288 UseMontgomerySquareIntrinsic = true;
289 }
290
291 #ifdef COMPILER2
292 if (FLAG_IS_DEFAULT(OptoScheduling)) {
293 OptoScheduling = true;
294 }
295 #endif
296 }
297
298 void VM_Version::initialize() {
299 ResourceMark rm;
300
301 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
302 if (stub_blob == NULL) {
303 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
304 }
305
306 CodeBuffer c(stub_blob);
307 VM_Version_StubGenerator g(&c);
308 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
309 g.generate_getPsrInfo());
310
311 get_processor_features();
312 }