85
86 #ifdef COMPILER2
87 if (!UseSIGTRAP) {
88 MSG(TrapBasedRangeChecks);
89 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
90 }
91
92 // On Power6 test for section size.
93 if (PowerArchitecturePPC64 == 6) {
94 determine_section_size();
95 // TODO: PPC port } else {
96 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
97 }
98
99 MaxVectorSize = 8;
100 #endif
101
102 // Create and print feature-string.
103 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
104 jio_snprintf(buf, sizeof(buf),
105 "ppc64%s%s%s%s%s%s%s%s",
106 (has_fsqrt() ? " fsqrt" : ""),
107 (has_isel() ? " isel" : ""),
108 (has_lxarxeh() ? " lxarxeh" : ""),
109 (has_cmpb() ? " cmpb" : ""),
110 //(has_mftgpr()? " mftgpr" : ""),
111 (has_popcntb() ? " popcntb" : ""),
112 (has_popcntw() ? " popcntw" : ""),
113 (has_fcfids() ? " fcfids" : ""),
114 (has_vand() ? " vand" : "")
115 // Make sure number of %s matches num_features!
116 );
117 _features_str = strdup(buf);
118 NOT_PRODUCT(if (Verbose) print_features(););
119
120 // PPC64 supports 8-byte compare-exchange operations (see
121 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
122 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
123 _supports_cx8 = true;
124
125 UseSSE = 0; // Only on x86 and x64
126
127 intx cache_line_size = _measured_cache_line_size;
128
129 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
130
131 if (AllocatePrefetchStyle == 4) {
132 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
133 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
134 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
139 }
140
141 assert(AllocatePrefetchLines > 0, "invalid value");
142 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
143 AllocatePrefetchLines = 1; // Conservative value.
144 }
145
146 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
147 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
148 }
149
150 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
151
152 if (UseCRC32Intrinsics) {
153 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
154 warning("CRC32 intrinsics are not available on this CPU");
155 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
156 }
157
158 // The AES intrinsic stubs require AES instruction support.
159 if (UseAES) {
160 warning("AES instructions are not available on this CPU");
161 FLAG_SET_DEFAULT(UseAES, false);
162 }
163 if (UseAESIntrinsics) {
164 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
165 warning("AES intrinsics are not available on this CPU");
166 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
167 }
168
169 if (UseSHA) {
170 warning("SHA instructions are not available on this CPU");
171 FLAG_SET_DEFAULT(UseSHA, false);
172 }
173 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
174 warning("SHA intrinsics are not available on this CPU");
175 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
176 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
177 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
178 }
179
180 }
181
182 void VM_Version::print_features() {
183 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size());
184 }
185
186 #ifdef COMPILER2
187 // Determine section size on power6: If section size is 8 instructions,
435
436 // Must be set to true so we can generate the test code.
437 _features = VM_Version::all_features_m;
438
439 // Emit code.
440 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
441 uint32_t *code = (uint32_t *)a->pc();
442 // Don't use R0 in ldarx.
443 // Keep R3_ARG1 unmodified, it contains &field (see below).
444 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
445 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
446 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
447 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
448 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
449 a->cmpb(R7, R5, R6); // code[4] -> bcmp
450 //a->mftgpr(R7, F3); // code[5] -> mftgpr
451 a->popcntb(R7, R5); // code[6] -> popcntb
452 a->popcntw(R7, R5); // code[7] -> popcntw
453 a->fcfids(F3, F4); // code[8] -> fcfids
454 a->vand(VR0, VR0, VR0); // code[9] -> vand
455 a->blr();
456
457 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
458 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
459 a->dcbz(R3_ARG1); // R3_ARG1 = addr
460 a->blr();
461
462 uint32_t *code_end = (uint32_t *)a->pc();
463 a->flush();
464 _features = VM_Version::unknown_m;
465
466 // Print the detection code.
467 if (PrintAssembly) {
468 ttyLocker ttyl;
469 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
470 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
471 }
472
473 // Measure cache line size.
474 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
478 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
479 _measured_cache_line_size = count;
480
481 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
482 VM_Version::_is_determine_features_test_running = true;
483 (*test)((address)mid_of_test_area, (uint64_t)0);
484 VM_Version::_is_determine_features_test_running = false;
485
486 // determine which instructions are legal.
487 int feature_cntr = 0;
488 if (code[feature_cntr++]) features |= fsqrt_m;
489 if (code[feature_cntr++]) features |= fsqrts_m;
490 if (code[feature_cntr++]) features |= isel_m;
491 if (code[feature_cntr++]) features |= lxarxeh_m;
492 if (code[feature_cntr++]) features |= cmpb_m;
493 //if(code[feature_cntr++])features |= mftgpr_m;
494 if (code[feature_cntr++]) features |= popcntb_m;
495 if (code[feature_cntr++]) features |= popcntw_m;
496 if (code[feature_cntr++]) features |= fcfids_m;
497 if (code[feature_cntr++]) features |= vand_m;
498
499 // Print the detection code.
500 if (PrintAssembly) {
501 ttyLocker ttyl;
502 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
503 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
504 }
505
506 _features = features;
507 }
508
509
510 static int saved_features = 0;
511
512 void VM_Version::allow_all() {
513 saved_features = _features;
514 _features = all_features_m;
515 }
516
517 void VM_Version::revert() {
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85
86 #ifdef COMPILER2
87 if (!UseSIGTRAP) {
88 MSG(TrapBasedRangeChecks);
89 FLAG_SET_ERGO(bool, TrapBasedRangeChecks, false);
90 }
91
92 // On Power6 test for section size.
93 if (PowerArchitecturePPC64 == 6) {
94 determine_section_size();
95 // TODO: PPC port } else {
96 // TODO: PPC port PdScheduling::power6SectorSize = 0x20;
97 }
98
99 MaxVectorSize = 8;
100 #endif
101
102 // Create and print feature-string.
103 char buf[(num_features+1) * 16]; // Max 16 chars per feature.
104 jio_snprintf(buf, sizeof(buf),
105 "ppc64%s%s%s%s%s%s%s%s%s",
106 (has_fsqrt() ? " fsqrt" : ""),
107 (has_isel() ? " isel" : ""),
108 (has_lxarxeh() ? " lxarxeh" : ""),
109 (has_cmpb() ? " cmpb" : ""),
110 //(has_mftgpr()? " mftgpr" : ""),
111 (has_popcntb() ? " popcntb" : ""),
112 (has_popcntw() ? " popcntw" : ""),
113 (has_fcfids() ? " fcfids" : ""),
114 (has_vand() ? " vand" : ""),
115 (has_vcipher() ? " aes" : "")
116 // Make sure number of %s matches num_features!
117 );
118 _features_str = strdup(buf);
119 NOT_PRODUCT(if (Verbose) print_features(););
120
121 // PPC64 supports 8-byte compare-exchange operations (see
122 // Atomic::cmpxchg and StubGenerator::generate_atomic_cmpxchg_ptr)
123 // and 'atomic long memory ops' (see Unsafe_GetLongVolatile).
124 _supports_cx8 = true;
125
126 UseSSE = 0; // Only on x86 and x64
127
128 intx cache_line_size = _measured_cache_line_size;
129
130 if (FLAG_IS_DEFAULT(AllocatePrefetchStyle)) AllocatePrefetchStyle = 1;
131
132 if (AllocatePrefetchStyle == 4) {
133 AllocatePrefetchStepSize = cache_line_size; // Need exact value.
134 if (FLAG_IS_DEFAULT(AllocatePrefetchLines)) AllocatePrefetchLines = 12; // Use larger blocks by default.
135 if (AllocatePrefetchDistance < 0) AllocatePrefetchDistance = 2*cache_line_size; // Default is not defined?
140 }
141
142 assert(AllocatePrefetchLines > 0, "invalid value");
143 if (AllocatePrefetchLines < 1) { // Set valid value in product VM.
144 AllocatePrefetchLines = 1; // Conservative value.
145 }
146
147 if (AllocatePrefetchStyle == 3 && AllocatePrefetchDistance < cache_line_size) {
148 AllocatePrefetchStyle = 1; // Fall back if inappropriate.
149 }
150
151 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
152
153 if (UseCRC32Intrinsics) {
154 if (!FLAG_IS_DEFAULT(UseCRC32Intrinsics))
155 warning("CRC32 intrinsics are not available on this CPU");
156 FLAG_SET_DEFAULT(UseCRC32Intrinsics, false);
157 }
158
159 // The AES intrinsic stubs require AES instruction support.
160 #if defined(VM_LITTLE_ENDIAN)
161 if (has_vcipher()) {
162 if (FLAG_IS_DEFAULT(UseAES)) {
163 UseAES = true;
164 }
165 } else if (UseAES) {
166 if (!FLAG_IS_DEFAULT(UseAES))
167 warning("AES instructions are not available on this CPU");
168 FLAG_SET_DEFAULT(UseAES, false);
169 }
170
171 if (UseAES && has_vcipher()) {
172 if (FLAG_IS_DEFAULT(UseAESIntrinsics)) {
173 UseAESIntrinsics = true;
174 }
175 } else if (UseAESIntrinsics) {
176 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
177 warning("AES intrinsics are not available on this CPU");
178 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
179 }
180
181 #else
182 if (UseAES) {
183 warning("AES instructions are not available on this CPU");
184 FLAG_SET_DEFAULT(UseAES, false);
185 }
186 if (UseAESIntrinsics) {
187 if (!FLAG_IS_DEFAULT(UseAESIntrinsics))
188 warning("AES intrinsics are not available on this CPU");
189 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
190 }
191 #endif
192
193 if (UseSHA) {
194 warning("SHA instructions are not available on this CPU");
195 FLAG_SET_DEFAULT(UseSHA, false);
196 }
197 if (UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics) {
198 warning("SHA intrinsics are not available on this CPU");
199 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
200 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
201 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
202 }
203
204 }
205
206 void VM_Version::print_features() {
207 tty->print_cr("Version: %s cache_line_size = %d", cpu_features(), (int) get_cache_line_size());
208 }
209
210 #ifdef COMPILER2
211 // Determine section size on power6: If section size is 8 instructions,
459
460 // Must be set to true so we can generate the test code.
461 _features = VM_Version::all_features_m;
462
463 // Emit code.
464 void (*test)(address addr, uint64_t offset)=(void(*)(address addr, uint64_t offset))(void *)a->function_entry();
465 uint32_t *code = (uint32_t *)a->pc();
466 // Don't use R0 in ldarx.
467 // Keep R3_ARG1 unmodified, it contains &field (see below).
468 // Keep R4_ARG2 unmodified, it contains offset = 0 (see below).
469 a->fsqrt(F3, F4); // code[0] -> fsqrt_m
470 a->fsqrts(F3, F4); // code[1] -> fsqrts_m
471 a->isel(R7, R5, R6, 0); // code[2] -> isel_m
472 a->ldarx_unchecked(R7, R3_ARG1, R4_ARG2, 1); // code[3] -> lxarx_m
473 a->cmpb(R7, R5, R6); // code[4] -> bcmp
474 //a->mftgpr(R7, F3); // code[5] -> mftgpr
475 a->popcntb(R7, R5); // code[6] -> popcntb
476 a->popcntw(R7, R5); // code[7] -> popcntw
477 a->fcfids(F3, F4); // code[8] -> fcfids
478 a->vand(VR0, VR0, VR0); // code[9] -> vand
479 a->vcipher(VR0, VR1, VR2); // code[10] -> vcipher
480 a->blr();
481
482 // Emit function to set one cache line to zero. Emit function descriptor and get pointer to it.
483 void (*zero_cacheline_func_ptr)(char*) = (void(*)(char*))(void *)a->function_entry();
484 a->dcbz(R3_ARG1); // R3_ARG1 = addr
485 a->blr();
486
487 uint32_t *code_end = (uint32_t *)a->pc();
488 a->flush();
489 _features = VM_Version::unknown_m;
490
491 // Print the detection code.
492 if (PrintAssembly) {
493 ttyLocker ttyl;
494 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " before execution:", p2i(code));
495 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
496 }
497
498 // Measure cache line size.
499 memset(test_area, 0xFF, BUFFER_SIZE); // Fill test area with 0xFF.
503 guarantee(is_power_of_2(count), "cache line size needs to be a power of 2");
504 _measured_cache_line_size = count;
505
506 // Execute code. Illegal instructions will be replaced by 0 in the signal handler.
507 VM_Version::_is_determine_features_test_running = true;
508 (*test)((address)mid_of_test_area, (uint64_t)0);
509 VM_Version::_is_determine_features_test_running = false;
510
511 // determine which instructions are legal.
512 int feature_cntr = 0;
513 if (code[feature_cntr++]) features |= fsqrt_m;
514 if (code[feature_cntr++]) features |= fsqrts_m;
515 if (code[feature_cntr++]) features |= isel_m;
516 if (code[feature_cntr++]) features |= lxarxeh_m;
517 if (code[feature_cntr++]) features |= cmpb_m;
518 //if(code[feature_cntr++])features |= mftgpr_m;
519 if (code[feature_cntr++]) features |= popcntb_m;
520 if (code[feature_cntr++]) features |= popcntw_m;
521 if (code[feature_cntr++]) features |= fcfids_m;
522 if (code[feature_cntr++]) features |= vand_m;
523 if (code[feature_cntr++]) features |= vcipher_m;
524
525 // Print the detection code.
526 if (PrintAssembly) {
527 ttyLocker ttyl;
528 tty->print_cr("Decoding cpu-feature detection stub at " INTPTR_FORMAT " after execution:", p2i(code));
529 Disassembler::decode((u_char*)code, (u_char*)code_end, tty);
530 }
531
532 _features = features;
533 }
534
535
536 static int saved_features = 0;
537
538 void VM_Version::allow_all() {
539 saved_features = _features;
540 _features = all_features_m;
541 }
542
543 void VM_Version::revert() {
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