1 /*
   2  * Copyright (c) 2016, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2016, 2017, SAP SE. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #include "precompiled.hpp"
  27 #include "asm/codeBuffer.hpp"
  28 #include "asm/macroAssembler.inline.hpp"
  29 #include "compiler/disassembler.hpp"
  30 #include "gc/shared/collectedHeap.inline.hpp"
  31 #include "interpreter/interpreter.hpp"
  32 #include "gc/shared/cardTableModRefBS.hpp"
  33 #include "memory/resourceArea.hpp"
  34 #include "memory/universe.hpp"
  35 #include "oops/klass.inline.hpp"
  36 #include "opto/compile.hpp"
  37 #include "opto/intrinsicnode.hpp"
  38 #include "opto/matcher.hpp"
  39 #include "prims/methodHandles.hpp"
  40 #include "registerSaver_s390.hpp"
  41 #include "runtime/biasedLocking.hpp"
  42 #include "runtime/icache.hpp"
  43 #include "runtime/interfaceSupport.hpp"
  44 #include "runtime/objectMonitor.hpp"
  45 #include "runtime/os.hpp"
  46 #include "runtime/sharedRuntime.hpp"
  47 #include "runtime/stubRoutines.hpp"
  48 #include "utilities/events.hpp"
  49 #include "utilities/macros.hpp"
  50 #if INCLUDE_ALL_GCS
  51 #include "gc/g1/g1CollectedHeap.inline.hpp"
  52 #include "gc/g1/g1SATBCardTableModRefBS.hpp"
  53 #include "gc/g1/heapRegion.hpp"
  54 #endif
  55 
  56 #include <ucontext.h>
  57 
  58 #define BLOCK_COMMENT(str) block_comment(str)
  59 #define BIND(label)        bind(label); BLOCK_COMMENT(#label ":")
  60 
  61 // Move 32-bit register if destination and source are different.
  62 void MacroAssembler::lr_if_needed(Register rd, Register rs) {
  63   if (rs != rd) { z_lr(rd, rs); }
  64 }
  65 
  66 // Move register if destination and source are different.
  67 void MacroAssembler::lgr_if_needed(Register rd, Register rs) {
  68   if (rs != rd) { z_lgr(rd, rs); }
  69 }
  70 
  71 // Zero-extend 32-bit register into 64-bit register if destination and source are different.
  72 void MacroAssembler::llgfr_if_needed(Register rd, Register rs) {
  73   if (rs != rd) { z_llgfr(rd, rs); }
  74 }
  75 
  76 // Move float register if destination and source are different.
  77 void MacroAssembler::ldr_if_needed(FloatRegister rd, FloatRegister rs) {
  78   if (rs != rd) { z_ldr(rd, rs); }
  79 }
  80 
  81 // Move integer register if destination and source are different.
  82 // It is assumed that shorter-than-int types are already
  83 // appropriately sign-extended.
  84 void MacroAssembler::move_reg_if_needed(Register dst, BasicType dst_type, Register src,
  85                                         BasicType src_type) {
  86   assert((dst_type != T_FLOAT) && (dst_type != T_DOUBLE), "use move_freg for float types");
  87   assert((src_type != T_FLOAT) && (src_type != T_DOUBLE), "use move_freg for float types");
  88 
  89   if (dst_type == src_type) {
  90     lgr_if_needed(dst, src); // Just move all 64 bits.
  91     return;
  92   }
  93 
  94   switch (dst_type) {
  95     // Do not support these types for now.
  96     //  case T_BOOLEAN:
  97     case T_BYTE:  // signed byte
  98       switch (src_type) {
  99         case T_INT:
 100           z_lgbr(dst, src);
 101           break;
 102         default:
 103           ShouldNotReachHere();
 104       }
 105       return;
 106 
 107     case T_CHAR:
 108     case T_SHORT:
 109       switch (src_type) {
 110         case T_INT:
 111           if (dst_type == T_CHAR) {
 112             z_llghr(dst, src);
 113           } else {
 114             z_lghr(dst, src);
 115           }
 116           break;
 117         default:
 118           ShouldNotReachHere();
 119       }
 120       return;
 121 
 122     case T_INT:
 123       switch (src_type) {
 124         case T_BOOLEAN:
 125         case T_BYTE:
 126         case T_CHAR:
 127         case T_SHORT:
 128         case T_INT:
 129         case T_LONG:
 130         case T_OBJECT:
 131         case T_ARRAY:
 132         case T_VOID:
 133         case T_ADDRESS:
 134           lr_if_needed(dst, src);
 135           // llgfr_if_needed(dst, src);  // zero-extend (in case we need to find a bug).
 136           return;
 137 
 138         default:
 139           assert(false, "non-integer src type");
 140           return;
 141       }
 142     case T_LONG:
 143       switch (src_type) {
 144         case T_BOOLEAN:
 145         case T_BYTE:
 146         case T_CHAR:
 147         case T_SHORT:
 148         case T_INT:
 149           z_lgfr(dst, src); // sign extension
 150           return;
 151 
 152         case T_LONG:
 153         case T_OBJECT:
 154         case T_ARRAY:
 155         case T_VOID:
 156         case T_ADDRESS:
 157           lgr_if_needed(dst, src);
 158           return;
 159 
 160         default:
 161           assert(false, "non-integer src type");
 162           return;
 163       }
 164       return;
 165     case T_OBJECT:
 166     case T_ARRAY:
 167     case T_VOID:
 168     case T_ADDRESS:
 169       switch (src_type) {
 170         // These types don't make sense to be converted to pointers:
 171         //      case T_BOOLEAN:
 172         //      case T_BYTE:
 173         //      case T_CHAR:
 174         //      case T_SHORT:
 175 
 176         case T_INT:
 177           z_llgfr(dst, src); // zero extension
 178           return;
 179 
 180         case T_LONG:
 181         case T_OBJECT:
 182         case T_ARRAY:
 183         case T_VOID:
 184         case T_ADDRESS:
 185           lgr_if_needed(dst, src);
 186           return;
 187 
 188         default:
 189           assert(false, "non-integer src type");
 190           return;
 191       }
 192       return;
 193     default:
 194       assert(false, "non-integer dst type");
 195       return;
 196   }
 197 }
 198 
 199 // Move float register if destination and source are different.
 200 void MacroAssembler::move_freg_if_needed(FloatRegister dst, BasicType dst_type,
 201                                          FloatRegister src, BasicType src_type) {
 202   assert((dst_type == T_FLOAT) || (dst_type == T_DOUBLE), "use move_reg for int types");
 203   assert((src_type == T_FLOAT) || (src_type == T_DOUBLE), "use move_reg for int types");
 204   if (dst_type == src_type) {
 205     ldr_if_needed(dst, src); // Just move all 64 bits.
 206   } else {
 207     switch (dst_type) {
 208       case T_FLOAT:
 209         assert(src_type == T_DOUBLE, "invalid float type combination");
 210         z_ledbr(dst, src);
 211         return;
 212       case T_DOUBLE:
 213         assert(src_type == T_FLOAT, "invalid float type combination");
 214         z_ldebr(dst, src);
 215         return;
 216       default:
 217         assert(false, "non-float dst type");
 218         return;
 219     }
 220   }
 221 }
 222 
 223 // Optimized emitter for reg to mem operations.
 224 // Uses modern instructions if running on modern hardware, classic instructions
 225 // otherwise. Prefers (usually shorter) classic instructions if applicable.
 226 // Data register (reg) cannot be used as work register.
 227 //
 228 // Don't rely on register locking, instead pass a scratch register (Z_R0 by default).
 229 // CAUTION! Passing registers >= Z_R2 may produce bad results on old CPUs!
 230 void MacroAssembler::freg2mem_opt(FloatRegister reg,
 231                                   int64_t       disp,
 232                                   Register      index,
 233                                   Register      base,
 234                                   void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),
 235                                   void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),
 236                                   Register      scratch) {
 237   index = (index == noreg) ? Z_R0 : index;
 238   if (Displacement::is_shortDisp(disp)) {
 239     (this->*classic)(reg, disp, index, base);
 240   } else {
 241     if (Displacement::is_validDisp(disp)) {
 242       (this->*modern)(reg, disp, index, base);
 243     } else {
 244       if (scratch != Z_R0 && scratch != Z_R1) {
 245         (this->*modern)(reg, disp, index, base);      // Will fail with disp out of range.
 246       } else {
 247         if (scratch != Z_R0) {   // scratch == Z_R1
 248           if ((scratch == index) || (index == base)) {
 249             (this->*modern)(reg, disp, index, base);  // Will fail with disp out of range.
 250           } else {
 251             add2reg(scratch, disp, base);
 252             (this->*classic)(reg, 0, index, scratch);
 253             if (base == scratch) {
 254               add2reg(base, -disp);  // Restore base.
 255             }
 256           }
 257         } else {   // scratch == Z_R0
 258           z_lgr(scratch, base);
 259           add2reg(base, disp);
 260           (this->*classic)(reg, 0, index, base);
 261           z_lgr(base, scratch);      // Restore base.
 262         }
 263       }
 264     }
 265   }
 266 }
 267 
 268 void MacroAssembler::freg2mem_opt(FloatRegister reg, const Address &a, bool is_double) {
 269   if (is_double) {
 270     freg2mem_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_FFUN(z_stdy), CLASSIC_FFUN(z_std));
 271   } else {
 272     freg2mem_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_FFUN(z_stey), CLASSIC_FFUN(z_ste));
 273   }
 274 }
 275 
 276 // Optimized emitter for mem to reg operations.
 277 // Uses modern instructions if running on modern hardware, classic instructions
 278 // otherwise. Prefers (usually shorter) classic instructions if applicable.
 279 // data register (reg) cannot be used as work register.
 280 //
 281 // Don't rely on register locking, instead pass a scratch register (Z_R0 by default).
 282 // CAUTION! Passing registers >= Z_R2 may produce bad results on old CPUs!
 283 void MacroAssembler::mem2freg_opt(FloatRegister reg,
 284                                   int64_t       disp,
 285                                   Register      index,
 286                                   Register      base,
 287                                   void (MacroAssembler::*modern) (FloatRegister, int64_t, Register, Register),
 288                                   void (MacroAssembler::*classic)(FloatRegister, int64_t, Register, Register),
 289                                   Register      scratch) {
 290   index = (index == noreg) ? Z_R0 : index;
 291   if (Displacement::is_shortDisp(disp)) {
 292     (this->*classic)(reg, disp, index, base);
 293   } else {
 294     if (Displacement::is_validDisp(disp)) {
 295       (this->*modern)(reg, disp, index, base);
 296     } else {
 297       if (scratch != Z_R0 && scratch != Z_R1) {
 298         (this->*modern)(reg, disp, index, base);      // Will fail with disp out of range.
 299       } else {
 300         if (scratch != Z_R0) {   // scratch == Z_R1
 301           if ((scratch == index) || (index == base)) {
 302             (this->*modern)(reg, disp, index, base);  // Will fail with disp out of range.
 303           } else {
 304             add2reg(scratch, disp, base);
 305             (this->*classic)(reg, 0, index, scratch);
 306             if (base == scratch) {
 307               add2reg(base, -disp);  // Restore base.
 308             }
 309           }
 310         } else {   // scratch == Z_R0
 311           z_lgr(scratch, base);
 312           add2reg(base, disp);
 313           (this->*classic)(reg, 0, index, base);
 314           z_lgr(base, scratch);      // Restore base.
 315         }
 316       }
 317     }
 318   }
 319 }
 320 
 321 void MacroAssembler::mem2freg_opt(FloatRegister reg, const Address &a, bool is_double) {
 322   if (is_double) {
 323     mem2freg_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_FFUN(z_ldy), CLASSIC_FFUN(z_ld));
 324   } else {
 325     mem2freg_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_FFUN(z_ley), CLASSIC_FFUN(z_le));
 326   }
 327 }
 328 
 329 // Optimized emitter for reg to mem operations.
 330 // Uses modern instructions if running on modern hardware, classic instructions
 331 // otherwise. Prefers (usually shorter) classic instructions if applicable.
 332 // Data register (reg) cannot be used as work register.
 333 //
 334 // Don't rely on register locking, instead pass a scratch register
 335 // (Z_R0 by default)
 336 // CAUTION! passing registers >= Z_R2 may produce bad results on old CPUs!
 337 void MacroAssembler::reg2mem_opt(Register reg,
 338                                  int64_t  disp,
 339                                  Register index,
 340                                  Register base,
 341                                  void (MacroAssembler::*modern) (Register, int64_t, Register, Register),
 342                                  void (MacroAssembler::*classic)(Register, int64_t, Register, Register),
 343                                  Register scratch) {
 344   index = (index == noreg) ? Z_R0 : index;
 345   if (Displacement::is_shortDisp(disp)) {
 346     (this->*classic)(reg, disp, index, base);
 347   } else {
 348     if (Displacement::is_validDisp(disp)) {
 349       (this->*modern)(reg, disp, index, base);
 350     } else {
 351       if (scratch != Z_R0 && scratch != Z_R1) {
 352         (this->*modern)(reg, disp, index, base);      // Will fail with disp out of range.
 353       } else {
 354         if (scratch != Z_R0) {   // scratch == Z_R1
 355           if ((scratch == index) || (index == base)) {
 356             (this->*modern)(reg, disp, index, base);  // Will fail with disp out of range.
 357           } else {
 358             add2reg(scratch, disp, base);
 359             (this->*classic)(reg, 0, index, scratch);
 360             if (base == scratch) {
 361               add2reg(base, -disp);  // Restore base.
 362             }
 363           }
 364         } else {   // scratch == Z_R0
 365           if ((scratch == reg) || (scratch == base) || (reg == base)) {
 366             (this->*modern)(reg, disp, index, base);  // Will fail with disp out of range.
 367           } else {
 368             z_lgr(scratch, base);
 369             add2reg(base, disp);
 370             (this->*classic)(reg, 0, index, base);
 371             z_lgr(base, scratch);    // Restore base.
 372           }
 373         }
 374       }
 375     }
 376   }
 377 }
 378 
 379 int MacroAssembler::reg2mem_opt(Register reg, const Address &a, bool is_double) {
 380   int store_offset = offset();
 381   if (is_double) {
 382     reg2mem_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_IFUN(z_stg), CLASSIC_IFUN(z_stg));
 383   } else {
 384     reg2mem_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_IFUN(z_sty), CLASSIC_IFUN(z_st));
 385   }
 386   return store_offset;
 387 }
 388 
 389 // Optimized emitter for mem to reg operations.
 390 // Uses modern instructions if running on modern hardware, classic instructions
 391 // otherwise. Prefers (usually shorter) classic instructions if applicable.
 392 // Data register (reg) will be used as work register where possible.
 393 void MacroAssembler::mem2reg_opt(Register reg,
 394                                  int64_t  disp,
 395                                  Register index,
 396                                  Register base,
 397                                  void (MacroAssembler::*modern) (Register, int64_t, Register, Register),
 398                                  void (MacroAssembler::*classic)(Register, int64_t, Register, Register)) {
 399   index = (index == noreg) ? Z_R0 : index;
 400   if (Displacement::is_shortDisp(disp)) {
 401     (this->*classic)(reg, disp, index, base);
 402   } else {
 403     if (Displacement::is_validDisp(disp)) {
 404       (this->*modern)(reg, disp, index, base);
 405     } else {
 406       if ((reg == index) && (reg == base)) {
 407         z_sllg(reg, reg, 1);
 408         add2reg(reg, disp);
 409         (this->*classic)(reg, 0, noreg, reg);
 410       } else if ((reg == index) && (reg != Z_R0)) {
 411         add2reg(reg, disp);
 412         (this->*classic)(reg, 0, reg, base);
 413       } else if (reg == base) {
 414         add2reg(reg, disp);
 415         (this->*classic)(reg, 0, index, reg);
 416       } else if (reg != Z_R0) {
 417         add2reg(reg, disp, base);
 418         (this->*classic)(reg, 0, index, reg);
 419       } else { // reg == Z_R0 && reg != base here
 420         add2reg(base, disp);
 421         (this->*classic)(reg, 0, index, base);
 422         add2reg(base, -disp);
 423       }
 424     }
 425   }
 426 }
 427 
 428 void MacroAssembler::mem2reg_opt(Register reg, const Address &a, bool is_double) {
 429   if (is_double) {
 430     z_lg(reg, a);
 431   } else {
 432     mem2reg_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_IFUN(z_ly), CLASSIC_IFUN(z_l));
 433   }
 434 }
 435 
 436 void MacroAssembler::mem2reg_signed_opt(Register reg, const Address &a) {
 437   mem2reg_opt(reg, a.disp20(), a.indexOrR0(), a.baseOrR0(), MODERN_IFUN(z_lgf), CLASSIC_IFUN(z_lgf));
 438 }
 439 
 440 void MacroAssembler::and_imm(Register r, long mask,
 441                              Register tmp /* = Z_R0 */,
 442                              bool wide    /* = false */) {
 443   assert(wide || Immediate::is_simm32(mask), "mask value too large");
 444 
 445   if (!wide) {
 446     z_nilf(r, mask);
 447     return;
 448   }
 449 
 450   assert(r != tmp, " need a different temporary register !");
 451   load_const_optimized(tmp, mask);
 452   z_ngr(r, tmp);
 453 }
 454 
 455 // Calculate the 1's complement.
 456 // Note: The condition code is neither preserved nor correctly set by this code!!!
 457 // Note: (wide == false) does not protect the high order half of the target register
 458 //       from alteration. It only serves as optimization hint for 32-bit results.
 459 void MacroAssembler::not_(Register r1, Register r2, bool wide) {
 460 
 461   if ((r2 == noreg) || (r2 == r1)) { // Calc 1's complement in place.
 462     z_xilf(r1, -1);
 463     if (wide) {
 464       z_xihf(r1, -1);
 465     }
 466   } else { // Distinct src and dst registers.
 467     if (VM_Version::has_DistinctOpnds()) {
 468       load_const_optimized(r1, -1);
 469       z_xgrk(r1, r2, r1);
 470     } else {
 471       if (wide) {
 472         z_lgr(r1, r2);
 473         z_xilf(r1, -1);
 474         z_xihf(r1, -1);
 475       } else {
 476         z_lr(r1, r2);
 477         z_xilf(r1, -1);
 478       }
 479     }
 480   }
 481 }
 482 
 483 unsigned long MacroAssembler::create_mask(int lBitPos, int rBitPos) {
 484   assert(lBitPos >=  0,      "zero is  leftmost bit position");
 485   assert(rBitPos <= 63,      "63   is rightmost bit position");
 486   assert(lBitPos <= rBitPos, "inverted selection interval");
 487   return (lBitPos == 0 ? (unsigned long)(-1L) : ((1UL<<(63-lBitPos+1))-1)) & (~((1UL<<(63-rBitPos))-1));
 488 }
 489 
 490 // Helper function for the "Rotate_then_<logicalOP>" emitters.
 491 // Rotate src, then mask register contents such that only bits in range survive.
 492 // For oneBits == false, all bits not in range are set to 0. Useful for deleting all bits outside range.
 493 // For oneBits == true,  all bits not in range are set to 1. Useful for preserving all bits outside range.
 494 // The caller must ensure that the selected range only contains bits with defined value.
 495 void MacroAssembler::rotate_then_mask(Register dst, Register src, int lBitPos, int rBitPos,
 496                                       int nRotate, bool src32bit, bool dst32bit, bool oneBits) {
 497   assert(!(dst32bit && lBitPos < 32), "selection interval out of range for int destination");
 498   bool sll4rll = (nRotate >= 0) && (nRotate <= (63-rBitPos)); // Substitute SLL(G) for RLL(G).
 499   bool srl4rll = (nRotate <  0) && (-nRotate <= lBitPos);     // Substitute SRL(G) for RLL(G).
 500   //  Pre-determine which parts of dst will be zero after shift/rotate.
 501   bool llZero  =  sll4rll && (nRotate >= 16);
 502   bool lhZero  = (sll4rll && (nRotate >= 32)) || (srl4rll && (nRotate <= -48));
 503   bool lfZero  = llZero && lhZero;
 504   bool hlZero  = (sll4rll && (nRotate >= 48)) || (srl4rll && (nRotate <= -32));
 505   bool hhZero  =                                 (srl4rll && (nRotate <= -16));
 506   bool hfZero  = hlZero && hhZero;
 507 
 508   // rotate then mask src operand.
 509   // if oneBits == true,  all bits outside selected range are 1s.
 510   // if oneBits == false, all bits outside selected range are 0s.
 511   if (src32bit) {   // There might be garbage in the upper 32 bits which will get masked away.
 512     if (dst32bit) {
 513       z_rll(dst, src, nRotate);   // Copy and rotate, upper half of reg remains undisturbed.
 514     } else {
 515       if      (sll4rll) { z_sllg(dst, src,  nRotate); }
 516       else if (srl4rll) { z_srlg(dst, src, -nRotate); }
 517       else              { z_rllg(dst, src,  nRotate); }
 518     }
 519   } else {
 520     if      (sll4rll) { z_sllg(dst, src,  nRotate); }
 521     else if (srl4rll) { z_srlg(dst, src, -nRotate); }
 522     else              { z_rllg(dst, src,  nRotate); }
 523   }
 524 
 525   unsigned long  range_mask    = create_mask(lBitPos, rBitPos);
 526   unsigned int   range_mask_h  = (unsigned int)(range_mask >> 32);
 527   unsigned int   range_mask_l  = (unsigned int)range_mask;
 528   unsigned short range_mask_hh = (unsigned short)(range_mask >> 48);
 529   unsigned short range_mask_hl = (unsigned short)(range_mask >> 32);
 530   unsigned short range_mask_lh = (unsigned short)(range_mask >> 16);
 531   unsigned short range_mask_ll = (unsigned short)range_mask;
 532   // Works for z9 and newer H/W.
 533   if (oneBits) {
 534     if ((~range_mask_l) != 0)                { z_oilf(dst, ~range_mask_l); } // All bits outside range become 1s.
 535     if (((~range_mask_h) != 0) && !dst32bit) { z_oihf(dst, ~range_mask_h); }
 536   } else {
 537     // All bits outside range become 0s
 538     if (((~range_mask_l) != 0) &&              !lfZero) {
 539       z_nilf(dst, range_mask_l);
 540     }
 541     if (((~range_mask_h) != 0) && !dst32bit && !hfZero) {
 542       z_nihf(dst, range_mask_h);
 543     }
 544   }
 545 }
 546 
 547 // Rotate src, then insert selected range from rotated src into dst.
 548 // Clear dst before, if requested.
 549 void MacroAssembler::rotate_then_insert(Register dst, Register src, int lBitPos, int rBitPos,
 550                                         int nRotate, bool clear_dst) {
 551   // This version does not depend on src being zero-extended int2long.
 552   nRotate &= 0x003f;                                       // For risbg, pretend it's an unsigned value.
 553   z_risbg(dst, src, lBitPos, rBitPos, nRotate, clear_dst); // Rotate, then insert selected, clear the rest.
 554 }
 555 
 556 // Rotate src, then and selected range from rotated src into dst.
 557 // Set condition code only if so requested. Otherwise it is unpredictable.
 558 // See performance note in macroAssembler_s390.hpp for important information.
 559 void MacroAssembler::rotate_then_and(Register dst, Register src, int lBitPos, int rBitPos,
 560                                      int nRotate, bool test_only) {
 561   guarantee(!test_only, "Emitter not fit for test_only instruction variant.");
 562   // This version does not depend on src being zero-extended int2long.
 563   nRotate &= 0x003f;                                       // For risbg, pretend it's an unsigned value.
 564   z_rxsbg(dst, src, lBitPos, rBitPos, nRotate, test_only); // Rotate, then xor selected.
 565 }
 566 
 567 // Rotate src, then or selected range from rotated src into dst.
 568 // Set condition code only if so requested. Otherwise it is unpredictable.
 569 // See performance note in macroAssembler_s390.hpp for important information.
 570 void MacroAssembler::rotate_then_or(Register dst, Register src,  int  lBitPos,  int  rBitPos,
 571                                     int nRotate, bool test_only) {
 572   guarantee(!test_only, "Emitter not fit for test_only instruction variant.");
 573   // This version does not depend on src being zero-extended int2long.
 574   nRotate &= 0x003f;                                       // For risbg, pretend it's an unsigned value.
 575   z_rosbg(dst, src, lBitPos, rBitPos, nRotate, test_only); // Rotate, then xor selected.
 576 }
 577 
 578 // Rotate src, then xor selected range from rotated src into dst.
 579 // Set condition code only if so requested. Otherwise it is unpredictable.
 580 // See performance note in macroAssembler_s390.hpp for important information.
 581 void MacroAssembler::rotate_then_xor(Register dst, Register src,  int  lBitPos,  int  rBitPos,
 582                                      int nRotate, bool test_only) {
 583   guarantee(!test_only, "Emitter not fit for test_only instruction variant.");
 584     // This version does not depend on src being zero-extended int2long.
 585   nRotate &= 0x003f;                                       // For risbg, pretend it's an unsigned value.
 586   z_rxsbg(dst, src, lBitPos, rBitPos, nRotate, test_only); // Rotate, then xor selected.
 587 }
 588 
 589 void MacroAssembler::add64(Register r1, RegisterOrConstant inc) {
 590   if (inc.is_register()) {
 591     z_agr(r1, inc.as_register());
 592   } else { // constant
 593     intptr_t imm = inc.as_constant();
 594     add2reg(r1, imm);
 595   }
 596 }
 597 // Helper function to multiply the 64bit contents of a register by a 16bit constant.
 598 // The optimization tries to avoid the mghi instruction, since it uses the FPU for
 599 // calculation and is thus rather slow.
 600 //
 601 // There is no handling for special cases, e.g. cval==0 or cval==1.
 602 //
 603 // Returns len of generated code block.
 604 unsigned int MacroAssembler::mul_reg64_const16(Register rval, Register work, int cval) {
 605   int block_start = offset();
 606 
 607   bool sign_flip = cval < 0;
 608   cval = sign_flip ? -cval : cval;
 609 
 610   BLOCK_COMMENT("Reg64*Con16 {");
 611 
 612   int bit1 = cval & -cval;
 613   if (bit1 == cval) {
 614     z_sllg(rval, rval, exact_log2(bit1));
 615     if (sign_flip) { z_lcgr(rval, rval); }
 616   } else {
 617     int bit2 = (cval-bit1) & -(cval-bit1);
 618     if ((bit1+bit2) == cval) {
 619       z_sllg(work, rval, exact_log2(bit1));
 620       z_sllg(rval, rval, exact_log2(bit2));
 621       z_agr(rval, work);
 622       if (sign_flip) { z_lcgr(rval, rval); }
 623     } else {
 624       if (sign_flip) { z_mghi(rval, -cval); }
 625       else           { z_mghi(rval,  cval); }
 626     }
 627   }
 628   BLOCK_COMMENT("} Reg64*Con16");
 629 
 630   int block_end = offset();
 631   return block_end - block_start;
 632 }
 633 
 634 // Generic operation r1 := r2 + imm.
 635 //
 636 // Should produce the best code for each supported CPU version.
 637 // r2 == noreg yields r1 := r1 + imm
 638 // imm == 0 emits either no instruction or r1 := r2 !
 639 // NOTES: 1) Don't use this function where fixed sized
 640 //           instruction sequences are required!!!
 641 //        2) Don't use this function if condition code
 642 //           setting is required!
 643 //        3) Despite being declared as int64_t, the parameter imm
 644 //           must be a simm_32 value (= signed 32-bit integer).
 645 void MacroAssembler::add2reg(Register r1, int64_t imm, Register r2) {
 646   assert(Immediate::is_simm32(imm), "probably an implicit conversion went wrong");
 647 
 648   if (r2 == noreg) { r2 = r1; }
 649 
 650   // Handle special case imm == 0.
 651   if (imm == 0) {
 652     lgr_if_needed(r1, r2);
 653     // Nothing else to do.
 654     return;
 655   }
 656 
 657   if (!PreferLAoverADD || (r2 == Z_R0)) {
 658     bool distinctOpnds = VM_Version::has_DistinctOpnds();
 659 
 660     // Can we encode imm in 16 bits signed?
 661     if (Immediate::is_simm16(imm)) {
 662       if (r1 == r2) {
 663         z_aghi(r1, imm);
 664         return;
 665       }
 666       if (distinctOpnds) {
 667         z_aghik(r1, r2, imm);
 668         return;
 669       }
 670       z_lgr(r1, r2);
 671       z_aghi(r1, imm);
 672       return;
 673     }
 674   } else {
 675     // Can we encode imm in 12 bits unsigned?
 676     if (Displacement::is_shortDisp(imm)) {
 677       z_la(r1, imm, r2);
 678       return;
 679     }
 680     // Can we encode imm in 20 bits signed?
 681     if (Displacement::is_validDisp(imm)) {
 682       // Always use LAY instruction, so we don't need the tmp register.
 683       z_lay(r1, imm, r2);
 684       return;
 685     }
 686 
 687   }
 688 
 689   // Can handle it (all possible values) with long immediates.
 690   lgr_if_needed(r1, r2);
 691   z_agfi(r1, imm);
 692 }
 693 
 694 // Generic operation r := b + x + d
 695 //
 696 // Addition of several operands with address generation semantics - sort of:
 697 //  - no restriction on the registers. Any register will do for any operand.
 698 //  - x == noreg: operand will be disregarded.
 699 //  - b == noreg: will use (contents of) result reg as operand (r := r + d).
 700 //  - x == Z_R0:  just disregard
 701 //  - b == Z_R0:  use as operand. This is not address generation semantics!!!
 702 //
 703 // The same restrictions as on add2reg() are valid!!!
 704 void MacroAssembler::add2reg_with_index(Register r, int64_t d, Register x, Register b) {
 705   assert(Immediate::is_simm32(d), "probably an implicit conversion went wrong");
 706 
 707   if (x == noreg) { x = Z_R0; }
 708   if (b == noreg) { b = r; }
 709 
 710   // Handle special case x == R0.
 711   if (x == Z_R0) {
 712     // Can simply add the immediate value to the base register.
 713     add2reg(r, d, b);
 714     return;
 715   }
 716 
 717   if (!PreferLAoverADD || (b == Z_R0)) {
 718     bool distinctOpnds = VM_Version::has_DistinctOpnds();
 719     // Handle special case d == 0.
 720     if (d == 0) {
 721       if (b == x)        { z_sllg(r, b, 1); return; }
 722       if (r == x)        { z_agr(r, b);     return; }
 723       if (r == b)        { z_agr(r, x);     return; }
 724       if (distinctOpnds) { z_agrk(r, x, b); return; }
 725       z_lgr(r, b);
 726       z_agr(r, x);
 727     } else {
 728       if (x == b)             { z_sllg(r, x, 1); }
 729       else if (r == x)        { z_agr(r, b); }
 730       else if (r == b)        { z_agr(r, x); }
 731       else if (distinctOpnds) { z_agrk(r, x, b); }
 732       else {
 733         z_lgr(r, b);
 734         z_agr(r, x);
 735       }
 736       add2reg(r, d);
 737     }
 738   } else {
 739     // Can we encode imm in 12 bits unsigned?
 740     if (Displacement::is_shortDisp(d)) {
 741       z_la(r, d, x, b);
 742       return;
 743     }
 744     // Can we encode imm in 20 bits signed?
 745     if (Displacement::is_validDisp(d)) {
 746       z_lay(r, d, x, b);
 747       return;
 748     }
 749     z_la(r, 0, x, b);
 750     add2reg(r, d);
 751   }
 752 }
 753 
 754 // Generic emitter (32bit) for direct memory increment.
 755 // For optimal code, do not specify Z_R0 as temp register.
 756 void MacroAssembler::add2mem_32(const Address &a, int64_t imm, Register tmp) {
 757   if (VM_Version::has_MemWithImmALUOps() && Immediate::is_simm8(imm)) {
 758     z_asi(a, imm);
 759   } else {
 760     z_lgf(tmp, a);
 761     add2reg(tmp, imm);
 762     z_st(tmp, a);
 763   }
 764 }
 765 
 766 void MacroAssembler::add2mem_64(const Address &a, int64_t imm, Register tmp) {
 767   if (VM_Version::has_MemWithImmALUOps() && Immediate::is_simm8(imm)) {
 768     z_agsi(a, imm);
 769   } else {
 770     z_lg(tmp, a);
 771     add2reg(tmp, imm);
 772     z_stg(tmp, a);
 773   }
 774 }
 775 
 776 void MacroAssembler::load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed) {
 777   switch (size_in_bytes) {
 778     case  8: z_lg(dst, src); break;
 779     case  4: is_signed ? z_lgf(dst, src) : z_llgf(dst, src); break;
 780     case  2: is_signed ? z_lgh(dst, src) : z_llgh(dst, src); break;
 781     case  1: is_signed ? z_lgb(dst, src) : z_llgc(dst, src); break;
 782     default: ShouldNotReachHere();
 783   }
 784 }
 785 
 786 void MacroAssembler::store_sized_value(Register src, Address dst, size_t size_in_bytes) {
 787   switch (size_in_bytes) {
 788     case  8: z_stg(src, dst); break;
 789     case  4: z_st(src, dst); break;
 790     case  2: z_sth(src, dst); break;
 791     case  1: z_stc(src, dst); break;
 792     default: ShouldNotReachHere();
 793   }
 794 }
 795 
 796 // Split a si20 offset (20bit, signed) into an ui12 offset (12bit, unsigned) and
 797 // a high-order summand in register tmp.
 798 //
 799 // return value: <  0: No split required, si20 actually has property uimm12.
 800 //               >= 0: Split performed. Use return value as uimm12 displacement and
 801 //                     tmp as index register.
 802 int MacroAssembler::split_largeoffset(int64_t si20_offset, Register tmp, bool fixed_codelen, bool accumulate) {
 803   assert(Immediate::is_simm20(si20_offset), "sanity");
 804   int lg_off = (int)si20_offset &  0x0fff; // Punch out low-order 12 bits, always positive.
 805   int ll_off = (int)si20_offset & ~0x0fff; // Force low-order 12 bits to zero.
 806   assert((Displacement::is_shortDisp(si20_offset) && (ll_off == 0)) ||
 807          !Displacement::is_shortDisp(si20_offset), "unexpected offset values");
 808   assert((lg_off+ll_off) == si20_offset, "offset splitup error");
 809 
 810   Register work = accumulate? Z_R0 : tmp;
 811 
 812   if (fixed_codelen) {          // Len of code = 10 = 4 + 6.
 813     z_lghi(work, ll_off>>12);   // Implicit sign extension.
 814     z_slag(work, work, 12);
 815   } else {                      // Len of code = 0..10.
 816     if (ll_off == 0) { return -1; }
 817     // ll_off has 8 significant bits (at most) plus sign.
 818     if ((ll_off & 0x0000f000) == 0) {    // Non-zero bits only in upper halfbyte.
 819       z_llilh(work, ll_off >> 16);
 820       if (ll_off < 0) {                  // Sign-extension required.
 821         z_lgfr(work, work);
 822       }
 823     } else {
 824       if ((ll_off & 0x000f0000) == 0) {  // Non-zero bits only in lower halfbyte.
 825         z_llill(work, ll_off);
 826       } else {                           // Non-zero bits in both halfbytes.
 827         z_lghi(work, ll_off>>12);        // Implicit sign extension.
 828         z_slag(work, work, 12);
 829       }
 830     }
 831   }
 832   if (accumulate) { z_algr(tmp, work); } // len of code += 4
 833   return lg_off;
 834 }
 835 
 836 void MacroAssembler::load_float_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp) {
 837   if (Displacement::is_validDisp(si20)) {
 838     z_ley(t, si20, a);
 839   } else {
 840     // Fixed_codelen = true is a simple way to ensure that the size of load_float_largeoffset
 841     // does not depend on si20 (scratch buffer emit size == code buffer emit size for constant
 842     // pool loads).
 843     bool accumulate    = true;
 844     bool fixed_codelen = true;
 845     Register work;
 846 
 847     if (fixed_codelen) {
 848       z_lgr(tmp, a);  // Lgr_if_needed not applicable due to fixed_codelen.
 849     } else {
 850       accumulate = (a == tmp);
 851     }
 852     work = tmp;
 853 
 854     int disp12 = split_largeoffset(si20, work, fixed_codelen, accumulate);
 855     if (disp12 < 0) {
 856       z_le(t, si20, work);
 857     } else {
 858       if (accumulate) {
 859         z_le(t, disp12, work);
 860       } else {
 861         z_le(t, disp12, work, a);
 862       }
 863     }
 864   }
 865 }
 866 
 867 void MacroAssembler::load_double_largeoffset(FloatRegister t, int64_t si20, Register a, Register tmp) {
 868   if (Displacement::is_validDisp(si20)) {
 869     z_ldy(t, si20, a);
 870   } else {
 871     // Fixed_codelen = true is a simple way to ensure that the size of load_double_largeoffset
 872     // does not depend on si20 (scratch buffer emit size == code buffer emit size for constant
 873     // pool loads).
 874     bool accumulate    = true;
 875     bool fixed_codelen = true;
 876     Register work;
 877 
 878     if (fixed_codelen) {
 879       z_lgr(tmp, a);  // Lgr_if_needed not applicable due to fixed_codelen.
 880     } else {
 881       accumulate = (a == tmp);
 882     }
 883     work = tmp;
 884 
 885     int disp12 = split_largeoffset(si20, work, fixed_codelen, accumulate);
 886     if (disp12 < 0) {
 887       z_ld(t, si20, work);
 888     } else {
 889       if (accumulate) {
 890         z_ld(t, disp12, work);
 891       } else {
 892         z_ld(t, disp12, work, a);
 893       }
 894     }
 895   }
 896 }
 897 
 898 // PCrelative TOC access.
 899 // Returns distance (in bytes) from current position to start of consts section.
 900 // Returns 0 (zero) if no consts section exists or if it has size zero.
 901 long MacroAssembler::toc_distance() {
 902   CodeSection* cs = code()->consts();
 903   return (long)((cs != NULL) ? cs->start()-pc() : 0);
 904 }
 905 
 906 // Implementation on x86/sparc assumes that constant and instruction section are
 907 // adjacent, but this doesn't hold. Two special situations may occur, that we must
 908 // be able to handle:
 909 //   1. const section may be located apart from the inst section.
 910 //   2. const section may be empty
 911 // In both cases, we use the const section's start address to compute the "TOC",
 912 // this seems to occur only temporarily; in the final step we always seem to end up
 913 // with the pc-relatice variant.
 914 //
 915 // PC-relative offset could be +/-2**32 -> use long for disp
 916 // Furthermore: makes no sense to have special code for
 917 // adjacent const and inst sections.
 918 void MacroAssembler::load_toc(Register Rtoc) {
 919   // Simply use distance from start of const section (should be patched in the end).
 920   long disp = toc_distance();
 921 
 922   RelocationHolder rspec = internal_word_Relocation::spec(pc() + disp);
 923   relocate(rspec);
 924   z_larl(Rtoc, RelAddr::pcrel_off32(disp));  // Offset is in halfwords.
 925 }
 926 
 927 // PCrelative TOC access.
 928 // Load from anywhere pcrelative (with relocation of load instr)
 929 void MacroAssembler::load_long_pcrelative(Register Rdst, address dataLocation) {
 930   address          pc             = this->pc();
 931   ptrdiff_t        total_distance = dataLocation - pc;
 932   RelocationHolder rspec          = internal_word_Relocation::spec(dataLocation);
 933 
 934   assert((total_distance & 0x01L) == 0, "halfword alignment is mandatory");
 935   assert(total_distance != 0, "sanity");
 936 
 937   // Some extra safety net.
 938   if (!RelAddr::is_in_range_of_RelAddr32(total_distance)) {
 939     guarantee(RelAddr::is_in_range_of_RelAddr32(total_distance), "too far away");
 940   }
 941 
 942   (this)->relocate(rspec, relocInfo::pcrel_addr_format);
 943   z_lgrl(Rdst, RelAddr::pcrel_off32(total_distance));
 944 }
 945 
 946 
 947 // PCrelative TOC access.
 948 // Load from anywhere pcrelative (with relocation of load instr)
 949 // loaded addr has to be relocated when added to constant pool.
 950 void MacroAssembler::load_addr_pcrelative(Register Rdst, address addrLocation) {
 951   address          pc             = this->pc();
 952   ptrdiff_t        total_distance = addrLocation - pc;
 953   RelocationHolder rspec          = internal_word_Relocation::spec(addrLocation);
 954 
 955   assert((total_distance & 0x01L) == 0, "halfword alignment is mandatory");
 956 
 957   // Some extra safety net.
 958   if (!RelAddr::is_in_range_of_RelAddr32(total_distance)) {
 959     guarantee(RelAddr::is_in_range_of_RelAddr32(total_distance), "too far away");
 960   }
 961 
 962   (this)->relocate(rspec, relocInfo::pcrel_addr_format);
 963   z_lgrl(Rdst, RelAddr::pcrel_off32(total_distance));
 964 }
 965 
 966 // Generic operation: load a value from memory and test.
 967 // CondCode indicates the sign (<0, ==0, >0) of the loaded value.
 968 void MacroAssembler::load_and_test_byte(Register dst, const Address &a) {
 969   z_lb(dst, a);
 970   z_ltr(dst, dst);
 971 }
 972 
 973 void MacroAssembler::load_and_test_short(Register dst, const Address &a) {
 974   int64_t disp = a.disp20();
 975   if (Displacement::is_shortDisp(disp)) {
 976     z_lh(dst, a);
 977   } else if (Displacement::is_longDisp(disp)) {
 978     z_lhy(dst, a);
 979   } else {
 980     guarantee(false, "displacement out of range");
 981   }
 982   z_ltr(dst, dst);
 983 }
 984 
 985 void MacroAssembler::load_and_test_int(Register dst, const Address &a) {
 986   z_lt(dst, a);
 987 }
 988 
 989 void MacroAssembler::load_and_test_int2long(Register dst, const Address &a) {
 990   z_ltgf(dst, a);
 991 }
 992 
 993 void MacroAssembler::load_and_test_long(Register dst, const Address &a) {
 994   z_ltg(dst, a);
 995 }
 996 
 997 // Test a bit in memory.
 998 void MacroAssembler::testbit(const Address &a, unsigned int bit) {
 999   assert(a.index() == noreg, "no index reg allowed in testbit");
1000   if (bit <= 7) {
1001     z_tm(a.disp() + 3, a.base(), 1 << bit);
1002   } else if (bit <= 15) {
1003     z_tm(a.disp() + 2, a.base(), 1 << (bit - 8));
1004   } else if (bit <= 23) {
1005     z_tm(a.disp() + 1, a.base(), 1 << (bit - 16));
1006   } else if (bit <= 31) {
1007     z_tm(a.disp() + 0, a.base(), 1 << (bit - 24));
1008   } else {
1009     ShouldNotReachHere();
1010   }
1011 }
1012 
1013 // Test a bit in a register. Result is reflected in CC.
1014 void MacroAssembler::testbit(Register r, unsigned int bitPos) {
1015   if (bitPos < 16) {
1016     z_tmll(r, 1U<<bitPos);
1017   } else if (bitPos < 32) {
1018     z_tmlh(r, 1U<<(bitPos-16));
1019   } else if (bitPos < 48) {
1020     z_tmhl(r, 1U<<(bitPos-32));
1021   } else if (bitPos < 64) {
1022     z_tmhh(r, 1U<<(bitPos-48));
1023   } else {
1024     ShouldNotReachHere();
1025   }
1026 }
1027 
1028 // Clear a register, i.e. load const zero into reg.
1029 // Return len (in bytes) of generated instruction(s).
1030 // whole_reg: Clear 64 bits if true, 32 bits otherwise.
1031 // set_cc:    Use instruction that sets the condition code, if true.
1032 int MacroAssembler::clear_reg(Register r, bool whole_reg, bool set_cc) {
1033   unsigned int start_off = offset();
1034   if (whole_reg) {
1035     set_cc ? z_xgr(r, r) : z_laz(r, 0, Z_R0);
1036   } else {  // Only 32bit register.
1037     set_cc ? z_xr(r, r) : z_lhi(r, 0);
1038   }
1039   return offset() - start_off;
1040 }
1041 
1042 #ifdef ASSERT
1043 int MacroAssembler::preset_reg(Register r, unsigned long pattern, int pattern_len) {
1044   switch (pattern_len) {
1045     case 1:
1046       pattern = (pattern & 0x000000ff)  | ((pattern & 0x000000ff)<<8);
1047     case 2:
1048       pattern = (pattern & 0x0000ffff)  | ((pattern & 0x0000ffff)<<16);
1049     case 4:
1050       pattern = (pattern & 0xffffffffL) | ((pattern & 0xffffffffL)<<32);
1051     case 8:
1052       return load_const_optimized_rtn_len(r, pattern, true);
1053       break;
1054     default:
1055       guarantee(false, "preset_reg: bad len");
1056   }
1057   return 0;
1058 }
1059 #endif
1060 
1061 // addr: Address descriptor of memory to clear index register will not be used !
1062 // size: Number of bytes to clear.
1063 //    !!! DO NOT USE THEM FOR ATOMIC MEMORY CLEARING !!!
1064 //    !!! Use store_const() instead                  !!!
1065 void MacroAssembler::clear_mem(const Address& addr, unsigned size) {
1066   guarantee(size <= 256, "MacroAssembler::clear_mem: size too large");
1067 
1068   if (size == 1) {
1069     z_mvi(addr, 0);
1070     return;
1071   }
1072 
1073   switch (size) {
1074     case 2: z_mvhhi(addr, 0);
1075       return;
1076     case 4: z_mvhi(addr, 0);
1077       return;
1078     case 8: z_mvghi(addr, 0);
1079       return;
1080     default: ; // Fallthru to xc.
1081   }
1082 
1083   z_xc(addr, size, addr);
1084 }
1085 
1086 void MacroAssembler::align(int modulus) {
1087   while (offset() % modulus != 0) z_nop();
1088 }
1089 
1090 // Special version for non-relocateable code if required alignment
1091 // is larger than CodeEntryAlignment.
1092 void MacroAssembler::align_address(int modulus) {
1093   while ((uintptr_t)pc() % modulus != 0) z_nop();
1094 }
1095 
1096 Address MacroAssembler::argument_address(RegisterOrConstant arg_slot,
1097                                          Register temp_reg,
1098                                          int64_t extra_slot_offset) {
1099   // On Z, we can have index and disp in an Address. So don't call argument_offset,
1100   // which issues an unnecessary add instruction.
1101   int stackElementSize = Interpreter::stackElementSize;
1102   int64_t offset = extra_slot_offset * stackElementSize;
1103   const Register argbase = Z_esp;
1104   if (arg_slot.is_constant()) {
1105     offset += arg_slot.as_constant() * stackElementSize;
1106     return Address(argbase, offset);
1107   }
1108   // else
1109   assert(temp_reg != noreg, "must specify");
1110   assert(temp_reg != Z_ARG1, "base and index are conflicting");
1111   z_sllg(temp_reg, arg_slot.as_register(), exact_log2(stackElementSize)); // tempreg = arg_slot << 3
1112   return Address(argbase, temp_reg, offset);
1113 }
1114 
1115 
1116 //===================================================================
1117 //===   START   C O N S T A N T S   I N   C O D E   S T R E A M   ===
1118 //===================================================================
1119 //===            P A T CH A B L E   C O N S T A N T S             ===
1120 //===================================================================
1121 
1122 
1123 //---------------------------------------------------
1124 //  Load (patchable) constant into register
1125 //---------------------------------------------------
1126 
1127 
1128 // Load absolute address (and try to optimize).
1129 //   Note: This method is usable only for position-fixed code,
1130 //         referring to a position-fixed target location.
1131 //         If not so, relocations and patching must be used.
1132 void MacroAssembler::load_absolute_address(Register d, address addr) {
1133   assert(addr != NULL, "should not happen");
1134   BLOCK_COMMENT("load_absolute_address:");
1135   if (addr == NULL) {
1136     z_larl(d, pc()); // Dummy emit for size calc.
1137     return;
1138   }
1139 
1140   if (RelAddr::is_in_range_of_RelAddr32(addr, pc())) {
1141     z_larl(d, addr);
1142     return;
1143   }
1144 
1145   load_const_optimized(d, (long)addr);
1146 }
1147 
1148 // Load a 64bit constant.
1149 // Patchable code sequence, but not atomically patchable.
1150 // Make sure to keep code size constant -> no value-dependent optimizations.
1151 // Do not kill condition code.
1152 void MacroAssembler::load_const(Register t, long x) {
1153   Assembler::z_iihf(t, (int)(x >> 32));
1154   Assembler::z_iilf(t, (int)(x & 0xffffffff));
1155 }
1156 
1157 // Load a 32bit constant into a 64bit register, sign-extend or zero-extend.
1158 // Patchable code sequence, but not atomically patchable.
1159 // Make sure to keep code size constant -> no value-dependent optimizations.
1160 // Do not kill condition code.
1161 void MacroAssembler::load_const_32to64(Register t, int64_t x, bool sign_extend) {
1162   if (sign_extend) { Assembler::z_lgfi(t, x); }
1163   else             { Assembler::z_llilf(t, x); }
1164 }
1165 
1166 // Load narrow oop constant, no decompression.
1167 void MacroAssembler::load_narrow_oop(Register t, narrowOop a) {
1168   assert(UseCompressedOops, "must be on to call this method");
1169   load_const_32to64(t, a, false /*sign_extend*/);
1170 }
1171 
1172 // Load narrow klass constant, compression required.
1173 void MacroAssembler::load_narrow_klass(Register t, Klass* k) {
1174   assert(UseCompressedClassPointers, "must be on to call this method");
1175   narrowKlass encoded_k = Klass::encode_klass(k);
1176   load_const_32to64(t, encoded_k, false /*sign_extend*/);
1177 }
1178 
1179 //------------------------------------------------------
1180 //  Compare (patchable) constant with register.
1181 //------------------------------------------------------
1182 
1183 // Compare narrow oop in reg with narrow oop constant, no decompression.
1184 void MacroAssembler::compare_immediate_narrow_oop(Register oop1, narrowOop oop2) {
1185   assert(UseCompressedOops, "must be on to call this method");
1186 
1187   Assembler::z_clfi(oop1, oop2);
1188 }
1189 
1190 // Compare narrow oop in reg with narrow oop constant, no decompression.
1191 void MacroAssembler::compare_immediate_narrow_klass(Register klass1, Klass* klass2) {
1192   assert(UseCompressedClassPointers, "must be on to call this method");
1193   narrowKlass encoded_k = Klass::encode_klass(klass2);
1194 
1195   Assembler::z_clfi(klass1, encoded_k);
1196 }
1197 
1198 //----------------------------------------------------------
1199 //  Check which kind of load_constant we have here.
1200 //----------------------------------------------------------
1201 
1202 // Detection of CPU version dependent load_const sequence.
1203 // The detection is valid only for code sequences generated by load_const,
1204 // not load_const_optimized.
1205 bool MacroAssembler::is_load_const(address a) {
1206   unsigned long inst1, inst2;
1207   unsigned int  len1,  len2;
1208 
1209   len1 = get_instruction(a, &inst1);
1210   len2 = get_instruction(a + len1, &inst2);
1211 
1212   return is_z_iihf(inst1) && is_z_iilf(inst2);
1213 }
1214 
1215 // Detection of CPU version dependent load_const_32to64 sequence.
1216 // Mostly used for narrow oops and narrow Klass pointers.
1217 // The detection is valid only for code sequences generated by load_const_32to64.
1218 bool MacroAssembler::is_load_const_32to64(address pos) {
1219   unsigned long inst1, inst2;
1220   unsigned int len1;
1221 
1222   len1 = get_instruction(pos, &inst1);
1223   return is_z_llilf(inst1);
1224 }
1225 
1226 // Detection of compare_immediate_narrow sequence.
1227 // The detection is valid only for code sequences generated by compare_immediate_narrow_oop.
1228 bool MacroAssembler::is_compare_immediate32(address pos) {
1229   return is_equal(pos, CLFI_ZOPC, RIL_MASK);
1230 }
1231 
1232 // Detection of compare_immediate_narrow sequence.
1233 // The detection is valid only for code sequences generated by compare_immediate_narrow_oop.
1234 bool MacroAssembler::is_compare_immediate_narrow_oop(address pos) {
1235   return is_compare_immediate32(pos);
1236   }
1237 
1238 // Detection of compare_immediate_narrow sequence.
1239 // The detection is valid only for code sequences generated by compare_immediate_narrow_klass.
1240 bool MacroAssembler::is_compare_immediate_narrow_klass(address pos) {
1241   return is_compare_immediate32(pos);
1242 }
1243 
1244 //-----------------------------------
1245 //  patch the load_constant
1246 //-----------------------------------
1247 
1248 // CPU-version dependend patching of load_const.
1249 void MacroAssembler::patch_const(address a, long x) {
1250   assert(is_load_const(a), "not a load of a constant");
1251   set_imm32((address)a, (int) ((x >> 32) & 0xffffffff));
1252   set_imm32((address)(a + 6), (int)(x & 0xffffffff));
1253 }
1254 
1255 // Patching the value of CPU version dependent load_const_32to64 sequence.
1256 // The passed ptr MUST be in compressed format!
1257 int MacroAssembler::patch_load_const_32to64(address pos, int64_t np) {
1258   assert(is_load_const_32to64(pos), "not a load of a narrow ptr (oop or klass)");
1259 
1260   set_imm32(pos, np);
1261   return 6;
1262 }
1263 
1264 // Patching the value of CPU version dependent compare_immediate_narrow sequence.
1265 // The passed ptr MUST be in compressed format!
1266 int MacroAssembler::patch_compare_immediate_32(address pos, int64_t np) {
1267   assert(is_compare_immediate32(pos), "not a compressed ptr compare");
1268 
1269   set_imm32(pos, np);
1270   return 6;
1271 }
1272 
1273 // Patching the immediate value of CPU version dependent load_narrow_oop sequence.
1274 // The passed ptr must NOT be in compressed format!
1275 int MacroAssembler::patch_load_narrow_oop(address pos, oop o) {
1276   assert(UseCompressedOops, "Can only patch compressed oops");
1277 
1278   narrowOop no = oopDesc::encode_heap_oop(o);
1279   return patch_load_const_32to64(pos, no);
1280 }
1281 
1282 // Patching the immediate value of CPU version dependent load_narrow_klass sequence.
1283 // The passed ptr must NOT be in compressed format!
1284 int MacroAssembler::patch_load_narrow_klass(address pos, Klass* k) {
1285   assert(UseCompressedClassPointers, "Can only patch compressed klass pointers");
1286 
1287   narrowKlass nk = Klass::encode_klass(k);
1288   return patch_load_const_32to64(pos, nk);
1289 }
1290 
1291 // Patching the immediate value of CPU version dependent compare_immediate_narrow_oop sequence.
1292 // The passed ptr must NOT be in compressed format!
1293 int MacroAssembler::patch_compare_immediate_narrow_oop(address pos, oop o) {
1294   assert(UseCompressedOops, "Can only patch compressed oops");
1295 
1296   narrowOop no = oopDesc::encode_heap_oop(o);
1297   return patch_compare_immediate_32(pos, no);
1298 }
1299 
1300 // Patching the immediate value of CPU version dependent compare_immediate_narrow_klass sequence.
1301 // The passed ptr must NOT be in compressed format!
1302 int MacroAssembler::patch_compare_immediate_narrow_klass(address pos, Klass* k) {
1303   assert(UseCompressedClassPointers, "Can only patch compressed klass pointers");
1304 
1305   narrowKlass nk = Klass::encode_klass(k);
1306   return patch_compare_immediate_32(pos, nk);
1307 }
1308 
1309 //------------------------------------------------------------------------
1310 //  Extract the constant from a load_constant instruction stream.
1311 //------------------------------------------------------------------------
1312 
1313 // Get constant from a load_const sequence.
1314 long MacroAssembler::get_const(address a) {
1315   assert(is_load_const(a), "not a load of a constant");
1316   unsigned long x;
1317   x =  (((unsigned long) (get_imm32(a,0) & 0xffffffff)) << 32);
1318   x |= (((unsigned long) (get_imm32(a,1) & 0xffffffff)));
1319   return (long) x;
1320 }
1321 
1322 //--------------------------------------
1323 //  Store a constant in memory.
1324 //--------------------------------------
1325 
1326 // General emitter to move a constant to memory.
1327 // The store is atomic.
1328 //  o Address must be given in RS format (no index register)
1329 //  o Displacement should be 12bit unsigned for efficiency. 20bit signed also supported.
1330 //  o Constant can be 1, 2, 4, or 8 bytes, signed or unsigned.
1331 //  o Memory slot can be 1, 2, 4, or 8 bytes, signed or unsigned.
1332 //  o Memory slot must be at least as wide as constant, will assert otherwise.
1333 //  o Signed constants will sign-extend, unsigned constants will zero-extend to slot width.
1334 int MacroAssembler::store_const(const Address &dest, long imm,
1335                                 unsigned int lm, unsigned int lc,
1336                                 Register scratch) {
1337   int64_t  disp = dest.disp();
1338   Register base = dest.base();
1339   assert(!dest.has_index(), "not supported");
1340   assert((lm==1)||(lm==2)||(lm==4)||(lm==8), "memory   length not supported");
1341   assert((lc==1)||(lc==2)||(lc==4)||(lc==8), "constant length not supported");
1342   assert(lm>=lc, "memory slot too small");
1343   assert(lc==8 || Immediate::is_simm(imm, lc*8), "const out of range");
1344   assert(Displacement::is_validDisp(disp), "displacement out of range");
1345 
1346   bool is_shortDisp = Displacement::is_shortDisp(disp);
1347   int store_offset = -1;
1348 
1349   // For target len == 1 it's easy.
1350   if (lm == 1) {
1351     store_offset = offset();
1352     if (is_shortDisp) {
1353       z_mvi(disp, base, imm);
1354       return store_offset;
1355     } else {
1356       z_mviy(disp, base, imm);
1357       return store_offset;
1358     }
1359   }
1360 
1361   // All the "good stuff" takes an unsigned displacement.
1362   if (is_shortDisp) {
1363     // NOTE: Cannot use clear_mem for imm==0, because it is not atomic.
1364 
1365     store_offset = offset();
1366     switch (lm) {
1367       case 2:  // Lc == 1 handled correctly here, even for unsigned. Instruction does no widening.
1368         z_mvhhi(disp, base, imm);
1369         return store_offset;
1370       case 4:
1371         if (Immediate::is_simm16(imm)) {
1372           z_mvhi(disp, base, imm);
1373           return store_offset;
1374         }
1375         break;
1376       case 8:
1377         if (Immediate::is_simm16(imm)) {
1378           z_mvghi(disp, base, imm);
1379           return store_offset;
1380         }
1381         break;
1382       default:
1383         ShouldNotReachHere();
1384         break;
1385     }
1386   }
1387 
1388   //  Can't optimize, so load value and store it.
1389   guarantee(scratch != noreg, " need a scratch register here !");
1390   if (imm != 0) {
1391     load_const_optimized(scratch, imm);  // Preserves CC anyway.
1392   } else {
1393     // Leave CC alone!!
1394     (void) clear_reg(scratch, true, false); // Indicate unused result.
1395   }
1396 
1397   store_offset = offset();
1398   if (is_shortDisp) {
1399     switch (lm) {
1400       case 2:
1401         z_sth(scratch, disp, Z_R0, base);
1402         return store_offset;
1403       case 4:
1404         z_st(scratch, disp, Z_R0, base);
1405         return store_offset;
1406       case 8:
1407         z_stg(scratch, disp, Z_R0, base);
1408         return store_offset;
1409       default:
1410         ShouldNotReachHere();
1411         break;
1412     }
1413   } else {
1414     switch (lm) {
1415       case 2:
1416         z_sthy(scratch, disp, Z_R0, base);
1417         return store_offset;
1418       case 4:
1419         z_sty(scratch, disp, Z_R0, base);
1420         return store_offset;
1421       case 8:
1422         z_stg(scratch, disp, Z_R0, base);
1423         return store_offset;
1424       default:
1425         ShouldNotReachHere();
1426         break;
1427     }
1428   }
1429   return -1; // should not reach here
1430 }
1431 
1432 //===================================================================
1433 //===       N O T   P A T CH A B L E   C O N S T A N T S          ===
1434 //===================================================================
1435 
1436 // Load constant x into register t with a fast instrcution sequence
1437 // depending on the bits in x. Preserves CC under all circumstances.
1438 int MacroAssembler::load_const_optimized_rtn_len(Register t, long x, bool emit) {
1439   if (x == 0) {
1440     int len;
1441     if (emit) {
1442       len = clear_reg(t, true, false);
1443     } else {
1444       len = 4;
1445     }
1446     return len;
1447   }
1448 
1449   if (Immediate::is_simm16(x)) {
1450     if (emit) { z_lghi(t, x); }
1451     return 4;
1452   }
1453 
1454   // 64 bit value: | part1 | part2 | part3 | part4 |
1455   // At least one part is not zero!
1456   int part1 = ((x >> 32) & 0xffff0000) >> 16;
1457   int part2 = (x >> 32) & 0x0000ffff;
1458   int part3 = (x & 0xffff0000) >> 16;
1459   int part4 = (x & 0x0000ffff);
1460 
1461   // Lower word only (unsigned).
1462   if ((part1 == 0) && (part2 == 0)) {
1463     if (part3 == 0) {
1464       if (emit) z_llill(t, part4);
1465       return 4;
1466     }
1467     if (part4 == 0) {
1468       if (emit) z_llilh(t, part3);
1469       return 4;
1470     }
1471     if (emit) z_llilf(t, (int)(x & 0xffffffff));
1472     return 6;
1473   }
1474 
1475   // Upper word only.
1476   if ((part3 == 0) && (part4 == 0)) {
1477     if (part1 == 0) {
1478       if (emit) z_llihl(t, part2);
1479       return 4;
1480     }
1481     if (part2 == 0) {
1482       if (emit) z_llihh(t, part1);
1483       return 4;
1484     }
1485     if (emit) z_llihf(t, (int)(x >> 32));
1486     return 6;
1487   }
1488 
1489   // Lower word only (signed).
1490   if ((part1 == 0x0000ffff) && (part2 == 0x0000ffff) && ((part3 & 0x00008000) != 0)) {
1491     if (emit) z_lgfi(t, (int)(x & 0xffffffff));
1492     return 6;
1493   }
1494 
1495   int len = 0;
1496 
1497   if ((part1 == 0) || (part2 == 0)) {
1498     if (part1 == 0) {
1499       if (emit) z_llihl(t, part2);
1500       len += 4;
1501     } else {
1502       if (emit) z_llihh(t, part1);
1503       len += 4;
1504     }
1505   } else {
1506     if (emit) z_llihf(t, (int)(x >> 32));
1507     len += 6;
1508   }
1509 
1510   if ((part3 == 0) || (part4 == 0)) {
1511     if (part3 == 0) {
1512       if (emit) z_iill(t, part4);
1513       len += 4;
1514     } else {
1515       if (emit) z_iilh(t, part3);
1516       len += 4;
1517     }
1518   } else {
1519     if (emit) z_iilf(t, (int)(x & 0xffffffff));
1520     len += 6;
1521   }
1522   return len;
1523 }
1524 
1525 //=====================================================================
1526 //===     H I G H E R   L E V E L   B R A N C H   E M I T T E R S   ===
1527 //=====================================================================
1528 
1529 // Note: In the worst case, one of the scratch registers is destroyed!!!
1530 void MacroAssembler::compare32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& lbl) {
1531   // Right operand is constant.
1532   if (x2.is_constant()) {
1533     jlong value = x2.as_constant();
1534     compare_and_branch_optimized(r1, value, cond, lbl, /*len64=*/false, /*has_sign=*/true);
1535     return;
1536   }
1537 
1538   // Right operand is in register.
1539   compare_and_branch_optimized(r1, x2.as_register(), cond, lbl, /*len64=*/false, /*has_sign=*/true);
1540 }
1541 
1542 // Note: In the worst case, one of the scratch registers is destroyed!!!
1543 void MacroAssembler::compareU32_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& lbl) {
1544   // Right operand is constant.
1545   if (x2.is_constant()) {
1546     jlong value = x2.as_constant();
1547     compare_and_branch_optimized(r1, value, cond, lbl, /*len64=*/false, /*has_sign=*/false);
1548     return;
1549   }
1550 
1551   // Right operand is in register.
1552   compare_and_branch_optimized(r1, x2.as_register(), cond, lbl, /*len64=*/false, /*has_sign=*/false);
1553 }
1554 
1555 // Note: In the worst case, one of the scratch registers is destroyed!!!
1556 void MacroAssembler::compare64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& lbl) {
1557   // Right operand is constant.
1558   if (x2.is_constant()) {
1559     jlong value = x2.as_constant();
1560     compare_and_branch_optimized(r1, value, cond, lbl, /*len64=*/true, /*has_sign=*/true);
1561     return;
1562   }
1563 
1564   // Right operand is in register.
1565   compare_and_branch_optimized(r1, x2.as_register(), cond, lbl, /*len64=*/true, /*has_sign=*/true);
1566 }
1567 
1568 void MacroAssembler::compareU64_and_branch(Register r1, RegisterOrConstant x2, branch_condition cond, Label& lbl) {
1569   // Right operand is constant.
1570   if (x2.is_constant()) {
1571     jlong value = x2.as_constant();
1572     compare_and_branch_optimized(r1, value, cond, lbl, /*len64=*/true, /*has_sign=*/false);
1573     return;
1574   }
1575 
1576   // Right operand is in register.
1577   compare_and_branch_optimized(r1, x2.as_register(), cond, lbl, /*len64=*/true, /*has_sign=*/false);
1578 }
1579 
1580 // Generate an optimal branch to the branch target.
1581 // Optimal means that a relative branch (brc or brcl) is used if the
1582 // branch distance is short enough. Loading the target address into a
1583 // register and branching via reg is used as fallback only.
1584 //
1585 // Used registers:
1586 //   Z_R1 - work reg. Holds branch target address.
1587 //          Used in fallback case only.
1588 //
1589 // This version of branch_optimized is good for cases where the target address is known
1590 // and constant, i.e. is never changed (no relocation, no patching).
1591 void MacroAssembler::branch_optimized(Assembler::branch_condition cond, address branch_addr) {
1592   address branch_origin = pc();
1593 
1594   if (RelAddr::is_in_range_of_RelAddr16(branch_addr, branch_origin)) {
1595     z_brc(cond, branch_addr);
1596   } else if (RelAddr::is_in_range_of_RelAddr32(branch_addr, branch_origin)) {
1597     z_brcl(cond, branch_addr);
1598   } else {
1599     load_const_optimized(Z_R1, branch_addr);  // CC must not get killed by load_const_optimized.
1600     z_bcr(cond, Z_R1);
1601   }
1602 }
1603 
1604 // This version of branch_optimized is good for cases where the target address
1605 // is potentially not yet known at the time the code is emitted.
1606 //
1607 // One very common case is a branch to an unbound label which is handled here.
1608 // The caller might know (or hope) that the branch distance is short enough
1609 // to be encoded in a 16bit relative address. In this case he will pass a
1610 // NearLabel branch_target.
1611 // Care must be taken with unbound labels. Each call to target(label) creates
1612 // an entry in the patch queue for that label to patch all references of the label
1613 // once it gets bound. Those recorded patch locations must be patchable. Otherwise,
1614 // an assertion fires at patch time.
1615 void MacroAssembler::branch_optimized(Assembler::branch_condition cond, Label& branch_target) {
1616   if (branch_target.is_bound()) {
1617     address branch_addr = target(branch_target);
1618     branch_optimized(cond, branch_addr);
1619   } else if (branch_target.is_near()) {
1620     z_brc(cond, branch_target);  // Caller assures that the target will be in range for z_brc.
1621   } else {
1622     z_brcl(cond, branch_target); // Let's hope target is in range. Otherwise, we will abort at patch time.
1623   }
1624 }
1625 
1626 // Generate an optimal compare and branch to the branch target.
1627 // Optimal means that a relative branch (clgrj, brc or brcl) is used if the
1628 // branch distance is short enough. Loading the target address into a
1629 // register and branching via reg is used as fallback only.
1630 //
1631 // Input:
1632 //   r1 - left compare operand
1633 //   r2 - right compare operand
1634 void MacroAssembler::compare_and_branch_optimized(Register r1,
1635                                                   Register r2,
1636                                                   Assembler::branch_condition cond,
1637                                                   address  branch_addr,
1638                                                   bool     len64,
1639                                                   bool     has_sign) {
1640   unsigned int casenum = (len64?2:0)+(has_sign?0:1);
1641 
1642   address branch_origin = pc();
1643   if (VM_Version::has_CompareBranch() && RelAddr::is_in_range_of_RelAddr16(branch_addr, branch_origin)) {
1644     switch (casenum) {
1645       case 0: z_crj( r1, r2, cond, branch_addr); break;
1646       case 1: z_clrj (r1, r2, cond, branch_addr); break;
1647       case 2: z_cgrj(r1, r2, cond, branch_addr); break;
1648       case 3: z_clgrj(r1, r2, cond, branch_addr); break;
1649       default: ShouldNotReachHere(); break;
1650     }
1651   } else {
1652     switch (casenum) {
1653       case 0: z_cr( r1, r2); break;
1654       case 1: z_clr(r1, r2); break;
1655       case 2: z_cgr(r1, r2); break;
1656       case 3: z_clgr(r1, r2); break;
1657       default: ShouldNotReachHere(); break;
1658     }
1659     branch_optimized(cond, branch_addr);
1660   }
1661 }
1662 
1663 // Generate an optimal compare and branch to the branch target.
1664 // Optimal means that a relative branch (clgij, brc or brcl) is used if the
1665 // branch distance is short enough. Loading the target address into a
1666 // register and branching via reg is used as fallback only.
1667 //
1668 // Input:
1669 //   r1 - left compare operand (in register)
1670 //   x2 - right compare operand (immediate)
1671 void MacroAssembler::compare_and_branch_optimized(Register r1,
1672                                                   jlong    x2,
1673                                                   Assembler::branch_condition cond,
1674                                                   Label&   branch_target,
1675                                                   bool     len64,
1676                                                   bool     has_sign) {
1677   address      branch_origin = pc();
1678   bool         x2_imm8       = (has_sign && Immediate::is_simm8(x2)) || (!has_sign && Immediate::is_uimm8(x2));
1679   bool         is_RelAddr16  = branch_target.is_near() ||
1680                                (branch_target.is_bound() &&
1681                                 RelAddr::is_in_range_of_RelAddr16(target(branch_target), branch_origin));
1682   unsigned int casenum       = (len64?2:0)+(has_sign?0:1);
1683 
1684   if (VM_Version::has_CompareBranch() && is_RelAddr16 && x2_imm8) {
1685     switch (casenum) {
1686       case 0: z_cij( r1, x2, cond, branch_target); break;
1687       case 1: z_clij(r1, x2, cond, branch_target); break;
1688       case 2: z_cgij(r1, x2, cond, branch_target); break;
1689       case 3: z_clgij(r1, x2, cond, branch_target); break;
1690       default: ShouldNotReachHere(); break;
1691     }
1692     return;
1693   }
1694 
1695   if (x2 == 0) {
1696     switch (casenum) {
1697       case 0: z_ltr(r1, r1); break;
1698       case 1: z_ltr(r1, r1); break; // Caution: unsigned test only provides zero/notZero indication!
1699       case 2: z_ltgr(r1, r1); break;
1700       case 3: z_ltgr(r1, r1); break; // Caution: unsigned test only provides zero/notZero indication!
1701       default: ShouldNotReachHere(); break;
1702     }
1703   } else {
1704     if ((has_sign && Immediate::is_simm16(x2)) || (!has_sign && Immediate::is_uimm(x2, 15))) {
1705       switch (casenum) {
1706         case 0: z_chi(r1, x2); break;
1707         case 1: z_chi(r1, x2); break; // positive immediate < 2**15
1708         case 2: z_cghi(r1, x2); break;
1709         case 3: z_cghi(r1, x2); break; // positive immediate < 2**15
1710         default: break;
1711       }
1712     } else if ( (has_sign && Immediate::is_simm32(x2)) || (!has_sign && Immediate::is_uimm32(x2)) ) {
1713       switch (casenum) {
1714         case 0: z_cfi( r1, x2); break;
1715         case 1: z_clfi(r1, x2); break;
1716         case 2: z_cgfi(r1, x2); break;
1717         case 3: z_clgfi(r1, x2); break;
1718         default: ShouldNotReachHere(); break;
1719       }
1720     } else {
1721       // No instruction with immediate operand possible, so load into register.
1722       Register scratch = (r1 != Z_R0) ? Z_R0 : Z_R1;
1723       load_const_optimized(scratch, x2);
1724       switch (casenum) {
1725         case 0: z_cr( r1, scratch); break;
1726         case 1: z_clr(r1, scratch); break;
1727         case 2: z_cgr(r1, scratch); break;
1728         case 3: z_clgr(r1, scratch); break;
1729         default: ShouldNotReachHere(); break;
1730       }
1731     }
1732   }
1733   branch_optimized(cond, branch_target);
1734 }
1735 
1736 // Generate an optimal compare and branch to the branch target.
1737 // Optimal means that a relative branch (clgrj, brc or brcl) is used if the
1738 // branch distance is short enough. Loading the target address into a
1739 // register and branching via reg is used as fallback only.
1740 //
1741 // Input:
1742 //   r1 - left compare operand
1743 //   r2 - right compare operand
1744 void MacroAssembler::compare_and_branch_optimized(Register r1,
1745                                                   Register r2,
1746                                                   Assembler::branch_condition cond,
1747                                                   Label&   branch_target,
1748                                                   bool     len64,
1749                                                   bool     has_sign) {
1750   unsigned int casenum = (len64 ? 2 : 0) + (has_sign ? 0 : 1);
1751 
1752   if (branch_target.is_bound()) {
1753     address branch_addr = target(branch_target);
1754     compare_and_branch_optimized(r1, r2, cond, branch_addr, len64, has_sign);
1755   } else {
1756     if (VM_Version::has_CompareBranch() && branch_target.is_near()) {
1757       switch (casenum) {
1758         case 0: z_crj(  r1, r2, cond, branch_target); break;
1759         case 1: z_clrj( r1, r2, cond, branch_target); break;
1760         case 2: z_cgrj( r1, r2, cond, branch_target); break;
1761         case 3: z_clgrj(r1, r2, cond, branch_target); break;
1762         default: ShouldNotReachHere(); break;
1763       }
1764     } else {
1765       switch (casenum) {
1766         case 0: z_cr( r1, r2); break;
1767         case 1: z_clr(r1, r2); break;
1768         case 2: z_cgr(r1, r2); break;
1769         case 3: z_clgr(r1, r2); break;
1770         default: ShouldNotReachHere(); break;
1771       }
1772       branch_optimized(cond, branch_target);
1773     }
1774   }
1775 }
1776 
1777 //===========================================================================
1778 //===   END     H I G H E R   L E V E L   B R A N C H   E M I T T E R S   ===
1779 //===========================================================================
1780 
1781 AddressLiteral MacroAssembler::allocate_metadata_address(Metadata* obj) {
1782   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1783   int index = oop_recorder()->allocate_metadata_index(obj);
1784   RelocationHolder rspec = metadata_Relocation::spec(index);
1785   return AddressLiteral((address)obj, rspec);
1786 }
1787 
1788 AddressLiteral MacroAssembler::constant_metadata_address(Metadata* obj) {
1789   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1790   int index = oop_recorder()->find_index(obj);
1791   RelocationHolder rspec = metadata_Relocation::spec(index);
1792   return AddressLiteral((address)obj, rspec);
1793 }
1794 
1795 AddressLiteral MacroAssembler::allocate_oop_address(jobject obj) {
1796   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1797   int oop_index = oop_recorder()->allocate_oop_index(obj);
1798   return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));
1799 }
1800 
1801 AddressLiteral MacroAssembler::constant_oop_address(jobject obj) {
1802   assert(oop_recorder() != NULL, "this assembler needs an OopRecorder");
1803   int oop_index = oop_recorder()->find_index(obj);
1804   return AddressLiteral(address(obj), oop_Relocation::spec(oop_index));
1805 }
1806 
1807 // NOTE: destroys r
1808 void MacroAssembler::c2bool(Register r, Register t) {
1809   z_lcr(t, r);   // t = -r
1810   z_or(r, t);    // r = -r OR r
1811   z_srl(r, 31);  // Yields 0 if r was 0, 1 otherwise.
1812 }
1813 
1814 RegisterOrConstant MacroAssembler::delayed_value_impl(intptr_t* delayed_value_addr,
1815                                                       Register tmp,
1816                                                       int offset) {
1817   intptr_t value = *delayed_value_addr;
1818   if (value != 0) {
1819     return RegisterOrConstant(value + offset);
1820   }
1821 
1822   BLOCK_COMMENT("delayed_value {");
1823   // Load indirectly to solve generation ordering problem.
1824   load_absolute_address(tmp, (address) delayed_value_addr); // tmp = a;
1825   z_lg(tmp, 0, tmp);                   // tmp = *tmp;
1826 
1827 #ifdef ASSERT
1828   NearLabel L;
1829   compare64_and_branch(tmp, (intptr_t)0L, Assembler::bcondNotEqual, L);
1830   z_illtrap();
1831   bind(L);
1832 #endif
1833 
1834   if (offset != 0) {
1835     z_agfi(tmp, offset);               // tmp = tmp + offset;
1836   }
1837 
1838   BLOCK_COMMENT("} delayed_value");
1839   return RegisterOrConstant(tmp);
1840 }
1841 
1842 // Patch instruction `inst' at offset `inst_pos' to refer to `dest_pos'
1843 // and return the resulting instruction.
1844 // Dest_pos and inst_pos are 32 bit only. These parms can only designate
1845 // relative positions.
1846 // Use correct argument types. Do not pre-calculate distance.
1847 unsigned long MacroAssembler::patched_branch(address dest_pos, unsigned long inst, address inst_pos) {
1848   int c = 0;
1849   unsigned long patched_inst = 0;
1850   if (is_call_pcrelative_short(inst) ||
1851       is_branch_pcrelative_short(inst) ||
1852       is_branchoncount_pcrelative_short(inst) ||
1853       is_branchonindex32_pcrelative_short(inst)) {
1854     c = 1;
1855     int m = fmask(15, 0);    // simm16(-1, 16, 32);
1856     int v = simm16(RelAddr::pcrel_off16(dest_pos, inst_pos), 16, 32);
1857     patched_inst = (inst & ~m) | v;
1858   } else if (is_compareandbranch_pcrelative_short(inst)) {
1859     c = 2;
1860     long m = fmask(31, 16);  // simm16(-1, 16, 48);
1861     long v = simm16(RelAddr::pcrel_off16(dest_pos, inst_pos), 16, 48);
1862     patched_inst = (inst & ~m) | v;
1863   } else if (is_branchonindex64_pcrelative_short(inst)) {
1864     c = 3;
1865     long m = fmask(31, 16);  // simm16(-1, 16, 48);
1866     long v = simm16(RelAddr::pcrel_off16(dest_pos, inst_pos), 16, 48);
1867     patched_inst = (inst & ~m) | v;
1868   } else if (is_call_pcrelative_long(inst) || is_branch_pcrelative_long(inst)) {
1869     c = 4;
1870     long m = fmask(31, 0);  // simm32(-1, 16, 48);
1871     long v = simm32(RelAddr::pcrel_off32(dest_pos, inst_pos), 16, 48);
1872     patched_inst = (inst & ~m) | v;
1873   } else if (is_pcrelative_long(inst)) { // These are the non-branch pc-relative instructions.
1874     c = 5;
1875     long m = fmask(31, 0);  // simm32(-1, 16, 48);
1876     long v = simm32(RelAddr::pcrel_off32(dest_pos, inst_pos), 16, 48);
1877     patched_inst = (inst & ~m) | v;
1878   } else {
1879     print_dbg_msg(tty, inst, "not a relative branch", 0);
1880     dump_code_range(tty, inst_pos, 32, "not a pcrelative branch");
1881     ShouldNotReachHere();
1882   }
1883 
1884   long new_off = get_pcrel_offset(patched_inst);
1885   if (new_off != (dest_pos-inst_pos)) {
1886     tty->print_cr("case %d: dest_pos = %p, inst_pos = %p, disp = %ld(%12.12lx)", c, dest_pos, inst_pos, new_off, new_off);
1887     print_dbg_msg(tty, inst,         "<- original instruction: branch patching error", 0);
1888     print_dbg_msg(tty, patched_inst, "<- patched  instruction: branch patching error", 0);
1889 #ifdef LUCY_DBG
1890     VM_Version::z_SIGSEGV();
1891 #endif
1892     ShouldNotReachHere();
1893   }
1894   return patched_inst;
1895 }
1896 
1897 // Only called when binding labels (share/vm/asm/assembler.cpp)
1898 // Pass arguments as intended. Do not pre-calculate distance.
1899 void MacroAssembler::pd_patch_instruction(address branch, address target) {
1900   unsigned long stub_inst;
1901   int           inst_len = get_instruction(branch, &stub_inst);
1902 
1903   set_instruction(branch, patched_branch(target, stub_inst, branch), inst_len);
1904 }
1905 
1906 
1907 // Extract relative address (aka offset).
1908 // inv_simm16 works for 4-byte instructions only.
1909 // compare and branch instructions are 6-byte and have a 16bit offset "in the middle".
1910 long MacroAssembler::get_pcrel_offset(unsigned long inst) {
1911 
1912   if (MacroAssembler::is_pcrelative_short(inst)) {
1913     if (((inst&0xFFFFffff00000000UL) == 0) && ((inst&0x00000000FFFF0000UL) != 0)) {
1914       return RelAddr::inv_pcrel_off16(inv_simm16(inst));
1915     } else {
1916       return RelAddr::inv_pcrel_off16(inv_simm16_48(inst));
1917     }
1918   }
1919 
1920   if (MacroAssembler::is_pcrelative_long(inst)) {
1921     return RelAddr::inv_pcrel_off32(inv_simm32(inst));
1922   }
1923 
1924   print_dbg_msg(tty, inst, "not a pcrelative instruction", 6);
1925 #ifdef LUCY_DBG
1926   VM_Version::z_SIGSEGV();
1927 #else
1928   ShouldNotReachHere();
1929 #endif
1930   return -1;
1931 }
1932 
1933 long MacroAssembler::get_pcrel_offset(address pc) {
1934   unsigned long inst;
1935   unsigned int  len = get_instruction(pc, &inst);
1936 
1937 #ifdef ASSERT
1938   long offset;
1939   if (MacroAssembler::is_pcrelative_short(inst) || MacroAssembler::is_pcrelative_long(inst)) {
1940     offset = get_pcrel_offset(inst);
1941   } else {
1942     offset = -1;
1943   }
1944 
1945   if (offset == -1) {
1946     dump_code_range(tty, pc, 32, "not a pcrelative instruction");
1947 #ifdef LUCY_DBG
1948     VM_Version::z_SIGSEGV();
1949 #else
1950     ShouldNotReachHere();
1951 #endif
1952   }
1953   return offset;
1954 #else
1955   return get_pcrel_offset(inst);
1956 #endif // ASSERT
1957 }
1958 
1959 // Get target address from pc-relative instructions.
1960 address MacroAssembler::get_target_addr_pcrel(address pc) {
1961   assert(is_pcrelative_long(pc), "not a pcrelative instruction");
1962   return pc + get_pcrel_offset(pc);
1963 }
1964 
1965 // Patch pc relative load address.
1966 void MacroAssembler::patch_target_addr_pcrel(address pc, address con) {
1967   unsigned long inst;
1968   // Offset is +/- 2**32 -> use long.
1969   ptrdiff_t distance = con - pc;
1970 
1971   get_instruction(pc, &inst);
1972 
1973   if (is_pcrelative_short(inst)) {
1974     *(short *)(pc+2) = RelAddr::pcrel_off16(con, pc);  // Instructions are at least 2-byte aligned, no test required.
1975 
1976     // Some extra safety net.
1977     if (!RelAddr::is_in_range_of_RelAddr16(distance)) {
1978       print_dbg_msg(tty, inst, "distance out of range (16bit)", 4);
1979       dump_code_range(tty, pc, 32, "distance out of range (16bit)");
1980       guarantee(RelAddr::is_in_range_of_RelAddr16(distance), "too far away (more than +/- 2**16");
1981     }
1982     return;
1983   }
1984 
1985   if (is_pcrelative_long(inst)) {
1986     *(int *)(pc+2)   = RelAddr::pcrel_off32(con, pc);
1987 
1988     // Some Extra safety net.
1989     if (!RelAddr::is_in_range_of_RelAddr32(distance)) {
1990       print_dbg_msg(tty, inst, "distance out of range (32bit)", 6);
1991       dump_code_range(tty, pc, 32, "distance out of range (32bit)");
1992       guarantee(RelAddr::is_in_range_of_RelAddr32(distance), "too far away (more than +/- 2**32");
1993     }
1994     return;
1995   }
1996 
1997   guarantee(false, "not a pcrelative instruction to patch!");
1998 }
1999 
2000 // "Current PC" here means the address just behind the basr instruction.
2001 address MacroAssembler::get_PC(Register result) {
2002   z_basr(result, Z_R0); // Don't branch, just save next instruction address in result.
2003   return pc();
2004 }
2005 
2006 // Get current PC + offset.
2007 // Offset given in bytes, must be even!
2008 // "Current PC" here means the address of the larl instruction plus the given offset.
2009 address MacroAssembler::get_PC(Register result, int64_t offset) {
2010   address here = pc();
2011   z_larl(result, offset/2); // Save target instruction address in result.
2012   return here + offset;
2013 }
2014 
2015 // Resize_frame with SP(new) = SP(old) - [offset].
2016 void MacroAssembler::resize_frame_sub(Register offset, Register fp, bool load_fp)
2017 {
2018   assert_different_registers(offset, fp, Z_SP);
2019   if (load_fp) { z_lg(fp, _z_abi(callers_sp), Z_SP); }
2020 
2021   z_sgr(Z_SP, offset);
2022   z_stg(fp, _z_abi(callers_sp), Z_SP);
2023 }
2024 
2025 // Resize_frame with SP(new) = [newSP] + offset.
2026 //   This emitter is useful if we already have calculated a pointer
2027 //   into the to-be-allocated stack space, e.g. with special alignment properties,
2028 //   but need some additional space, e.g. for spilling.
2029 //   newSP    is the pre-calculated pointer. It must not be modified.
2030 //   fp       holds, or is filled with, the frame pointer.
2031 //   offset   is the additional increment which is added to addr to form the new SP.
2032 //            Note: specify a negative value to reserve more space!
2033 //   load_fp == true  only indicates that fp is not pre-filled with the frame pointer.
2034 //                    It does not guarantee that fp contains the frame pointer at the end.
2035 void MacroAssembler::resize_frame_abs_with_offset(Register newSP, Register fp, int offset, bool load_fp) {
2036   assert_different_registers(newSP, fp, Z_SP);
2037 
2038   if (load_fp) {
2039     z_lg(fp, _z_abi(callers_sp), Z_SP);
2040   }
2041 
2042   add2reg(Z_SP, offset, newSP);
2043   z_stg(fp, _z_abi(callers_sp), Z_SP);
2044 }
2045 
2046 // Resize_frame with SP(new) = [newSP].
2047 //   load_fp == true  only indicates that fp is not pre-filled with the frame pointer.
2048 //                    It does not guarantee that fp contains the frame pointer at the end.
2049 void MacroAssembler::resize_frame_absolute(Register newSP, Register fp, bool load_fp) {
2050   assert_different_registers(newSP, fp, Z_SP);
2051 
2052   if (load_fp) {
2053     z_lg(fp, _z_abi(callers_sp), Z_SP); // need to use load/store.
2054   }
2055 
2056   z_lgr(Z_SP, newSP);
2057   if (newSP != Z_R0) { // make sure we generate correct code, no matter what register newSP uses.
2058     z_stg(fp, _z_abi(callers_sp), newSP);
2059   } else {
2060     z_stg(fp, _z_abi(callers_sp), Z_SP);
2061   }
2062 }
2063 
2064 // Resize_frame with SP(new) = SP(old) + offset.
2065 void MacroAssembler::resize_frame(RegisterOrConstant offset, Register fp, bool load_fp) {
2066   assert_different_registers(fp, Z_SP);
2067 
2068   if (load_fp) {
2069     z_lg(fp, _z_abi(callers_sp), Z_SP);
2070   }
2071   add64(Z_SP, offset);
2072   z_stg(fp, _z_abi(callers_sp), Z_SP);
2073 }
2074 
2075 void MacroAssembler::push_frame(Register bytes, Register old_sp, bool copy_sp, bool bytes_with_inverted_sign) {
2076 #ifdef ASSERT
2077   assert_different_registers(bytes, old_sp, Z_SP);
2078   if (!copy_sp) {
2079     z_cgr(old_sp, Z_SP);
2080     asm_assert_eq("[old_sp]!=[Z_SP]", 0x211);
2081   }
2082 #endif
2083   if (copy_sp) { z_lgr(old_sp, Z_SP); }
2084   if (bytes_with_inverted_sign) {
2085     z_agr(Z_SP, bytes);
2086   } else {
2087     z_sgr(Z_SP, bytes); // Z_sgfr sufficient, but probably not faster.
2088   }
2089   z_stg(old_sp, _z_abi(callers_sp), Z_SP);
2090 }
2091 
2092 unsigned int MacroAssembler::push_frame(unsigned int bytes, Register scratch) {
2093   long offset = Assembler::align(bytes, frame::alignment_in_bytes);
2094   assert(offset > 0, "should push a frame with positive size, size = %ld.", offset);
2095   assert(Displacement::is_validDisp(-offset), "frame size out of range, size = %ld", offset);
2096 
2097   // We must not write outside the current stack bounds (given by Z_SP).
2098   // Thus, we have to first update Z_SP and then store the previous SP as stack linkage.
2099   // We rely on Z_R0 by default to be available as scratch.
2100   z_lgr(scratch, Z_SP);
2101   add2reg(Z_SP, -offset);
2102   z_stg(scratch, _z_abi(callers_sp), Z_SP);
2103 #ifdef ASSERT
2104   // Just make sure nobody uses the value in the default scratch register.
2105   // When another register is used, the caller might rely on it containing the frame pointer.
2106   if (scratch == Z_R0) {
2107     z_iihf(scratch, 0xbaadbabe);
2108     z_iilf(scratch, 0xdeadbeef);
2109   }
2110 #endif
2111   return offset;
2112 }
2113 
2114 // Push a frame of size `bytes' plus abi160 on top.
2115 unsigned int MacroAssembler::push_frame_abi160(unsigned int bytes) {
2116   BLOCK_COMMENT("push_frame_abi160 {");
2117   unsigned int res = push_frame(bytes + frame::z_abi_160_size);
2118   BLOCK_COMMENT("} push_frame_abi160");
2119   return res;
2120 }
2121 
2122 // Pop current C frame.
2123 void MacroAssembler::pop_frame() {
2124   BLOCK_COMMENT("pop_frame:");
2125   Assembler::z_lg(Z_SP, _z_abi(callers_sp), Z_SP);
2126 }
2127 
2128 // Pop current C frame and restore return PC register (Z_R14).
2129 void MacroAssembler::pop_frame_restore_retPC(int frame_size_in_bytes) {
2130   BLOCK_COMMENT("pop_frame_restore_retPC:");
2131   int retPC_offset = _z_abi16(return_pc) + frame_size_in_bytes;
2132   // If possible, pop frame by add instead of load (a penny saved is a penny got :-).
2133   if (Displacement::is_validDisp(retPC_offset)) {
2134     z_lg(Z_R14, retPC_offset, Z_SP);
2135     add2reg(Z_SP, frame_size_in_bytes);
2136   } else {
2137     add2reg(Z_SP, frame_size_in_bytes);
2138     restore_return_pc();
2139   }
2140 }
2141 
2142 void MacroAssembler::call_VM_leaf_base(address entry_point, bool allow_relocation) {
2143   if (allow_relocation) {
2144     call_c(entry_point);
2145   } else {
2146     call_c_static(entry_point);
2147   }
2148 }
2149 
2150 void MacroAssembler::call_VM_leaf_base(address entry_point) {
2151   bool allow_relocation = true;
2152   call_VM_leaf_base(entry_point, allow_relocation);
2153 }
2154 
2155 void MacroAssembler::call_VM_base(Register oop_result,
2156                                   Register last_java_sp,
2157                                   address  entry_point,
2158                                   bool     allow_relocation,
2159                                   bool     check_exceptions) { // Defaults to true.
2160   // Allow_relocation indicates, if true, that the generated code shall
2161   // be fit for code relocation or referenced data relocation. In other
2162   // words: all addresses must be considered variable. PC-relative addressing
2163   // is not possible then.
2164   // On the other hand, if (allow_relocation == false), addresses and offsets
2165   // may be considered stable, enabling us to take advantage of some PC-relative
2166   // addressing tweaks. These might improve performance and reduce code size.
2167 
2168   // Determine last_java_sp register.
2169   if (!last_java_sp->is_valid()) {
2170     last_java_sp = Z_SP;  // Load Z_SP as SP.
2171   }
2172 
2173   set_top_ijava_frame_at_SP_as_last_Java_frame(last_java_sp, Z_R1, allow_relocation);
2174 
2175   // ARG1 must hold thread address.
2176   z_lgr(Z_ARG1, Z_thread);
2177 
2178   address return_pc = NULL;
2179   if (allow_relocation) {
2180     return_pc = call_c(entry_point);
2181   } else {
2182     return_pc = call_c_static(entry_point);
2183   }
2184 
2185   reset_last_Java_frame(allow_relocation);
2186 
2187   // C++ interp handles this in the interpreter.
2188   check_and_handle_popframe(Z_thread);
2189   check_and_handle_earlyret(Z_thread);
2190 
2191   // Check for pending exceptions.
2192   if (check_exceptions) {
2193     // Check for pending exceptions (java_thread is set upon return).
2194     load_and_test_long(Z_R0_scratch, Address(Z_thread, Thread::pending_exception_offset()));
2195 
2196     // This used to conditionally jump to forward_exception however it is
2197     // possible if we relocate that the branch will not reach. So we must jump
2198     // around so we can always reach.
2199 
2200     Label ok;
2201     z_bre(ok); // Bcondequal is the same as bcondZero.
2202     call_stub(StubRoutines::forward_exception_entry());
2203     bind(ok);
2204   }
2205 
2206   // Get oop result if there is one and reset the value in the thread.
2207   if (oop_result->is_valid()) {
2208     get_vm_result(oop_result);
2209   }
2210 
2211   _last_calls_return_pc = return_pc;  // Wipe out other (error handling) calls.
2212 }
2213 
2214 void MacroAssembler::call_VM_base(Register oop_result,
2215                                   Register last_java_sp,
2216                                   address  entry_point,
2217                                   bool     check_exceptions) { // Defaults to true.
2218   bool allow_relocation = true;
2219   call_VM_base(oop_result, last_java_sp, entry_point, allow_relocation, check_exceptions);
2220 }
2221 
2222 // VM calls without explicit last_java_sp.
2223 
2224 void MacroAssembler::call_VM(Register oop_result, address entry_point, bool check_exceptions) {
2225   // Call takes possible detour via InterpreterMacroAssembler.
2226   call_VM_base(oop_result, noreg, entry_point, true, check_exceptions);
2227 }
2228 
2229 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, bool check_exceptions) {
2230   // Z_ARG1 is reserved for the thread.
2231   lgr_if_needed(Z_ARG2, arg_1);
2232   call_VM(oop_result, entry_point, check_exceptions);
2233 }
2234 
2235 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2, bool check_exceptions) {
2236   // Z_ARG1 is reserved for the thread.
2237   lgr_if_needed(Z_ARG2, arg_1);
2238   assert(arg_2 != Z_ARG2, "smashed argument");
2239   lgr_if_needed(Z_ARG3, arg_2);
2240   call_VM(oop_result, entry_point, check_exceptions);
2241 }
2242 
2243 void MacroAssembler::call_VM(Register oop_result, address entry_point, Register arg_1, Register arg_2,
2244                              Register arg_3, bool check_exceptions) {
2245   // Z_ARG1 is reserved for the thread.
2246   lgr_if_needed(Z_ARG2, arg_1);
2247   assert(arg_2 != Z_ARG2, "smashed argument");
2248   lgr_if_needed(Z_ARG3, arg_2);
2249   assert(arg_3 != Z_ARG2 && arg_3 != Z_ARG3, "smashed argument");
2250   lgr_if_needed(Z_ARG4, arg_3);
2251   call_VM(oop_result, entry_point, check_exceptions);
2252 }
2253 
2254 // VM static calls without explicit last_java_sp.
2255 
2256 void MacroAssembler::call_VM_static(Register oop_result, address entry_point, bool check_exceptions) {
2257   // Call takes possible detour via InterpreterMacroAssembler.
2258   call_VM_base(oop_result, noreg, entry_point, false, check_exceptions);
2259 }
2260 
2261 void MacroAssembler::call_VM_static(Register oop_result, address entry_point, Register arg_1, Register arg_2,
2262                                     Register arg_3, bool check_exceptions) {
2263   // Z_ARG1 is reserved for the thread.
2264   lgr_if_needed(Z_ARG2, arg_1);
2265   assert(arg_2 != Z_ARG2, "smashed argument");
2266   lgr_if_needed(Z_ARG3, arg_2);
2267   assert(arg_3 != Z_ARG2 && arg_3 != Z_ARG3, "smashed argument");
2268   lgr_if_needed(Z_ARG4, arg_3);
2269   call_VM_static(oop_result, entry_point, check_exceptions);
2270 }
2271 
2272 // VM calls with explicit last_java_sp.
2273 
2274 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, bool check_exceptions) {
2275   // Call takes possible detour via InterpreterMacroAssembler.
2276   call_VM_base(oop_result, last_java_sp, entry_point, true, check_exceptions);
2277 }
2278 
2279 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions) {
2280    // Z_ARG1 is reserved for the thread.
2281    lgr_if_needed(Z_ARG2, arg_1);
2282    call_VM(oop_result, last_java_sp, entry_point, check_exceptions);
2283 }
2284 
2285 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1,
2286                              Register arg_2, bool check_exceptions) {
2287    // Z_ARG1 is reserved for the thread.
2288    lgr_if_needed(Z_ARG2, arg_1);
2289    assert(arg_2 != Z_ARG2, "smashed argument");
2290    lgr_if_needed(Z_ARG3, arg_2);
2291    call_VM(oop_result, last_java_sp, entry_point, check_exceptions);
2292 }
2293 
2294 void MacroAssembler::call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1,
2295                              Register arg_2, Register arg_3, bool check_exceptions) {
2296   // Z_ARG1 is reserved for the thread.
2297   lgr_if_needed(Z_ARG2, arg_1);
2298   assert(arg_2 != Z_ARG2, "smashed argument");
2299   lgr_if_needed(Z_ARG3, arg_2);
2300   assert(arg_3 != Z_ARG2 && arg_3 != Z_ARG3, "smashed argument");
2301   lgr_if_needed(Z_ARG4, arg_3);
2302   call_VM(oop_result, last_java_sp, entry_point, check_exceptions);
2303 }
2304 
2305 // VM leaf calls.
2306 
2307 void MacroAssembler::call_VM_leaf(address entry_point) {
2308   // Call takes possible detour via InterpreterMacroAssembler.
2309   call_VM_leaf_base(entry_point, true);
2310 }
2311 
2312 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1) {
2313   if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2314   call_VM_leaf(entry_point);
2315 }
2316 
2317 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2) {
2318   if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2319   assert(arg_2 != Z_ARG1, "smashed argument");
2320   if (arg_2 != noreg) lgr_if_needed(Z_ARG2, arg_2);
2321   call_VM_leaf(entry_point);
2322 }
2323 
2324 void MacroAssembler::call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
2325   if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2326   assert(arg_2 != Z_ARG1, "smashed argument");
2327   if (arg_2 != noreg) lgr_if_needed(Z_ARG2, arg_2);
2328   assert(arg_3 != Z_ARG1 && arg_3 != Z_ARG2, "smashed argument");
2329   if (arg_3 != noreg) lgr_if_needed(Z_ARG3, arg_3);
2330   call_VM_leaf(entry_point);
2331 }
2332 
2333 // Static VM leaf calls.
2334 // Really static VM leaf calls are never patched.
2335 
2336 void MacroAssembler::call_VM_leaf_static(address entry_point) {
2337   // Call takes possible detour via InterpreterMacroAssembler.
2338   call_VM_leaf_base(entry_point, false);
2339 }
2340 
2341 void MacroAssembler::call_VM_leaf_static(address entry_point, Register arg_1) {
2342   if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2343   call_VM_leaf_static(entry_point);
2344 }
2345 
2346 void MacroAssembler::call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2) {
2347   if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2348   assert(arg_2 != Z_ARG1, "smashed argument");
2349   if (arg_2 != noreg) lgr_if_needed(Z_ARG2, arg_2);
2350   call_VM_leaf_static(entry_point);
2351 }
2352 
2353 void MacroAssembler::call_VM_leaf_static(address entry_point, Register arg_1, Register arg_2, Register arg_3) {
2354   if (arg_1 != noreg) lgr_if_needed(Z_ARG1, arg_1);
2355   assert(arg_2 != Z_ARG1, "smashed argument");
2356   if (arg_2 != noreg) lgr_if_needed(Z_ARG2, arg_2);
2357   assert(arg_3 != Z_ARG1 && arg_3 != Z_ARG2, "smashed argument");
2358   if (arg_3 != noreg) lgr_if_needed(Z_ARG3, arg_3);
2359   call_VM_leaf_static(entry_point);
2360 }
2361 
2362 // Don't use detour via call_c(reg).
2363 address MacroAssembler::call_c(address function_entry) {
2364   load_const(Z_R1, function_entry);
2365   return call(Z_R1);
2366 }
2367 
2368 // Variant for really static (non-relocatable) calls which are never patched.
2369 address MacroAssembler::call_c_static(address function_entry) {
2370   load_absolute_address(Z_R1, function_entry);
2371 #if 0 // def ASSERT
2372   // Verify that call site did not move.
2373   load_const_optimized(Z_R0, function_entry);
2374   z_cgr(Z_R1, Z_R0);
2375   z_brc(bcondEqual, 3);
2376   z_illtrap(0xba);
2377 #endif
2378   return call(Z_R1);
2379 }
2380 
2381 address MacroAssembler::call_c_opt(address function_entry) {
2382   bool success = call_far_patchable(function_entry, -2 /* emit relocation + constant */);
2383   _last_calls_return_pc = success ? pc() : NULL;
2384   return _last_calls_return_pc;
2385 }
2386 
2387 // Identify a call_far_patchable instruction: LARL + LG + BASR
2388 //
2389 //    nop                   ; optionally, if required for alignment
2390 //    lgrl rx,A(TOC entry)  ; PC-relative access into constant pool
2391 //    basr Z_R14,rx         ; end of this instruction must be aligned to a word boundary
2392 //
2393 // Code pattern will eventually get patched into variant2 (see below for detection code).
2394 //
2395 bool MacroAssembler::is_call_far_patchable_variant0_at(address instruction_addr) {
2396   address iaddr = instruction_addr;
2397 
2398   // Check for the actual load instruction.
2399   if (!is_load_const_from_toc(iaddr)) { return false; }
2400   iaddr += load_const_from_toc_size();
2401 
2402   // Check for the call (BASR) instruction, finally.
2403   assert(iaddr-instruction_addr+call_byregister_size() == call_far_patchable_size(), "size mismatch");
2404   return is_call_byregister(iaddr);
2405 }
2406 
2407 // Identify a call_far_patchable instruction: BRASL
2408 //
2409 // Code pattern to suits atomic patching:
2410 //    nop                       ; Optionally, if required for alignment.
2411 //    nop    ...                ; Multiple filler nops to compensate for size difference (variant0 is longer).
2412 //    nop                       ; For code pattern detection: Prepend each BRASL with a nop.
2413 //    brasl  Z_R14,<reladdr>    ; End of code must be 4-byte aligned !
2414 bool MacroAssembler::is_call_far_patchable_variant2_at(address instruction_addr) {
2415   const address call_addr = (address)((intptr_t)instruction_addr + call_far_patchable_size() - call_far_pcrelative_size());
2416 
2417   // Check for correct number of leading nops.
2418   address iaddr;
2419   for (iaddr = instruction_addr; iaddr < call_addr; iaddr += nop_size()) {
2420     if (!is_z_nop(iaddr)) { return false; }
2421   }
2422   assert(iaddr == call_addr, "sanity");
2423 
2424   // --> Check for call instruction.
2425   if (is_call_far_pcrelative(call_addr)) {
2426     assert(call_addr-instruction_addr+call_far_pcrelative_size() == call_far_patchable_size(), "size mismatch");
2427     return true;
2428   }
2429 
2430   return false;
2431 }
2432 
2433 // Emit a NOT mt-safely patchable 64 bit absolute call.
2434 // If toc_offset == -2, then the destination of the call (= target) is emitted
2435 //                      to the constant pool and a runtime_call relocation is added
2436 //                      to the code buffer.
2437 // If toc_offset != -2, target must already be in the constant pool at
2438 //                      _ctableStart+toc_offset (a caller can retrieve toc_offset
2439 //                      from the runtime_call relocation).
2440 // Special handling of emitting to scratch buffer when there is no constant pool.
2441 // Slightly changed code pattern. We emit an additional nop if we would
2442 // not end emitting at a word aligned address. This is to ensure
2443 // an atomically patchable displacement in brasl instructions.
2444 //
2445 // A call_far_patchable comes in different flavors:
2446 //  - LARL(CP) / LG(CP) / BR (address in constant pool, access via CP register)
2447 //  - LGRL(CP) / BR          (address in constant pool, pc-relative accesss)
2448 //  - BRASL                  (relative address of call target coded in instruction)
2449 // All flavors occupy the same amount of space. Length differences are compensated
2450 // by leading nops, such that the instruction sequence always ends at the same
2451 // byte offset. This is required to keep the return offset constant.
2452 // Furthermore, the return address (the end of the instruction sequence) is forced
2453 // to be on a 4-byte boundary. This is required for atomic patching, should we ever
2454 // need to patch the call target of the BRASL flavor.
2455 // RETURN value: false, if no constant pool entry could be allocated, true otherwise.
2456 bool MacroAssembler::call_far_patchable(address target, int64_t tocOffset) {
2457   // Get current pc and ensure word alignment for end of instr sequence.
2458   const address start_pc = pc();
2459   const intptr_t       start_off = offset();
2460   assert(!call_far_patchable_requires_alignment_nop(start_pc), "call_far_patchable requires aligned address");
2461   const ptrdiff_t      dist      = (ptrdiff_t)(target - (start_pc + 2)); // Prepend each BRASL with a nop.
2462   const bool emit_target_to_pool = (tocOffset == -2) && !code_section()->scratch_emit();
2463   const bool emit_relative_call  = !emit_target_to_pool &&
2464                                    RelAddr::is_in_range_of_RelAddr32(dist) &&
2465                                    ReoptimizeCallSequences &&
2466                                    !code_section()->scratch_emit();
2467 
2468   if (emit_relative_call) {
2469     // Add padding to get the same size as below.
2470     const unsigned int padding = call_far_patchable_size() - call_far_pcrelative_size();
2471     unsigned int current_padding;
2472     for (current_padding = 0; current_padding < padding; current_padding += nop_size()) { z_nop(); }
2473     assert(current_padding == padding, "sanity");
2474 
2475     // relative call: len = 2(nop) + 6 (brasl)
2476     // CodeBlob resize cannot occur in this case because
2477     // this call is emitted into pre-existing space.
2478     z_nop(); // Prepend each BRASL with a nop.
2479     z_brasl(Z_R14, target);
2480   } else {
2481     // absolute call: Get address from TOC.
2482     // len = (load TOC){6|0} + (load from TOC){6} + (basr){2} = {14|8}
2483     if (emit_target_to_pool) {
2484       // When emitting the call for the first time, we do not need to use
2485       // the pc-relative version. It will be patched anyway, when the code
2486       // buffer is copied.
2487       // Relocation is not needed when !ReoptimizeCallSequences.
2488       relocInfo::relocType rt = ReoptimizeCallSequences ? relocInfo::runtime_call_w_cp_type : relocInfo::none;
2489       AddressLiteral dest(target, rt);
2490       // Store_oop_in_toc() adds dest to the constant table. As side effect, this kills
2491       // inst_mark(). Reset if possible.
2492       bool reset_mark = (inst_mark() == pc());
2493       tocOffset = store_oop_in_toc(dest);
2494       if (reset_mark) { set_inst_mark(); }
2495       if (tocOffset == -1) {
2496         return false; // Couldn't create constant pool entry.
2497       }
2498     }
2499     assert(offset() == start_off, "emit no code before this point!");
2500 
2501     address tocPos = pc() + tocOffset;
2502     if (emit_target_to_pool) {
2503       tocPos = code()->consts()->start() + tocOffset;
2504     }
2505     load_long_pcrelative(Z_R14, tocPos);
2506     z_basr(Z_R14, Z_R14);
2507   }
2508 
2509 #ifdef ASSERT
2510   // Assert that we can identify the emitted call.
2511   assert(is_call_far_patchable_at(addr_at(start_off)), "can't identify emitted call");
2512   assert(offset() == start_off+call_far_patchable_size(), "wrong size");
2513 
2514   if (emit_target_to_pool) {
2515     assert(get_dest_of_call_far_patchable_at(addr_at(start_off), code()->consts()->start()) == target,
2516            "wrong encoding of dest address");
2517   }
2518 #endif
2519   return true; // success
2520 }
2521 
2522 // Identify a call_far_patchable instruction.
2523 // For more detailed information see header comment of call_far_patchable.
2524 bool MacroAssembler::is_call_far_patchable_at(address instruction_addr) {
2525   return is_call_far_patchable_variant2_at(instruction_addr)  || // short version: BRASL
2526          is_call_far_patchable_variant0_at(instruction_addr);    // long version LARL + LG + BASR
2527 }
2528 
2529 // Does the call_far_patchable instruction use a pc-relative encoding
2530 // of the call destination?
2531 bool MacroAssembler::is_call_far_patchable_pcrelative_at(address instruction_addr) {
2532   // Variant 2 is pc-relative.
2533   return is_call_far_patchable_variant2_at(instruction_addr);
2534 }
2535 
2536 bool MacroAssembler::is_call_far_pcrelative(address instruction_addr) {
2537   // Prepend each BRASL with a nop.
2538   return is_z_nop(instruction_addr) && is_z_brasl(instruction_addr + nop_size());  // Match at position after one nop required.
2539 }
2540 
2541 // Set destination address of a call_far_patchable instruction.
2542 void MacroAssembler::set_dest_of_call_far_patchable_at(address instruction_addr, address dest, int64_t tocOffset) {
2543   ResourceMark rm;
2544 
2545   // Now that CP entry is verified, patch call to a pc-relative call (if circumstances permit).
2546   int code_size = MacroAssembler::call_far_patchable_size();
2547   CodeBuffer buf(instruction_addr, code_size);
2548   MacroAssembler masm(&buf);
2549   masm.call_far_patchable(dest, tocOffset);
2550   ICache::invalidate_range(instruction_addr, code_size); // Empty on z.
2551 }
2552 
2553 // Get dest address of a call_far_patchable instruction.
2554 address MacroAssembler::get_dest_of_call_far_patchable_at(address instruction_addr, address ctable) {
2555   // Dynamic TOC: absolute address in constant pool.
2556   // Check variant2 first, it is more frequent.
2557 
2558   // Relative address encoded in call instruction.
2559   if (is_call_far_patchable_variant2_at(instruction_addr)) {
2560     return MacroAssembler::get_target_addr_pcrel(instruction_addr + nop_size()); // Prepend each BRASL with a nop.
2561 
2562   // Absolute address in constant pool.
2563   } else if (is_call_far_patchable_variant0_at(instruction_addr)) {
2564     address iaddr = instruction_addr;
2565 
2566     long    tocOffset = get_load_const_from_toc_offset(iaddr);
2567     address tocLoc    = iaddr + tocOffset;
2568     return *(address *)(tocLoc);
2569   } else {
2570     fprintf(stderr, "MacroAssembler::get_dest_of_call_far_patchable_at has a problem at %p:\n", instruction_addr);
2571     fprintf(stderr, "not a call_far_patchable: %16.16lx %16.16lx, len = %d\n",
2572             *(unsigned long*)instruction_addr,
2573             *(unsigned long*)(instruction_addr+8),
2574             call_far_patchable_size());
2575     Disassembler::decode(instruction_addr, instruction_addr+call_far_patchable_size());
2576     ShouldNotReachHere();
2577     return NULL;
2578   }
2579 }
2580 
2581 void MacroAssembler::align_call_far_patchable(address pc) {
2582   if (call_far_patchable_requires_alignment_nop(pc)) { z_nop(); }
2583 }
2584 
2585 void MacroAssembler::check_and_handle_earlyret(Register java_thread) {
2586 }
2587 
2588 void MacroAssembler::check_and_handle_popframe(Register java_thread) {
2589 }
2590 
2591 // Read from the polling page.
2592 // Use TM or TMY instruction, depending on read offset.
2593 //   offset = 0: Use TM, safepoint polling.
2594 //   offset < 0: Use TMY, profiling safepoint polling.
2595 void MacroAssembler::load_from_polling_page(Register polling_page_address, int64_t offset) {
2596   if (Immediate::is_uimm12(offset)) {
2597     z_tm(offset, polling_page_address, mask_safepoint);
2598   } else {
2599     z_tmy(offset, polling_page_address, mask_profiling);
2600   }
2601 }
2602 
2603 // Check whether z_instruction is a read access to the polling page
2604 // which was emitted by load_from_polling_page(..).
2605 bool MacroAssembler::is_load_from_polling_page(address instr_loc) {
2606   unsigned long z_instruction;
2607   unsigned int  ilen = get_instruction(instr_loc, &z_instruction);
2608 
2609   if (ilen == 2) { return false; } // It's none of the allowed instructions.
2610 
2611   if (ilen == 4) {
2612     if (!is_z_tm(z_instruction)) { return false; } // It's len=4, but not a z_tm. fail.
2613 
2614     int ms = inv_mask(z_instruction,8,32);  // mask
2615     int ra = inv_reg(z_instruction,16,32);  // base register
2616     int ds = inv_uimm12(z_instruction);     // displacement
2617 
2618     if (!(ds == 0 && ra != 0 && ms == mask_safepoint)) {
2619       return false; // It's not a z_tm(0, ra, mask_safepoint). Fail.
2620     }
2621 
2622   } else { /* if (ilen == 6) */
2623 
2624     assert(!is_z_lg(z_instruction), "old form (LG) polling page access. Please fix and use TM(Y).");
2625 
2626     if (!is_z_tmy(z_instruction)) { return false; } // It's len=6, but not a z_tmy. fail.
2627 
2628     int ms = inv_mask(z_instruction,8,48);  // mask
2629     int ra = inv_reg(z_instruction,16,48);  // base register
2630     int ds = inv_simm20(z_instruction);     // displacement
2631   }
2632 
2633   return true;
2634 }
2635 
2636 // Extract poll address from instruction and ucontext.
2637 address MacroAssembler::get_poll_address(address instr_loc, void* ucontext) {
2638   assert(ucontext != NULL, "must have ucontext");
2639   ucontext_t* uc = (ucontext_t*) ucontext;
2640   unsigned long z_instruction;
2641   unsigned int ilen = get_instruction(instr_loc, &z_instruction);
2642 
2643   if (ilen == 4 && is_z_tm(z_instruction)) {
2644     int ra = inv_reg(z_instruction, 16, 32);  // base register
2645     int ds = inv_uimm12(z_instruction);       // displacement
2646     address addr = (address)uc->uc_mcontext.gregs[ra];
2647     return addr + ds;
2648   } else if (ilen == 6 && is_z_tmy(z_instruction)) {
2649     int ra = inv_reg(z_instruction, 16, 48);  // base register
2650     int ds = inv_simm20(z_instruction);       // displacement
2651     address addr = (address)uc->uc_mcontext.gregs[ra];
2652     return addr + ds;
2653   }
2654 
2655   ShouldNotReachHere();
2656   return NULL;
2657 }
2658 
2659 // Extract poll register from instruction.
2660 uint MacroAssembler::get_poll_register(address instr_loc) {
2661   unsigned long z_instruction;
2662   unsigned int ilen = get_instruction(instr_loc, &z_instruction);
2663 
2664   if (ilen == 4 && is_z_tm(z_instruction)) {
2665     return (uint)inv_reg(z_instruction, 16, 32);  // base register
2666   } else if (ilen == 6 && is_z_tmy(z_instruction)) {
2667     return (uint)inv_reg(z_instruction, 16, 48);  // base register
2668   }
2669 
2670   ShouldNotReachHere();
2671   return 0;
2672 }
2673 
2674 bool MacroAssembler::is_memory_serialization(int instruction, JavaThread* thread, void* ucontext) {
2675   ShouldNotCallThis();
2676   return false;
2677 }
2678 
2679 // Write serialization page so VM thread can do a pseudo remote membar
2680 // We use the current thread pointer to calculate a thread specific
2681 // offset to write to within the page. This minimizes bus traffic
2682 // due to cache line collision.
2683 void MacroAssembler::serialize_memory(Register thread, Register tmp1, Register tmp2) {
2684   assert_different_registers(tmp1, tmp2);
2685   z_sllg(tmp2, thread, os::get_serialize_page_shift_count());
2686   load_const_optimized(tmp1, (long) os::get_memory_serialize_page());
2687 
2688   int mask = os::get_serialize_page_mask();
2689   if (Immediate::is_uimm16(mask)) {
2690     z_nill(tmp2, mask);
2691     z_llghr(tmp2, tmp2);
2692   } else {
2693     z_nilf(tmp2, mask);
2694     z_llgfr(tmp2, tmp2);
2695   }
2696 
2697   z_release();
2698   z_st(Z_R0, 0, tmp2, tmp1);
2699 }
2700 
2701 // Don't rely on register locking, always use Z_R1 as scratch register instead.
2702 void MacroAssembler::bang_stack_with_offset(int offset) {
2703   // Stack grows down, caller passes positive offset.
2704   assert(offset > 0, "must bang with positive offset");
2705   if (Displacement::is_validDisp(-offset)) {
2706     z_tmy(-offset, Z_SP, mask_stackbang);
2707   } else {
2708     add2reg(Z_R1, -offset, Z_SP);    // Do not destroy Z_SP!!!
2709     z_tm(0, Z_R1, mask_stackbang);  // Just banging.
2710   }
2711 }
2712 
2713 void MacroAssembler::reserved_stack_check(Register return_pc) {
2714   // Test if reserved zone needs to be enabled.
2715   Label no_reserved_zone_enabling;
2716   assert(return_pc == Z_R14, "Return pc must be in R14 before z_br() to StackOverflow stub.");
2717   BLOCK_COMMENT("reserved_stack_check {");
2718 
2719   z_clg(Z_SP, Address(Z_thread, JavaThread::reserved_stack_activation_offset()));
2720   z_brl(no_reserved_zone_enabling);
2721 
2722   // Enable reserved zone again, throw stack overflow exception.
2723   save_return_pc();
2724   push_frame_abi160(0);
2725   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::enable_stack_reserved_zone), Z_thread);
2726   pop_frame();
2727   restore_return_pc();
2728 
2729   load_const_optimized(Z_R1, StubRoutines::throw_delayed_StackOverflowError_entry());
2730   // Don't use call() or z_basr(), they will invalidate Z_R14 which contains the return pc.
2731   z_br(Z_R1);
2732 
2733   should_not_reach_here();
2734 
2735   bind(no_reserved_zone_enabling);
2736   BLOCK_COMMENT("} reserved_stack_check");
2737 }
2738 
2739 // Defines obj, preserves var_size_in_bytes, okay for t2 == var_size_in_bytes.
2740 void MacroAssembler::tlab_allocate(Register obj,
2741                                    Register var_size_in_bytes,
2742                                    int con_size_in_bytes,
2743                                    Register t1,
2744                                    Label& slow_case) {
2745   assert_different_registers(obj, var_size_in_bytes, t1);
2746   Register end = t1;
2747   Register thread = Z_thread;
2748 
2749   z_lg(obj, Address(thread, JavaThread::tlab_top_offset()));
2750   if (var_size_in_bytes == noreg) {
2751     z_lay(end, Address(obj, con_size_in_bytes));
2752   } else {
2753     z_lay(end, Address(obj, var_size_in_bytes));
2754   }
2755   z_cg(end, Address(thread, JavaThread::tlab_end_offset()));
2756   branch_optimized(bcondHigh, slow_case);
2757 
2758   // Update the tlab top pointer.
2759   z_stg(end, Address(thread, JavaThread::tlab_top_offset()));
2760 
2761   // Recover var_size_in_bytes if necessary.
2762   if (var_size_in_bytes == end) {
2763     z_sgr(var_size_in_bytes, obj);
2764   }
2765 }
2766 
2767 // Emitter for interface method lookup.
2768 //   input: recv_klass, intf_klass, itable_index
2769 //   output: method_result
2770 //   kills: itable_index, temp1_reg, Z_R0, Z_R1
2771 // TODO: Temp2_reg is unused. we may use this emitter also in the itable stubs.
2772 // If the register is still not needed then, remove it.
2773 void MacroAssembler::lookup_interface_method(Register           recv_klass,
2774                                              Register           intf_klass,
2775                                              RegisterOrConstant itable_index,
2776                                              Register           method_result,
2777                                              Register           temp1_reg,
2778                                              Register           temp2_reg,
2779                                              Label&             no_such_interface) {
2780 
2781   const Register vtable_len = temp1_reg;    // Used to compute itable_entry_addr.
2782   const Register itable_entry_addr = Z_R1_scratch;
2783   const Register itable_interface = Z_R0_scratch;
2784 
2785   BLOCK_COMMENT("lookup_interface_method {");
2786 
2787   // Load start of itable entries into itable_entry_addr.
2788   z_llgf(vtable_len, Address(recv_klass, Klass::vtable_length_offset()));
2789   z_sllg(vtable_len, vtable_len, exact_log2(vtableEntry::size_in_bytes()));
2790 
2791   // Loop over all itable entries until desired interfaceOop(Rinterface) found.
2792   const int vtable_base_offset = in_bytes(Klass::vtable_start_offset());
2793 
2794   add2reg_with_index(itable_entry_addr,
2795                      vtable_base_offset + itableOffsetEntry::interface_offset_in_bytes(),
2796                      recv_klass, vtable_len);
2797 
2798   const int itable_offset_search_inc = itableOffsetEntry::size() * wordSize;
2799   Label     search;
2800 
2801   bind(search);
2802 
2803   // Handle IncompatibleClassChangeError.
2804   // If the entry is NULL then we've reached the end of the table
2805   // without finding the expected interface, so throw an exception.
2806   load_and_test_long(itable_interface, Address(itable_entry_addr));
2807   z_bre(no_such_interface);
2808 
2809   add2reg(itable_entry_addr, itable_offset_search_inc);
2810   z_cgr(itable_interface, intf_klass);
2811   z_brne(search);
2812 
2813   // Entry found and itable_entry_addr points to it, get offset of vtable for interface.
2814 
2815   const int vtable_offset_offset = (itableOffsetEntry::offset_offset_in_bytes() -
2816                                     itableOffsetEntry::interface_offset_in_bytes()) -
2817                                    itable_offset_search_inc;
2818 
2819   // Compute itableMethodEntry and get method and entry point
2820   // we use addressing with index and displacement, since the formula
2821   // for computing the entry's offset has a fixed and a dynamic part,
2822   // the latter depending on the matched interface entry and on the case,
2823   // that the itable index has been passed as a register, not a constant value.
2824   int method_offset = itableMethodEntry::method_offset_in_bytes();
2825                            // Fixed part (displacement), common operand.
2826   Register itable_offset;  // Dynamic part (index register).
2827 
2828   if (itable_index.is_register()) {
2829      // Compute the method's offset in that register, for the formula, see the
2830      // else-clause below.
2831      itable_offset = itable_index.as_register();
2832 
2833      z_sllg(itable_offset, itable_offset, exact_log2(itableMethodEntry::size() * wordSize));
2834      z_agf(itable_offset, vtable_offset_offset, itable_entry_addr);
2835   } else {
2836     itable_offset = Z_R1_scratch;
2837     // Displacement increases.
2838     method_offset += itableMethodEntry::size() * wordSize * itable_index.as_constant();
2839 
2840     // Load index from itable.
2841     z_llgf(itable_offset, vtable_offset_offset, itable_entry_addr);
2842   }
2843 
2844   // Finally load the method's oop.
2845   z_lg(method_result, method_offset, itable_offset, recv_klass);
2846   BLOCK_COMMENT("} lookup_interface_method");
2847 }
2848 
2849 // Lookup for virtual method invocation.
2850 void MacroAssembler::lookup_virtual_method(Register           recv_klass,
2851                                            RegisterOrConstant vtable_index,
2852                                            Register           method_result) {
2853   assert_different_registers(recv_klass, vtable_index.register_or_noreg());
2854   assert(vtableEntry::size() * wordSize == wordSize,
2855          "else adjust the scaling in the code below");
2856 
2857   BLOCK_COMMENT("lookup_virtual_method {");
2858 
2859   const int base = in_bytes(Klass::vtable_start_offset());
2860 
2861   if (vtable_index.is_constant()) {
2862     // Load with base + disp.
2863     Address vtable_entry_addr(recv_klass,
2864                               vtable_index.as_constant() * wordSize +
2865                               base +
2866                               vtableEntry::method_offset_in_bytes());
2867 
2868     z_lg(method_result, vtable_entry_addr);
2869   } else {
2870     // Shift index properly and load with base + index + disp.
2871     Register vindex = vtable_index.as_register();
2872     Address  vtable_entry_addr(recv_klass, vindex,
2873                                base + vtableEntry::method_offset_in_bytes());
2874 
2875     z_sllg(vindex, vindex, exact_log2(wordSize));
2876     z_lg(method_result, vtable_entry_addr);
2877   }
2878   BLOCK_COMMENT("} lookup_virtual_method");
2879 }
2880 
2881 // Factor out code to call ic_miss_handler.
2882 // Generate code to call the inline cache miss handler.
2883 //
2884 // In most cases, this code will be generated out-of-line.
2885 // The method parameters are intended to provide some variability.
2886 //   ICM          - Label which has to be bound to the start of useful code (past any traps).
2887 //   trapMarker   - Marking byte for the generated illtrap instructions (if any).
2888 //                  Any value except 0x00 is supported.
2889 //                  = 0x00 - do not generate illtrap instructions.
2890 //                         use nops to fill ununsed space.
2891 //   requiredSize - required size of the generated code. If the actually
2892 //                  generated code is smaller, use padding instructions to fill up.
2893 //                  = 0 - no size requirement, no padding.
2894 //   scratch      - scratch register to hold branch target address.
2895 //
2896 //  The method returns the code offset of the bound label.
2897 unsigned int MacroAssembler::call_ic_miss_handler(Label& ICM, int trapMarker, int requiredSize, Register scratch) {
2898   intptr_t startOffset = offset();
2899 
2900   // Prevent entry at content_begin().
2901   if (trapMarker != 0) {
2902     z_illtrap(trapMarker);
2903   }
2904 
2905   // Load address of inline cache miss code into scratch register
2906   // and branch to cache miss handler.
2907   BLOCK_COMMENT("IC miss handler {");
2908   BIND(ICM);
2909   unsigned int   labelOffset = offset();
2910   AddressLiteral icmiss(SharedRuntime::get_ic_miss_stub());
2911 
2912   load_const_optimized(scratch, icmiss);
2913   z_br(scratch);
2914 
2915   // Fill unused space.
2916   if (requiredSize > 0) {
2917     while ((offset() - startOffset) < requiredSize) {
2918       if (trapMarker == 0) {
2919         z_nop();
2920       } else {
2921         z_illtrap(trapMarker);
2922       }
2923     }
2924   }
2925   BLOCK_COMMENT("} IC miss handler");
2926   return labelOffset;
2927 }
2928 
2929 void MacroAssembler::nmethod_UEP(Label& ic_miss) {
2930   Register ic_reg       = as_Register(Matcher::inline_cache_reg_encode());
2931   int      klass_offset = oopDesc::klass_offset_in_bytes();
2932   if (!ImplicitNullChecks || MacroAssembler::needs_explicit_null_check(klass_offset)) {
2933     if (VM_Version::has_CompareBranch()) {
2934       z_cgij(Z_ARG1, 0, Assembler::bcondEqual, ic_miss);
2935     } else {
2936       z_ltgr(Z_ARG1, Z_ARG1);
2937       z_bre(ic_miss);
2938     }
2939   }
2940   // Compare cached class against klass from receiver.
2941   compare_klass_ptr(ic_reg, klass_offset, Z_ARG1, false);
2942   z_brne(ic_miss);
2943 }
2944 
2945 void MacroAssembler::check_klass_subtype_fast_path(Register   sub_klass,
2946                                                    Register   super_klass,
2947                                                    Register   temp1_reg,
2948                                                    Label*     L_success,
2949                                                    Label*     L_failure,
2950                                                    Label*     L_slow_path,
2951                                                    RegisterOrConstant super_check_offset) {
2952 
2953   const int sc_offset  = in_bytes(Klass::secondary_super_cache_offset());
2954   const int sco_offset = in_bytes(Klass::super_check_offset_offset());
2955 
2956   bool must_load_sco = (super_check_offset.constant_or_zero() == -1);
2957   bool need_slow_path = (must_load_sco ||
2958                          super_check_offset.constant_or_zero() == sc_offset);
2959 
2960   // Input registers must not overlap.
2961   assert_different_registers(sub_klass, super_klass, temp1_reg);
2962   if (super_check_offset.is_register()) {
2963     assert_different_registers(sub_klass, super_klass,
2964                                super_check_offset.as_register());
2965   } else if (must_load_sco) {
2966     assert(temp1_reg != noreg, "supply either a temp or a register offset");
2967   }
2968 
2969   const Register Rsuper_check_offset = temp1_reg;
2970 
2971   NearLabel L_fallthrough;
2972   int label_nulls = 0;
2973   if (L_success == NULL)   { L_success   = &L_fallthrough; label_nulls++; }
2974   if (L_failure == NULL)   { L_failure   = &L_fallthrough; label_nulls++; }
2975   if (L_slow_path == NULL) { L_slow_path = &L_fallthrough; label_nulls++; }
2976   assert(label_nulls <= 1 ||
2977          (L_slow_path == &L_fallthrough && label_nulls <= 2 && !need_slow_path),
2978          "at most one NULL in the batch, usually");
2979 
2980   BLOCK_COMMENT("check_klass_subtype_fast_path {");
2981   // If the pointers are equal, we are done (e.g., String[] elements).
2982   // This self-check enables sharing of secondary supertype arrays among
2983   // non-primary types such as array-of-interface. Otherwise, each such
2984   // type would need its own customized SSA.
2985   // We move this check to the front of the fast path because many
2986   // type checks are in fact trivially successful in this manner,
2987   // so we get a nicely predicted branch right at the start of the check.
2988   compare64_and_branch(sub_klass, super_klass, bcondEqual, *L_success);
2989 
2990   // Check the supertype display, which is uint.
2991   if (must_load_sco) {
2992     z_llgf(Rsuper_check_offset, sco_offset, super_klass);
2993     super_check_offset = RegisterOrConstant(Rsuper_check_offset);
2994   }
2995   Address super_check_addr(sub_klass, super_check_offset, 0);
2996   z_cg(super_klass, super_check_addr); // compare w/ displayed supertype
2997 
2998   // This check has worked decisively for primary supers.
2999   // Secondary supers are sought in the super_cache ('super_cache_addr').
3000   // (Secondary supers are interfaces and very deeply nested subtypes.)
3001   // This works in the same check above because of a tricky aliasing
3002   // between the super_cache and the primary super display elements.
3003   // (The 'super_check_addr' can address either, as the case requires.)
3004   // Note that the cache is updated below if it does not help us find
3005   // what we need immediately.
3006   // So if it was a primary super, we can just fail immediately.
3007   // Otherwise, it's the slow path for us (no success at this point).
3008 
3009   // Hacked jmp, which may only be used just before L_fallthrough.
3010 #define final_jmp(label)                                                \
3011   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
3012   else                            { branch_optimized(Assembler::bcondAlways, label); } /*omit semicolon*/
3013 
3014   if (super_check_offset.is_register()) {
3015     branch_optimized(Assembler::bcondEqual, *L_success);
3016     z_cfi(super_check_offset.as_register(), sc_offset);
3017     if (L_failure == &L_fallthrough) {
3018       branch_optimized(Assembler::bcondEqual, *L_slow_path);
3019     } else {
3020       branch_optimized(Assembler::bcondNotEqual, *L_failure);
3021       final_jmp(*L_slow_path);
3022     }
3023   } else if (super_check_offset.as_constant() == sc_offset) {
3024     // Need a slow path; fast failure is impossible.
3025     if (L_slow_path == &L_fallthrough) {
3026       branch_optimized(Assembler::bcondEqual, *L_success);
3027     } else {
3028       branch_optimized(Assembler::bcondNotEqual, *L_slow_path);
3029       final_jmp(*L_success);
3030     }
3031   } else {
3032     // No slow path; it's a fast decision.
3033     if (L_failure == &L_fallthrough) {
3034       branch_optimized(Assembler::bcondEqual, *L_success);
3035     } else {
3036       branch_optimized(Assembler::bcondNotEqual, *L_failure);
3037       final_jmp(*L_success);
3038     }
3039   }
3040 
3041   bind(L_fallthrough);
3042 #undef local_brc
3043 #undef final_jmp
3044   BLOCK_COMMENT("} check_klass_subtype_fast_path");
3045   // fallthru (to slow path)
3046 }
3047 
3048 void MacroAssembler::check_klass_subtype_slow_path(Register Rsubklass,
3049                                                    Register Rsuperklass,
3050                                                    Register Rarray_ptr,  // tmp
3051                                                    Register Rlength,     // tmp
3052                                                    Label* L_success,
3053                                                    Label* L_failure) {
3054   // Input registers must not overlap.
3055   // Also check for R1 which is explicitely used here.
3056   assert_different_registers(Z_R1, Rsubklass, Rsuperklass, Rarray_ptr, Rlength);
3057   NearLabel L_fallthrough, L_loop;
3058   int label_nulls = 0;
3059   if (L_success == NULL) { L_success = &L_fallthrough; label_nulls++; }
3060   if (L_failure == NULL) { L_failure = &L_fallthrough; label_nulls++; }
3061   assert(label_nulls <= 1, "at most one NULL in the batch");
3062 
3063   const int ss_offset = in_bytes(Klass::secondary_supers_offset());
3064   const int sc_offset = in_bytes(Klass::secondary_super_cache_offset());
3065 
3066   const int length_offset = Array<Klass*>::length_offset_in_bytes();
3067   const int base_offset   = Array<Klass*>::base_offset_in_bytes();
3068 
3069   // Hacked jmp, which may only be used just before L_fallthrough.
3070 #define final_jmp(label)                                                \
3071   if (&(label) == &L_fallthrough) { /*do nothing*/ }                    \
3072   else                            branch_optimized(Assembler::bcondAlways, label) /*omit semicolon*/
3073 
3074   NearLabel loop_iterate, loop_count, match;
3075 
3076   BLOCK_COMMENT("check_klass_subtype_slow_path {");
3077   z_lg(Rarray_ptr, ss_offset, Rsubklass);
3078 
3079   load_and_test_int(Rlength, Address(Rarray_ptr, length_offset));
3080   branch_optimized(Assembler::bcondZero, *L_failure);
3081 
3082   // Oops in table are NO MORE compressed.
3083   z_cg(Rsuperklass, base_offset, Rarray_ptr); // Check array element for match.
3084   z_bre(match);                               // Shortcut for array length = 1.
3085 
3086   // No match yet, so we must walk the array's elements.
3087   z_lngfr(Rlength, Rlength);
3088   z_sllg(Rlength, Rlength, LogBytesPerWord); // -#bytes of cache array
3089   z_llill(Z_R1, BytesPerWord);               // Set increment/end index.
3090   add2reg(Rlength, 2 * BytesPerWord);        // start index  = -(n-2)*BytesPerWord
3091   z_slgr(Rarray_ptr, Rlength);               // start addr: +=  (n-2)*BytesPerWord
3092   z_bru(loop_count);
3093 
3094   BIND(loop_iterate);
3095   z_cg(Rsuperklass, base_offset, Rlength, Rarray_ptr); // Check array element for match.
3096   z_bre(match);
3097   BIND(loop_count);
3098   z_brxlg(Rlength, Z_R1, loop_iterate);
3099 
3100   // Rsuperklass not found among secondary super classes -> failure.
3101   branch_optimized(Assembler::bcondAlways, *L_failure);
3102 
3103   // Got a hit. Return success (zero result). Set cache.
3104   // Cache load doesn't happen here. For speed it is directly emitted by the compiler.
3105 
3106   BIND(match);
3107 
3108   z_stg(Rsuperklass, sc_offset, Rsubklass); // Save result to cache.
3109 
3110   final_jmp(*L_success);
3111 
3112   // Exit to the surrounding code.
3113   BIND(L_fallthrough);
3114 #undef local_brc
3115 #undef final_jmp
3116   BLOCK_COMMENT("} check_klass_subtype_slow_path");
3117 }
3118 
3119 // Emitter for combining fast and slow path.
3120 void MacroAssembler::check_klass_subtype(Register sub_klass,
3121                                          Register super_klass,
3122                                          Register temp1_reg,
3123                                          Register temp2_reg,
3124                                          Label&   L_success) {
3125   NearLabel failure;
3126   BLOCK_COMMENT(err_msg("check_klass_subtype(%s subclass of %s) {", sub_klass->name(), super_klass->name()));
3127   check_klass_subtype_fast_path(sub_klass, super_klass, temp1_reg,
3128                                 &L_success, &failure, NULL);
3129   check_klass_subtype_slow_path(sub_klass, super_klass,
3130                                 temp1_reg, temp2_reg, &L_success, NULL);
3131   BIND(failure);
3132   BLOCK_COMMENT("} check_klass_subtype");
3133 }
3134 
3135 // Increment a counter at counter_address when the eq condition code is
3136 // set. Kills registers tmp1_reg and tmp2_reg and preserves the condition code.
3137 void MacroAssembler::increment_counter_eq(address counter_address, Register tmp1_reg, Register tmp2_reg) {
3138   Label l;
3139   z_brne(l);
3140   load_const(tmp1_reg, counter_address);
3141   add2mem_32(Address(tmp1_reg), 1, tmp2_reg);
3142   z_cr(tmp1_reg, tmp1_reg); // Set cc to eq.
3143   bind(l);
3144 }
3145 
3146 // Semantics are dependent on the slow_case label:
3147 //   If the slow_case label is not NULL, failure to biased-lock the object
3148 //   transfers control to the location of the slow_case label. If the
3149 //   object could be biased-locked, control is transferred to the done label.
3150 //   The condition code is unpredictable.
3151 //
3152 //   If the slow_case label is NULL, failure to biased-lock the object results
3153 //   in a transfer of control to the done label with a condition code of not_equal.
3154 //   If the biased-lock could be successfully obtained, control is transfered to
3155 //   the done label with a condition code of equal.
3156 //   It is mandatory to react on the condition code At the done label.
3157 //
3158 void MacroAssembler::biased_locking_enter(Register  obj_reg,
3159                                           Register  mark_reg,
3160                                           Register  temp_reg,
3161                                           Register  temp2_reg,    // May be Z_RO!
3162                                           Label    &done,
3163                                           Label    *slow_case) {
3164   assert(UseBiasedLocking, "why call this otherwise?");
3165   assert_different_registers(obj_reg, mark_reg, temp_reg, temp2_reg);
3166 
3167   Label cas_label; // Try, if implemented, CAS locking. Fall thru to slow path otherwise.
3168 
3169   BLOCK_COMMENT("biased_locking_enter {");
3170 
3171   // Biased locking
3172   // See whether the lock is currently biased toward our thread and
3173   // whether the epoch is still valid.
3174   // Note that the runtime guarantees sufficient alignment of JavaThread
3175   // pointers to allow age to be placed into low bits.
3176   assert(markOopDesc::age_shift == markOopDesc::lock_bits + markOopDesc::biased_lock_bits,
3177          "biased locking makes assumptions about bit layout");
3178   z_lr(temp_reg, mark_reg);
3179   z_nilf(temp_reg, markOopDesc::biased_lock_mask_in_place);
3180   z_chi(temp_reg, markOopDesc::biased_lock_pattern);
3181   z_brne(cas_label);  // Try cas if object is not biased, i.e. cannot be biased locked.
3182 
3183   load_prototype_header(temp_reg, obj_reg);
3184   load_const_optimized(temp2_reg, ~((int) markOopDesc::age_mask_in_place));
3185 
3186   z_ogr(temp_reg, Z_thread);
3187   z_xgr(temp_reg, mark_reg);
3188   z_ngr(temp_reg, temp2_reg);
3189   if (PrintBiasedLockingStatistics) {
3190     increment_counter_eq((address) BiasedLocking::biased_lock_entry_count_addr(), mark_reg, temp2_reg);
3191     // Restore mark_reg.
3192     z_lg(mark_reg, oopDesc::mark_offset_in_bytes(), obj_reg);
3193   }
3194   branch_optimized(Assembler::bcondEqual, done);  // Biased lock obtained, return success.
3195 
3196   Label try_revoke_bias;
3197   Label try_rebias;
3198   Address mark_addr = Address(obj_reg, oopDesc::mark_offset_in_bytes());
3199 
3200   //----------------------------------------------------------------------------
3201   // At this point we know that the header has the bias pattern and
3202   // that we are not the bias owner in the current epoch. We need to
3203   // figure out more details about the state of the header in order to
3204   // know what operations can be legally performed on the object's
3205   // header.
3206 
3207   // If the low three bits in the xor result aren't clear, that means
3208   // the prototype header is no longer biased and we have to revoke
3209   // the bias on this object.
3210   z_tmll(temp_reg, markOopDesc::biased_lock_mask_in_place);
3211   z_brnaz(try_revoke_bias);
3212 
3213   // Biasing is still enabled for this data type. See whether the
3214   // epoch of the current bias is still valid, meaning that the epoch
3215   // bits of the mark word are equal to the epoch bits of the
3216   // prototype header. (Note that the prototype header's epoch bits
3217   // only change at a safepoint.) If not, attempt to rebias the object
3218   // toward the current thread. Note that we must be absolutely sure
3219   // that the current epoch is invalid in order to do this because
3220   // otherwise the manipulations it performs on the mark word are
3221   // illegal.
3222   z_tmll(temp_reg, markOopDesc::epoch_mask_in_place);
3223   z_brnaz(try_rebias);
3224 
3225   //----------------------------------------------------------------------------
3226   // The epoch of the current bias is still valid but we know nothing
3227   // about the owner; it might be set or it might be clear. Try to
3228   // acquire the bias of the object using an atomic operation. If this
3229   // fails we will go in to the runtime to revoke the object's bias.
3230   // Note that we first construct the presumed unbiased header so we
3231   // don't accidentally blow away another thread's valid bias.
3232   z_nilf(mark_reg, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place |
3233          markOopDesc::epoch_mask_in_place);
3234   z_lgr(temp_reg, Z_thread);
3235   z_llgfr(mark_reg, mark_reg);
3236   z_ogr(temp_reg, mark_reg);
3237 
3238   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
3239 
3240   z_csg(mark_reg, temp_reg, 0, obj_reg);
3241 
3242   // If the biasing toward our thread failed, this means that
3243   // another thread succeeded in biasing it toward itself and we
3244   // need to revoke that bias. The revocation will occur in the
3245   // interpreter runtime in the slow case.
3246 
3247   if (PrintBiasedLockingStatistics) {
3248     increment_counter_eq((address) BiasedLocking::anonymously_biased_lock_entry_count_addr(),
3249                          temp_reg, temp2_reg);
3250   }
3251   if (slow_case != NULL) {
3252     branch_optimized(Assembler::bcondNotEqual, *slow_case); // Biased lock not obtained, need to go the long way.
3253   }
3254   branch_optimized(Assembler::bcondAlways, done);           // Biased lock status given in condition code.
3255 
3256   //----------------------------------------------------------------------------
3257   bind(try_rebias);
3258   // At this point we know the epoch has expired, meaning that the
3259   // current "bias owner", if any, is actually invalid. Under these
3260   // circumstances _only_, we are allowed to use the current header's
3261   // value as the comparison value when doing the cas to acquire the
3262   // bias in the current epoch. In other words, we allow transfer of
3263   // the bias from one thread to another directly in this situation.
3264 
3265   z_nilf(mark_reg, markOopDesc::biased_lock_mask_in_place | markOopDesc::age_mask_in_place | markOopDesc::epoch_mask_in_place);
3266   load_prototype_header(temp_reg, obj_reg);
3267   z_llgfr(mark_reg, mark_reg);
3268 
3269   z_ogr(temp_reg, Z_thread);
3270 
3271   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
3272 
3273   z_csg(mark_reg, temp_reg, 0, obj_reg);
3274 
3275   // If the biasing toward our thread failed, this means that
3276   // another thread succeeded in biasing it toward itself and we
3277   // need to revoke that bias. The revocation will occur in the
3278   // interpreter runtime in the slow case.
3279 
3280   if (PrintBiasedLockingStatistics) {
3281     increment_counter_eq((address) BiasedLocking::rebiased_lock_entry_count_addr(), temp_reg, temp2_reg);
3282   }
3283   if (slow_case != NULL) {
3284     branch_optimized(Assembler::bcondNotEqual, *slow_case);  // Biased lock not obtained, need to go the long way.
3285   }
3286   z_bru(done);           // Biased lock status given in condition code.
3287 
3288   //----------------------------------------------------------------------------
3289   bind(try_revoke_bias);
3290   // The prototype mark in the klass doesn't have the bias bit set any
3291   // more, indicating that objects of this data type are not supposed
3292   // to be biased any more. We are going to try to reset the mark of
3293   // this object to the prototype value and fall through to the
3294   // CAS-based locking scheme. Note that if our CAS fails, it means
3295   // that another thread raced us for the privilege of revoking the
3296   // bias of this particular object, so it's okay to continue in the
3297   // normal locking code.
3298   load_prototype_header(temp_reg, obj_reg);
3299 
3300   assert(oopDesc::mark_offset_in_bytes() == 0, "offset of _mark is not 0");
3301 
3302   z_csg(mark_reg, temp_reg, 0, obj_reg);
3303 
3304   // Fall through to the normal CAS-based lock, because no matter what
3305   // the result of the above CAS, some thread must have succeeded in
3306   // removing the bias bit from the object's header.
3307   if (PrintBiasedLockingStatistics) {
3308     // z_cgr(mark_reg, temp2_reg);
3309     increment_counter_eq((address) BiasedLocking::revoked_lock_entry_count_addr(), temp_reg, temp2_reg);
3310   }
3311 
3312   bind(cas_label);
3313   BLOCK_COMMENT("} biased_locking_enter");
3314 }
3315 
3316 void MacroAssembler::biased_locking_exit(Register mark_addr, Register temp_reg, Label& done) {
3317   // Check for biased locking unlock case, which is a no-op
3318   // Note: we do not have to check the thread ID for two reasons.
3319   // First, the interpreter checks for IllegalMonitorStateException at
3320   // a higher level. Second, if the bias was revoked while we held the
3321   // lock, the object could not be rebiased toward another thread, so
3322   // the bias bit would be clear.
3323   BLOCK_COMMENT("biased_locking_exit {");
3324 
3325   z_lg(temp_reg, 0, mark_addr);
3326   z_nilf(temp_reg, markOopDesc::biased_lock_mask_in_place);
3327 
3328   z_chi(temp_reg, markOopDesc::biased_lock_pattern);
3329   z_bre(done);
3330   BLOCK_COMMENT("} biased_locking_exit");
3331 }
3332 
3333 void MacroAssembler::compiler_fast_lock_object(Register oop, Register box, Register temp1, Register temp2, bool try_bias) {
3334   Register displacedHeader = temp1;
3335   Register currentHeader = temp1;
3336   Register temp = temp2;
3337   NearLabel done, object_has_monitor;
3338 
3339   BLOCK_COMMENT("compiler_fast_lock_object {");
3340 
3341   // Load markOop from oop into mark.
3342   z_lg(displacedHeader, 0, oop);
3343 
3344   if (try_bias) {
3345     biased_locking_enter(oop, displacedHeader, temp, Z_R0, done);
3346   }
3347 
3348   // Handle existing monitor.
3349   if ((EmitSync & 0x01) == 0) {
3350     // The object has an existing monitor iff (mark & monitor_value) != 0.
3351     guarantee(Immediate::is_uimm16(markOopDesc::monitor_value), "must be half-word");
3352     z_lr(temp, displacedHeader);
3353     z_nill(temp, markOopDesc::monitor_value);
3354     z_brne(object_has_monitor);
3355   }
3356 
3357   // Set mark to markOop | markOopDesc::unlocked_value.
3358   z_oill(displacedHeader, markOopDesc::unlocked_value);
3359 
3360   // Load Compare Value application register.
3361 
3362   // Initialize the box (must happen before we update the object mark).
3363   z_stg(displacedHeader, BasicLock::displaced_header_offset_in_bytes(), box);
3364 
3365   // Memory Fence (in cmpxchgd)
3366   // Compare object markOop with mark and if equal exchange scratch1 with object markOop.
3367 
3368   // If the compare-and-swap succeeded, then we found an unlocked object and we
3369   // have now locked it.
3370   z_csg(displacedHeader, box, 0, oop);
3371   assert(currentHeader==displacedHeader, "must be same register"); // Identified two registers from z/Architecture.
3372   z_bre(done);
3373 
3374   // We did not see an unlocked object so try the fast recursive case.
3375 
3376   z_sgr(currentHeader, Z_SP);
3377   load_const_optimized(temp, (~(os::vm_page_size()-1) | markOopDesc::lock_mask_in_place));
3378 
3379   z_ngr(currentHeader, temp);
3380   //   z_brne(done);
3381   //   z_release();
3382   z_stg(currentHeader/*==0 or not 0*/, BasicLock::displaced_header_offset_in_bytes(), box);
3383 
3384   z_bru(done);
3385 
3386   if ((EmitSync & 0x01) == 0) {
3387     Register zero = temp;
3388     Register monitor_tagged = displacedHeader; // Tagged with markOopDesc::monitor_value.
3389     bind(object_has_monitor);
3390     // The object's monitor m is unlocked iff m->owner == NULL,
3391     // otherwise m->owner may contain a thread or a stack address.
3392     //
3393     // Try to CAS m->owner from NULL to current thread.
3394     z_lghi(zero, 0);
3395     // If m->owner is null, then csg succeeds and sets m->owner=THREAD and CR=EQ.
3396     z_csg(zero, Z_thread, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), monitor_tagged);
3397     // Store a non-null value into the box.
3398     z_stg(box, BasicLock::displaced_header_offset_in_bytes(), box);
3399 #ifdef ASSERT
3400       z_brne(done);
3401       // We've acquired the monitor, check some invariants.
3402       // Invariant 1: _recursions should be 0.
3403       asm_assert_mem8_is_zero(OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions), monitor_tagged,
3404                               "monitor->_recursions should be 0", -1);
3405       z_ltgr(zero, zero); // Set CR=EQ.
3406 #endif
3407   }
3408   bind(done);
3409 
3410   BLOCK_COMMENT("} compiler_fast_lock_object");
3411   // If locking was successful, CR should indicate 'EQ'.
3412   // The compiler or the native wrapper generates a branch to the runtime call
3413   // _complete_monitor_locking_Java.
3414 }
3415 
3416 void MacroAssembler::compiler_fast_unlock_object(Register oop, Register box, Register temp1, Register temp2, bool try_bias) {
3417   Register displacedHeader = temp1;
3418   Register currentHeader = temp2;
3419   Register temp = temp1;
3420   Register monitor = temp2;
3421 
3422   Label done, object_has_monitor;
3423 
3424   BLOCK_COMMENT("compiler_fast_unlock_object {");
3425 
3426   if (try_bias) {
3427     biased_locking_exit(oop, currentHeader, done);
3428   }
3429 
3430   // Find the lock address and load the displaced header from the stack.
3431   // if the displaced header is zero, we have a recursive unlock.
3432   load_and_test_long(displacedHeader, Address(box, BasicLock::displaced_header_offset_in_bytes()));
3433   z_bre(done);
3434 
3435   // Handle existing monitor.
3436   if ((EmitSync & 0x02) == 0) {
3437     // The object has an existing monitor iff (mark & monitor_value) != 0.
3438     z_lg(currentHeader, oopDesc::mark_offset_in_bytes(), oop);
3439     guarantee(Immediate::is_uimm16(markOopDesc::monitor_value), "must be half-word");
3440     z_nill(currentHeader, markOopDesc::monitor_value);
3441     z_brne(object_has_monitor);
3442   }
3443 
3444   // Check if it is still a light weight lock, this is true if we see
3445   // the stack address of the basicLock in the markOop of the object
3446   // copy box to currentHeader such that csg does not kill it.
3447   z_lgr(currentHeader, box);
3448   z_csg(currentHeader, displacedHeader, 0, oop);
3449   z_bru(done); // Csg sets CR as desired.
3450 
3451   // Handle existing monitor.
3452   if ((EmitSync & 0x02) == 0) {
3453     bind(object_has_monitor);
3454     z_lg(currentHeader, oopDesc::mark_offset_in_bytes(), oop);    // CurrentHeader is tagged with monitor_value set.
3455     load_and_test_long(temp, Address(currentHeader, OM_OFFSET_NO_MONITOR_VALUE_TAG(recursions)));
3456     z_brne(done);
3457     load_and_test_long(temp, Address(currentHeader, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner)));
3458     z_brne(done);
3459     load_and_test_long(temp, Address(currentHeader, OM_OFFSET_NO_MONITOR_VALUE_TAG(EntryList)));
3460     z_brne(done);
3461     load_and_test_long(temp, Address(currentHeader, OM_OFFSET_NO_MONITOR_VALUE_TAG(cxq)));
3462     z_brne(done);
3463     z_release();
3464     z_stg(temp/*=0*/, OM_OFFSET_NO_MONITOR_VALUE_TAG(owner), currentHeader);
3465   }
3466 
3467   bind(done);
3468 
3469   BLOCK_COMMENT("} compiler_fast_unlock_object");
3470   // flag == EQ indicates success
3471   // flag == NE indicates failure
3472 }
3473 
3474 // Write to card table for modification at store_addr - register is destroyed afterwards.
3475 void MacroAssembler::card_write_barrier_post(Register store_addr, Register tmp) {
3476   CardTableModRefBS* bs = (CardTableModRefBS*) Universe::heap()->barrier_set();
3477   assert(bs->kind() == BarrierSet::CardTableForRS ||
3478          bs->kind() == BarrierSet::CardTableExtension, "wrong barrier");
3479   assert_different_registers(store_addr, tmp);
3480   z_srlg(store_addr, store_addr, CardTableModRefBS::card_shift);
3481   load_absolute_address(tmp, (address)bs->byte_map_base);
3482   z_agr(store_addr, tmp);
3483   z_mvi(0, store_addr, 0); // Store byte 0.
3484 }
3485 
3486 void MacroAssembler::resolve_jobject(Register value, Register tmp1, Register tmp2) {
3487   NearLabel Ldone;
3488   z_ltgr(tmp1, value);
3489   z_bre(Ldone);          // Use NULL result as-is.
3490 
3491   z_nill(value, ~JNIHandles::weak_tag_mask);
3492   z_lg(value, 0, value); // Resolve (untagged) jobject.
3493 
3494 #if INCLUDE_ALL_GCS
3495   if (UseG1GC) {
3496     NearLabel Lnot_weak;
3497     z_tmll(tmp1, JNIHandles::weak_tag_mask); // Test for jweak tag.
3498     z_braz(Lnot_weak);
3499     verify_oop(value);
3500     g1_write_barrier_pre(noreg /* obj */,
3501                          noreg /* offset */,
3502                          value /* pre_val */,
3503                          noreg /* val */,
3504                          tmp1  /* tmp1 */,
3505                          tmp2  /* tmp2 */,
3506                          true  /* pre_val_needed */);
3507     bind(Lnot_weak);
3508   }
3509 #endif // INCLUDE_ALL_GCS
3510   verify_oop(value);
3511   bind(Ldone);
3512 }
3513 
3514 #if INCLUDE_ALL_GCS
3515 
3516 //------------------------------------------------------
3517 // General G1 pre-barrier generator.
3518 // Purpose: record the previous value if it is not null.
3519 // All non-tmps are preserved.
3520 //------------------------------------------------------
3521 // Note: Rpre_val needs special attention.
3522 //   The flag pre_val_needed indicated that the caller of this emitter function
3523 //   relies on Rpre_val containing the correct value, that is:
3524 //     either the value it contained on entry to this code segment
3525 //     or the value that was loaded into the register from (Robj+offset).
3526 //
3527 //   Independent from this requirement, the contents of Rpre_val must survive
3528 //   the push_frame() operation. push_frame() uses Z_R0_scratch by default
3529 //   to temporarily remember the frame pointer.
3530 //   If Rpre_val is assigned Z_R0_scratch by the caller, code must be emitted to
3531 //   save it's value.
3532 void MacroAssembler::g1_write_barrier_pre(Register           Robj,
3533                                           RegisterOrConstant offset,
3534                                           Register           Rpre_val,      // Ideally, this is a non-volatile register.
3535                                           Register           Rval,          // Will be preserved.
3536                                           Register           Rtmp1,         // If Rpre_val is volatile, either Rtmp1
3537                                           Register           Rtmp2,         // or Rtmp2 has to be non-volatile..
3538                                           bool               pre_val_needed // Save Rpre_val across runtime call, caller uses it.
3539                                        ) {
3540   Label callRuntime, filtered;
3541   const int active_offset = in_bytes(JavaThread::satb_mark_queue_offset() + SATBMarkQueue::byte_offset_of_active());
3542   const int buffer_offset = in_bytes(JavaThread::satb_mark_queue_offset() + SATBMarkQueue::byte_offset_of_buf());
3543   const int index_offset  = in_bytes(JavaThread::satb_mark_queue_offset() + SATBMarkQueue::byte_offset_of_index());
3544   assert_different_registers(Rtmp1, Rtmp2, Z_R0_scratch); // None of the Rtmp<i> must be Z_R0!!
3545   assert_different_registers(Robj, Z_R0_scratch);         // Used for addressing. Furthermore, push_frame destroys Z_R0!!
3546   assert_different_registers(Rval, Z_R0_scratch);         // push_frame destroys Z_R0!!
3547 
3548 #ifdef ASSERT
3549   // make sure the register is not Z_R0. Used for addressing. Furthermore, would be destroyed by push_frame.
3550   if (offset.is_register() && offset.as_register()->encoding() == 0) {
3551     tty->print_cr("Roffset(g1_write_barrier_pre)  = %%r%d", offset.as_register()->encoding());
3552     assert(false, "bad register for offset");
3553   }
3554 #endif
3555 
3556   BLOCK_COMMENT("g1_write_barrier_pre {");
3557 
3558   // Is marking active?
3559   // Note: value is loaded for test purposes only. No further use here.
3560   if (in_bytes(SATBMarkQueue::byte_width_of_active()) == 4) {
3561     load_and_test_int(Rtmp1, Address(Z_thread, active_offset));
3562   } else {
3563     guarantee(in_bytes(SATBMarkQueue::byte_width_of_active()) == 1, "Assumption");
3564     load_and_test_byte(Rtmp1, Address(Z_thread, active_offset));
3565   }
3566   z_bre(filtered); // Activity indicator is zero, so there is no marking going on currently.
3567 
3568   assert(Rpre_val != noreg, "must have a real register");
3569 
3570 
3571   // If an object is given, we need to load the previous value into Rpre_val.
3572   if (Robj != noreg) {
3573     // Load the previous value...
3574     Register ixReg = offset.is_register() ? offset.register_or_noreg() : Z_R0;
3575     if (UseCompressedOops) {
3576       z_llgf(Rpre_val, offset.constant_or_zero(), ixReg, Robj);
3577     } else {
3578       z_lg(Rpre_val, offset.constant_or_zero(), ixReg, Robj);
3579     }
3580   }
3581 
3582   // Is the previous value NULL?
3583   // If so, we don't need to record it and we're done.
3584   // Note: pre_val is loaded, decompressed and stored (directly or via runtime call).
3585   //       Register contents is preserved across runtime call if caller requests to do so.
3586   z_ltgr(Rpre_val, Rpre_val);
3587   z_bre(filtered); // previous value is NULL, so we don't need to record it.
3588 
3589   // Decode the oop now. We know it's not NULL.
3590   if (Robj != noreg && UseCompressedOops) {
3591     oop_decoder(Rpre_val, Rpre_val, /*maybeNULL=*/false);
3592   }
3593 
3594   // OK, it's not filtered, so we'll need to call enqueue.
3595 
3596   // We can store the original value in the thread's buffer
3597   // only if index > 0. Otherwise, we need runtime to handle.
3598   // (The index field is typed as size_t.)
3599   Register Rbuffer = Rtmp1, Rindex = Rtmp2;
3600   assert_different_registers(Rbuffer, Rindex, Rpre_val);
3601 
3602   z_lg(Rbuffer, buffer_offset, Z_thread);
3603 
3604   load_and_test_long(Rindex, Address(Z_thread, index_offset));
3605   z_bre(callRuntime); // If index == 0, goto runtime.
3606 
3607   add2reg(Rindex, -wordSize); // Decrement index.
3608   z_stg(Rindex, index_offset, Z_thread);
3609 
3610   // Record the previous value.
3611   z_stg(Rpre_val, 0, Rbuffer, Rindex);
3612   z_bru(filtered);  // We are done.
3613 
3614   Rbuffer = noreg;  // end of life
3615   Rindex  = noreg;  // end of life
3616 
3617   bind(callRuntime);
3618 
3619   // Save some registers (inputs and result) over runtime call
3620   // by spilling them into the top frame.
3621   if (Robj != noreg && Robj->is_volatile()) {
3622     z_stg(Robj, Robj->encoding()*BytesPerWord, Z_SP);
3623   }
3624   if (offset.is_register() && offset.as_register()->is_volatile()) {
3625     Register Roff = offset.as_register();
3626     z_stg(Roff, Roff->encoding()*BytesPerWord, Z_SP);
3627   }
3628   if (Rval != noreg && Rval->is_volatile()) {
3629     z_stg(Rval, Rval->encoding()*BytesPerWord, Z_SP);
3630   }
3631 
3632   // Save Rpre_val (result) over runtime call.
3633   Register Rpre_save = Rpre_val;
3634   if ((Rpre_val == Z_R0_scratch) || (pre_val_needed && Rpre_val->is_volatile())) {
3635     guarantee(!Rtmp1->is_volatile() || !Rtmp2->is_volatile(), "oops!");
3636     Rpre_save = !Rtmp1->is_volatile() ? Rtmp1 : Rtmp2;
3637   }
3638   lgr_if_needed(Rpre_save, Rpre_val);
3639 
3640   // Push frame to protect top frame with return pc and spilled register values.
3641   save_return_pc();
3642   push_frame_abi160(0); // Will use Z_R0 as tmp.
3643 
3644   // Rpre_val may be destroyed by push_frame().
3645   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_pre), Rpre_save, Z_thread);
3646 
3647   pop_frame();
3648   restore_return_pc();
3649 
3650   // Restore spilled values.
3651   if (Robj != noreg && Robj->is_volatile()) {
3652     z_lg(Robj, Robj->encoding()*BytesPerWord, Z_SP);
3653   }
3654   if (offset.is_register() && offset.as_register()->is_volatile()) {
3655     Register Roff = offset.as_register();
3656     z_lg(Roff, Roff->encoding()*BytesPerWord, Z_SP);
3657   }
3658   if (Rval != noreg && Rval->is_volatile()) {
3659     z_lg(Rval, Rval->encoding()*BytesPerWord, Z_SP);
3660   }
3661   if (pre_val_needed && Rpre_val->is_volatile()) {
3662     lgr_if_needed(Rpre_val, Rpre_save);
3663   }
3664 
3665   bind(filtered);
3666   BLOCK_COMMENT("} g1_write_barrier_pre");
3667 }
3668 
3669 // General G1 post-barrier generator.
3670 // Purpose: Store cross-region card.
3671 void MacroAssembler::g1_write_barrier_post(Register Rstore_addr,
3672                                            Register Rnew_val,
3673                                            Register Rtmp1,
3674                                            Register Rtmp2,
3675                                            Register Rtmp3) {
3676   Label callRuntime, filtered;
3677 
3678   assert_different_registers(Rstore_addr, Rnew_val, Rtmp1, Rtmp2); // Most probably, Rnew_val == Rtmp3.
3679 
3680   G1SATBCardTableModRefBS* bs = (G1SATBCardTableModRefBS*) Universe::heap()->barrier_set();
3681   assert(bs->kind() == BarrierSet::G1SATBCTLogging, "wrong barrier");
3682 
3683   BLOCK_COMMENT("g1_write_barrier_post {");
3684 
3685   // Does store cross heap regions?
3686   // It does if the two addresses specify different grain addresses.
3687   if (G1RSBarrierRegionFilter) {
3688     if (VM_Version::has_DistinctOpnds()) {
3689       z_xgrk(Rtmp1, Rstore_addr, Rnew_val);
3690     } else {
3691       z_lgr(Rtmp1, Rstore_addr);
3692       z_xgr(Rtmp1, Rnew_val);
3693     }
3694     z_srag(Rtmp1, Rtmp1, HeapRegion::LogOfHRGrainBytes);
3695     z_bre(filtered);
3696   }
3697 
3698   // Crosses regions, storing NULL?
3699 #ifdef ASSERT
3700   z_ltgr(Rnew_val, Rnew_val);
3701   asm_assert_ne("null oop not allowed (G1)", 0x255); // TODO: also on z? Checked by caller on PPC64, so following branch is obsolete:
3702   z_bre(filtered);  // Safety net: don't break if we have a NULL oop.
3703 #endif
3704   Rnew_val = noreg; // end of lifetime
3705 
3706   // Storing region crossing non-NULL, is card already dirty?
3707   assert(sizeof(*bs->byte_map_base) == sizeof(jbyte), "adjust this code");
3708   assert_different_registers(Rtmp1, Rtmp2, Rtmp3);
3709   // Make sure not to use Z_R0 for any of these registers.
3710   Register Rcard_addr = (Rtmp1 != Z_R0_scratch) ? Rtmp1 : Rtmp3;
3711   Register Rbase      = (Rtmp2 != Z_R0_scratch) ? Rtmp2 : Rtmp3;
3712 
3713   // calculate address of card
3714   load_const_optimized(Rbase, (address)bs->byte_map_base);        // Card table base.
3715   z_srlg(Rcard_addr, Rstore_addr, CardTableModRefBS::card_shift); // Index into card table.
3716   z_algr(Rcard_addr, Rbase);                                      // Explicit calculation needed for cli.
3717   Rbase = noreg; // end of lifetime
3718 
3719   // Filter young.
3720   assert((unsigned int)G1SATBCardTableModRefBS::g1_young_card_val() <= 255, "otherwise check this code");
3721   z_cli(0, Rcard_addr, (int)G1SATBCardTableModRefBS::g1_young_card_val());
3722   z_bre(filtered);
3723 
3724   // Check the card value. If dirty, we're done.
3725   // This also avoids false sharing of the (already dirty) card.
3726   z_sync(); // Required to support concurrent cleaning.
3727   assert((unsigned int)CardTableModRefBS::dirty_card_val() <= 255, "otherwise check this code");
3728   z_cli(0, Rcard_addr, CardTableModRefBS::dirty_card_val()); // Reload after membar.
3729   z_bre(filtered);
3730 
3731   // Storing a region crossing, non-NULL oop, card is clean.
3732   // Dirty card and log.
3733   z_mvi(0, Rcard_addr, CardTableModRefBS::dirty_card_val());
3734 
3735   Register Rcard_addr_x = Rcard_addr;
3736   Register Rqueue_index = (Rtmp2 != Z_R0_scratch) ? Rtmp2 : Rtmp1;
3737   Register Rqueue_buf   = (Rtmp3 != Z_R0_scratch) ? Rtmp3 : Rtmp1;
3738   const int qidx_off    = in_bytes(JavaThread::dirty_card_queue_offset() + SATBMarkQueue::byte_offset_of_index());
3739   const int qbuf_off    = in_bytes(JavaThread::dirty_card_queue_offset() + SATBMarkQueue::byte_offset_of_buf());
3740   if ((Rcard_addr == Rqueue_buf) || (Rcard_addr == Rqueue_index)) {
3741     Rcard_addr_x = Z_R0_scratch;  // Register shortage. We have to use Z_R0.
3742   }
3743   lgr_if_needed(Rcard_addr_x, Rcard_addr);
3744 
3745   load_and_test_long(Rqueue_index, Address(Z_thread, qidx_off));
3746   z_bre(callRuntime); // Index == 0 then jump to runtime.
3747 
3748   z_lg(Rqueue_buf, qbuf_off, Z_thread);
3749 
3750   add2reg(Rqueue_index, -wordSize); // Decrement index.
3751   z_stg(Rqueue_index, qidx_off, Z_thread);
3752 
3753   z_stg(Rcard_addr_x, 0, Rqueue_index, Rqueue_buf); // Store card.
3754   z_bru(filtered);
3755 
3756   bind(callRuntime);
3757 
3758   // TODO: do we need a frame? Introduced to be on the safe side.
3759   bool needs_frame = true;
3760   lgr_if_needed(Rcard_addr, Rcard_addr_x); // copy back asap. push_frame will destroy Z_R0_scratch!
3761 
3762   // VM call need frame to access(write) O register.
3763   if (needs_frame) {
3764     save_return_pc();
3765     push_frame_abi160(0); // Will use Z_R0 as tmp on old CPUs.
3766   }
3767 
3768   // Save the live input values.
3769   call_VM_leaf(CAST_FROM_FN_PTR(address, SharedRuntime::g1_wb_post), Rcard_addr, Z_thread);
3770 
3771   if (needs_frame) {
3772     pop_frame();
3773     restore_return_pc();
3774   }
3775 
3776   bind(filtered);
3777 
3778   BLOCK_COMMENT("} g1_write_barrier_post");
3779 }
3780 
3781 // Called from init_globals() after universe_init() and before interpreter_init()
3782 void g1_barrier_stubs_init() {
3783   // G1 barrier stubs currently only generated on SPARC
3784 }
3785 #endif // INCLUDE_ALL_GCS
3786 
3787 // Last_Java_sp must comply to the rules in frame_s390.hpp.
3788 void MacroAssembler::set_last_Java_frame(Register last_Java_sp, Register last_Java_pc, bool allow_relocation) {
3789   BLOCK_COMMENT("set_last_Java_frame {");
3790 
3791   // Always set last_Java_pc and flags first because once last_Java_sp
3792   // is visible has_last_Java_frame is true and users will look at the
3793   // rest of the fields. (Note: flags should always be zero before we
3794   // get here so doesn't need to be set.)
3795 
3796   // Verify that last_Java_pc was zeroed on return to Java.
3797   if (allow_relocation) {
3798     asm_assert_mem8_is_zero(in_bytes(JavaThread::last_Java_pc_offset()),
3799                             Z_thread,
3800                             "last_Java_pc not zeroed before leaving Java",
3801                             0x200);
3802   } else {
3803     asm_assert_mem8_is_zero_static(in_bytes(JavaThread::last_Java_pc_offset()),
3804                                    Z_thread,
3805                                    "last_Java_pc not zeroed before leaving Java",
3806                                    0x200);
3807   }
3808 
3809   // When returning from calling out from Java mode the frame anchor's
3810   // last_Java_pc will always be set to NULL. It is set here so that
3811   // if we are doing a call to native (not VM) that we capture the
3812   // known pc and don't have to rely on the native call having a
3813   // standard frame linkage where we can find the pc.
3814   if (last_Java_pc!=noreg) {
3815     z_stg(last_Java_pc, Address(Z_thread, JavaThread::last_Java_pc_offset()));
3816   }
3817 
3818   // This membar release is not required on z/Architecture, since the sequence of stores
3819   // in maintained. Nevertheless, we leave it in to document the required ordering.
3820   // The implementation of z_release() should be empty.
3821   // z_release();
3822 
3823   z_stg(last_Java_sp, Address(Z_thread, JavaThread::last_Java_sp_offset()));
3824   BLOCK_COMMENT("} set_last_Java_frame");
3825 }
3826 
3827 void MacroAssembler::reset_last_Java_frame(bool allow_relocation) {
3828   BLOCK_COMMENT("reset_last_Java_frame {");
3829 
3830   if (allow_relocation) {
3831     asm_assert_mem8_isnot_zero(in_bytes(JavaThread::last_Java_sp_offset()),
3832                                Z_thread,
3833                                "SP was not set, still zero",
3834                                0x202);
3835   } else {
3836     asm_assert_mem8_isnot_zero_static(in_bytes(JavaThread::last_Java_sp_offset()),
3837                                       Z_thread,
3838                                       "SP was not set, still zero",
3839                                       0x202);
3840   }
3841 
3842   // _last_Java_sp = 0
3843   // Clearing storage must be atomic here, so don't use clear_mem()!
3844   store_const(Address(Z_thread, JavaThread::last_Java_sp_offset()), 0);
3845 
3846   // _last_Java_pc = 0
3847   store_const(Address(Z_thread, JavaThread::last_Java_pc_offset()), 0);
3848 
3849   BLOCK_COMMENT("} reset_last_Java_frame");
3850   return;
3851 }
3852 
3853 void MacroAssembler::set_top_ijava_frame_at_SP_as_last_Java_frame(Register sp, Register tmp1, bool allow_relocation) {
3854   assert_different_registers(sp, tmp1);
3855 
3856   // We cannot trust that code generated by the C++ compiler saves R14
3857   // to z_abi_160.return_pc, because sometimes it spills R14 using stmg at
3858   // z_abi_160.gpr14 (e.g. InterpreterRuntime::_new()).
3859   // Therefore we load the PC into tmp1 and let set_last_Java_frame() save
3860   // it into the frame anchor.
3861   get_PC(tmp1);
3862   set_last_Java_frame(/*sp=*/sp, /*pc=*/tmp1, allow_relocation);
3863 }
3864 
3865 void MacroAssembler::set_thread_state(JavaThreadState new_state) {
3866   z_release();
3867 
3868   assert(Immediate::is_uimm16(_thread_max_state), "enum value out of range for instruction");
3869   assert(sizeof(JavaThreadState) == sizeof(int), "enum value must have base type int");
3870   store_const(Address(Z_thread, JavaThread::thread_state_offset()), new_state, Z_R0, false);
3871 }
3872 
3873 void MacroAssembler::get_vm_result(Register oop_result) {
3874   verify_thread();
3875 
3876   z_lg(oop_result, Address(Z_thread, JavaThread::vm_result_offset()));
3877   clear_mem(Address(Z_thread, JavaThread::vm_result_offset()), sizeof(void*));
3878 
3879   verify_oop(oop_result);
3880 }
3881 
3882 void MacroAssembler::get_vm_result_2(Register result) {
3883   verify_thread();
3884 
3885   z_lg(result, Address(Z_thread, JavaThread::vm_result_2_offset()));
3886   clear_mem(Address(Z_thread, JavaThread::vm_result_2_offset()), sizeof(void*));
3887 }
3888 
3889 // We require that C code which does not return a value in vm_result will
3890 // leave it undisturbed.
3891 void MacroAssembler::set_vm_result(Register oop_result) {
3892   z_stg(oop_result, Address(Z_thread, JavaThread::vm_result_offset()));
3893 }
3894 
3895 // Explicit null checks (used for method handle code).
3896 void MacroAssembler::null_check(Register reg, Register tmp, int64_t offset) {
3897   if (!ImplicitNullChecks) {
3898     NearLabel ok;
3899 
3900     compare64_and_branch(reg, (intptr_t) 0, Assembler::bcondNotEqual, ok);
3901 
3902     // We just put the address into reg if it was 0 (tmp==Z_R0 is allowed so we can't use it for the address).
3903     address exception_entry = Interpreter::throw_NullPointerException_entry();
3904     load_absolute_address(reg, exception_entry);
3905     z_br(reg);
3906 
3907     bind(ok);
3908   } else {
3909     if (needs_explicit_null_check((intptr_t)offset)) {
3910       // Provoke OS NULL exception if reg = NULL by
3911       // accessing M[reg] w/o changing any registers.
3912       z_lg(tmp, 0, reg);
3913     }
3914     // else
3915       // Nothing to do, (later) access of M[reg + offset]
3916       // will provoke OS NULL exception if reg = NULL.
3917   }
3918 }
3919 
3920 //-------------------------------------
3921 //  Compressed Klass Pointers
3922 //-------------------------------------
3923 
3924 // Klass oop manipulations if compressed.
3925 void MacroAssembler::encode_klass_not_null(Register dst, Register src) {
3926   Register current = (src != noreg) ? src : dst; // Klass is in dst if no src provided. (dst == src) also possible.
3927   address  base    = Universe::narrow_klass_base();
3928   int      shift   = Universe::narrow_klass_shift();
3929   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3930 
3931   BLOCK_COMMENT("cKlass encoder {");
3932 
3933 #ifdef ASSERT
3934   Label ok;
3935   z_tmll(current, KlassAlignmentInBytes-1); // Check alignment.
3936   z_brc(Assembler::bcondAllZero, ok);
3937   // The plain disassembler does not recognize illtrap. It instead displays
3938   // a 32-bit value. Issueing two illtraps assures the disassembler finds
3939   // the proper beginning of the next instruction.
3940   z_illtrap(0xee);
3941   z_illtrap(0xee);
3942   bind(ok);
3943 #endif
3944 
3945   if (base != NULL) {
3946     unsigned int base_h = ((unsigned long)base)>>32;
3947     unsigned int base_l = (unsigned int)((unsigned long)base);
3948     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3949       lgr_if_needed(dst, current);
3950       z_aih(dst, -((int)base_h));     // Base has no set bits in lower half.
3951     } else if ((base_h == 0) && (base_l != 0)) {
3952       lgr_if_needed(dst, current);
3953       z_agfi(dst, -(int)base_l);
3954     } else {
3955       load_const(Z_R0, base);
3956       lgr_if_needed(dst, current);
3957       z_sgr(dst, Z_R0);
3958     }
3959     current = dst;
3960   }
3961   if (shift != 0) {
3962     assert (LogKlassAlignmentInBytes == shift, "decode alg wrong");
3963     z_srlg(dst, current, shift);
3964     current = dst;
3965   }
3966   lgr_if_needed(dst, current); // Move may be required (if neither base nor shift != 0).
3967 
3968   BLOCK_COMMENT("} cKlass encoder");
3969 }
3970 
3971 // This function calculates the size of the code generated by
3972 //   decode_klass_not_null(register dst, Register src)
3973 // when (Universe::heap() != NULL). Hence, if the instructions
3974 // it generates change, then this method needs to be updated.
3975 int MacroAssembler::instr_size_for_decode_klass_not_null() {
3976   address  base    = Universe::narrow_klass_base();
3977   int shift_size   = Universe::narrow_klass_shift() == 0 ? 0 : 6; /* sllg */
3978   int addbase_size = 0;
3979   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
3980 
3981   if (base != NULL) {
3982     unsigned int base_h = ((unsigned long)base)>>32;
3983     unsigned int base_l = (unsigned int)((unsigned long)base);
3984     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
3985       addbase_size += 6; /* aih */
3986     } else if ((base_h == 0) && (base_l != 0)) {
3987       addbase_size += 6; /* algfi */
3988     } else {
3989       addbase_size += load_const_size();
3990       addbase_size += 4; /* algr */
3991     }
3992   }
3993 #ifdef ASSERT
3994   addbase_size += 10;
3995   addbase_size += 2; // Extra sigill.
3996 #endif
3997   return addbase_size + shift_size;
3998 }
3999 
4000 // !!! If the instructions that get generated here change
4001 //     then function instr_size_for_decode_klass_not_null()
4002 //     needs to get updated.
4003 // This variant of decode_klass_not_null() must generate predictable code!
4004 // The code must only depend on globally known parameters.
4005 void MacroAssembler::decode_klass_not_null(Register dst) {
4006   address  base    = Universe::narrow_klass_base();
4007   int      shift   = Universe::narrow_klass_shift();
4008   int      beg_off = offset();
4009   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
4010 
4011   BLOCK_COMMENT("cKlass decoder (const size) {");
4012 
4013   if (shift != 0) { // Shift required?
4014     z_sllg(dst, dst, shift);
4015   }
4016   if (base != NULL) {
4017     unsigned int base_h = ((unsigned long)base)>>32;
4018     unsigned int base_l = (unsigned int)((unsigned long)base);
4019     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
4020       z_aih(dst, base_h);     // Base has no set bits in lower half.
4021     } else if ((base_h == 0) && (base_l != 0)) {
4022       z_algfi(dst, base_l);   // Base has no set bits in upper half.
4023     } else {
4024       load_const(Z_R0, base); // Base has set bits everywhere.
4025       z_algr(dst, Z_R0);
4026     }
4027   }
4028 
4029 #ifdef ASSERT
4030   Label ok;
4031   z_tmll(dst, KlassAlignmentInBytes-1); // Check alignment.
4032   z_brc(Assembler::bcondAllZero, ok);
4033   // The plain disassembler does not recognize illtrap. It instead displays
4034   // a 32-bit value. Issueing two illtraps assures the disassembler finds
4035   // the proper beginning of the next instruction.
4036   z_illtrap(0xd1);
4037   z_illtrap(0xd1);
4038   bind(ok);
4039 #endif
4040   assert(offset() == beg_off + instr_size_for_decode_klass_not_null(), "Code gen mismatch.");
4041 
4042   BLOCK_COMMENT("} cKlass decoder (const size)");
4043 }
4044 
4045 // This variant of decode_klass_not_null() is for cases where
4046 //  1) the size of the generated instructions may vary
4047 //  2) the result is (potentially) stored in a register different from the source.
4048 void MacroAssembler::decode_klass_not_null(Register dst, Register src) {
4049   address base  = Universe::narrow_klass_base();
4050   int     shift = Universe::narrow_klass_shift();
4051   assert(UseCompressedClassPointers, "only for compressed klass ptrs");
4052 
4053   BLOCK_COMMENT("cKlass decoder {");
4054 
4055   if (src == noreg) src = dst;
4056 
4057   if (shift != 0) { // Shift or at least move required?
4058     z_sllg(dst, src, shift);
4059   } else {
4060     lgr_if_needed(dst, src);
4061   }
4062 
4063   if (base != NULL) {
4064     unsigned int base_h = ((unsigned long)base)>>32;
4065     unsigned int base_l = (unsigned int)((unsigned long)base);
4066     if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
4067       z_aih(dst, base_h);     // Base has not set bits in lower half.
4068     } else if ((base_h == 0) && (base_l != 0)) {
4069       z_algfi(dst, base_l);   // Base has no set bits in upper half.
4070     } else {
4071       load_const_optimized(Z_R0, base); // Base has set bits everywhere.
4072       z_algr(dst, Z_R0);
4073     }
4074   }
4075 
4076 #ifdef ASSERT
4077   Label ok;
4078   z_tmll(dst, KlassAlignmentInBytes-1); // Check alignment.
4079   z_brc(Assembler::bcondAllZero, ok);
4080   // The plain disassembler does not recognize illtrap. It instead displays
4081   // a 32-bit value. Issueing two illtraps assures the disassembler finds
4082   // the proper beginning of the next instruction.
4083   z_illtrap(0xd2);
4084   z_illtrap(0xd2);
4085   bind(ok);
4086 #endif
4087   BLOCK_COMMENT("} cKlass decoder");
4088 }
4089 
4090 void MacroAssembler::load_klass(Register klass, Address mem) {
4091   if (UseCompressedClassPointers) {
4092     z_llgf(klass, mem);
4093     // Attention: no null check here!
4094     decode_klass_not_null(klass);
4095   } else {
4096     z_lg(klass, mem);
4097   }
4098 }
4099 
4100 void MacroAssembler::load_klass(Register klass, Register src_oop) {
4101   if (UseCompressedClassPointers) {
4102     z_llgf(klass, oopDesc::klass_offset_in_bytes(), src_oop);
4103     // Attention: no null check here!
4104     decode_klass_not_null(klass);
4105   } else {
4106     z_lg(klass, oopDesc::klass_offset_in_bytes(), src_oop);
4107   }
4108 }
4109 
4110 void MacroAssembler::load_prototype_header(Register Rheader, Register Rsrc_oop) {
4111   assert_different_registers(Rheader, Rsrc_oop);
4112   load_klass(Rheader, Rsrc_oop);
4113   z_lg(Rheader, Address(Rheader, Klass::prototype_header_offset()));
4114 }
4115 
4116 void MacroAssembler::store_klass(Register klass, Register dst_oop, Register ck) {
4117   if (UseCompressedClassPointers) {
4118     assert_different_registers(dst_oop, klass, Z_R0);
4119     if (ck == noreg) ck = klass;
4120     encode_klass_not_null(ck, klass);
4121     z_st(ck, Address(dst_oop, oopDesc::klass_offset_in_bytes()));
4122   } else {
4123     z_stg(klass, Address(dst_oop, oopDesc::klass_offset_in_bytes()));
4124   }
4125 }
4126 
4127 void MacroAssembler::store_klass_gap(Register s, Register d) {
4128   if (UseCompressedClassPointers) {
4129     assert(s != d, "not enough registers");
4130     // Support s = noreg.
4131     if (s != noreg) {
4132       z_st(s, Address(d, oopDesc::klass_gap_offset_in_bytes()));
4133     } else {
4134       z_mvhi(Address(d, oopDesc::klass_gap_offset_in_bytes()), 0);
4135     }
4136   }
4137 }
4138 
4139 // Compare klass ptr in memory against klass ptr in register.
4140 //
4141 // Rop1            - klass in register, always uncompressed.
4142 // disp            - Offset of klass in memory, compressed/uncompressed, depending on runtime flag.
4143 // Rbase           - Base address of cKlass in memory.
4144 // maybeNULL       - True if Rop1 possibly is a NULL.
4145 void MacroAssembler::compare_klass_ptr(Register Rop1, int64_t disp, Register Rbase, bool maybeNULL) {
4146 
4147   BLOCK_COMMENT("compare klass ptr {");
4148 
4149   if (UseCompressedClassPointers) {
4150     const int shift = Universe::narrow_klass_shift();
4151     address   base  = Universe::narrow_klass_base();
4152 
4153     assert((shift == 0) || (shift == LogKlassAlignmentInBytes), "cKlass encoder detected bad shift");
4154     assert_different_registers(Rop1, Z_R0);
4155     assert_different_registers(Rop1, Rbase, Z_R1);
4156 
4157     // First encode register oop and then compare with cOop in memory.
4158     // This sequence saves an unnecessary cOop load and decode.
4159     if (base == NULL) {
4160       if (shift == 0) {
4161         z_cl(Rop1, disp, Rbase);     // Unscaled
4162       } else {
4163         z_srlg(Z_R0, Rop1, shift);   // ZeroBased
4164         z_cl(Z_R0, disp, Rbase);
4165       }
4166     } else {                         // HeapBased
4167 #ifdef ASSERT
4168       bool     used_R0 = true;
4169       bool     used_R1 = true;
4170 #endif
4171       Register current = Rop1;
4172       Label    done;
4173 
4174       if (maybeNULL) {       // NULL ptr must be preserved!
4175         z_ltgr(Z_R0, current);
4176         z_bre(done);
4177         current = Z_R0;
4178       }
4179 
4180       unsigned int base_h = ((unsigned long)base)>>32;
4181       unsigned int base_l = (unsigned int)((unsigned long)base);
4182       if ((base_h != 0) && (base_l == 0) && VM_Version::has_HighWordInstr()) {
4183         lgr_if_needed(Z_R0, current);
4184         z_aih(Z_R0, -((int)base_h));     // Base has no set bits in lower half.
4185       } else if ((base_h == 0) && (base_l != 0)) {
4186         lgr_if_needed(Z_R0, current);
4187         z_agfi(Z_R0, -(int)base_l);
4188       } else {
4189         int pow2_offset = get_oop_base_complement(Z_R1, ((uint64_t)(intptr_t)base));
4190         add2reg_with_index(Z_R0, pow2_offset, Z_R1, Rop1); // Subtract base by adding complement.
4191       }
4192 
4193       if (shift != 0) {
4194         z_srlg(Z_R0, Z_R0, shift);
4195       }
4196       bind(done);
4197       z_cl(Z_R0, disp, Rbase);
4198 #ifdef ASSERT
4199       if (used_R0) preset_reg(Z_R0, 0xb05bUL, 2);
4200       if (used_R1) preset_reg(Z_R1, 0xb06bUL, 2);
4201 #endif
4202     }
4203   } else {
4204     z_clg(Rop1, disp, Z_R0, Rbase);
4205   }
4206   BLOCK_COMMENT("} compare klass ptr");
4207 }
4208 
4209 //---------------------------
4210 //  Compressed oops
4211 //---------------------------
4212 
4213 void MacroAssembler::encode_heap_oop(Register oop) {
4214   oop_encoder(oop, oop, true /*maybe null*/);
4215 }
4216 
4217 void MacroAssembler::encode_heap_oop_not_null(Register oop) {
4218   oop_encoder(oop, oop, false /*not null*/);
4219 }
4220 
4221 // Called with something derived from the oop base. e.g. oop_base>>3.
4222 int MacroAssembler::get_oop_base_pow2_offset(uint64_t oop_base) {
4223   unsigned int oop_base_ll = ((unsigned int)(oop_base >>  0)) & 0xffff;
4224   unsigned int oop_base_lh = ((unsigned int)(oop_base >> 16)) & 0xffff;
4225   unsigned int oop_base_hl = ((unsigned int)(oop_base >> 32)) & 0xffff;
4226   unsigned int oop_base_hh = ((unsigned int)(oop_base >> 48)) & 0xffff;
4227   unsigned int n_notzero_parts = (oop_base_ll == 0 ? 0:1)
4228                                + (oop_base_lh == 0 ? 0:1)
4229                                + (oop_base_hl == 0 ? 0:1)
4230                                + (oop_base_hh == 0 ? 0:1);
4231 
4232   assert(oop_base != 0, "This is for HeapBased cOops only");
4233 
4234   if (n_notzero_parts != 1) { //  Check if oop_base is just a few pages shy of a power of 2.
4235     uint64_t pow2_offset = 0x10000 - oop_base_ll;
4236     if (pow2_offset < 0x8000) {  // This might not be necessary.
4237       uint64_t oop_base2 = oop_base + pow2_offset;
4238 
4239       oop_base_ll = ((unsigned int)(oop_base2 >>  0)) & 0xffff;
4240       oop_base_lh = ((unsigned int)(oop_base2 >> 16)) & 0xffff;
4241       oop_base_hl = ((unsigned int)(oop_base2 >> 32)) & 0xffff;
4242       oop_base_hh = ((unsigned int)(oop_base2 >> 48)) & 0xffff;
4243       n_notzero_parts = (oop_base_ll == 0 ? 0:1) +
4244                         (oop_base_lh == 0 ? 0:1) +
4245                         (oop_base_hl == 0 ? 0:1) +
4246                         (oop_base_hh == 0 ? 0:1);
4247       if (n_notzero_parts == 1) {
4248         assert(-(int64_t)pow2_offset != (int64_t)-1, "We use -1 to signal uninitialized base register");
4249         return -pow2_offset;
4250       }
4251     }
4252   }
4253   return 0;
4254 }
4255 
4256 // If base address is offset from a straight power of two by just a few pages,
4257 // return this offset to the caller for a possible later composite add.
4258 // TODO/FIX: will only work correctly for 4k pages.
4259 int MacroAssembler::get_oop_base(Register Rbase, uint64_t oop_base) {
4260   int pow2_offset = get_oop_base_pow2_offset(oop_base);
4261 
4262   load_const_optimized(Rbase, oop_base - pow2_offset); // Best job possible.
4263 
4264   return pow2_offset;
4265 }
4266 
4267 int MacroAssembler::get_oop_base_complement(Register Rbase, uint64_t oop_base) {
4268   int offset = get_oop_base(Rbase, oop_base);
4269   z_lcgr(Rbase, Rbase);
4270   return -offset;
4271 }
4272 
4273 // Compare compressed oop in memory against oop in register.
4274 // Rop1            - Oop in register.
4275 // disp            - Offset of cOop in memory.
4276 // Rbase           - Base address of cOop in memory.
4277 // maybeNULL       - True if Rop1 possibly is a NULL.
4278 // maybeNULLtarget - Branch target for Rop1 == NULL, if flow control shall NOT continue with compare instruction.
4279 void MacroAssembler::compare_heap_oop(Register Rop1, Address mem, bool maybeNULL) {
4280   Register Rbase  = mem.baseOrR0();
4281   Register Rindex = mem.indexOrR0();
4282   int64_t  disp   = mem.disp();
4283 
4284   const int shift = Universe::narrow_oop_shift();
4285   address   base  = Universe::narrow_oop_base();
4286 
4287   assert(UseCompressedOops, "must be on to call this method");
4288   assert(Universe::heap() != NULL, "java heap must be initialized to call this method");
4289   assert((shift == 0) || (shift == LogMinObjAlignmentInBytes), "cOop encoder detected bad shift");
4290   assert_different_registers(Rop1, Z_R0);
4291   assert_different_registers(Rop1, Rbase, Z_R1);
4292   assert_different_registers(Rop1, Rindex, Z_R1);
4293 
4294   BLOCK_COMMENT("compare heap oop {");
4295 
4296   // First encode register oop and then compare with cOop in memory.
4297   // This sequence saves an unnecessary cOop load and decode.
4298   if (base == NULL) {
4299     if (shift == 0) {
4300       z_cl(Rop1, disp, Rindex, Rbase);  // Unscaled
4301     } else {
4302       z_srlg(Z_R0, Rop1, shift);        // ZeroBased
4303       z_cl(Z_R0, disp, Rindex, Rbase);
4304     }
4305   } else {                              // HeapBased
4306 #ifdef ASSERT
4307     bool  used_R0 = true;
4308     bool  used_R1 = true;
4309 #endif
4310     Label done;
4311     int   pow2_offset = get_oop_base_complement(Z_R1, ((uint64_t)(intptr_t)base));
4312 
4313     if (maybeNULL) {       // NULL ptr must be preserved!
4314       z_ltgr(Z_R0, Rop1);
4315       z_bre(done);
4316     }
4317 
4318     add2reg_with_index(Z_R0, pow2_offset, Z_R1, Rop1);
4319     z_srlg(Z_R0, Z_R0, shift);
4320 
4321     bind(done);
4322     z_cl(Z_R0, disp, Rindex, Rbase);
4323 #ifdef ASSERT
4324     if (used_R0) preset_reg(Z_R0, 0xb05bUL, 2);
4325     if (used_R1) preset_reg(Z_R1, 0xb06bUL, 2);
4326 #endif
4327   }
4328   BLOCK_COMMENT("} compare heap oop");
4329 }
4330 
4331 // Load heap oop and decompress, if necessary.
4332 void  MacroAssembler::load_heap_oop(Register dest, const Address &a) {
4333   if (UseCompressedOops) {
4334     z_llgf(dest, a.disp(), a.indexOrR0(), a.baseOrR0());
4335     oop_decoder(dest, dest, true);
4336   } else {
4337     z_lg(dest, a.disp(), a.indexOrR0(), a.baseOrR0());
4338   }
4339 }
4340 
4341 // Load heap oop and decompress, if necessary.
4342 void MacroAssembler::load_heap_oop(Register dest, int64_t disp, Register base) {
4343   if (UseCompressedOops) {
4344     z_llgf(dest, disp, base);
4345     oop_decoder(dest, dest, true);
4346   } else {
4347     z_lg(dest, disp, base);
4348   }
4349 }
4350 
4351 // Load heap oop and decompress, if necessary.
4352 void MacroAssembler::load_heap_oop_not_null(Register dest, int64_t disp, Register base) {
4353   if (UseCompressedOops) {
4354     z_llgf(dest, disp, base);
4355     oop_decoder(dest, dest, false);
4356   } else {
4357     z_lg(dest, disp, base);
4358   }
4359 }
4360 
4361 // Compress, if necessary, and store oop to heap.
4362 void MacroAssembler::store_heap_oop(Register Roop, RegisterOrConstant offset, Register base) {
4363   Register Ridx = offset.is_register() ? offset.register_or_noreg() : Z_R0;
4364   if (UseCompressedOops) {
4365     assert_different_registers(Roop, offset.register_or_noreg(), base);
4366     encode_heap_oop(Roop);
4367     z_st(Roop, offset.constant_or_zero(), Ridx, base);
4368   } else {
4369     z_stg(Roop, offset.constant_or_zero(), Ridx, base);
4370   }
4371 }
4372 
4373 // Compress, if necessary, and store oop to heap. Oop is guaranteed to be not NULL.
4374 void MacroAssembler::store_heap_oop_not_null(Register Roop, RegisterOrConstant offset, Register base) {
4375   Register Ridx = offset.is_register() ? offset.register_or_noreg() : Z_R0;
4376   if (UseCompressedOops) {
4377     assert_different_registers(Roop, offset.register_or_noreg(), base);
4378     encode_heap_oop_not_null(Roop);
4379     z_st(Roop, offset.constant_or_zero(), Ridx, base);
4380   } else {
4381     z_stg(Roop, offset.constant_or_zero(), Ridx, base);
4382   }
4383 }
4384 
4385 // Store NULL oop to heap.
4386 void MacroAssembler::store_heap_oop_null(Register zero, RegisterOrConstant offset, Register base) {
4387   Register Ridx = offset.is_register() ? offset.register_or_noreg() : Z_R0;
4388   if (UseCompressedOops) {
4389     z_st(zero, offset.constant_or_zero(), Ridx, base);
4390   } else {
4391     z_stg(zero, offset.constant_or_zero(), Ridx, base);
4392   }
4393 }
4394 
4395 //-------------------------------------------------
4396 // Encode compressed oop. Generally usable encoder.
4397 //-------------------------------------------------
4398 // Rsrc - contains regular oop on entry. It remains unchanged.
4399 // Rdst - contains compressed oop on exit.
4400 // Rdst and Rsrc may indicate same register, in which case Rsrc does not remain unchanged.
4401 //
4402 // Rdst must not indicate scratch register Z_R1 (Z_R1_scratch) for functionality.
4403 // Rdst should not indicate scratch register Z_R0 (Z_R0_scratch) for performance.
4404 //
4405 // only32bitValid is set, if later code only uses the lower 32 bits. In this
4406 // case we must not fix the upper 32 bits.
4407 void MacroAssembler::oop_encoder(Register Rdst, Register Rsrc, bool maybeNULL,
4408                                  Register Rbase, int pow2_offset, bool only32bitValid) {
4409 
4410   const address oop_base  = Universe::narrow_oop_base();
4411   const int     oop_shift = Universe::narrow_oop_shift();
4412   const bool    disjoint  = Universe::narrow_oop_base_disjoint();
4413 
4414   assert(UseCompressedOops, "must be on to call this method");
4415   assert(Universe::heap() != NULL, "java heap must be initialized to call this encoder");
4416   assert((oop_shift == 0) || (oop_shift == LogMinObjAlignmentInBytes), "cOop encoder detected bad shift");
4417 
4418   if (disjoint || (oop_base == NULL)) {
4419     BLOCK_COMMENT("cOop encoder zeroBase {");
4420     if (oop_shift == 0) {
4421       if (oop_base != NULL && !only32bitValid) {
4422         z_llgfr(Rdst, Rsrc); // Clear upper bits in case the register will be decoded again.
4423       } else {
4424         lgr_if_needed(Rdst, Rsrc);
4425       }
4426     } else {
4427       z_srlg(Rdst, Rsrc, oop_shift);
4428       if (oop_base != NULL && !only32bitValid) {
4429         z_llgfr(Rdst, Rdst); // Clear upper bits in case the register will be decoded again.
4430       }
4431     }
4432     BLOCK_COMMENT("} cOop encoder zeroBase");
4433     return;
4434   }
4435 
4436   bool used_R0 = false;
4437   bool used_R1 = false;
4438 
4439   BLOCK_COMMENT("cOop encoder general {");
4440   assert_different_registers(Rdst, Z_R1);
4441   assert_different_registers(Rsrc, Rbase);
4442   if (maybeNULL) {
4443     Label done;
4444     // We reorder shifting and subtracting, so that we can compare
4445     // and shift in parallel:
4446     //
4447     // cycle 0:  potential LoadN, base = <const>
4448     // cycle 1:  base = !base     dst = src >> 3,    cmp cr = (src != 0)
4449     // cycle 2:  if (cr) br,      dst = dst + base + offset
4450 
4451     // Get oop_base components.
4452     if (pow2_offset == -1) {
4453       if (Rdst == Rbase) {
4454         if (Rdst == Z_R1 || Rsrc == Z_R1) {
4455           Rbase = Z_R0;
4456           used_R0 = true;
4457         } else {
4458           Rdst = Z_R1;
4459           used_R1 = true;
4460         }
4461       }
4462       if (Rbase == Z_R1) {
4463         used_R1 = true;
4464       }
4465       pow2_offset = get_oop_base_complement(Rbase, ((uint64_t)(intptr_t)oop_base) >> oop_shift);
4466     }
4467     assert_different_registers(Rdst, Rbase);
4468 
4469     // Check for NULL oop (must be left alone) and shift.
4470     if (oop_shift != 0) {  // Shift out alignment bits
4471       if (((intptr_t)oop_base&0xc000000000000000L) == 0L) { // We are sure: no single address will have the leftmost bit set.
4472         z_srag(Rdst, Rsrc, oop_shift);  // Arithmetic shift sets the condition code.
4473       } else {
4474         z_srlg(Rdst, Rsrc, oop_shift);
4475         z_ltgr(Rsrc, Rsrc);  // This is the recommended way of testing for zero.
4476         // This probably is faster, as it does not write a register. No!
4477         // z_cghi(Rsrc, 0);
4478       }
4479     } else {
4480       z_ltgr(Rdst, Rsrc);   // Move NULL to result register.
4481     }
4482     z_bre(done);
4483 
4484     // Subtract oop_base components.
4485     if ((Rdst == Z_R0) || (Rbase == Z_R0)) {
4486       z_algr(Rdst, Rbase);
4487       if (pow2_offset != 0) { add2reg(Rdst, pow2_offset); }
4488     } else {
4489       add2reg_with_index(Rdst, pow2_offset, Rbase, Rdst);
4490     }
4491     if (!only32bitValid) {
4492       z_llgfr(Rdst, Rdst); // Clear upper bits in case the register will be decoded again.
4493     }
4494     bind(done);
4495 
4496   } else {  // not null
4497     // Get oop_base components.
4498     if (pow2_offset == -1) {
4499       pow2_offset = get_oop_base_complement(Rbase, (uint64_t)(intptr_t)oop_base);
4500     }
4501 
4502     // Subtract oop_base components and shift.
4503     if (Rdst == Z_R0 || Rsrc == Z_R0 || Rbase == Z_R0) {
4504       // Don't use lay instruction.
4505       if (Rdst == Rsrc) {
4506         z_algr(Rdst, Rbase);
4507       } else {
4508         lgr_if_needed(Rdst, Rbase);
4509         z_algr(Rdst, Rsrc);
4510       }
4511       if (pow2_offset != 0) add2reg(Rdst, pow2_offset);
4512     } else {
4513       add2reg_with_index(Rdst, pow2_offset, Rbase, Rsrc);
4514     }
4515     if (oop_shift != 0) {   // Shift out alignment bits.
4516       z_srlg(Rdst, Rdst, oop_shift);
4517     }
4518     if (!only32bitValid) {
4519       z_llgfr(Rdst, Rdst); // Clear upper bits in case the register will be decoded again.
4520     }
4521   }
4522 #ifdef ASSERT
4523   if (used_R0 && Rdst != Z_R0 && Rsrc != Z_R0) { preset_reg(Z_R0, 0xb01bUL, 2); }
4524   if (used_R1 && Rdst != Z_R1 && Rsrc != Z_R1) { preset_reg(Z_R1, 0xb02bUL, 2); }
4525 #endif
4526   BLOCK_COMMENT("} cOop encoder general");
4527 }
4528 
4529 //-------------------------------------------------
4530 // decode compressed oop. Generally usable decoder.
4531 //-------------------------------------------------
4532 // Rsrc - contains compressed oop on entry.
4533 // Rdst - contains regular oop on exit.
4534 // Rdst and Rsrc may indicate same register.
4535 // Rdst must not be the same register as Rbase, if Rbase was preloaded (before call).
4536 // Rdst can be the same register as Rbase. Then, either Z_R0 or Z_R1 must be available as scratch.
4537 // Rbase - register to use for the base
4538 // pow2_offset - offset of base to nice value. If -1, base must be loaded.
4539 // For performance, it is good to
4540 //  - avoid Z_R0 for any of the argument registers.
4541 //  - keep Rdst and Rsrc distinct from Rbase. Rdst == Rsrc is ok for performance.
4542 //  - avoid Z_R1 for Rdst if Rdst == Rbase.
4543 void MacroAssembler::oop_decoder(Register Rdst, Register Rsrc, bool maybeNULL, Register Rbase, int pow2_offset) {
4544 
4545   const address oop_base  = Universe::narrow_oop_base();
4546   const int     oop_shift = Universe::narrow_oop_shift();
4547   const bool    disjoint  = Universe::narrow_oop_base_disjoint();
4548 
4549   assert(UseCompressedOops, "must be on to call this method");
4550   assert(Universe::heap() != NULL, "java heap must be initialized to call this decoder");
4551   assert((oop_shift == 0) || (oop_shift == LogMinObjAlignmentInBytes),
4552          "cOop encoder detected bad shift");
4553 
4554   // cOops are always loaded zero-extended from memory. No explicit zero-extension necessary.
4555 
4556   if (oop_base != NULL) {
4557     unsigned int oop_base_hl = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 32)) & 0xffff;
4558     unsigned int oop_base_hh = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 48)) & 0xffff;
4559     unsigned int oop_base_hf = ((unsigned int)((uint64_t)(intptr_t)oop_base >> 32)) & 0xFFFFffff;
4560     if (disjoint && (oop_base_hl == 0 || oop_base_hh == 0)) {
4561       BLOCK_COMMENT("cOop decoder disjointBase {");
4562       // We do not need to load the base. Instead, we can install the upper bits
4563       // with an OR instead of an ADD.
4564       Label done;
4565 
4566       // Rsrc contains a narrow oop. Thus we are sure the leftmost <oop_shift> bits will never be set.
4567       if (maybeNULL) {  // NULL ptr must be preserved!
4568         z_slag(Rdst, Rsrc, oop_shift);  // Arithmetic shift sets the condition code.
4569         z_bre(done);
4570       } else {
4571         z_sllg(Rdst, Rsrc, oop_shift);  // Logical shift leaves condition code alone.
4572       }
4573       if ((oop_base_hl != 0) && (oop_base_hh != 0)) {
4574         z_oihf(Rdst, oop_base_hf);
4575       } else if (oop_base_hl != 0) {
4576         z_oihl(Rdst, oop_base_hl);
4577       } else {
4578         assert(oop_base_hh != 0, "not heapbased mode");
4579         z_oihh(Rdst, oop_base_hh);
4580       }
4581       bind(done);
4582       BLOCK_COMMENT("} cOop decoder disjointBase");
4583     } else {
4584       BLOCK_COMMENT("cOop decoder general {");
4585       // There are three decode steps:
4586       //   scale oop offset (shift left)
4587       //   get base (in reg) and pow2_offset (constant)
4588       //   add base, pow2_offset, and oop offset
4589       // The following register overlap situations may exist:
4590       // Rdst == Rsrc,  Rbase any other
4591       //   not a problem. Scaling in-place leaves Rbase undisturbed.
4592       //   Loading Rbase does not impact the scaled offset.
4593       // Rdst == Rbase, Rsrc  any other
4594       //   scaling would destroy a possibly preloaded Rbase. Loading Rbase
4595       //   would destroy the scaled offset.
4596       //   Remedy: use Rdst_tmp if Rbase has been preloaded.
4597       //           use Rbase_tmp if base has to be loaded.
4598       // Rsrc == Rbase, Rdst  any other
4599       //   Only possible without preloaded Rbase.
4600       //   Loading Rbase does not destroy compressed oop because it was scaled into Rdst before.
4601       // Rsrc == Rbase, Rdst == Rbase
4602       //   Only possible without preloaded Rbase.
4603       //   Loading Rbase would destroy compressed oop. Scaling in-place is ok.
4604       //   Remedy: use Rbase_tmp.
4605       //
4606       Label    done;
4607       Register Rdst_tmp       = Rdst;
4608       Register Rbase_tmp      = Rbase;
4609       bool     used_R0        = false;
4610       bool     used_R1        = false;
4611       bool     base_preloaded = pow2_offset >= 0;
4612       guarantee(!(base_preloaded && (Rsrc == Rbase)), "Register clash, check caller");
4613       assert(oop_shift != 0, "room for optimization");
4614 
4615       // Check if we need to use scratch registers.
4616       if (Rdst == Rbase) {
4617         assert(!(((Rdst == Z_R0) && (Rsrc == Z_R1)) || ((Rdst == Z_R1) && (Rsrc == Z_R0))), "need a scratch reg");
4618         if (Rdst != Rsrc) {
4619           if (base_preloaded) { Rdst_tmp  = (Rdst == Z_R1) ? Z_R0 : Z_R1; }
4620           else                { Rbase_tmp = (Rdst == Z_R1) ? Z_R0 : Z_R1; }
4621         } else {
4622           Rbase_tmp = (Rdst == Z_R1) ? Z_R0 : Z_R1;
4623         }
4624       }
4625       if (base_preloaded) lgr_if_needed(Rbase_tmp, Rbase);
4626 
4627       // Scale oop and check for NULL.
4628       // Rsrc contains a narrow oop. Thus we are sure the leftmost <oop_shift> bits will never be set.
4629       if (maybeNULL) {  // NULL ptr must be preserved!
4630         z_slag(Rdst_tmp, Rsrc, oop_shift);  // Arithmetic shift sets the condition code.
4631         z_bre(done);
4632       } else {
4633         z_sllg(Rdst_tmp, Rsrc, oop_shift);  // Logical shift leaves condition code alone.
4634       }
4635 
4636       // Get oop_base components.
4637       if (!base_preloaded) {
4638         pow2_offset = get_oop_base(Rbase_tmp, (uint64_t)(intptr_t)oop_base);
4639       }
4640 
4641       // Add up all components.
4642       if ((Rbase_tmp == Z_R0) || (Rdst_tmp == Z_R0)) {
4643         z_algr(Rdst_tmp, Rbase_tmp);
4644         if (pow2_offset != 0) { add2reg(Rdst_tmp, pow2_offset); }
4645       } else {
4646         add2reg_with_index(Rdst_tmp, pow2_offset, Rbase_tmp, Rdst_tmp);
4647       }
4648 
4649       bind(done);
4650       lgr_if_needed(Rdst, Rdst_tmp);
4651 #ifdef ASSERT
4652       if (used_R0 && Rdst != Z_R0 && Rsrc != Z_R0) { preset_reg(Z_R0, 0xb03bUL, 2); }
4653       if (used_R1 && Rdst != Z_R1 && Rsrc != Z_R1) { preset_reg(Z_R1, 0xb04bUL, 2); }
4654 #endif
4655       BLOCK_COMMENT("} cOop decoder general");
4656     }
4657   } else {
4658     BLOCK_COMMENT("cOop decoder zeroBase {");
4659     if (oop_shift == 0) {
4660       lgr_if_needed(Rdst, Rsrc);
4661     } else {
4662       z_sllg(Rdst, Rsrc, oop_shift);
4663     }
4664     BLOCK_COMMENT("} cOop decoder zeroBase");
4665   }
4666 }
4667 
4668 // ((OopHandle)result).resolve();
4669 void MacroAssembler::resolve_oop_handle(Register result) {
4670   // OopHandle::resolve is an indirection.
4671   z_lg(result, 0, result);
4672 }
4673 
4674 void MacroAssembler::load_mirror(Register mirror, Register method) {
4675   mem2reg_opt(mirror, Address(method, Method::const_offset()));
4676   mem2reg_opt(mirror, Address(mirror, ConstMethod::constants_offset()));
4677   mem2reg_opt(mirror, Address(mirror, ConstantPool::pool_holder_offset_in_bytes()));
4678   mem2reg_opt(mirror, Address(mirror, Klass::java_mirror_offset()));
4679   resolve_oop_handle(mirror);
4680 }
4681 
4682 //---------------------------------------------------------------
4683 //---  Operations on arrays.
4684 //---------------------------------------------------------------
4685 
4686 // Compiler ensures base is doubleword aligned and cnt is #doublewords.
4687 // Emitter does not KILL cnt and base arguments, since they need to be copied to
4688 // work registers anyway.
4689 // Actually, only r0, r1, and r5 are killed.
4690 unsigned int MacroAssembler::Clear_Array(Register cnt_arg, Register base_pointer_arg, Register src_addr, Register src_len) {
4691   // Src_addr is evenReg.
4692   // Src_len is odd_Reg.
4693 
4694   int      block_start = offset();
4695   Register tmp_reg  = src_len; // Holds target instr addr for EX.
4696   Register dst_len  = Z_R1;    // Holds dst len  for MVCLE.
4697   Register dst_addr = Z_R0;    // Holds dst addr for MVCLE.
4698 
4699   Label doXC, doMVCLE, done;
4700 
4701   BLOCK_COMMENT("Clear_Array {");
4702 
4703   // Check for zero len and convert to long.
4704   z_ltgfr(src_len, cnt_arg);      // Remember casted value for doSTG case.
4705   z_bre(done);                    // Nothing to do if len == 0.
4706 
4707   // Prefetch data to be cleared.
4708   if (VM_Version::has_Prefetch()) {
4709     z_pfd(0x02,   0, Z_R0, base_pointer_arg);
4710     z_pfd(0x02, 256, Z_R0, base_pointer_arg);
4711   }
4712 
4713   z_sllg(dst_len, src_len, 3);    // #bytes to clear.
4714   z_cghi(src_len, 32);            // Check for len <= 256 bytes (<=32 DW).
4715   z_brnh(doXC);                   // If so, use executed XC to clear.
4716 
4717   // MVCLE: initialize long arrays (general case).
4718   bind(doMVCLE);
4719   z_lgr(dst_addr, base_pointer_arg);
4720   clear_reg(src_len, true, false); // Src len of MVCLE is zero.
4721 
4722   MacroAssembler::move_long_ext(dst_addr, src_addr, 0);
4723   z_bru(done);
4724 
4725   // XC: initialize short arrays.
4726   Label XC_template; // Instr template, never exec directly!
4727     bind(XC_template);
4728     z_xc(0,0,base_pointer_arg,0,base_pointer_arg);
4729 
4730   bind(doXC);
4731     add2reg(dst_len, -1);             // Get #bytes-1 for EXECUTE.
4732     if (VM_Version::has_ExecuteExtensions()) {
4733       z_exrl(dst_len, XC_template);   // Execute XC with var. len.
4734     } else {
4735       z_larl(tmp_reg, XC_template);
4736       z_ex(dst_len,0,Z_R0,tmp_reg);   // Execute XC with var. len.
4737     }
4738     // z_bru(done);      // fallthru
4739 
4740   bind(done);
4741 
4742   BLOCK_COMMENT("} Clear_Array");
4743 
4744   int block_end = offset();
4745   return block_end - block_start;
4746 }
4747 
4748 // Compiler ensures base is doubleword aligned and cnt is count of doublewords.
4749 // Emitter does not KILL any arguments nor work registers.
4750 // Emitter generates up to 16 XC instructions, depending on the array length.
4751 unsigned int MacroAssembler::Clear_Array_Const(long cnt, Register base) {
4752   int  block_start    = offset();
4753   int  off;
4754   int  lineSize_Bytes = AllocatePrefetchStepSize;
4755   int  lineSize_DW    = AllocatePrefetchStepSize>>LogBytesPerWord;
4756   bool doPrefetch     = VM_Version::has_Prefetch();
4757   int  XC_maxlen      = 256;
4758   int  numXCInstr     = cnt > 0 ? (cnt*BytesPerWord-1)/XC_maxlen+1 : 0;
4759 
4760   BLOCK_COMMENT("Clear_Array_Const {");
4761   assert(cnt*BytesPerWord <= 4096, "ClearArrayConst can handle 4k only");
4762 
4763   // Do less prefetching for very short arrays.
4764   if (numXCInstr > 0) {
4765     // Prefetch only some cache lines, then begin clearing.
4766     if (doPrefetch) {
4767       if (cnt*BytesPerWord <= lineSize_Bytes/4) {  // If less than 1/4 of a cache line to clear,
4768         z_pfd(0x02, 0, Z_R0, base);                // prefetch just the first cache line.
4769       } else {
4770         assert(XC_maxlen == lineSize_Bytes, "ClearArrayConst needs 256B cache lines");
4771         for (off = 0; (off < AllocatePrefetchLines) && (off <= numXCInstr); off ++) {
4772           z_pfd(0x02, off*lineSize_Bytes, Z_R0, base);
4773         }
4774       }
4775     }
4776 
4777     for (off=0; off<(numXCInstr-1); off++) {
4778       z_xc(off*XC_maxlen, XC_maxlen-1, base, off*XC_maxlen, base);
4779 
4780       // Prefetch some cache lines in advance.
4781       if (doPrefetch && (off <= numXCInstr-AllocatePrefetchLines)) {
4782         z_pfd(0x02, (off+AllocatePrefetchLines)*lineSize_Bytes, Z_R0, base);
4783       }
4784     }
4785     if (off*XC_maxlen < cnt*BytesPerWord) {
4786       z_xc(off*XC_maxlen, (cnt*BytesPerWord-off*XC_maxlen)-1, base, off*XC_maxlen, base);
4787     }
4788   }
4789   BLOCK_COMMENT("} Clear_Array_Const");
4790 
4791   int block_end = offset();
4792   return block_end - block_start;
4793 }
4794 
4795 // Compiler ensures base is doubleword aligned and cnt is #doublewords.
4796 // Emitter does not KILL cnt and base arguments, since they need to be copied to
4797 // work registers anyway.
4798 // Actually, only r0, r1, r4, and r5 (which are work registers) are killed.
4799 //
4800 // For very large arrays, exploit MVCLE H/W support.
4801 // MVCLE instruction automatically exploits H/W-optimized page mover.
4802 // - Bytes up to next page boundary are cleared with a series of XC to self.
4803 // - All full pages are cleared with the page mover H/W assist.
4804 // - Remaining bytes are again cleared by a series of XC to self.
4805 //
4806 unsigned int MacroAssembler::Clear_Array_Const_Big(long cnt, Register base_pointer_arg, Register src_addr, Register src_len) {
4807   // Src_addr is evenReg.
4808   // Src_len is odd_Reg.
4809 
4810   int      block_start = offset();
4811   Register dst_len  = Z_R1;      // Holds dst len  for MVCLE.
4812   Register dst_addr = Z_R0;      // Holds dst addr for MVCLE.
4813 
4814   BLOCK_COMMENT("Clear_Array_Const_Big {");
4815 
4816   // Get len to clear.
4817   load_const_optimized(dst_len, (long)cnt*8L);  // in Bytes = #DW*8
4818 
4819   // Prepare other args to MVCLE.
4820   z_lgr(dst_addr, base_pointer_arg);
4821   // Indicate unused result.
4822   (void) clear_reg(src_len, true, false);  // Src len of MVCLE is zero.
4823 
4824   // Clear.
4825   MacroAssembler::move_long_ext(dst_addr, src_addr, 0);
4826   BLOCK_COMMENT("} Clear_Array_Const_Big");
4827 
4828   int block_end = offset();
4829   return block_end - block_start;
4830 }
4831 
4832 // Allocator.
4833 unsigned int MacroAssembler::CopyRawMemory_AlignedDisjoint(Register src_reg, Register dst_reg,
4834                                                            Register cnt_reg,
4835                                                            Register tmp1_reg, Register tmp2_reg) {
4836   // Tmp1 is oddReg.
4837   // Tmp2 is evenReg.
4838 
4839   int block_start = offset();
4840   Label doMVC, doMVCLE, done, MVC_template;
4841 
4842   BLOCK_COMMENT("CopyRawMemory_AlignedDisjoint {");
4843 
4844   // Check for zero len and convert to long.
4845   z_ltgfr(cnt_reg, cnt_reg);      // Remember casted value for doSTG case.
4846   z_bre(done);                    // Nothing to do if len == 0.
4847 
4848   z_sllg(Z_R1, cnt_reg, 3);       // Dst len in bytes. calc early to have the result ready.
4849 
4850   z_cghi(cnt_reg, 32);            // Check for len <= 256 bytes (<=32 DW).
4851   z_brnh(doMVC);                  // If so, use executed MVC to clear.
4852 
4853   bind(doMVCLE);                  // A lot of data (more than 256 bytes).
4854   // Prep dest reg pair.
4855   z_lgr(Z_R0, dst_reg);           // dst addr
4856   // Dst len already in Z_R1.
4857   // Prep src reg pair.
4858   z_lgr(tmp2_reg, src_reg);       // src addr
4859   z_lgr(tmp1_reg, Z_R1);          // Src len same as dst len.
4860 
4861   // Do the copy.
4862   move_long_ext(Z_R0, tmp2_reg, 0xb0); // Bypass cache.
4863   z_bru(done);                         // All done.
4864 
4865   bind(MVC_template);             // Just some data (not more than 256 bytes).
4866   z_mvc(0, 0, dst_reg, 0, src_reg);
4867 
4868   bind(doMVC);
4869 
4870   if (VM_Version::has_ExecuteExtensions()) {
4871     add2reg(Z_R1, -1);
4872   } else {
4873     add2reg(tmp1_reg, -1, Z_R1);
4874     z_larl(Z_R1, MVC_template);
4875   }
4876 
4877   if (VM_Version::has_Prefetch()) {
4878     z_pfd(1,  0,Z_R0,src_reg);
4879     z_pfd(2,  0,Z_R0,dst_reg);
4880     //    z_pfd(1,256,Z_R0,src_reg);    // Assume very short copy.
4881     //    z_pfd(2,256,Z_R0,dst_reg);
4882   }
4883 
4884   if (VM_Version::has_ExecuteExtensions()) {
4885     z_exrl(Z_R1, MVC_template);
4886   } else {
4887     z_ex(tmp1_reg, 0, Z_R0, Z_R1);
4888   }
4889 
4890   bind(done);
4891 
4892   BLOCK_COMMENT("} CopyRawMemory_AlignedDisjoint");
4893 
4894   int block_end = offset();
4895   return block_end - block_start;
4896 }
4897 
4898 //------------------------------------------------------
4899 //   Special String Intrinsics. Implementation
4900 //------------------------------------------------------
4901 
4902 // Intrinsics for CompactStrings
4903 
4904 // Compress char[] to byte[]. odd_reg contains cnt. Kills dst. Early clobber: result
4905 // The result is the number of characters copied before the first incompatible character was found.
4906 // If tmp2 is provided and the compression fails, the compression stops exactly at this point and the result is precise.
4907 //
4908 // Note: Does not behave exactly like package private StringUTF16 compress java implementation in case of failure:
4909 // - Different number of characters may have been written to dead array (if tmp2 not provided).
4910 // - Returns a number <cnt instead of 0. (Result gets compared with cnt.)
4911 unsigned int MacroAssembler::string_compress(Register result, Register src, Register dst, Register odd_reg,
4912                                              Register even_reg, Register tmp, Register tmp2) {
4913   int block_start = offset();
4914   Label Lloop1, Lloop2, Lslow, Ldone;
4915   const Register addr2 = dst, ind1 = result, mask = tmp;
4916   const bool precise = (tmp2 != noreg);
4917 
4918   BLOCK_COMMENT("string_compress {");
4919 
4920   z_sll(odd_reg, 1);       // Number of bytes to read. (Must be a positive simm32.)
4921   clear_reg(ind1);         // Index to read.
4922   z_llilf(mask, 0xFF00FF00);
4923   z_ahi(odd_reg, -16);     // Last possible index for fast loop.
4924   z_brl(Lslow);
4925 
4926   // ind1: index, even_reg: index increment, odd_reg: index limit
4927   z_iihf(mask, 0xFF00FF00);
4928   z_lhi(even_reg, 16);
4929 
4930   bind(Lloop1); // 8 Characters per iteration.
4931   z_lg(Z_R0, Address(src, ind1));
4932   z_lg(Z_R1, Address(src, ind1, 8));
4933   if (precise) {
4934     if (VM_Version::has_DistinctOpnds()) {
4935       z_ogrk(tmp2, Z_R0, Z_R1);
4936     } else {
4937       z_lgr(tmp2, Z_R0);
4938       z_ogr(tmp2, Z_R1);
4939     }
4940     z_ngr(tmp2, mask);
4941     z_brne(Lslow);         // Failed fast case, retry slowly.
4942   }
4943   z_stcmh(Z_R0, 5, 0, addr2);
4944   z_stcm(Z_R0, 5, 2, addr2);
4945   if (!precise) { z_ogr(Z_R0, Z_R1); }
4946   z_stcmh(Z_R1, 5, 4, addr2);
4947   z_stcm(Z_R1, 5, 6, addr2);
4948   if (!precise) {
4949     z_ngr(Z_R0, mask);
4950     z_brne(Ldone);         // Failed (more than needed was written).
4951   }
4952   z_aghi(addr2, 8);
4953   z_brxle(ind1, even_reg, Lloop1);
4954 
4955   bind(Lslow);
4956   // Compute index limit and skip if negative.
4957   z_ahi(odd_reg, 16-2);    // Last possible index for slow loop.
4958   z_lhi(even_reg, 2);
4959   z_cr(ind1, odd_reg);
4960   z_brh(Ldone);
4961 
4962   bind(Lloop2); // 1 Character per iteration.
4963   z_llh(Z_R0, Address(src, ind1));
4964   z_tmll(Z_R0, 0xFF00);
4965   z_brnaz(Ldone);          // Failed slow case: Return number of written characters.
4966   z_stc(Z_R0, Address(addr2));
4967   z_aghi(addr2, 1);
4968   z_brxle(ind1, even_reg, Lloop2);
4969 
4970   bind(Ldone);             // result = ind1 = 2*cnt
4971   z_srl(ind1, 1);
4972 
4973   BLOCK_COMMENT("} string_compress");
4974 
4975   return offset() - block_start;
4976 }
4977 
4978 // Inflate byte[] to char[].
4979 unsigned int MacroAssembler::string_inflate_trot(Register src, Register dst, Register cnt, Register tmp) {
4980   int block_start = offset();
4981 
4982   BLOCK_COMMENT("string_inflate {");
4983 
4984   Register stop_char = Z_R0;
4985   Register table     = Z_R1;
4986   Register src_addr  = tmp;
4987 
4988   assert_different_registers(Z_R0, Z_R1, tmp, src, dst, cnt);
4989   assert(dst->encoding()%2 == 0, "must be even reg");
4990   assert(cnt->encoding()%2 == 1, "must be odd reg");
4991   assert(cnt->encoding() - dst->encoding() == 1, "must be even/odd pair");
4992 
4993   StubRoutines::zarch::generate_load_trot_table_addr(this, table);  // kills Z_R0 (if ASSERT)
4994   clear_reg(stop_char);  // Stop character. Not used here, but initialized to have a defined value.
4995   lgr_if_needed(src_addr, src);
4996   z_llgfr(cnt, cnt);     // # src characters, must be a positive simm32.
4997 
4998   translate_ot(dst, src_addr, /* mask = */ 0x0001);
4999 
5000   BLOCK_COMMENT("} string_inflate");
5001 
5002   return offset() - block_start;
5003 }
5004 
5005 // Inflate byte[] to char[]. odd_reg contains cnt. Kills src.
5006 unsigned int MacroAssembler::string_inflate(Register src, Register dst, Register odd_reg,
5007                                             Register even_reg, Register tmp) {
5008   int block_start = offset();
5009 
5010   BLOCK_COMMENT("string_inflate {");
5011 
5012   Label Lloop1, Lloop2, Lslow, Ldone;
5013   const Register addr1 = src, ind2 = tmp;
5014 
5015   z_sll(odd_reg, 1);       // Number of bytes to write. (Must be a positive simm32.)
5016   clear_reg(ind2);         // Index to write.
5017   z_ahi(odd_reg, -16);     // Last possible index for fast loop.
5018   z_brl(Lslow);
5019 
5020   // ind2: index, even_reg: index increment, odd_reg: index limit
5021   clear_reg(Z_R0);
5022   clear_reg(Z_R1);
5023   z_lhi(even_reg, 16);
5024 
5025   bind(Lloop1); // 8 Characters per iteration.
5026   z_icmh(Z_R0, 5, 0, addr1);
5027   z_icmh(Z_R1, 5, 4, addr1);
5028   z_icm(Z_R0, 5, 2, addr1);
5029   z_icm(Z_R1, 5, 6, addr1);
5030   z_aghi(addr1, 8);
5031   z_stg(Z_R0, Address(dst, ind2));
5032   z_stg(Z_R1, Address(dst, ind2, 8));
5033   z_brxle(ind2, even_reg, Lloop1);
5034 
5035   bind(Lslow);
5036   // Compute index limit and skip if negative.
5037   z_ahi(odd_reg, 16-2);    // Last possible index for slow loop.
5038   z_lhi(even_reg, 2);
5039   z_cr(ind2, odd_reg);
5040   z_brh(Ldone);
5041 
5042   bind(Lloop2); // 1 Character per iteration.
5043   z_llc(Z_R0, Address(addr1));
5044   z_sth(Z_R0, Address(dst, ind2));
5045   z_aghi(addr1, 1);
5046   z_brxle(ind2, even_reg, Lloop2);
5047 
5048   bind(Ldone);
5049 
5050   BLOCK_COMMENT("} string_inflate");
5051 
5052   return offset() - block_start;
5053 }
5054 
5055 // Kills src.
5056 unsigned int MacroAssembler::has_negatives(Register result, Register src, Register cnt,
5057                                            Register odd_reg, Register even_reg, Register tmp) {
5058   int block_start = offset();
5059   Label Lloop1, Lloop2, Lslow, Lnotfound, Ldone;
5060   const Register addr = src, mask = tmp;
5061 
5062   BLOCK_COMMENT("has_negatives {");
5063 
5064   z_llgfr(Z_R1, cnt);      // Number of bytes to read. (Must be a positive simm32.)
5065   z_llilf(mask, 0x80808080);
5066   z_lhi(result, 1);        // Assume true.
5067   // Last possible addr for fast loop.
5068   z_lay(odd_reg, -16, Z_R1, src);
5069   z_chi(cnt, 16);
5070   z_brl(Lslow);
5071 
5072   // ind1: index, even_reg: index increment, odd_reg: index limit
5073   z_iihf(mask, 0x80808080);
5074   z_lghi(even_reg, 16);
5075 
5076   bind(Lloop1); // 16 bytes per iteration.
5077   z_lg(Z_R0, Address(addr));
5078   z_lg(Z_R1, Address(addr, 8));
5079   z_ogr(Z_R0, Z_R1);
5080   z_ngr(Z_R0, mask);
5081   z_brne(Ldone);           // If found return 1.
5082   z_brxlg(addr, even_reg, Lloop1);
5083 
5084   bind(Lslow);
5085   z_aghi(odd_reg, 16-1);   // Last possible addr for slow loop.
5086   z_lghi(even_reg, 1);
5087   z_cgr(addr, odd_reg);
5088   z_brh(Lnotfound);
5089 
5090   bind(Lloop2); // 1 byte per iteration.
5091   z_cli(Address(addr), 0x80);
5092   z_brnl(Ldone);           // If found return 1.
5093   z_brxlg(addr, even_reg, Lloop2);
5094 
5095   bind(Lnotfound);
5096   z_lhi(result, 0);
5097 
5098   bind(Ldone);
5099 
5100   BLOCK_COMMENT("} has_negatives");
5101 
5102   return offset() - block_start;
5103 }
5104 
5105 // kill: cnt1, cnt2, odd_reg, even_reg; early clobber: result
5106 unsigned int MacroAssembler::string_compare(Register str1, Register str2,
5107                                             Register cnt1, Register cnt2,
5108                                             Register odd_reg, Register even_reg, Register result, int ae) {
5109   int block_start = offset();
5110 
5111   assert_different_registers(str1, cnt1, cnt2, odd_reg, even_reg, result);
5112   assert_different_registers(str2, cnt1, cnt2, odd_reg, even_reg, result);
5113 
5114   // If strings are equal up to min length, return the length difference.
5115   const Register diff = result, // Pre-set result with length difference.
5116                  min  = cnt1,   // min number of bytes
5117                  tmp  = cnt2;
5118 
5119   // Note: Making use of the fact that compareTo(a, b) == -compareTo(b, a)
5120   // we interchange str1 and str2 in the UL case and negate the result.
5121   // Like this, str1 is always latin1 encoded, except for the UU case.
5122   // In addition, we need 0 (or sign which is 0) extend when using 64 bit register.
5123   const bool used_as_LU = (ae == StrIntrinsicNode::LU || ae == StrIntrinsicNode::UL);
5124 
5125   BLOCK_COMMENT("string_compare {");
5126 
5127   if (used_as_LU) {
5128     z_srl(cnt2, 1);
5129   }
5130 
5131   // See if the lengths are different, and calculate min in cnt1.
5132   // Save diff in case we need it for a tie-breaker.
5133 
5134   // diff = cnt1 - cnt2
5135   if (VM_Version::has_DistinctOpnds()) {
5136     z_srk(diff, cnt1, cnt2);
5137   } else {
5138     z_lr(diff, cnt1);
5139     z_sr(diff, cnt2);
5140   }
5141   if (str1 != str2) {
5142     if (VM_Version::has_LoadStoreConditional()) {
5143       z_locr(min, cnt2, Assembler::bcondHigh);
5144     } else {
5145       Label Lskip;
5146       z_brl(Lskip);    // min ok if cnt1 < cnt2
5147       z_lr(min, cnt2); // min = cnt2
5148       bind(Lskip);
5149     }
5150   }
5151 
5152   if (ae == StrIntrinsicNode::UU) {
5153     z_sra(diff, 1);
5154   }
5155   if (str1 != str2) {
5156     Label Ldone;
5157     if (used_as_LU) {
5158       // Loop which searches the first difference character by character.
5159       Label Lloop;
5160       const Register ind1 = Z_R1,
5161                      ind2 = min;
5162       int stride1 = 1, stride2 = 2; // See comment above.
5163 
5164       // ind1: index, even_reg: index increment, odd_reg: index limit
5165       z_llilf(ind1, (unsigned int)(-stride1));
5166       z_lhi(even_reg, stride1);
5167       add2reg(odd_reg, -stride1, min);
5168       clear_reg(ind2); // kills min
5169 
5170       bind(Lloop);
5171       z_brxh(ind1, even_reg, Ldone);
5172       z_llc(tmp, Address(str1, ind1));
5173       z_llh(Z_R0, Address(str2, ind2));
5174       z_ahi(ind2, stride2);
5175       z_sr(tmp, Z_R0);
5176       z_bre(Lloop);
5177 
5178       z_lr(result, tmp);
5179 
5180     } else {
5181       // Use clcle in fast loop (only for same encoding).
5182       z_lgr(Z_R0, str1);
5183       z_lgr(even_reg, str2);
5184       z_llgfr(Z_R1, min);
5185       z_llgfr(odd_reg, min);
5186 
5187       if (ae == StrIntrinsicNode::LL) {
5188         compare_long_ext(Z_R0, even_reg, 0);
5189       } else {
5190         compare_long_uni(Z_R0, even_reg, 0);
5191       }
5192       z_bre(Ldone);
5193       z_lgr(Z_R1, Z_R0);
5194       if (ae == StrIntrinsicNode::LL) {
5195         z_llc(Z_R0, Address(even_reg));
5196         z_llc(result, Address(Z_R1));
5197       } else {
5198         z_llh(Z_R0, Address(even_reg));
5199         z_llh(result, Address(Z_R1));
5200       }
5201       z_sr(result, Z_R0);
5202     }
5203 
5204     // Otherwise, return the difference between the first mismatched chars.
5205     bind(Ldone);
5206   }
5207 
5208   if (ae == StrIntrinsicNode::UL) {
5209     z_lcr(result, result); // Negate result (see note above).
5210   }
5211 
5212   BLOCK_COMMENT("} string_compare");
5213 
5214   return offset() - block_start;
5215 }
5216 
5217 unsigned int MacroAssembler::array_equals(bool is_array_equ, Register ary1, Register ary2, Register limit,
5218                                           Register odd_reg, Register even_reg, Register result, bool is_byte) {
5219   int block_start = offset();
5220 
5221   BLOCK_COMMENT("array_equals {");
5222 
5223   assert_different_registers(ary1, limit, odd_reg, even_reg);
5224   assert_different_registers(ary2, limit, odd_reg, even_reg);
5225 
5226   Label Ldone, Ldone_true, Ldone_false, Lclcle, CLC_template;
5227   int base_offset = 0;
5228 
5229   if (ary1 != ary2) {
5230     if (is_array_equ) {
5231       base_offset = arrayOopDesc::base_offset_in_bytes(is_byte ? T_BYTE : T_CHAR);
5232 
5233       // Return true if the same array.
5234       compareU64_and_branch(ary1, ary2, Assembler::bcondEqual, Ldone_true);
5235 
5236       // Return false if one of them is NULL.
5237       compareU64_and_branch(ary1, (intptr_t)0, Assembler::bcondEqual, Ldone_false);
5238       compareU64_and_branch(ary2, (intptr_t)0, Assembler::bcondEqual, Ldone_false);
5239 
5240       // Load the lengths of arrays.
5241       z_llgf(odd_reg, Address(ary1, arrayOopDesc::length_offset_in_bytes()));
5242 
5243       // Return false if the two arrays are not equal length.
5244       z_c(odd_reg, Address(ary2, arrayOopDesc::length_offset_in_bytes()));
5245       z_brne(Ldone_false);
5246 
5247       // string len in bytes (right operand)
5248       if (!is_byte) {
5249         z_chi(odd_reg, 128);
5250         z_sll(odd_reg, 1); // preserves flags
5251         z_brh(Lclcle);
5252       } else {
5253         compareU32_and_branch(odd_reg, (intptr_t)256, Assembler::bcondHigh, Lclcle);
5254       }
5255     } else {
5256       z_llgfr(odd_reg, limit); // Need to zero-extend prior to using the value.
5257       compareU32_and_branch(limit, (intptr_t)256, Assembler::bcondHigh, Lclcle);
5258     }
5259 
5260 
5261     // Use clc instruction for up to 256 bytes.
5262     {
5263       Register str1_reg = ary1,
5264           str2_reg = ary2;
5265       if (is_array_equ) {
5266         str1_reg = Z_R1;
5267         str2_reg = even_reg;
5268         add2reg(str1_reg, base_offset, ary1); // string addr (left operand)
5269         add2reg(str2_reg, base_offset, ary2); // string addr (right operand)
5270       }
5271       z_ahi(odd_reg, -1); // Clc uses decremented limit. Also compare result to 0.
5272       z_brl(Ldone_true);
5273       // Note: We could jump to the template if equal.
5274 
5275       assert(VM_Version::has_ExecuteExtensions(), "unsupported hardware");
5276       z_exrl(odd_reg, CLC_template);
5277       z_bre(Ldone_true);
5278       // fall through
5279 
5280       bind(Ldone_false);
5281       clear_reg(result);
5282       z_bru(Ldone);
5283 
5284       bind(CLC_template);
5285       z_clc(0, 0, str1_reg, 0, str2_reg);
5286     }
5287 
5288     // Use clcle instruction.
5289     {
5290       bind(Lclcle);
5291       add2reg(even_reg, base_offset, ary2); // string addr (right operand)
5292       add2reg(Z_R0, base_offset, ary1);     // string addr (left operand)
5293 
5294       z_lgr(Z_R1, odd_reg); // string len in bytes (left operand)
5295       if (is_byte) {
5296         compare_long_ext(Z_R0, even_reg, 0);
5297       } else {
5298         compare_long_uni(Z_R0, even_reg, 0);
5299       }
5300       z_lghi(result, 0); // Preserve flags.
5301       z_brne(Ldone);
5302     }
5303   }
5304   // fall through
5305 
5306   bind(Ldone_true);
5307   z_lghi(result, 1); // All characters are equal.
5308   bind(Ldone);
5309 
5310   BLOCK_COMMENT("} array_equals");
5311 
5312   return offset() - block_start;
5313 }
5314 
5315 // kill: haycnt, needlecnt, odd_reg, even_reg; early clobber: result
5316 unsigned int MacroAssembler::string_indexof(Register result, Register haystack, Register haycnt,
5317                                             Register needle, Register needlecnt, int needlecntval,
5318                                             Register odd_reg, Register even_reg, int ae) {
5319   int block_start = offset();
5320 
5321   // Ensure 0<needlecnt<=haycnt in ideal graph as prerequisite!
5322   assert(ae != StrIntrinsicNode::LU, "Invalid encoding");
5323   const int h_csize = (ae == StrIntrinsicNode::LL) ? 1 : 2;
5324   const int n_csize = (ae == StrIntrinsicNode::UU) ? 2 : 1;
5325   Label L_needle1, L_Found, L_NotFound;
5326 
5327   BLOCK_COMMENT("string_indexof {");
5328 
5329   if (needle == haystack) {
5330     z_lhi(result, 0);
5331   } else {
5332 
5333   // Load first character of needle (R0 used by search_string instructions).
5334   if (n_csize == 2) { z_llgh(Z_R0, Address(needle)); } else { z_llgc(Z_R0, Address(needle)); }
5335 
5336   // Compute last haystack addr to use if no match gets found.
5337   if (needlecnt != noreg) { // variable needlecnt
5338     z_ahi(needlecnt, -1); // Remaining characters after first one.
5339     z_sr(haycnt, needlecnt); // Compute index succeeding last element to compare.
5340     if (n_csize == 2) { z_sll(needlecnt, 1); } // In bytes.
5341   } else { // constant needlecnt
5342     assert((needlecntval & 0x7fff) == needlecntval, "must be positive simm16 immediate");
5343     // Compute index succeeding last element to compare.
5344     if (needlecntval != 1) { z_ahi(haycnt, 1 - needlecntval); }
5345   }
5346 
5347   z_llgfr(haycnt, haycnt); // Clear high half.
5348   z_lgr(result, haystack); // Final result will be computed from needle start pointer.
5349   if (h_csize == 2) { z_sll(haycnt, 1); } // Scale to number of bytes.
5350   z_agr(haycnt, haystack); // Point to address succeeding last element (haystack+scale*(haycnt-needlecnt+1)).
5351 
5352   if (h_csize != n_csize) {
5353     assert(ae == StrIntrinsicNode::UL, "Invalid encoding");
5354 
5355     if (needlecnt != noreg || needlecntval != 1) {
5356       if (needlecnt != noreg) {
5357         compare32_and_branch(needlecnt, (intptr_t)0, Assembler::bcondEqual, L_needle1);
5358       }
5359 
5360       // Main Loop: UL version (now we have at least 2 characters).
5361       Label L_OuterLoop, L_InnerLoop, L_Skip;
5362       bind(L_OuterLoop); // Search for 1st 2 characters.
5363       z_lgr(Z_R1, haycnt);
5364       MacroAssembler::search_string_uni(Z_R1, result);
5365       z_brc(Assembler::bcondNotFound, L_NotFound);
5366       z_lgr(result, Z_R1);
5367 
5368       z_lghi(Z_R1, n_csize);
5369       z_lghi(even_reg, h_csize);
5370       bind(L_InnerLoop);
5371       z_llgc(odd_reg, Address(needle, Z_R1));
5372       z_ch(odd_reg, Address(result, even_reg));
5373       z_brne(L_Skip);
5374       if (needlecnt != noreg) { z_cr(Z_R1, needlecnt); } else { z_chi(Z_R1, needlecntval - 1); }
5375       z_brnl(L_Found);
5376       z_aghi(Z_R1, n_csize);
5377       z_aghi(even_reg, h_csize);
5378       z_bru(L_InnerLoop);
5379 
5380       bind(L_Skip);
5381       z_aghi(result, h_csize); // This is the new address we want to use for comparing.
5382       z_bru(L_OuterLoop);
5383     }
5384 
5385   } else {
5386     const intptr_t needle_bytes = (n_csize == 2) ? ((needlecntval - 1) << 1) : (needlecntval - 1);
5387     Label L_clcle;
5388 
5389     if (needlecnt != noreg || (needlecntval != 1 && needle_bytes <= 256)) {
5390       if (needlecnt != noreg) {
5391         compare32_and_branch(needlecnt, 256, Assembler::bcondHigh, L_clcle);
5392         z_ahi(needlecnt, -1); // remaining bytes -1 (for CLC)
5393         z_brl(L_needle1);
5394       }
5395 
5396       // Main Loop: clc version (now we have at least 2 characters).
5397       Label L_OuterLoop, CLC_template;
5398       bind(L_OuterLoop); // Search for 1st 2 characters.
5399       z_lgr(Z_R1, haycnt);
5400       if (h_csize == 1) {
5401         MacroAssembler::search_string(Z_R1, result);
5402       } else {
5403         MacroAssembler::search_string_uni(Z_R1, result);
5404       }
5405       z_brc(Assembler::bcondNotFound, L_NotFound);
5406       z_lgr(result, Z_R1);
5407 
5408       if (needlecnt != noreg) {
5409         assert(VM_Version::has_ExecuteExtensions(), "unsupported hardware");
5410         z_exrl(needlecnt, CLC_template);
5411       } else {
5412         z_clc(h_csize, needle_bytes -1, Z_R1, n_csize, needle);
5413       }
5414       z_bre(L_Found);
5415       z_aghi(result, h_csize); // This is the new address we want to use for comparing.
5416       z_bru(L_OuterLoop);
5417 
5418       if (needlecnt != noreg) {
5419         bind(CLC_template);
5420         z_clc(h_csize, 0, Z_R1, n_csize, needle);
5421       }
5422     }
5423 
5424     if (needlecnt != noreg || needle_bytes > 256) {
5425       bind(L_clcle);
5426 
5427       // Main Loop: clcle version (now we have at least 256 bytes).
5428       Label L_OuterLoop, CLC_template;
5429       bind(L_OuterLoop); // Search for 1st 2 characters.
5430       z_lgr(Z_R1, haycnt);
5431       if (h_csize == 1) {
5432         MacroAssembler::search_string(Z_R1, result);
5433       } else {
5434         MacroAssembler::search_string_uni(Z_R1, result);
5435       }
5436       z_brc(Assembler::bcondNotFound, L_NotFound);
5437 
5438       add2reg(Z_R0, n_csize, needle);
5439       add2reg(even_reg, h_csize, Z_R1);
5440       z_lgr(result, Z_R1);
5441       if (needlecnt != noreg) {
5442         z_llgfr(Z_R1, needlecnt); // needle len in bytes (left operand)
5443         z_llgfr(odd_reg, needlecnt);
5444       } else {
5445         load_const_optimized(Z_R1, needle_bytes);
5446         if (Immediate::is_simm16(needle_bytes)) { z_lghi(odd_reg, needle_bytes); } else { z_lgr(odd_reg, Z_R1); }
5447       }
5448       if (h_csize == 1) {
5449         compare_long_ext(Z_R0, even_reg, 0);
5450       } else {
5451         compare_long_uni(Z_R0, even_reg, 0);
5452       }
5453       z_bre(L_Found);
5454 
5455       if (n_csize == 2) { z_llgh(Z_R0, Address(needle)); } else { z_llgc(Z_R0, Address(needle)); } // Reload.
5456       z_aghi(result, h_csize); // This is the new address we want to use for comparing.
5457       z_bru(L_OuterLoop);
5458     }
5459   }
5460 
5461   if (needlecnt != noreg || needlecntval == 1) {
5462     bind(L_needle1);
5463 
5464     // Single needle character version.
5465     if (h_csize == 1) {
5466       MacroAssembler::search_string(haycnt, result);
5467     } else {
5468       MacroAssembler::search_string_uni(haycnt, result);
5469     }
5470     z_lgr(result, haycnt);
5471     z_brc(Assembler::bcondFound, L_Found);
5472   }
5473 
5474   bind(L_NotFound);
5475   add2reg(result, -1, haystack); // Return -1.
5476 
5477   bind(L_Found); // Return index (or -1 in fallthrough case).
5478   z_sgr(result, haystack);
5479   if (h_csize == 2) { z_srag(result, result, exact_log2(sizeof(jchar))); }
5480   }
5481   BLOCK_COMMENT("} string_indexof");
5482 
5483   return offset() - block_start;
5484 }
5485 
5486 // early clobber: result
5487 unsigned int MacroAssembler::string_indexof_char(Register result, Register haystack, Register haycnt,
5488                                                  Register needle, jchar needleChar, Register odd_reg, Register even_reg, bool is_byte) {
5489   int block_start = offset();
5490 
5491   BLOCK_COMMENT("string_indexof_char {");
5492 
5493   if (needle == haystack) {
5494     z_lhi(result, 0);
5495   } else {
5496 
5497   Label Ldone;
5498 
5499   z_llgfr(odd_reg, haycnt);  // Preset loop ctr/searchrange end.
5500   if (needle == noreg) {
5501     load_const_optimized(Z_R0, (unsigned long)needleChar);
5502   } else {
5503     if (is_byte) {
5504       z_llgcr(Z_R0, needle); // First (and only) needle char.
5505     } else {
5506       z_llghr(Z_R0, needle); // First (and only) needle char.
5507     }
5508   }
5509 
5510   if (!is_byte) {
5511     z_agr(odd_reg, odd_reg); // Calc #bytes to be processed with SRSTU.
5512   }
5513 
5514   z_lgr(even_reg, haystack); // haystack addr
5515   z_agr(odd_reg, haystack);  // First char after range end.
5516   z_lghi(result, -1);
5517 
5518   if (is_byte) {
5519     MacroAssembler::search_string(odd_reg, even_reg);
5520   } else {
5521     MacroAssembler::search_string_uni(odd_reg, even_reg);
5522   }
5523   z_brc(Assembler::bcondNotFound, Ldone);
5524   if (is_byte) {
5525     if (VM_Version::has_DistinctOpnds()) {
5526       z_sgrk(result, odd_reg, haystack);
5527     } else {
5528       z_sgr(odd_reg, haystack);
5529       z_lgr(result, odd_reg);
5530     }
5531   } else {
5532     z_slgr(odd_reg, haystack);
5533     z_srlg(result, odd_reg, exact_log2(sizeof(jchar)));
5534   }
5535 
5536   bind(Ldone);
5537   }
5538   BLOCK_COMMENT("} string_indexof_char");
5539 
5540   return offset() - block_start;
5541 }
5542 
5543 
5544 //-------------------------------------------------
5545 //   Constants (scalar and oop) in constant pool
5546 //-------------------------------------------------
5547 
5548 // Add a non-relocated constant to the CP.
5549 int MacroAssembler::store_const_in_toc(AddressLiteral& val) {
5550   long    value  = val.value();
5551   address tocPos = long_constant(value);
5552 
5553   if (tocPos != NULL) {
5554     int tocOffset = (int)(tocPos - code()->consts()->start());
5555     return tocOffset;
5556   }
5557   // Address_constant returned NULL, so no constant entry has been created.
5558   // In that case, we return a "fatal" offset, just in case that subsequently
5559   // generated access code is executed.
5560   return -1;
5561 }
5562 
5563 // Returns the TOC offset where the address is stored.
5564 // Add a relocated constant to the CP.
5565 int MacroAssembler::store_oop_in_toc(AddressLiteral& oop) {
5566   // Use RelocationHolder::none for the constant pool entry.
5567   // Otherwise we will end up with a failing NativeCall::verify(x),
5568   // where x is the address of the constant pool entry.
5569   address tocPos = address_constant((address)oop.value(), RelocationHolder::none);
5570 
5571   if (tocPos != NULL) {
5572     int              tocOffset = (int)(tocPos - code()->consts()->start());
5573     RelocationHolder rsp = oop.rspec();
5574     Relocation      *rel = rsp.reloc();
5575 
5576     // Store toc_offset in relocation, used by call_far_patchable.
5577     if ((relocInfo::relocType)rel->type() == relocInfo::runtime_call_w_cp_type) {
5578       ((runtime_call_w_cp_Relocation *)(rel))->set_constant_pool_offset(tocOffset);
5579     }
5580     // Relocate at the load's pc.
5581     relocate(rsp);
5582 
5583     return tocOffset;
5584   }
5585   // Address_constant returned NULL, so no constant entry has been created
5586   // in that case, we return a "fatal" offset, just in case that subsequently
5587   // generated access code is executed.
5588   return -1;
5589 }
5590 
5591 bool MacroAssembler::load_const_from_toc(Register dst, AddressLiteral& a, Register Rtoc) {
5592   int     tocOffset = store_const_in_toc(a);
5593   if (tocOffset == -1) return false;
5594   address tocPos    = tocOffset + code()->consts()->start();
5595   assert((address)code()->consts()->start() != NULL, "Please add CP address");
5596 
5597   load_long_pcrelative(dst, tocPos);
5598   return true;
5599 }
5600 
5601 bool MacroAssembler::load_oop_from_toc(Register dst, AddressLiteral& a, Register Rtoc) {
5602   int     tocOffset = store_oop_in_toc(a);
5603   if (tocOffset == -1) return false;
5604   address tocPos    = tocOffset + code()->consts()->start();
5605   assert((address)code()->consts()->start() != NULL, "Please add CP address");
5606 
5607   load_addr_pcrelative(dst, tocPos);
5608   return true;
5609 }
5610 
5611 // If the instruction sequence at the given pc is a load_const_from_toc
5612 // sequence, return the value currently stored at the referenced position
5613 // in the TOC.
5614 intptr_t MacroAssembler::get_const_from_toc(address pc) {
5615 
5616   assert(is_load_const_from_toc(pc), "must be load_const_from_pool");
5617 
5618   long    offset  = get_load_const_from_toc_offset(pc);
5619   address dataLoc = NULL;
5620   if (is_load_const_from_toc_pcrelative(pc)) {
5621     dataLoc = pc + offset;
5622   } else {
5623     CodeBlob* cb = CodeCache::find_blob_unsafe(pc);   // Else we get assertion if nmethod is zombie.
5624     assert(cb && cb->is_nmethod(), "sanity");
5625     nmethod* nm = (nmethod*)cb;
5626     dataLoc = nm->ctable_begin() + offset;
5627   }
5628   return *(intptr_t *)dataLoc;
5629 }
5630 
5631 // If the instruction sequence at the given pc is a load_const_from_toc
5632 // sequence, copy the passed-in new_data value into the referenced
5633 // position in the TOC.
5634 void MacroAssembler::set_const_in_toc(address pc, unsigned long new_data, CodeBlob *cb) {
5635   assert(is_load_const_from_toc(pc), "must be load_const_from_pool");
5636 
5637   long    offset = MacroAssembler::get_load_const_from_toc_offset(pc);
5638   address dataLoc = NULL;
5639   if (is_load_const_from_toc_pcrelative(pc)) {
5640     dataLoc = pc+offset;
5641   } else {
5642     nmethod* nm = CodeCache::find_nmethod(pc);
5643     assert((cb == NULL) || (nm == (nmethod*)cb), "instruction address should be in CodeBlob");
5644     dataLoc = nm->ctable_begin() + offset;
5645   }
5646   if (*(unsigned long *)dataLoc != new_data) { // Prevent cache invalidation: update only if necessary.
5647     *(unsigned long *)dataLoc = new_data;
5648   }
5649 }
5650 
5651 // Dynamic TOC. Getter must only be called if "a" is a load_const_from_toc
5652 // site. Verify by calling is_load_const_from_toc() before!!
5653 // Offset is +/- 2**32 -> use long.
5654 long MacroAssembler::get_load_const_from_toc_offset(address a) {
5655   assert(is_load_const_from_toc_pcrelative(a), "expected pc relative load");
5656   //  expected code sequence:
5657   //    z_lgrl(t, simm32);    len = 6
5658   unsigned long inst;
5659   unsigned int  len = get_instruction(a, &inst);
5660   return get_pcrel_offset(inst);
5661 }
5662 
5663 //**********************************************************************************
5664 //  inspection of generated instruction sequences for a particular pattern
5665 //**********************************************************************************
5666 
5667 bool MacroAssembler::is_load_const_from_toc_pcrelative(address a) {
5668 #ifdef ASSERT
5669   unsigned long inst;
5670   unsigned int  len = get_instruction(a+2, &inst);
5671   if ((len == 6) && is_load_pcrelative_long(a) && is_call_pcrelative_long(inst)) {
5672     const int range = 128;
5673     Assembler::dump_code_range(tty, a, range, "instr(a) == z_lgrl && instr(a+2) == z_brasl");
5674     VM_Version::z_SIGSEGV();
5675   }
5676 #endif
5677   // expected code sequence:
5678   //   z_lgrl(t, relAddr32);    len = 6
5679   //TODO: verify accessed data is in CP, if possible.
5680   return is_load_pcrelative_long(a);  // TODO: might be too general. Currently, only lgrl is used.
5681 }
5682 
5683 bool MacroAssembler::is_load_const_from_toc_call(address a) {
5684   return is_load_const_from_toc(a) && is_call_byregister(a + load_const_from_toc_size());
5685 }
5686 
5687 bool MacroAssembler::is_load_const_call(address a) {
5688   return is_load_const(a) && is_call_byregister(a + load_const_size());
5689 }
5690 
5691 //-------------------------------------------------
5692 //   Emitters for some really CICS instructions
5693 //-------------------------------------------------
5694 
5695 void MacroAssembler::move_long_ext(Register dst, Register src, unsigned int pad) {
5696   assert(dst->encoding()%2==0, "must be an even/odd register pair");
5697   assert(src->encoding()%2==0, "must be an even/odd register pair");
5698   assert(pad<256, "must be a padding BYTE");
5699 
5700   Label retry;
5701   bind(retry);
5702   Assembler::z_mvcle(dst, src, pad);
5703   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5704 }
5705 
5706 void MacroAssembler::compare_long_ext(Register left, Register right, unsigned int pad) {
5707   assert(left->encoding() % 2 == 0, "must be an even/odd register pair");
5708   assert(right->encoding() % 2 == 0, "must be an even/odd register pair");
5709   assert(pad<256, "must be a padding BYTE");
5710 
5711   Label retry;
5712   bind(retry);
5713   Assembler::z_clcle(left, right, pad, Z_R0);
5714   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5715 }
5716 
5717 void MacroAssembler::compare_long_uni(Register left, Register right, unsigned int pad) {
5718   assert(left->encoding() % 2 == 0, "must be an even/odd register pair");
5719   assert(right->encoding() % 2 == 0, "must be an even/odd register pair");
5720   assert(pad<=0xfff, "must be a padding HALFWORD");
5721   assert(VM_Version::has_ETF2(), "instruction must be available");
5722 
5723   Label retry;
5724   bind(retry);
5725   Assembler::z_clclu(left, right, pad, Z_R0);
5726   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5727 }
5728 
5729 void MacroAssembler::search_string(Register end, Register start) {
5730   assert(end->encoding() != 0, "end address must not be in R0");
5731   assert(start->encoding() != 0, "start address must not be in R0");
5732 
5733   Label retry;
5734   bind(retry);
5735   Assembler::z_srst(end, start);
5736   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5737 }
5738 
5739 void MacroAssembler::search_string_uni(Register end, Register start) {
5740   assert(end->encoding() != 0, "end address must not be in R0");
5741   assert(start->encoding() != 0, "start address must not be in R0");
5742   assert(VM_Version::has_ETF3(), "instruction must be available");
5743 
5744   Label retry;
5745   bind(retry);
5746   Assembler::z_srstu(end, start);
5747   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5748 }
5749 
5750 void MacroAssembler::kmac(Register srcBuff) {
5751   assert(srcBuff->encoding()     != 0, "src buffer address can't be in Z_R0");
5752   assert(srcBuff->encoding() % 2 == 0, "src buffer/len must be an even/odd register pair");
5753 
5754   Label retry;
5755   bind(retry);
5756   Assembler::z_kmac(Z_R0, srcBuff);
5757   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5758 }
5759 
5760 void MacroAssembler::kimd(Register srcBuff) {
5761   assert(srcBuff->encoding()     != 0, "src buffer address can't be in Z_R0");
5762   assert(srcBuff->encoding() % 2 == 0, "src buffer/len must be an even/odd register pair");
5763 
5764   Label retry;
5765   bind(retry);
5766   Assembler::z_kimd(Z_R0, srcBuff);
5767   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5768 }
5769 
5770 void MacroAssembler::klmd(Register srcBuff) {
5771   assert(srcBuff->encoding()     != 0, "src buffer address can't be in Z_R0");
5772   assert(srcBuff->encoding() % 2 == 0, "src buffer/len must be an even/odd register pair");
5773 
5774   Label retry;
5775   bind(retry);
5776   Assembler::z_klmd(Z_R0, srcBuff);
5777   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5778 }
5779 
5780 void MacroAssembler::km(Register dstBuff, Register srcBuff) {
5781   // DstBuff and srcBuff are allowed to be the same register (encryption in-place).
5782   // DstBuff and srcBuff storage must not overlap destructively, and neither must overlap the parameter block.
5783   assert(srcBuff->encoding()     != 0, "src buffer address can't be in Z_R0");
5784   assert(dstBuff->encoding() % 2 == 0, "dst buffer addr must be an even register");
5785   assert(srcBuff->encoding() % 2 == 0, "src buffer addr/len must be an even/odd register pair");
5786 
5787   Label retry;
5788   bind(retry);
5789   Assembler::z_km(dstBuff, srcBuff);
5790   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5791 }
5792 
5793 void MacroAssembler::kmc(Register dstBuff, Register srcBuff) {
5794   // DstBuff and srcBuff are allowed to be the same register (encryption in-place).
5795   // DstBuff and srcBuff storage must not overlap destructively, and neither must overlap the parameter block.
5796   assert(srcBuff->encoding()     != 0, "src buffer address can't be in Z_R0");
5797   assert(dstBuff->encoding() % 2 == 0, "dst buffer addr must be an even register");
5798   assert(srcBuff->encoding() % 2 == 0, "src buffer addr/len must be an even/odd register pair");
5799 
5800   Label retry;
5801   bind(retry);
5802   Assembler::z_kmc(dstBuff, srcBuff);
5803   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5804 }
5805 
5806 void MacroAssembler::cksm(Register crcBuff, Register srcBuff) {
5807   assert(srcBuff->encoding() % 2 == 0, "src buffer addr/len must be an even/odd register pair");
5808 
5809   Label retry;
5810   bind(retry);
5811   Assembler::z_cksm(crcBuff, srcBuff);
5812   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5813 }
5814 
5815 void MacroAssembler::translate_oo(Register r1, Register r2, uint m3) {
5816   assert(r1->encoding() % 2 == 0, "dst addr/src len must be an even/odd register pair");
5817   assert((m3 & 0b1110) == 0, "Unused mask bits must be zero");
5818 
5819   Label retry;
5820   bind(retry);
5821   Assembler::z_troo(r1, r2, m3);
5822   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5823 }
5824 
5825 void MacroAssembler::translate_ot(Register r1, Register r2, uint m3) {
5826   assert(r1->encoding() % 2 == 0, "dst addr/src len must be an even/odd register pair");
5827   assert((m3 & 0b1110) == 0, "Unused mask bits must be zero");
5828 
5829   Label retry;
5830   bind(retry);
5831   Assembler::z_trot(r1, r2, m3);
5832   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5833 }
5834 
5835 void MacroAssembler::translate_to(Register r1, Register r2, uint m3) {
5836   assert(r1->encoding() % 2 == 0, "dst addr/src len must be an even/odd register pair");
5837   assert((m3 & 0b1110) == 0, "Unused mask bits must be zero");
5838 
5839   Label retry;
5840   bind(retry);
5841   Assembler::z_trto(r1, r2, m3);
5842   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5843 }
5844 
5845 void MacroAssembler::translate_tt(Register r1, Register r2, uint m3) {
5846   assert(r1->encoding() % 2 == 0, "dst addr/src len must be an even/odd register pair");
5847   assert((m3 & 0b1110) == 0, "Unused mask bits must be zero");
5848 
5849   Label retry;
5850   bind(retry);
5851   Assembler::z_trtt(r1, r2, m3);
5852   Assembler::z_brc(Assembler::bcondOverflow /* CC==3 (iterate) */, retry);
5853 }
5854 
5855 void MacroAssembler::generate_safepoint_check(Label& slow_path, Register scratch, bool may_relocate) {
5856   if (scratch == noreg) scratch = Z_R1;
5857   address Astate = SafepointSynchronize::address_of_state();
5858   BLOCK_COMMENT("safepoint check:");
5859 
5860   if (may_relocate) {
5861     ptrdiff_t total_distance = Astate - this->pc();
5862     if (RelAddr::is_in_range_of_RelAddr32(total_distance)) {
5863       RelocationHolder rspec = external_word_Relocation::spec(Astate);
5864       (this)->relocate(rspec, relocInfo::pcrel_addr_format);
5865       load_absolute_address(scratch, Astate);
5866     } else {
5867       load_const_optimized(scratch, Astate);
5868     }
5869   } else {
5870     load_absolute_address(scratch, Astate);
5871   }
5872   z_cli(/*SafepointSynchronize::sz_state()*/4-1, scratch, SafepointSynchronize::_not_synchronized);
5873   z_brne(slow_path);
5874 }
5875 
5876 
5877 void MacroAssembler::generate_type_profiling(const Register Rdata,
5878                                              const Register Rreceiver_klass,
5879                                              const Register Rwanted_receiver_klass,
5880                                              const Register Rmatching_row,
5881                                              bool is_virtual_call) {
5882   const int row_size = in_bytes(ReceiverTypeData::receiver_offset(1)) -
5883                        in_bytes(ReceiverTypeData::receiver_offset(0));
5884   const int num_rows = ReceiverTypeData::row_limit();
5885   NearLabel found_free_row;
5886   NearLabel do_increment;
5887   NearLabel found_no_slot;
5888 
5889   BLOCK_COMMENT("type profiling {");
5890 
5891   // search for:
5892   //    a) The type given in Rwanted_receiver_klass.
5893   //    b) The *first* empty row.
5894 
5895   // First search for a) only, just running over b) with no regard.
5896   // This is possible because
5897   //    wanted_receiver_class == receiver_class  &&  wanted_receiver_class == 0
5898   // is never true (receiver_class can't be zero).
5899   for (int row_num = 0; row_num < num_rows; row_num++) {
5900     // Row_offset should be a well-behaved positive number. The generated code relies
5901     // on that wrt constant code size. Add2reg can handle all row_offset values, but
5902     // will have to vary generated code size.
5903     int row_offset = in_bytes(ReceiverTypeData::receiver_offset(row_num));
5904     assert(Displacement::is_shortDisp(row_offset), "Limitation of generated code");
5905 
5906     // Is Rwanted_receiver_klass in this row?
5907     if (VM_Version::has_CompareBranch()) {
5908       z_lg(Rwanted_receiver_klass, row_offset, Z_R0, Rdata);
5909       // Rmatching_row = Rdata + row_offset;
5910       add2reg(Rmatching_row, row_offset, Rdata);
5911       // if (*row_recv == (intptr_t) receiver_klass) goto fill_existing_slot;
5912       compare64_and_branch(Rwanted_receiver_klass, Rreceiver_klass, Assembler::bcondEqual, do_increment);
5913     } else {
5914       add2reg(Rmatching_row, row_offset, Rdata);
5915       z_cg(Rreceiver_klass, row_offset, Z_R0, Rdata);
5916       z_bre(do_increment);
5917     }
5918   }
5919 
5920   // Now that we did not find a match, let's search for b).
5921 
5922   // We could save the first calculation of Rmatching_row if we woud search for a) in reverse order.
5923   // We would then end up here with Rmatching_row containing the value for row_num == 0.
5924   // We would not see much benefit, if any at all, because the CPU can schedule
5925   // two instructions together with a branch anyway.
5926   for (int row_num = 0; row_num < num_rows; row_num++) {
5927     int row_offset = in_bytes(ReceiverTypeData::receiver_offset(row_num));
5928 
5929     // Has this row a zero receiver_klass, i.e. is it empty?
5930     if (VM_Version::has_CompareBranch()) {
5931       z_lg(Rwanted_receiver_klass, row_offset, Z_R0, Rdata);
5932       // Rmatching_row = Rdata + row_offset
5933       add2reg(Rmatching_row, row_offset, Rdata);
5934       // if (*row_recv == (intptr_t) 0) goto found_free_row
5935       compare64_and_branch(Rwanted_receiver_klass, (intptr_t)0, Assembler::bcondEqual, found_free_row);
5936     } else {
5937       add2reg(Rmatching_row, row_offset, Rdata);
5938       load_and_test_long(Rwanted_receiver_klass, Address(Rdata, row_offset));
5939       z_bre(found_free_row);  // zero -> Found a free row.
5940     }
5941   }
5942 
5943   // No match, no empty row found.
5944   // Increment total counter to indicate polymorphic case.
5945   if (is_virtual_call) {
5946     add2mem_64(Address(Rdata, CounterData::count_offset()), 1, Rmatching_row);
5947   }
5948   z_bru(found_no_slot);
5949 
5950   // Here we found an empty row, but we have not found Rwanted_receiver_klass.
5951   // Rmatching_row holds the address to the first empty row.
5952   bind(found_free_row);
5953   // Store receiver_klass into empty slot.
5954   z_stg(Rreceiver_klass, 0, Z_R0, Rmatching_row);
5955 
5956   // Increment the counter of Rmatching_row.
5957   bind(do_increment);
5958   ByteSize counter_offset = ReceiverTypeData::receiver_count_offset(0) - ReceiverTypeData::receiver_offset(0);
5959   add2mem_64(Address(Rmatching_row, counter_offset), 1, Rdata);
5960 
5961   bind(found_no_slot);
5962 
5963   BLOCK_COMMENT("} type profiling");
5964 }
5965 
5966 //---------------------------------------
5967 // Helpers for Intrinsic Emitters
5968 //---------------------------------------
5969 
5970 /**
5971  * uint32_t crc;
5972  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
5973  */
5974 void MacroAssembler::fold_byte_crc32(Register crc, Register val, Register table, Register tmp) {
5975   assert_different_registers(crc, table, tmp);
5976   assert_different_registers(val, table);
5977   if (crc == val) {      // Must rotate first to use the unmodified value.
5978     rotate_then_insert(tmp, val, 56-2, 63-2, 2, true);  // Insert byte 7 of val, shifted left by 2, into byte 6..7 of tmp, clear the rest.
5979     z_srl(crc, 8);       // Unsigned shift, clear leftmost 8 bits.
5980   } else {
5981     z_srl(crc, 8);       // Unsigned shift, clear leftmost 8 bits.
5982     rotate_then_insert(tmp, val, 56-2, 63-2, 2, true);  // Insert byte 7 of val, shifted left by 2, into byte 6..7 of tmp, clear the rest.
5983   }
5984   z_x(crc, Address(table, tmp, 0));
5985 }
5986 
5987 /**
5988  * uint32_t crc;
5989  * timesXtoThe32[crc & 0xFF] ^ (crc >> 8);
5990  */
5991 void MacroAssembler::fold_8bit_crc32(Register crc, Register table, Register tmp) {
5992   fold_byte_crc32(crc, crc, table, tmp);
5993 }
5994 
5995 /**
5996  * Emits code to update CRC-32 with a byte value according to constants in table.
5997  *
5998  * @param [in,out]crc Register containing the crc.
5999  * @param [in]val     Register containing the byte to fold into the CRC.
6000  * @param [in]table   Register containing the table of crc constants.
6001  *
6002  * uint32_t crc;
6003  * val = crc_table[(val ^ crc) & 0xFF];
6004  * crc = val ^ (crc >> 8);
6005  */
6006 void MacroAssembler::update_byte_crc32(Register crc, Register val, Register table) {
6007   z_xr(val, crc);
6008   fold_byte_crc32(crc, val, table, val);
6009 }
6010 
6011 
6012 /**
6013  * @param crc   register containing existing CRC (32-bit)
6014  * @param buf   register pointing to input byte buffer (byte*)
6015  * @param len   register containing number of bytes
6016  * @param table register pointing to CRC table
6017  */
6018 void MacroAssembler::update_byteLoop_crc32(Register crc, Register buf, Register len, Register table, Register data) {
6019   assert_different_registers(crc, buf, len, table, data);
6020 
6021   Label L_mainLoop, L_done;
6022   const int mainLoop_stepping = 1;
6023 
6024   // Process all bytes in a single-byte loop.
6025   z_ltr(len, len);
6026   z_brnh(L_done);
6027 
6028   bind(L_mainLoop);
6029     z_llgc(data, Address(buf, (intptr_t)0));// Current byte of input buffer (zero extended). Avoids garbage in upper half of register.
6030     add2reg(buf, mainLoop_stepping);        // Advance buffer position.
6031     update_byte_crc32(crc, data, table);
6032     z_brct(len, L_mainLoop);                // Iterate.
6033 
6034   bind(L_done);
6035 }
6036 
6037 /**
6038  * Emits code to update CRC-32 with a 4-byte value according to constants in table.
6039  * Implementation according to jdk/src/share/native/java/util/zip/zlib-1.2.8/crc32.c.
6040  *
6041  */
6042 void MacroAssembler::update_1word_crc32(Register crc, Register buf, Register table, int bufDisp, int bufInc,
6043                                         Register t0,  Register t1,  Register t2,    Register t3) {
6044   // This is what we implement (the DOBIG4 part):
6045   //
6046   // #define DOBIG4 c ^= *++buf4; \
6047   //         c = crc_table[4][c & 0xff] ^ crc_table[5][(c >> 8) & 0xff] ^ \
6048   //             crc_table[6][(c >> 16) & 0xff] ^ crc_table[7][c >> 24]
6049   // #define DOBIG32 DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4; DOBIG4
6050   // Pre-calculate (constant) column offsets, use columns 4..7 for big-endian.
6051   const int ix0 = 4*(4*CRC32_COLUMN_SIZE);
6052   const int ix1 = 5*(4*CRC32_COLUMN_SIZE);
6053   const int ix2 = 6*(4*CRC32_COLUMN_SIZE);
6054   const int ix3 = 7*(4*CRC32_COLUMN_SIZE);
6055 
6056   // XOR crc with next four bytes of buffer.
6057   lgr_if_needed(t0, crc);
6058   z_x(t0, Address(buf, bufDisp));
6059   if (bufInc != 0) {
6060     add2reg(buf, bufInc);
6061   }
6062 
6063   // Chop crc into 4 single-byte pieces, shifted left 2 bits, to form the table indices.
6064   rotate_then_insert(t3, t0, 56-2, 63-2, 2,    true);  // ((c >>  0) & 0xff) << 2
6065   rotate_then_insert(t2, t0, 56-2, 63-2, 2-8,  true);  // ((c >>  8) & 0xff) << 2
6066   rotate_then_insert(t1, t0, 56-2, 63-2, 2-16, true);  // ((c >> 16) & 0xff) << 2
6067   rotate_then_insert(t0, t0, 56-2, 63-2, 2-24, true);  // ((c >> 24) & 0xff) << 2
6068 
6069   // XOR indexed table values to calculate updated crc.
6070   z_ly(t2, Address(table, t2, (intptr_t)ix1));
6071   z_ly(t0, Address(table, t0, (intptr_t)ix3));
6072   z_xy(t2, Address(table, t3, (intptr_t)ix0));
6073   z_xy(t0, Address(table, t1, (intptr_t)ix2));
6074   z_xr(t0, t2);           // Now t0 contains the updated CRC value.
6075   lgr_if_needed(crc, t0);
6076 }
6077 
6078 /**
6079  * @param crc   register containing existing CRC (32-bit)
6080  * @param buf   register pointing to input byte buffer (byte*)
6081  * @param len   register containing number of bytes
6082  * @param table register pointing to CRC table
6083  *
6084  * uses Z_R10..Z_R13 as work register. Must be saved/restored by caller!
6085  */
6086 void MacroAssembler::kernel_crc32_2word(Register crc, Register buf, Register len, Register table,
6087                                         Register t0,  Register t1,  Register t2,  Register t3,
6088                                         bool invertCRC) {
6089   assert_different_registers(crc, buf, len, table);
6090 
6091   Label L_mainLoop, L_tail;
6092   Register  data = t0;
6093   Register  ctr  = Z_R0;
6094   const int mainLoop_stepping = 8;
6095   const int tailLoop_stepping = 1;
6096   const int log_stepping      = exact_log2(mainLoop_stepping);
6097 
6098   // Don't test for len <= 0 here. This pathological case should not occur anyway.
6099   // Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles.
6100   // The situation itself is detected and handled correctly by the conditional branches
6101   // following aghi(len, -stepping) and aghi(len, +stepping).
6102 
6103   if (invertCRC) {
6104     not_(crc, noreg, false);           // 1s complement of crc
6105   }
6106 
6107 #if 0
6108   {
6109     // Pre-mainLoop alignment did not show any positive effect on performance.
6110     // We leave the code in for reference. Maybe the vector instructions in z13 depend on alignment.
6111 
6112     z_cghi(len, mainLoop_stepping);    // Alignment is useless for short data streams.
6113     z_brnh(L_tail);
6114 
6115     // Align buf to word (4-byte) boundary.
6116     z_lcr(ctr, buf);
6117     rotate_then_insert(ctr, ctr, 62, 63, 0, true); // TODO: should set cc
6118     z_sgfr(len, ctr);                  // Remaining len after alignment.
6119 
6120     update_byteLoop_crc32(crc, buf, ctr, table, data);
6121   }
6122 #endif
6123 
6124   // Check for short (<mainLoop_stepping bytes) buffer.
6125   z_srag(ctr, len, log_stepping);
6126   z_brnh(L_tail);
6127 
6128   z_lrvr(crc, crc);          // Revert byte order because we are dealing with big-endian data.
6129   rotate_then_insert(len, len, 64-log_stepping, 63, 0, true); // #bytes for tailLoop
6130 
6131   BIND(L_mainLoop);
6132     update_1word_crc32(crc, buf, table, 0, 0, crc, t1, t2, t3);
6133     update_1word_crc32(crc, buf, table, 4, mainLoop_stepping, crc, t1, t2, t3);
6134     z_brct(ctr, L_mainLoop); // Iterate.
6135 
6136   z_lrvr(crc, crc);          // Revert byte order back to original.
6137 
6138   // Process last few (<8) bytes of buffer.
6139   BIND(L_tail);
6140   update_byteLoop_crc32(crc, buf, len, table, data);
6141 
6142   if (invertCRC) {
6143     not_(crc, noreg, false);           // 1s complement of crc
6144   }
6145 }
6146 
6147 /**
6148  * @param crc   register containing existing CRC (32-bit)
6149  * @param buf   register pointing to input byte buffer (byte*)
6150  * @param len   register containing number of bytes
6151  * @param table register pointing to CRC table
6152  *
6153  * uses Z_R10..Z_R13 as work register. Must be saved/restored by caller!
6154  */
6155 void MacroAssembler::kernel_crc32_1word(Register crc, Register buf, Register len, Register table,
6156                                         Register t0,  Register t1,  Register t2,  Register t3,
6157                                         bool invertCRC) {
6158   assert_different_registers(crc, buf, len, table);
6159 
6160   Label L_mainLoop, L_tail;
6161   Register  data = t0;
6162   Register  ctr  = Z_R0;
6163   const int mainLoop_stepping = 4;
6164   const int log_stepping      = exact_log2(mainLoop_stepping);
6165 
6166   // Don't test for len <= 0 here. This pathological case should not occur anyway.
6167   // Optimizing for it by adding a test and a branch seems to be a waste of CPU cycles.
6168   // The situation itself is detected and handled correctly by the conditional branches
6169   // following aghi(len, -stepping) and aghi(len, +stepping).
6170 
6171   if (invertCRC) {
6172     not_(crc, noreg, false);           // 1s complement of crc
6173   }
6174 
6175   // Check for short (<4 bytes) buffer.
6176   z_srag(ctr, len, log_stepping);
6177   z_brnh(L_tail);
6178 
6179   z_lrvr(crc, crc);          // Revert byte order because we are dealing with big-endian data.
6180   rotate_then_insert(len, len, 64-log_stepping, 63, 0, true); // #bytes for tailLoop
6181 
6182   BIND(L_mainLoop);
6183     update_1word_crc32(crc, buf, table, 0, mainLoop_stepping, crc, t1, t2, t3);
6184     z_brct(ctr, L_mainLoop); // Iterate.
6185 
6186   z_lrvr(crc, crc);          // Revert byte order back to original.
6187 
6188   // Process last few (<8) bytes of buffer.
6189   BIND(L_tail);
6190   update_byteLoop_crc32(crc, buf, len, table, data);
6191 
6192   if (invertCRC) {
6193     not_(crc, noreg, false);           // 1s complement of crc
6194   }
6195 }
6196 
6197 /**
6198  * @param crc   register containing existing CRC (32-bit)
6199  * @param buf   register pointing to input byte buffer (byte*)
6200  * @param len   register containing number of bytes
6201  * @param table register pointing to CRC table
6202  */
6203 void MacroAssembler::kernel_crc32_1byte(Register crc, Register buf, Register len, Register table,
6204                                         Register t0,  Register t1,  Register t2,  Register t3,
6205                                         bool invertCRC) {
6206   assert_different_registers(crc, buf, len, table);
6207   Register data = t0;
6208 
6209   if (invertCRC) {
6210     not_(crc, noreg, false);           // 1s complement of crc
6211   }
6212 
6213   update_byteLoop_crc32(crc, buf, len, table, data);
6214 
6215   if (invertCRC) {
6216     not_(crc, noreg, false);           // 1s complement of crc
6217   }
6218 }
6219 
6220 void MacroAssembler::kernel_crc32_singleByte(Register crc, Register buf, Register len, Register table, Register tmp,
6221                                              bool invertCRC) {
6222   assert_different_registers(crc, buf, len, table, tmp);
6223 
6224   if (invertCRC) {
6225     not_(crc, noreg, false);           // 1s complement of crc
6226   }
6227 
6228   z_llgc(tmp, Address(buf, (intptr_t)0));  // Current byte of input buffer (zero extended). Avoids garbage in upper half of register.
6229   update_byte_crc32(crc, tmp, table);
6230 
6231   if (invertCRC) {
6232     not_(crc, noreg, false);           // 1s complement of crc
6233   }
6234 }
6235 
6236 void MacroAssembler::kernel_crc32_singleByteReg(Register crc, Register val, Register table,
6237                                                 bool invertCRC) {
6238   assert_different_registers(crc, val, table);
6239 
6240   if (invertCRC) {
6241     not_(crc, noreg, false);           // 1s complement of crc
6242   }
6243 
6244   update_byte_crc32(crc, val, table);
6245 
6246   if (invertCRC) {
6247     not_(crc, noreg, false);           // 1s complement of crc
6248   }
6249 }
6250 
6251 //
6252 // Code for BigInteger::multiplyToLen() intrinsic.
6253 //
6254 
6255 // dest_lo += src1 + src2
6256 // dest_hi += carry1 + carry2
6257 // Z_R7 is destroyed !
6258 void MacroAssembler::add2_with_carry(Register dest_hi, Register dest_lo,
6259                                      Register src1, Register src2) {
6260   clear_reg(Z_R7);
6261   z_algr(dest_lo, src1);
6262   z_alcgr(dest_hi, Z_R7);
6263   z_algr(dest_lo, src2);
6264   z_alcgr(dest_hi, Z_R7);
6265 }
6266 
6267 // Multiply 64 bit by 64 bit first loop.
6268 void MacroAssembler::multiply_64_x_64_loop(Register x, Register xstart,
6269                                            Register x_xstart,
6270                                            Register y, Register y_idx,
6271                                            Register z,
6272                                            Register carry,
6273                                            Register product,
6274                                            Register idx, Register kdx) {
6275   // jlong carry, x[], y[], z[];
6276   // for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx--, kdx--) {
6277   //   huge_128 product = y[idx] * x[xstart] + carry;
6278   //   z[kdx] = (jlong)product;
6279   //   carry  = (jlong)(product >>> 64);
6280   // }
6281   // z[xstart] = carry;
6282 
6283   Label L_first_loop, L_first_loop_exit;
6284   Label L_one_x, L_one_y, L_multiply;
6285 
6286   z_aghi(xstart, -1);
6287   z_brl(L_one_x);   // Special case: length of x is 1.
6288 
6289   // Load next two integers of x.
6290   z_sllg(Z_R1_scratch, xstart, LogBytesPerInt);
6291   mem2reg_opt(x_xstart, Address(x, Z_R1_scratch, 0));
6292 
6293 
6294   bind(L_first_loop);
6295 
6296   z_aghi(idx, -1);
6297   z_brl(L_first_loop_exit);
6298   z_aghi(idx, -1);
6299   z_brl(L_one_y);
6300 
6301   // Load next two integers of y.
6302   z_sllg(Z_R1_scratch, idx, LogBytesPerInt);
6303   mem2reg_opt(y_idx, Address(y, Z_R1_scratch, 0));
6304 
6305 
6306   bind(L_multiply);
6307 
6308   Register multiplicand = product->successor();
6309   Register product_low = multiplicand;
6310 
6311   lgr_if_needed(multiplicand, x_xstart);
6312   z_mlgr(product, y_idx);     // multiplicand * y_idx -> product::multiplicand
6313   clear_reg(Z_R7);
6314   z_algr(product_low, carry); // Add carry to result.
6315   z_alcgr(product, Z_R7);     // Add carry of the last addition.
6316   add2reg(kdx, -2);
6317 
6318   // Store result.
6319   z_sllg(Z_R7, kdx, LogBytesPerInt);
6320   reg2mem_opt(product_low, Address(z, Z_R7, 0));
6321   lgr_if_needed(carry, product);
6322   z_bru(L_first_loop);
6323 
6324 
6325   bind(L_one_y); // Load one 32 bit portion of y as (0,value).
6326 
6327   clear_reg(y_idx);
6328   mem2reg_opt(y_idx, Address(y, (intptr_t) 0), false);
6329   z_bru(L_multiply);
6330 
6331 
6332   bind(L_one_x); // Load one 32 bit portion of x as (0,value).
6333 
6334   clear_reg(x_xstart);
6335   mem2reg_opt(x_xstart, Address(x, (intptr_t) 0), false);
6336   z_bru(L_first_loop);
6337 
6338   bind(L_first_loop_exit);
6339 }
6340 
6341 // Multiply 64 bit by 64 bit and add 128 bit.
6342 void MacroAssembler::multiply_add_128_x_128(Register x_xstart, Register y,
6343                                             Register z,
6344                                             Register yz_idx, Register idx,
6345                                             Register carry, Register product,
6346                                             int offset) {
6347   // huge_128 product = (y[idx] * x_xstart) + z[kdx] + carry;
6348   // z[kdx] = (jlong)product;
6349 
6350   Register multiplicand = product->successor();
6351   Register product_low = multiplicand;
6352 
6353   z_sllg(Z_R7, idx, LogBytesPerInt);
6354   mem2reg_opt(yz_idx, Address(y, Z_R7, offset));
6355 
6356   lgr_if_needed(multiplicand, x_xstart);
6357   z_mlgr(product, yz_idx); // multiplicand * yz_idx -> product::multiplicand
6358   mem2reg_opt(yz_idx, Address(z, Z_R7, offset));
6359 
6360   add2_with_carry(product, product_low, carry, yz_idx);
6361 
6362   z_sllg(Z_R7, idx, LogBytesPerInt);
6363   reg2mem_opt(product_low, Address(z, Z_R7, offset));
6364 
6365 }
6366 
6367 // Multiply 128 bit by 128 bit. Unrolled inner loop.
6368 void MacroAssembler::multiply_128_x_128_loop(Register x_xstart,
6369                                              Register y, Register z,
6370                                              Register yz_idx, Register idx,
6371                                              Register jdx,
6372                                              Register carry, Register product,
6373                                              Register carry2) {
6374   // jlong carry, x[], y[], z[];
6375   // int kdx = ystart+1;
6376   // for (int idx=ystart-2; idx >= 0; idx -= 2) { // Third loop
6377   //   huge_128 product = (y[idx+1] * x_xstart) + z[kdx+idx+1] + carry;
6378   //   z[kdx+idx+1] = (jlong)product;
6379   //   jlong carry2 = (jlong)(product >>> 64);
6380   //   product = (y[idx] * x_xstart) + z[kdx+idx] + carry2;
6381   //   z[kdx+idx] = (jlong)product;
6382   //   carry = (jlong)(product >>> 64);
6383   // }
6384   // idx += 2;
6385   // if (idx > 0) {
6386   //   product = (y[idx] * x_xstart) + z[kdx+idx] + carry;
6387   //   z[kdx+idx] = (jlong)product;
6388   //   carry = (jlong)(product >>> 64);
6389   // }
6390 
6391   Label L_third_loop, L_third_loop_exit, L_post_third_loop_done;
6392 
6393   // scale the index
6394   lgr_if_needed(jdx, idx);
6395   and_imm(jdx, 0xfffffffffffffffcL);
6396   rshift(jdx, 2);
6397 
6398 
6399   bind(L_third_loop);
6400 
6401   z_aghi(jdx, -1);
6402   z_brl(L_third_loop_exit);
6403   add2reg(idx, -4);
6404 
6405   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 8);
6406   lgr_if_needed(carry2, product);
6407 
6408   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry2, product, 0);
6409   lgr_if_needed(carry, product);
6410   z_bru(L_third_loop);
6411 
6412 
6413   bind(L_third_loop_exit);  // Handle any left-over operand parts.
6414 
6415   and_imm(idx, 0x3);
6416   z_brz(L_post_third_loop_done);
6417 
6418   Label L_check_1;
6419 
6420   z_aghi(idx, -2);
6421   z_brl(L_check_1);
6422 
6423   multiply_add_128_x_128(x_xstart, y, z, yz_idx, idx, carry, product, 0);
6424   lgr_if_needed(carry, product);
6425 
6426 
6427   bind(L_check_1);
6428 
6429   add2reg(idx, 0x2);
6430   and_imm(idx, 0x1);
6431   z_aghi(idx, -1);
6432   z_brl(L_post_third_loop_done);
6433 
6434   Register   multiplicand = product->successor();
6435   Register   product_low = multiplicand;
6436 
6437   z_sllg(Z_R7, idx, LogBytesPerInt);
6438   clear_reg(yz_idx);
6439   mem2reg_opt(yz_idx, Address(y, Z_R7, 0), false);
6440   lgr_if_needed(multiplicand, x_xstart);
6441   z_mlgr(product, yz_idx); // multiplicand * yz_idx -> product::multiplicand
6442   clear_reg(yz_idx);
6443   mem2reg_opt(yz_idx, Address(z, Z_R7, 0), false);
6444 
6445   add2_with_carry(product, product_low, yz_idx, carry);
6446 
6447   z_sllg(Z_R7, idx, LogBytesPerInt);
6448   reg2mem_opt(product_low, Address(z, Z_R7, 0), false);
6449   rshift(product_low, 32);
6450 
6451   lshift(product, 32);
6452   z_ogr(product_low, product);
6453   lgr_if_needed(carry, product_low);
6454 
6455   bind(L_post_third_loop_done);
6456 }
6457 
6458 void MacroAssembler::multiply_to_len(Register x, Register xlen,
6459                                      Register y, Register ylen,
6460                                      Register z,
6461                                      Register tmp1, Register tmp2,
6462                                      Register tmp3, Register tmp4,
6463                                      Register tmp5) {
6464   ShortBranchVerifier sbv(this);
6465 
6466   assert_different_registers(x, xlen, y, ylen, z,
6467                              tmp1, tmp2, tmp3, tmp4, tmp5, Z_R1_scratch, Z_R7);
6468   assert_different_registers(x, xlen, y, ylen, z,
6469                              tmp1, tmp2, tmp3, tmp4, tmp5, Z_R8);
6470 
6471   z_stmg(Z_R7, Z_R13, _z_abi(gpr7), Z_SP);
6472 
6473   // In openJdk, we store the argument as 32-bit value to slot.
6474   Address zlen(Z_SP, _z_abi(remaining_cargs));  // Int in long on big endian.
6475 
6476   const Register idx = tmp1;
6477   const Register kdx = tmp2;
6478   const Register xstart = tmp3;
6479 
6480   const Register y_idx = tmp4;
6481   const Register carry = tmp5;
6482   const Register product  = Z_R0_scratch;
6483   const Register x_xstart = Z_R8;
6484 
6485   // First Loop.
6486   //
6487   //   final static long LONG_MASK = 0xffffffffL;
6488   //   int xstart = xlen - 1;
6489   //   int ystart = ylen - 1;
6490   //   long carry = 0;
6491   //   for (int idx=ystart, kdx=ystart+1+xstart; idx >= 0; idx-, kdx--) {
6492   //     long product = (y[idx] & LONG_MASK) * (x[xstart] & LONG_MASK) + carry;
6493   //     z[kdx] = (int)product;
6494   //     carry = product >>> 32;
6495   //   }
6496   //   z[xstart] = (int)carry;
6497   //
6498 
6499   lgr_if_needed(idx, ylen);  // idx = ylen
6500   z_llgf(kdx, zlen);         // C2 does not respect int to long conversion for stub calls, thus load zero-extended.
6501   clear_reg(carry);          // carry = 0
6502 
6503   Label L_done;
6504 
6505   lgr_if_needed(xstart, xlen);
6506   z_aghi(xstart, -1);
6507   z_brl(L_done);
6508 
6509   multiply_64_x_64_loop(x, xstart, x_xstart, y, y_idx, z, carry, product, idx, kdx);
6510 
6511   NearLabel L_second_loop;
6512   compare64_and_branch(kdx, RegisterOrConstant((intptr_t) 0), bcondEqual, L_second_loop);
6513 
6514   NearLabel L_carry;
6515   z_aghi(kdx, -1);
6516   z_brz(L_carry);
6517 
6518   // Store lower 32 bits of carry.
6519   z_sllg(Z_R1_scratch, kdx, LogBytesPerInt);
6520   reg2mem_opt(carry, Address(z, Z_R1_scratch, 0), false);
6521   rshift(carry, 32);
6522   z_aghi(kdx, -1);
6523 
6524 
6525   bind(L_carry);
6526 
6527   // Store upper 32 bits of carry.
6528   z_sllg(Z_R1_scratch, kdx, LogBytesPerInt);
6529   reg2mem_opt(carry, Address(z, Z_R1_scratch, 0), false);
6530 
6531   // Second and third (nested) loops.
6532   //
6533   // for (int i = xstart-1; i >= 0; i--) { // Second loop
6534   //   carry = 0;
6535   //   for (int jdx=ystart, k=ystart+1+i; jdx >= 0; jdx--, k--) { // Third loop
6536   //     long product = (y[jdx] & LONG_MASK) * (x[i] & LONG_MASK) +
6537   //                    (z[k] & LONG_MASK) + carry;
6538   //     z[k] = (int)product;
6539   //     carry = product >>> 32;
6540   //   }
6541   //   z[i] = (int)carry;
6542   // }
6543   //
6544   // i = xlen, j = tmp1, k = tmp2, carry = tmp5, x[i] = rdx
6545 
6546   const Register jdx = tmp1;
6547 
6548   bind(L_second_loop);
6549 
6550   clear_reg(carry);           // carry = 0;
6551   lgr_if_needed(jdx, ylen);   // j = ystart+1
6552 
6553   z_aghi(xstart, -1);         // i = xstart-1;
6554   z_brl(L_done);
6555 
6556   // Use free slots in the current stackframe instead of push/pop.
6557   Address zsave(Z_SP, _z_abi(carg_1));
6558   reg2mem_opt(z, zsave);
6559 
6560 
6561   Label L_last_x;
6562 
6563   z_sllg(Z_R1_scratch, xstart, LogBytesPerInt);
6564   load_address(z, Address(z, Z_R1_scratch, 4)); // z = z + k - j
6565   z_aghi(xstart, -1);                           // i = xstart-1;
6566   z_brl(L_last_x);
6567 
6568   z_sllg(Z_R1_scratch, xstart, LogBytesPerInt);
6569   mem2reg_opt(x_xstart, Address(x, Z_R1_scratch, 0));
6570 
6571 
6572   Label L_third_loop_prologue;
6573 
6574   bind(L_third_loop_prologue);
6575 
6576   Address xsave(Z_SP, _z_abi(carg_2));
6577   Address xlensave(Z_SP, _z_abi(carg_3));
6578   Address ylensave(Z_SP, _z_abi(carg_4));
6579 
6580   reg2mem_opt(x, xsave);
6581   reg2mem_opt(xstart, xlensave);
6582   reg2mem_opt(ylen, ylensave);
6583 
6584 
6585   multiply_128_x_128_loop(x_xstart, y, z, y_idx, jdx, ylen, carry, product, x);
6586 
6587   mem2reg_opt(z, zsave);
6588   mem2reg_opt(x, xsave);
6589   mem2reg_opt(xlen, xlensave);   // This is the decrement of the loop counter!
6590   mem2reg_opt(ylen, ylensave);
6591 
6592   add2reg(tmp3, 1, xlen);
6593   z_sllg(Z_R1_scratch, tmp3, LogBytesPerInt);
6594   reg2mem_opt(carry, Address(z, Z_R1_scratch, 0), false);
6595   z_aghi(tmp3, -1);
6596   z_brl(L_done);
6597 
6598   rshift(carry, 32);
6599   z_sllg(Z_R1_scratch, tmp3, LogBytesPerInt);
6600   reg2mem_opt(carry, Address(z, Z_R1_scratch, 0), false);
6601   z_bru(L_second_loop);
6602 
6603   // Next infrequent code is moved outside loops.
6604   bind(L_last_x);
6605 
6606   clear_reg(x_xstart);
6607   mem2reg_opt(x_xstart, Address(x, (intptr_t) 0), false);
6608   z_bru(L_third_loop_prologue);
6609 
6610   bind(L_done);
6611 
6612   z_lmg(Z_R7, Z_R13, _z_abi(gpr7), Z_SP);
6613 }
6614 
6615 #ifndef PRODUCT
6616 // Assert if CC indicates "not equal" (check_equal==true) or "equal" (check_equal==false).
6617 void MacroAssembler::asm_assert(bool check_equal, const char *msg, int id) {
6618   Label ok;
6619   if (check_equal) {
6620     z_bre(ok);
6621   } else {
6622     z_brne(ok);
6623   }
6624   stop(msg, id);
6625   bind(ok);
6626 }
6627 
6628 // Assert if CC indicates "low".
6629 void MacroAssembler::asm_assert_low(const char *msg, int id) {
6630   Label ok;
6631   z_brnl(ok);
6632   stop(msg, id);
6633   bind(ok);
6634 }
6635 
6636 // Assert if CC indicates "high".
6637 void MacroAssembler::asm_assert_high(const char *msg, int id) {
6638   Label ok;
6639   z_brnh(ok);
6640   stop(msg, id);
6641   bind(ok);
6642 }
6643 
6644 // Assert if CC indicates "not equal" (check_equal==true) or "equal" (check_equal==false)
6645 // generate non-relocatable code.
6646 void MacroAssembler::asm_assert_static(bool check_equal, const char *msg, int id) {
6647   Label ok;
6648   if (check_equal) { z_bre(ok); }
6649   else             { z_brne(ok); }
6650   stop_static(msg, id);
6651   bind(ok);
6652 }
6653 
6654 void MacroAssembler::asm_assert_mems_zero(bool check_equal, bool allow_relocation, int size, int64_t mem_offset,
6655                                           Register mem_base, const char* msg, int id) {
6656   switch (size) {
6657     case 4:
6658       load_and_test_int(Z_R0, Address(mem_base, mem_offset));
6659       break;
6660     case 8:
6661       load_and_test_long(Z_R0,  Address(mem_base, mem_offset));
6662       break;
6663     default:
6664       ShouldNotReachHere();
6665   }
6666   if (allow_relocation) { asm_assert(check_equal, msg, id); }
6667   else                  { asm_assert_static(check_equal, msg, id); }
6668 }
6669 
6670 // Check the condition
6671 //   expected_size == FP - SP
6672 // after transformation:
6673 //   expected_size - FP + SP == 0
6674 // Destroys Register expected_size if no tmp register is passed.
6675 void MacroAssembler::asm_assert_frame_size(Register expected_size, Register tmp, const char* msg, int id) {
6676   if (tmp == noreg) {
6677     tmp = expected_size;
6678   } else {
6679     if (tmp != expected_size) {
6680       z_lgr(tmp, expected_size);
6681     }
6682     z_algr(tmp, Z_SP);
6683     z_slg(tmp, 0, Z_R0, Z_SP);
6684     asm_assert_eq(msg, id);
6685   }
6686 }
6687 #endif // !PRODUCT
6688 
6689 void MacroAssembler::verify_thread() {
6690   if (VerifyThread) {
6691     unimplemented("", 117);
6692   }
6693 }
6694 
6695 // Plausibility check for oops.
6696 void MacroAssembler::verify_oop(Register oop, const char* msg) {
6697   if (!VerifyOops) return;
6698 
6699   BLOCK_COMMENT("verify_oop {");
6700   Register tmp = Z_R0;
6701   unsigned int nbytes_save = 5*BytesPerWord;
6702   address entry = StubRoutines::verify_oop_subroutine_entry_address();
6703 
6704   save_return_pc();
6705   push_frame_abi160(nbytes_save);
6706   z_stmg(Z_R1, Z_R5, frame::z_abi_160_size, Z_SP);
6707 
6708   z_lgr(Z_ARG2, oop);
6709   load_const(Z_ARG1, (address) msg);
6710   load_const(Z_R1, entry);
6711   z_lg(Z_R1, 0, Z_R1);
6712   call_c(Z_R1);
6713 
6714   z_lmg(Z_R1, Z_R5, frame::z_abi_160_size, Z_SP);
6715   pop_frame();
6716   restore_return_pc();
6717 
6718   BLOCK_COMMENT("} verify_oop ");
6719 }
6720 
6721 const char* MacroAssembler::stop_types[] = {
6722   "stop",
6723   "untested",
6724   "unimplemented",
6725   "shouldnotreachhere"
6726 };
6727 
6728 static void stop_on_request(const char* tp, const char* msg) {
6729   tty->print("Z assembly code requires stop: (%s) %s\n", tp, msg);
6730   guarantee(false, "Z assembly code requires stop: %s", msg);
6731 }
6732 
6733 void MacroAssembler::stop(int type, const char* msg, int id) {
6734   BLOCK_COMMENT(err_msg("stop: %s {", msg));
6735 
6736   // Setup arguments.
6737   load_const(Z_ARG1, (void*) stop_types[type%stop_end]);
6738   load_const(Z_ARG2, (void*) msg);
6739   get_PC(Z_R14);     // Following code pushes a frame without entering a new function. Use current pc as return address.
6740   save_return_pc();  // Saves return pc Z_R14.
6741   push_frame_abi160(0);
6742   call_VM_leaf(CAST_FROM_FN_PTR(address, stop_on_request), Z_ARG1, Z_ARG2);
6743   // The plain disassembler does not recognize illtrap. It instead displays
6744   // a 32-bit value. Issueing two illtraps assures the disassembler finds
6745   // the proper beginning of the next instruction.
6746   z_illtrap(); // Illegal instruction.
6747   z_illtrap(); // Illegal instruction.
6748 
6749   BLOCK_COMMENT(" } stop");
6750 }
6751 
6752 // Special version of stop() for code size reduction.
6753 // Reuses the previously generated call sequence, if any.
6754 // Generates the call sequence on its own, if necessary.
6755 // Note: This code will work only in non-relocatable code!
6756 //       The relative address of the data elements (arg1, arg2) must not change.
6757 //       The reentry point must not move relative to it's users. This prerequisite
6758 //       should be given for "hand-written" code, if all chain calls are in the same code blob.
6759 //       Generated code must not undergo any transformation, e.g. ShortenBranches, to be safe.
6760 address MacroAssembler::stop_chain(address reentry, int type, const char* msg, int id, bool allow_relocation) {
6761   BLOCK_COMMENT(err_msg("stop_chain(%s,%s): %s {", reentry==NULL?"init":"cont", allow_relocation?"reloc ":"static", msg));
6762 
6763   // Setup arguments.
6764   if (allow_relocation) {
6765     // Relocatable version (for comparison purposes). Remove after some time.
6766     load_const(Z_ARG1, (void*) stop_types[type%stop_end]);
6767     load_const(Z_ARG2, (void*) msg);
6768   } else {
6769     load_absolute_address(Z_ARG1, (address)stop_types[type%stop_end]);
6770     load_absolute_address(Z_ARG2, (address)msg);
6771   }
6772   if ((reentry != NULL) && RelAddr::is_in_range_of_RelAddr16(reentry, pc())) {
6773     BLOCK_COMMENT("branch to reentry point:");
6774     z_brc(bcondAlways, reentry);
6775   } else {
6776     BLOCK_COMMENT("reentry point:");
6777     reentry = pc();      // Re-entry point for subsequent stop calls.
6778     save_return_pc();    // Saves return pc Z_R14.
6779     push_frame_abi160(0);
6780     if (allow_relocation) {
6781       reentry = NULL;    // Prevent reentry if code relocation is allowed.
6782       call_VM_leaf(CAST_FROM_FN_PTR(address, stop_on_request), Z_ARG1, Z_ARG2);
6783     } else {
6784       call_VM_leaf_static(CAST_FROM_FN_PTR(address, stop_on_request), Z_ARG1, Z_ARG2);
6785     }
6786     z_illtrap(); // Illegal instruction as emergency stop, should the above call return.
6787   }
6788   BLOCK_COMMENT(" } stop_chain");
6789 
6790   return reentry;
6791 }
6792 
6793 // Special version of stop() for code size reduction.
6794 // Assumes constant relative addresses for data and runtime call.
6795 void MacroAssembler::stop_static(int type, const char* msg, int id) {
6796   stop_chain(NULL, type, msg, id, false);
6797 }
6798 
6799 void MacroAssembler::stop_subroutine() {
6800   unimplemented("stop_subroutine", 710);
6801 }
6802 
6803 // Prints msg to stdout from within generated code..
6804 void MacroAssembler::warn(const char* msg) {
6805   RegisterSaver::save_live_registers(this, RegisterSaver::all_registers, Z_R14);
6806   load_absolute_address(Z_R1, (address) warning);
6807   load_absolute_address(Z_ARG1, (address) msg);
6808   (void) call(Z_R1);
6809   RegisterSaver::restore_live_registers(this, RegisterSaver::all_registers);
6810 }
6811 
6812 #ifndef PRODUCT
6813 
6814 // Write pattern 0x0101010101010101 in region [low-before, high+after].
6815 void MacroAssembler::zap_from_to(Register low, Register high, Register val, Register addr, int before, int after) {
6816   if (!ZapEmptyStackFields) return;
6817   BLOCK_COMMENT("zap memory region {");
6818   load_const_optimized(val, 0x0101010101010101);
6819   int size = before + after;
6820   if (low == high && size < 5 && size > 0) {
6821     int offset = -before*BytesPerWord;
6822     for (int i = 0; i < size; ++i) {
6823       z_stg(val, Address(low, offset));
6824       offset +=(1*BytesPerWord);
6825     }
6826   } else {
6827     add2reg(addr, -before*BytesPerWord, low);
6828     if (after) {
6829 #ifdef ASSERT
6830       jlong check = after * BytesPerWord;
6831       assert(Immediate::is_simm32(check) && Immediate::is_simm32(-check), "value not encodable !");
6832 #endif
6833       add2reg(high, after * BytesPerWord);
6834     }
6835     NearLabel loop;
6836     bind(loop);
6837     z_stg(val, Address(addr));
6838     add2reg(addr, 8);
6839     compare64_and_branch(addr, high, bcondNotHigh, loop);
6840     if (after) {
6841       add2reg(high, -after * BytesPerWord);
6842     }
6843   }
6844   BLOCK_COMMENT("} zap memory region");
6845 }
6846 #endif // !PRODUCT
6847 
6848 SkipIfEqual::SkipIfEqual(MacroAssembler* masm, const bool* flag_addr, bool value, Register _rscratch) {
6849   _masm = masm;
6850   _masm->load_absolute_address(_rscratch, (address)flag_addr);
6851   _masm->load_and_test_int(_rscratch, Address(_rscratch));
6852   if (value) {
6853     _masm->z_brne(_label); // Skip if true, i.e. != 0.
6854   } else {
6855     _masm->z_bre(_label);  // Skip if false, i.e. == 0.
6856   }
6857 }
6858 
6859 SkipIfEqual::~SkipIfEqual() {
6860   _masm->bind(_label);
6861 }