1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
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23 */
24
25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
27
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
30
31 class VM_Version: public Abstract_VM_Version {
32 protected:
33 enum Feature_Flag {
34 v8_instructions = 0,
35 hardware_mul32 = 1,
36 hardware_div32 = 2,
37 hardware_fsmuld = 3,
38 hardware_popc = 4,
39 v9_instructions = 5,
40 vis1_instructions = 6,
41 vis2_instructions = 7,
42 sun4v_instructions = 8,
43 blk_init_instructions = 9,
44 fmaf_instructions = 10,
45 fmau_instructions = 11,
46 vis3_instructions = 12,
47 cbcond_instructions = 13,
48 sparc64_family = 14,
49 M_family = 15,
50 T_family = 16,
51 T1_model = 17
52 };
53
54 enum Feature_Flag_Set {
55 unknown_m = 0,
56 all_features_m = -1,
57
58 v8_instructions_m = 1 << v8_instructions,
59 hardware_mul32_m = 1 << hardware_mul32,
60 hardware_div32_m = 1 << hardware_div32,
61 hardware_fsmuld_m = 1 << hardware_fsmuld,
62 hardware_popc_m = 1 << hardware_popc,
63 v9_instructions_m = 1 << v9_instructions,
64 vis1_instructions_m = 1 << vis1_instructions,
65 vis2_instructions_m = 1 << vis2_instructions,
66 sun4v_m = 1 << sun4v_instructions,
67 blk_init_instructions_m = 1 << blk_init_instructions,
68 fmaf_instructions_m = 1 << fmaf_instructions,
69 fmau_instructions_m = 1 << fmau_instructions,
70 vis3_instructions_m = 1 << vis3_instructions,
71 cbcond_instructions_m = 1 << cbcond_instructions,
72 sparc64_family_m = 1 << sparc64_family,
73 M_family_m = 1 << M_family,
74 T_family_m = 1 << T_family,
75 T1_model_m = 1 << T1_model,
76
77 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
78 generic_v9_m = generic_v8_m | v9_instructions_m,
79 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
80
81 // Temporary until we have something more accurate
82 niagara1_unique_m = sun4v_m,
83 niagara1_m = generic_v9_m | niagara1_unique_m
84 };
85
86 static int _features;
87 static const char* _features_str;
88
89 static void print_features();
90 static int determine_features();
91 static int platform_features(int features);
92
93 // Returns true if the platform is in the niagara line (T series)
94 static bool is_M_family(int features) { return (features & M_family_m) != 0; }
95 static bool is_T_family(int features) { return (features & T_family_m) != 0; }
96 static bool is_niagara() { return is_T_family(_features); }
97 #ifdef ASSERT
98 static bool is_niagara(int features) {
99 // 'sun4v_m' may be defined on both Sun/Oracle Sparc CPUs as well as
100 // on Fujitsu Sparc64 CPUs, but only Sun/Oracle Sparcs can be 'niagaras'.
101 return (features & sun4v_m) != 0 && (features & sparc64_family_m) == 0;
102 }
103 #endif
104
105 // Returns true if it is niagara1 (T1).
106 static bool is_T1_model(int features) { return is_T_family(features) && ((features & T1_model_m) != 0); }
107
108 static int maximum_niagara1_processor_count() { return 32; }
109
110 public:
111 // Initialization
112 static void initialize();
113
114 // Instruction support
115 static bool has_v8() { return (_features & v8_instructions_m) != 0; }
116 static bool has_v9() { return (_features & v9_instructions_m) != 0; }
117 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; }
118 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; }
119 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; }
120 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }
121 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }
122 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
123 static bool has_vis3() { return (_features & vis3_instructions_m) != 0; }
124 static bool has_blk_init() { return (_features & blk_init_instructions_m) != 0; }
125 static bool has_cbcond() { return (_features & cbcond_instructions_m) != 0; }
126
127 static bool supports_compare_and_exchange()
128 { return has_v9(); }
129
130 // Returns true if the platform is in the niagara line (T series)
131 // and newer than the niagara1.
132 static bool is_niagara_plus() { return is_T_family(_features) && !is_T1_model(_features); }
133
134 static bool is_M_series() { return is_M_family(_features); }
135 static bool is_T4() { return is_T_family(_features) && has_cbcond(); }
136
137 // Fujitsu SPARC64
138 static bool is_sparc64() { return (_features & sparc64_family_m) != 0; }
139
140 static bool is_sun4v() { return (_features & sun4v_m) != 0; }
141 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m && !is_sun4v() && !is_sparc64(); }
142
143 static bool has_fast_fxtof() { return is_niagara() || is_sparc64() || has_v9() && !is_ultra3(); }
144 static bool has_fast_idiv() { return is_niagara_plus() || is_sparc64(); }
145
146 // T4 and newer Sparc have fast RDPC instruction.
147 static bool has_fast_rdpc() { return is_T4(); }
148
149 // On T4 and newer Sparc BIS to the beginning of cache line always zeros it.
150 static bool has_block_zeroing() { return has_blk_init() && is_T4(); }
151
152 static const char* cpu_features() { return _features_str; }
153
154 static intx prefetch_data_size() {
155 return is_T4() ? 32 : 64; // default prefetch block size on sparc
156 }
157
158 // Prefetch
159 static intx prefetch_copy_interval_in_bytes() {
160 intx interval = PrefetchCopyIntervalInBytes;
161 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
162 }
163 static intx prefetch_scan_interval_in_bytes() {
164 intx interval = PrefetchScanIntervalInBytes;
165 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
166 }
167 static intx prefetch_fields_ahead() {
168 intx count = PrefetchFieldsAhead;
169 return count >= 0 ? count : (is_ultra3() ? 1 : 0);
170 }
171
172 static intx allocate_prefetch_distance() {
173 // This method should be called before allocate_prefetch_style().
174 intx count = AllocatePrefetchDistance;
175 if (count < 0) { // default is not defined ?
176 count = 512;
177 }
178 return count;
179 }
180 static intx allocate_prefetch_style() {
181 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
182 // Return 0 if AllocatePrefetchDistance was not defined.
183 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
184 }
185
186 // Assembler testing
187 static void allow_all();
188 static void revert();
189
190 // Override the Abstract_VM_Version implementation.
191 static uint page_size_count() { return is_sun4v() ? 4 : 2; }
192
193 // Calculates the number of parallel threads
194 static unsigned int calc_parallel_worker_threads();
195 };
196
197 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP