1 /* 2 * Copyright (c) 2003, 2013, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "asm/macroAssembler.inline.hpp" 27 #include "code/debugInfoRec.hpp" 28 #include "code/icBuffer.hpp" 29 #include "code/vtableStubs.hpp" 30 #include "interpreter/interpreter.hpp" 31 #include "oops/compiledICHolder.hpp" 32 #include "prims/jvmtiRedefineClassesTrace.hpp" 33 #include "runtime/sharedRuntime.hpp" 34 #include "runtime/vframeArray.hpp" 35 #include "vmreg_sparc.inline.hpp" 36 #ifdef COMPILER1 37 #include "c1/c1_Runtime1.hpp" 38 #endif 39 #ifdef COMPILER2 40 #include "opto/runtime.hpp" 41 #endif 42 #ifdef SHARK 43 #include "compiler/compileBroker.hpp" 44 #include "shark/sharkCompiler.hpp" 45 #endif 46 47 #define __ masm-> 48 49 50 class RegisterSaver { 51 52 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O. 53 // The Oregs are problematic. In the 32bit build the compiler can 54 // have O registers live with 64 bit quantities. A window save will 55 // cut the heads off of the registers. We have to do a very extensive 56 // stack dance to save and restore these properly. 57 58 // Note that the Oregs problem only exists if we block at either a polling 59 // page exception a compiled code safepoint that was not originally a call 60 // or deoptimize following one of these kinds of safepoints. 61 62 // Lots of registers to save. For all builds, a window save will preserve 63 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit 64 // builds a window-save will preserve the %o registers. In the LION build 65 // we need to save the 64-bit %o registers which requires we save them 66 // before the window-save (as then they become %i registers and get their 67 // heads chopped off on interrupt). We have to save some %g registers here 68 // as well. 69 enum { 70 // This frame's save area. Includes extra space for the native call: 71 // vararg's layout space and the like. Briefly holds the caller's 72 // register save area. 73 call_args_area = frame::register_save_words_sp_offset + 74 frame::memory_parameter_word_sp_offset*wordSize, 75 // Make sure save locations are always 8 byte aligned. 76 // can't use round_to because it doesn't produce compile time constant 77 start_of_extra_save_area = ((call_args_area + 7) & ~7), 78 g1_offset = start_of_extra_save_area, // g-regs needing saving 79 g3_offset = g1_offset+8, 80 g4_offset = g3_offset+8, 81 g5_offset = g4_offset+8, 82 o0_offset = g5_offset+8, 83 o1_offset = o0_offset+8, 84 o2_offset = o1_offset+8, 85 o3_offset = o2_offset+8, 86 o4_offset = o3_offset+8, 87 o5_offset = o4_offset+8, 88 start_of_flags_save_area = o5_offset+8, 89 ccr_offset = start_of_flags_save_area, 90 fsr_offset = ccr_offset + 8, 91 d00_offset = fsr_offset+8, // Start of float save area 92 register_save_size = d00_offset+8*32 93 }; 94 95 96 public: 97 98 static int Oexception_offset() { return o0_offset; }; 99 static int G3_offset() { return g3_offset; }; 100 static int G5_offset() { return g5_offset; }; 101 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words); 102 static void restore_live_registers(MacroAssembler* masm); 103 104 // During deoptimization only the result register need to be restored 105 // all the other values have already been extracted. 106 107 static void restore_result_registers(MacroAssembler* masm); 108 }; 109 110 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) { 111 // Record volatile registers as callee-save values in an OopMap so their save locations will be 112 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for 113 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers 114 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame 115 // (as the stub's I's) when the runtime routine called by the stub creates its frame. 116 int i; 117 // Always make the frame size 16 byte aligned. 118 int frame_size = round_to(additional_frame_words + register_save_size, 16); 119 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words 120 int frame_size_in_slots = frame_size / sizeof(jint); 121 // CodeBlob frame size is in words. 122 *total_frame_words = frame_size / wordSize; 123 // OopMap* map = new OopMap(*total_frame_words, 0); 124 OopMap* map = new OopMap(frame_size_in_slots, 0); 125 126 #if !defined(_LP64) 127 128 // Save 64-bit O registers; they will get their heads chopped off on a 'save'. 129 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); 130 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); 131 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); 132 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); 133 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); 134 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); 135 #endif /* _LP64 */ 136 137 __ save(SP, -frame_size, SP); 138 139 #ifndef _LP64 140 // Reload the 64 bit Oregs. Although they are now Iregs we load them 141 // to Oregs here to avoid interrupts cutting off their heads 142 143 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); 144 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); 145 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); 146 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); 147 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); 148 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); 149 150 __ stx(O0, SP, o0_offset+STACK_BIAS); 151 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg()); 152 153 __ stx(O1, SP, o1_offset+STACK_BIAS); 154 155 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg()); 156 157 __ stx(O2, SP, o2_offset+STACK_BIAS); 158 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg()); 159 160 __ stx(O3, SP, o3_offset+STACK_BIAS); 161 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg()); 162 163 __ stx(O4, SP, o4_offset+STACK_BIAS); 164 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg()); 165 166 __ stx(O5, SP, o5_offset+STACK_BIAS); 167 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg()); 168 #endif /* _LP64 */ 169 170 171 #ifdef _LP64 172 int debug_offset = 0; 173 #else 174 int debug_offset = 4; 175 #endif 176 // Save the G's 177 __ stx(G1, SP, g1_offset+STACK_BIAS); 178 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg()); 179 180 __ stx(G3, SP, g3_offset+STACK_BIAS); 181 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg()); 182 183 __ stx(G4, SP, g4_offset+STACK_BIAS); 184 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg()); 185 186 __ stx(G5, SP, g5_offset+STACK_BIAS); 187 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg()); 188 189 // This is really a waste but we'll keep things as they were for now 190 if (true) { 191 #ifndef _LP64 192 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next()); 193 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next()); 194 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next()); 195 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next()); 196 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next()); 197 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next()); 198 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next()); 199 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next()); 200 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next()); 201 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next()); 202 #endif /* _LP64 */ 203 } 204 205 206 // Save the flags 207 __ rdccr( G5 ); 208 __ stx(G5, SP, ccr_offset+STACK_BIAS); 209 __ stxfsr(SP, fsr_offset+STACK_BIAS); 210 211 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles) 212 int offset = d00_offset; 213 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { 214 FloatRegister f = as_FloatRegister(i); 215 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS); 216 // Record as callee saved both halves of double registers (2 float registers). 217 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg()); 218 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next()); 219 offset += sizeof(double); 220 } 221 222 // And we're done. 223 224 return map; 225 } 226 227 228 // Pop the current frame and restore all the registers that we 229 // saved. 230 void RegisterSaver::restore_live_registers(MacroAssembler* masm) { 231 232 // Restore all the FP registers 233 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) { 234 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i)); 235 } 236 237 __ ldx(SP, ccr_offset+STACK_BIAS, G1); 238 __ wrccr (G1) ; 239 240 // Restore the G's 241 // Note that G2 (AKA GThread) must be saved and restored separately. 242 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr. 243 244 __ ldx(SP, g1_offset+STACK_BIAS, G1); 245 __ ldx(SP, g3_offset+STACK_BIAS, G3); 246 __ ldx(SP, g4_offset+STACK_BIAS, G4); 247 __ ldx(SP, g5_offset+STACK_BIAS, G5); 248 249 250 #if !defined(_LP64) 251 // Restore the 64-bit O's. 252 __ ldx(SP, o0_offset+STACK_BIAS, O0); 253 __ ldx(SP, o1_offset+STACK_BIAS, O1); 254 __ ldx(SP, o2_offset+STACK_BIAS, O2); 255 __ ldx(SP, o3_offset+STACK_BIAS, O3); 256 __ ldx(SP, o4_offset+STACK_BIAS, O4); 257 __ ldx(SP, o5_offset+STACK_BIAS, O5); 258 259 // And temporarily place them in TLS 260 261 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); 262 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); 263 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8); 264 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8); 265 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8); 266 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8); 267 #endif /* _LP64 */ 268 269 // Restore flags 270 271 __ ldxfsr(SP, fsr_offset+STACK_BIAS); 272 273 __ restore(); 274 275 #if !defined(_LP64) 276 // Now reload the 64bit Oregs after we've restore the window. 277 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); 278 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); 279 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2); 280 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3); 281 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4); 282 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5); 283 #endif /* _LP64 */ 284 285 } 286 287 // Pop the current frame and restore the registers that might be holding 288 // a result. 289 void RegisterSaver::restore_result_registers(MacroAssembler* masm) { 290 291 #if !defined(_LP64) 292 // 32bit build returns longs in G1 293 __ ldx(SP, g1_offset+STACK_BIAS, G1); 294 295 // Retrieve the 64-bit O's. 296 __ ldx(SP, o0_offset+STACK_BIAS, O0); 297 __ ldx(SP, o1_offset+STACK_BIAS, O1); 298 // and save to TLS 299 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8); 300 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8); 301 #endif /* _LP64 */ 302 303 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0)); 304 305 __ restore(); 306 307 #if !defined(_LP64) 308 // Now reload the 64bit Oregs after we've restore the window. 309 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0); 310 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1); 311 #endif /* _LP64 */ 312 313 } 314 315 // Is vector's size (in bytes) bigger than a size saved by default? 316 // 8 bytes FP registers are saved by default on SPARC. 317 bool SharedRuntime::is_wide_vector(int size) { 318 // Note, MaxVectorSize == 8 on SPARC. 319 assert(size <= 8, err_msg_res("%d bytes vectors are not supported", size)); 320 return size > 8; 321 } 322 323 // The java_calling_convention describes stack locations as ideal slots on 324 // a frame with no abi restrictions. Since we must observe abi restrictions 325 // (like the placement of the register window) the slots must be biased by 326 // the following value. 327 static int reg2offset(VMReg r) { 328 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 329 } 330 331 static VMRegPair reg64_to_VMRegPair(Register r) { 332 VMRegPair ret; 333 if (wordSize == 8) { 334 ret.set2(r->as_VMReg()); 335 } else { 336 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg()); 337 } 338 return ret; 339 } 340 341 // --------------------------------------------------------------------------- 342 // Read the array of BasicTypes from a signature, and compute where the 343 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size) 344 // quantities. Values less than VMRegImpl::stack0 are registers, those above 345 // refer to 4-byte stack slots. All stack slots are based off of the window 346 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window, 347 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register 348 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit 349 // integer registers. Values 64-95 are the (32-bit only) float registers. 350 // Each 32-bit quantity is given its own number, so the integer registers 351 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is 352 // an O0-low and an O0-high. Essentially, all int register numbers are doubled. 353 354 // Register results are passed in O0-O5, for outgoing call arguments. To 355 // convert to incoming arguments, convert all O's to I's. The regs array 356 // refer to the low and hi 32-bit words of 64-bit registers or stack slots. 357 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a 358 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was 359 // passed (used as a placeholder for the other half of longs and doubles in 360 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is 361 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention). 362 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first() 363 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the 364 // same VMRegPair. 365 366 // Note: the INPUTS in sig_bt are in units of Java argument words, which are 367 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit 368 // units regardless of build. 369 370 371 // --------------------------------------------------------------------------- 372 // The compiled Java calling convention. The Java convention always passes 373 // 64-bit values in adjacent aligned locations (either registers or stack), 374 // floats in float registers and doubles in aligned float pairs. There is 375 // no backing varargs store for values in registers. 376 // In the 32-bit build, longs are passed on the stack (cannot be 377 // passed in I's, because longs in I's get their heads chopped off at 378 // interrupt). 379 int SharedRuntime::java_calling_convention(const BasicType *sig_bt, 380 VMRegPair *regs, 381 int total_args_passed, 382 int is_outgoing) { 383 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers"); 384 385 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM; 386 const int flt_reg_max = 8; 387 388 int int_reg = 0; 389 int flt_reg = 0; 390 int slot = 0; 391 392 for (int i = 0; i < total_args_passed; i++) { 393 switch (sig_bt[i]) { 394 case T_INT: 395 case T_SHORT: 396 case T_CHAR: 397 case T_BYTE: 398 case T_BOOLEAN: 399 #ifndef _LP64 400 case T_OBJECT: 401 case T_ARRAY: 402 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address 403 #endif // _LP64 404 if (int_reg < int_reg_max) { 405 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); 406 regs[i].set1(r->as_VMReg()); 407 } else { 408 regs[i].set1(VMRegImpl::stack2reg(slot++)); 409 } 410 break; 411 412 #ifdef _LP64 413 case T_LONG: 414 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); 415 // fall-through 416 case T_OBJECT: 417 case T_ARRAY: 418 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address 419 if (int_reg < int_reg_max) { 420 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++); 421 regs[i].set2(r->as_VMReg()); 422 } else { 423 slot = round_to(slot, 2); // align 424 regs[i].set2(VMRegImpl::stack2reg(slot)); 425 slot += 2; 426 } 427 break; 428 #else 429 case T_LONG: 430 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half"); 431 // On 32-bit SPARC put longs always on the stack to keep the pressure off 432 // integer argument registers. They should be used for oops. 433 slot = round_to(slot, 2); // align 434 regs[i].set2(VMRegImpl::stack2reg(slot)); 435 slot += 2; 436 #endif 437 break; 438 439 case T_FLOAT: 440 if (flt_reg < flt_reg_max) { 441 FloatRegister r = as_FloatRegister(flt_reg++); 442 regs[i].set1(r->as_VMReg()); 443 } else { 444 regs[i].set1(VMRegImpl::stack2reg(slot++)); 445 } 446 break; 447 448 case T_DOUBLE: 449 assert(sig_bt[i+1] == T_VOID, "expecting half"); 450 if (round_to(flt_reg, 2) + 1 < flt_reg_max) { 451 flt_reg = round_to(flt_reg, 2); // align 452 FloatRegister r = as_FloatRegister(flt_reg); 453 regs[i].set2(r->as_VMReg()); 454 flt_reg += 2; 455 } else { 456 slot = round_to(slot, 2); // align 457 regs[i].set2(VMRegImpl::stack2reg(slot)); 458 slot += 2; 459 } 460 break; 461 462 case T_VOID: 463 regs[i].set_bad(); // Halves of longs & doubles 464 break; 465 466 default: 467 fatal(err_msg_res("unknown basic type %d", sig_bt[i])); 468 break; 469 } 470 } 471 472 // retun the amount of stack space these arguments will need. 473 return slot; 474 } 475 476 // Helper class mostly to avoid passing masm everywhere, and handle 477 // store displacement overflow logic. 478 class AdapterGenerator { 479 MacroAssembler *masm; 480 Register Rdisp; 481 void set_Rdisp(Register r) { Rdisp = r; } 482 483 void patch_callers_callsite(); 484 485 // base+st_off points to top of argument 486 int arg_offset(const int st_off) { return st_off; } 487 int next_arg_offset(const int st_off) { 488 return st_off - Interpreter::stackElementSize; 489 } 490 491 // Argument slot values may be loaded first into a register because 492 // they might not fit into displacement. 493 RegisterOrConstant arg_slot(const int st_off); 494 RegisterOrConstant next_arg_slot(const int st_off); 495 496 // Stores long into offset pointed to by base 497 void store_c2i_long(Register r, Register base, 498 const int st_off, bool is_stack); 499 void store_c2i_object(Register r, Register base, 500 const int st_off); 501 void store_c2i_int(Register r, Register base, 502 const int st_off); 503 void store_c2i_double(VMReg r_2, 504 VMReg r_1, Register base, const int st_off); 505 void store_c2i_float(FloatRegister f, Register base, 506 const int st_off); 507 508 public: 509 void gen_c2i_adapter(int total_args_passed, 510 // VMReg max_arg, 511 int comp_args_on_stack, // VMRegStackSlots 512 const BasicType *sig_bt, 513 const VMRegPair *regs, 514 Label& skip_fixup); 515 void gen_i2c_adapter(int total_args_passed, 516 // VMReg max_arg, 517 int comp_args_on_stack, // VMRegStackSlots 518 const BasicType *sig_bt, 519 const VMRegPair *regs); 520 521 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {} 522 }; 523 524 525 // Patch the callers callsite with entry to compiled code if it exists. 526 void AdapterGenerator::patch_callers_callsite() { 527 Label L; 528 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); 529 __ br_null(G3_scratch, false, Assembler::pt, L); 530 __ delayed()->nop(); 531 // Call into the VM to patch the caller, then jump to compiled callee 532 __ save_frame(4); // Args in compiled layout; do not blow them 533 534 // Must save all the live Gregs the list is: 535 // G1: 1st Long arg (32bit build) 536 // G2: global allocated to TLS 537 // G3: used in inline cache check (scratch) 538 // G4: 2nd Long arg (32bit build); 539 // G5: used in inline cache check (Method*) 540 541 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops. 542 543 #ifdef _LP64 544 // mov(s,d) 545 __ mov(G1, L1); 546 __ mov(G4, L4); 547 __ mov(G5_method, L5); 548 __ mov(G5_method, O0); // VM needs target method 549 __ mov(I7, O1); // VM needs caller's callsite 550 // Must be a leaf call... 551 // can be very far once the blob has been relocated 552 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite)); 553 __ relocate(relocInfo::runtime_call_type); 554 __ jumpl_to(dest, O7, O7); 555 __ delayed()->mov(G2_thread, L7_thread_cache); 556 __ mov(L7_thread_cache, G2_thread); 557 __ mov(L1, G1); 558 __ mov(L4, G4); 559 __ mov(L5, G5_method); 560 #else 561 __ stx(G1, FP, -8 + STACK_BIAS); 562 __ stx(G4, FP, -16 + STACK_BIAS); 563 __ mov(G5_method, L5); 564 __ mov(G5_method, O0); // VM needs target method 565 __ mov(I7, O1); // VM needs caller's callsite 566 // Must be a leaf call... 567 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type); 568 __ delayed()->mov(G2_thread, L7_thread_cache); 569 __ mov(L7_thread_cache, G2_thread); 570 __ ldx(FP, -8 + STACK_BIAS, G1); 571 __ ldx(FP, -16 + STACK_BIAS, G4); 572 __ mov(L5, G5_method); 573 #endif /* _LP64 */ 574 575 __ restore(); // Restore args 576 __ bind(L); 577 } 578 579 580 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) { 581 RegisterOrConstant roc(arg_offset(st_off)); 582 return __ ensure_simm13_or_reg(roc, Rdisp); 583 } 584 585 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) { 586 RegisterOrConstant roc(next_arg_offset(st_off)); 587 return __ ensure_simm13_or_reg(roc, Rdisp); 588 } 589 590 591 // Stores long into offset pointed to by base 592 void AdapterGenerator::store_c2i_long(Register r, Register base, 593 const int st_off, bool is_stack) { 594 #ifdef _LP64 595 // In V9, longs are given 2 64-bit slots in the interpreter, but the 596 // data is passed in only 1 slot. 597 __ stx(r, base, next_arg_slot(st_off)); 598 #else 599 #ifdef COMPILER2 600 // Misaligned store of 64-bit data 601 __ stw(r, base, arg_slot(st_off)); // lo bits 602 __ srlx(r, 32, r); 603 __ stw(r, base, next_arg_slot(st_off)); // hi bits 604 #else 605 if (is_stack) { 606 // Misaligned store of 64-bit data 607 __ stw(r, base, arg_slot(st_off)); // lo bits 608 __ srlx(r, 32, r); 609 __ stw(r, base, next_arg_slot(st_off)); // hi bits 610 } else { 611 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits 612 __ stw(r , base, next_arg_slot(st_off)); // hi bits 613 } 614 #endif // COMPILER2 615 #endif // _LP64 616 } 617 618 void AdapterGenerator::store_c2i_object(Register r, Register base, 619 const int st_off) { 620 __ st_ptr (r, base, arg_slot(st_off)); 621 } 622 623 void AdapterGenerator::store_c2i_int(Register r, Register base, 624 const int st_off) { 625 __ st (r, base, arg_slot(st_off)); 626 } 627 628 // Stores into offset pointed to by base 629 void AdapterGenerator::store_c2i_double(VMReg r_2, 630 VMReg r_1, Register base, const int st_off) { 631 #ifdef _LP64 632 // In V9, doubles are given 2 64-bit slots in the interpreter, but the 633 // data is passed in only 1 slot. 634 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); 635 #else 636 // Need to marshal 64-bit value from misaligned Lesp loads 637 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off)); 638 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) ); 639 #endif 640 } 641 642 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base, 643 const int st_off) { 644 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off)); 645 } 646 647 void AdapterGenerator::gen_c2i_adapter( 648 int total_args_passed, 649 // VMReg max_arg, 650 int comp_args_on_stack, // VMRegStackSlots 651 const BasicType *sig_bt, 652 const VMRegPair *regs, 653 Label& L_skip_fixup) { 654 655 // Before we get into the guts of the C2I adapter, see if we should be here 656 // at all. We've come from compiled code and are attempting to jump to the 657 // interpreter, which means the caller made a static call to get here 658 // (vcalls always get a compiled target if there is one). Check for a 659 // compiled target. If there is one, we need to patch the caller's call. 660 // However we will run interpreted if we come thru here. The next pass 661 // thru the call site will run compiled. If we ran compiled here then 662 // we can (theorectically) do endless i2c->c2i->i2c transitions during 663 // deopt/uncommon trap cycles. If we always go interpreted here then 664 // we can have at most one and don't need to play any tricks to keep 665 // from endlessly growing the stack. 666 // 667 // Actually if we detected that we had an i2c->c2i transition here we 668 // ought to be able to reset the world back to the state of the interpreted 669 // call and not bother building another interpreter arg area. We don't 670 // do that at this point. 671 672 patch_callers_callsite(); 673 674 __ bind(L_skip_fixup); 675 676 // Since all args are passed on the stack, total_args_passed*wordSize is the 677 // space we need. Add in varargs area needed by the interpreter. Round up 678 // to stack alignment. 679 const int arg_size = total_args_passed * Interpreter::stackElementSize; 680 const int varargs_area = 681 (frame::varargs_offset - frame::register_save_words)*wordSize; 682 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize); 683 684 const int bias = STACK_BIAS; 685 const int interp_arg_offset = frame::varargs_offset*wordSize + 686 (total_args_passed-1)*Interpreter::stackElementSize; 687 688 const Register base = SP; 689 690 // Make some extra space on the stack. 691 __ sub(SP, __ ensure_simm13_or_reg(extraspace, G3_scratch), SP); 692 set_Rdisp(G3_scratch); 693 694 // Write the args into the outgoing interpreter space. 695 for (int i = 0; i < total_args_passed; i++) { 696 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias; 697 VMReg r_1 = regs[i].first(); 698 VMReg r_2 = regs[i].second(); 699 if (!r_1->is_valid()) { 700 assert(!r_2->is_valid(), ""); 701 continue; 702 } 703 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1 704 RegisterOrConstant ld_off = reg2offset(r_1) + extraspace + bias; 705 ld_off = __ ensure_simm13_or_reg(ld_off, Rdisp); 706 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle 707 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch); 708 else __ ldx(base, ld_off, G1_scratch); 709 } 710 711 if (r_1->is_Register()) { 712 Register r = r_1->as_Register()->after_restore(); 713 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) { 714 store_c2i_object(r, base, st_off); 715 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) { 716 store_c2i_long(r, base, st_off, r_2->is_stack()); 717 } else { 718 store_c2i_int(r, base, st_off); 719 } 720 } else { 721 assert(r_1->is_FloatRegister(), ""); 722 if (sig_bt[i] == T_FLOAT) { 723 store_c2i_float(r_1->as_FloatRegister(), base, st_off); 724 } else { 725 assert(sig_bt[i] == T_DOUBLE, "wrong type"); 726 store_c2i_double(r_2, r_1, base, st_off); 727 } 728 } 729 } 730 731 // Load the interpreter entry point. 732 __ ld_ptr(G5_method, in_bytes(Method::interpreter_entry_offset()), G3_scratch); 733 734 // Pass O5_savedSP as an argument to the interpreter. 735 // The interpreter will restore SP to this value before returning. 736 __ add(SP, __ ensure_simm13_or_reg(extraspace, G1), O5_savedSP); 737 738 __ mov((frame::varargs_offset)*wordSize - 739 1*Interpreter::stackElementSize+bias+BytesPerWord, G1); 740 // Jump to the interpreter just as if interpreter was doing it. 741 __ jmpl(G3_scratch, 0, G0); 742 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp 743 // (really L0) is in use by the compiled frame as a generic temp. However, 744 // the interpreter does not know where its args are without some kind of 745 // arg pointer being passed in. Pass it in Gargs. 746 __ delayed()->add(SP, G1, Gargs); 747 } 748 749 static void range_check(MacroAssembler* masm, Register pc_reg, Register temp_reg, Register temp2_reg, 750 address code_start, address code_end, 751 Label& L_ok) { 752 Label L_fail; 753 __ set(ExternalAddress(code_start), temp_reg); 754 __ set(pointer_delta(code_end, code_start, 1), temp2_reg); 755 __ cmp(pc_reg, temp_reg); 756 __ brx(Assembler::lessEqualUnsigned, false, Assembler::pn, L_fail); 757 __ delayed()->add(temp_reg, temp2_reg, temp_reg); 758 __ cmp(pc_reg, temp_reg); 759 __ cmp_and_brx_short(pc_reg, temp_reg, Assembler::lessUnsigned, Assembler::pt, L_ok); 760 __ bind(L_fail); 761 } 762 763 void AdapterGenerator::gen_i2c_adapter( 764 int total_args_passed, 765 // VMReg max_arg, 766 int comp_args_on_stack, // VMRegStackSlots 767 const BasicType *sig_bt, 768 const VMRegPair *regs) { 769 770 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame 771 // layout. Lesp was saved by the calling I-frame and will be restored on 772 // return. Meanwhile, outgoing arg space is all owned by the callee 773 // C-frame, so we can mangle it at will. After adjusting the frame size, 774 // hoist register arguments and repack other args according to the compiled 775 // code convention. Finally, end in a jump to the compiled code. The entry 776 // point address is the start of the buffer. 777 778 // We will only enter here from an interpreted frame and never from after 779 // passing thru a c2i. Azul allowed this but we do not. If we lose the 780 // race and use a c2i we will remain interpreted for the race loser(s). 781 // This removes all sorts of headaches on the x86 side and also eliminates 782 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions. 783 784 // More detail: 785 // Adapters can be frameless because they do not require the caller 786 // to perform additional cleanup work, such as correcting the stack pointer. 787 // An i2c adapter is frameless because the *caller* frame, which is interpreted, 788 // routinely repairs its own stack pointer (from interpreter_frame_last_sp), 789 // even if a callee has modified the stack pointer. 790 // A c2i adapter is frameless because the *callee* frame, which is interpreted, 791 // routinely repairs its caller's stack pointer (from sender_sp, which is set 792 // up via the senderSP register). 793 // In other words, if *either* the caller or callee is interpreted, we can 794 // get the stack pointer repaired after a call. 795 // This is why c2i and i2c adapters cannot be indefinitely composed. 796 // In particular, if a c2i adapter were to somehow call an i2c adapter, 797 // both caller and callee would be compiled methods, and neither would 798 // clean up the stack pointer changes performed by the two adapters. 799 // If this happens, control eventually transfers back to the compiled 800 // caller, but with an uncorrected stack, causing delayed havoc. 801 802 if (VerifyAdapterCalls && 803 (Interpreter::code() != NULL || StubRoutines::code1() != NULL)) { 804 // So, let's test for cascading c2i/i2c adapters right now. 805 // assert(Interpreter::contains($return_addr) || 806 // StubRoutines::contains($return_addr), 807 // "i2c adapter must return to an interpreter frame"); 808 __ block_comment("verify_i2c { "); 809 Label L_ok; 810 if (Interpreter::code() != NULL) 811 range_check(masm, O7, O0, O1, 812 Interpreter::code()->code_start(), Interpreter::code()->code_end(), 813 L_ok); 814 if (StubRoutines::code1() != NULL) 815 range_check(masm, O7, O0, O1, 816 StubRoutines::code1()->code_begin(), StubRoutines::code1()->code_end(), 817 L_ok); 818 if (StubRoutines::code2() != NULL) 819 range_check(masm, O7, O0, O1, 820 StubRoutines::code2()->code_begin(), StubRoutines::code2()->code_end(), 821 L_ok); 822 const char* msg = "i2c adapter must return to an interpreter frame"; 823 __ block_comment(msg); 824 __ stop(msg); 825 __ bind(L_ok); 826 __ block_comment("} verify_i2ce "); 827 } 828 829 // As you can see from the list of inputs & outputs there are not a lot 830 // of temp registers to work with: mostly G1, G3 & G4. 831 832 // Inputs: 833 // G2_thread - TLS 834 // G5_method - Method oop 835 // G4 (Gargs) - Pointer to interpreter's args 836 // O0..O4 - free for scratch 837 // O5_savedSP - Caller's saved SP, to be restored if needed 838 // O6 - Current SP! 839 // O7 - Valid return address 840 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) 841 842 // Outputs: 843 // G2_thread - TLS 844 // O0-O5 - Outgoing args in compiled layout 845 // O6 - Adjusted or restored SP 846 // O7 - Valid return address 847 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet) 848 // F0-F7 - more outgoing args 849 850 851 // Gargs is the incoming argument base, and also an outgoing argument. 852 __ sub(Gargs, BytesPerWord, Gargs); 853 854 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME 855 // WITH O7 HOLDING A VALID RETURN PC 856 // 857 // | | 858 // : java stack : 859 // | | 860 // +--------------+ <--- start of outgoing args 861 // | receiver | | 862 // : rest of args : |---size is java-arg-words 863 // | | | 864 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I 865 // | | | 866 // : unused : |---Space for max Java stack, plus stack alignment 867 // | | | 868 // +--------------+ <--- SP + 16*wordsize 869 // | | 870 // : window : 871 // | | 872 // +--------------+ <--- SP 873 874 // WE REPACK THE STACK. We use the common calling convention layout as 875 // discovered by calling SharedRuntime::calling_convention. We assume it 876 // causes an arbitrary shuffle of memory, which may require some register 877 // temps to do the shuffle. We hope for (and optimize for) the case where 878 // temps are not needed. We may have to resize the stack slightly, in case 879 // we need alignment padding (32-bit interpreter can pass longs & doubles 880 // misaligned, but the compilers expect them aligned). 881 // 882 // | | 883 // : java stack : 884 // | | 885 // +--------------+ <--- start of outgoing args 886 // | pad, align | | 887 // +--------------+ | 888 // | ints, longs, | | 889 // | floats, | |---Outgoing stack args. 890 // : doubles : | First few args in registers. 891 // | | | 892 // +--------------+ <--- SP' + 16*wordsize 893 // | | 894 // : window : 895 // | | 896 // +--------------+ <--- SP' 897 898 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME 899 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP 900 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN. 901 902 // Cut-out for having no stack args. Since up to 6 args are passed 903 // in registers, we will commonly have no stack args. 904 if (comp_args_on_stack > 0) { 905 // Convert VMReg stack slots to words. 906 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord; 907 // Round up to miminum stack alignment, in wordSize 908 comp_words_on_stack = round_to(comp_words_on_stack, 2); 909 // Now compute the distance from Lesp to SP. This calculation does not 910 // include the space for total_args_passed because Lesp has not yet popped 911 // the arguments. 912 __ sub(SP, (comp_words_on_stack)*wordSize, SP); 913 } 914 915 // Now generate the shuffle code. Pick up all register args and move the 916 // rest through G1_scratch. 917 for (int i = 0; i < total_args_passed; i++) { 918 if (sig_bt[i] == T_VOID) { 919 // Longs and doubles are passed in native word order, but misaligned 920 // in the 32-bit build. 921 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half"); 922 continue; 923 } 924 925 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the 926 // 32-bit build and aligned in the 64-bit build. Look for the obvious 927 // ldx/lddf optimizations. 928 929 // Load in argument order going down. 930 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize; 931 set_Rdisp(G1_scratch); 932 933 VMReg r_1 = regs[i].first(); 934 VMReg r_2 = regs[i].second(); 935 if (!r_1->is_valid()) { 936 assert(!r_2->is_valid(), ""); 937 continue; 938 } 939 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9 940 r_1 = F8->as_VMReg(); // as part of the load/store shuffle 941 if (r_2->is_valid()) r_2 = r_1->next(); 942 } 943 if (r_1->is_Register()) { // Register argument 944 Register r = r_1->as_Register()->after_restore(); 945 if (!r_2->is_valid()) { 946 __ ld(Gargs, arg_slot(ld_off), r); 947 } else { 948 #ifdef _LP64 949 // In V9, longs are given 2 64-bit slots in the interpreter, but the 950 // data is passed in only 1 slot. 951 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ? 952 next_arg_slot(ld_off) : arg_slot(ld_off); 953 __ ldx(Gargs, slot, r); 954 #else 955 fatal("longs should be on stack"); 956 #endif 957 } 958 } else { 959 assert(r_1->is_FloatRegister(), ""); 960 if (!r_2->is_valid()) { 961 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister()); 962 } else { 963 #ifdef _LP64 964 // In V9, doubles are given 2 64-bit slots in the interpreter, but the 965 // data is passed in only 1 slot. This code also handles longs that 966 // are passed on the stack, but need a stack-to-stack move through a 967 // spare float register. 968 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ? 969 next_arg_slot(ld_off) : arg_slot(ld_off); 970 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister()); 971 #else 972 // Need to marshal 64-bit value from misaligned Lesp loads 973 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister()); 974 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister()); 975 #endif 976 } 977 } 978 // Was the argument really intended to be on the stack, but was loaded 979 // into F8/F9? 980 if (regs[i].first()->is_stack()) { 981 assert(r_1->as_FloatRegister() == F8, "fix this code"); 982 // Convert stack slot to an SP offset 983 int st_off = reg2offset(regs[i].first()) + STACK_BIAS; 984 // Store down the shuffled stack word. Target address _is_ aligned. 985 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp); 986 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot); 987 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot); 988 } 989 } 990 991 // Jump to the compiled code just as if compiled code was doing it. 992 __ ld_ptr(G5_method, in_bytes(Method::from_compiled_offset()), G3); 993 994 // 6243940 We might end up in handle_wrong_method if 995 // the callee is deoptimized as we race thru here. If that 996 // happens we don't want to take a safepoint because the 997 // caller frame will look interpreted and arguments are now 998 // "compiled" so it is much better to make this transition 999 // invisible to the stack walking code. Unfortunately if 1000 // we try and find the callee by normal means a safepoint 1001 // is possible. So we stash the desired callee in the thread 1002 // and the vm will find there should this case occur. 1003 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset()); 1004 __ st_ptr(G5_method, callee_target_addr); 1005 __ jmpl(G3, 0, G0); 1006 __ delayed()->nop(); 1007 } 1008 1009 // --------------------------------------------------------------- 1010 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm, 1011 int total_args_passed, 1012 // VMReg max_arg, 1013 int comp_args_on_stack, // VMRegStackSlots 1014 const BasicType *sig_bt, 1015 const VMRegPair *regs, 1016 AdapterFingerPrint* fingerprint) { 1017 address i2c_entry = __ pc(); 1018 1019 AdapterGenerator agen(masm); 1020 1021 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs); 1022 1023 1024 // ------------------------------------------------------------------------- 1025 // Generate a C2I adapter. On entry we know G5 holds the Method*. The 1026 // args start out packed in the compiled layout. They need to be unpacked 1027 // into the interpreter layout. This will almost always require some stack 1028 // space. We grow the current (compiled) stack, then repack the args. We 1029 // finally end in a jump to the generic interpreter entry point. On exit 1030 // from the interpreter, the interpreter will restore our SP (lest the 1031 // compiled code, which relys solely on SP and not FP, get sick). 1032 1033 address c2i_unverified_entry = __ pc(); 1034 Label L_skip_fixup; 1035 { 1036 Register R_temp = G1; // another scratch register 1037 1038 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); 1039 1040 __ verify_oop(O0); 1041 __ load_klass(O0, G3_scratch); 1042 1043 __ ld_ptr(G5_method, CompiledICHolder::holder_klass_offset(), R_temp); 1044 __ cmp(G3_scratch, R_temp); 1045 1046 Label ok, ok2; 1047 __ brx(Assembler::equal, false, Assembler::pt, ok); 1048 __ delayed()->ld_ptr(G5_method, CompiledICHolder::holder_method_offset(), G5_method); 1049 __ jump_to(ic_miss, G3_scratch); 1050 __ delayed()->nop(); 1051 1052 __ bind(ok); 1053 // Method might have been compiled since the call site was patched to 1054 // interpreted if that is the case treat it as a miss so we can get 1055 // the call site corrected. 1056 __ ld_ptr(G5_method, in_bytes(Method::code_offset()), G3_scratch); 1057 __ bind(ok2); 1058 __ br_null(G3_scratch, false, Assembler::pt, L_skip_fixup); 1059 __ delayed()->nop(); 1060 __ jump_to(ic_miss, G3_scratch); 1061 __ delayed()->nop(); 1062 1063 } 1064 1065 address c2i_entry = __ pc(); 1066 1067 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, L_skip_fixup); 1068 1069 __ flush(); 1070 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry); 1071 1072 } 1073 1074 // Helper function for native calling conventions 1075 static VMReg int_stk_helper( int i ) { 1076 // Bias any stack based VMReg we get by ignoring the window area 1077 // but not the register parameter save area. 1078 // 1079 // This is strange for the following reasons. We'd normally expect 1080 // the calling convention to return an VMReg for a stack slot 1081 // completely ignoring any abi reserved area. C2 thinks of that 1082 // abi area as only out_preserve_stack_slots. This does not include 1083 // the area allocated by the C abi to store down integer arguments 1084 // because the java calling convention does not use it. So 1085 // since c2 assumes that there are only out_preserve_stack_slots 1086 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack 1087 // location the c calling convention must add in this bias amount 1088 // to make up for the fact that the out_preserve_stack_slots is 1089 // insufficient for C calls. What a mess. I sure hope those 6 1090 // stack words were worth it on every java call! 1091 1092 // Another way of cleaning this up would be for out_preserve_stack_slots 1093 // to take a parameter to say whether it was C or java calling conventions. 1094 // Then things might look a little better (but not much). 1095 1096 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM; 1097 if( mem_parm_offset < 0 ) { 1098 return as_oRegister(i)->as_VMReg(); 1099 } else { 1100 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word; 1101 // Now return a biased offset that will be correct when out_preserve_slots is added back in 1102 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots()); 1103 } 1104 } 1105 1106 1107 int SharedRuntime::c_calling_convention(const BasicType *sig_bt, 1108 VMRegPair *regs, 1109 VMRegPair *regs2, 1110 int total_args_passed) { 1111 assert(regs2 == NULL, "not needed on sparc"); 1112 1113 // Return the number of VMReg stack_slots needed for the args. 1114 // This value does not include an abi space (like register window 1115 // save area). 1116 1117 // The native convention is V8 if !LP64 1118 // The LP64 convention is the V9 convention which is slightly more sane. 1119 1120 // We return the amount of VMReg stack slots we need to reserve for all 1121 // the arguments NOT counting out_preserve_stack_slots. Since we always 1122 // have space for storing at least 6 registers to memory we start with that. 1123 // See int_stk_helper for a further discussion. 1124 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots(); 1125 1126 #ifdef _LP64 1127 // V9 convention: All things "as-if" on double-wide stack slots. 1128 // Hoist any int/ptr/long's in the first 6 to int regs. 1129 // Hoist any flt/dbl's in the first 16 dbl regs. 1130 int j = 0; // Count of actual args, not HALVES 1131 for( int i=0; i<total_args_passed; i++, j++ ) { 1132 switch( sig_bt[i] ) { 1133 case T_BOOLEAN: 1134 case T_BYTE: 1135 case T_CHAR: 1136 case T_INT: 1137 case T_SHORT: 1138 regs[i].set1( int_stk_helper( j ) ); break; 1139 case T_LONG: 1140 assert( sig_bt[i+1] == T_VOID, "expecting half" ); 1141 case T_ADDRESS: // raw pointers, like current thread, for VM calls 1142 case T_ARRAY: 1143 case T_OBJECT: 1144 case T_METADATA: 1145 regs[i].set2( int_stk_helper( j ) ); 1146 break; 1147 case T_FLOAT: 1148 if ( j < 16 ) { 1149 // V9ism: floats go in ODD registers 1150 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg()); 1151 } else { 1152 // V9ism: floats go in ODD stack slot 1153 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1))); 1154 } 1155 break; 1156 case T_DOUBLE: 1157 assert( sig_bt[i+1] == T_VOID, "expecting half" ); 1158 if ( j < 16 ) { 1159 // V9ism: doubles go in EVEN/ODD regs 1160 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg()); 1161 } else { 1162 // V9ism: doubles go in EVEN/ODD stack slots 1163 regs[i].set2(VMRegImpl::stack2reg(j<<1)); 1164 } 1165 break; 1166 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES 1167 default: 1168 ShouldNotReachHere(); 1169 } 1170 if (regs[i].first()->is_stack()) { 1171 int off = regs[i].first()->reg2stack(); 1172 if (off > max_stack_slots) max_stack_slots = off; 1173 } 1174 if (regs[i].second()->is_stack()) { 1175 int off = regs[i].second()->reg2stack(); 1176 if (off > max_stack_slots) max_stack_slots = off; 1177 } 1178 } 1179 1180 #else // _LP64 1181 // V8 convention: first 6 things in O-regs, rest on stack. 1182 // Alignment is willy-nilly. 1183 for( int i=0; i<total_args_passed; i++ ) { 1184 switch( sig_bt[i] ) { 1185 case T_ADDRESS: // raw pointers, like current thread, for VM calls 1186 case T_ARRAY: 1187 case T_BOOLEAN: 1188 case T_BYTE: 1189 case T_CHAR: 1190 case T_FLOAT: 1191 case T_INT: 1192 case T_OBJECT: 1193 case T_METADATA: 1194 case T_SHORT: 1195 regs[i].set1( int_stk_helper( i ) ); 1196 break; 1197 case T_DOUBLE: 1198 case T_LONG: 1199 assert( sig_bt[i+1] == T_VOID, "expecting half" ); 1200 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) ); 1201 break; 1202 case T_VOID: regs[i].set_bad(); break; 1203 default: 1204 ShouldNotReachHere(); 1205 } 1206 if (regs[i].first()->is_stack()) { 1207 int off = regs[i].first()->reg2stack(); 1208 if (off > max_stack_slots) max_stack_slots = off; 1209 } 1210 if (regs[i].second()->is_stack()) { 1211 int off = regs[i].second()->reg2stack(); 1212 if (off > max_stack_slots) max_stack_slots = off; 1213 } 1214 } 1215 #endif // _LP64 1216 1217 return round_to(max_stack_slots + 1, 2); 1218 1219 } 1220 1221 1222 // --------------------------------------------------------------------------- 1223 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { 1224 switch (ret_type) { 1225 case T_FLOAT: 1226 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS); 1227 break; 1228 case T_DOUBLE: 1229 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS); 1230 break; 1231 } 1232 } 1233 1234 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) { 1235 switch (ret_type) { 1236 case T_FLOAT: 1237 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0); 1238 break; 1239 case T_DOUBLE: 1240 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0); 1241 break; 1242 } 1243 } 1244 1245 // Check and forward and pending exception. Thread is stored in 1246 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there 1247 // is no exception handler. We merely pop this frame off and throw the 1248 // exception in the caller's frame. 1249 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) { 1250 Label L; 1251 __ br_null(Rex_oop, false, Assembler::pt, L); 1252 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception 1253 // Since this is a native call, we *know* the proper exception handler 1254 // without calling into the VM: it's the empty function. Just pop this 1255 // frame and then jump to forward_exception_entry; O7 will contain the 1256 // native caller's return PC. 1257 AddressLiteral exception_entry(StubRoutines::forward_exception_entry()); 1258 __ jump_to(exception_entry, G3_scratch); 1259 __ delayed()->restore(); // Pop this frame off. 1260 __ bind(L); 1261 } 1262 1263 // A simple move of integer like type 1264 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1265 if (src.first()->is_stack()) { 1266 if (dst.first()->is_stack()) { 1267 // stack to stack 1268 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); 1269 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); 1270 } else { 1271 // stack to reg 1272 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1273 } 1274 } else if (dst.first()->is_stack()) { 1275 // reg to stack 1276 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); 1277 } else { 1278 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1279 } 1280 } 1281 1282 // On 64 bit we will store integer like items to the stack as 1283 // 64 bits items (sparc abi) even though java would only store 1284 // 32bits for a parameter. On 32bit it will simply be 32 bits 1285 // So this routine will do 32->32 on 32bit and 32->64 on 64bit 1286 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1287 if (src.first()->is_stack()) { 1288 if (dst.first()->is_stack()) { 1289 // stack to stack 1290 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); 1291 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); 1292 } else { 1293 // stack to reg 1294 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1295 } 1296 } else if (dst.first()->is_stack()) { 1297 // reg to stack 1298 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); 1299 } else { 1300 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1301 } 1302 } 1303 1304 1305 static void move_ptr(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1306 if (src.first()->is_stack()) { 1307 if (dst.first()->is_stack()) { 1308 // stack to stack 1309 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, L5); 1310 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS); 1311 } else { 1312 // stack to reg 1313 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1314 } 1315 } else if (dst.first()->is_stack()) { 1316 // reg to stack 1317 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); 1318 } else { 1319 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1320 } 1321 } 1322 1323 1324 // An oop arg. Must pass a handle not the oop itself 1325 static void object_move(MacroAssembler* masm, 1326 OopMap* map, 1327 int oop_handle_offset, 1328 int framesize_in_slots, 1329 VMRegPair src, 1330 VMRegPair dst, 1331 bool is_receiver, 1332 int* receiver_offset) { 1333 1334 // must pass a handle. First figure out the location we use as a handle 1335 1336 if (src.first()->is_stack()) { 1337 // Oop is already on the stack 1338 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register(); 1339 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle); 1340 __ ld_ptr(rHandle, 0, L4); 1341 #ifdef _LP64 1342 __ movr( Assembler::rc_z, L4, G0, rHandle ); 1343 #else 1344 __ tst( L4 ); 1345 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); 1346 #endif 1347 if (dst.first()->is_stack()) { 1348 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); 1349 } 1350 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 1351 if (is_receiver) { 1352 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size; 1353 } 1354 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots)); 1355 } else { 1356 // Oop is in an input register pass we must flush it to the stack 1357 const Register rOop = src.first()->as_Register(); 1358 const Register rHandle = L5; 1359 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset; 1360 int offset = oop_slot*VMRegImpl::stack_slot_size; 1361 Label skip; 1362 __ st_ptr(rOop, SP, offset + STACK_BIAS); 1363 if (is_receiver) { 1364 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size; 1365 } 1366 map->set_oop(VMRegImpl::stack2reg(oop_slot)); 1367 __ add(SP, offset + STACK_BIAS, rHandle); 1368 #ifdef _LP64 1369 __ movr( Assembler::rc_z, rOop, G0, rHandle ); 1370 #else 1371 __ tst( rOop ); 1372 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle ); 1373 #endif 1374 1375 if (dst.first()->is_stack()) { 1376 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS); 1377 } else { 1378 __ mov(rHandle, dst.first()->as_Register()); 1379 } 1380 } 1381 } 1382 1383 // A float arg may have to do float reg int reg conversion 1384 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1385 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move"); 1386 1387 if (src.first()->is_stack()) { 1388 if (dst.first()->is_stack()) { 1389 // stack to stack the easiest of the bunch 1390 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); 1391 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); 1392 } else { 1393 // stack to reg 1394 if (dst.first()->is_Register()) { 1395 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1396 } else { 1397 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); 1398 } 1399 } 1400 } else if (dst.first()->is_stack()) { 1401 // reg to stack 1402 if (src.first()->is_Register()) { 1403 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); 1404 } else { 1405 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); 1406 } 1407 } else { 1408 // reg to reg 1409 if (src.first()->is_Register()) { 1410 if (dst.first()->is_Register()) { 1411 // gpr -> gpr 1412 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1413 } else { 1414 // gpr -> fpr 1415 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS); 1416 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister()); 1417 } 1418 } else if (dst.first()->is_Register()) { 1419 // fpr -> gpr 1420 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS); 1421 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register()); 1422 } else { 1423 // fpr -> fpr 1424 // In theory these overlap but the ordering is such that this is likely a nop 1425 if ( src.first() != dst.first()) { 1426 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); 1427 } 1428 } 1429 } 1430 } 1431 1432 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1433 VMRegPair src_lo(src.first()); 1434 VMRegPair src_hi(src.second()); 1435 VMRegPair dst_lo(dst.first()); 1436 VMRegPair dst_hi(dst.second()); 1437 simple_move32(masm, src_lo, dst_lo); 1438 simple_move32(masm, src_hi, dst_hi); 1439 } 1440 1441 // A long move 1442 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1443 1444 // Do the simple ones here else do two int moves 1445 if (src.is_single_phys_reg() ) { 1446 if (dst.is_single_phys_reg()) { 1447 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1448 } else { 1449 // split src into two separate registers 1450 // Remember hi means hi address or lsw on sparc 1451 // Move msw to lsw 1452 if (dst.second()->is_reg()) { 1453 // MSW -> MSW 1454 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register()); 1455 // Now LSW -> LSW 1456 // this will only move lo -> lo and ignore hi 1457 VMRegPair split(dst.second()); 1458 simple_move32(masm, src, split); 1459 } else { 1460 VMRegPair split(src.first(), L4->as_VMReg()); 1461 // MSW -> MSW (lo ie. first word) 1462 __ srax(src.first()->as_Register(), 32, L4); 1463 split_long_move(masm, split, dst); 1464 } 1465 } 1466 } else if (dst.is_single_phys_reg()) { 1467 if (src.is_adjacent_aligned_on_stack(2)) { 1468 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1469 } else { 1470 // dst is a single reg. 1471 // Remember lo is low address not msb for stack slots 1472 // and lo is the "real" register for registers 1473 // src is 1474 1475 VMRegPair split; 1476 1477 if (src.first()->is_reg()) { 1478 // src.lo (msw) is a reg, src.hi is stk/reg 1479 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg] 1480 split.set_pair(dst.first(), src.first()); 1481 } else { 1482 // msw is stack move to L5 1483 // lsw is stack move to dst.lo (real reg) 1484 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5 1485 split.set_pair(dst.first(), L5->as_VMReg()); 1486 } 1487 1488 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg) 1489 // msw -> src.lo/L5, lsw -> dst.lo 1490 split_long_move(masm, src, split); 1491 1492 // So dst now has the low order correct position the 1493 // msw half 1494 __ sllx(split.first()->as_Register(), 32, L5); 1495 1496 const Register d = dst.first()->as_Register(); 1497 __ or3(L5, d, d); 1498 } 1499 } else { 1500 // For LP64 we can probably do better. 1501 split_long_move(masm, src, dst); 1502 } 1503 } 1504 1505 // A double move 1506 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) { 1507 1508 // The painful thing here is that like long_move a VMRegPair might be 1509 // 1: a single physical register 1510 // 2: two physical registers (v8) 1511 // 3: a physical reg [lo] and a stack slot [hi] (v8) 1512 // 4: two stack slots 1513 1514 // Since src is always a java calling convention we know that the src pair 1515 // is always either all registers or all stack (and aligned?) 1516 1517 // in a register [lo] and a stack slot [hi] 1518 if (src.first()->is_stack()) { 1519 if (dst.first()->is_stack()) { 1520 // stack to stack the easiest of the bunch 1521 // ought to be a way to do this where if alignment is ok we use ldd/std when possible 1522 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5); 1523 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); 1524 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS); 1525 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); 1526 } else { 1527 // stack to reg 1528 if (dst.second()->is_stack()) { 1529 // stack -> reg, stack -> stack 1530 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); 1531 if (dst.first()->is_Register()) { 1532 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1533 } else { 1534 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); 1535 } 1536 // This was missing. (very rare case) 1537 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); 1538 } else { 1539 // stack -> reg 1540 // Eventually optimize for alignment QQQ 1541 if (dst.first()->is_Register()) { 1542 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register()); 1543 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register()); 1544 } else { 1545 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister()); 1546 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister()); 1547 } 1548 } 1549 } 1550 } else if (dst.first()->is_stack()) { 1551 // reg to stack 1552 if (src.first()->is_Register()) { 1553 // Eventually optimize for alignment QQQ 1554 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS); 1555 if (src.second()->is_stack()) { 1556 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4); 1557 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); 1558 } else { 1559 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS); 1560 } 1561 } else { 1562 // fpr to stack 1563 if (src.second()->is_stack()) { 1564 ShouldNotReachHere(); 1565 } else { 1566 // Is the stack aligned? 1567 if (reg2offset(dst.first()) & 0x7) { 1568 // No do as pairs 1569 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); 1570 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS); 1571 } else { 1572 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS); 1573 } 1574 } 1575 } 1576 } else { 1577 // reg to reg 1578 if (src.first()->is_Register()) { 1579 if (dst.first()->is_Register()) { 1580 // gpr -> gpr 1581 __ mov(src.first()->as_Register(), dst.first()->as_Register()); 1582 __ mov(src.second()->as_Register(), dst.second()->as_Register()); 1583 } else { 1584 // gpr -> fpr 1585 // ought to be able to do a single store 1586 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS); 1587 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS); 1588 // ought to be able to do a single load 1589 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister()); 1590 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister()); 1591 } 1592 } else if (dst.first()->is_Register()) { 1593 // fpr -> gpr 1594 // ought to be able to do a single store 1595 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS); 1596 // ought to be able to do a single load 1597 // REMEMBER first() is low address not LSB 1598 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register()); 1599 if (dst.second()->is_Register()) { 1600 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register()); 1601 } else { 1602 __ ld(FP, -4 + STACK_BIAS, L4); 1603 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS); 1604 } 1605 } else { 1606 // fpr -> fpr 1607 // In theory these overlap but the ordering is such that this is likely a nop 1608 if ( src.first() != dst.first()) { 1609 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister()); 1610 } 1611 } 1612 } 1613 } 1614 1615 // Creates an inner frame if one hasn't already been created, and 1616 // saves a copy of the thread in L7_thread_cache 1617 static void create_inner_frame(MacroAssembler* masm, bool* already_created) { 1618 if (!*already_created) { 1619 __ save_frame(0); 1620 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below 1621 // Don't use save_thread because it smashes G2 and we merely want to save a 1622 // copy 1623 __ mov(G2_thread, L7_thread_cache); 1624 *already_created = true; 1625 } 1626 } 1627 1628 1629 static void save_or_restore_arguments(MacroAssembler* masm, 1630 const int stack_slots, 1631 const int total_in_args, 1632 const int arg_save_area, 1633 OopMap* map, 1634 VMRegPair* in_regs, 1635 BasicType* in_sig_bt) { 1636 // if map is non-NULL then the code should store the values, 1637 // otherwise it should load them. 1638 if (map != NULL) { 1639 // Fill in the map 1640 for (int i = 0; i < total_in_args; i++) { 1641 if (in_sig_bt[i] == T_ARRAY) { 1642 if (in_regs[i].first()->is_stack()) { 1643 int offset_in_older_frame = in_regs[i].first()->reg2stack() + SharedRuntime::out_preserve_stack_slots(); 1644 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + stack_slots)); 1645 } else if (in_regs[i].first()->is_Register()) { 1646 map->set_oop(in_regs[i].first()); 1647 } else { 1648 ShouldNotReachHere(); 1649 } 1650 } 1651 } 1652 } 1653 1654 // Save or restore double word values 1655 int handle_index = 0; 1656 for (int i = 0; i < total_in_args; i++) { 1657 int slot = handle_index + arg_save_area; 1658 int offset = slot * VMRegImpl::stack_slot_size; 1659 if (in_sig_bt[i] == T_LONG && in_regs[i].first()->is_Register()) { 1660 const Register reg = in_regs[i].first()->as_Register(); 1661 if (reg->is_global()) { 1662 handle_index += 2; 1663 assert(handle_index <= stack_slots, "overflow"); 1664 if (map != NULL) { 1665 __ stx(reg, SP, offset + STACK_BIAS); 1666 } else { 1667 __ ldx(SP, offset + STACK_BIAS, reg); 1668 } 1669 } 1670 } else if (in_sig_bt[i] == T_DOUBLE && in_regs[i].first()->is_FloatRegister()) { 1671 handle_index += 2; 1672 assert(handle_index <= stack_slots, "overflow"); 1673 if (map != NULL) { 1674 __ stf(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); 1675 } else { 1676 __ ldf(FloatRegisterImpl::D, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); 1677 } 1678 } 1679 } 1680 // Save floats 1681 for (int i = 0; i < total_in_args; i++) { 1682 int slot = handle_index + arg_save_area; 1683 int offset = slot * VMRegImpl::stack_slot_size; 1684 if (in_sig_bt[i] == T_FLOAT && in_regs[i].first()->is_FloatRegister()) { 1685 handle_index++; 1686 assert(handle_index <= stack_slots, "overflow"); 1687 if (map != NULL) { 1688 __ stf(FloatRegisterImpl::S, in_regs[i].first()->as_FloatRegister(), SP, offset + STACK_BIAS); 1689 } else { 1690 __ ldf(FloatRegisterImpl::S, SP, offset + STACK_BIAS, in_regs[i].first()->as_FloatRegister()); 1691 } 1692 } 1693 } 1694 1695 } 1696 1697 1698 // Check GC_locker::needs_gc and enter the runtime if it's true. This 1699 // keeps a new JNI critical region from starting until a GC has been 1700 // forced. Save down any oops in registers and describe them in an 1701 // OopMap. 1702 static void check_needs_gc_for_critical_native(MacroAssembler* masm, 1703 const int stack_slots, 1704 const int total_in_args, 1705 const int arg_save_area, 1706 OopMapSet* oop_maps, 1707 VMRegPair* in_regs, 1708 BasicType* in_sig_bt) { 1709 __ block_comment("check GC_locker::needs_gc"); 1710 Label cont; 1711 AddressLiteral sync_state(GC_locker::needs_gc_address()); 1712 __ load_bool_contents(sync_state, G3_scratch); 1713 __ cmp_zero_and_br(Assembler::equal, G3_scratch, cont); 1714 __ delayed()->nop(); 1715 1716 // Save down any values that are live in registers and call into the 1717 // runtime to halt for a GC 1718 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 1719 save_or_restore_arguments(masm, stack_slots, total_in_args, 1720 arg_save_area, map, in_regs, in_sig_bt); 1721 1722 __ mov(G2_thread, L7_thread_cache); 1723 1724 __ set_last_Java_frame(SP, noreg); 1725 1726 __ block_comment("block_for_jni_critical"); 1727 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::block_for_jni_critical), relocInfo::runtime_call_type); 1728 __ delayed()->mov(L7_thread_cache, O0); 1729 oop_maps->add_gc_map( __ offset(), map); 1730 1731 __ restore_thread(L7_thread_cache); // restore G2_thread 1732 __ reset_last_Java_frame(); 1733 1734 // Reload all the register arguments 1735 save_or_restore_arguments(masm, stack_slots, total_in_args, 1736 arg_save_area, NULL, in_regs, in_sig_bt); 1737 1738 __ bind(cont); 1739 #ifdef ASSERT 1740 if (StressCriticalJNINatives) { 1741 // Stress register saving 1742 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 1743 save_or_restore_arguments(masm, stack_slots, total_in_args, 1744 arg_save_area, map, in_regs, in_sig_bt); 1745 // Destroy argument registers 1746 for (int i = 0; i < total_in_args; i++) { 1747 if (in_regs[i].first()->is_Register()) { 1748 const Register reg = in_regs[i].first()->as_Register(); 1749 if (reg->is_global()) { 1750 __ mov(G0, reg); 1751 } 1752 } else if (in_regs[i].first()->is_FloatRegister()) { 1753 __ fneg(FloatRegisterImpl::D, in_regs[i].first()->as_FloatRegister(), in_regs[i].first()->as_FloatRegister()); 1754 } 1755 } 1756 1757 save_or_restore_arguments(masm, stack_slots, total_in_args, 1758 arg_save_area, NULL, in_regs, in_sig_bt); 1759 } 1760 #endif 1761 } 1762 1763 // Unpack an array argument into a pointer to the body and the length 1764 // if the array is non-null, otherwise pass 0 for both. 1765 static void unpack_array_argument(MacroAssembler* masm, VMRegPair reg, BasicType in_elem_type, VMRegPair body_arg, VMRegPair length_arg) { 1766 // Pass the length, ptr pair 1767 Label is_null, done; 1768 if (reg.first()->is_stack()) { 1769 VMRegPair tmp = reg64_to_VMRegPair(L2); 1770 // Load the arg up from the stack 1771 move_ptr(masm, reg, tmp); 1772 reg = tmp; 1773 } 1774 __ cmp(reg.first()->as_Register(), G0); 1775 __ brx(Assembler::equal, false, Assembler::pt, is_null); 1776 __ delayed()->add(reg.first()->as_Register(), arrayOopDesc::base_offset_in_bytes(in_elem_type), L4); 1777 move_ptr(masm, reg64_to_VMRegPair(L4), body_arg); 1778 __ ld(reg.first()->as_Register(), arrayOopDesc::length_offset_in_bytes(), L4); 1779 move32_64(masm, reg64_to_VMRegPair(L4), length_arg); 1780 __ ba_short(done); 1781 __ bind(is_null); 1782 // Pass zeros 1783 move_ptr(masm, reg64_to_VMRegPair(G0), body_arg); 1784 move32_64(masm, reg64_to_VMRegPair(G0), length_arg); 1785 __ bind(done); 1786 } 1787 1788 static void verify_oop_args(MacroAssembler* masm, 1789 methodHandle method, 1790 const BasicType* sig_bt, 1791 const VMRegPair* regs) { 1792 Register temp_reg = G5_method; // not part of any compiled calling seq 1793 if (VerifyOops) { 1794 for (int i = 0; i < method->size_of_parameters(); i++) { 1795 if (sig_bt[i] == T_OBJECT || 1796 sig_bt[i] == T_ARRAY) { 1797 VMReg r = regs[i].first(); 1798 assert(r->is_valid(), "bad oop arg"); 1799 if (r->is_stack()) { 1800 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; 1801 ld_off = __ ensure_simm13_or_reg(ld_off, temp_reg); 1802 __ ld_ptr(SP, ld_off, temp_reg); 1803 __ verify_oop(temp_reg); 1804 } else { 1805 __ verify_oop(r->as_Register()); 1806 } 1807 } 1808 } 1809 } 1810 } 1811 1812 static void gen_special_dispatch(MacroAssembler* masm, 1813 methodHandle method, 1814 const BasicType* sig_bt, 1815 const VMRegPair* regs) { 1816 verify_oop_args(masm, method, sig_bt, regs); 1817 vmIntrinsics::ID iid = method->intrinsic_id(); 1818 1819 // Now write the args into the outgoing interpreter space 1820 bool has_receiver = false; 1821 Register receiver_reg = noreg; 1822 int member_arg_pos = -1; 1823 Register member_reg = noreg; 1824 int ref_kind = MethodHandles::signature_polymorphic_intrinsic_ref_kind(iid); 1825 if (ref_kind != 0) { 1826 member_arg_pos = method->size_of_parameters() - 1; // trailing MemberName argument 1827 member_reg = G5_method; // known to be free at this point 1828 has_receiver = MethodHandles::ref_kind_has_receiver(ref_kind); 1829 } else if (iid == vmIntrinsics::_invokeBasic) { 1830 has_receiver = true; 1831 } else { 1832 fatal(err_msg_res("unexpected intrinsic id %d", iid)); 1833 } 1834 1835 if (member_reg != noreg) { 1836 // Load the member_arg into register, if necessary. 1837 SharedRuntime::check_member_name_argument_is_last_argument(method, sig_bt, regs); 1838 VMReg r = regs[member_arg_pos].first(); 1839 if (r->is_stack()) { 1840 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; 1841 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); 1842 __ ld_ptr(SP, ld_off, member_reg); 1843 } else { 1844 // no data motion is needed 1845 member_reg = r->as_Register(); 1846 } 1847 } 1848 1849 if (has_receiver) { 1850 // Make sure the receiver is loaded into a register. 1851 assert(method->size_of_parameters() > 0, "oob"); 1852 assert(sig_bt[0] == T_OBJECT, "receiver argument must be an object"); 1853 VMReg r = regs[0].first(); 1854 assert(r->is_valid(), "bad receiver arg"); 1855 if (r->is_stack()) { 1856 // Porting note: This assumes that compiled calling conventions always 1857 // pass the receiver oop in a register. If this is not true on some 1858 // platform, pick a temp and load the receiver from stack. 1859 fatal("receiver always in a register"); 1860 receiver_reg = G3_scratch; // known to be free at this point 1861 RegisterOrConstant ld_off = reg2offset(r) + STACK_BIAS; 1862 ld_off = __ ensure_simm13_or_reg(ld_off, member_reg); 1863 __ ld_ptr(SP, ld_off, receiver_reg); 1864 } else { 1865 // no data motion is needed 1866 receiver_reg = r->as_Register(); 1867 } 1868 } 1869 1870 // Figure out which address we are really jumping to: 1871 MethodHandles::generate_method_handle_dispatch(masm, iid, 1872 receiver_reg, member_reg, /*for_compiler_entry:*/ true); 1873 } 1874 1875 // --------------------------------------------------------------------------- 1876 // Generate a native wrapper for a given method. The method takes arguments 1877 // in the Java compiled code convention, marshals them to the native 1878 // convention (handlizes oops, etc), transitions to native, makes the call, 1879 // returns to java state (possibly blocking), unhandlizes any result and 1880 // returns. 1881 // 1882 // Critical native functions are a shorthand for the use of 1883 // GetPrimtiveArrayCritical and disallow the use of any other JNI 1884 // functions. The wrapper is expected to unpack the arguments before 1885 // passing them to the callee and perform checks before and after the 1886 // native call to ensure that they GC_locker 1887 // lock_critical/unlock_critical semantics are followed. Some other 1888 // parts of JNI setup are skipped like the tear down of the JNI handle 1889 // block and the check for pending exceptions it's impossible for them 1890 // to be thrown. 1891 // 1892 // They are roughly structured like this: 1893 // if (GC_locker::needs_gc()) 1894 // SharedRuntime::block_for_jni_critical(); 1895 // tranistion to thread_in_native 1896 // unpack arrray arguments and call native entry point 1897 // check for safepoint in progress 1898 // check if any thread suspend flags are set 1899 // call into JVM and possible unlock the JNI critical 1900 // if a GC was suppressed while in the critical native. 1901 // transition back to thread_in_Java 1902 // return to caller 1903 // 1904 nmethod* SharedRuntime::generate_native_wrapper(MacroAssembler* masm, 1905 methodHandle method, 1906 int compile_id, 1907 BasicType* in_sig_bt, 1908 VMRegPair* in_regs, 1909 BasicType ret_type) { 1910 if (method->is_method_handle_intrinsic()) { 1911 vmIntrinsics::ID iid = method->intrinsic_id(); 1912 intptr_t start = (intptr_t)__ pc(); 1913 int vep_offset = ((intptr_t)__ pc()) - start; 1914 gen_special_dispatch(masm, 1915 method, 1916 in_sig_bt, 1917 in_regs); 1918 int frame_complete = ((intptr_t)__ pc()) - start; // not complete, period 1919 __ flush(); 1920 int stack_slots = SharedRuntime::out_preserve_stack_slots(); // no out slots at all, actually 1921 return nmethod::new_native_nmethod(method, 1922 compile_id, 1923 masm->code(), 1924 vep_offset, 1925 frame_complete, 1926 stack_slots / VMRegImpl::slots_per_word, 1927 in_ByteSize(-1), 1928 in_ByteSize(-1), 1929 (OopMapSet*)NULL); 1930 } 1931 bool is_critical_native = true; 1932 address native_func = method->critical_native_function(); 1933 if (native_func == NULL) { 1934 native_func = method->native_function(); 1935 is_critical_native = false; 1936 } 1937 assert(native_func != NULL, "must have function"); 1938 1939 // Native nmethod wrappers never take possesion of the oop arguments. 1940 // So the caller will gc the arguments. The only thing we need an 1941 // oopMap for is if the call is static 1942 // 1943 // An OopMap for lock (and class if static), and one for the VM call itself 1944 OopMapSet *oop_maps = new OopMapSet(); 1945 intptr_t start = (intptr_t)__ pc(); 1946 1947 // First thing make an ic check to see if we should even be here 1948 { 1949 Label L; 1950 const Register temp_reg = G3_scratch; 1951 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); 1952 __ verify_oop(O0); 1953 __ load_klass(O0, temp_reg); 1954 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); 1955 1956 __ jump_to(ic_miss, temp_reg); 1957 __ delayed()->nop(); 1958 __ align(CodeEntryAlignment); 1959 __ bind(L); 1960 } 1961 1962 int vep_offset = ((intptr_t)__ pc()) - start; 1963 1964 #ifdef COMPILER1 1965 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) { 1966 // Object.hashCode can pull the hashCode from the header word 1967 // instead of doing a full VM transition once it's been computed. 1968 // Since hashCode is usually polymorphic at call sites we can't do 1969 // this optimization at the call site without a lot of work. 1970 Label slowCase; 1971 Register receiver = O0; 1972 Register result = O0; 1973 Register header = G3_scratch; 1974 Register hash = G3_scratch; // overwrite header value with hash value 1975 Register mask = G1; // to get hash field from header 1976 1977 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked. 1978 // We depend on hash_mask being at most 32 bits and avoid the use of 1979 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit 1980 // vm: see markOop.hpp. 1981 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header); 1982 __ sethi(markOopDesc::hash_mask, mask); 1983 __ btst(markOopDesc::unlocked_value, header); 1984 __ br(Assembler::zero, false, Assembler::pn, slowCase); 1985 if (UseBiasedLocking) { 1986 // Check if biased and fall through to runtime if so 1987 __ delayed()->nop(); 1988 __ btst(markOopDesc::biased_lock_bit_in_place, header); 1989 __ br(Assembler::notZero, false, Assembler::pn, slowCase); 1990 } 1991 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask); 1992 1993 // Check for a valid (non-zero) hash code and get its value. 1994 #ifdef _LP64 1995 __ srlx(header, markOopDesc::hash_shift, hash); 1996 #else 1997 __ srl(header, markOopDesc::hash_shift, hash); 1998 #endif 1999 __ andcc(hash, mask, hash); 2000 __ br(Assembler::equal, false, Assembler::pn, slowCase); 2001 __ delayed()->nop(); 2002 2003 // leaf return. 2004 __ retl(); 2005 __ delayed()->mov(hash, result); 2006 __ bind(slowCase); 2007 } 2008 #endif // COMPILER1 2009 2010 2011 // We have received a description of where all the java arg are located 2012 // on entry to the wrapper. We need to convert these args to where 2013 // the jni function will expect them. To figure out where they go 2014 // we convert the java signature to a C signature by inserting 2015 // the hidden arguments as arg[0] and possibly arg[1] (static method) 2016 2017 const int total_in_args = method->size_of_parameters(); 2018 int total_c_args = total_in_args; 2019 int total_save_slots = 6 * VMRegImpl::slots_per_word; 2020 if (!is_critical_native) { 2021 total_c_args += 1; 2022 if (method->is_static()) { 2023 total_c_args++; 2024 } 2025 } else { 2026 for (int i = 0; i < total_in_args; i++) { 2027 if (in_sig_bt[i] == T_ARRAY) { 2028 // These have to be saved and restored across the safepoint 2029 total_c_args++; 2030 } 2031 } 2032 } 2033 2034 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args); 2035 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args); 2036 BasicType* in_elem_bt = NULL; 2037 2038 int argc = 0; 2039 if (!is_critical_native) { 2040 out_sig_bt[argc++] = T_ADDRESS; 2041 if (method->is_static()) { 2042 out_sig_bt[argc++] = T_OBJECT; 2043 } 2044 2045 for (int i = 0; i < total_in_args ; i++ ) { 2046 out_sig_bt[argc++] = in_sig_bt[i]; 2047 } 2048 } else { 2049 Thread* THREAD = Thread::current(); 2050 in_elem_bt = NEW_RESOURCE_ARRAY(BasicType, total_in_args); 2051 SignatureStream ss(method->signature()); 2052 for (int i = 0; i < total_in_args ; i++ ) { 2053 if (in_sig_bt[i] == T_ARRAY) { 2054 // Arrays are passed as int, elem* pair 2055 out_sig_bt[argc++] = T_INT; 2056 out_sig_bt[argc++] = T_ADDRESS; 2057 Symbol* atype = ss.as_symbol(CHECK_NULL); 2058 const char* at = atype->as_C_string(); 2059 if (strlen(at) == 2) { 2060 assert(at[0] == '[', "must be"); 2061 switch (at[1]) { 2062 case 'B': in_elem_bt[i] = T_BYTE; break; 2063 case 'C': in_elem_bt[i] = T_CHAR; break; 2064 case 'D': in_elem_bt[i] = T_DOUBLE; break; 2065 case 'F': in_elem_bt[i] = T_FLOAT; break; 2066 case 'I': in_elem_bt[i] = T_INT; break; 2067 case 'J': in_elem_bt[i] = T_LONG; break; 2068 case 'S': in_elem_bt[i] = T_SHORT; break; 2069 case 'Z': in_elem_bt[i] = T_BOOLEAN; break; 2070 default: ShouldNotReachHere(); 2071 } 2072 } 2073 } else { 2074 out_sig_bt[argc++] = in_sig_bt[i]; 2075 in_elem_bt[i] = T_VOID; 2076 } 2077 if (in_sig_bt[i] != T_VOID) { 2078 assert(in_sig_bt[i] == ss.type(), "must match"); 2079 ss.next(); 2080 } 2081 } 2082 } 2083 2084 // Now figure out where the args must be stored and how much stack space 2085 // they require (neglecting out_preserve_stack_slots but space for storing 2086 // the 1st six register arguments). It's weird see int_stk_helper. 2087 // 2088 int out_arg_slots; 2089 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); 2090 2091 if (is_critical_native) { 2092 // Critical natives may have to call out so they need a save area 2093 // for register arguments. 2094 int double_slots = 0; 2095 int single_slots = 0; 2096 for ( int i = 0; i < total_in_args; i++) { 2097 if (in_regs[i].first()->is_Register()) { 2098 const Register reg = in_regs[i].first()->as_Register(); 2099 switch (in_sig_bt[i]) { 2100 case T_ARRAY: 2101 case T_BOOLEAN: 2102 case T_BYTE: 2103 case T_SHORT: 2104 case T_CHAR: 2105 case T_INT: assert(reg->is_in(), "don't need to save these"); break; 2106 case T_LONG: if (reg->is_global()) double_slots++; break; 2107 default: ShouldNotReachHere(); 2108 } 2109 } else if (in_regs[i].first()->is_FloatRegister()) { 2110 switch (in_sig_bt[i]) { 2111 case T_FLOAT: single_slots++; break; 2112 case T_DOUBLE: double_slots++; break; 2113 default: ShouldNotReachHere(); 2114 } 2115 } 2116 } 2117 total_save_slots = double_slots * 2 + single_slots; 2118 } 2119 2120 // Compute framesize for the wrapper. We need to handlize all oops in 2121 // registers. We must create space for them here that is disjoint from 2122 // the windowed save area because we have no control over when we might 2123 // flush the window again and overwrite values that gc has since modified. 2124 // (The live window race) 2125 // 2126 // We always just allocate 6 word for storing down these object. This allow 2127 // us to simply record the base and use the Ireg number to decide which 2128 // slot to use. (Note that the reg number is the inbound number not the 2129 // outbound number). 2130 // We must shuffle args to match the native convention, and include var-args space. 2131 2132 // Calculate the total number of stack slots we will need. 2133 2134 // First count the abi requirement plus all of the outgoing args 2135 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; 2136 2137 // Now the space for the inbound oop handle area 2138 2139 int oop_handle_offset = round_to(stack_slots, 2); 2140 stack_slots += total_save_slots; 2141 2142 // Now any space we need for handlizing a klass if static method 2143 2144 int klass_slot_offset = 0; 2145 int klass_offset = -1; 2146 int lock_slot_offset = 0; 2147 bool is_static = false; 2148 2149 if (method->is_static()) { 2150 klass_slot_offset = stack_slots; 2151 stack_slots += VMRegImpl::slots_per_word; 2152 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size; 2153 is_static = true; 2154 } 2155 2156 // Plus a lock if needed 2157 2158 if (method->is_synchronized()) { 2159 lock_slot_offset = stack_slots; 2160 stack_slots += VMRegImpl::slots_per_word; 2161 } 2162 2163 // Now a place to save return value or as a temporary for any gpr -> fpr moves 2164 stack_slots += 2; 2165 2166 // Ok The space we have allocated will look like: 2167 // 2168 // 2169 // FP-> | | 2170 // |---------------------| 2171 // | 2 slots for moves | 2172 // |---------------------| 2173 // | lock box (if sync) | 2174 // |---------------------| <- lock_slot_offset 2175 // | klass (if static) | 2176 // |---------------------| <- klass_slot_offset 2177 // | oopHandle area | 2178 // |---------------------| <- oop_handle_offset 2179 // | outbound memory | 2180 // | based arguments | 2181 // | | 2182 // |---------------------| 2183 // | vararg area | 2184 // |---------------------| 2185 // | | 2186 // SP-> | out_preserved_slots | 2187 // 2188 // 2189 2190 2191 // Now compute actual number of stack words we need rounding to make 2192 // stack properly aligned. 2193 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word); 2194 2195 int stack_size = stack_slots * VMRegImpl::stack_slot_size; 2196 2197 // Generate stack overflow check before creating frame 2198 __ generate_stack_overflow_check(stack_size); 2199 2200 // Generate a new frame for the wrapper. 2201 __ save(SP, -stack_size, SP); 2202 2203 int frame_complete = ((intptr_t)__ pc()) - start; 2204 2205 __ verify_thread(); 2206 2207 if (is_critical_native) { 2208 check_needs_gc_for_critical_native(masm, stack_slots, total_in_args, 2209 oop_handle_offset, oop_maps, in_regs, in_sig_bt); 2210 } 2211 2212 // 2213 // We immediately shuffle the arguments so that any vm call we have to 2214 // make from here on out (sync slow path, jvmti, etc.) we will have 2215 // captured the oops from our caller and have a valid oopMap for 2216 // them. 2217 2218 // ----------------- 2219 // The Grand Shuffle 2220 // 2221 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv* 2222 // (derived from JavaThread* which is in L7_thread_cache) and, if static, 2223 // the class mirror instead of a receiver. This pretty much guarantees that 2224 // register layout will not match. We ignore these extra arguments during 2225 // the shuffle. The shuffle is described by the two calling convention 2226 // vectors we have in our possession. We simply walk the java vector to 2227 // get the source locations and the c vector to get the destinations. 2228 // Because we have a new window and the argument registers are completely 2229 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about 2230 // here. 2231 2232 // This is a trick. We double the stack slots so we can claim 2233 // the oops in the caller's frame. Since we are sure to have 2234 // more args than the caller doubling is enough to make 2235 // sure we can capture all the incoming oop args from the 2236 // caller. 2237 // 2238 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/); 2239 // Record sp-based slot for receiver on stack for non-static methods 2240 int receiver_offset = -1; 2241 2242 // We move the arguments backward because the floating point registers 2243 // destination will always be to a register with a greater or equal register 2244 // number or the stack. 2245 2246 #ifdef ASSERT 2247 bool reg_destroyed[RegisterImpl::number_of_registers]; 2248 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; 2249 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { 2250 reg_destroyed[r] = false; 2251 } 2252 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { 2253 freg_destroyed[f] = false; 2254 } 2255 2256 #endif /* ASSERT */ 2257 2258 for ( int i = total_in_args - 1, c_arg = total_c_args - 1; i >= 0 ; i--, c_arg-- ) { 2259 2260 #ifdef ASSERT 2261 if (in_regs[i].first()->is_Register()) { 2262 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!"); 2263 } else if (in_regs[i].first()->is_FloatRegister()) { 2264 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!"); 2265 } 2266 if (out_regs[c_arg].first()->is_Register()) { 2267 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true; 2268 } else if (out_regs[c_arg].first()->is_FloatRegister()) { 2269 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true; 2270 } 2271 #endif /* ASSERT */ 2272 2273 switch (in_sig_bt[i]) { 2274 case T_ARRAY: 2275 if (is_critical_native) { 2276 unpack_array_argument(masm, in_regs[i], in_elem_bt[i], out_regs[c_arg], out_regs[c_arg - 1]); 2277 c_arg--; 2278 break; 2279 } 2280 case T_OBJECT: 2281 assert(!is_critical_native, "no oop arguments"); 2282 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg], 2283 ((i == 0) && (!is_static)), 2284 &receiver_offset); 2285 break; 2286 case T_VOID: 2287 break; 2288 2289 case T_FLOAT: 2290 float_move(masm, in_regs[i], out_regs[c_arg]); 2291 break; 2292 2293 case T_DOUBLE: 2294 assert( i + 1 < total_in_args && 2295 in_sig_bt[i + 1] == T_VOID && 2296 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); 2297 double_move(masm, in_regs[i], out_regs[c_arg]); 2298 break; 2299 2300 case T_LONG : 2301 long_move(masm, in_regs[i], out_regs[c_arg]); 2302 break; 2303 2304 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); 2305 2306 default: 2307 move32_64(masm, in_regs[i], out_regs[c_arg]); 2308 } 2309 } 2310 2311 // Pre-load a static method's oop into O1. Used both by locking code and 2312 // the normal JNI call code. 2313 if (method->is_static() && !is_critical_native) { 2314 __ set_oop_constant(JNIHandles::make_local(method->method_holder()->java_mirror()), O1); 2315 2316 // Now handlize the static class mirror in O1. It's known not-null. 2317 __ st_ptr(O1, SP, klass_offset + STACK_BIAS); 2318 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset)); 2319 __ add(SP, klass_offset + STACK_BIAS, O1); 2320 } 2321 2322 2323 const Register L6_handle = L6; 2324 2325 if (method->is_synchronized()) { 2326 assert(!is_critical_native, "unhandled"); 2327 __ mov(O1, L6_handle); 2328 } 2329 2330 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs 2331 // except O6/O7. So if we must call out we must push a new frame. We immediately 2332 // push a new frame and flush the windows. 2333 #ifdef _LP64 2334 intptr_t thepc = (intptr_t) __ pc(); 2335 { 2336 address here = __ pc(); 2337 // Call the next instruction 2338 __ call(here + 8, relocInfo::none); 2339 __ delayed()->nop(); 2340 } 2341 #else 2342 intptr_t thepc = __ load_pc_address(O7, 0); 2343 #endif /* _LP64 */ 2344 2345 // We use the same pc/oopMap repeatedly when we call out 2346 oop_maps->add_gc_map(thepc - start, map); 2347 2348 // O7 now has the pc loaded that we will use when we finally call to native. 2349 2350 // Save thread in L7; it crosses a bunch of VM calls below 2351 // Don't use save_thread because it smashes G2 and we merely 2352 // want to save a copy 2353 __ mov(G2_thread, L7_thread_cache); 2354 2355 2356 // If we create an inner frame once is plenty 2357 // when we create it we must also save G2_thread 2358 bool inner_frame_created = false; 2359 2360 // dtrace method entry support 2361 { 2362 SkipIfEqual skip_if( 2363 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); 2364 // create inner frame 2365 __ save_frame(0); 2366 __ mov(G2_thread, L7_thread_cache); 2367 __ set_metadata_constant(method(), O1); 2368 __ call_VM_leaf(L7_thread_cache, 2369 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry), 2370 G2_thread, O1); 2371 __ restore(); 2372 } 2373 2374 // RedefineClasses() tracing support for obsolete method entry 2375 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) { 2376 // create inner frame 2377 __ save_frame(0); 2378 __ mov(G2_thread, L7_thread_cache); 2379 __ set_metadata_constant(method(), O1); 2380 __ call_VM_leaf(L7_thread_cache, 2381 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry), 2382 G2_thread, O1); 2383 __ restore(); 2384 } 2385 2386 // We are in the jni frame unless saved_frame is true in which case 2387 // we are in one frame deeper (the "inner" frame). If we are in the 2388 // "inner" frames the args are in the Iregs and if the jni frame then 2389 // they are in the Oregs. 2390 // If we ever need to go to the VM (for locking, jvmti) then 2391 // we will always be in the "inner" frame. 2392 2393 // Lock a synchronized method 2394 int lock_offset = -1; // Set if locked 2395 if (method->is_synchronized()) { 2396 Register Roop = O1; 2397 const Register L3_box = L3; 2398 2399 create_inner_frame(masm, &inner_frame_created); 2400 2401 __ ld_ptr(I1, 0, O1); 2402 Label done; 2403 2404 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size); 2405 __ add(FP, lock_offset+STACK_BIAS, L3_box); 2406 #ifdef ASSERT 2407 if (UseBiasedLocking) { 2408 // making the box point to itself will make it clear it went unused 2409 // but also be obviously invalid 2410 __ st_ptr(L3_box, L3_box, 0); 2411 } 2412 #endif // ASSERT 2413 // 2414 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch 2415 // 2416 __ compiler_lock_object(Roop, L1, L3_box, L2); 2417 __ br(Assembler::equal, false, Assembler::pt, done); 2418 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box); 2419 2420 2421 // None of the above fast optimizations worked so we have to get into the 2422 // slow case of monitor enter. Inline a special case of call_VM that 2423 // disallows any pending_exception. 2424 __ mov(Roop, O0); // Need oop in O0 2425 __ mov(L3_box, O1); 2426 2427 // Record last_Java_sp, in case the VM code releases the JVM lock. 2428 2429 __ set_last_Java_frame(FP, I7); 2430 2431 // do the call 2432 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type); 2433 __ delayed()->mov(L7_thread_cache, O2); 2434 2435 __ restore_thread(L7_thread_cache); // restore G2_thread 2436 __ reset_last_Java_frame(); 2437 2438 #ifdef ASSERT 2439 { Label L; 2440 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); 2441 __ br_null_short(O0, Assembler::pt, L); 2442 __ stop("no pending exception allowed on exit from IR::monitorenter"); 2443 __ bind(L); 2444 } 2445 #endif 2446 __ bind(done); 2447 } 2448 2449 2450 // Finally just about ready to make the JNI call 2451 2452 __ flushw(); 2453 if (inner_frame_created) { 2454 __ restore(); 2455 } else { 2456 // Store only what we need from this frame 2457 // QQQ I think that non-v9 (like we care) we don't need these saves 2458 // either as the flush traps and the current window goes too. 2459 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS); 2460 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS); 2461 } 2462 2463 // get JNIEnv* which is first argument to native 2464 if (!is_critical_native) { 2465 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0); 2466 } 2467 2468 // Use that pc we placed in O7 a while back as the current frame anchor 2469 __ set_last_Java_frame(SP, O7); 2470 2471 // We flushed the windows ages ago now mark them as flushed before transitioning. 2472 __ set(JavaFrameAnchor::flushed, G3_scratch); 2473 __ st(G3_scratch, G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset()); 2474 2475 // Transition from _thread_in_Java to _thread_in_native. 2476 __ set(_thread_in_native, G3_scratch); 2477 2478 #ifdef _LP64 2479 AddressLiteral dest(native_func); 2480 __ relocate(relocInfo::runtime_call_type); 2481 __ jumpl_to(dest, O7, O7); 2482 #else 2483 __ call(native_func, relocInfo::runtime_call_type); 2484 #endif 2485 __ delayed()->st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); 2486 2487 __ restore_thread(L7_thread_cache); // restore G2_thread 2488 2489 // Unpack native results. For int-types, we do any needed sign-extension 2490 // and move things into I0. The return value there will survive any VM 2491 // calls for blocking or unlocking. An FP or OOP result (handle) is done 2492 // specially in the slow-path code. 2493 switch (ret_type) { 2494 case T_VOID: break; // Nothing to do! 2495 case T_FLOAT: break; // Got it where we want it (unless slow-path) 2496 case T_DOUBLE: break; // Got it where we want it (unless slow-path) 2497 // In 64 bits build result is in O0, in O0, O1 in 32bit build 2498 case T_LONG: 2499 #ifndef _LP64 2500 __ mov(O1, I1); 2501 #endif 2502 // Fall thru 2503 case T_OBJECT: // Really a handle 2504 case T_ARRAY: 2505 case T_INT: 2506 __ mov(O0, I0); 2507 break; 2508 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false 2509 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break; 2510 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value! 2511 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break; 2512 break; // Cannot de-handlize until after reclaiming jvm_lock 2513 default: 2514 ShouldNotReachHere(); 2515 } 2516 2517 Label after_transition; 2518 // must we block? 2519 2520 // Block, if necessary, before resuming in _thread_in_Java state. 2521 // In order for GC to work, don't clear the last_Java_sp until after blocking. 2522 { Label no_block; 2523 AddressLiteral sync_state(SafepointSynchronize::address_of_state()); 2524 2525 // Switch thread to "native transition" state before reading the synchronization state. 2526 // This additional state is necessary because reading and testing the synchronization 2527 // state is not atomic w.r.t. GC, as this scenario demonstrates: 2528 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted. 2529 // VM thread changes sync state to synchronizing and suspends threads for GC. 2530 // Thread A is resumed to finish this native method, but doesn't block here since it 2531 // didn't see any synchronization is progress, and escapes. 2532 __ set(_thread_in_native_trans, G3_scratch); 2533 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); 2534 if(os::is_MP()) { 2535 if (UseMembar) { 2536 // Force this write out before the read below 2537 __ membar(Assembler::StoreLoad); 2538 } else { 2539 // Write serialization page so VM thread can do a pseudo remote membar. 2540 // We use the current thread pointer to calculate a thread specific 2541 // offset to write to within the page. This minimizes bus traffic 2542 // due to cache line collision. 2543 __ serialize_memory(G2_thread, G1_scratch, G3_scratch); 2544 } 2545 } 2546 __ load_contents(sync_state, G3_scratch); 2547 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized); 2548 2549 Label L; 2550 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset()); 2551 __ br(Assembler::notEqual, false, Assembler::pn, L); 2552 __ delayed()->ld(suspend_state, G3_scratch); 2553 __ cmp_and_br_short(G3_scratch, 0, Assembler::equal, Assembler::pt, no_block); 2554 __ bind(L); 2555 2556 // Block. Save any potential method result value before the operation and 2557 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this 2558 // lets us share the oopMap we used when we went native rather the create 2559 // a distinct one for this pc 2560 // 2561 save_native_result(masm, ret_type, stack_slots); 2562 if (!is_critical_native) { 2563 __ call_VM_leaf(L7_thread_cache, 2564 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans), 2565 G2_thread); 2566 } else { 2567 __ call_VM_leaf(L7_thread_cache, 2568 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans_and_transition), 2569 G2_thread); 2570 } 2571 2572 // Restore any method result value 2573 restore_native_result(masm, ret_type, stack_slots); 2574 2575 if (is_critical_native) { 2576 // The call above performed the transition to thread_in_Java so 2577 // skip the transition logic below. 2578 __ ba(after_transition); 2579 __ delayed()->nop(); 2580 } 2581 2582 __ bind(no_block); 2583 } 2584 2585 // thread state is thread_in_native_trans. Any safepoint blocking has already 2586 // happened so we can now change state to _thread_in_Java. 2587 __ set(_thread_in_Java, G3_scratch); 2588 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset()); 2589 __ bind(after_transition); 2590 2591 Label no_reguard; 2592 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch); 2593 __ cmp_and_br_short(G3_scratch, JavaThread::stack_guard_yellow_disabled, Assembler::notEqual, Assembler::pt, no_reguard); 2594 2595 save_native_result(masm, ret_type, stack_slots); 2596 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages)); 2597 __ delayed()->nop(); 2598 2599 __ restore_thread(L7_thread_cache); // restore G2_thread 2600 restore_native_result(masm, ret_type, stack_slots); 2601 2602 __ bind(no_reguard); 2603 2604 // Handle possible exception (will unlock if necessary) 2605 2606 // native result if any is live in freg or I0 (and I1 if long and 32bit vm) 2607 2608 // Unlock 2609 if (method->is_synchronized()) { 2610 Label done; 2611 Register I2_ex_oop = I2; 2612 const Register L3_box = L3; 2613 // Get locked oop from the handle we passed to jni 2614 __ ld_ptr(L6_handle, 0, L4); 2615 __ add(SP, lock_offset+STACK_BIAS, L3_box); 2616 // Must save pending exception around the slow-path VM call. Since it's a 2617 // leaf call, the pending exception (if any) can be kept in a register. 2618 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop); 2619 // Now unlock 2620 // (Roop, Rmark, Rbox, Rscratch) 2621 __ compiler_unlock_object(L4, L1, L3_box, L2); 2622 __ br(Assembler::equal, false, Assembler::pt, done); 2623 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box); 2624 2625 // save and restore any potential method result value around the unlocking 2626 // operation. Will save in I0 (or stack for FP returns). 2627 save_native_result(masm, ret_type, stack_slots); 2628 2629 // Must clear pending-exception before re-entering the VM. Since this is 2630 // a leaf call, pending-exception-oop can be safely kept in a register. 2631 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset())); 2632 2633 // slow case of monitor enter. Inline a special case of call_VM that 2634 // disallows any pending_exception. 2635 __ mov(L3_box, O1); 2636 2637 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type); 2638 __ delayed()->mov(L4, O0); // Need oop in O0 2639 2640 __ restore_thread(L7_thread_cache); // restore G2_thread 2641 2642 #ifdef ASSERT 2643 { Label L; 2644 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0); 2645 __ br_null_short(O0, Assembler::pt, L); 2646 __ stop("no pending exception allowed on exit from IR::monitorexit"); 2647 __ bind(L); 2648 } 2649 #endif 2650 restore_native_result(masm, ret_type, stack_slots); 2651 // check_forward_pending_exception jump to forward_exception if any pending 2652 // exception is set. The forward_exception routine expects to see the 2653 // exception in pending_exception and not in a register. Kind of clumsy, 2654 // since all folks who branch to forward_exception must have tested 2655 // pending_exception first and hence have it in a register already. 2656 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset())); 2657 __ bind(done); 2658 } 2659 2660 // Tell dtrace about this method exit 2661 { 2662 SkipIfEqual skip_if( 2663 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero); 2664 save_native_result(masm, ret_type, stack_slots); 2665 __ set_metadata_constant(method(), O1); 2666 __ call_VM_leaf(L7_thread_cache, 2667 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), 2668 G2_thread, O1); 2669 restore_native_result(masm, ret_type, stack_slots); 2670 } 2671 2672 // Clear "last Java frame" SP and PC. 2673 __ verify_thread(); // G2_thread must be correct 2674 __ reset_last_Java_frame(); 2675 2676 // Unpack oop result 2677 if (ret_type == T_OBJECT || ret_type == T_ARRAY) { 2678 Label L; 2679 __ addcc(G0, I0, G0); 2680 __ brx(Assembler::notZero, true, Assembler::pt, L); 2681 __ delayed()->ld_ptr(I0, 0, I0); 2682 __ mov(G0, I0); 2683 __ bind(L); 2684 __ verify_oop(I0); 2685 } 2686 2687 if (!is_critical_native) { 2688 // reset handle block 2689 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5); 2690 __ st(G0, L5, JNIHandleBlock::top_offset_in_bytes()); 2691 2692 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch); 2693 check_forward_pending_exception(masm, G3_scratch); 2694 } 2695 2696 2697 // Return 2698 2699 #ifndef _LP64 2700 if (ret_type == T_LONG) { 2701 2702 // Must leave proper result in O0,O1 and G1 (c2/tiered only) 2703 __ sllx(I0, 32, G1); // Shift bits into high G1 2704 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) 2705 __ or3 (I1, G1, G1); // OR 64 bits into G1 2706 } 2707 #endif 2708 2709 __ ret(); 2710 __ delayed()->restore(); 2711 2712 __ flush(); 2713 2714 nmethod *nm = nmethod::new_native_nmethod(method, 2715 compile_id, 2716 masm->code(), 2717 vep_offset, 2718 frame_complete, 2719 stack_slots / VMRegImpl::slots_per_word, 2720 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)), 2721 in_ByteSize(lock_offset), 2722 oop_maps); 2723 2724 if (is_critical_native) { 2725 nm->set_lazy_critical_native(true); 2726 } 2727 return nm; 2728 2729 } 2730 2731 #ifdef HAVE_DTRACE_H 2732 // --------------------------------------------------------------------------- 2733 // Generate a dtrace nmethod for a given signature. The method takes arguments 2734 // in the Java compiled code convention, marshals them to the native 2735 // abi and then leaves nops at the position you would expect to call a native 2736 // function. When the probe is enabled the nops are replaced with a trap 2737 // instruction that dtrace inserts and the trace will cause a notification 2738 // to dtrace. 2739 // 2740 // The probes are only able to take primitive types and java/lang/String as 2741 // arguments. No other java types are allowed. Strings are converted to utf8 2742 // strings so that from dtrace point of view java strings are converted to C 2743 // strings. There is an arbitrary fixed limit on the total space that a method 2744 // can use for converting the strings. (256 chars per string in the signature). 2745 // So any java string larger then this is truncated. 2746 2747 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 }; 2748 static bool offsets_initialized = false; 2749 2750 nmethod *SharedRuntime::generate_dtrace_nmethod( 2751 MacroAssembler *masm, methodHandle method) { 2752 2753 2754 // generate_dtrace_nmethod is guarded by a mutex so we are sure to 2755 // be single threaded in this method. 2756 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be"); 2757 2758 // Fill in the signature array, for the calling-convention call. 2759 int total_args_passed = method->size_of_parameters(); 2760 2761 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed); 2762 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed); 2763 2764 // The signature we are going to use for the trap that dtrace will see 2765 // java/lang/String is converted. We drop "this" and any other object 2766 // is converted to NULL. (A one-slot java/lang/Long object reference 2767 // is converted to a two-slot long, which is why we double the allocation). 2768 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2); 2769 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2); 2770 2771 int i=0; 2772 int total_strings = 0; 2773 int first_arg_to_pass = 0; 2774 int total_c_args = 0; 2775 2776 // Skip the receiver as dtrace doesn't want to see it 2777 if( !method->is_static() ) { 2778 in_sig_bt[i++] = T_OBJECT; 2779 first_arg_to_pass = 1; 2780 } 2781 2782 SignatureStream ss(method->signature()); 2783 for ( ; !ss.at_return_type(); ss.next()) { 2784 BasicType bt = ss.type(); 2785 in_sig_bt[i++] = bt; // Collect remaining bits of signature 2786 out_sig_bt[total_c_args++] = bt; 2787 if( bt == T_OBJECT) { 2788 Symbol* s = ss.as_symbol_or_null(); 2789 if (s == vmSymbols::java_lang_String()) { 2790 total_strings++; 2791 out_sig_bt[total_c_args-1] = T_ADDRESS; 2792 } else if (s == vmSymbols::java_lang_Boolean() || 2793 s == vmSymbols::java_lang_Byte()) { 2794 out_sig_bt[total_c_args-1] = T_BYTE; 2795 } else if (s == vmSymbols::java_lang_Character() || 2796 s == vmSymbols::java_lang_Short()) { 2797 out_sig_bt[total_c_args-1] = T_SHORT; 2798 } else if (s == vmSymbols::java_lang_Integer() || 2799 s == vmSymbols::java_lang_Float()) { 2800 out_sig_bt[total_c_args-1] = T_INT; 2801 } else if (s == vmSymbols::java_lang_Long() || 2802 s == vmSymbols::java_lang_Double()) { 2803 out_sig_bt[total_c_args-1] = T_LONG; 2804 out_sig_bt[total_c_args++] = T_VOID; 2805 } 2806 } else if ( bt == T_LONG || bt == T_DOUBLE ) { 2807 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots 2808 // We convert double to long 2809 out_sig_bt[total_c_args-1] = T_LONG; 2810 out_sig_bt[total_c_args++] = T_VOID; 2811 } else if ( bt == T_FLOAT) { 2812 // We convert float to int 2813 out_sig_bt[total_c_args-1] = T_INT; 2814 } 2815 } 2816 2817 assert(i==total_args_passed, "validly parsed signature"); 2818 2819 // Now get the compiled-Java layout as input arguments 2820 int comp_args_on_stack; 2821 comp_args_on_stack = SharedRuntime::java_calling_convention( 2822 in_sig_bt, in_regs, total_args_passed, false); 2823 2824 // We have received a description of where all the java arg are located 2825 // on entry to the wrapper. We need to convert these args to where 2826 // the a native (non-jni) function would expect them. To figure out 2827 // where they go we convert the java signature to a C signature and remove 2828 // T_VOID for any long/double we might have received. 2829 2830 2831 // Now figure out where the args must be stored and how much stack space 2832 // they require (neglecting out_preserve_stack_slots but space for storing 2833 // the 1st six register arguments). It's weird see int_stk_helper. 2834 // 2835 int out_arg_slots; 2836 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, NULL, total_c_args); 2837 2838 // Calculate the total number of stack slots we will need. 2839 2840 // First count the abi requirement plus all of the outgoing args 2841 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots; 2842 2843 // Plus a temp for possible converion of float/double/long register args 2844 2845 int conversion_temp = stack_slots; 2846 stack_slots += 2; 2847 2848 2849 // Now space for the string(s) we must convert 2850 2851 int string_locs = stack_slots; 2852 stack_slots += total_strings * 2853 (max_dtrace_string_size / VMRegImpl::stack_slot_size); 2854 2855 // Ok The space we have allocated will look like: 2856 // 2857 // 2858 // FP-> | | 2859 // |---------------------| 2860 // | string[n] | 2861 // |---------------------| <- string_locs[n] 2862 // | string[n-1] | 2863 // |---------------------| <- string_locs[n-1] 2864 // | ... | 2865 // | ... | 2866 // |---------------------| <- string_locs[1] 2867 // | string[0] | 2868 // |---------------------| <- string_locs[0] 2869 // | temp | 2870 // |---------------------| <- conversion_temp 2871 // | outbound memory | 2872 // | based arguments | 2873 // | | 2874 // |---------------------| 2875 // | | 2876 // SP-> | out_preserved_slots | 2877 // 2878 // 2879 2880 // Now compute actual number of stack words we need rounding to make 2881 // stack properly aligned. 2882 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word); 2883 2884 int stack_size = stack_slots * VMRegImpl::stack_slot_size; 2885 2886 intptr_t start = (intptr_t)__ pc(); 2887 2888 // First thing make an ic check to see if we should even be here 2889 2890 { 2891 Label L; 2892 const Register temp_reg = G3_scratch; 2893 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub()); 2894 __ verify_oop(O0); 2895 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg); 2896 __ cmp_and_brx_short(temp_reg, G5_inline_cache_reg, Assembler::equal, Assembler::pt, L); 2897 2898 __ jump_to(ic_miss, temp_reg); 2899 __ delayed()->nop(); 2900 __ align(CodeEntryAlignment); 2901 __ bind(L); 2902 } 2903 2904 int vep_offset = ((intptr_t)__ pc()) - start; 2905 2906 2907 // The instruction at the verified entry point must be 5 bytes or longer 2908 // because it can be patched on the fly by make_non_entrant. The stack bang 2909 // instruction fits that requirement. 2910 2911 // Generate stack overflow check before creating frame 2912 __ generate_stack_overflow_check(stack_size); 2913 2914 assert(((intptr_t)__ pc() - start - vep_offset) >= 5, 2915 "valid size for make_non_entrant"); 2916 2917 // Generate a new frame for the wrapper. 2918 __ save(SP, -stack_size, SP); 2919 2920 // Frame is now completed as far a size and linkage. 2921 2922 int frame_complete = ((intptr_t)__ pc()) - start; 2923 2924 #ifdef ASSERT 2925 bool reg_destroyed[RegisterImpl::number_of_registers]; 2926 bool freg_destroyed[FloatRegisterImpl::number_of_registers]; 2927 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) { 2928 reg_destroyed[r] = false; 2929 } 2930 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) { 2931 freg_destroyed[f] = false; 2932 } 2933 2934 #endif /* ASSERT */ 2935 2936 VMRegPair zero; 2937 const Register g0 = G0; // without this we get a compiler warning (why??) 2938 zero.set2(g0->as_VMReg()); 2939 2940 int c_arg, j_arg; 2941 2942 Register conversion_off = noreg; 2943 2944 for (j_arg = first_arg_to_pass, c_arg = 0 ; 2945 j_arg < total_args_passed ; j_arg++, c_arg++ ) { 2946 2947 VMRegPair src = in_regs[j_arg]; 2948 VMRegPair dst = out_regs[c_arg]; 2949 2950 #ifdef ASSERT 2951 if (src.first()->is_Register()) { 2952 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!"); 2953 } else if (src.first()->is_FloatRegister()) { 2954 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding( 2955 FloatRegisterImpl::S)], "ack!"); 2956 } 2957 if (dst.first()->is_Register()) { 2958 reg_destroyed[dst.first()->as_Register()->encoding()] = true; 2959 } else if (dst.first()->is_FloatRegister()) { 2960 freg_destroyed[dst.first()->as_FloatRegister()->encoding( 2961 FloatRegisterImpl::S)] = true; 2962 } 2963 #endif /* ASSERT */ 2964 2965 switch (in_sig_bt[j_arg]) { 2966 case T_ARRAY: 2967 case T_OBJECT: 2968 { 2969 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT || 2970 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) { 2971 // need to unbox a one-slot value 2972 Register in_reg = L0; 2973 Register tmp = L2; 2974 if ( src.first()->is_reg() ) { 2975 in_reg = src.first()->as_Register(); 2976 } else { 2977 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS), 2978 "must be"); 2979 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg); 2980 } 2981 // If the final destination is an acceptable register 2982 if ( dst.first()->is_reg() ) { 2983 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) { 2984 tmp = dst.first()->as_Register(); 2985 } 2986 } 2987 2988 Label skipUnbox; 2989 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) { 2990 __ mov(G0, tmp->successor()); 2991 } 2992 __ br_null(in_reg, true, Assembler::pn, skipUnbox); 2993 __ delayed()->mov(G0, tmp); 2994 2995 BasicType bt = out_sig_bt[c_arg]; 2996 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt); 2997 switch (bt) { 2998 case T_BYTE: 2999 __ ldub(in_reg, box_offset, tmp); break; 3000 case T_SHORT: 3001 __ lduh(in_reg, box_offset, tmp); break; 3002 case T_INT: 3003 __ ld(in_reg, box_offset, tmp); break; 3004 case T_LONG: 3005 __ ld_long(in_reg, box_offset, tmp); break; 3006 default: ShouldNotReachHere(); 3007 } 3008 3009 __ bind(skipUnbox); 3010 // If tmp wasn't final destination copy to final destination 3011 if (tmp == L2) { 3012 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2); 3013 if (out_sig_bt[c_arg] == T_LONG) { 3014 long_move(masm, tmp_as_VM, dst); 3015 } else { 3016 move32_64(masm, tmp_as_VM, out_regs[c_arg]); 3017 } 3018 } 3019 if (out_sig_bt[c_arg] == T_LONG) { 3020 assert(out_sig_bt[c_arg+1] == T_VOID, "must be"); 3021 ++c_arg; // move over the T_VOID to keep the loop indices in sync 3022 } 3023 } else if (out_sig_bt[c_arg] == T_ADDRESS) { 3024 Register s = 3025 src.first()->is_reg() ? src.first()->as_Register() : L2; 3026 Register d = 3027 dst.first()->is_reg() ? dst.first()->as_Register() : L2; 3028 3029 // We store the oop now so that the conversion pass can reach 3030 // while in the inner frame. This will be the only store if 3031 // the oop is NULL. 3032 if (s != L2) { 3033 // src is register 3034 if (d != L2) { 3035 // dst is register 3036 __ mov(s, d); 3037 } else { 3038 assert(Assembler::is_simm13(reg2offset(dst.first()) + 3039 STACK_BIAS), "must be"); 3040 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS); 3041 } 3042 } else { 3043 // src not a register 3044 assert(Assembler::is_simm13(reg2offset(src.first()) + 3045 STACK_BIAS), "must be"); 3046 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d); 3047 if (d == L2) { 3048 assert(Assembler::is_simm13(reg2offset(dst.first()) + 3049 STACK_BIAS), "must be"); 3050 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS); 3051 } 3052 } 3053 } else if (out_sig_bt[c_arg] != T_VOID) { 3054 // Convert the arg to NULL 3055 if (dst.first()->is_reg()) { 3056 __ mov(G0, dst.first()->as_Register()); 3057 } else { 3058 assert(Assembler::is_simm13(reg2offset(dst.first()) + 3059 STACK_BIAS), "must be"); 3060 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS); 3061 } 3062 } 3063 } 3064 break; 3065 case T_VOID: 3066 break; 3067 3068 case T_FLOAT: 3069 if (src.first()->is_stack()) { 3070 // Stack to stack/reg is simple 3071 move32_64(masm, src, dst); 3072 } else { 3073 if (dst.first()->is_reg()) { 3074 // freg -> reg 3075 int off = 3076 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; 3077 Register d = dst.first()->as_Register(); 3078 if (Assembler::is_simm13(off)) { 3079 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), 3080 SP, off); 3081 __ ld(SP, off, d); 3082 } else { 3083 if (conversion_off == noreg) { 3084 __ set(off, L6); 3085 conversion_off = L6; 3086 } 3087 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), 3088 SP, conversion_off); 3089 __ ld(SP, conversion_off , d); 3090 } 3091 } else { 3092 // freg -> mem 3093 int off = STACK_BIAS + reg2offset(dst.first()); 3094 if (Assembler::is_simm13(off)) { 3095 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), 3096 SP, off); 3097 } else { 3098 if (conversion_off == noreg) { 3099 __ set(off, L6); 3100 conversion_off = L6; 3101 } 3102 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), 3103 SP, conversion_off); 3104 } 3105 } 3106 } 3107 break; 3108 3109 case T_DOUBLE: 3110 assert( j_arg + 1 < total_args_passed && 3111 in_sig_bt[j_arg + 1] == T_VOID && 3112 out_sig_bt[c_arg+1] == T_VOID, "bad arg list"); 3113 if (src.first()->is_stack()) { 3114 // Stack to stack/reg is simple 3115 long_move(masm, src, dst); 3116 } else { 3117 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2; 3118 3119 // Destination could be an odd reg on 32bit in which case 3120 // we can't load direct to the destination. 3121 3122 if (!d->is_even() && wordSize == 4) { 3123 d = L2; 3124 } 3125 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; 3126 if (Assembler::is_simm13(off)) { 3127 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), 3128 SP, off); 3129 __ ld_long(SP, off, d); 3130 } else { 3131 if (conversion_off == noreg) { 3132 __ set(off, L6); 3133 conversion_off = L6; 3134 } 3135 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), 3136 SP, conversion_off); 3137 __ ld_long(SP, conversion_off, d); 3138 } 3139 if (d == L2) { 3140 long_move(masm, reg64_to_VMRegPair(L2), dst); 3141 } 3142 } 3143 break; 3144 3145 case T_LONG : 3146 // 32bit can't do a split move of something like g1 -> O0, O1 3147 // so use a memory temp 3148 if (src.is_single_phys_reg() && wordSize == 4) { 3149 Register tmp = L2; 3150 if (dst.first()->is_reg() && 3151 (wordSize == 8 || dst.first()->as_Register()->is_even())) { 3152 tmp = dst.first()->as_Register(); 3153 } 3154 3155 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size; 3156 if (Assembler::is_simm13(off)) { 3157 __ stx(src.first()->as_Register(), SP, off); 3158 __ ld_long(SP, off, tmp); 3159 } else { 3160 if (conversion_off == noreg) { 3161 __ set(off, L6); 3162 conversion_off = L6; 3163 } 3164 __ stx(src.first()->as_Register(), SP, conversion_off); 3165 __ ld_long(SP, conversion_off, tmp); 3166 } 3167 3168 if (tmp == L2) { 3169 long_move(masm, reg64_to_VMRegPair(L2), dst); 3170 } 3171 } else { 3172 long_move(masm, src, dst); 3173 } 3174 break; 3175 3176 case T_ADDRESS: assert(false, "found T_ADDRESS in java args"); 3177 3178 default: 3179 move32_64(masm, src, dst); 3180 } 3181 } 3182 3183 3184 // If we have any strings we must store any register based arg to the stack 3185 // This includes any still live xmm registers too. 3186 3187 if (total_strings > 0 ) { 3188 3189 // protect all the arg registers 3190 __ save_frame(0); 3191 __ mov(G2_thread, L7_thread_cache); 3192 const Register L2_string_off = L2; 3193 3194 // Get first string offset 3195 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off); 3196 3197 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) { 3198 if (out_sig_bt[c_arg] == T_ADDRESS) { 3199 3200 VMRegPair dst = out_regs[c_arg]; 3201 const Register d = dst.first()->is_reg() ? 3202 dst.first()->as_Register()->after_save() : noreg; 3203 3204 // It's a string the oop and it was already copied to the out arg 3205 // position 3206 if (d != noreg) { 3207 __ mov(d, O0); 3208 } else { 3209 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), 3210 "must be"); 3211 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0); 3212 } 3213 Label skip; 3214 3215 __ br_null(O0, false, Assembler::pn, skip); 3216 __ delayed()->add(FP, L2_string_off, O1); 3217 3218 if (d != noreg) { 3219 __ mov(O1, d); 3220 } else { 3221 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS), 3222 "must be"); 3223 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS); 3224 } 3225 3226 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf), 3227 relocInfo::runtime_call_type); 3228 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off); 3229 3230 __ bind(skip); 3231 3232 } 3233 3234 } 3235 __ mov(L7_thread_cache, G2_thread); 3236 __ restore(); 3237 3238 } 3239 3240 3241 // Ok now we are done. Need to place the nop that dtrace wants in order to 3242 // patch in the trap 3243 3244 int patch_offset = ((intptr_t)__ pc()) - start; 3245 3246 __ nop(); 3247 3248 3249 // Return 3250 3251 __ ret(); 3252 __ delayed()->restore(); 3253 3254 __ flush(); 3255 3256 nmethod *nm = nmethod::new_dtrace_nmethod( 3257 method, masm->code(), vep_offset, patch_offset, frame_complete, 3258 stack_slots / VMRegImpl::slots_per_word); 3259 return nm; 3260 3261 } 3262 3263 #endif // HAVE_DTRACE_H 3264 3265 // this function returns the adjust size (in number of words) to a c2i adapter 3266 // activation for use during deoptimization 3267 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) { 3268 assert(callee_locals >= callee_parameters, 3269 "test and remove; got more parms than locals"); 3270 if (callee_locals < callee_parameters) 3271 return 0; // No adjustment for negative locals 3272 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords; 3273 return round_to(diff, WordsPerLong); 3274 } 3275 3276 // "Top of Stack" slots that may be unused by the calling convention but must 3277 // otherwise be preserved. 3278 // On Intel these are not necessary and the value can be zero. 3279 // On Sparc this describes the words reserved for storing a register window 3280 // when an interrupt occurs. 3281 uint SharedRuntime::out_preserve_stack_slots() { 3282 return frame::register_save_words * VMRegImpl::slots_per_word; 3283 } 3284 3285 static void gen_new_frame(MacroAssembler* masm, bool deopt) { 3286 // 3287 // Common out the new frame generation for deopt and uncommon trap 3288 // 3289 Register G3pcs = G3_scratch; // Array of new pcs (input) 3290 Register Oreturn0 = O0; 3291 Register Oreturn1 = O1; 3292 Register O2UnrollBlock = O2; 3293 Register O3array = O3; // Array of frame sizes (input) 3294 Register O4array_size = O4; // number of frames (input) 3295 Register O7frame_size = O7; // number of frames (input) 3296 3297 __ ld_ptr(O3array, 0, O7frame_size); 3298 __ sub(G0, O7frame_size, O7frame_size); 3299 __ save(SP, O7frame_size, SP); 3300 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc 3301 3302 #ifdef ASSERT 3303 // make sure that the frames are aligned properly 3304 #ifndef _LP64 3305 __ btst(wordSize*2-1, SP); 3306 __ breakpoint_trap(Assembler::notZero, Assembler::ptr_cc); 3307 #endif 3308 #endif 3309 3310 // Deopt needs to pass some extra live values from frame to frame 3311 3312 if (deopt) { 3313 __ mov(Oreturn0->after_save(), Oreturn0); 3314 __ mov(Oreturn1->after_save(), Oreturn1); 3315 } 3316 3317 __ mov(O4array_size->after_save(), O4array_size); 3318 __ sub(O4array_size, 1, O4array_size); 3319 __ mov(O3array->after_save(), O3array); 3320 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock); 3321 __ add(G3pcs, wordSize, G3pcs); // point to next pc value 3322 3323 #ifdef ASSERT 3324 // trash registers to show a clear pattern in backtraces 3325 __ set(0xDEAD0000, I0); 3326 __ add(I0, 2, I1); 3327 __ add(I0, 4, I2); 3328 __ add(I0, 6, I3); 3329 __ add(I0, 8, I4); 3330 // Don't touch I5 could have valuable savedSP 3331 __ set(0xDEADBEEF, L0); 3332 __ mov(L0, L1); 3333 __ mov(L0, L2); 3334 __ mov(L0, L3); 3335 __ mov(L0, L4); 3336 __ mov(L0, L5); 3337 3338 // trash the return value as there is nothing to return yet 3339 __ set(0xDEAD0001, O7); 3340 #endif 3341 3342 __ mov(SP, O5_savedSP); 3343 } 3344 3345 3346 static void make_new_frames(MacroAssembler* masm, bool deopt) { 3347 // 3348 // loop through the UnrollBlock info and create new frames 3349 // 3350 Register G3pcs = G3_scratch; 3351 Register Oreturn0 = O0; 3352 Register Oreturn1 = O1; 3353 Register O2UnrollBlock = O2; 3354 Register O3array = O3; 3355 Register O4array_size = O4; 3356 Label loop; 3357 3358 #ifdef ASSERT 3359 // Compilers generate code that bang the stack by as much as the 3360 // interpreter would need. So this stack banging should never 3361 // trigger a fault. Verify that it does not on non product builds. 3362 if (UseStackBanging) { 3363 // Get total frame size for interpreted frames 3364 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4); 3365 __ bang_stack_size(O4, O3, G3_scratch); 3366 } 3367 #endif 3368 3369 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size); 3370 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs); 3371 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array); 3372 3373 // Adjust old interpreter frame to make space for new frame's extra java locals 3374 // 3375 // We capture the original sp for the transition frame only because it is needed in 3376 // order to properly calculate interpreter_sp_adjustment. Even though in real life 3377 // every interpreter frame captures a savedSP it is only needed at the transition 3378 // (fortunately). If we had to have it correct everywhere then we would need to 3379 // be told the sp_adjustment for each frame we create. If the frame size array 3380 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size] 3381 // for each frame we create and keep up the illusion every where. 3382 // 3383 3384 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7); 3385 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment 3386 __ sub(SP, O7, SP); 3387 3388 #ifdef ASSERT 3389 // make sure that there is at least one entry in the array 3390 __ tst(O4array_size); 3391 __ breakpoint_trap(Assembler::zero, Assembler::icc); 3392 #endif 3393 3394 // Now push the new interpreter frames 3395 __ bind(loop); 3396 3397 // allocate a new frame, filling the registers 3398 3399 gen_new_frame(masm, deopt); // allocate an interpreter frame 3400 3401 __ cmp_zero_and_br(Assembler::notZero, O4array_size, loop); 3402 __ delayed()->add(O3array, wordSize, O3array); 3403 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc 3404 3405 } 3406 3407 //------------------------------generate_deopt_blob---------------------------- 3408 // Ought to generate an ideal graph & compile, but here's some SPARC ASM 3409 // instead. 3410 void SharedRuntime::generate_deopt_blob() { 3411 // allocate space for the code 3412 ResourceMark rm; 3413 // setup code generation tools 3414 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code 3415 #ifdef ASSERT 3416 if (UseStackBanging) { 3417 pad += StackShadowPages*16 + 32; 3418 } 3419 #endif 3420 #ifdef _LP64 3421 CodeBuffer buffer("deopt_blob", 2100+pad, 512); 3422 #else 3423 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread) 3424 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread) 3425 CodeBuffer buffer("deopt_blob", 1600+pad, 512); 3426 #endif /* _LP64 */ 3427 MacroAssembler* masm = new MacroAssembler(&buffer); 3428 FloatRegister Freturn0 = F0; 3429 Register Greturn1 = G1; 3430 Register Oreturn0 = O0; 3431 Register Oreturn1 = O1; 3432 Register O2UnrollBlock = O2; 3433 Register L0deopt_mode = L0; 3434 Register G4deopt_mode = G4_scratch; 3435 int frame_size_words; 3436 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS); 3437 #if !defined(_LP64) && defined(COMPILER2) 3438 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS); 3439 #endif 3440 Label cont; 3441 3442 OopMapSet *oop_maps = new OopMapSet(); 3443 3444 // 3445 // This is the entry point for code which is returning to a de-optimized 3446 // frame. 3447 // The steps taken by this frame are as follows: 3448 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1) 3449 // and all potentially live registers (at a pollpoint many registers can be live). 3450 // 3451 // - call the C routine: Deoptimization::fetch_unroll_info (this function 3452 // returns information about the number and size of interpreter frames 3453 // which are equivalent to the frame which is being deoptimized) 3454 // - deallocate the unpack frame, restoring only results values. Other 3455 // volatile registers will now be captured in the vframeArray as needed. 3456 // - deallocate the deoptimization frame 3457 // - in a loop using the information returned in the previous step 3458 // push new interpreter frames (take care to propagate the return 3459 // values through each new frame pushed) 3460 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0) 3461 // - call the C routine: Deoptimization::unpack_frames (this function 3462 // lays out values on the interpreter frame which was just created) 3463 // - deallocate the dummy unpack_frame 3464 // - ensure that all the return values are correctly set and then do 3465 // a return to the interpreter entry point 3466 // 3467 // Refer to the following methods for more information: 3468 // - Deoptimization::fetch_unroll_info 3469 // - Deoptimization::unpack_frames 3470 3471 OopMap* map = NULL; 3472 3473 int start = __ offset(); 3474 3475 // restore G2, the trampoline destroyed it 3476 __ get_thread(); 3477 3478 // On entry we have been called by the deoptimized nmethod with a call that 3479 // replaced the original call (or safepoint polling location) so the deoptimizing 3480 // pc is now in O7. Return values are still in the expected places 3481 3482 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); 3483 __ ba(cont); 3484 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode); 3485 3486 int exception_offset = __ offset() - start; 3487 3488 // restore G2, the trampoline destroyed it 3489 __ get_thread(); 3490 3491 // On entry we have been jumped to by the exception handler (or exception_blob 3492 // for server). O0 contains the exception oop and O7 contains the original 3493 // exception pc. So if we push a frame here it will look to the 3494 // stack walking code (fetch_unroll_info) just like a normal call so 3495 // state will be extracted normally. 3496 3497 // save exception oop in JavaThread and fall through into the 3498 // exception_in_tls case since they are handled in same way except 3499 // for where the pending exception is kept. 3500 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset()); 3501 3502 // 3503 // Vanilla deoptimization with an exception pending in exception_oop 3504 // 3505 int exception_in_tls_offset = __ offset() - start; 3506 3507 // No need to update oop_map as each call to save_live_registers will produce identical oopmap 3508 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); 3509 3510 // Restore G2_thread 3511 __ get_thread(); 3512 3513 #ifdef ASSERT 3514 { 3515 // verify that there is really an exception oop in exception_oop 3516 Label has_exception; 3517 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception); 3518 __ br_notnull_short(Oexception, Assembler::pt, has_exception); 3519 __ stop("no exception in thread"); 3520 __ bind(has_exception); 3521 3522 // verify that there is no pending exception 3523 Label no_pending_exception; 3524 Address exception_addr(G2_thread, Thread::pending_exception_offset()); 3525 __ ld_ptr(exception_addr, Oexception); 3526 __ br_null_short(Oexception, Assembler::pt, no_pending_exception); 3527 __ stop("must not have pending exception here"); 3528 __ bind(no_pending_exception); 3529 } 3530 #endif 3531 3532 __ ba(cont); 3533 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);; 3534 3535 // 3536 // Reexecute entry, similar to c2 uncommon trap 3537 // 3538 int reexecute_offset = __ offset() - start; 3539 3540 // No need to update oop_map as each call to save_live_registers will produce identical oopmap 3541 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words); 3542 3543 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode); 3544 3545 __ bind(cont); 3546 3547 __ set_last_Java_frame(SP, noreg); 3548 3549 // do the call by hand so we can get the oopmap 3550 3551 __ mov(G2_thread, L7_thread_cache); 3552 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type); 3553 __ delayed()->mov(G2_thread, O0); 3554 3555 // Set an oopmap for the call site this describes all our saved volatile registers 3556 3557 oop_maps->add_gc_map( __ offset()-start, map); 3558 3559 __ mov(L7_thread_cache, G2_thread); 3560 3561 __ reset_last_Java_frame(); 3562 3563 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers 3564 // so this move will survive 3565 3566 __ mov(L0deopt_mode, G4deopt_mode); 3567 3568 __ mov(O0, O2UnrollBlock->after_save()); 3569 3570 RegisterSaver::restore_result_registers(masm); 3571 3572 Label noException; 3573 __ cmp_and_br_short(G4deopt_mode, Deoptimization::Unpack_exception, Assembler::notEqual, Assembler::pt, noException); 3574 3575 // Move the pending exception from exception_oop to Oexception so 3576 // the pending exception will be picked up the interpreter. 3577 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception); 3578 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); 3579 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); 3580 __ bind(noException); 3581 3582 // deallocate the deoptimization frame taking care to preserve the return values 3583 __ mov(Oreturn0, Oreturn0->after_save()); 3584 __ mov(Oreturn1, Oreturn1->after_save()); 3585 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); 3586 __ restore(); 3587 3588 // Allocate new interpreter frame(s) and possible c2i adapter frame 3589 3590 make_new_frames(masm, true); 3591 3592 // push a dummy "unpack_frame" taking care of float return values and 3593 // call Deoptimization::unpack_frames to have the unpacker layout 3594 // information in the interpreter frames just created and then return 3595 // to the interpreter entry point 3596 __ save(SP, -frame_size_words*wordSize, SP); 3597 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr); 3598 #if !defined(_LP64) 3599 #if defined(COMPILER2) 3600 // 32-bit 1-register longs return longs in G1 3601 __ stx(Greturn1, saved_Greturn1_addr); 3602 #endif 3603 __ set_last_Java_frame(SP, noreg); 3604 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode); 3605 #else 3606 // LP64 uses g4 in set_last_Java_frame 3607 __ mov(G4deopt_mode, O1); 3608 __ set_last_Java_frame(SP, G0); 3609 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1); 3610 #endif 3611 __ reset_last_Java_frame(); 3612 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0); 3613 3614 #if !defined(_LP64) && defined(COMPILER2) 3615 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into 3616 // I0/I1 if the return value is long. 3617 Label not_long; 3618 __ cmp_and_br_short(O0,T_LONG, Assembler::notEqual, Assembler::pt, not_long); 3619 __ ldd(saved_Greturn1_addr,I0); 3620 __ bind(not_long); 3621 #endif 3622 __ ret(); 3623 __ delayed()->restore(); 3624 3625 masm->flush(); 3626 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words); 3627 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset); 3628 } 3629 3630 #ifdef COMPILER2 3631 3632 //------------------------------generate_uncommon_trap_blob-------------------- 3633 // Ought to generate an ideal graph & compile, but here's some SPARC ASM 3634 // instead. 3635 void SharedRuntime::generate_uncommon_trap_blob() { 3636 // allocate space for the code 3637 ResourceMark rm; 3638 // setup code generation tools 3639 int pad = VerifyThread ? 512 : 0; 3640 #ifdef ASSERT 3641 if (UseStackBanging) { 3642 pad += StackShadowPages*16 + 32; 3643 } 3644 #endif 3645 #ifdef _LP64 3646 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512); 3647 #else 3648 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread) 3649 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread) 3650 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512); 3651 #endif 3652 MacroAssembler* masm = new MacroAssembler(&buffer); 3653 Register O2UnrollBlock = O2; 3654 Register O2klass_index = O2; 3655 3656 // 3657 // This is the entry point for all traps the compiler takes when it thinks 3658 // it cannot handle further execution of compilation code. The frame is 3659 // deoptimized in these cases and converted into interpreter frames for 3660 // execution 3661 // The steps taken by this frame are as follows: 3662 // - push a fake "unpack_frame" 3663 // - call the C routine Deoptimization::uncommon_trap (this function 3664 // packs the current compiled frame into vframe arrays and returns 3665 // information about the number and size of interpreter frames which 3666 // are equivalent to the frame which is being deoptimized) 3667 // - deallocate the "unpack_frame" 3668 // - deallocate the deoptimization frame 3669 // - in a loop using the information returned in the previous step 3670 // push interpreter frames; 3671 // - create a dummy "unpack_frame" 3672 // - call the C routine: Deoptimization::unpack_frames (this function 3673 // lays out values on the interpreter frame which was just created) 3674 // - deallocate the dummy unpack_frame 3675 // - return to the interpreter entry point 3676 // 3677 // Refer to the following methods for more information: 3678 // - Deoptimization::uncommon_trap 3679 // - Deoptimization::unpack_frame 3680 3681 // the unloaded class index is in O0 (first parameter to this blob) 3682 3683 // push a dummy "unpack_frame" 3684 // and call Deoptimization::uncommon_trap to pack the compiled frame into 3685 // vframe array and return the UnrollBlock information 3686 __ save_frame(0); 3687 __ set_last_Java_frame(SP, noreg); 3688 __ mov(I0, O2klass_index); 3689 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index); 3690 __ reset_last_Java_frame(); 3691 __ mov(O0, O2UnrollBlock->after_save()); 3692 __ restore(); 3693 3694 // deallocate the deoptimized frame taking care to preserve the return values 3695 __ mov(O2UnrollBlock, O2UnrollBlock->after_save()); 3696 __ restore(); 3697 3698 // Allocate new interpreter frame(s) and possible c2i adapter frame 3699 3700 make_new_frames(masm, false); 3701 3702 // push a dummy "unpack_frame" taking care of float return values and 3703 // call Deoptimization::unpack_frames to have the unpacker layout 3704 // information in the interpreter frames just created and then return 3705 // to the interpreter entry point 3706 __ save_frame(0); 3707 __ set_last_Java_frame(SP, noreg); 3708 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case 3709 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3); 3710 __ reset_last_Java_frame(); 3711 __ ret(); 3712 __ delayed()->restore(); 3713 3714 masm->flush(); 3715 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize); 3716 } 3717 3718 #endif // COMPILER2 3719 3720 //------------------------------generate_handler_blob------------------- 3721 // 3722 // Generate a special Compile2Runtime blob that saves all registers, and sets 3723 // up an OopMap. 3724 // 3725 // This blob is jumped to (via a breakpoint and the signal handler) from a 3726 // safepoint in compiled code. On entry to this blob, O7 contains the 3727 // address in the original nmethod at which we should resume normal execution. 3728 // Thus, this blob looks like a subroutine which must preserve lots of 3729 // registers and return normally. Note that O7 is never register-allocated, 3730 // so it is guaranteed to be free here. 3731 // 3732 3733 // The hardest part of what this blob must do is to save the 64-bit %o 3734 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and 3735 // an interrupt will chop off their heads. Making space in the caller's frame 3736 // first will let us save the 64-bit %o's before save'ing, but we cannot hand 3737 // the adjusted FP off to the GC stack-crawler: this will modify the caller's 3738 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save 3739 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP). 3740 // Tricky, tricky, tricky... 3741 3742 SafepointBlob* SharedRuntime::generate_handler_blob(address call_ptr, int poll_type) { 3743 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); 3744 3745 // allocate space for the code 3746 ResourceMark rm; 3747 // setup code generation tools 3748 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) 3749 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) 3750 // even larger with TraceJumps 3751 int pad = TraceJumps ? 512 : 0; 3752 CodeBuffer buffer("handler_blob", 1600 + pad, 512); 3753 MacroAssembler* masm = new MacroAssembler(&buffer); 3754 int frame_size_words; 3755 OopMapSet *oop_maps = new OopMapSet(); 3756 OopMap* map = NULL; 3757 3758 int start = __ offset(); 3759 3760 bool cause_return = (poll_type == POLL_AT_RETURN); 3761 // If this causes a return before the processing, then do a "restore" 3762 if (cause_return) { 3763 __ restore(); 3764 } else { 3765 // Make it look like we were called via the poll 3766 // so that frame constructor always sees a valid return address 3767 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7); 3768 __ sub(O7, frame::pc_return_offset, O7); 3769 } 3770 3771 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); 3772 3773 // setup last_Java_sp (blows G4) 3774 __ set_last_Java_frame(SP, noreg); 3775 3776 // call into the runtime to handle illegal instructions exception 3777 // Do not use call_VM_leaf, because we need to make a GC map at this call site. 3778 __ mov(G2_thread, O0); 3779 __ save_thread(L7_thread_cache); 3780 __ call(call_ptr); 3781 __ delayed()->nop(); 3782 3783 // Set an oopmap for the call site. 3784 // We need this not only for callee-saved registers, but also for volatile 3785 // registers that the compiler might be keeping live across a safepoint. 3786 3787 oop_maps->add_gc_map( __ offset() - start, map); 3788 3789 __ restore_thread(L7_thread_cache); 3790 // clear last_Java_sp 3791 __ reset_last_Java_frame(); 3792 3793 // Check for exceptions 3794 Label pending; 3795 3796 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); 3797 __ br_notnull_short(O1, Assembler::pn, pending); 3798 3799 RegisterSaver::restore_live_registers(masm); 3800 3801 // We are back the the original state on entry and ready to go. 3802 3803 __ retl(); 3804 __ delayed()->nop(); 3805 3806 // Pending exception after the safepoint 3807 3808 __ bind(pending); 3809 3810 RegisterSaver::restore_live_registers(masm); 3811 3812 // We are back the the original state on entry. 3813 3814 // Tail-call forward_exception_entry, with the issuing PC in O7, 3815 // so it looks like the original nmethod called forward_exception_entry. 3816 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); 3817 __ JMP(O0, 0); 3818 __ delayed()->nop(); 3819 3820 // ------------- 3821 // make sure all code is generated 3822 masm->flush(); 3823 3824 // return exception blob 3825 return SafepointBlob::create(&buffer, oop_maps, frame_size_words); 3826 } 3827 3828 // 3829 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss 3830 // 3831 // Generate a stub that calls into vm to find out the proper destination 3832 // of a java call. All the argument registers are live at this point 3833 // but since this is generic code we don't know what they are and the caller 3834 // must do any gc of the args. 3835 // 3836 RuntimeStub* SharedRuntime::generate_resolve_blob(address destination, const char* name) { 3837 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before"); 3838 3839 // allocate space for the code 3840 ResourceMark rm; 3841 // setup code generation tools 3842 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread) 3843 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread) 3844 // even larger with TraceJumps 3845 int pad = TraceJumps ? 512 : 0; 3846 CodeBuffer buffer(name, 1600 + pad, 512); 3847 MacroAssembler* masm = new MacroAssembler(&buffer); 3848 int frame_size_words; 3849 OopMapSet *oop_maps = new OopMapSet(); 3850 OopMap* map = NULL; 3851 3852 int start = __ offset(); 3853 3854 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words); 3855 3856 int frame_complete = __ offset(); 3857 3858 // setup last_Java_sp (blows G4) 3859 __ set_last_Java_frame(SP, noreg); 3860 3861 // call into the runtime to handle illegal instructions exception 3862 // Do not use call_VM_leaf, because we need to make a GC map at this call site. 3863 __ mov(G2_thread, O0); 3864 __ save_thread(L7_thread_cache); 3865 __ call(destination, relocInfo::runtime_call_type); 3866 __ delayed()->nop(); 3867 3868 // O0 contains the address we are going to jump to assuming no exception got installed 3869 3870 // Set an oopmap for the call site. 3871 // We need this not only for callee-saved registers, but also for volatile 3872 // registers that the compiler might be keeping live across a safepoint. 3873 3874 oop_maps->add_gc_map( __ offset() - start, map); 3875 3876 __ restore_thread(L7_thread_cache); 3877 // clear last_Java_sp 3878 __ reset_last_Java_frame(); 3879 3880 // Check for exceptions 3881 Label pending; 3882 3883 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1); 3884 __ br_notnull_short(O1, Assembler::pn, pending); 3885 3886 // get the returned Method* 3887 3888 __ get_vm_result_2(G5_method); 3889 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS); 3890 3891 // O0 is where we want to jump, overwrite G3 which is saved and scratch 3892 3893 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS); 3894 3895 RegisterSaver::restore_live_registers(masm); 3896 3897 // We are back the the original state on entry and ready to go. 3898 3899 __ JMP(G3, 0); 3900 __ delayed()->nop(); 3901 3902 // Pending exception after the safepoint 3903 3904 __ bind(pending); 3905 3906 RegisterSaver::restore_live_registers(masm); 3907 3908 // We are back the the original state on entry. 3909 3910 // Tail-call forward_exception_entry, with the issuing PC in O7, 3911 // so it looks like the original nmethod called forward_exception_entry. 3912 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0); 3913 __ JMP(O0, 0); 3914 __ delayed()->nop(); 3915 3916 // ------------- 3917 // make sure all code is generated 3918 masm->flush(); 3919 3920 // return the blob 3921 // frame_size_words or bytes?? 3922 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true); 3923 }