1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.hpp"
  30 
  31 // MacroAssembler extends Assembler by frequently used macros.
  32 //
  33 // Instructions for which a 'better' code sequence exists depending
  34 // on arguments should also go in here.
  35 
  36 class MacroAssembler: public Assembler {
  37   friend class LIR_Assembler;
  38 
  39  public:
  40   using Assembler::mov;
  41   using Assembler::movi;
  42 
  43  protected:
  44 
  45   // Support for VM calls
  46   //
  47   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  48   // may customize this version by overriding it for its purposes (e.g., to save/restore
  49   // additional registers when doing a VM call).
  50   virtual void call_VM_leaf_base(
  51     address entry_point,               // the entry point
  52     int     number_of_arguments,        // the number of arguments to pop after the call
  53     Label *retaddr = NULL
  54   );
  55 
  56   virtual void call_VM_leaf_base(
  57     address entry_point,               // the entry point
  58     int     number_of_arguments,        // the number of arguments to pop after the call
  59     Label &retaddr) {
  60     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  61   }
  62 
  63   // This is the base routine called by the different versions of call_VM. The interpreter
  64   // may customize this version by overriding it for its purposes (e.g., to save/restore
  65   // additional registers when doing a VM call).
  66   //
  67   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  68   // returns the register which contains the thread upon return. If a thread register has been
  69   // specified, the return value will correspond to that register. If no last_java_sp is specified
  70   // (noreg) than rsp will be used instead.
  71   virtual void call_VM_base(           // returns the register containing the thread upon return
  72     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  73     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  74     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  75     address  entry_point,              // the entry point
  76     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  77     bool     check_exceptions          // whether to check for pending exceptions after return
  78   );
  79 
  80   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  81 
  82   // Maximum size of class area in Metaspace when compressed
  83   uint64_t use_XOR_for_compressed_class_base;
  84 
  85  public:
  86   MacroAssembler(CodeBuffer* code) : Assembler(code) {
  87     /* SRDM This is not friendly */
  88     const uint64_t UnscaledClassSpaceMax = (uint64_t(max_juint) + 1);
  89 
  90     use_XOR_for_compressed_class_base
  91       = (operand_valid_for_logical_immediate(false /*is32*/,
  92                                              (uint64_t)Universe::narrow_klass_base())
  93          && ((uint64_t)Universe::narrow_klass_base()
  94              > (1ul << log2_intptr(UnscaledClassSpaceMax))));
  95   }
  96 
  97  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  98  // The implementation is only non-empty for the InterpreterMacroAssembler,
  99  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
 100  virtual void check_and_handle_popframe(Register java_thread);
 101  virtual void check_and_handle_earlyret(Register java_thread);
 102 
 103   void safepoint_poll(Label& slow_path);
 104   void safepoint_poll_acquire(Label& slow_path);
 105 
 106   // Biased locking support
 107   // lock_reg and obj_reg must be loaded up with the appropriate values.
 108   // swap_reg is killed.
 109   // tmp_reg must be supplied and must not be rscratch1 or rscratch2
 110   // Optional slow case is for implementations (interpreter and C1) which branch to
 111   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 112   // Returns offset of first potentially-faulting instruction for null
 113   // check info (currently consumed only by C1). If
 114   // swap_reg_contains_mark is true then returns -1 as it is assumed
 115   // the calling code has already passed any potential faults.
 116   int biased_locking_enter(Register lock_reg, Register obj_reg,
 117                            Register swap_reg, Register tmp_reg,
 118                            bool swap_reg_contains_mark,
 119                            Label& done, Label* slow_case = NULL,
 120                            BiasedLockingCounters* counters = NULL);
 121   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 122 
 123 
 124   // Helper functions for statistics gathering.
 125   // Unconditional atomic increment.
 126   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 127   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 128     lea(tmp1, counter_addr);
 129     atomic_incw(tmp1, tmp2, tmp3);
 130   }
 131   // Load Effective Address
 132   void lea(Register r, const Address &a) {
 133     InstructionMark im(this);
 134     code_section()->relocate(inst_mark(), a.rspec());
 135     a.lea(this, r);
 136   }
 137 
 138   void addmw(Address a, Register incr, Register scratch) {
 139     ldrw(scratch, a);
 140     addw(scratch, scratch, incr);
 141     strw(scratch, a);
 142   }
 143 
 144   // Add constant to memory word
 145   void addmw(Address a, int imm, Register scratch) {
 146     ldrw(scratch, a);
 147     if (imm > 0)
 148       addw(scratch, scratch, (unsigned)imm);
 149     else
 150       subw(scratch, scratch, (unsigned)-imm);
 151     strw(scratch, a);
 152   }
 153 
 154   void bind(Label& L) {
 155     Assembler::bind(L);
 156     code()->clear_last_membar();
 157   }
 158 
 159   void membar(Membar_mask_bits order_constraint);
 160 
 161   // Frame creation and destruction shared between JITs.
 162   void build_frame(int framesize);
 163   void remove_frame(int framesize);
 164 
 165   virtual void _call_Unimplemented(address call_site) {
 166     mov(rscratch2, call_site);
 167     haltsim();
 168   }
 169 
 170 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 171 
 172   virtual void notify(int type);
 173 
 174   // aliases defined in AARCH64 spec
 175 
 176   template<class T>
 177   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 178   // imm is limited to 12 bits.
 179   inline void cmp(Register Rd, unsigned imm)  { subs(zr, Rd, imm); }
 180 
 181   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 182   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 183 
 184   void cset(Register Rd, Assembler::Condition cond) {
 185     csinc(Rd, zr, zr, ~cond);
 186   }
 187   void csetw(Register Rd, Assembler::Condition cond) {
 188     csincw(Rd, zr, zr, ~cond);
 189   }
 190 
 191   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 192     csneg(Rd, Rn, Rn, ~cond);
 193   }
 194   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 195     csnegw(Rd, Rn, Rn, ~cond);
 196   }
 197 
 198   inline void movw(Register Rd, Register Rn) {
 199     if (Rd == sp || Rn == sp) {
 200       addw(Rd, Rn, 0U);
 201     } else {
 202       orrw(Rd, zr, Rn);
 203     }
 204   }
 205   inline void mov(Register Rd, Register Rn) {
 206     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 207     if (Rd == Rn) {
 208     } else if (Rd == sp || Rn == sp) {
 209       add(Rd, Rn, 0U);
 210     } else {
 211       orr(Rd, zr, Rn);
 212     }
 213   }
 214 
 215   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 216   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 217 
 218   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 219   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 220 
 221   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 222   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 223 
 224   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 225     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 226   }
 227   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 228     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 229   }
 230 
 231   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 232     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 233   }
 234   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 235     bfm(Rd, Rn, lsb , (lsb + width - 1));
 236   }
 237 
 238   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 239     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 240   }
 241   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 242     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 243   }
 244 
 245   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 246     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 247   }
 248   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 249     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 250   }
 251 
 252   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 253     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 254   }
 255   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 256     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 257   }
 258 
 259   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 260     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 261   }
 262   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 263     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 264   }
 265 
 266   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 267     sbfmw(Rd, Rn, imm, 31);
 268   }
 269 
 270   inline void asr(Register Rd, Register Rn, unsigned imm) {
 271     sbfm(Rd, Rn, imm, 63);
 272   }
 273 
 274   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 275     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 276   }
 277 
 278   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 279     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 280   }
 281 
 282   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 283     ubfmw(Rd, Rn, imm, 31);
 284   }
 285 
 286   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 287     ubfm(Rd, Rn, imm, 63);
 288   }
 289 
 290   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 291     extrw(Rd, Rn, Rn, imm);
 292   }
 293 
 294   inline void ror(Register Rd, Register Rn, unsigned imm) {
 295     extr(Rd, Rn, Rn, imm);
 296   }
 297 
 298   inline void sxtbw(Register Rd, Register Rn) {
 299     sbfmw(Rd, Rn, 0, 7);
 300   }
 301   inline void sxthw(Register Rd, Register Rn) {
 302     sbfmw(Rd, Rn, 0, 15);
 303   }
 304   inline void sxtb(Register Rd, Register Rn) {
 305     sbfm(Rd, Rn, 0, 7);
 306   }
 307   inline void sxth(Register Rd, Register Rn) {
 308     sbfm(Rd, Rn, 0, 15);
 309   }
 310   inline void sxtw(Register Rd, Register Rn) {
 311     sbfm(Rd, Rn, 0, 31);
 312   }
 313 
 314   inline void uxtbw(Register Rd, Register Rn) {
 315     ubfmw(Rd, Rn, 0, 7);
 316   }
 317   inline void uxthw(Register Rd, Register Rn) {
 318     ubfmw(Rd, Rn, 0, 15);
 319   }
 320   inline void uxtb(Register Rd, Register Rn) {
 321     ubfm(Rd, Rn, 0, 7);
 322   }
 323   inline void uxth(Register Rd, Register Rn) {
 324     ubfm(Rd, Rn, 0, 15);
 325   }
 326   inline void uxtw(Register Rd, Register Rn) {
 327     ubfm(Rd, Rn, 0, 31);
 328   }
 329 
 330   inline void cmnw(Register Rn, Register Rm) {
 331     addsw(zr, Rn, Rm);
 332   }
 333   inline void cmn(Register Rn, Register Rm) {
 334     adds(zr, Rn, Rm);
 335   }
 336 
 337   inline void cmpw(Register Rn, Register Rm) {
 338     subsw(zr, Rn, Rm);
 339   }
 340   inline void cmp(Register Rn, Register Rm) {
 341     subs(zr, Rn, Rm);
 342   }
 343 
 344   inline void negw(Register Rd, Register Rn) {
 345     subw(Rd, zr, Rn);
 346   }
 347 
 348   inline void neg(Register Rd, Register Rn) {
 349     sub(Rd, zr, Rn);
 350   }
 351 
 352   inline void negsw(Register Rd, Register Rn) {
 353     subsw(Rd, zr, Rn);
 354   }
 355 
 356   inline void negs(Register Rd, Register Rn) {
 357     subs(Rd, zr, Rn);
 358   }
 359 
 360   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 361     addsw(zr, Rn, Rm, kind, shift);
 362   }
 363   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 364     adds(zr, Rn, Rm, kind, shift);
 365   }
 366 
 367   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 368     subsw(zr, Rn, Rm, kind, shift);
 369   }
 370   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 371     subs(zr, Rn, Rm, kind, shift);
 372   }
 373 
 374   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 375     subw(Rd, zr, Rn, kind, shift);
 376   }
 377 
 378   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 379     sub(Rd, zr, Rn, kind, shift);
 380   }
 381 
 382   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 383     subsw(Rd, zr, Rn, kind, shift);
 384   }
 385 
 386   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 387     subs(Rd, zr, Rn, kind, shift);
 388   }
 389 
 390   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 391     msubw(Rd, Rn, Rm, zr);
 392   }
 393   inline void mneg(Register Rd, Register Rn, Register Rm) {
 394     msub(Rd, Rn, Rm, zr);
 395   }
 396 
 397   inline void mulw(Register Rd, Register Rn, Register Rm) {
 398     maddw(Rd, Rn, Rm, zr);
 399   }
 400   inline void mul(Register Rd, Register Rn, Register Rm) {
 401     madd(Rd, Rn, Rm, zr);
 402   }
 403 
 404   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 405     smsubl(Rd, Rn, Rm, zr);
 406   }
 407   inline void smull(Register Rd, Register Rn, Register Rm) {
 408     smaddl(Rd, Rn, Rm, zr);
 409   }
 410 
 411   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 412     umsubl(Rd, Rn, Rm, zr);
 413   }
 414   inline void umull(Register Rd, Register Rn, Register Rm) {
 415     umaddl(Rd, Rn, Rm, zr);
 416   }
 417 
 418 #define WRAP(INSN)                                                            \
 419   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 420     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 421       nop();                                                                  \
 422     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 423   }
 424 
 425   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 426   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 427 #undef WRAP
 428 
 429 
 430   // macro assembly operations needed for aarch64
 431 
 432   // first two private routines for loading 32 bit or 64 bit constants
 433 private:
 434 
 435   void mov_immediate64(Register dst, u_int64_t imm64);
 436   void mov_immediate32(Register dst, u_int32_t imm32);
 437 
 438   int push(unsigned int bitset, Register stack);
 439   int pop(unsigned int bitset, Register stack);
 440 
 441   void mov(Register dst, Address a);
 442 
 443 public:
 444   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 445   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 446 
 447   // Push and pop everything that might be clobbered by a native
 448   // runtime call except rscratch1 and rscratch2.  (They are always
 449   // scratch, so we don't have to protect them.)  Only save the lower
 450   // 64 bits of each vector register.
 451   void push_call_clobbered_registers();
 452   void pop_call_clobbered_registers();
 453 
 454   // now mov instructions for loading absolute addresses and 32 or
 455   // 64 bit integers
 456 
 457   inline void mov(Register dst, address addr)
 458   {
 459     mov_immediate64(dst, (u_int64_t)addr);
 460   }
 461 
 462   inline void mov(Register dst, u_int64_t imm64)
 463   {
 464     mov_immediate64(dst, imm64);
 465   }
 466 
 467   inline void movw(Register dst, u_int32_t imm32)
 468   {
 469     mov_immediate32(dst, imm32);
 470   }
 471 
 472   inline void mov(Register dst, long l)
 473   {
 474     mov(dst, (u_int64_t)l);
 475   }
 476 
 477   inline void mov(Register dst, int i)
 478   {
 479     mov(dst, (long)i);
 480   }
 481 
 482   void mov(Register dst, RegisterOrConstant src) {
 483     if (src.is_register())
 484       mov(dst, src.as_register());
 485     else
 486       mov(dst, src.as_constant());
 487   }
 488 
 489   void movptr(Register r, uintptr_t imm64);
 490 
 491   void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
 492 
 493   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 494     orr(Vd, T, Vn, Vn);
 495   }
 496 
 497 public:
 498 
 499   // Generalized Test Bit And Branch, including a "far" variety which
 500   // spans more than 32KiB.
 501   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
 502     assert(cond == EQ || cond == NE, "must be");
 503 
 504     if (far)
 505       cond = ~cond;
 506 
 507     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 508     if (cond == Assembler::EQ)
 509       branch = &Assembler::tbz;
 510     else
 511       branch = &Assembler::tbnz;
 512 
 513     if (far) {
 514       Label L;
 515       (this->*branch)(Rt, bitpos, L);
 516       b(dest);
 517       bind(L);
 518     } else {
 519       (this->*branch)(Rt, bitpos, dest);
 520     }
 521   }
 522 
 523   // macro instructions for accessing and updating floating point
 524   // status register
 525   //
 526   // FPSR : op1 == 011
 527   //        CRn == 0100
 528   //        CRm == 0100
 529   //        op2 == 001
 530 
 531   inline void get_fpsr(Register reg)
 532   {
 533     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 534   }
 535 
 536   inline void set_fpsr(Register reg)
 537   {
 538     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 539   }
 540 
 541   inline void clear_fpsr()
 542   {
 543     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 544   }
 545 
 546   // DCZID_EL0: op1 == 011
 547   //            CRn == 0000
 548   //            CRm == 0000
 549   //            op2 == 111
 550   inline void get_dczid_el0(Register reg)
 551   {
 552     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 553   }
 554 
 555   // CTR_EL0:   op1 == 011
 556   //            CRn == 0000
 557   //            CRm == 0000
 558   //            op2 == 001
 559   inline void get_ctr_el0(Register reg)
 560   {
 561     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 562   }
 563 
 564   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 565   int corrected_idivl(Register result, Register ra, Register rb,
 566                       bool want_remainder, Register tmp = rscratch1);
 567   int corrected_idivq(Register result, Register ra, Register rb,
 568                       bool want_remainder, Register tmp = rscratch1);
 569 
 570   // Support for NULL-checks
 571   //
 572   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 573   // If the accessed location is M[reg + offset] and the offset is known, provide the
 574   // offset. No explicit code generation is needed if the offset is within a certain
 575   // range (0 <= offset <= page_size).
 576 
 577   virtual void null_check(Register reg, int offset = -1);
 578   static bool needs_explicit_null_check(intptr_t offset);
 579 
 580   static address target_addr_for_insn(address insn_addr, unsigned insn);
 581   static address target_addr_for_insn(address insn_addr) {
 582     unsigned insn = *(unsigned*)insn_addr;
 583     return target_addr_for_insn(insn_addr, insn);
 584   }
 585 
 586   // Required platform-specific helpers for Label::patch_instructions.
 587   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 588   static int pd_patch_instruction_size(address branch, address target);
 589   static void pd_patch_instruction(address branch, address target) {
 590     pd_patch_instruction_size(branch, target);
 591   }
 592   static address pd_call_destination(address branch) {
 593     return target_addr_for_insn(branch);
 594   }
 595 #ifndef PRODUCT
 596   static void pd_print_patched_instruction(address branch);
 597 #endif
 598 
 599   static int patch_oop(address insn_addr, address o);
 600   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 601 
 602   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 603 
 604   // The following 4 methods return the offset of the appropriate move instruction
 605 
 606   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 607   int load_unsigned_byte(Register dst, Address src);
 608   int load_unsigned_short(Register dst, Address src);
 609 
 610   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 611   int load_signed_byte(Register dst, Address src);
 612   int load_signed_short(Register dst, Address src);
 613 
 614   int load_signed_byte32(Register dst, Address src);
 615   int load_signed_short32(Register dst, Address src);
 616 
 617   // Support for sign-extension (hi:lo = extend_sign(lo))
 618   void extend_sign(Register hi, Register lo);
 619 
 620   // Load and store values by size and signed-ness
 621   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 622   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 623 
 624   // Support for inc/dec with optimal instruction selection depending on value
 625 
 626   // x86_64 aliases an unqualified register/address increment and
 627   // decrement to call incrementq and decrementq but also supports
 628   // explicitly sized calls to incrementq/decrementq or
 629   // incrementl/decrementl
 630 
 631   // for aarch64 the proper convention would be to use
 632   // increment/decrement for 64 bit operatons and
 633   // incrementw/decrementw for 32 bit operations. so when porting
 634   // x86_64 code we can leave calls to increment/decrement as is,
 635   // replace incrementq/decrementq with increment/decrement and
 636   // replace incrementl/decrementl with incrementw/decrementw.
 637 
 638   // n.b. increment/decrement calls with an Address destination will
 639   // need to use a scratch register to load the value to be
 640   // incremented. increment/decrement calls which add or subtract a
 641   // constant value greater than 2^12 will need to use a 2nd scratch
 642   // register to hold the constant. so, a register increment/decrement
 643   // may trash rscratch2 and an address increment/decrement trash
 644   // rscratch and rscratch2
 645 
 646   void decrementw(Address dst, int value = 1);
 647   void decrementw(Register reg, int value = 1);
 648 
 649   void decrement(Register reg, int value = 1);
 650   void decrement(Address dst, int value = 1);
 651 
 652   void incrementw(Address dst, int value = 1);
 653   void incrementw(Register reg, int value = 1);
 654 
 655   void increment(Register reg, int value = 1);
 656   void increment(Address dst, int value = 1);
 657 
 658 
 659   // Alignment
 660   void align(int modulus);
 661 
 662   // Stack frame creation/removal
 663   void enter()
 664   {
 665     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 666     mov(rfp, sp);
 667   }
 668   void leave()
 669   {
 670     mov(sp, rfp);
 671     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 672   }
 673 
 674   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 675   // The pointer will be loaded into the thread register.
 676   void get_thread(Register thread);
 677 
 678 
 679   // Support for VM calls
 680   //
 681   // It is imperative that all calls into the VM are handled via the call_VM macros.
 682   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 683   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 684 
 685 
 686   void call_VM(Register oop_result,
 687                address entry_point,
 688                bool check_exceptions = true);
 689   void call_VM(Register oop_result,
 690                address entry_point,
 691                Register arg_1,
 692                bool check_exceptions = true);
 693   void call_VM(Register oop_result,
 694                address entry_point,
 695                Register arg_1, Register arg_2,
 696                bool check_exceptions = true);
 697   void call_VM(Register oop_result,
 698                address entry_point,
 699                Register arg_1, Register arg_2, Register arg_3,
 700                bool check_exceptions = true);
 701 
 702   // Overloadings with last_Java_sp
 703   void call_VM(Register oop_result,
 704                Register last_java_sp,
 705                address entry_point,
 706                int number_of_arguments = 0,
 707                bool check_exceptions = true);
 708   void call_VM(Register oop_result,
 709                Register last_java_sp,
 710                address entry_point,
 711                Register arg_1, bool
 712                check_exceptions = true);
 713   void call_VM(Register oop_result,
 714                Register last_java_sp,
 715                address entry_point,
 716                Register arg_1, Register arg_2,
 717                bool check_exceptions = true);
 718   void call_VM(Register oop_result,
 719                Register last_java_sp,
 720                address entry_point,
 721                Register arg_1, Register arg_2, Register arg_3,
 722                bool check_exceptions = true);
 723 
 724   void get_vm_result  (Register oop_result, Register thread);
 725   void get_vm_result_2(Register metadata_result, Register thread);
 726 
 727   // These always tightly bind to MacroAssembler::call_VM_base
 728   // bypassing the virtual implementation
 729   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 730   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 731   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 732   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 733   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 734 
 735   void call_VM_leaf(address entry_point,
 736                     int number_of_arguments = 0);
 737   void call_VM_leaf(address entry_point,
 738                     Register arg_1);
 739   void call_VM_leaf(address entry_point,
 740                     Register arg_1, Register arg_2);
 741   void call_VM_leaf(address entry_point,
 742                     Register arg_1, Register arg_2, Register arg_3);
 743 
 744   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 745   // bypassing the virtual implementation
 746   void super_call_VM_leaf(address entry_point);
 747   void super_call_VM_leaf(address entry_point, Register arg_1);
 748   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 749   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 750   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 751 
 752   // last Java Frame (fills frame anchor)
 753   void set_last_Java_frame(Register last_java_sp,
 754                            Register last_java_fp,
 755                            address last_java_pc,
 756                            Register scratch);
 757 
 758   void set_last_Java_frame(Register last_java_sp,
 759                            Register last_java_fp,
 760                            Label &last_java_pc,
 761                            Register scratch);
 762 
 763   void set_last_Java_frame(Register last_java_sp,
 764                            Register last_java_fp,
 765                            Register last_java_pc,
 766                            Register scratch);
 767 
 768   void reset_last_Java_frame(Register thread);
 769 
 770   // thread in the default location (rthread)
 771   void reset_last_Java_frame(bool clear_fp);
 772 
 773   // Stores
 774   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 775   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 776 
 777 #if INCLUDE_ALL_GCS
 778 
 779   void g1_write_barrier_pre(Register obj,
 780                             Register pre_val,
 781                             Register thread,
 782                             Register tmp,
 783                             bool tosca_live,
 784                             bool expand_call);
 785 
 786   void g1_write_barrier_post(Register store_addr,
 787                              Register new_val,
 788                              Register thread,
 789                              Register tmp,
 790                              Register tmp2);
 791 
 792 #endif // INCLUDE_ALL_GCS
 793 
 794   // oop manipulations
 795   void load_klass(Register dst, Register src);
 796   void store_klass(Register dst, Register src);
 797   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 798 
 799   void resolve_oop_handle(Register result);
 800   void load_mirror(Register dst, Register method);
 801 
 802   void load_heap_oop(Register dst, Address src);
 803 
 804   void load_heap_oop_not_null(Register dst, Address src);
 805   void store_heap_oop(Address dst, Register src);
 806 
 807   // currently unimplemented
 808   // Used for storing NULL. All other oop constants should be
 809   // stored using routines that take a jobject.
 810   void store_heap_oop_null(Address dst);
 811 
 812   void load_prototype_header(Register dst, Register src);
 813 
 814   void store_klass_gap(Register dst, Register src);
 815 
 816   // This dummy is to prevent a call to store_heap_oop from
 817   // converting a zero (like NULL) into a Register by giving
 818   // the compiler two choices it can't resolve
 819 
 820   void store_heap_oop(Address dst, void* dummy);
 821 
 822   void encode_heap_oop(Register d, Register s);
 823   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 824   void decode_heap_oop(Register d, Register s);
 825   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 826   void encode_heap_oop_not_null(Register r);
 827   void decode_heap_oop_not_null(Register r);
 828   void encode_heap_oop_not_null(Register dst, Register src);
 829   void decode_heap_oop_not_null(Register dst, Register src);
 830 
 831   void set_narrow_oop(Register dst, jobject obj);
 832 
 833   void encode_klass_not_null(Register r);
 834   void decode_klass_not_null(Register r);
 835   void encode_klass_not_null(Register dst, Register src);
 836   void decode_klass_not_null(Register dst, Register src);
 837 
 838   void set_narrow_klass(Register dst, Klass* k);
 839 
 840   // if heap base register is used - reinit it with the correct value
 841   void reinit_heapbase();
 842 
 843   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 844 
 845   void push_CPU_state(bool save_vectors = false);
 846   void pop_CPU_state(bool restore_vectors = false) ;
 847 
 848   // Round up to a power of two
 849   void round_to(Register reg, int modulus);
 850 
 851   // allocation
 852   void eden_allocate(
 853     Register obj,                      // result: pointer to object after successful allocation
 854     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 855     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 856     Register t1,                       // temp register
 857     Label&   slow_case                 // continuation point if fast allocation fails
 858   );
 859   void tlab_allocate(
 860     Register obj,                      // result: pointer to object after successful allocation
 861     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 862     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 863     Register t1,                       // temp register
 864     Register t2,                       // temp register
 865     Label&   slow_case                 // continuation point if fast allocation fails
 866   );
 867   Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
 868   void zero_memory(Register addr, Register len, Register t1);
 869   void verify_tlab();
 870 
 871   void incr_allocated_bytes(Register thread,
 872                             Register var_size_in_bytes, int con_size_in_bytes,
 873                             Register t1 = noreg);
 874 
 875   // interface method calling
 876   void lookup_interface_method(Register recv_klass,
 877                                Register intf_klass,
 878                                RegisterOrConstant itable_index,
 879                                Register method_result,
 880                                Register scan_temp,
 881                                Label& no_such_interface);
 882 
 883   // virtual method calling
 884   // n.b. x86 allows RegisterOrConstant for vtable_index
 885   void lookup_virtual_method(Register recv_klass,
 886                              RegisterOrConstant vtable_index,
 887                              Register method_result);
 888 
 889   // Test sub_klass against super_klass, with fast and slow paths.
 890 
 891   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 892   // One of the three labels can be NULL, meaning take the fall-through.
 893   // If super_check_offset is -1, the value is loaded up from super_klass.
 894   // No registers are killed, except temp_reg.
 895   void check_klass_subtype_fast_path(Register sub_klass,
 896                                      Register super_klass,
 897                                      Register temp_reg,
 898                                      Label* L_success,
 899                                      Label* L_failure,
 900                                      Label* L_slow_path,
 901                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 902 
 903   // The rest of the type check; must be wired to a corresponding fast path.
 904   // It does not repeat the fast path logic, so don't use it standalone.
 905   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 906   // Updates the sub's secondary super cache as necessary.
 907   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 908   void check_klass_subtype_slow_path(Register sub_klass,
 909                                      Register super_klass,
 910                                      Register temp_reg,
 911                                      Register temp2_reg,
 912                                      Label* L_success,
 913                                      Label* L_failure,
 914                                      bool set_cond_codes = false);
 915 
 916   // Simplified, combined version, good for typical uses.
 917   // Falls through on failure.
 918   void check_klass_subtype(Register sub_klass,
 919                            Register super_klass,
 920                            Register temp_reg,
 921                            Label& L_success);
 922 
 923   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 924 
 925 
 926   // Debugging
 927 
 928   // only if +VerifyOops
 929   void verify_oop(Register reg, const char* s = "broken oop");
 930   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 931 
 932 // TODO: verify method and klass metadata (compare against vptr?)
 933   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 934   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 935 
 936 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 937 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 938 
 939   // only if +VerifyFPU
 940   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 941 
 942   // prints msg, dumps registers and stops execution
 943   void stop(const char* msg);
 944 
 945   // prints msg and continues
 946   void warn(const char* msg);
 947 
 948   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 949 
 950   void untested()                                { stop("untested"); }
 951 
 952   void unimplemented(const char* what = "");
 953 
 954   void should_not_reach_here()                   { stop("should not reach here"); }
 955 
 956   // Stack overflow checking
 957   void bang_stack_with_offset(int offset) {
 958     // stack grows down, caller passes positive offset
 959     assert(offset > 0, "must bang with negative offset");
 960     sub(rscratch2, sp, offset);
 961     str(zr, Address(rscratch2));
 962   }
 963 
 964   // Writes to stack successive pages until offset reached to check for
 965   // stack overflow + shadow pages.  Also, clobbers tmp
 966   void bang_stack_size(Register size, Register tmp);
 967 
 968   // Check for reserved stack access in method being exited (for JIT)
 969   void reserved_stack_check();
 970 
 971   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 972                                                 Register tmp,
 973                                                 int offset);
 974 
 975   // Support for serializing memory accesses between threads
 976   void serialize_memory(Register thread, Register tmp);
 977 
 978   // Arithmetics
 979 
 980   void addptr(const Address &dst, int32_t src);
 981   void cmpptr(Register src1, Address src2);
 982 
 983   // Various forms of CAS
 984 
 985   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
 986                           Label &suceed, Label *fail);
 987   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
 988                   Label &suceed, Label *fail);
 989 
 990   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
 991                   Label &suceed, Label *fail);
 992 
 993   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
 994   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
 995   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
 996   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
 997 
 998   void atomic_xchg(Register prev, Register newv, Register addr);
 999   void atomic_xchgw(Register prev, Register newv, Register addr);
1000   void atomic_xchgal(Register prev, Register newv, Register addr);
1001   void atomic_xchgalw(Register prev, Register newv, Register addr);
1002 
1003   void orptr(Address adr, RegisterOrConstant src) {
1004     ldr(rscratch1, adr);
1005     if (src.is_register())
1006       orr(rscratch1, rscratch1, src.as_register());
1007     else
1008       orr(rscratch1, rscratch1, src.as_constant());
1009     str(rscratch1, adr);
1010   }
1011 
1012   // A generic CAS; success or failure is in the EQ flag.
1013   // Clobbers rscratch1
1014   void cmpxchg(Register addr, Register expected, Register new_val,
1015                enum operand_size size,
1016                bool acquire, bool release, bool weak,
1017                Register result);
1018 
1019   // Calls
1020 
1021   address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1022 
1023   static bool far_branches() {
1024     return ReservedCodeCacheSize > branch_range;
1025   }
1026 
1027   // Jumps that can reach anywhere in the code cache.
1028   // Trashes tmp.
1029   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1030   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1031 
1032   static int far_branch_size() {
1033     if (far_branches()) {
1034       return 3 * 4;  // adrp, add, br
1035     } else {
1036       return 4;
1037     }
1038   }
1039 
1040   // Emit the CompiledIC call idiom
1041   address ic_call(address entry, jint method_index = 0);
1042 
1043 public:
1044 
1045   // Data
1046 
1047   void mov_metadata(Register dst, Metadata* obj);
1048   Address allocate_metadata_address(Metadata* obj);
1049   Address constant_oop_address(jobject obj);
1050 
1051   void movoop(Register dst, jobject obj, bool immediate = false);
1052 
1053   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1054   void kernel_crc32(Register crc, Register buf, Register len,
1055         Register table0, Register table1, Register table2, Register table3,
1056         Register tmp, Register tmp2, Register tmp3);
1057   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1058   void kernel_crc32c(Register crc, Register buf, Register len,
1059         Register table0, Register table1, Register table2, Register table3,
1060         Register tmp, Register tmp2, Register tmp3);
1061 
1062   // Stack push and pop individual 64 bit registers
1063   void push(Register src);
1064   void pop(Register dst);
1065 
1066   // push all registers onto the stack
1067   void pusha();
1068   void popa();
1069 
1070   void repne_scan(Register addr, Register value, Register count,
1071                   Register scratch);
1072   void repne_scanw(Register addr, Register value, Register count,
1073                    Register scratch);
1074 
1075   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1076   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1077 
1078   // If a constant does not fit in an immediate field, generate some
1079   // number of MOV instructions and then perform the operation
1080   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1081                              add_sub_imm_insn insn1,
1082                              add_sub_reg_insn insn2);
1083   // Seperate vsn which sets the flags
1084   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1085                              add_sub_imm_insn insn1,
1086                              add_sub_reg_insn insn2);
1087 
1088 #define WRAP(INSN)                                                      \
1089   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1090     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1091   }                                                                     \
1092                                                                         \
1093   void INSN(Register Rd, Register Rn, Register Rm,                      \
1094              enum shift_kind kind, unsigned shift = 0) {                \
1095     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1096   }                                                                     \
1097                                                                         \
1098   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1099     Assembler::INSN(Rd, Rn, Rm);                                        \
1100   }                                                                     \
1101                                                                         \
1102   void INSN(Register Rd, Register Rn, Register Rm,                      \
1103            ext::operation option, int amount = 0) {                     \
1104     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1105   }
1106 
1107   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1108 
1109 #undef WRAP
1110 #define WRAP(INSN)                                                      \
1111   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1112     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1113   }                                                                     \
1114                                                                         \
1115   void INSN(Register Rd, Register Rn, Register Rm,                      \
1116              enum shift_kind kind, unsigned shift = 0) {                \
1117     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1118   }                                                                     \
1119                                                                         \
1120   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1121     Assembler::INSN(Rd, Rn, Rm);                                        \
1122   }                                                                     \
1123                                                                         \
1124   void INSN(Register Rd, Register Rn, Register Rm,                      \
1125            ext::operation option, int amount = 0) {                     \
1126     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1127   }
1128 
1129   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1130 
1131   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1132   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1133   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1134   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1135 
1136   void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1137 
1138   void tableswitch(Register index, jint lowbound, jint highbound,
1139                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1140     adr(rscratch1, jumptable);
1141     subsw(rscratch2, index, lowbound);
1142     subsw(zr, rscratch2, highbound - lowbound);
1143     br(Assembler::HS, jumptable_end);
1144     add(rscratch1, rscratch1, rscratch2,
1145         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1146     br(rscratch1);
1147   }
1148 
1149   // Form an address from base + offset in Rd.  Rd may or may not
1150   // actually be used: you must use the Address that is returned.  It
1151   // is up to you to ensure that the shift provided matches the size
1152   // of your data.
1153   Address form_address(Register Rd, Register base, long byte_offset, int shift);
1154 
1155   // Return true iff an address is within the 48-bit AArch64 address
1156   // space.
1157   bool is_valid_AArch64_address(address a) {
1158     return ((uint64_t)a >> 48) == 0;
1159   }
1160 
1161   // Load the base of the cardtable byte map into reg.
1162   void load_byte_map_base(Register reg);
1163 
1164   // Prolog generator routines to support switch between x86 code and
1165   // generated ARM code
1166 
1167   // routine to generate an x86 prolog for a stub function which
1168   // bootstraps into the generated ARM code which directly follows the
1169   // stub
1170   //
1171 
1172   public:
1173   // enum used for aarch64--x86 linkage to define return type of x86 function
1174   enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1175 
1176 #ifdef BUILTIN_SIM
1177   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1178 #else
1179   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1180 #endif
1181 
1182   // special version of call_VM_leaf_base needed for aarch64 simulator
1183   // where we need to specify both the gp and fp arg counts and the
1184   // return type so that the linkage routine from aarch64 to x86 and
1185   // back knows which aarch64 registers to copy to x86 registers and
1186   // which x86 result register to copy back to an aarch64 register
1187 
1188   void call_VM_leaf_base1(
1189     address  entry_point,             // the entry point
1190     int      number_of_gp_arguments,  // the number of gp reg arguments to pass
1191     int      number_of_fp_arguments,  // the number of fp reg arguments to pass
1192     ret_type type,                    // the return type for the call
1193     Label*   retaddr = NULL
1194   );
1195 
1196   void ldr_constant(Register dest, const Address &const_addr) {
1197     if (NearCpool) {
1198       ldr(dest, const_addr);
1199     } else {
1200       unsigned long offset;
1201       adrp(dest, InternalAddress(const_addr.target()), offset);
1202       ldr(dest, Address(dest, offset));
1203     }
1204   }
1205 
1206   address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1207   address read_polling_page(Register r, relocInfo::relocType rtype);
1208   void get_polling_page(Register dest, address page, relocInfo::relocType rtype);
1209 
1210   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1211   void update_byte_crc32(Register crc, Register val, Register table);
1212   void update_word_crc32(Register crc, Register v, Register tmp,
1213         Register table0, Register table1, Register table2, Register table3,
1214         bool upper = false);
1215 
1216   void string_compare(Register str1, Register str2,
1217                       Register cnt1, Register cnt2, Register result,
1218                       Register tmp1,
1219                       FloatRegister vtmp, FloatRegister vtmpZ, int ae);
1220 
1221   void has_negatives(Register ary1, Register len, Register result);
1222 
1223   void arrays_equals(Register a1, Register a2,
1224                      Register result, Register cnt1,
1225                      int elem_size, bool is_string);
1226 
1227   void fill_words(Register base, Register cnt, Register value);
1228   void zero_words(Register base, u_int64_t cnt);
1229   void zero_words(Register ptr, Register cnt);
1230   void zero_dcache_blocks(Register base, Register cnt);
1231 
1232   static const int zero_words_block_size;
1233 
1234   void byte_array_inflate(Register src, Register dst, Register len,
1235                           FloatRegister vtmp1, FloatRegister vtmp2,
1236                           FloatRegister vtmp3, Register tmp4);
1237 
1238   void char_array_compress(Register src, Register dst, Register len,
1239                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1240                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1241                            Register result);
1242 
1243   void encode_iso_array(Register src, Register dst,
1244                         Register len, Register result,
1245                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1246                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1247   void string_indexof(Register str1, Register str2,
1248                       Register cnt1, Register cnt2,
1249                       Register tmp1, Register tmp2,
1250                       Register tmp3, Register tmp4,
1251                       int int_cnt1, Register result, int ae);
1252   void string_indexof_char(Register str1, Register cnt1,
1253                            Register ch, Register result,
1254                            Register tmp1, Register tmp2, Register tmp3);
1255 private:
1256   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1257                        Register src1, Register src2);
1258   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1259     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1260   }
1261   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1262                              Register y, Register y_idx, Register z,
1263                              Register carry, Register product,
1264                              Register idx, Register kdx);
1265   void multiply_128_x_128_loop(Register y, Register z,
1266                                Register carry, Register carry2,
1267                                Register idx, Register jdx,
1268                                Register yz_idx1, Register yz_idx2,
1269                                Register tmp, Register tmp3, Register tmp4,
1270                                Register tmp7, Register product_hi);
1271   void kernel_crc32_using_crc32(Register crc, Register buf,
1272         Register len, Register tmp0, Register tmp1, Register tmp2,
1273         Register tmp3);
1274   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1275         Register len, Register tmp0, Register tmp1, Register tmp2,
1276         Register tmp3);
1277 public:
1278   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1279                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1280                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1281   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1282   // ISB may be needed because of a safepoint
1283   void maybe_isb() { isb(); }
1284 
1285 private:
1286   // Return the effective address r + (r1 << ext) + offset.
1287   // Uses rscratch2.
1288   Address offsetted_address(Register r, Register r1, Address::extend ext,
1289                             int offset, int size);
1290 
1291 private:
1292   // Returns an address on the stack which is reachable with a ldr/str of size
1293   // Uses rscratch2 if the address is not directly reachable
1294   Address spill_address(int size, int offset, Register tmp=rscratch2);
1295 
1296 public:
1297   void spill(Register Rx, bool is64, int offset) {
1298     if (is64) {
1299       str(Rx, spill_address(8, offset));
1300     } else {
1301       strw(Rx, spill_address(4, offset));
1302     }
1303   }
1304   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1305     str(Vx, T, spill_address(1 << (int)T, offset));
1306   }
1307   void unspill(Register Rx, bool is64, int offset) {
1308     if (is64) {
1309       ldr(Rx, spill_address(8, offset));
1310     } else {
1311       ldrw(Rx, spill_address(4, offset));
1312     }
1313   }
1314   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1315     ldr(Vx, T, spill_address(1 << (int)T, offset));
1316   }
1317   void spill_copy128(int src_offset, int dst_offset,
1318                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1319     if (src_offset < 512 && (src_offset & 7) == 0 &&
1320         dst_offset < 512 && (dst_offset & 7) == 0) {
1321       ldp(tmp1, tmp2, Address(sp, src_offset));
1322       stp(tmp1, tmp2, Address(sp, dst_offset));
1323     } else {
1324       unspill(tmp1, true, src_offset);
1325       spill(tmp1, true, dst_offset);
1326       unspill(tmp1, true, src_offset+8);
1327       spill(tmp1, true, dst_offset+8);
1328     }
1329   }
1330 };
1331 
1332 #ifdef ASSERT
1333 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1334 #endif
1335 
1336 /**
1337  * class SkipIfEqual:
1338  *
1339  * Instantiating this class will result in assembly code being output that will
1340  * jump around any code emitted between the creation of the instance and it's
1341  * automatic destruction at the end of a scope block, depending on the value of
1342  * the flag passed to the constructor, which will be checked at run-time.
1343  */
1344 class SkipIfEqual {
1345  private:
1346   MacroAssembler* _masm;
1347   Label _label;
1348 
1349  public:
1350    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1351    ~SkipIfEqual();
1352 };
1353 
1354 struct tableswitch {
1355   Register _reg;
1356   int _insn_index; jint _first_key; jint _last_key;
1357   Label _after;
1358   Label _branches;
1359 };
1360 
1361 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP