rev 48167 : 8193266: AArch64: TestOptionsWithRanges.java SIGSEGV

   1 /*
   2  * Copyright (c) 1997, 2017, Oracle and/or its affiliates. All rights reserved.
   3  * Copyright (c) 2014, 2015, Red Hat Inc. All rights reserved.
   4  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   5  *
   6  * This code is free software; you can redistribute it and/or modify it
   7  * under the terms of the GNU General Public License version 2 only, as
   8  * published by the Free Software Foundation.
   9  *
  10  * This code is distributed in the hope that it will be useful, but WITHOUT
  11  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  12  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  13  * version 2 for more details (a copy is included in the LICENSE file that
  14  * accompanied this code).
  15  *
  16  * You should have received a copy of the GNU General Public License version
  17  * 2 along with this work; if not, write to the Free Software Foundation,
  18  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  19  *
  20  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  21  * or visit www.oracle.com if you need additional information or have any
  22  * questions.
  23  *
  24  */
  25 
  26 #ifndef CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  27 #define CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
  28 
  29 #include "asm/assembler.hpp"
  30 
  31 // MacroAssembler extends Assembler by frequently used macros.
  32 //
  33 // Instructions for which a 'better' code sequence exists depending
  34 // on arguments should also go in here.
  35 
  36 class MacroAssembler: public Assembler {
  37   friend class LIR_Assembler;
  38 
  39  public:
  40   using Assembler::mov;
  41   using Assembler::movi;
  42 
  43  protected:
  44 
  45   // Support for VM calls
  46   //
  47   // This is the base routine called by the different versions of call_VM_leaf. The interpreter
  48   // may customize this version by overriding it for its purposes (e.g., to save/restore
  49   // additional registers when doing a VM call).
  50   virtual void call_VM_leaf_base(
  51     address entry_point,               // the entry point
  52     int     number_of_arguments,        // the number of arguments to pop after the call
  53     Label *retaddr = NULL
  54   );
  55 
  56   virtual void call_VM_leaf_base(
  57     address entry_point,               // the entry point
  58     int     number_of_arguments,        // the number of arguments to pop after the call
  59     Label &retaddr) {
  60     call_VM_leaf_base(entry_point, number_of_arguments, &retaddr);
  61   }
  62 
  63   // This is the base routine called by the different versions of call_VM. The interpreter
  64   // may customize this version by overriding it for its purposes (e.g., to save/restore
  65   // additional registers when doing a VM call).
  66   //
  67   // If no java_thread register is specified (noreg) than rthread will be used instead. call_VM_base
  68   // returns the register which contains the thread upon return. If a thread register has been
  69   // specified, the return value will correspond to that register. If no last_java_sp is specified
  70   // (noreg) than rsp will be used instead.
  71   virtual void call_VM_base(           // returns the register containing the thread upon return
  72     Register oop_result,               // where an oop-result ends up if any; use noreg otherwise
  73     Register java_thread,              // the thread if computed before     ; use noreg otherwise
  74     Register last_java_sp,             // to set up last_Java_frame in stubs; use noreg otherwise
  75     address  entry_point,              // the entry point
  76     int      number_of_arguments,      // the number of arguments (w/o thread) to pop after the call
  77     bool     check_exceptions          // whether to check for pending exceptions after return
  78   );
  79 
  80   void call_VM_helper(Register oop_result, address entry_point, int number_of_arguments, bool check_exceptions = true);
  81 
  82   // Maximum size of class area in Metaspace when compressed
  83   uint64_t use_XOR_for_compressed_class_base;
  84 
  85  public:
  86   MacroAssembler(CodeBuffer* code) : Assembler(code) {



  87     use_XOR_for_compressed_class_base
  88       = (operand_valid_for_logical_immediate(false /*is32*/,
  89                                              (uint64_t)Universe::narrow_klass_base())
  90          && ((uint64_t)Universe::narrow_klass_base()
  91              > (1u << log2_intptr(CompressedClassSpaceSize))));
  92   }
  93 
  94  // These routines should emit JVMTI PopFrame and ForceEarlyReturn handling code.
  95  // The implementation is only non-empty for the InterpreterMacroAssembler,
  96  // as only the interpreter handles PopFrame and ForceEarlyReturn requests.
  97  virtual void check_and_handle_popframe(Register java_thread);
  98  virtual void check_and_handle_earlyret(Register java_thread);
  99 
 100   void safepoint_poll(Label& slow_path);
 101   void safepoint_poll_acquire(Label& slow_path);
 102 
 103   // Biased locking support
 104   // lock_reg and obj_reg must be loaded up with the appropriate values.
 105   // swap_reg is killed.
 106   // tmp_reg must be supplied and must not be rscratch1 or rscratch2
 107   // Optional slow case is for implementations (interpreter and C1) which branch to
 108   // slow case directly. Leaves condition codes set for C2's Fast_Lock node.
 109   // Returns offset of first potentially-faulting instruction for null
 110   // check info (currently consumed only by C1). If
 111   // swap_reg_contains_mark is true then returns -1 as it is assumed
 112   // the calling code has already passed any potential faults.
 113   int biased_locking_enter(Register lock_reg, Register obj_reg,
 114                            Register swap_reg, Register tmp_reg,
 115                            bool swap_reg_contains_mark,
 116                            Label& done, Label* slow_case = NULL,
 117                            BiasedLockingCounters* counters = NULL);
 118   void biased_locking_exit (Register obj_reg, Register temp_reg, Label& done);
 119 
 120 
 121   // Helper functions for statistics gathering.
 122   // Unconditional atomic increment.
 123   void atomic_incw(Register counter_addr, Register tmp, Register tmp2);
 124   void atomic_incw(Address counter_addr, Register tmp1, Register tmp2, Register tmp3) {
 125     lea(tmp1, counter_addr);
 126     atomic_incw(tmp1, tmp2, tmp3);
 127   }
 128   // Load Effective Address
 129   void lea(Register r, const Address &a) {
 130     InstructionMark im(this);
 131     code_section()->relocate(inst_mark(), a.rspec());
 132     a.lea(this, r);
 133   }
 134 
 135   void addmw(Address a, Register incr, Register scratch) {
 136     ldrw(scratch, a);
 137     addw(scratch, scratch, incr);
 138     strw(scratch, a);
 139   }
 140 
 141   // Add constant to memory word
 142   void addmw(Address a, int imm, Register scratch) {
 143     ldrw(scratch, a);
 144     if (imm > 0)
 145       addw(scratch, scratch, (unsigned)imm);
 146     else
 147       subw(scratch, scratch, (unsigned)-imm);
 148     strw(scratch, a);
 149   }
 150 
 151   void bind(Label& L) {
 152     Assembler::bind(L);
 153     code()->clear_last_membar();
 154   }
 155 
 156   void membar(Membar_mask_bits order_constraint);
 157 
 158   // Frame creation and destruction shared between JITs.
 159   void build_frame(int framesize);
 160   void remove_frame(int framesize);
 161 
 162   virtual void _call_Unimplemented(address call_site) {
 163     mov(rscratch2, call_site);
 164     haltsim();
 165   }
 166 
 167 #define call_Unimplemented() _call_Unimplemented((address)__PRETTY_FUNCTION__)
 168 
 169   virtual void notify(int type);
 170 
 171   // aliases defined in AARCH64 spec
 172 
 173   template<class T>
 174   inline void cmpw(Register Rd, T imm)  { subsw(zr, Rd, imm); }
 175   // imm is limited to 12 bits.
 176   inline void cmp(Register Rd, unsigned imm)  { subs(zr, Rd, imm); }
 177 
 178   inline void cmnw(Register Rd, unsigned imm) { addsw(zr, Rd, imm); }
 179   inline void cmn(Register Rd, unsigned imm) { adds(zr, Rd, imm); }
 180 
 181   void cset(Register Rd, Assembler::Condition cond) {
 182     csinc(Rd, zr, zr, ~cond);
 183   }
 184   void csetw(Register Rd, Assembler::Condition cond) {
 185     csincw(Rd, zr, zr, ~cond);
 186   }
 187 
 188   void cneg(Register Rd, Register Rn, Assembler::Condition cond) {
 189     csneg(Rd, Rn, Rn, ~cond);
 190   }
 191   void cnegw(Register Rd, Register Rn, Assembler::Condition cond) {
 192     csnegw(Rd, Rn, Rn, ~cond);
 193   }
 194 
 195   inline void movw(Register Rd, Register Rn) {
 196     if (Rd == sp || Rn == sp) {
 197       addw(Rd, Rn, 0U);
 198     } else {
 199       orrw(Rd, zr, Rn);
 200     }
 201   }
 202   inline void mov(Register Rd, Register Rn) {
 203     assert(Rd != r31_sp && Rn != r31_sp, "should be");
 204     if (Rd == Rn) {
 205     } else if (Rd == sp || Rn == sp) {
 206       add(Rd, Rn, 0U);
 207     } else {
 208       orr(Rd, zr, Rn);
 209     }
 210   }
 211 
 212   inline void moviw(Register Rd, unsigned imm) { orrw(Rd, zr, imm); }
 213   inline void movi(Register Rd, unsigned imm) { orr(Rd, zr, imm); }
 214 
 215   inline void tstw(Register Rd, Register Rn) { andsw(zr, Rd, Rn); }
 216   inline void tst(Register Rd, Register Rn) { ands(zr, Rd, Rn); }
 217 
 218   inline void tstw(Register Rd, uint64_t imm) { andsw(zr, Rd, imm); }
 219   inline void tst(Register Rd, uint64_t imm) { ands(zr, Rd, imm); }
 220 
 221   inline void bfiw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 222     bfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 223   }
 224   inline void bfi(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 225     bfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 226   }
 227 
 228   inline void bfxilw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 229     bfmw(Rd, Rn, lsb, (lsb + width - 1));
 230   }
 231   inline void bfxil(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 232     bfm(Rd, Rn, lsb , (lsb + width - 1));
 233   }
 234 
 235   inline void sbfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 236     sbfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 237   }
 238   inline void sbfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 239     sbfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 240   }
 241 
 242   inline void sbfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 243     sbfmw(Rd, Rn, lsb, (lsb + width - 1));
 244   }
 245   inline void sbfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 246     sbfm(Rd, Rn, lsb , (lsb + width - 1));
 247   }
 248 
 249   inline void ubfizw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 250     ubfmw(Rd, Rn, ((32 - lsb) & 31), (width - 1));
 251   }
 252   inline void ubfiz(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 253     ubfm(Rd, Rn, ((64 - lsb) & 63), (width - 1));
 254   }
 255 
 256   inline void ubfxw(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 257     ubfmw(Rd, Rn, lsb, (lsb + width - 1));
 258   }
 259   inline void ubfx(Register Rd, Register Rn, unsigned lsb, unsigned width) {
 260     ubfm(Rd, Rn, lsb , (lsb + width - 1));
 261   }
 262 
 263   inline void asrw(Register Rd, Register Rn, unsigned imm) {
 264     sbfmw(Rd, Rn, imm, 31);
 265   }
 266 
 267   inline void asr(Register Rd, Register Rn, unsigned imm) {
 268     sbfm(Rd, Rn, imm, 63);
 269   }
 270 
 271   inline void lslw(Register Rd, Register Rn, unsigned imm) {
 272     ubfmw(Rd, Rn, ((32 - imm) & 31), (31 - imm));
 273   }
 274 
 275   inline void lsl(Register Rd, Register Rn, unsigned imm) {
 276     ubfm(Rd, Rn, ((64 - imm) & 63), (63 - imm));
 277   }
 278 
 279   inline void lsrw(Register Rd, Register Rn, unsigned imm) {
 280     ubfmw(Rd, Rn, imm, 31);
 281   }
 282 
 283   inline void lsr(Register Rd, Register Rn, unsigned imm) {
 284     ubfm(Rd, Rn, imm, 63);
 285   }
 286 
 287   inline void rorw(Register Rd, Register Rn, unsigned imm) {
 288     extrw(Rd, Rn, Rn, imm);
 289   }
 290 
 291   inline void ror(Register Rd, Register Rn, unsigned imm) {
 292     extr(Rd, Rn, Rn, imm);
 293   }
 294 
 295   inline void sxtbw(Register Rd, Register Rn) {
 296     sbfmw(Rd, Rn, 0, 7);
 297   }
 298   inline void sxthw(Register Rd, Register Rn) {
 299     sbfmw(Rd, Rn, 0, 15);
 300   }
 301   inline void sxtb(Register Rd, Register Rn) {
 302     sbfm(Rd, Rn, 0, 7);
 303   }
 304   inline void sxth(Register Rd, Register Rn) {
 305     sbfm(Rd, Rn, 0, 15);
 306   }
 307   inline void sxtw(Register Rd, Register Rn) {
 308     sbfm(Rd, Rn, 0, 31);
 309   }
 310 
 311   inline void uxtbw(Register Rd, Register Rn) {
 312     ubfmw(Rd, Rn, 0, 7);
 313   }
 314   inline void uxthw(Register Rd, Register Rn) {
 315     ubfmw(Rd, Rn, 0, 15);
 316   }
 317   inline void uxtb(Register Rd, Register Rn) {
 318     ubfm(Rd, Rn, 0, 7);
 319   }
 320   inline void uxth(Register Rd, Register Rn) {
 321     ubfm(Rd, Rn, 0, 15);
 322   }
 323   inline void uxtw(Register Rd, Register Rn) {
 324     ubfm(Rd, Rn, 0, 31);
 325   }
 326 
 327   inline void cmnw(Register Rn, Register Rm) {
 328     addsw(zr, Rn, Rm);
 329   }
 330   inline void cmn(Register Rn, Register Rm) {
 331     adds(zr, Rn, Rm);
 332   }
 333 
 334   inline void cmpw(Register Rn, Register Rm) {
 335     subsw(zr, Rn, Rm);
 336   }
 337   inline void cmp(Register Rn, Register Rm) {
 338     subs(zr, Rn, Rm);
 339   }
 340 
 341   inline void negw(Register Rd, Register Rn) {
 342     subw(Rd, zr, Rn);
 343   }
 344 
 345   inline void neg(Register Rd, Register Rn) {
 346     sub(Rd, zr, Rn);
 347   }
 348 
 349   inline void negsw(Register Rd, Register Rn) {
 350     subsw(Rd, zr, Rn);
 351   }
 352 
 353   inline void negs(Register Rd, Register Rn) {
 354     subs(Rd, zr, Rn);
 355   }
 356 
 357   inline void cmnw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 358     addsw(zr, Rn, Rm, kind, shift);
 359   }
 360   inline void cmn(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 361     adds(zr, Rn, Rm, kind, shift);
 362   }
 363 
 364   inline void cmpw(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 365     subsw(zr, Rn, Rm, kind, shift);
 366   }
 367   inline void cmp(Register Rn, Register Rm, enum shift_kind kind, unsigned shift = 0) {
 368     subs(zr, Rn, Rm, kind, shift);
 369   }
 370 
 371   inline void negw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 372     subw(Rd, zr, Rn, kind, shift);
 373   }
 374 
 375   inline void neg(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 376     sub(Rd, zr, Rn, kind, shift);
 377   }
 378 
 379   inline void negsw(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 380     subsw(Rd, zr, Rn, kind, shift);
 381   }
 382 
 383   inline void negs(Register Rd, Register Rn, enum shift_kind kind, unsigned shift = 0) {
 384     subs(Rd, zr, Rn, kind, shift);
 385   }
 386 
 387   inline void mnegw(Register Rd, Register Rn, Register Rm) {
 388     msubw(Rd, Rn, Rm, zr);
 389   }
 390   inline void mneg(Register Rd, Register Rn, Register Rm) {
 391     msub(Rd, Rn, Rm, zr);
 392   }
 393 
 394   inline void mulw(Register Rd, Register Rn, Register Rm) {
 395     maddw(Rd, Rn, Rm, zr);
 396   }
 397   inline void mul(Register Rd, Register Rn, Register Rm) {
 398     madd(Rd, Rn, Rm, zr);
 399   }
 400 
 401   inline void smnegl(Register Rd, Register Rn, Register Rm) {
 402     smsubl(Rd, Rn, Rm, zr);
 403   }
 404   inline void smull(Register Rd, Register Rn, Register Rm) {
 405     smaddl(Rd, Rn, Rm, zr);
 406   }
 407 
 408   inline void umnegl(Register Rd, Register Rn, Register Rm) {
 409     umsubl(Rd, Rn, Rm, zr);
 410   }
 411   inline void umull(Register Rd, Register Rn, Register Rm) {
 412     umaddl(Rd, Rn, Rm, zr);
 413   }
 414 
 415 #define WRAP(INSN)                                                            \
 416   void INSN(Register Rd, Register Rn, Register Rm, Register Ra) {             \
 417     if ((VM_Version::features() & VM_Version::CPU_A53MAC) && Ra != zr)        \
 418       nop();                                                                  \
 419     Assembler::INSN(Rd, Rn, Rm, Ra);                                          \
 420   }
 421 
 422   WRAP(madd) WRAP(msub) WRAP(maddw) WRAP(msubw)
 423   WRAP(smaddl) WRAP(smsubl) WRAP(umaddl) WRAP(umsubl)
 424 #undef WRAP
 425 
 426 
 427   // macro assembly operations needed for aarch64
 428 
 429   // first two private routines for loading 32 bit or 64 bit constants
 430 private:
 431 
 432   void mov_immediate64(Register dst, u_int64_t imm64);
 433   void mov_immediate32(Register dst, u_int32_t imm32);
 434 
 435   int push(unsigned int bitset, Register stack);
 436   int pop(unsigned int bitset, Register stack);
 437 
 438   void mov(Register dst, Address a);
 439 
 440 public:
 441   void push(RegSet regs, Register stack) { if (regs.bits()) push(regs.bits(), stack); }
 442   void pop(RegSet regs, Register stack) { if (regs.bits()) pop(regs.bits(), stack); }
 443 
 444   // Push and pop everything that might be clobbered by a native
 445   // runtime call except rscratch1 and rscratch2.  (They are always
 446   // scratch, so we don't have to protect them.)  Only save the lower
 447   // 64 bits of each vector register.
 448   void push_call_clobbered_registers();
 449   void pop_call_clobbered_registers();
 450 
 451   // now mov instructions for loading absolute addresses and 32 or
 452   // 64 bit integers
 453 
 454   inline void mov(Register dst, address addr)
 455   {
 456     mov_immediate64(dst, (u_int64_t)addr);
 457   }
 458 
 459   inline void mov(Register dst, u_int64_t imm64)
 460   {
 461     mov_immediate64(dst, imm64);
 462   }
 463 
 464   inline void movw(Register dst, u_int32_t imm32)
 465   {
 466     mov_immediate32(dst, imm32);
 467   }
 468 
 469   inline void mov(Register dst, long l)
 470   {
 471     mov(dst, (u_int64_t)l);
 472   }
 473 
 474   inline void mov(Register dst, int i)
 475   {
 476     mov(dst, (long)i);
 477   }
 478 
 479   void mov(Register dst, RegisterOrConstant src) {
 480     if (src.is_register())
 481       mov(dst, src.as_register());
 482     else
 483       mov(dst, src.as_constant());
 484   }
 485 
 486   void movptr(Register r, uintptr_t imm64);
 487 
 488   void mov(FloatRegister Vd, SIMD_Arrangement T, u_int32_t imm32);
 489 
 490   void mov(FloatRegister Vd, SIMD_Arrangement T, FloatRegister Vn) {
 491     orr(Vd, T, Vn, Vn);
 492   }
 493 
 494 public:
 495 
 496   // Generalized Test Bit And Branch, including a "far" variety which
 497   // spans more than 32KiB.
 498   void tbr(Condition cond, Register Rt, int bitpos, Label &dest, bool far = false) {
 499     assert(cond == EQ || cond == NE, "must be");
 500 
 501     if (far)
 502       cond = ~cond;
 503 
 504     void (Assembler::* branch)(Register Rt, int bitpos, Label &L);
 505     if (cond == Assembler::EQ)
 506       branch = &Assembler::tbz;
 507     else
 508       branch = &Assembler::tbnz;
 509 
 510     if (far) {
 511       Label L;
 512       (this->*branch)(Rt, bitpos, L);
 513       b(dest);
 514       bind(L);
 515     } else {
 516       (this->*branch)(Rt, bitpos, dest);
 517     }
 518   }
 519 
 520   // macro instructions for accessing and updating floating point
 521   // status register
 522   //
 523   // FPSR : op1 == 011
 524   //        CRn == 0100
 525   //        CRm == 0100
 526   //        op2 == 001
 527 
 528   inline void get_fpsr(Register reg)
 529   {
 530     mrs(0b11, 0b0100, 0b0100, 0b001, reg);
 531   }
 532 
 533   inline void set_fpsr(Register reg)
 534   {
 535     msr(0b011, 0b0100, 0b0100, 0b001, reg);
 536   }
 537 
 538   inline void clear_fpsr()
 539   {
 540     msr(0b011, 0b0100, 0b0100, 0b001, zr);
 541   }
 542 
 543   // DCZID_EL0: op1 == 011
 544   //            CRn == 0000
 545   //            CRm == 0000
 546   //            op2 == 111
 547   inline void get_dczid_el0(Register reg)
 548   {
 549     mrs(0b011, 0b0000, 0b0000, 0b111, reg);
 550   }
 551 
 552   // CTR_EL0:   op1 == 011
 553   //            CRn == 0000
 554   //            CRm == 0000
 555   //            op2 == 001
 556   inline void get_ctr_el0(Register reg)
 557   {
 558     mrs(0b011, 0b0000, 0b0000, 0b001, reg);
 559   }
 560 
 561   // idiv variant which deals with MINLONG as dividend and -1 as divisor
 562   int corrected_idivl(Register result, Register ra, Register rb,
 563                       bool want_remainder, Register tmp = rscratch1);
 564   int corrected_idivq(Register result, Register ra, Register rb,
 565                       bool want_remainder, Register tmp = rscratch1);
 566 
 567   // Support for NULL-checks
 568   //
 569   // Generates code that causes a NULL OS exception if the content of reg is NULL.
 570   // If the accessed location is M[reg + offset] and the offset is known, provide the
 571   // offset. No explicit code generation is needed if the offset is within a certain
 572   // range (0 <= offset <= page_size).
 573 
 574   virtual void null_check(Register reg, int offset = -1);
 575   static bool needs_explicit_null_check(intptr_t offset);
 576 
 577   static address target_addr_for_insn(address insn_addr, unsigned insn);
 578   static address target_addr_for_insn(address insn_addr) {
 579     unsigned insn = *(unsigned*)insn_addr;
 580     return target_addr_for_insn(insn_addr, insn);
 581   }
 582 
 583   // Required platform-specific helpers for Label::patch_instructions.
 584   // They _shadow_ the declarations in AbstractAssembler, which are undefined.
 585   static int pd_patch_instruction_size(address branch, address target);
 586   static void pd_patch_instruction(address branch, address target) {
 587     pd_patch_instruction_size(branch, target);
 588   }
 589   static address pd_call_destination(address branch) {
 590     return target_addr_for_insn(branch);
 591   }
 592 #ifndef PRODUCT
 593   static void pd_print_patched_instruction(address branch);
 594 #endif
 595 
 596   static int patch_oop(address insn_addr, address o);
 597   static int patch_narrow_klass(address insn_addr, narrowKlass n);
 598 
 599   address emit_trampoline_stub(int insts_call_instruction_offset, address target);
 600 
 601   // The following 4 methods return the offset of the appropriate move instruction
 602 
 603   // Support for fast byte/short loading with zero extension (depending on particular CPU)
 604   int load_unsigned_byte(Register dst, Address src);
 605   int load_unsigned_short(Register dst, Address src);
 606 
 607   // Support for fast byte/short loading with sign extension (depending on particular CPU)
 608   int load_signed_byte(Register dst, Address src);
 609   int load_signed_short(Register dst, Address src);
 610 
 611   int load_signed_byte32(Register dst, Address src);
 612   int load_signed_short32(Register dst, Address src);
 613 
 614   // Support for sign-extension (hi:lo = extend_sign(lo))
 615   void extend_sign(Register hi, Register lo);
 616 
 617   // Load and store values by size and signed-ness
 618   void load_sized_value(Register dst, Address src, size_t size_in_bytes, bool is_signed, Register dst2 = noreg);
 619   void store_sized_value(Address dst, Register src, size_t size_in_bytes, Register src2 = noreg);
 620 
 621   // Support for inc/dec with optimal instruction selection depending on value
 622 
 623   // x86_64 aliases an unqualified register/address increment and
 624   // decrement to call incrementq and decrementq but also supports
 625   // explicitly sized calls to incrementq/decrementq or
 626   // incrementl/decrementl
 627 
 628   // for aarch64 the proper convention would be to use
 629   // increment/decrement for 64 bit operatons and
 630   // incrementw/decrementw for 32 bit operations. so when porting
 631   // x86_64 code we can leave calls to increment/decrement as is,
 632   // replace incrementq/decrementq with increment/decrement and
 633   // replace incrementl/decrementl with incrementw/decrementw.
 634 
 635   // n.b. increment/decrement calls with an Address destination will
 636   // need to use a scratch register to load the value to be
 637   // incremented. increment/decrement calls which add or subtract a
 638   // constant value greater than 2^12 will need to use a 2nd scratch
 639   // register to hold the constant. so, a register increment/decrement
 640   // may trash rscratch2 and an address increment/decrement trash
 641   // rscratch and rscratch2
 642 
 643   void decrementw(Address dst, int value = 1);
 644   void decrementw(Register reg, int value = 1);
 645 
 646   void decrement(Register reg, int value = 1);
 647   void decrement(Address dst, int value = 1);
 648 
 649   void incrementw(Address dst, int value = 1);
 650   void incrementw(Register reg, int value = 1);
 651 
 652   void increment(Register reg, int value = 1);
 653   void increment(Address dst, int value = 1);
 654 
 655 
 656   // Alignment
 657   void align(int modulus);
 658 
 659   // Stack frame creation/removal
 660   void enter()
 661   {
 662     stp(rfp, lr, Address(pre(sp, -2 * wordSize)));
 663     mov(rfp, sp);
 664   }
 665   void leave()
 666   {
 667     mov(sp, rfp);
 668     ldp(rfp, lr, Address(post(sp, 2 * wordSize)));
 669   }
 670 
 671   // Support for getting the JavaThread pointer (i.e.; a reference to thread-local information)
 672   // The pointer will be loaded into the thread register.
 673   void get_thread(Register thread);
 674 
 675 
 676   // Support for VM calls
 677   //
 678   // It is imperative that all calls into the VM are handled via the call_VM macros.
 679   // They make sure that the stack linkage is setup correctly. call_VM's correspond
 680   // to ENTRY/ENTRY_X entry points while call_VM_leaf's correspond to LEAF entry points.
 681 
 682 
 683   void call_VM(Register oop_result,
 684                address entry_point,
 685                bool check_exceptions = true);
 686   void call_VM(Register oop_result,
 687                address entry_point,
 688                Register arg_1,
 689                bool check_exceptions = true);
 690   void call_VM(Register oop_result,
 691                address entry_point,
 692                Register arg_1, Register arg_2,
 693                bool check_exceptions = true);
 694   void call_VM(Register oop_result,
 695                address entry_point,
 696                Register arg_1, Register arg_2, Register arg_3,
 697                bool check_exceptions = true);
 698 
 699   // Overloadings with last_Java_sp
 700   void call_VM(Register oop_result,
 701                Register last_java_sp,
 702                address entry_point,
 703                int number_of_arguments = 0,
 704                bool check_exceptions = true);
 705   void call_VM(Register oop_result,
 706                Register last_java_sp,
 707                address entry_point,
 708                Register arg_1, bool
 709                check_exceptions = true);
 710   void call_VM(Register oop_result,
 711                Register last_java_sp,
 712                address entry_point,
 713                Register arg_1, Register arg_2,
 714                bool check_exceptions = true);
 715   void call_VM(Register oop_result,
 716                Register last_java_sp,
 717                address entry_point,
 718                Register arg_1, Register arg_2, Register arg_3,
 719                bool check_exceptions = true);
 720 
 721   void get_vm_result  (Register oop_result, Register thread);
 722   void get_vm_result_2(Register metadata_result, Register thread);
 723 
 724   // These always tightly bind to MacroAssembler::call_VM_base
 725   // bypassing the virtual implementation
 726   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, int number_of_arguments = 0, bool check_exceptions = true);
 727   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, bool check_exceptions = true);
 728   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, bool check_exceptions = true);
 729   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, bool check_exceptions = true);
 730   void super_call_VM(Register oop_result, Register last_java_sp, address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4, bool check_exceptions = true);
 731 
 732   void call_VM_leaf(address entry_point,
 733                     int number_of_arguments = 0);
 734   void call_VM_leaf(address entry_point,
 735                     Register arg_1);
 736   void call_VM_leaf(address entry_point,
 737                     Register arg_1, Register arg_2);
 738   void call_VM_leaf(address entry_point,
 739                     Register arg_1, Register arg_2, Register arg_3);
 740 
 741   // These always tightly bind to MacroAssembler::call_VM_leaf_base
 742   // bypassing the virtual implementation
 743   void super_call_VM_leaf(address entry_point);
 744   void super_call_VM_leaf(address entry_point, Register arg_1);
 745   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2);
 746   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3);
 747   void super_call_VM_leaf(address entry_point, Register arg_1, Register arg_2, Register arg_3, Register arg_4);
 748 
 749   // last Java Frame (fills frame anchor)
 750   void set_last_Java_frame(Register last_java_sp,
 751                            Register last_java_fp,
 752                            address last_java_pc,
 753                            Register scratch);
 754 
 755   void set_last_Java_frame(Register last_java_sp,
 756                            Register last_java_fp,
 757                            Label &last_java_pc,
 758                            Register scratch);
 759 
 760   void set_last_Java_frame(Register last_java_sp,
 761                            Register last_java_fp,
 762                            Register last_java_pc,
 763                            Register scratch);
 764 
 765   void reset_last_Java_frame(Register thread);
 766 
 767   // thread in the default location (rthread)
 768   void reset_last_Java_frame(bool clear_fp);
 769 
 770   // Stores
 771   void store_check(Register obj);                // store check for obj - register is destroyed afterwards
 772   void store_check(Register obj, Address dst);   // same as above, dst is exact store location (reg. is destroyed)
 773 
 774 #if INCLUDE_ALL_GCS
 775 
 776   void g1_write_barrier_pre(Register obj,
 777                             Register pre_val,
 778                             Register thread,
 779                             Register tmp,
 780                             bool tosca_live,
 781                             bool expand_call);
 782 
 783   void g1_write_barrier_post(Register store_addr,
 784                              Register new_val,
 785                              Register thread,
 786                              Register tmp,
 787                              Register tmp2);
 788 
 789 #endif // INCLUDE_ALL_GCS
 790 
 791   // oop manipulations
 792   void load_klass(Register dst, Register src);
 793   void store_klass(Register dst, Register src);
 794   void cmp_klass(Register oop, Register trial_klass, Register tmp);
 795 
 796   void resolve_oop_handle(Register result);
 797   void load_mirror(Register dst, Register method);
 798 
 799   void load_heap_oop(Register dst, Address src);
 800 
 801   void load_heap_oop_not_null(Register dst, Address src);
 802   void store_heap_oop(Address dst, Register src);
 803 
 804   // currently unimplemented
 805   // Used for storing NULL. All other oop constants should be
 806   // stored using routines that take a jobject.
 807   void store_heap_oop_null(Address dst);
 808 
 809   void load_prototype_header(Register dst, Register src);
 810 
 811   void store_klass_gap(Register dst, Register src);
 812 
 813   // This dummy is to prevent a call to store_heap_oop from
 814   // converting a zero (like NULL) into a Register by giving
 815   // the compiler two choices it can't resolve
 816 
 817   void store_heap_oop(Address dst, void* dummy);
 818 
 819   void encode_heap_oop(Register d, Register s);
 820   void encode_heap_oop(Register r) { encode_heap_oop(r, r); }
 821   void decode_heap_oop(Register d, Register s);
 822   void decode_heap_oop(Register r) { decode_heap_oop(r, r); }
 823   void encode_heap_oop_not_null(Register r);
 824   void decode_heap_oop_not_null(Register r);
 825   void encode_heap_oop_not_null(Register dst, Register src);
 826   void decode_heap_oop_not_null(Register dst, Register src);
 827 
 828   void set_narrow_oop(Register dst, jobject obj);
 829 
 830   void encode_klass_not_null(Register r);
 831   void decode_klass_not_null(Register r);
 832   void encode_klass_not_null(Register dst, Register src);
 833   void decode_klass_not_null(Register dst, Register src);
 834 
 835   void set_narrow_klass(Register dst, Klass* k);
 836 
 837   // if heap base register is used - reinit it with the correct value
 838   void reinit_heapbase();
 839 
 840   DEBUG_ONLY(void verify_heapbase(const char* msg);)
 841 
 842   void push_CPU_state(bool save_vectors = false);
 843   void pop_CPU_state(bool restore_vectors = false) ;
 844 
 845   // Round up to a power of two
 846   void round_to(Register reg, int modulus);
 847 
 848   // allocation
 849   void eden_allocate(
 850     Register obj,                      // result: pointer to object after successful allocation
 851     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 852     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 853     Register t1,                       // temp register
 854     Label&   slow_case                 // continuation point if fast allocation fails
 855   );
 856   void tlab_allocate(
 857     Register obj,                      // result: pointer to object after successful allocation
 858     Register var_size_in_bytes,        // object size in bytes if unknown at compile time; invalid otherwise
 859     int      con_size_in_bytes,        // object size in bytes if   known at compile time
 860     Register t1,                       // temp register
 861     Register t2,                       // temp register
 862     Label&   slow_case                 // continuation point if fast allocation fails
 863   );
 864   Register tlab_refill(Label& retry_tlab, Label& try_eden, Label& slow_case); // returns TLS address
 865   void zero_memory(Register addr, Register len, Register t1);
 866   void verify_tlab();
 867 
 868   void incr_allocated_bytes(Register thread,
 869                             Register var_size_in_bytes, int con_size_in_bytes,
 870                             Register t1 = noreg);
 871 
 872   // interface method calling
 873   void lookup_interface_method(Register recv_klass,
 874                                Register intf_klass,
 875                                RegisterOrConstant itable_index,
 876                                Register method_result,
 877                                Register scan_temp,
 878                                Label& no_such_interface);
 879 
 880   // virtual method calling
 881   // n.b. x86 allows RegisterOrConstant for vtable_index
 882   void lookup_virtual_method(Register recv_klass,
 883                              RegisterOrConstant vtable_index,
 884                              Register method_result);
 885 
 886   // Test sub_klass against super_klass, with fast and slow paths.
 887 
 888   // The fast path produces a tri-state answer: yes / no / maybe-slow.
 889   // One of the three labels can be NULL, meaning take the fall-through.
 890   // If super_check_offset is -1, the value is loaded up from super_klass.
 891   // No registers are killed, except temp_reg.
 892   void check_klass_subtype_fast_path(Register sub_klass,
 893                                      Register super_klass,
 894                                      Register temp_reg,
 895                                      Label* L_success,
 896                                      Label* L_failure,
 897                                      Label* L_slow_path,
 898                 RegisterOrConstant super_check_offset = RegisterOrConstant(-1));
 899 
 900   // The rest of the type check; must be wired to a corresponding fast path.
 901   // It does not repeat the fast path logic, so don't use it standalone.
 902   // The temp_reg and temp2_reg can be noreg, if no temps are available.
 903   // Updates the sub's secondary super cache as necessary.
 904   // If set_cond_codes, condition codes will be Z on success, NZ on failure.
 905   void check_klass_subtype_slow_path(Register sub_klass,
 906                                      Register super_klass,
 907                                      Register temp_reg,
 908                                      Register temp2_reg,
 909                                      Label* L_success,
 910                                      Label* L_failure,
 911                                      bool set_cond_codes = false);
 912 
 913   // Simplified, combined version, good for typical uses.
 914   // Falls through on failure.
 915   void check_klass_subtype(Register sub_klass,
 916                            Register super_klass,
 917                            Register temp_reg,
 918                            Label& L_success);
 919 
 920   Address argument_address(RegisterOrConstant arg_slot, int extra_slot_offset = 0);
 921 
 922 
 923   // Debugging
 924 
 925   // only if +VerifyOops
 926   void verify_oop(Register reg, const char* s = "broken oop");
 927   void verify_oop_addr(Address addr, const char * s = "broken oop addr");
 928 
 929 // TODO: verify method and klass metadata (compare against vptr?)
 930   void _verify_method_ptr(Register reg, const char * msg, const char * file, int line) {}
 931   void _verify_klass_ptr(Register reg, const char * msg, const char * file, int line){}
 932 
 933 #define verify_method_ptr(reg) _verify_method_ptr(reg, "broken method " #reg, __FILE__, __LINE__)
 934 #define verify_klass_ptr(reg) _verify_klass_ptr(reg, "broken klass " #reg, __FILE__, __LINE__)
 935 
 936   // only if +VerifyFPU
 937   void verify_FPU(int stack_depth, const char* s = "illegal FPU state");
 938 
 939   // prints msg, dumps registers and stops execution
 940   void stop(const char* msg);
 941 
 942   // prints msg and continues
 943   void warn(const char* msg);
 944 
 945   static void debug64(char* msg, int64_t pc, int64_t regs[]);
 946 
 947   void untested()                                { stop("untested"); }
 948 
 949   void unimplemented(const char* what = "");
 950 
 951   void should_not_reach_here()                   { stop("should not reach here"); }
 952 
 953   // Stack overflow checking
 954   void bang_stack_with_offset(int offset) {
 955     // stack grows down, caller passes positive offset
 956     assert(offset > 0, "must bang with negative offset");
 957     sub(rscratch2, sp, offset);
 958     str(zr, Address(rscratch2));
 959   }
 960 
 961   // Writes to stack successive pages until offset reached to check for
 962   // stack overflow + shadow pages.  Also, clobbers tmp
 963   void bang_stack_size(Register size, Register tmp);
 964 
 965   // Check for reserved stack access in method being exited (for JIT)
 966   void reserved_stack_check();
 967 
 968   virtual RegisterOrConstant delayed_value_impl(intptr_t* delayed_value_addr,
 969                                                 Register tmp,
 970                                                 int offset);
 971 
 972   // Support for serializing memory accesses between threads
 973   void serialize_memory(Register thread, Register tmp);
 974 
 975   // Arithmetics
 976 
 977   void addptr(const Address &dst, int32_t src);
 978   void cmpptr(Register src1, Address src2);
 979 
 980   // Various forms of CAS
 981 
 982   void cmpxchg_obj_header(Register oldv, Register newv, Register obj, Register tmp,
 983                           Label &suceed, Label *fail);
 984   void cmpxchgptr(Register oldv, Register newv, Register addr, Register tmp,
 985                   Label &suceed, Label *fail);
 986 
 987   void cmpxchgw(Register oldv, Register newv, Register addr, Register tmp,
 988                   Label &suceed, Label *fail);
 989 
 990   void atomic_add(Register prev, RegisterOrConstant incr, Register addr);
 991   void atomic_addw(Register prev, RegisterOrConstant incr, Register addr);
 992   void atomic_addal(Register prev, RegisterOrConstant incr, Register addr);
 993   void atomic_addalw(Register prev, RegisterOrConstant incr, Register addr);
 994 
 995   void atomic_xchg(Register prev, Register newv, Register addr);
 996   void atomic_xchgw(Register prev, Register newv, Register addr);
 997   void atomic_xchgal(Register prev, Register newv, Register addr);
 998   void atomic_xchgalw(Register prev, Register newv, Register addr);
 999 
1000   void orptr(Address adr, RegisterOrConstant src) {
1001     ldr(rscratch1, adr);
1002     if (src.is_register())
1003       orr(rscratch1, rscratch1, src.as_register());
1004     else
1005       orr(rscratch1, rscratch1, src.as_constant());
1006     str(rscratch1, adr);
1007   }
1008 
1009   // A generic CAS; success or failure is in the EQ flag.
1010   // Clobbers rscratch1
1011   void cmpxchg(Register addr, Register expected, Register new_val,
1012                enum operand_size size,
1013                bool acquire, bool release, bool weak,
1014                Register result);
1015 
1016   // Calls
1017 
1018   address trampoline_call(Address entry, CodeBuffer *cbuf = NULL);
1019 
1020   static bool far_branches() {
1021     return ReservedCodeCacheSize > branch_range;
1022   }
1023 
1024   // Jumps that can reach anywhere in the code cache.
1025   // Trashes tmp.
1026   void far_call(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1027   void far_jump(Address entry, CodeBuffer *cbuf = NULL, Register tmp = rscratch1);
1028 
1029   static int far_branch_size() {
1030     if (far_branches()) {
1031       return 3 * 4;  // adrp, add, br
1032     } else {
1033       return 4;
1034     }
1035   }
1036 
1037   // Emit the CompiledIC call idiom
1038   address ic_call(address entry, jint method_index = 0);
1039 
1040 public:
1041 
1042   // Data
1043 
1044   void mov_metadata(Register dst, Metadata* obj);
1045   Address allocate_metadata_address(Metadata* obj);
1046   Address constant_oop_address(jobject obj);
1047 
1048   void movoop(Register dst, jobject obj, bool immediate = false);
1049 
1050   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1051   void kernel_crc32(Register crc, Register buf, Register len,
1052         Register table0, Register table1, Register table2, Register table3,
1053         Register tmp, Register tmp2, Register tmp3);
1054   // CRC32 code for java.util.zip.CRC32C::updateBytes() instrinsic.
1055   void kernel_crc32c(Register crc, Register buf, Register len,
1056         Register table0, Register table1, Register table2, Register table3,
1057         Register tmp, Register tmp2, Register tmp3);
1058 
1059   // Stack push and pop individual 64 bit registers
1060   void push(Register src);
1061   void pop(Register dst);
1062 
1063   // push all registers onto the stack
1064   void pusha();
1065   void popa();
1066 
1067   void repne_scan(Register addr, Register value, Register count,
1068                   Register scratch);
1069   void repne_scanw(Register addr, Register value, Register count,
1070                    Register scratch);
1071 
1072   typedef void (MacroAssembler::* add_sub_imm_insn)(Register Rd, Register Rn, unsigned imm);
1073   typedef void (MacroAssembler::* add_sub_reg_insn)(Register Rd, Register Rn, Register Rm, enum shift_kind kind, unsigned shift);
1074 
1075   // If a constant does not fit in an immediate field, generate some
1076   // number of MOV instructions and then perform the operation
1077   void wrap_add_sub_imm_insn(Register Rd, Register Rn, unsigned imm,
1078                              add_sub_imm_insn insn1,
1079                              add_sub_reg_insn insn2);
1080   // Seperate vsn which sets the flags
1081   void wrap_adds_subs_imm_insn(Register Rd, Register Rn, unsigned imm,
1082                              add_sub_imm_insn insn1,
1083                              add_sub_reg_insn insn2);
1084 
1085 #define WRAP(INSN)                                                      \
1086   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1087     wrap_add_sub_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1088   }                                                                     \
1089                                                                         \
1090   void INSN(Register Rd, Register Rn, Register Rm,                      \
1091              enum shift_kind kind, unsigned shift = 0) {                \
1092     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1093   }                                                                     \
1094                                                                         \
1095   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1096     Assembler::INSN(Rd, Rn, Rm);                                        \
1097   }                                                                     \
1098                                                                         \
1099   void INSN(Register Rd, Register Rn, Register Rm,                      \
1100            ext::operation option, int amount = 0) {                     \
1101     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1102   }
1103 
1104   WRAP(add) WRAP(addw) WRAP(sub) WRAP(subw)
1105 
1106 #undef WRAP
1107 #define WRAP(INSN)                                                      \
1108   void INSN(Register Rd, Register Rn, unsigned imm) {                   \
1109     wrap_adds_subs_imm_insn(Rd, Rn, imm, &Assembler::INSN, &Assembler::INSN); \
1110   }                                                                     \
1111                                                                         \
1112   void INSN(Register Rd, Register Rn, Register Rm,                      \
1113              enum shift_kind kind, unsigned shift = 0) {                \
1114     Assembler::INSN(Rd, Rn, Rm, kind, shift);                           \
1115   }                                                                     \
1116                                                                         \
1117   void INSN(Register Rd, Register Rn, Register Rm) {                    \
1118     Assembler::INSN(Rd, Rn, Rm);                                        \
1119   }                                                                     \
1120                                                                         \
1121   void INSN(Register Rd, Register Rn, Register Rm,                      \
1122            ext::operation option, int amount = 0) {                     \
1123     Assembler::INSN(Rd, Rn, Rm, option, amount);                        \
1124   }
1125 
1126   WRAP(adds) WRAP(addsw) WRAP(subs) WRAP(subsw)
1127 
1128   void add(Register Rd, Register Rn, RegisterOrConstant increment);
1129   void addw(Register Rd, Register Rn, RegisterOrConstant increment);
1130   void sub(Register Rd, Register Rn, RegisterOrConstant decrement);
1131   void subw(Register Rd, Register Rn, RegisterOrConstant decrement);
1132 
1133   void adrp(Register reg1, const Address &dest, unsigned long &byte_offset);
1134 
1135   void tableswitch(Register index, jint lowbound, jint highbound,
1136                    Label &jumptable, Label &jumptable_end, int stride = 1) {
1137     adr(rscratch1, jumptable);
1138     subsw(rscratch2, index, lowbound);
1139     subsw(zr, rscratch2, highbound - lowbound);
1140     br(Assembler::HS, jumptable_end);
1141     add(rscratch1, rscratch1, rscratch2,
1142         ext::sxtw, exact_log2(stride * Assembler::instruction_size));
1143     br(rscratch1);
1144   }
1145 
1146   // Form an address from base + offset in Rd.  Rd may or may not
1147   // actually be used: you must use the Address that is returned.  It
1148   // is up to you to ensure that the shift provided matches the size
1149   // of your data.
1150   Address form_address(Register Rd, Register base, long byte_offset, int shift);
1151 
1152   // Return true iff an address is within the 48-bit AArch64 address
1153   // space.
1154   bool is_valid_AArch64_address(address a) {
1155     return ((uint64_t)a >> 48) == 0;
1156   }
1157 
1158   // Load the base of the cardtable byte map into reg.
1159   void load_byte_map_base(Register reg);
1160 
1161   // Prolog generator routines to support switch between x86 code and
1162   // generated ARM code
1163 
1164   // routine to generate an x86 prolog for a stub function which
1165   // bootstraps into the generated ARM code which directly follows the
1166   // stub
1167   //
1168 
1169   public:
1170   // enum used for aarch64--x86 linkage to define return type of x86 function
1171   enum ret_type { ret_type_void, ret_type_integral, ret_type_float, ret_type_double};
1172 
1173 #ifdef BUILTIN_SIM
1174   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type, address *prolog_ptr = NULL);
1175 #else
1176   void c_stub_prolog(int gp_arg_count, int fp_arg_count, int ret_type) { }
1177 #endif
1178 
1179   // special version of call_VM_leaf_base needed for aarch64 simulator
1180   // where we need to specify both the gp and fp arg counts and the
1181   // return type so that the linkage routine from aarch64 to x86 and
1182   // back knows which aarch64 registers to copy to x86 registers and
1183   // which x86 result register to copy back to an aarch64 register
1184 
1185   void call_VM_leaf_base1(
1186     address  entry_point,             // the entry point
1187     int      number_of_gp_arguments,  // the number of gp reg arguments to pass
1188     int      number_of_fp_arguments,  // the number of fp reg arguments to pass
1189     ret_type type,                    // the return type for the call
1190     Label*   retaddr = NULL
1191   );
1192 
1193   void ldr_constant(Register dest, const Address &const_addr) {
1194     if (NearCpool) {
1195       ldr(dest, const_addr);
1196     } else {
1197       unsigned long offset;
1198       adrp(dest, InternalAddress(const_addr.target()), offset);
1199       ldr(dest, Address(dest, offset));
1200     }
1201   }
1202 
1203   address read_polling_page(Register r, address page, relocInfo::relocType rtype);
1204   address read_polling_page(Register r, relocInfo::relocType rtype);
1205   void get_polling_page(Register dest, address page, relocInfo::relocType rtype);
1206 
1207   // CRC32 code for java.util.zip.CRC32::updateBytes() instrinsic.
1208   void update_byte_crc32(Register crc, Register val, Register table);
1209   void update_word_crc32(Register crc, Register v, Register tmp,
1210         Register table0, Register table1, Register table2, Register table3,
1211         bool upper = false);
1212 
1213   void string_compare(Register str1, Register str2,
1214                       Register cnt1, Register cnt2, Register result,
1215                       Register tmp1,
1216                       FloatRegister vtmp, FloatRegister vtmpZ, int ae);
1217 
1218   void has_negatives(Register ary1, Register len, Register result);
1219 
1220   void arrays_equals(Register a1, Register a2,
1221                      Register result, Register cnt1,
1222                      int elem_size, bool is_string);
1223 
1224   void fill_words(Register base, Register cnt, Register value);
1225   void zero_words(Register base, u_int64_t cnt);
1226   void zero_words(Register ptr, Register cnt);
1227   void zero_dcache_blocks(Register base, Register cnt);
1228 
1229   static const int zero_words_block_size;
1230 
1231   void byte_array_inflate(Register src, Register dst, Register len,
1232                           FloatRegister vtmp1, FloatRegister vtmp2,
1233                           FloatRegister vtmp3, Register tmp4);
1234 
1235   void char_array_compress(Register src, Register dst, Register len,
1236                            FloatRegister tmp1Reg, FloatRegister tmp2Reg,
1237                            FloatRegister tmp3Reg, FloatRegister tmp4Reg,
1238                            Register result);
1239 
1240   void encode_iso_array(Register src, Register dst,
1241                         Register len, Register result,
1242                         FloatRegister Vtmp1, FloatRegister Vtmp2,
1243                         FloatRegister Vtmp3, FloatRegister Vtmp4);
1244   void string_indexof(Register str1, Register str2,
1245                       Register cnt1, Register cnt2,
1246                       Register tmp1, Register tmp2,
1247                       Register tmp3, Register tmp4,
1248                       int int_cnt1, Register result, int ae);
1249   void string_indexof_char(Register str1, Register cnt1,
1250                            Register ch, Register result,
1251                            Register tmp1, Register tmp2, Register tmp3);
1252 private:
1253   void add2_with_carry(Register final_dest_hi, Register dest_hi, Register dest_lo,
1254                        Register src1, Register src2);
1255   void add2_with_carry(Register dest_hi, Register dest_lo, Register src1, Register src2) {
1256     add2_with_carry(dest_hi, dest_hi, dest_lo, src1, src2);
1257   }
1258   void multiply_64_x_64_loop(Register x, Register xstart, Register x_xstart,
1259                              Register y, Register y_idx, Register z,
1260                              Register carry, Register product,
1261                              Register idx, Register kdx);
1262   void multiply_128_x_128_loop(Register y, Register z,
1263                                Register carry, Register carry2,
1264                                Register idx, Register jdx,
1265                                Register yz_idx1, Register yz_idx2,
1266                                Register tmp, Register tmp3, Register tmp4,
1267                                Register tmp7, Register product_hi);
1268   void kernel_crc32_using_crc32(Register crc, Register buf,
1269         Register len, Register tmp0, Register tmp1, Register tmp2,
1270         Register tmp3);
1271   void kernel_crc32c_using_crc32c(Register crc, Register buf,
1272         Register len, Register tmp0, Register tmp1, Register tmp2,
1273         Register tmp3);
1274 public:
1275   void multiply_to_len(Register x, Register xlen, Register y, Register ylen, Register z,
1276                        Register zlen, Register tmp1, Register tmp2, Register tmp3,
1277                        Register tmp4, Register tmp5, Register tmp6, Register tmp7);
1278   void mul_add(Register out, Register in, Register offs, Register len, Register k);
1279   // ISB may be needed because of a safepoint
1280   void maybe_isb() { isb(); }
1281 
1282 private:
1283   // Return the effective address r + (r1 << ext) + offset.
1284   // Uses rscratch2.
1285   Address offsetted_address(Register r, Register r1, Address::extend ext,
1286                             int offset, int size);
1287 
1288 private:
1289   // Returns an address on the stack which is reachable with a ldr/str of size
1290   // Uses rscratch2 if the address is not directly reachable
1291   Address spill_address(int size, int offset, Register tmp=rscratch2);
1292 
1293 public:
1294   void spill(Register Rx, bool is64, int offset) {
1295     if (is64) {
1296       str(Rx, spill_address(8, offset));
1297     } else {
1298       strw(Rx, spill_address(4, offset));
1299     }
1300   }
1301   void spill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1302     str(Vx, T, spill_address(1 << (int)T, offset));
1303   }
1304   void unspill(Register Rx, bool is64, int offset) {
1305     if (is64) {
1306       ldr(Rx, spill_address(8, offset));
1307     } else {
1308       ldrw(Rx, spill_address(4, offset));
1309     }
1310   }
1311   void unspill(FloatRegister Vx, SIMD_RegVariant T, int offset) {
1312     ldr(Vx, T, spill_address(1 << (int)T, offset));
1313   }
1314   void spill_copy128(int src_offset, int dst_offset,
1315                      Register tmp1=rscratch1, Register tmp2=rscratch2) {
1316     if (src_offset < 512 && (src_offset & 7) == 0 &&
1317         dst_offset < 512 && (dst_offset & 7) == 0) {
1318       ldp(tmp1, tmp2, Address(sp, src_offset));
1319       stp(tmp1, tmp2, Address(sp, dst_offset));
1320     } else {
1321       unspill(tmp1, true, src_offset);
1322       spill(tmp1, true, dst_offset);
1323       unspill(tmp1, true, src_offset+8);
1324       spill(tmp1, true, dst_offset+8);
1325     }
1326   }
1327 };
1328 
1329 #ifdef ASSERT
1330 inline bool AbstractAssembler::pd_check_instruction_mark() { return false; }
1331 #endif
1332 
1333 /**
1334  * class SkipIfEqual:
1335  *
1336  * Instantiating this class will result in assembly code being output that will
1337  * jump around any code emitted between the creation of the instance and it's
1338  * automatic destruction at the end of a scope block, depending on the value of
1339  * the flag passed to the constructor, which will be checked at run-time.
1340  */
1341 class SkipIfEqual {
1342  private:
1343   MacroAssembler* _masm;
1344   Label _label;
1345 
1346  public:
1347    SkipIfEqual(MacroAssembler*, const bool* flag_addr, bool value);
1348    ~SkipIfEqual();
1349 };
1350 
1351 struct tableswitch {
1352   Register _reg;
1353   int _insn_index; jint _first_key; jint _last_key;
1354   Label _after;
1355   Label _branches;
1356 };
1357 
1358 #endif // CPU_AARCH64_VM_MACROASSEMBLER_AARCH64_HPP
--- EOF ---