1 /*
2 * Copyright (c) 1997, 2012, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2014, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 */
24
25 #include <stdio.h>
26 #include <sys/types.h>
27
28 #include "precompiled.hpp"
29 #include "asm/assembler.hpp"
30 #include "asm/assembler.inline.hpp"
31 #include "interpreter/interpreter.hpp"
32
33 #ifndef PRODUCT
34 const unsigned long Assembler::asm_bp = 0x00007fffee09ac88;
35 #endif
36
37 #include "compiler/disassembler.hpp"
38 #include "memory/resourceArea.hpp"
39 #include "runtime/interfaceSupport.inline.hpp"
40 #include "runtime/sharedRuntime.hpp"
41
42 // for the moment we reuse the logical/floating point immediate encode
43 // and decode functiosn provided by the simulator. when we move to
44 // real hardware we will need to pull taht code into here
45
46 #include "immediate_aarch64.hpp"
47
48 extern "C" void entry(CodeBuffer *cb);
49
50 #define __ _masm.
51 #ifdef PRODUCT
52 #define BLOCK_COMMENT(str) /* nothing */
53 #else
54 #define BLOCK_COMMENT(str) block_comment(str)
55 #endif
56
57 #define BIND(label) bind(label); __ BLOCK_COMMENT(#label ":")
58
59 static float unpack(unsigned value);
60
61 short Assembler::SIMD_Size_in_bytes[] = {
62 // T8B, T16B, T4H, T8H, T2S, T4S, T1D, T2D, T1Q
63 8, 16, 8, 16, 8, 16, 8, 16, 16
64 };
65
66 #ifdef ASSERT
67 static void asm_check(const unsigned int *insns, const unsigned int *insns1, size_t len) {
68 bool ok = true;
69 for (unsigned int i = 0; i < len; i++) {
70 if (insns[i] != insns1[i]) {
71 ok = false;
72 printf("Ours:\n");
73 Disassembler::decode((address)&insns1[i], (address)&insns1[i+1]);
74 printf("Theirs:\n");
75 Disassembler::decode((address)&insns[i], (address)&insns[i+1]);
76 printf("\n");
77 }
78 }
79 assert(ok, "Assembler smoke test failed");
80 }
81 #endif // ASSERT
82
83 void entry(CodeBuffer *cb) {
84
85 // {
86 // for (int i = 0; i < 256; i+=16)
87 // {
88 // printf("\"%20.20g\", ", unpack(i));
89 // printf("\"%20.20g\", ", unpack(i+1));
90 // }
91 // printf("\n");
92 // }
93
94 Assembler _masm(cb);
95 address entry = __ pc();
96
97 // Smoke test for assembler
98
99 #ifdef ASSERT
100 // BEGIN Generated code -- do not edit
101 // Generated by aarch64-asmtest.py
102 Label back, forth;
103 __ bind(back);
104
105 // ArithOp
106 __ add(r19, r22, r7, Assembler::LSL, 28); // add x19, x22, x7, LSL #28
107 __ sub(r16, r11, r10, Assembler::LSR, 13); // sub x16, x11, x10, LSR #13
108 __ adds(r27, r13, r28, Assembler::ASR, 2); // adds x27, x13, x28, ASR #2
109 __ subs(r20, r28, r26, Assembler::ASR, 41); // subs x20, x28, x26, ASR #41
110 __ addw(r8, r19, r19, Assembler::ASR, 19); // add w8, w19, w19, ASR #19
111 __ subw(r4, r9, r10, Assembler::LSL, 14); // sub w4, w9, w10, LSL #14
112 __ addsw(r8, r11, r30, Assembler::LSL, 13); // adds w8, w11, w30, LSL #13
113 __ subsw(r0, r25, r19, Assembler::LSL, 9); // subs w0, w25, w19, LSL #9
114 __ andr(r20, r0, r21, Assembler::LSL, 19); // and x20, x0, x21, LSL #19
115 __ orr(r21, r14, r20, Assembler::LSL, 17); // orr x21, x14, x20, LSL #17
116 __ eor(r25, r28, r1, Assembler::LSL, 51); // eor x25, x28, x1, LSL #51
117 __ ands(r10, r27, r11, Assembler::ASR, 15); // ands x10, x27, x11, ASR #15
118 __ andw(r25, r5, r12, Assembler::ASR, 23); // and w25, w5, w12, ASR #23
119 __ orrw(r18, r14, r10, Assembler::LSR, 4); // orr w18, w14, w10, LSR #4
120 __ eorw(r4, r21, r5, Assembler::ASR, 22); // eor w4, w21, w5, ASR #22
121 __ andsw(r21, r0, r5, Assembler::ASR, 29); // ands w21, w0, w5, ASR #29
122 __ bic(r26, r30, r6, Assembler::ASR, 37); // bic x26, x30, x6, ASR #37
123 __ orn(r3, r1, r13, Assembler::LSR, 29); // orn x3, x1, x13, LSR #29
124 __ eon(r0, r28, r9, Assembler::LSL, 47); // eon x0, x28, x9, LSL #47
125 __ bics(r29, r5, r28, Assembler::LSL, 46); // bics x29, x5, x28, LSL #46
126 __ bicw(r9, r18, r7, Assembler::LSR, 20); // bic w9, w18, w7, LSR #20
127 __ ornw(r26, r13, r25, Assembler::ASR, 24); // orn w26, w13, w25, ASR #24
128 __ eonw(r25, r4, r19, Assembler::LSL, 6); // eon w25, w4, w19, LSL #6
129 __ bicsw(r5, r26, r4, Assembler::LSR, 24); // bics w5, w26, w4, LSR #24
130
131 // AddSubImmOp
132 __ addw(r7, r19, 340u); // add w7, w19, #340
133 __ addsw(r8, r0, 401u); // adds w8, w0, #401
134 __ subw(r29, r20, 163u); // sub w29, w20, #163
135 __ subsw(r8, r23, 759u); // subs w8, w23, #759
136 __ add(r1, r12, 523u); // add x1, x12, #523
137 __ adds(r2, r11, 426u); // adds x2, x11, #426
138 __ sub(r14, r29, 716u); // sub x14, x29, #716
139 __ subs(r11, r5, 582u); // subs x11, x5, #582
140
141 // LogicalImmOp
142 __ andw(r23, r22, 32768ul); // and w23, w22, #0x8000
143 __ orrw(r4, r10, 4042322160ul); // orr w4, w10, #0xf0f0f0f0
144 __ eorw(r0, r24, 4042322160ul); // eor w0, w24, #0xf0f0f0f0
145 __ andsw(r19, r29, 2139127680ul); // ands w19, w29, #0x7f807f80
146 __ andr(r5, r10, 4503599627354112ul); // and x5, x10, #0xfffffffffc000
147 __ orr(r12, r30, 18445618178097414144ul); // orr x12, x30, #0xfffc0000fffc0000
148 __ eor(r30, r5, 262128ul); // eor x30, x5, #0x3fff0
149 __ ands(r26, r23, 4194300ul); // ands x26, x23, #0x3ffffc
150
151 // AbsOp
152 __ b(__ pc()); // b .
153 __ b(back); // b back
154 __ b(forth); // b forth
155 __ bl(__ pc()); // bl .
156 __ bl(back); // bl back
157 __ bl(forth); // bl forth
158
159 // RegAndAbsOp
160 __ cbzw(r12, __ pc()); // cbz w12, .
161 __ cbzw(r12, back); // cbz w12, back
162 __ cbzw(r12, forth); // cbz w12, forth
163 __ cbnzw(r20, __ pc()); // cbnz w20, .
164 __ cbnzw(r20, back); // cbnz w20, back
165 __ cbnzw(r20, forth); // cbnz w20, forth
166 __ cbz(r12, __ pc()); // cbz x12, .
167 __ cbz(r12, back); // cbz x12, back
168 __ cbz(r12, forth); // cbz x12, forth
169 __ cbnz(r24, __ pc()); // cbnz x24, .
170 __ cbnz(r24, back); // cbnz x24, back
171 __ cbnz(r24, forth); // cbnz x24, forth
172 __ adr(r6, __ pc()); // adr x6, .
173 __ adr(r6, back); // adr x6, back
174 __ adr(r6, forth); // adr x6, forth
175 __ _adrp(r21, __ pc()); // adrp x21, .
176
177 // RegImmAbsOp
178 __ tbz(r1, 1, __ pc()); // tbz x1, #1, .
179 __ tbz(r1, 1, back); // tbz x1, #1, back
180 __ tbz(r1, 1, forth); // tbz x1, #1, forth
181 __ tbnz(r8, 9, __ pc()); // tbnz x8, #9, .
182 __ tbnz(r8, 9, back); // tbnz x8, #9, back
183 __ tbnz(r8, 9, forth); // tbnz x8, #9, forth
184
185 // MoveWideImmOp
186 __ movnw(r12, 23175, 0); // movn w12, #23175, lsl 0
187 __ movzw(r11, 20476, 16); // movz w11, #20476, lsl 16
188 __ movkw(r21, 3716, 0); // movk w21, #3716, lsl 0
189 __ movn(r29, 28661, 48); // movn x29, #28661, lsl 48
190 __ movz(r3, 6927, 0); // movz x3, #6927, lsl 0
191 __ movk(r22, 9828, 16); // movk x22, #9828, lsl 16
192
193 // BitfieldOp
194 __ sbfm(r12, r8, 6, 22); // sbfm x12, x8, #6, #22
195 __ bfmw(r19, r25, 25, 19); // bfm w19, w25, #25, #19
196 __ ubfmw(r9, r12, 29, 15); // ubfm w9, w12, #29, #15
197 __ sbfm(r28, r25, 16, 16); // sbfm x28, x25, #16, #16
198 __ bfm(r12, r5, 4, 25); // bfm x12, x5, #4, #25
199 __ ubfm(r0, r10, 6, 8); // ubfm x0, x10, #6, #8
200
201 // ExtractOp
202 __ extrw(r4, r13, r26, 24); // extr w4, w13, w26, #24
203 __ extr(r23, r30, r24, 31); // extr x23, x30, x24, #31
204
205 // CondBranchOp
206 __ br(Assembler::EQ, __ pc()); // b.EQ .
207 __ br(Assembler::EQ, back); // b.EQ back
208 __ br(Assembler::EQ, forth); // b.EQ forth
209 __ br(Assembler::NE, __ pc()); // b.NE .
210 __ br(Assembler::NE, back); // b.NE back
211 __ br(Assembler::NE, forth); // b.NE forth
212 __ br(Assembler::HS, __ pc()); // b.HS .
213 __ br(Assembler::HS, back); // b.HS back
214 __ br(Assembler::HS, forth); // b.HS forth
215 __ br(Assembler::CS, __ pc()); // b.CS .
216 __ br(Assembler::CS, back); // b.CS back
217 __ br(Assembler::CS, forth); // b.CS forth
218 __ br(Assembler::LO, __ pc()); // b.LO .
219 __ br(Assembler::LO, back); // b.LO back
220 __ br(Assembler::LO, forth); // b.LO forth
221 __ br(Assembler::CC, __ pc()); // b.CC .
222 __ br(Assembler::CC, back); // b.CC back
223 __ br(Assembler::CC, forth); // b.CC forth
224 __ br(Assembler::MI, __ pc()); // b.MI .
225 __ br(Assembler::MI, back); // b.MI back
226 __ br(Assembler::MI, forth); // b.MI forth
227 __ br(Assembler::PL, __ pc()); // b.PL .
228 __ br(Assembler::PL, back); // b.PL back
229 __ br(Assembler::PL, forth); // b.PL forth
230 __ br(Assembler::VS, __ pc()); // b.VS .
231 __ br(Assembler::VS, back); // b.VS back
232 __ br(Assembler::VS, forth); // b.VS forth
233 __ br(Assembler::VC, __ pc()); // b.VC .
234 __ br(Assembler::VC, back); // b.VC back
235 __ br(Assembler::VC, forth); // b.VC forth
236 __ br(Assembler::HI, __ pc()); // b.HI .
237 __ br(Assembler::HI, back); // b.HI back
238 __ br(Assembler::HI, forth); // b.HI forth
239 __ br(Assembler::LS, __ pc()); // b.LS .
240 __ br(Assembler::LS, back); // b.LS back
241 __ br(Assembler::LS, forth); // b.LS forth
242 __ br(Assembler::GE, __ pc()); // b.GE .
243 __ br(Assembler::GE, back); // b.GE back
244 __ br(Assembler::GE, forth); // b.GE forth
245 __ br(Assembler::LT, __ pc()); // b.LT .
246 __ br(Assembler::LT, back); // b.LT back
247 __ br(Assembler::LT, forth); // b.LT forth
248 __ br(Assembler::GT, __ pc()); // b.GT .
249 __ br(Assembler::GT, back); // b.GT back
250 __ br(Assembler::GT, forth); // b.GT forth
251 __ br(Assembler::LE, __ pc()); // b.LE .
252 __ br(Assembler::LE, back); // b.LE back
253 __ br(Assembler::LE, forth); // b.LE forth
254 __ br(Assembler::AL, __ pc()); // b.AL .
255 __ br(Assembler::AL, back); // b.AL back
256 __ br(Assembler::AL, forth); // b.AL forth
257 __ br(Assembler::NV, __ pc()); // b.NV .
258 __ br(Assembler::NV, back); // b.NV back
259 __ br(Assembler::NV, forth); // b.NV forth
260
261 // ImmOp
262 __ svc(12729); // svc #12729
263 __ hvc(6788); // hvc #6788
264 __ smc(1535); // smc #1535
265 __ brk(16766); // brk #16766
266 __ hlt(9753); // hlt #9753
267
268 // Op
269 __ nop(); // nop
270 __ eret(); // eret
271 __ drps(); // drps
272 __ isb(); // isb
273
274 // SystemOp
275 __ dsb(Assembler::SY); // dsb SY
276 __ dmb(Assembler::ISHST); // dmb ISHST
277
278 // OneRegOp
279 __ br(r2); // br x2
280 __ blr(r5); // blr x5
281
282 // LoadStoreExclusiveOp
283 __ stxr(r20, r21, r2); // stxr w20, x21, [x2]
284 __ stlxr(r5, r29, r7); // stlxr w5, x29, [x7]
285 __ ldxr(r5, r16); // ldxr x5, [x16]
286 __ ldaxr(r27, r29); // ldaxr x27, [x29]
287 __ stlr(r0, r29); // stlr x0, [x29]
288 __ ldar(r21, r28); // ldar x21, [x28]
289
290 // LoadStoreExclusiveOp
291 __ stxrw(r21, r24, r7); // stxr w21, w24, [x7]
292 __ stlxrw(r21, r26, r28); // stlxr w21, w26, [x28]
293 __ ldxrw(r21, r6); // ldxr w21, [x6]
294 __ ldaxrw(r15, r30); // ldaxr w15, [x30]
295 __ stlrw(r19, r3); // stlr w19, [x3]
296 __ ldarw(r22, r2); // ldar w22, [x2]
297
298 // LoadStoreExclusiveOp
299 __ stxrh(r18, r15, r0); // stxrh w18, w15, [x0]
300 __ stlxrh(r11, r5, r28); // stlxrh w11, w5, [x28]
301 __ ldxrh(r29, r6); // ldxrh w29, [x6]
302 __ ldaxrh(r18, r7); // ldaxrh w18, [x7]
303 __ stlrh(r25, r28); // stlrh w25, [x28]
304 __ ldarh(r2, r19); // ldarh w2, [x19]
305
306 // LoadStoreExclusiveOp
307 __ stxrb(r10, r30, r1); // stxrb w10, w30, [x1]
308 __ stlxrb(r20, r21, r22); // stlxrb w20, w21, [x22]
309 __ ldxrb(r25, r2); // ldxrb w25, [x2]
310 __ ldaxrb(r24, r5); // ldaxrb w24, [x5]
311 __ stlrb(r16, r3); // stlrb w16, [x3]
312 __ ldarb(r22, r29); // ldarb w22, [x29]
313
314 // LoadStoreExclusiveOp
315 __ ldxp(r8, r2, r19); // ldxp x8, x2, [x19]
316 __ ldaxp(r7, r19, r14); // ldaxp x7, x19, [x14]
317 __ stxp(r8, r27, r28, r5); // stxp w8, x27, x28, [x5]
318 __ stlxp(r5, r8, r14, r6); // stlxp w5, x8, x14, [x6]
319
320 // LoadStoreExclusiveOp
321 __ ldxpw(r25, r4, r22); // ldxp w25, w4, [x22]
322 __ ldaxpw(r13, r14, r15); // ldaxp w13, w14, [x15]
323 __ stxpw(r20, r26, r8, r10); // stxp w20, w26, w8, [x10]
324 __ stlxpw(r23, r18, r18, r18); // stlxp w23, w18, w18, [x18]
325
326 // base_plus_unscaled_offset
327 // LoadStoreOp
328 __ str(r30, Address(r11, 99)); // str x30, [x11, 99]
329 __ strw(r23, Address(r25, -77)); // str w23, [x25, -77]
330 __ strb(r2, Address(r14, 3)); // strb w2, [x14, 3]
331 __ strh(r9, Address(r10, 5)); // strh w9, [x10, 5]
332 __ ldr(r20, Address(r15, 57)); // ldr x20, [x15, 57]
333 __ ldrw(r12, Address(r16, -78)); // ldr w12, [x16, -78]
334 __ ldrb(r22, Address(r26, -3)); // ldrb w22, [x26, -3]
335 __ ldrh(r30, Address(r19, -47)); // ldrh w30, [x19, -47]
336 __ ldrsb(r9, Address(r10, -12)); // ldrsb x9, [x10, -12]
337 __ ldrsh(r28, Address(r17, 14)); // ldrsh x28, [x17, 14]
338 __ ldrshw(r3, Address(r5, 10)); // ldrsh w3, [x5, 10]
339 __ ldrsw(r17, Address(r17, -91)); // ldrsw x17, [x17, -91]
340 __ ldrd(v2, Address(r20, -17)); // ldr d2, [x20, -17]
341 __ ldrs(v22, Address(r7, -10)); // ldr s22, [x7, -10]
342 __ strd(v30, Address(r18, -223)); // str d30, [x18, -223]
343 __ strs(v13, Address(r22, 21)); // str s13, [x22, 21]
344
345 // pre
346 // LoadStoreOp
347 __ str(r9, Address(__ pre(r18, -112))); // str x9, [x18, -112]!
348 __ strw(r29, Address(__ pre(r23, 11))); // str w29, [x23, 11]!
349 __ strb(r18, Address(__ pre(r12, -1))); // strb w18, [x12, -1]!
350 __ strh(r16, Address(__ pre(r20, -23))); // strh w16, [x20, -23]!
351 __ ldr(r3, Address(__ pre(r29, 9))); // ldr x3, [x29, 9]!
352 __ ldrw(r25, Address(__ pre(r3, 19))); // ldr w25, [x3, 19]!
353 __ ldrb(r1, Address(__ pre(r29, -1))); // ldrb w1, [x29, -1]!
354 __ ldrh(r8, Address(__ pre(r29, -57))); // ldrh w8, [x29, -57]!
355 __ ldrsb(r5, Address(__ pre(r14, -13))); // ldrsb x5, [x14, -13]!
356 __ ldrsh(r10, Address(__ pre(r27, 1))); // ldrsh x10, [x27, 1]!
357 __ ldrshw(r11, Address(__ pre(r10, 25))); // ldrsh w11, [x10, 25]!
358 __ ldrsw(r4, Address(__ pre(r22, -92))); // ldrsw x4, [x22, -92]!
359 __ ldrd(v11, Address(__ pre(r23, 8))); // ldr d11, [x23, 8]!
360 __ ldrs(v25, Address(__ pre(r19, 54))); // ldr s25, [x19, 54]!
361 __ strd(v1, Address(__ pre(r7, -174))); // str d1, [x7, -174]!
362 __ strs(v8, Address(__ pre(r25, 54))); // str s8, [x25, 54]!
363
364 // post
365 // LoadStoreOp
366 __ str(r5, Address(__ post(r11, 37))); // str x5, [x11], 37
367 __ strw(r24, Address(__ post(r15, 19))); // str w24, [x15], 19
368 __ strb(r15, Address(__ post(r26, -1))); // strb w15, [x26], -1
369 __ strh(r18, Address(__ post(r18, -6))); // strh w18, [x18], -6
370 __ ldr(r7, Address(__ post(r2, -230))); // ldr x7, [x2], -230
371 __ ldrw(r27, Address(__ post(r11, -27))); // ldr w27, [x11], -27
372 __ ldrb(r18, Address(__ post(r3, -25))); // ldrb w18, [x3], -25
373 __ ldrh(r10, Address(__ post(r24, -32))); // ldrh w10, [x24], -32
374 __ ldrsb(r22, Address(__ post(r10, 4))); // ldrsb x22, [x10], 4
375 __ ldrsh(r17, Address(__ post(r12, 25))); // ldrsh x17, [x12], 25
376 __ ldrshw(r8, Address(__ post(r7, -62))); // ldrsh w8, [x7], -62
377 __ ldrsw(r23, Address(__ post(r22, -51))); // ldrsw x23, [x22], -51
378 __ ldrd(v24, Address(__ post(r25, 48))); // ldr d24, [x25], 48
379 __ ldrs(v21, Address(__ post(r12, -10))); // ldr s21, [x12], -10
380 __ strd(v18, Address(__ post(r13, -222))); // str d18, [x13], -222
381 __ strs(v16, Address(__ post(r1, -41))); // str s16, [x1], -41
382
383 // base_plus_reg
384 // LoadStoreOp
385 __ str(r2, Address(r22, r15, Address::sxtw(0))); // str x2, [x22, w15, sxtw #0]
386 __ strw(r2, Address(r16, r29, Address::lsl(0))); // str w2, [x16, x29, lsl #0]
387 __ strb(r20, Address(r18, r14, Address::uxtw(0))); // strb w20, [x18, w14, uxtw #0]
388 __ strh(r6, Address(r19, r20, Address::sxtx(1))); // strh w6, [x19, x20, sxtx #1]
389 __ ldr(r14, Address(r29, r14, Address::sxtw(0))); // ldr x14, [x29, w14, sxtw #0]
390 __ ldrw(r16, Address(r20, r12, Address::sxtw(2))); // ldr w16, [x20, w12, sxtw #2]
391 __ ldrb(r9, Address(r12, r0, Address::sxtw(0))); // ldrb w9, [x12, w0, sxtw #0]
392 __ ldrh(r12, Address(r17, r3, Address::lsl(1))); // ldrh w12, [x17, x3, lsl #1]
393 __ ldrsb(r2, Address(r17, r3, Address::sxtx(0))); // ldrsb x2, [x17, x3, sxtx #0]
394 __ ldrsh(r7, Address(r1, r17, Address::uxtw(1))); // ldrsh x7, [x1, w17, uxtw #1]
395 __ ldrshw(r25, Address(r15, r18, Address::sxtw(1))); // ldrsh w25, [x15, w18, sxtw #1]
396 __ ldrsw(r23, Address(r21, r12, Address::lsl(0))); // ldrsw x23, [x21, x12, lsl #0]
397 __ ldrd(v5, Address(r13, r8, Address::lsl(3))); // ldr d5, [x13, x8, lsl #3]
398 __ ldrs(v3, Address(r10, r22, Address::lsl(2))); // ldr s3, [x10, x22, lsl #2]
399 __ strd(v14, Address(r2, r27, Address::sxtw(0))); // str d14, [x2, w27, sxtw #0]
400 __ strs(v20, Address(r6, r25, Address::lsl(0))); // str s20, [x6, x25, lsl #0]
401
402 // base_plus_scaled_offset
403 // LoadStoreOp
404 __ str(r30, Address(r7, 16256)); // str x30, [x7, 16256]
405 __ strw(r15, Address(r8, 7588)); // str w15, [x8, 7588]
406 __ strb(r11, Address(r0, 1866)); // strb w11, [x0, 1866]
407 __ strh(r3, Address(r17, 3734)); // strh w3, [x17, 3734]
408 __ ldr(r2, Address(r7, 14224)); // ldr x2, [x7, 14224]
409 __ ldrw(r5, Address(r9, 7396)); // ldr w5, [x9, 7396]
410 __ ldrb(r28, Address(r9, 1721)); // ldrb w28, [x9, 1721]
411 __ ldrh(r2, Address(r20, 3656)); // ldrh w2, [x20, 3656]
412 __ ldrsb(r22, Address(r14, 1887)); // ldrsb x22, [x14, 1887]
413 __ ldrsh(r8, Address(r0, 4080)); // ldrsh x8, [x0, 4080]
414 __ ldrshw(r0, Address(r30, 3916)); // ldrsh w0, [x30, 3916]
415 __ ldrsw(r24, Address(r19, 6828)); // ldrsw x24, [x19, 6828]
416 __ ldrd(v24, Address(r12, 13032)); // ldr d24, [x12, 13032]
417 __ ldrs(v8, Address(r8, 7452)); // ldr s8, [x8, 7452]
418 __ strd(v10, Address(r15, 15992)); // str d10, [x15, 15992]
419 __ strs(v26, Address(r19, 6688)); // str s26, [x19, 6688]
420
421 // pcrel
422 // LoadStoreOp
423 __ ldr(r10, forth); // ldr x10, forth
424 __ ldrw(r3, __ pc()); // ldr w3, .
425
426 // LoadStoreOp
427 __ prfm(Address(r23, 9)); // prfm PLDL1KEEP, [x23, 9]
428
429 // LoadStoreOp
430 __ prfm(back); // prfm PLDL1KEEP, back
431
432 // LoadStoreOp
433 __ prfm(Address(r3, r8, Address::uxtw(0))); // prfm PLDL1KEEP, [x3, w8, uxtw #0]
434
435 // LoadStoreOp
436 __ prfm(Address(r11, 15080)); // prfm PLDL1KEEP, [x11, 15080]
437
438 // AddSubCarryOp
439 __ adcw(r13, r9, r28); // adc w13, w9, w28
440 __ adcsw(r27, r19, r28); // adcs w27, w19, w28
441 __ sbcw(r19, r18, r6); // sbc w19, w18, w6
442 __ sbcsw(r14, r20, r3); // sbcs w14, w20, w3
443 __ adc(r16, r14, r8); // adc x16, x14, x8
444 __ adcs(r0, r29, r8); // adcs x0, x29, x8
445 __ sbc(r8, r24, r20); // sbc x8, x24, x20
446 __ sbcs(r12, r28, r0); // sbcs x12, x28, x0
447
448 // AddSubExtendedOp
449 __ addw(r23, r6, r16, ext::uxtb, 4); // add w23, w6, w16, uxtb #4
450 __ addsw(r25, r25, r23, ext::sxth, 2); // adds w25, w25, w23, sxth #2
451 __ sub(r26, r22, r4, ext::uxtx, 1); // sub x26, x22, x4, uxtx #1
452 __ subsw(r17, r29, r19, ext::sxtx, 3); // subs w17, w29, w19, sxtx #3
453 __ add(r11, r30, r21, ext::uxtb, 3); // add x11, x30, x21, uxtb #3
454 __ adds(r16, r19, r0, ext::sxtb, 2); // adds x16, x19, x0, sxtb #2
455 __ sub(r11, r9, r25, ext::sxtx, 1); // sub x11, x9, x25, sxtx #1
456 __ subs(r17, r20, r12, ext::sxtb, 4); // subs x17, x20, x12, sxtb #4
457
458 // ConditionalCompareOp
459 __ ccmnw(r13, r11, 3u, Assembler::LE); // ccmn w13, w11, #3, LE
460 __ ccmpw(r13, r12, 2u, Assembler::HI); // ccmp w13, w12, #2, HI
461 __ ccmn(r3, r2, 12u, Assembler::NE); // ccmn x3, x2, #12, NE
462 __ ccmp(r7, r21, 3u, Assembler::VS); // ccmp x7, x21, #3, VS
463
464 // ConditionalCompareImmedOp
465 __ ccmnw(r2, 14, 4, Assembler::CC); // ccmn w2, #14, #4, CC
466 __ ccmpw(r17, 17, 6, Assembler::PL); // ccmp w17, #17, #6, PL
467 __ ccmn(r10, 12, 0, Assembler::CS); // ccmn x10, #12, #0, CS
468 __ ccmp(r21, 18, 14, Assembler::GE); // ccmp x21, #18, #14, GE
469
470 // ConditionalSelectOp
471 __ cselw(r21, r13, r12, Assembler::GT); // csel w21, w13, w12, GT
472 __ csincw(r10, r27, r15, Assembler::LS); // csinc w10, w27, w15, LS
473 __ csinvw(r0, r13, r9, Assembler::HI); // csinv w0, w13, w9, HI
474 __ csnegw(r18, r4, r26, Assembler::VS); // csneg w18, w4, w26, VS
475 __ csel(r12, r29, r7, Assembler::LS); // csel x12, x29, x7, LS
476 __ csinc(r6, r7, r20, Assembler::VC); // csinc x6, x7, x20, VC
477 __ csinv(r22, r21, r3, Assembler::LE); // csinv x22, x21, x3, LE
478 __ csneg(r19, r12, r27, Assembler::LS); // csneg x19, x12, x27, LS
479
480 // TwoRegOp
481 __ rbitw(r0, r16); // rbit w0, w16
482 __ rev16w(r17, r23); // rev16 w17, w23
483 __ revw(r17, r14); // rev w17, w14
484 __ clzw(r24, r30); // clz w24, w30
485 __ clsw(r24, r22); // cls w24, w22
486 __ rbit(r3, r17); // rbit x3, x17
487 __ rev16(r12, r13); // rev16 x12, x13
488 __ rev32(r9, r22); // rev32 x9, x22
489 __ rev(r0, r0); // rev x0, x0
490 __ clz(r5, r16); // clz x5, x16
491 __ cls(r25, r22); // cls x25, x22
492
493 // ThreeRegOp
494 __ udivw(r29, r4, r0); // udiv w29, w4, w0
495 __ sdivw(r0, r29, r29); // sdiv w0, w29, w29
496 __ lslvw(r5, r17, r21); // lslv w5, w17, w21
497 __ lsrvw(r9, r9, r18); // lsrv w9, w9, w18
498 __ asrvw(r1, r27, r8); // asrv w1, w27, w8
499 __ rorvw(r18, r20, r13); // rorv w18, w20, w13
500 __ udiv(r8, r25, r12); // udiv x8, x25, x12
501 __ sdiv(r7, r5, r28); // sdiv x7, x5, x28
502 __ lslv(r5, r17, r27); // lslv x5, x17, x27
503 __ lsrv(r23, r26, r20); // lsrv x23, x26, x20
504 __ asrv(r28, r8, r28); // asrv x28, x8, x28
505 __ rorv(r3, r29, r4); // rorv x3, x29, x4
506
507 // FourRegMulOp
508 __ maddw(r17, r14, r26, r21); // madd w17, w14, w26, w21
509 __ msubw(r1, r30, r11, r11); // msub w1, w30, w11, w11
510 __ madd(r1, r17, r6, r28); // madd x1, x17, x6, x28
511 __ msub(r30, r6, r30, r8); // msub x30, x6, x30, x8
512 __ smaddl(r21, r6, r14, r8); // smaddl x21, w6, w14, x8
513 __ smsubl(r10, r10, r24, r19); // smsubl x10, w10, w24, x19
514 __ umaddl(r20, r18, r14, r24); // umaddl x20, w18, w14, x24
515 __ umsubl(r18, r2, r5, r5); // umsubl x18, w2, w5, x5
516
517 // ThreeRegFloatOp
518 __ fmuls(v8, v18, v13); // fmul s8, s18, s13
519 __ fdivs(v2, v14, v28); // fdiv s2, s14, s28
520 __ fadds(v15, v12, v28); // fadd s15, s12, s28
521 __ fsubs(v0, v12, v1); // fsub s0, s12, s1
522 __ fmuls(v15, v29, v4); // fmul s15, s29, s4
523 __ fmuld(v12, v1, v23); // fmul d12, d1, d23
524 __ fdivd(v27, v8, v18); // fdiv d27, d8, d18
525 __ faddd(v23, v20, v11); // fadd d23, d20, d11
526 __ fsubd(v8, v12, v18); // fsub d8, d12, d18
527 __ fmuld(v26, v24, v23); // fmul d26, d24, d23
528
529 // FourRegFloatOp
530 __ fmadds(v21, v23, v13, v25); // fmadd s21, s23, s13, s25
531 __ fmsubs(v22, v10, v1, v14); // fmsub s22, s10, s1, s14
532 __ fnmadds(v14, v20, v2, v30); // fnmadd s14, s20, s2, s30
533 __ fnmadds(v7, v29, v22, v22); // fnmadd s7, s29, s22, s22
534 __ fmaddd(v13, v5, v15, v5); // fmadd d13, d5, d15, d5
535 __ fmsubd(v14, v12, v5, v10); // fmsub d14, d12, d5, d10
536 __ fnmaddd(v10, v19, v0, v1); // fnmadd d10, d19, d0, d1
537 __ fnmaddd(v20, v2, v2, v0); // fnmadd d20, d2, d2, d0
538
539 // TwoRegFloatOp
540 __ fmovs(v25, v9); // fmov s25, s9
541 __ fabss(v20, v4); // fabs s20, s4
542 __ fnegs(v3, v27); // fneg s3, s27
543 __ fsqrts(v1, v2); // fsqrt s1, s2
544 __ fcvts(v30, v0); // fcvt d30, s0
545 __ fmovd(v12, v4); // fmov d12, d4
546 __ fabsd(v1, v27); // fabs d1, d27
547 __ fnegd(v8, v22); // fneg d8, d22
548 __ fsqrtd(v11, v11); // fsqrt d11, d11
549 __ fcvtd(v22, v28); // fcvt s22, d28
550
551 // FloatConvertOp
552 __ fcvtzsw(r28, v22); // fcvtzs w28, s22
553 __ fcvtzs(r20, v27); // fcvtzs x20, s27
554 __ fcvtzdw(r14, v0); // fcvtzs w14, d0
555 __ fcvtzd(r26, v11); // fcvtzs x26, d11
556 __ scvtfws(v28, r22); // scvtf s28, w22
557 __ scvtfs(v16, r10); // scvtf s16, x10
558 __ scvtfwd(v8, r21); // scvtf d8, w21
559 __ scvtfd(v21, r28); // scvtf d21, x28
560 __ fmovs(r24, v24); // fmov w24, s24
561 __ fmovd(r8, v19); // fmov x8, d19
562 __ fmovs(v8, r12); // fmov s8, w12
563 __ fmovd(v6, r7); // fmov d6, x7
564
565 // TwoRegFloatOp
566 __ fcmps(v30, v16); // fcmp s30, s16
567 __ fcmpd(v25, v11); // fcmp d25, d11
568 __ fcmps(v11, 0.0); // fcmp s11, #0.0
569 __ fcmpd(v11, 0.0); // fcmp d11, #0.0
570
571 // LoadStorePairOp
572 __ stpw(r29, r12, Address(r17, 128)); // stp w29, w12, [x17, #128]
573 __ ldpw(r22, r18, Address(r14, -96)); // ldp w22, w18, [x14, #-96]
574 __ ldpsw(r11, r16, Address(r1, 64)); // ldpsw x11, x16, [x1, #64]
575 __ stp(r0, r11, Address(r26, 112)); // stp x0, x11, [x26, #112]
576 __ ldp(r7, r1, Address(r26, 16)); // ldp x7, x1, [x26, #16]
577
578 // LoadStorePairOp
579 __ stpw(r10, r7, Address(__ pre(r24, 0))); // stp w10, w7, [x24, #0]!
580 __ ldpw(r7, r28, Address(__ pre(r24, -256))); // ldp w7, w28, [x24, #-256]!
581 __ ldpsw(r25, r28, Address(__ pre(r21, -240))); // ldpsw x25, x28, [x21, #-240]!
582 __ stp(r20, r18, Address(__ pre(r14, -16))); // stp x20, x18, [x14, #-16]!
583 __ ldp(r8, r10, Address(__ pre(r13, 80))); // ldp x8, x10, [x13, #80]!
584
585 // LoadStorePairOp
586 __ stpw(r26, r24, Address(__ post(r2, -128))); // stp w26, w24, [x2], #-128
587 __ ldpw(r2, r25, Address(__ post(r21, -192))); // ldp w2, w25, [x21], #-192
588 __ ldpsw(r17, r2, Address(__ post(r21, -144))); // ldpsw x17, x2, [x21], #-144
589 __ stp(r12, r10, Address(__ post(r11, 96))); // stp x12, x10, [x11], #96
590 __ ldp(r24, r6, Address(__ post(r17, -32))); // ldp x24, x6, [x17], #-32
591
592 // LoadStorePairOp
593 __ stnpw(r3, r30, Address(r14, -224)); // stnp w3, w30, [x14, #-224]
594 __ ldnpw(r15, r20, Address(r26, -144)); // ldnp w15, w20, [x26, #-144]
595 __ stnp(r22, r25, Address(r12, -128)); // stnp x22, x25, [x12, #-128]
596 __ ldnp(r27, r22, Address(r17, -176)); // ldnp x27, x22, [x17, #-176]
597
598 // FloatImmediateOp
599 __ fmovd(v0, 2.0); // fmov d0, #2.0
600 __ fmovd(v0, 2.125); // fmov d0, #2.125
601 __ fmovd(v0, 4.0); // fmov d0, #4.0
602 __ fmovd(v0, 4.25); // fmov d0, #4.25
603 __ fmovd(v0, 8.0); // fmov d0, #8.0
604 __ fmovd(v0, 8.5); // fmov d0, #8.5
605 __ fmovd(v0, 16.0); // fmov d0, #16.0
606 __ fmovd(v0, 17.0); // fmov d0, #17.0
607 __ fmovd(v0, 0.125); // fmov d0, #0.125
608 __ fmovd(v0, 0.1328125); // fmov d0, #0.1328125
609 __ fmovd(v0, 0.25); // fmov d0, #0.25
610 __ fmovd(v0, 0.265625); // fmov d0, #0.265625
611 __ fmovd(v0, 0.5); // fmov d0, #0.5
612 __ fmovd(v0, 0.53125); // fmov d0, #0.53125
613 __ fmovd(v0, 1.0); // fmov d0, #1.0
614 __ fmovd(v0, 1.0625); // fmov d0, #1.0625
615 __ fmovd(v0, -2.0); // fmov d0, #-2.0
616 __ fmovd(v0, -2.125); // fmov d0, #-2.125
617 __ fmovd(v0, -4.0); // fmov d0, #-4.0
618 __ fmovd(v0, -4.25); // fmov d0, #-4.25
619 __ fmovd(v0, -8.0); // fmov d0, #-8.0
620 __ fmovd(v0, -8.5); // fmov d0, #-8.5
621 __ fmovd(v0, -16.0); // fmov d0, #-16.0
622 __ fmovd(v0, -17.0); // fmov d0, #-17.0
623 __ fmovd(v0, -0.125); // fmov d0, #-0.125
624 __ fmovd(v0, -0.1328125); // fmov d0, #-0.1328125
625 __ fmovd(v0, -0.25); // fmov d0, #-0.25
626 __ fmovd(v0, -0.265625); // fmov d0, #-0.265625
627 __ fmovd(v0, -0.5); // fmov d0, #-0.5
628 __ fmovd(v0, -0.53125); // fmov d0, #-0.53125
629 __ fmovd(v0, -1.0); // fmov d0, #-1.0
630 __ fmovd(v0, -1.0625); // fmov d0, #-1.0625
631
632 __ bind(forth);
633
634 /*
635 aarch64ops.o: file format elf64-littleaarch64
636
637
638 Disassembly of section .text:
639
640 0000000000000000 <back>:
641 0: 8b0772d3 add x19, x22, x7, lsl #28
642 4: cb4a3570 sub x16, x11, x10, lsr #13
643 8: ab9c09bb adds x27, x13, x28, asr #2
644 c: eb9aa794 subs x20, x28, x26, asr #41
645 10: 0b934e68 add w8, w19, w19, asr #19
646 14: 4b0a3924 sub w4, w9, w10, lsl #14
647 18: 2b1e3568 adds w8, w11, w30, lsl #13
648 1c: 6b132720 subs w0, w25, w19, lsl #9
649 20: 8a154c14 and x20, x0, x21, lsl #19
650 24: aa1445d5 orr x21, x14, x20, lsl #17
651 28: ca01cf99 eor x25, x28, x1, lsl #51
652 2c: ea8b3f6a ands x10, x27, x11, asr #15
653 30: 0a8c5cb9 and w25, w5, w12, asr #23
654 34: 2a4a11d2 orr w18, w14, w10, lsr #4
655 38: 4a855aa4 eor w4, w21, w5, asr #22
656 3c: 6a857415 ands w21, w0, w5, asr #29
657 40: 8aa697da bic x26, x30, x6, asr #37
658 44: aa6d7423 orn x3, x1, x13, lsr #29
659 48: ca29bf80 eon x0, x28, x9, lsl #47
660 4c: ea3cb8bd bics x29, x5, x28, lsl #46
661 50: 0a675249 bic w9, w18, w7, lsr #20
662 54: 2ab961ba orn w26, w13, w25, asr #24
663 58: 4a331899 eon w25, w4, w19, lsl #6
664 5c: 6a646345 bics w5, w26, w4, lsr #24
665 60: 11055267 add w7, w19, #0x154
666 64: 31064408 adds w8, w0, #0x191
667 68: 51028e9d sub w29, w20, #0xa3
668 6c: 710bdee8 subs w8, w23, #0x2f7
669 70: 91082d81 add x1, x12, #0x20b
670 74: b106a962 adds x2, x11, #0x1aa
671 78: d10b33ae sub x14, x29, #0x2cc
672 7c: f10918ab subs x11, x5, #0x246
673 80: 121102d7 and w23, w22, #0x8000
674 84: 3204cd44 orr w4, w10, #0xf0f0f0f0
675 88: 5204cf00 eor w0, w24, #0xf0f0f0f0
676 8c: 72099fb3 ands w19, w29, #0x7f807f80
677 90: 92729545 and x5, x10, #0xfffffffffc000
678 94: b20e37cc orr x12, x30, #0xfffc0000fffc0000
679 98: d27c34be eor x30, x5, #0x3fff0
680 9c: f27e4efa ands x26, x23, #0x3ffffc
681 a0: 14000000 b a0 <back+0xa0>
682 a4: 17ffffd7 b 0 <back>
683 a8: 1400017f b 6a4 <forth>
684 ac: 94000000 bl ac <back+0xac>
685 b0: 97ffffd4 bl 0 <back>
686 b4: 9400017c bl 6a4 <forth>
687 b8: 3400000c cbz w12, b8 <back+0xb8>
688 bc: 34fffa2c cbz w12, 0 <back>
689 c0: 34002f2c cbz w12, 6a4 <forth>
690 c4: 35000014 cbnz w20, c4 <back+0xc4>
691 c8: 35fff9d4 cbnz w20, 0 <back>
692 cc: 35002ed4 cbnz w20, 6a4 <forth>
693 d0: b400000c cbz x12, d0 <back+0xd0>
694 d4: b4fff96c cbz x12, 0 <back>
695 d8: b4002e6c cbz x12, 6a4 <forth>
696 dc: b5000018 cbnz x24, dc <back+0xdc>
697 e0: b5fff918 cbnz x24, 0 <back>
698 e4: b5002e18 cbnz x24, 6a4 <forth>
699 e8: 10000006 adr x6, e8 <back+0xe8>
700 ec: 10fff8a6 adr x6, 0 <back>
701 f0: 10002da6 adr x6, 6a4 <forth>
702 f4: 90000015 adrp x21, 0 <back>
703 f8: 36080001 tbz w1, #1, f8 <back+0xf8>
704 fc: 360ff821 tbz w1, #1, 0 <back>
705 100: 36082d21 tbz w1, #1, 6a4 <forth>
706 104: 37480008 tbnz w8, #9, 104 <back+0x104>
707 108: 374ff7c8 tbnz w8, #9, 0 <back>
708 10c: 37482cc8 tbnz w8, #9, 6a4 <forth>
709 110: 128b50ec movn w12, #0x5a87
710 114: 52a9ff8b movz w11, #0x4ffc, lsl #16
711 118: 7281d095 movk w21, #0xe84
712 11c: 92edfebd movn x29, #0x6ff5, lsl #48
713 120: d28361e3 movz x3, #0x1b0f
714 124: f2a4cc96 movk x22, #0x2664, lsl #16
715 128: 9346590c sbfx x12, x8, #6, #17
716 12c: 33194f33 bfi w19, w25, #7, #20
717 130: 531d3d89 ubfiz w9, w12, #3, #16
718 134: 9350433c sbfx x28, x25, #16, #1
719 138: b34464ac bfxil x12, x5, #4, #22
720 13c: d3462140 ubfx x0, x10, #6, #3
721 140: 139a61a4 extr w4, w13, w26, #24
722 144: 93d87fd7 extr x23, x30, x24, #31
723 148: 54000000 b.eq 148 <back+0x148>
724 14c: 54fff5a0 b.eq 0 <back>
725 150: 54002aa0 b.eq 6a4 <forth>
726 154: 54000001 b.ne 154 <back+0x154>
727 158: 54fff541 b.ne 0 <back>
728 15c: 54002a41 b.ne 6a4 <forth>
729 160: 54000002 b.cs 160 <back+0x160>
730 164: 54fff4e2 b.cs 0 <back>
731 168: 540029e2 b.cs 6a4 <forth>
732 16c: 54000002 b.cs 16c <back+0x16c>
733 170: 54fff482 b.cs 0 <back>
734 174: 54002982 b.cs 6a4 <forth>
735 178: 54000003 b.cc 178 <back+0x178>
736 17c: 54fff423 b.cc 0 <back>
737 180: 54002923 b.cc 6a4 <forth>
738 184: 54000003 b.cc 184 <back+0x184>
739 188: 54fff3c3 b.cc 0 <back>
740 18c: 540028c3 b.cc 6a4 <forth>
741 190: 54000004 b.mi 190 <back+0x190>
742 194: 54fff364 b.mi 0 <back>
743 198: 54002864 b.mi 6a4 <forth>
744 19c: 54000005 b.pl 19c <back+0x19c>
745 1a0: 54fff305 b.pl 0 <back>
746 1a4: 54002805 b.pl 6a4 <forth>
747 1a8: 54000006 b.vs 1a8 <back+0x1a8>
748 1ac: 54fff2a6 b.vs 0 <back>
749 1b0: 540027a6 b.vs 6a4 <forth>
750 1b4: 54000007 b.vc 1b4 <back+0x1b4>
751 1b8: 54fff247 b.vc 0 <back>
752 1bc: 54002747 b.vc 6a4 <forth>
753 1c0: 54000008 b.hi 1c0 <back+0x1c0>
754 1c4: 54fff1e8 b.hi 0 <back>
755 1c8: 540026e8 b.hi 6a4 <forth>
756 1cc: 54000009 b.ls 1cc <back+0x1cc>
757 1d0: 54fff189 b.ls 0 <back>
758 1d4: 54002689 b.ls 6a4 <forth>
759 1d8: 5400000a b.ge 1d8 <back+0x1d8>
760 1dc: 54fff12a b.ge 0 <back>
761 1e0: 5400262a b.ge 6a4 <forth>
762 1e4: 5400000b b.lt 1e4 <back+0x1e4>
763 1e8: 54fff0cb b.lt 0 <back>
764 1ec: 540025cb b.lt 6a4 <forth>
765 1f0: 5400000c b.gt 1f0 <back+0x1f0>
766 1f4: 54fff06c b.gt 0 <back>
767 1f8: 5400256c b.gt 6a4 <forth>
768 1fc: 5400000d b.le 1fc <back+0x1fc>
769 200: 54fff00d b.le 0 <back>
770 204: 5400250d b.le 6a4 <forth>
771 208: 5400000e b.al 208 <back+0x208>
772 20c: 54ffefae b.al 0 <back>
773 210: 540024ae b.al 6a4 <forth>
774 214: 5400000f b.nv 214 <back+0x214>
775 218: 54ffef4f b.nv 0 <back>
776 21c: 5400244f b.nv 6a4 <forth>
777 220: d4063721 svc #0x31b9
778 224: d4035082 hvc #0x1a84
779 228: d400bfe3 smc #0x5ff
780 22c: d4282fc0 brk #0x417e
781 230: d444c320 hlt #0x2619
782 234: d503201f nop
783 238: d69f03e0 eret
784 23c: d6bf03e0 drps
785 240: d5033fdf isb
786 244: d5033f9f dsb sy
787 248: d5033abf dmb ishst
788 24c: d61f0040 br x2
789 250: d63f00a0 blr x5
790 254: c8147c55 stxr w20, x21, [x2]
791 258: c805fcfd stlxr w5, x29, [x7]
792 25c: c85f7e05 ldxr x5, [x16]
793 260: c85fffbb ldaxr x27, [x29]
794 264: c89fffa0 stlr x0, [x29]
795 268: c8dfff95 ldar x21, [x28]
796 26c: 88157cf8 stxr w21, w24, [x7]
797 270: 8815ff9a stlxr w21, w26, [x28]
798 274: 885f7cd5 ldxr w21, [x6]
799 278: 885fffcf ldaxr w15, [x30]
800 27c: 889ffc73 stlr w19, [x3]
801 280: 88dffc56 ldar w22, [x2]
802 284: 48127c0f stxrh w18, w15, [x0]
803 288: 480bff85 stlxrh w11, w5, [x28]
804 28c: 485f7cdd ldxrh w29, [x6]
805 290: 485ffcf2 ldaxrh w18, [x7]
806 294: 489fff99 stlrh w25, [x28]
807 298: 48dffe62 ldarh w2, [x19]
808 29c: 080a7c3e stxrb w10, w30, [x1]
809 2a0: 0814fed5 stlxrb w20, w21, [x22]
810 2a4: 085f7c59 ldxrb w25, [x2]
811 2a8: 085ffcb8 ldaxrb w24, [x5]
812 2ac: 089ffc70 stlrb w16, [x3]
813 2b0: 08dfffb6 ldarb w22, [x29]
814 2b4: c87f0a68 ldxp x8, x2, [x19]
815 2b8: c87fcdc7 ldaxp x7, x19, [x14]
816 2bc: c82870bb stxp w8, x27, x28, [x5]
817 2c0: c825b8c8 stlxp w5, x8, x14, [x6]
818 2c4: 887f12d9 ldxp w25, w4, [x22]
819 2c8: 887fb9ed ldaxp w13, w14, [x15]
820 2cc: 8834215a stxp w20, w26, w8, [x10]
821 2d0: 8837ca52 stlxp w23, w18, w18, [x18]
822 2d4: f806317e str x30, [x11,#99]
823 2d8: b81b3337 str w23, [x25,#-77]
824 2dc: 39000dc2 strb w2, [x14,#3]
825 2e0: 78005149 strh w9, [x10,#5]
826 2e4: f84391f4 ldr x20, [x15,#57]
827 2e8: b85b220c ldr w12, [x16,#-78]
828 2ec: 385fd356 ldrb w22, [x26,#-3]
829 2f0: 785d127e ldrh w30, [x19,#-47]
830 2f4: 389f4149 ldrsb x9, [x10,#-12]
831 2f8: 79801e3c ldrsh x28, [x17,#14]
832 2fc: 79c014a3 ldrsh w3, [x5,#10]
833 300: b89a5231 ldrsw x17, [x17,#-91]
834 304: fc5ef282 ldr d2, [x20,#-17]
835 308: bc5f60f6 ldr s22, [x7,#-10]
836 30c: fc12125e str d30, [x18,#-223]
837 310: bc0152cd str s13, [x22,#21]
838 314: f8190e49 str x9, [x18,#-112]!
839 318: b800befd str w29, [x23,#11]!
840 31c: 381ffd92 strb w18, [x12,#-1]!
841 320: 781e9e90 strh w16, [x20,#-23]!
842 324: f8409fa3 ldr x3, [x29,#9]!
843 328: b8413c79 ldr w25, [x3,#19]!
844 32c: 385fffa1 ldrb w1, [x29,#-1]!
845 330: 785c7fa8 ldrh w8, [x29,#-57]!
846 334: 389f3dc5 ldrsb x5, [x14,#-13]!
847 338: 78801f6a ldrsh x10, [x27,#1]!
848 33c: 78c19d4b ldrsh w11, [x10,#25]!
849 340: b89a4ec4 ldrsw x4, [x22,#-92]!
850 344: fc408eeb ldr d11, [x23,#8]!
851 348: bc436e79 ldr s25, [x19,#54]!
852 34c: fc152ce1 str d1, [x7,#-174]!
853 350: bc036f28 str s8, [x25,#54]!
854 354: f8025565 str x5, [x11],#37
855 358: b80135f8 str w24, [x15],#19
856 35c: 381ff74f strb w15, [x26],#-1
857 360: 781fa652 strh w18, [x18],#-6
858 364: f851a447 ldr x7, [x2],#-230
859 368: b85e557b ldr w27, [x11],#-27
860 36c: 385e7472 ldrb w18, [x3],#-25
861 370: 785e070a ldrh w10, [x24],#-32
862 374: 38804556 ldrsb x22, [x10],#4
863 378: 78819591 ldrsh x17, [x12],#25
864 37c: 78dc24e8 ldrsh w8, [x7],#-62
865 380: b89cd6d7 ldrsw x23, [x22],#-51
866 384: fc430738 ldr d24, [x25],#48
867 388: bc5f6595 ldr s21, [x12],#-10
868 38c: fc1225b2 str d18, [x13],#-222
869 390: bc1d7430 str s16, [x1],#-41
870 394: f82fcac2 str x2, [x22,w15,sxtw]
871 398: b83d6a02 str w2, [x16,x29]
872 39c: 382e5a54 strb w20, [x18,w14,uxtw #0]
873 3a0: 7834fa66 strh w6, [x19,x20,sxtx #1]
874 3a4: f86ecbae ldr x14, [x29,w14,sxtw]
875 3a8: b86cda90 ldr w16, [x20,w12,sxtw #2]
876 3ac: 3860d989 ldrb w9, [x12,w0,sxtw #0]
877 3b0: 78637a2c ldrh w12, [x17,x3,lsl #1]
878 3b4: 38a3fa22 ldrsb x2, [x17,x3,sxtx #0]
879 3b8: 78b15827 ldrsh x7, [x1,w17,uxtw #1]
880 3bc: 78f2d9f9 ldrsh w25, [x15,w18,sxtw #1]
881 3c0: b8ac6ab7 ldrsw x23, [x21,x12]
882 3c4: fc6879a5 ldr d5, [x13,x8,lsl #3]
883 3c8: bc767943 ldr s3, [x10,x22,lsl #2]
884 3cc: fc3bc84e str d14, [x2,w27,sxtw]
885 3d0: bc3968d4 str s20, [x6,x25]
886 3d4: f91fc0fe str x30, [x7,#16256]
887 3d8: b91da50f str w15, [x8,#7588]
888 3dc: 391d280b strb w11, [x0,#1866]
889 3e0: 791d2e23 strh w3, [x17,#3734]
890 3e4: f95bc8e2 ldr x2, [x7,#14224]
891 3e8: b95ce525 ldr w5, [x9,#7396]
892 3ec: 395ae53c ldrb w28, [x9,#1721]
893 3f0: 795c9282 ldrh w2, [x20,#3656]
894 3f4: 399d7dd6 ldrsb x22, [x14,#1887]
895 3f8: 799fe008 ldrsh x8, [x0,#4080]
896 3fc: 79de9bc0 ldrsh w0, [x30,#3916]
897 400: b99aae78 ldrsw x24, [x19,#6828]
898 404: fd597598 ldr d24, [x12,#13032]
899 408: bd5d1d08 ldr s8, [x8,#7452]
900 40c: fd1f3dea str d10, [x15,#15992]
901 410: bd1a227a str s26, [x19,#6688]
902 414: 5800148a ldr x10, 6a4 <forth>
903 418: 18000003 ldr w3, 418 <back+0x418>
904 41c: f88092e0 prfm pldl1keep, [x23,#9]
905 420: d8ffdf00 prfm pldl1keep, 0 <back>
906 424: f8a84860 prfm pldl1keep, [x3,w8,uxtw]
907 428: f99d7560 prfm pldl1keep, [x11,#15080]
908 42c: 1a1c012d adc w13, w9, w28
909 430: 3a1c027b adcs w27, w19, w28
910 434: 5a060253 sbc w19, w18, w6
911 438: 7a03028e sbcs w14, w20, w3
912 43c: 9a0801d0 adc x16, x14, x8
913 440: ba0803a0 adcs x0, x29, x8
914 444: da140308 sbc x8, x24, x20
915 448: fa00038c sbcs x12, x28, x0
916 44c: 0b3010d7 add w23, w6, w16, uxtb #4
917 450: 2b37ab39 adds w25, w25, w23, sxth #2
918 454: cb2466da sub x26, x22, x4, uxtx #1
919 458: 6b33efb1 subs w17, w29, w19, sxtx #3
920 45c: 8b350fcb add x11, x30, w21, uxtb #3
921 460: ab208a70 adds x16, x19, w0, sxtb #2
922 464: cb39e52b sub x11, x9, x25, sxtx #1
923 468: eb2c9291 subs x17, x20, w12, sxtb #4
924 46c: 3a4bd1a3 ccmn w13, w11, #0x3, le
925 470: 7a4c81a2 ccmp w13, w12, #0x2, hi
926 474: ba42106c ccmn x3, x2, #0xc, ne
927 478: fa5560e3 ccmp x7, x21, #0x3, vs
928 47c: 3a4e3844 ccmn w2, #0xe, #0x4, cc
929 480: 7a515a26 ccmp w17, #0x11, #0x6, pl
930 484: ba4c2940 ccmn x10, #0xc, #0x0, cs
931 488: fa52aaae ccmp x21, #0x12, #0xe, ge
932 48c: 1a8cc1b5 csel w21, w13, w12, gt
933 490: 1a8f976a csinc w10, w27, w15, ls
934 494: 5a8981a0 csinv w0, w13, w9, hi
935 498: 5a9a6492 csneg w18, w4, w26, vs
936 49c: 9a8793ac csel x12, x29, x7, ls
937 4a0: 9a9474e6 csinc x6, x7, x20, vc
938 4a4: da83d2b6 csinv x22, x21, x3, le
939 4a8: da9b9593 csneg x19, x12, x27, ls
940 4ac: 5ac00200 rbit w0, w16
941 4b0: 5ac006f1 rev16 w17, w23
942 4b4: 5ac009d1 rev w17, w14
943 4b8: 5ac013d8 clz w24, w30
944 4bc: 5ac016d8 cls w24, w22
945 4c0: dac00223 rbit x3, x17
946 4c4: dac005ac rev16 x12, x13
947 4c8: dac00ac9 rev32 x9, x22
948 4cc: dac00c00 rev x0, x0
949 4d0: dac01205 clz x5, x16
950 4d4: dac016d9 cls x25, x22
951 4d8: 1ac0089d udiv w29, w4, w0
952 4dc: 1add0fa0 sdiv w0, w29, w29
953 4e0: 1ad52225 lsl w5, w17, w21
954 4e4: 1ad22529 lsr w9, w9, w18
955 4e8: 1ac82b61 asr w1, w27, w8
956 4ec: 1acd2e92 ror w18, w20, w13
957 4f0: 9acc0b28 udiv x8, x25, x12
958 4f4: 9adc0ca7 sdiv x7, x5, x28
959 4f8: 9adb2225 lsl x5, x17, x27
960 4fc: 9ad42757 lsr x23, x26, x20
961 500: 9adc291c asr x28, x8, x28
962 504: 9ac42fa3 ror x3, x29, x4
963 508: 1b1a55d1 madd w17, w14, w26, w21
964 50c: 1b0bafc1 msub w1, w30, w11, w11
965 510: 9b067221 madd x1, x17, x6, x28
966 514: 9b1ea0de msub x30, x6, x30, x8
967 518: 9b2e20d5 smaddl x21, w6, w14, x8
968 51c: 9b38cd4a smsubl x10, w10, w24, x19
969 520: 9bae6254 umaddl x20, w18, w14, x24
970 524: 9ba59452 umsubl x18, w2, w5, x5
971 528: 1e2d0a48 fmul s8, s18, s13
972 52c: 1e3c19c2 fdiv s2, s14, s28
973 530: 1e3c298f fadd s15, s12, s28
974 534: 1e213980 fsub s0, s12, s1
975 538: 1e240baf fmul s15, s29, s4
976 53c: 1e77082c fmul d12, d1, d23
977 540: 1e72191b fdiv d27, d8, d18
978 544: 1e6b2a97 fadd d23, d20, d11
979 548: 1e723988 fsub d8, d12, d18
980 54c: 1e770b1a fmul d26, d24, d23
981 550: 1f0d66f5 fmadd s21, s23, s13, s25
982 554: 1f01b956 fmsub s22, s10, s1, s14
983 558: 1f227a8e fnmadd s14, s20, s2, s30
984 55c: 1f365ba7 fnmadd s7, s29, s22, s22
985 560: 1f4f14ad fmadd d13, d5, d15, d5
986 564: 1f45a98e fmsub d14, d12, d5, d10
987 568: 1f60066a fnmadd d10, d19, d0, d1
988 56c: 1f620054 fnmadd d20, d2, d2, d0
989 570: 1e204139 fmov s25, s9
990 574: 1e20c094 fabs s20, s4
991 578: 1e214363 fneg s3, s27
992 57c: 1e21c041 fsqrt s1, s2
993 580: 1e22c01e fcvt d30, s0
994 584: 1e60408c fmov d12, d4
995 588: 1e60c361 fabs d1, d27
996 58c: 1e6142c8 fneg d8, d22
997 590: 1e61c16b fsqrt d11, d11
998 594: 1e624396 fcvt s22, d28
999 598: 1e3802dc fcvtzs w28, s22
1000 59c: 9e380374 fcvtzs x20, s27
1001 5a0: 1e78000e fcvtzs w14, d0
1002 5a4: 9e78017a fcvtzs x26, d11
1003 5a8: 1e2202dc scvtf s28, w22
1004 5ac: 9e220150 scvtf s16, x10
1005 5b0: 1e6202a8 scvtf d8, w21
1006 5b4: 9e620395 scvtf d21, x28
1007 5b8: 1e260318 fmov w24, s24
1008 5bc: 9e660268 fmov x8, d19
1009 5c0: 1e270188 fmov s8, w12
1010 5c4: 9e6700e6 fmov d6, x7
1011 5c8: 1e3023c0 fcmp s30, s16
1012 5cc: 1e6b2320 fcmp d25, d11
1013 5d0: 1e202168 fcmp s11, #0.0
1014 5d4: 1e602168 fcmp d11, #0.0
1015 5d8: 2910323d stp w29, w12, [x17,#128]
1016 5dc: 297449d6 ldp w22, w18, [x14,#-96]
1017 5e0: 6948402b ldpsw x11, x16, [x1,#64]
1018 5e4: a9072f40 stp x0, x11, [x26,#112]
1019 5e8: a9410747 ldp x7, x1, [x26,#16]
1020 5ec: 29801f0a stp w10, w7, [x24,#0]!
1021 5f0: 29e07307 ldp w7, w28, [x24,#-256]!
1022 5f4: 69e272b9 ldpsw x25, x28, [x21,#-240]!
1023 5f8: a9bf49d4 stp x20, x18, [x14,#-16]!
1024 5fc: a9c529a8 ldp x8, x10, [x13,#80]!
1025 600: 28b0605a stp w26, w24, [x2],#-128
1026 604: 28e866a2 ldp w2, w25, [x21],#-192
1027 608: 68ee0ab1 ldpsw x17, x2, [x21],#-144
1028 60c: a886296c stp x12, x10, [x11],#96
1029 610: a8fe1a38 ldp x24, x6, [x17],#-32
1030 614: 282479c3 stnp w3, w30, [x14,#-224]
1031 618: 286e534f ldnp w15, w20, [x26,#-144]
1032 61c: a8386596 stnp x22, x25, [x12,#-128]
1033 620: a8755a3b ldnp x27, x22, [x17,#-176]
1034 624: 1e601000 fmov d0, #2.000000000000000000e+00
1035 628: 1e603000 fmov d0, #2.125000000000000000e+00
1036 62c: 1e621000 fmov d0, #4.000000000000000000e+00
1037 630: 1e623000 fmov d0, #4.250000000000000000e+00
1038 634: 1e641000 fmov d0, #8.000000000000000000e+00
1039 638: 1e643000 fmov d0, #8.500000000000000000e+00
1040 63c: 1e661000 fmov d0, #1.600000000000000000e+01
1041 640: 1e663000 fmov d0, #1.700000000000000000e+01
1042 644: 1e681000 fmov d0, #1.250000000000000000e-01
1043 648: 1e683000 fmov d0, #1.328125000000000000e-01
1044 64c: 1e6a1000 fmov d0, #2.500000000000000000e-01
1045 650: 1e6a3000 fmov d0, #2.656250000000000000e-01
1046 654: 1e6c1000 fmov d0, #5.000000000000000000e-01
1047 658: 1e6c3000 fmov d0, #5.312500000000000000e-01
1048 65c: 1e6e1000 fmov d0, #1.000000000000000000e+00
1049 660: 1e6e3000 fmov d0, #1.062500000000000000e+00
1050 664: 1e701000 fmov d0, #-2.000000000000000000e+00
1051 668: 1e703000 fmov d0, #-2.125000000000000000e+00
1052 66c: 1e721000 fmov d0, #-4.000000000000000000e+00
1053 670: 1e723000 fmov d0, #-4.250000000000000000e+00
1054 674: 1e741000 fmov d0, #-8.000000000000000000e+00
1055 678: 1e743000 fmov d0, #-8.500000000000000000e+00
1056 67c: 1e761000 fmov d0, #-1.600000000000000000e+01
1057 680: 1e763000 fmov d0, #-1.700000000000000000e+01
1058 684: 1e781000 fmov d0, #-1.250000000000000000e-01
1059 688: 1e783000 fmov d0, #-1.328125000000000000e-01
1060 68c: 1e7a1000 fmov d0, #-2.500000000000000000e-01
1061 690: 1e7a3000 fmov d0, #-2.656250000000000000e-01
1062 694: 1e7c1000 fmov d0, #-5.000000000000000000e-01
1063 698: 1e7c3000 fmov d0, #-5.312500000000000000e-01
1064 69c: 1e7e1000 fmov d0, #-1.000000000000000000e+00
1065 6a0: 1e7e3000 fmov d0, #-1.062500000000000000e+00
1066 */
1067
1068 static const unsigned int insns[] =
1069 {
1070 0x8b0772d3, 0xcb4a3570, 0xab9c09bb, 0xeb9aa794,
1071 0x0b934e68, 0x4b0a3924, 0x2b1e3568, 0x6b132720,
1072 0x8a154c14, 0xaa1445d5, 0xca01cf99, 0xea8b3f6a,
1073 0x0a8c5cb9, 0x2a4a11d2, 0x4a855aa4, 0x6a857415,
1074 0x8aa697da, 0xaa6d7423, 0xca29bf80, 0xea3cb8bd,
1075 0x0a675249, 0x2ab961ba, 0x4a331899, 0x6a646345,
1076 0x11055267, 0x31064408, 0x51028e9d, 0x710bdee8,
1077 0x91082d81, 0xb106a962, 0xd10b33ae, 0xf10918ab,
1078 0x121102d7, 0x3204cd44, 0x5204cf00, 0x72099fb3,
1079 0x92729545, 0xb20e37cc, 0xd27c34be, 0xf27e4efa,
1080 0x14000000, 0x17ffffd7, 0x1400017f, 0x94000000,
1081 0x97ffffd4, 0x9400017c, 0x3400000c, 0x34fffa2c,
1082 0x34002f2c, 0x35000014, 0x35fff9d4, 0x35002ed4,
1083 0xb400000c, 0xb4fff96c, 0xb4002e6c, 0xb5000018,
1084 0xb5fff918, 0xb5002e18, 0x10000006, 0x10fff8a6,
1085 0x10002da6, 0x90000015, 0x36080001, 0x360ff821,
1086 0x36082d21, 0x37480008, 0x374ff7c8, 0x37482cc8,
1087 0x128b50ec, 0x52a9ff8b, 0x7281d095, 0x92edfebd,
1088 0xd28361e3, 0xf2a4cc96, 0x9346590c, 0x33194f33,
1089 0x531d3d89, 0x9350433c, 0xb34464ac, 0xd3462140,
1090 0x139a61a4, 0x93d87fd7, 0x54000000, 0x54fff5a0,
1091 0x54002aa0, 0x54000001, 0x54fff541, 0x54002a41,
1092 0x54000002, 0x54fff4e2, 0x540029e2, 0x54000002,
1093 0x54fff482, 0x54002982, 0x54000003, 0x54fff423,
1094 0x54002923, 0x54000003, 0x54fff3c3, 0x540028c3,
1095 0x54000004, 0x54fff364, 0x54002864, 0x54000005,
1096 0x54fff305, 0x54002805, 0x54000006, 0x54fff2a6,
1097 0x540027a6, 0x54000007, 0x54fff247, 0x54002747,
1098 0x54000008, 0x54fff1e8, 0x540026e8, 0x54000009,
1099 0x54fff189, 0x54002689, 0x5400000a, 0x54fff12a,
1100 0x5400262a, 0x5400000b, 0x54fff0cb, 0x540025cb,
1101 0x5400000c, 0x54fff06c, 0x5400256c, 0x5400000d,
1102 0x54fff00d, 0x5400250d, 0x5400000e, 0x54ffefae,
1103 0x540024ae, 0x5400000f, 0x54ffef4f, 0x5400244f,
1104 0xd4063721, 0xd4035082, 0xd400bfe3, 0xd4282fc0,
1105 0xd444c320, 0xd503201f, 0xd69f03e0, 0xd6bf03e0,
1106 0xd5033fdf, 0xd5033f9f, 0xd5033abf, 0xd61f0040,
1107 0xd63f00a0, 0xc8147c55, 0xc805fcfd, 0xc85f7e05,
1108 0xc85fffbb, 0xc89fffa0, 0xc8dfff95, 0x88157cf8,
1109 0x8815ff9a, 0x885f7cd5, 0x885fffcf, 0x889ffc73,
1110 0x88dffc56, 0x48127c0f, 0x480bff85, 0x485f7cdd,
1111 0x485ffcf2, 0x489fff99, 0x48dffe62, 0x080a7c3e,
1112 0x0814fed5, 0x085f7c59, 0x085ffcb8, 0x089ffc70,
1113 0x08dfffb6, 0xc87f0a68, 0xc87fcdc7, 0xc82870bb,
1114 0xc825b8c8, 0x887f12d9, 0x887fb9ed, 0x8834215a,
1115 0x8837ca52, 0xf806317e, 0xb81b3337, 0x39000dc2,
1116 0x78005149, 0xf84391f4, 0xb85b220c, 0x385fd356,
1117 0x785d127e, 0x389f4149, 0x79801e3c, 0x79c014a3,
1118 0xb89a5231, 0xfc5ef282, 0xbc5f60f6, 0xfc12125e,
1119 0xbc0152cd, 0xf8190e49, 0xb800befd, 0x381ffd92,
1120 0x781e9e90, 0xf8409fa3, 0xb8413c79, 0x385fffa1,
1121 0x785c7fa8, 0x389f3dc5, 0x78801f6a, 0x78c19d4b,
1122 0xb89a4ec4, 0xfc408eeb, 0xbc436e79, 0xfc152ce1,
1123 0xbc036f28, 0xf8025565, 0xb80135f8, 0x381ff74f,
1124 0x781fa652, 0xf851a447, 0xb85e557b, 0x385e7472,
1125 0x785e070a, 0x38804556, 0x78819591, 0x78dc24e8,
1126 0xb89cd6d7, 0xfc430738, 0xbc5f6595, 0xfc1225b2,
1127 0xbc1d7430, 0xf82fcac2, 0xb83d6a02, 0x382e5a54,
1128 0x7834fa66, 0xf86ecbae, 0xb86cda90, 0x3860d989,
1129 0x78637a2c, 0x38a3fa22, 0x78b15827, 0x78f2d9f9,
1130 0xb8ac6ab7, 0xfc6879a5, 0xbc767943, 0xfc3bc84e,
1131 0xbc3968d4, 0xf91fc0fe, 0xb91da50f, 0x391d280b,
1132 0x791d2e23, 0xf95bc8e2, 0xb95ce525, 0x395ae53c,
1133 0x795c9282, 0x399d7dd6, 0x799fe008, 0x79de9bc0,
1134 0xb99aae78, 0xfd597598, 0xbd5d1d08, 0xfd1f3dea,
1135 0xbd1a227a, 0x5800148a, 0x18000003, 0xf88092e0,
1136 0xd8ffdf00, 0xf8a84860, 0xf99d7560, 0x1a1c012d,
1137 0x3a1c027b, 0x5a060253, 0x7a03028e, 0x9a0801d0,
1138 0xba0803a0, 0xda140308, 0xfa00038c, 0x0b3010d7,
1139 0x2b37ab39, 0xcb2466da, 0x6b33efb1, 0x8b350fcb,
1140 0xab208a70, 0xcb39e52b, 0xeb2c9291, 0x3a4bd1a3,
1141 0x7a4c81a2, 0xba42106c, 0xfa5560e3, 0x3a4e3844,
1142 0x7a515a26, 0xba4c2940, 0xfa52aaae, 0x1a8cc1b5,
1143 0x1a8f976a, 0x5a8981a0, 0x5a9a6492, 0x9a8793ac,
1144 0x9a9474e6, 0xda83d2b6, 0xda9b9593, 0x5ac00200,
1145 0x5ac006f1, 0x5ac009d1, 0x5ac013d8, 0x5ac016d8,
1146 0xdac00223, 0xdac005ac, 0xdac00ac9, 0xdac00c00,
1147 0xdac01205, 0xdac016d9, 0x1ac0089d, 0x1add0fa0,
1148 0x1ad52225, 0x1ad22529, 0x1ac82b61, 0x1acd2e92,
1149 0x9acc0b28, 0x9adc0ca7, 0x9adb2225, 0x9ad42757,
1150 0x9adc291c, 0x9ac42fa3, 0x1b1a55d1, 0x1b0bafc1,
1151 0x9b067221, 0x9b1ea0de, 0x9b2e20d5, 0x9b38cd4a,
1152 0x9bae6254, 0x9ba59452, 0x1e2d0a48, 0x1e3c19c2,
1153 0x1e3c298f, 0x1e213980, 0x1e240baf, 0x1e77082c,
1154 0x1e72191b, 0x1e6b2a97, 0x1e723988, 0x1e770b1a,
1155 0x1f0d66f5, 0x1f01b956, 0x1f227a8e, 0x1f365ba7,
1156 0x1f4f14ad, 0x1f45a98e, 0x1f60066a, 0x1f620054,
1157 0x1e204139, 0x1e20c094, 0x1e214363, 0x1e21c041,
1158 0x1e22c01e, 0x1e60408c, 0x1e60c361, 0x1e6142c8,
1159 0x1e61c16b, 0x1e624396, 0x1e3802dc, 0x9e380374,
1160 0x1e78000e, 0x9e78017a, 0x1e2202dc, 0x9e220150,
1161 0x1e6202a8, 0x9e620395, 0x1e260318, 0x9e660268,
1162 0x1e270188, 0x9e6700e6, 0x1e3023c0, 0x1e6b2320,
1163 0x1e202168, 0x1e602168, 0x2910323d, 0x297449d6,
1164 0x6948402b, 0xa9072f40, 0xa9410747, 0x29801f0a,
1165 0x29e07307, 0x69e272b9, 0xa9bf49d4, 0xa9c529a8,
1166 0x28b0605a, 0x28e866a2, 0x68ee0ab1, 0xa886296c,
1167 0xa8fe1a38, 0x282479c3, 0x286e534f, 0xa8386596,
1168 0xa8755a3b, 0x1e601000, 0x1e603000, 0x1e621000,
1169 0x1e623000, 0x1e641000, 0x1e643000, 0x1e661000,
1170 0x1e663000, 0x1e681000, 0x1e683000, 0x1e6a1000,
1171 0x1e6a3000, 0x1e6c1000, 0x1e6c3000, 0x1e6e1000,
1172 0x1e6e3000, 0x1e701000, 0x1e703000, 0x1e721000,
1173 0x1e723000, 0x1e741000, 0x1e743000, 0x1e761000,
1174 0x1e763000, 0x1e781000, 0x1e783000, 0x1e7a1000,
1175 0x1e7a3000, 0x1e7c1000, 0x1e7c3000, 0x1e7e1000,
1176 0x1e7e3000,
1177 };
1178 // END Generated code -- do not edit
1179
1180 asm_check((unsigned int *)entry, insns, sizeof insns / sizeof insns[0]);
1181
1182 {
1183 address PC = __ pc();
1184 __ ld1(v0, __ T16B, Address(r16)); // No offset
1185 __ ld1(v0, __ T8H, __ post(r16, 16)); // Post-index
1186 __ ld2(v0, v1, __ T8H, __ post(r24, 16 * 2)); // Post-index
1187 __ ld1(v0, __ T16B, __ post(r16, r17)); // Register post-index
1188 static const unsigned int vector_insns[] = {
1189 0x4c407200, // ld1 {v0.16b}, [x16]
1190 0x4cdf7600, // ld1 {v0.8h}, [x16], #16
1191 0x4cdf8700, // ld2 {v0.8h, v1.8h}, [x24], #32
1192 0x4cd17200, // ld1 {v0.16b}, [x16], x17
1193 };
1194 asm_check((unsigned int *)PC, vector_insns,
1195 sizeof vector_insns / sizeof vector_insns[0]);
1196 }
1197
1198 #endif // ASSERT
1199 }
1200
1201 #undef __
1202
1203 void Assembler::emit_data64(jlong data,
1204 relocInfo::relocType rtype,
1205 int format) {
1206 if (rtype == relocInfo::none) {
1207 emit_int64(data);
1208 } else {
1209 emit_data64(data, Relocation::spec_simple(rtype), format);
1210 }
1211 }
1212
1213 void Assembler::emit_data64(jlong data,
1214 RelocationHolder const& rspec,
1215 int format) {
1216
1217 assert(inst_mark() != NULL, "must be inside InstructionMark");
1218 // Do not use AbstractAssembler::relocate, which is not intended for
1219 // embedded words. Instead, relocate to the enclosing instruction.
1220 code_section()->relocate(inst_mark(), rspec, format);
1221 emit_int64(data);
1222 }
1223
1224 extern "C" {
1225 void das(uint64_t start, int len) {
1226 ResourceMark rm;
1227 len <<= 2;
1228 if (len < 0)
1229 Disassembler::decode((address)start + len, (address)start);
1230 else
1231 Disassembler::decode((address)start, (address)start + len);
1232 }
1233
1234 JNIEXPORT void das1(unsigned long insn) {
1235 das(insn, 1);
1236 }
1237 }
1238
1239 #define gas_assert(ARG1) assert(ARG1, #ARG1)
1240
1241 #define __ as->
1242
1243 void Address::lea(MacroAssembler *as, Register r) const {
1244 Relocation* reloc = _rspec.reloc();
1245 relocInfo::relocType rtype = (relocInfo::relocType) reloc->type();
1246
1247 switch(_mode) {
1248 case base_plus_offset: {
1249 if (_offset == 0 && _base == r) // it's a nop
1250 break;
1251 if (_offset > 0)
1252 __ add(r, _base, _offset);
1253 else
1254 __ sub(r, _base, -_offset);
1255 break;
1256 }
1257 case base_plus_offset_reg: {
1258 __ add(r, _base, _index, _ext.op(), MAX(_ext.shift(), 0));
1259 break;
1260 }
1261 case literal: {
1262 if (rtype == relocInfo::none)
1263 __ mov(r, target());
1264 else
1265 __ movptr(r, (uint64_t)target());
1266 break;
1267 }
1268 default:
1269 ShouldNotReachHere();
1270 }
1271 }
1272
1273 void Assembler::adrp(Register reg1, const Address &dest, unsigned long &byte_offset) {
1274 ShouldNotReachHere();
1275 }
1276
1277 #undef __
1278
1279 #define starti Instruction_aarch64 do_not_use(this); set_current(&do_not_use)
1280
1281 void Assembler::adr(Register Rd, address adr) {
1282 long offset = adr - pc();
1283 int offset_lo = offset & 3;
1284 offset >>= 2;
1285 starti;
1286 f(0, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1287 rf(Rd, 0);
1288 }
1289
1290 void Assembler::_adrp(Register Rd, address adr) {
1291 uint64_t pc_page = (uint64_t)pc() >> 12;
1292 uint64_t adr_page = (uint64_t)adr >> 12;
1293 long offset = adr_page - pc_page;
1294 int offset_lo = offset & 3;
1295 offset >>= 2;
1296 starti;
1297 f(1, 31), f(offset_lo, 30, 29), f(0b10000, 28, 24), sf(offset, 23, 5);
1298 rf(Rd, 0);
1299 }
1300
1301 #undef starti
1302
1303 Address::Address(address target, relocInfo::relocType rtype) : _mode(literal){
1304 _is_lval = false;
1305 _target = target;
1306 switch (rtype) {
1307 case relocInfo::oop_type:
1308 case relocInfo::metadata_type:
1309 // Oops are a special case. Normally they would be their own section
1310 // but in cases like icBuffer they are literals in the code stream that
1311 // we don't have a section for. We use none so that we get a literal address
1312 // which is always patchable.
1313 break;
1314 case relocInfo::external_word_type:
1315 _rspec = external_word_Relocation::spec(target);
1316 break;
1317 case relocInfo::internal_word_type:
1318 _rspec = internal_word_Relocation::spec(target);
1319 break;
1320 case relocInfo::opt_virtual_call_type:
1321 _rspec = opt_virtual_call_Relocation::spec();
1322 break;
1323 case relocInfo::static_call_type:
1324 _rspec = static_call_Relocation::spec();
1325 break;
1326 case relocInfo::runtime_call_type:
1327 _rspec = runtime_call_Relocation::spec();
1328 break;
1329 case relocInfo::poll_type:
1330 case relocInfo::poll_return_type:
1331 _rspec = Relocation::spec_simple(rtype);
1332 break;
1333 case relocInfo::none:
1334 _rspec = RelocationHolder::none;
1335 break;
1336 default:
1337 ShouldNotReachHere();
1338 break;
1339 }
1340 }
1341
1342 void Assembler::b(const Address &dest) {
1343 code_section()->relocate(pc(), dest.rspec());
1344 b(dest.target());
1345 }
1346
1347 void Assembler::bl(const Address &dest) {
1348 code_section()->relocate(pc(), dest.rspec());
1349 bl(dest.target());
1350 }
1351
1352 void Assembler::adr(Register r, const Address &dest) {
1353 code_section()->relocate(pc(), dest.rspec());
1354 adr(r, dest.target());
1355 }
1356
1357 void Assembler::br(Condition cc, Label &L) {
1358 if (L.is_bound()) {
1359 br(cc, target(L));
1360 } else {
1361 L.add_patch_at(code(), locator());
1362 br(cc, pc());
1363 }
1364 }
1365
1366 void Assembler::wrap_label(Label &L,
1367 Assembler::uncond_branch_insn insn) {
1368 if (L.is_bound()) {
1369 (this->*insn)(target(L));
1370 } else {
1371 L.add_patch_at(code(), locator());
1372 (this->*insn)(pc());
1373 }
1374 }
1375
1376 void Assembler::wrap_label(Register r, Label &L,
1377 compare_and_branch_insn insn) {
1378 if (L.is_bound()) {
1379 (this->*insn)(r, target(L));
1380 } else {
1381 L.add_patch_at(code(), locator());
1382 (this->*insn)(r, pc());
1383 }
1384 }
1385
1386 void Assembler::wrap_label(Register r, int bitpos, Label &L,
1387 test_and_branch_insn insn) {
1388 if (L.is_bound()) {
1389 (this->*insn)(r, bitpos, target(L));
1390 } else {
1391 L.add_patch_at(code(), locator());
1392 (this->*insn)(r, bitpos, pc());
1393 }
1394 }
1395
1396 void Assembler::wrap_label(Label &L, prfop op, prefetch_insn insn) {
1397 if (L.is_bound()) {
1398 (this->*insn)(target(L), op);
1399 } else {
1400 L.add_patch_at(code(), locator());
1401 (this->*insn)(pc(), op);
1402 }
1403 }
1404
1405 // An "all-purpose" add/subtract immediate, per ARM documentation:
1406 // A "programmer-friendly" assembler may accept a negative immediate
1407 // between -(2^24 -1) and -1 inclusive, causing it to convert a
1408 // requested ADD operation to a SUB, or vice versa, and then encode
1409 // the absolute value of the immediate as for uimm24.
1410 void Assembler::add_sub_immediate(Register Rd, Register Rn, unsigned uimm, int op,
1411 int negated_op) {
1412 bool sets_flags = op & 1; // this op sets flags
1413 union {
1414 unsigned u;
1415 int imm;
1416 };
1417 u = uimm;
1418 bool shift = false;
1419 bool neg = imm < 0;
1420 if (neg) {
1421 imm = -imm;
1422 op = negated_op;
1423 }
1424 assert(Rd != sp || imm % 16 == 0, "misaligned stack");
1425 if (imm >= (1 << 11)
1426 && ((imm >> 12) << 12 == imm)) {
1427 imm >>= 12;
1428 shift = true;
1429 }
1430 f(op, 31, 29), f(0b10001, 28, 24), f(shift, 23, 22), f(imm, 21, 10);
1431
1432 // add/subtract immediate ops with the S bit set treat r31 as zr;
1433 // with S unset they use sp.
1434 if (sets_flags)
1435 zrf(Rd, 0);
1436 else
1437 srf(Rd, 0);
1438
1439 srf(Rn, 5);
1440 }
1441
1442 bool Assembler::operand_valid_for_add_sub_immediate(long imm) {
1443 bool shift = false;
1444 unsigned long uimm = uabs(imm);
1445 if (uimm < (1 << 12))
1446 return true;
1447 if (uimm < (1 << 24)
1448 && ((uimm >> 12) << 12 == uimm)) {
1449 return true;
1450 }
1451 return false;
1452 }
1453
1454 bool Assembler::operand_valid_for_logical_immediate(bool is32, uint64_t imm) {
1455 return encode_logical_immediate(is32, imm) != 0xffffffff;
1456 }
1457
1458 static uint64_t doubleTo64Bits(jdouble d) {
1459 union {
1460 jdouble double_value;
1461 uint64_t double_bits;
1462 };
1463
1464 double_value = d;
1465 return double_bits;
1466 }
1467
1468 bool Assembler::operand_valid_for_float_immediate(double imm) {
1469 // If imm is all zero bits we can use ZR as the source of a
1470 // floating-point value.
1471 if (doubleTo64Bits(imm) == 0)
1472 return true;
1473
1474 // Otherwise try to encode imm then convert the encoded value back
1475 // and make sure it's the exact same bit pattern.
1476 unsigned result = encoding_for_fp_immediate(imm);
1477 return doubleTo64Bits(imm) == fp_immediate_for_encoding(result, true);
1478 }
1479
1480 int AbstractAssembler::code_fill_byte() {
1481 return 0;
1482 }
1483
1484 // n.b. this is implemented in subclass MacroAssembler
1485 void Assembler::bang_stack_with_offset(int offset) { Unimplemented(); }
1486
1487
1488 // these are the functions provided by the simulator which are used to
1489 // encode and decode logical immediates and floating point immediates
1490 //
1491 // u_int64_t logical_immediate_for_encoding(u_int32_t encoding);
1492 //
1493 // u_int32_t encoding_for_logical_immediate(u_int64_t immediate);
1494 //
1495 // u_int64_t fp_immediate_for_encoding(u_int32_t imm8, int is_dp);
1496 //
1497 // u_int32_t encoding_for_fp_immediate(float immediate);
1498 //
1499 // we currently import these from the simulator librray but the
1500 // definitions will need to be moved to here when we switch to real
1501 // hardware.
1502
1503 // and now the routines called by the assembler which encapsulate the
1504 // above encode and decode functions
1505
1506 uint32_t
1507 asm_util::encode_logical_immediate(bool is32, uint64_t imm)
1508 {
1509 if (is32) {
1510 /* Allow all zeros or all ones in top 32-bits, so that
1511 constant expressions like ~1 are permitted. */
1512 if (imm >> 32 != 0 && imm >> 32 != 0xffffffff)
1513 return 0xffffffff;
1514 /* Replicate the 32 lower bits to the 32 upper bits. */
1515 imm &= 0xffffffff;
1516 imm |= imm << 32;
1517 }
1518
1519 return encoding_for_logical_immediate(imm);
1520 }
1521
1522 unsigned Assembler::pack(double value) {
1523 float val = (float)value;
1524 unsigned result = encoding_for_fp_immediate(val);
1525 guarantee(unpack(result) == value,
1526 "Invalid floating-point immediate operand");
1527 return result;
1528 }
1529
1530 // Packed operands for Floating-point Move (immediate)
1531
1532 static float unpack(unsigned value) {
1533 union {
1534 unsigned ival;
1535 float val;
1536 };
1537 ival = fp_immediate_for_encoding(value, 0);
1538 return val;
1539 }