1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * Copyright (c) 2015, Red Hat Inc. All rights reserved.
4 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
5 *
6 * This code is free software; you can redistribute it and/or modify it
7 * under the terms of the GNU General Public License version 2 only, as
8 * published by the Free Software Foundation.
9 *
10 * This code is distributed in the hope that it will be useful, but WITHOUT
11 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
12 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
13 * version 2 for more details (a copy is included in the LICENSE file that
14 * accompanied this code).
15 *
16 * You should have received a copy of the GNU General Public License version
17 * 2 along with this work; if not, write to the Free Software Foundation,
18 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
19 *
20 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
21 * or visit www.oracle.com if you need additional information or have any
22 * questions.
23 *
24 */
25
26 #include "precompiled.hpp"
27 #include "asm/macroAssembler.hpp"
28 #include "asm/macroAssembler.inline.hpp"
29 #include "memory/resourceArea.hpp"
30 #include "runtime/java.hpp"
31 #include "runtime/stubCodeGenerator.hpp"
32 #include "utilities/macros.hpp"
33 #include "vm_version_aarch64.hpp"
34
35 #include OS_HEADER_INLINE(os)
36
37 #ifndef BUILTIN_SIM
38 #include <sys/auxv.h>
39 #include <asm/hwcap.h>
40 #else
41 #define getauxval(hwcap) 0
42 #endif
43
44 #ifndef HWCAP_AES
45 #define HWCAP_AES (1<<3)
46 #endif
47
48 #ifndef HWCAP_PMULL
49 #define HWCAP_PMULL (1<<4)
50 #endif
51
52 #ifndef HWCAP_SHA1
53 #define HWCAP_SHA1 (1<<5)
54 #endif
55
56 #ifndef HWCAP_SHA2
57 #define HWCAP_SHA2 (1<<6)
58 #endif
59
60 #ifndef HWCAP_CRC32
61 #define HWCAP_CRC32 (1<<7)
62 #endif
63
64 #ifndef HWCAP_ATOMICS
65 #define HWCAP_ATOMICS (1<<8)
66 #endif
67
68 int VM_Version::_cpu;
69 int VM_Version::_model;
70 int VM_Version::_model2;
71 int VM_Version::_variant;
72 int VM_Version::_revision;
73 int VM_Version::_stepping;
74 VM_Version::PsrInfo VM_Version::_psr_info = { 0, };
75
76 static BufferBlob* stub_blob;
77 static const int stub_size = 550;
78
79 extern "C" {
80 typedef void (*getPsrInfo_stub_t)(void*);
81 }
82 static getPsrInfo_stub_t getPsrInfo_stub = NULL;
83
84
85 class VM_Version_StubGenerator: public StubCodeGenerator {
86 public:
87
88 VM_Version_StubGenerator(CodeBuffer *c) : StubCodeGenerator(c) {}
89
90 address generate_getPsrInfo() {
91 StubCodeMark mark(this, "VM_Version", "getPsrInfo_stub");
92 # define __ _masm->
93 address start = __ pc();
94
95 #ifdef BUILTIN_SIM
96 __ c_stub_prolog(1, 0, MacroAssembler::ret_type_void);
97 #endif
98
99 // void getPsrInfo(VM_Version::PsrInfo* psr_info);
100
101 address entry = __ pc();
102
103 __ enter();
104
105 __ get_dczid_el0(rscratch1);
106 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::dczid_el0_offset())));
107
108 __ get_ctr_el0(rscratch1);
109 __ strw(rscratch1, Address(c_rarg0, in_bytes(VM_Version::ctr_el0_offset())));
110
111 __ leave();
112 __ ret(lr);
113
114 # undef __
115
116 return start;
117 }
118 };
119
120
121 void VM_Version::get_processor_features() {
122 _supports_cx8 = true;
123 _supports_atomic_getset4 = true;
124 _supports_atomic_getadd4 = true;
125 _supports_atomic_getset8 = true;
126 _supports_atomic_getadd8 = true;
127
128 getPsrInfo_stub(&_psr_info);
129
130 int dcache_line = VM_Version::dcache_line_size();
131
132 if (FLAG_IS_DEFAULT(AllocatePrefetchDistance))
133 FLAG_SET_DEFAULT(AllocatePrefetchDistance, 3*dcache_line);
134 if (FLAG_IS_DEFAULT(AllocatePrefetchStepSize))
135 FLAG_SET_DEFAULT(AllocatePrefetchStepSize, dcache_line);
136 if (FLAG_IS_DEFAULT(PrefetchScanIntervalInBytes))
137 FLAG_SET_DEFAULT(PrefetchScanIntervalInBytes, 3*dcache_line);
138 if (FLAG_IS_DEFAULT(PrefetchCopyIntervalInBytes))
139 FLAG_SET_DEFAULT(PrefetchCopyIntervalInBytes, 3*dcache_line);
140 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance))
141 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, 3*dcache_line);
142
143 if (PrefetchCopyIntervalInBytes != -1 &&
144 ((PrefetchCopyIntervalInBytes & 7) || (PrefetchCopyIntervalInBytes >= 32768))) {
145 warning("PrefetchCopyIntervalInBytes must be -1, or a multiple of 8 and < 32768");
146 PrefetchCopyIntervalInBytes &= ~7;
147 if (PrefetchCopyIntervalInBytes >= 32768)
148 PrefetchCopyIntervalInBytes = 32760;
149 }
150
151 if (AllocatePrefetchDistance !=-1 && (AllocatePrefetchDistance & 7)) {
152 warning("AllocatePrefetchDistance must be multiple of 8");
153 AllocatePrefetchDistance &= ~7;
154 }
155
156 if (AllocatePrefetchStepSize & 7) {
157 warning("AllocatePrefetchStepSize must be multiple of 8");
158 AllocatePrefetchStepSize &= ~7;
159 }
160
161 if (SoftwarePrefetchHintDistance != -1 &&
162 (SoftwarePrefetchHintDistance & 7)) {
163 warning("SoftwarePrefetchHintDistance must be -1, or a multiple of 8");
164 SoftwarePrefetchHintDistance &= ~7;
165 }
166
167 unsigned long auxv = getauxval(AT_HWCAP);
168
169 char buf[512];
170
171 _features = auxv;
172
173 int cpu_lines = 0;
174 if (FILE *f = fopen("/proc/cpuinfo", "r")) {
175 char buf[128], *p;
176 while (fgets(buf, sizeof (buf), f) != NULL) {
177 if (p = strchr(buf, ':')) {
178 long v = strtol(p+1, NULL, 0);
179 if (strncmp(buf, "CPU implementer", sizeof "CPU implementer" - 1) == 0) {
180 _cpu = v;
181 cpu_lines++;
182 } else if (strncmp(buf, "CPU variant", sizeof "CPU variant" - 1) == 0) {
183 _variant = v;
184 } else if (strncmp(buf, "CPU part", sizeof "CPU part" - 1) == 0) {
185 if (_model != v) _model2 = _model;
186 _model = v;
187 } else if (strncmp(buf, "CPU revision", sizeof "CPU revision" - 1) == 0) {
188 _revision = v;
189 }
190 }
191 }
192 fclose(f);
193 }
194
195 // Enable vendor specific features
196
197 // ThunderX
198 if (_cpu == CPU_CAVIUM && (_model == 0xA1)) {
199 if (_variant == 0) _features |= CPU_DMB_ATOMICS;
200 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
201 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
202 }
203 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
204 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, (_variant > 0));
205 }
206 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
207 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
208 }
209 }
210
211 // ThunderX2
212 if ((_cpu == CPU_CAVIUM && (_model == 0xAF)) ||
213 (_cpu == CPU_BROADCOM && (_model == 0x516))) {
214 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
215 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
216 }
217 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
218 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
219 }
220 }
221
222 // HiSilicon TSV110
223 if (_cpu == CPU_HISILICON && _model == 0xd01) {
224 if (FLAG_IS_DEFAULT(AvoidUnalignedAccesses)) {
225 FLAG_SET_DEFAULT(AvoidUnalignedAccesses, true);
226 }
227 if (FLAG_IS_DEFAULT(UseSIMDForMemoryOps)) {
228 FLAG_SET_DEFAULT(UseSIMDForMemoryOps, true);
229 }
230 }
231
232 // Cortex A53
233 if (_cpu == CPU_ARM && (_model == 0xd03 || _model2 == 0xd03)) {
234 _features |= CPU_A53MAC;
235 if (FLAG_IS_DEFAULT(UseSIMDForArrayEquals)) {
236 FLAG_SET_DEFAULT(UseSIMDForArrayEquals, false);
237 }
238 }
239
240 // Cortex A73
241 if (_cpu == CPU_ARM && (_model == 0xd09 || _model2 == 0xd09)) {
242 if (FLAG_IS_DEFAULT(SoftwarePrefetchHintDistance)) {
243 FLAG_SET_DEFAULT(SoftwarePrefetchHintDistance, -1);
244 }
245 // A73 is faster with short-and-easy-for-speculative-execution-loop
246 if (FLAG_IS_DEFAULT(UseSimpleArrayEquals)) {
247 FLAG_SET_DEFAULT(UseSimpleArrayEquals, true);
248 }
249 }
250
251 if (_cpu == CPU_ARM && (_model == 0xd07 || _model2 == 0xd07)) _features |= CPU_STXR_PREFETCH;
252 // If an olde style /proc/cpuinfo (cpu_lines == 1) then if _model is an A57 (0xd07)
253 // we assume the worst and assume we could be on a big little system and have
254 // undisclosed A53 cores which we could be swapped to at any stage
255 if (_cpu == CPU_ARM && cpu_lines == 1 && _model == 0xd07) _features |= CPU_A53MAC;
256
257 sprintf(buf, "0x%02x:0x%x:0x%03x:%d", _cpu, _variant, _model, _revision);
258 if (_model2) sprintf(buf+strlen(buf), "(0x%03x)", _model2);
259 if (auxv & HWCAP_ASIMD) strcat(buf, ", simd");
260 if (auxv & HWCAP_CRC32) strcat(buf, ", crc");
261 if (auxv & HWCAP_AES) strcat(buf, ", aes");
262 if (auxv & HWCAP_SHA1) strcat(buf, ", sha1");
263 if (auxv & HWCAP_SHA2) strcat(buf, ", sha256");
264 if (auxv & HWCAP_ATOMICS) strcat(buf, ", lse");
265
266 _features_string = os::strdup(buf);
267
268 if (FLAG_IS_DEFAULT(UseCRC32)) {
269 UseCRC32 = (auxv & HWCAP_CRC32) != 0;
270 }
271
272 if (UseCRC32 && (auxv & HWCAP_CRC32) == 0) {
273 warning("UseCRC32 specified, but not supported on this CPU");
274 FLAG_SET_DEFAULT(UseCRC32, false);
275 }
276
277 if (FLAG_IS_DEFAULT(UseAdler32Intrinsics)) {
278 FLAG_SET_DEFAULT(UseAdler32Intrinsics, true);
279 }
280
281 if (UseVectorizedMismatchIntrinsic) {
282 warning("UseVectorizedMismatchIntrinsic specified, but not available on this CPU.");
283 FLAG_SET_DEFAULT(UseVectorizedMismatchIntrinsic, false);
284 }
285
286 if (auxv & HWCAP_ATOMICS) {
287 if (FLAG_IS_DEFAULT(UseLSE))
288 FLAG_SET_DEFAULT(UseLSE, true);
289 } else {
290 if (UseLSE) {
291 warning("UseLSE specified, but not supported on this CPU");
292 FLAG_SET_DEFAULT(UseLSE, false);
293 }
294 }
295
296 if (auxv & HWCAP_AES) {
297 UseAES = UseAES || FLAG_IS_DEFAULT(UseAES);
298 UseAESIntrinsics =
299 UseAESIntrinsics || (UseAES && FLAG_IS_DEFAULT(UseAESIntrinsics));
300 if (UseAESIntrinsics && !UseAES) {
301 warning("UseAESIntrinsics enabled, but UseAES not, enabling");
302 UseAES = true;
303 }
304 } else {
305 if (UseAES) {
306 warning("UseAES specified, but not supported on this CPU");
307 FLAG_SET_DEFAULT(UseAES, false);
308 }
309 if (UseAESIntrinsics) {
310 warning("UseAESIntrinsics specified, but not supported on this CPU");
311 FLAG_SET_DEFAULT(UseAESIntrinsics, false);
312 }
313 }
314
315 if (UseAESCTRIntrinsics) {
316 warning("AES/CTR intrinsics are not available on this CPU");
317 FLAG_SET_DEFAULT(UseAESCTRIntrinsics, false);
318 }
319
320 if (FLAG_IS_DEFAULT(UseCRC32Intrinsics)) {
321 UseCRC32Intrinsics = true;
322 }
323
324 if (auxv & HWCAP_CRC32) {
325 if (FLAG_IS_DEFAULT(UseCRC32CIntrinsics)) {
326 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, true);
327 }
328 } else if (UseCRC32CIntrinsics) {
329 warning("CRC32C is not available on the CPU");
330 FLAG_SET_DEFAULT(UseCRC32CIntrinsics, false);
331 }
332
333 if (FLAG_IS_DEFAULT(UseFMA)) {
334 FLAG_SET_DEFAULT(UseFMA, true);
335 }
336
337 if (auxv & (HWCAP_SHA1 | HWCAP_SHA2)) {
338 if (FLAG_IS_DEFAULT(UseSHA)) {
339 FLAG_SET_DEFAULT(UseSHA, true);
340 }
341 } else if (UseSHA) {
342 warning("SHA instructions are not available on this CPU");
343 FLAG_SET_DEFAULT(UseSHA, false);
344 }
345
346 if (UseSHA && (auxv & HWCAP_SHA1)) {
347 if (FLAG_IS_DEFAULT(UseSHA1Intrinsics)) {
348 FLAG_SET_DEFAULT(UseSHA1Intrinsics, true);
349 }
350 } else if (UseSHA1Intrinsics) {
351 warning("Intrinsics for SHA-1 crypto hash functions not available on this CPU.");
352 FLAG_SET_DEFAULT(UseSHA1Intrinsics, false);
353 }
354
355 if (UseSHA && (auxv & HWCAP_SHA2)) {
356 if (FLAG_IS_DEFAULT(UseSHA256Intrinsics)) {
357 FLAG_SET_DEFAULT(UseSHA256Intrinsics, true);
358 }
359 } else if (UseSHA256Intrinsics) {
360 warning("Intrinsics for SHA-224 and SHA-256 crypto hash functions not available on this CPU.");
361 FLAG_SET_DEFAULT(UseSHA256Intrinsics, false);
362 }
363
364 if (UseSHA512Intrinsics) {
365 warning("Intrinsics for SHA-384 and SHA-512 crypto hash functions not available on this CPU.");
366 FLAG_SET_DEFAULT(UseSHA512Intrinsics, false);
367 }
368
369 if (!(UseSHA1Intrinsics || UseSHA256Intrinsics || UseSHA512Intrinsics)) {
370 FLAG_SET_DEFAULT(UseSHA, false);
371 }
372
373 if (auxv & HWCAP_PMULL) {
374 if (FLAG_IS_DEFAULT(UseGHASHIntrinsics)) {
375 FLAG_SET_DEFAULT(UseGHASHIntrinsics, true);
376 }
377 } else if (UseGHASHIntrinsics) {
378 warning("GHASH intrinsics are not available on this CPU");
379 FLAG_SET_DEFAULT(UseGHASHIntrinsics, false);
380 }
381
382 if (is_zva_enabled()) {
383 if (FLAG_IS_DEFAULT(UseBlockZeroing)) {
384 FLAG_SET_DEFAULT(UseBlockZeroing, true);
385 }
386 if (FLAG_IS_DEFAULT(BlockZeroingLowLimit)) {
387 FLAG_SET_DEFAULT(BlockZeroingLowLimit, 4 * VM_Version::zva_length());
388 }
389 } else if (UseBlockZeroing) {
390 warning("DC ZVA is not available on this CPU");
391 FLAG_SET_DEFAULT(UseBlockZeroing, false);
392 }
393
394 // This machine allows unaligned memory accesses
395 if (FLAG_IS_DEFAULT(UseUnalignedAccesses)) {
396 FLAG_SET_DEFAULT(UseUnalignedAccesses, true);
397 }
398
399 if (FLAG_IS_DEFAULT(UseBarriersForVolatile)) {
400 UseBarriersForVolatile = (_features & CPU_DMB_ATOMICS) != 0;
401 }
402
403 if (FLAG_IS_DEFAULT(UsePopCountInstruction)) {
404 UsePopCountInstruction = true;
405 }
406
407 #ifdef COMPILER2
408 if (FLAG_IS_DEFAULT(UseMultiplyToLenIntrinsic)) {
409 UseMultiplyToLenIntrinsic = true;
410 }
411
412 if (FLAG_IS_DEFAULT(UseSquareToLenIntrinsic)) {
413 UseSquareToLenIntrinsic = true;
414 }
415
416 if (FLAG_IS_DEFAULT(UseMulAddIntrinsic)) {
417 UseMulAddIntrinsic = true;
418 }
419
420 if (FLAG_IS_DEFAULT(UseMontgomeryMultiplyIntrinsic)) {
421 UseMontgomeryMultiplyIntrinsic = true;
422 }
423 if (FLAG_IS_DEFAULT(UseMontgomerySquareIntrinsic)) {
424 UseMontgomerySquareIntrinsic = true;
425 }
426
427 if (FLAG_IS_DEFAULT(OptoScheduling)) {
428 OptoScheduling = true;
429 }
430 #endif
431 }
432
433 void VM_Version::initialize() {
434 ResourceMark rm;
435
436 stub_blob = BufferBlob::create("getPsrInfo_stub", stub_size);
437 if (stub_blob == NULL) {
438 vm_exit_during_initialization("Unable to allocate getPsrInfo_stub");
439 }
440
441 CodeBuffer c(stub_blob);
442 VM_Version_StubGenerator g(&c);
443 getPsrInfo_stub = CAST_TO_FN_PTR(getPsrInfo_stub_t,
444 g.generate_getPsrInfo());
445
446 get_processor_features();
447
448 UNSUPPORTED_OPTION(CriticalJNINatives);
449 }