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src/hotspot/cpu/x86/assembler_x86.hpp
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*** 182,193 ****
--- 182,195 ----
}
private:
Register _base;
Register _index;
+ XMMRegister _xmmindex;
ScaleFactor _scale;
int _disp;
+ bool _isxmmindex;
RelocationHolder _rspec;
// Easily misused constructors make them private
// %%% can we make these go away?
NOT_LP64(Address(address loc, RelocationHolder spec);)
*** 199,241 ****
int disp() { return _disp; }
// creation
Address()
: _base(noreg),
_index(noreg),
_scale(no_scale),
! _disp(0) {
}
// No default displacement otherwise Register can be implicitly
// converted to 0(Register) which is quite a different animal.
Address(Register base, int disp)
: _base(base),
_index(noreg),
_scale(no_scale),
! _disp(disp) {
}
Address(Register base, Register index, ScaleFactor scale, int disp = 0)
: _base (base),
_index(index),
_scale(scale),
! _disp (disp) {
assert(!index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
: _base (base),
_index(index.register_or_noreg()),
_scale(scale),
! _disp (disp + (index.constant_or_zero() * scale_size(scale))) {
if (!index.is_register()) scale = Address::no_scale;
assert(!_index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
Address plus_disp(int disp) const {
Address a = (*this);
a._disp += disp;
return a;
}
--- 201,262 ----
int disp() { return _disp; }
// creation
Address()
: _base(noreg),
_index(noreg),
+ _xmmindex(xnoreg),
_scale(no_scale),
! _disp(0),
! _isxmmindex(false){
}
// No default displacement otherwise Register can be implicitly
// converted to 0(Register) which is quite a different animal.
Address(Register base, int disp)
: _base(base),
_index(noreg),
+ _xmmindex(xnoreg),
_scale(no_scale),
! _disp(disp),
! _isxmmindex(false){
}
Address(Register base, Register index, ScaleFactor scale, int disp = 0)
: _base (base),
_index(index),
+ _xmmindex(xnoreg),
_scale(scale),
! _disp (disp),
! _isxmmindex(false) {
assert(!index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
Address(Register base, RegisterOrConstant index, ScaleFactor scale = times_1, int disp = 0)
: _base (base),
_index(index.register_or_noreg()),
+ _xmmindex(xnoreg),
_scale(scale),
! _disp (disp + (index.constant_or_zero() * scale_size(scale))),
! _isxmmindex(false){
if (!index.is_register()) scale = Address::no_scale;
assert(!_index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
+ Address(Register base, XMMRegister index, ScaleFactor scale, int disp = 0)
+ : _base (base),
+ _index(noreg),
+ _xmmindex(index),
+ _scale(scale),
+ _disp(disp),
+ _isxmmindex(true) {
+ assert(!index->is_valid() == (scale == Address::no_scale),
+ "inconsistent address");
+ }
+
Address plus_disp(int disp) const {
Address a = (*this);
a._disp += disp;
return a;
}
*** 267,294 ****
#ifdef ASSERT
Address(Register base, ByteSize disp)
: _base(base),
_index(noreg),
_scale(no_scale),
! _disp(in_bytes(disp)) {
}
Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
: _base(base),
_index(index),
_scale(scale),
! _disp(in_bytes(disp)) {
assert(!index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
-
Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
: _base (base),
_index(index.register_or_noreg()),
_scale(scale),
! _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))) {
if (!index.is_register()) scale = Address::no_scale;
assert(!_index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
--- 288,320 ----
#ifdef ASSERT
Address(Register base, ByteSize disp)
: _base(base),
_index(noreg),
+ _xmmindex(xnoreg),
_scale(no_scale),
! _disp(in_bytes(disp)),
! _isxmmindex(false){
}
Address(Register base, Register index, ScaleFactor scale, ByteSize disp)
: _base(base),
_index(index),
+ _xmmindex(xnoreg),
_scale(scale),
! _disp(in_bytes(disp)),
! _isxmmindex(false){
assert(!index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
Address(Register base, RegisterOrConstant index, ScaleFactor scale, ByteSize disp)
: _base (base),
_index(index.register_or_noreg()),
+ _xmmindex(xnoreg),
_scale(scale),
! _disp (in_bytes(disp) + (index.constant_or_zero() * scale_size(scale))),
! _isxmmindex(false) {
if (!index.is_register()) scale = Address::no_scale;
assert(!_index->is_valid() == (scale == Address::no_scale),
"inconsistent address");
}
*** 296,307 ****
--- 322,335 ----
// accessors
bool uses(Register reg) const { return _base == reg || _index == reg; }
Register base() const { return _base; }
Register index() const { return _index; }
+ XMMRegister xmmindex() const { return _xmmindex; }
ScaleFactor scale() const { return _scale; }
int disp() const { return _disp; }
+ bool isxmmindex() const { return _isxmmindex; }
// Convert the raw encoding form into the form expected by the constructor for
// Address. An index of 4 (rsp) corresponds to having no index, so convert
// that to noreg for the Address constructor.
static Address make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc);
*** 315,324 ****
--- 343,356 ----
bool index_needs_rex() const {
return _index != noreg &&_index->encoding() >= 8;
}
+ bool xmmindex_needs_rex() const {
+ return _xmmindex != xnoreg && _xmmindex->encoding() >= 8;
+ }
+
relocInfo::relocType reloc() const { return _rspec.type(); }
friend class Assembler;
friend class MacroAssembler;
friend class LIR_Assembler; // base/index/scale/disp
*** 681,690 ****
--- 713,726 ----
Register base, Register index, Address::ScaleFactor scale,
int disp,
RelocationHolder const& rspec,
int rip_relative_correction = 0);
+ void emit_operand(XMMRegister reg, Register base, XMMRegister index,
+ Address::ScaleFactor scale,
+ int disp, RelocationHolder const& rspec);
+
void emit_operand(Register reg, Address adr, int rip_relative_correction = 0);
// operands that only take the original 32bit registers
void emit_operand32(Register reg, Address adr);
*** 1549,1558 ****
--- 1585,1595 ----
// Pemutation of 64bit words
void vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len);
void vpermq(XMMRegister dst, XMMRegister src, int imm8);
void vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
void vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8);
+ void evpermi2q(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void pause();
// Undefined Instruction
void ud2();
*** 1615,1629 ****
--- 1652,1671 ----
// SSE4.1 packed move
void pmovzxbw(XMMRegister dst, XMMRegister src);
void pmovzxbw(XMMRegister dst, Address src);
void vpmovzxbw( XMMRegister dst, Address src, int vector_len);
+ void vpmovzxbw(XMMRegister dst, XMMRegister src, int vector_len);
void evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len);
void evpmovwb(Address dst, XMMRegister src, int vector_len);
void evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len);
+ void vpmovzxwd(XMMRegister dst, XMMRegister src, int vector_len);
+
+ void evpmovdb(Address dst, XMMRegister src, int vector_len);
+
#ifndef _LP64 // no 32bit push/pop on amd64
void popl(Address dst);
#endif
#ifdef _LP64
*** 2019,2028 ****
--- 2061,2072 ----
void vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len);
void vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
void vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len);
+ void evpsrlvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
+ void evpsllvw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
// Arithmetic shift right packed integers (only shorts and ints, no instructions for longs)
void psraw(XMMRegister dst, int shift);
void psrad(XMMRegister dst, int shift);
void psraw(XMMRegister dst, XMMRegister shift);
*** 2034,2051 ****
--- 2078,2097 ----
// And packed integers
void pand(XMMRegister dst, XMMRegister src);
void vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
+ void vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
// Andn packed integers
void pandn(XMMRegister dst, XMMRegister src);
// Or packed integers
void por(XMMRegister dst, XMMRegister src);
void vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
+ void vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
// Xor packed integers
void pxor(XMMRegister dst, XMMRegister src);
void vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len);
void vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len);
*** 2109,2118 ****
--- 2155,2166 ----
void evpbroadcastb(XMMRegister dst, Register src, int vector_len);
void evpbroadcastw(XMMRegister dst, Register src, int vector_len);
void evpbroadcastd(XMMRegister dst, Register src, int vector_len);
void evpbroadcastq(XMMRegister dst, Register src, int vector_len);
+ void evpgatherdd(XMMRegister dst, KRegister k1, Address src, int vector_len);
+
// Carry-Less Multiplication Quadword
void pclmulqdq(XMMRegister dst, XMMRegister src, int mask);
void vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask);
void evpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask, int vector_len);
// AVX instruction which is used to clear upper 128 bits of YMM registers and
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