1 /*
2 * Copyright (c) 1997, 2018, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "precompiled.hpp"
26 #include "asm/assembler.hpp"
27 #include "asm/assembler.inline.hpp"
28 #include "gc/shared/cardTableBarrierSet.hpp"
29 #include "gc/shared/collectedHeap.inline.hpp"
30 #include "interpreter/interpreter.hpp"
31 #include "memory/resourceArea.hpp"
32 #include "prims/methodHandles.hpp"
33 #include "runtime/biasedLocking.hpp"
34 #include "runtime/objectMonitor.hpp"
35 #include "runtime/os.hpp"
36 #include "runtime/sharedRuntime.hpp"
37 #include "runtime/stubRoutines.hpp"
38 #include "utilities/macros.hpp"
39 #if INCLUDE_ALL_GCS
40 #include "gc/g1/g1BarrierSet.hpp"
41 #include "gc/g1/g1CollectedHeap.inline.hpp"
42 #include "gc/g1/heapRegion.hpp"
43 #endif // INCLUDE_ALL_GCS
44
45 #ifdef PRODUCT
46 #define BLOCK_COMMENT(str) /* nothing */
47 #define STOP(error) stop(error)
48 #else
49 #define BLOCK_COMMENT(str) block_comment(str)
50 #define STOP(error) block_comment(error); stop(error)
51 #endif
52
53 #define BIND(label) bind(label); BLOCK_COMMENT(#label ":")
54 // Implementation of AddressLiteral
55
56 // A 2-D table for managing compressed displacement(disp8) on EVEX enabled platforms.
57 unsigned char tuple_table[Assembler::EVEX_ETUP + 1][Assembler::AVX_512bit + 1] = {
58 // -----------------Table 4.5 -------------------- //
59 16, 32, 64, // EVEX_FV(0)
60 4, 4, 4, // EVEX_FV(1) - with Evex.b
61 16, 32, 64, // EVEX_FV(2) - with Evex.w
62 8, 8, 8, // EVEX_FV(3) - with Evex.w and Evex.b
63 8, 16, 32, // EVEX_HV(0)
64 4, 4, 4, // EVEX_HV(1) - with Evex.b
65 // -----------------Table 4.6 -------------------- //
66 16, 32, 64, // EVEX_FVM(0)
67 1, 1, 1, // EVEX_T1S(0)
68 2, 2, 2, // EVEX_T1S(1)
69 4, 4, 4, // EVEX_T1S(2)
70 8, 8, 8, // EVEX_T1S(3)
71 4, 4, 4, // EVEX_T1F(0)
72 8, 8, 8, // EVEX_T1F(1)
73 8, 8, 8, // EVEX_T2(0)
74 0, 16, 16, // EVEX_T2(1)
75 0, 16, 16, // EVEX_T4(0)
76 0, 0, 32, // EVEX_T4(1)
77 0, 0, 32, // EVEX_T8(0)
78 8, 16, 32, // EVEX_HVM(0)
79 4, 8, 16, // EVEX_QVM(0)
80 2, 4, 8, // EVEX_OVM(0)
81 16, 16, 16, // EVEX_M128(0)
82 8, 32, 64, // EVEX_DUP(0)
83 0, 0, 0 // EVEX_NTUP
84 };
85
86 AddressLiteral::AddressLiteral(address target, relocInfo::relocType rtype) {
87 _is_lval = false;
88 _target = target;
89 switch (rtype) {
90 case relocInfo::oop_type:
91 case relocInfo::metadata_type:
92 // Oops are a special case. Normally they would be their own section
93 // but in cases like icBuffer they are literals in the code stream that
94 // we don't have a section for. We use none so that we get a literal address
95 // which is always patchable.
96 break;
97 case relocInfo::external_word_type:
98 _rspec = external_word_Relocation::spec(target);
99 break;
100 case relocInfo::internal_word_type:
101 _rspec = internal_word_Relocation::spec(target);
102 break;
103 case relocInfo::opt_virtual_call_type:
104 _rspec = opt_virtual_call_Relocation::spec();
105 break;
106 case relocInfo::static_call_type:
107 _rspec = static_call_Relocation::spec();
108 break;
109 case relocInfo::runtime_call_type:
110 _rspec = runtime_call_Relocation::spec();
111 break;
112 case relocInfo::poll_type:
113 case relocInfo::poll_return_type:
114 _rspec = Relocation::spec_simple(rtype);
115 break;
116 case relocInfo::none:
117 break;
118 default:
119 ShouldNotReachHere();
120 break;
121 }
122 }
123
124 // Implementation of Address
125
126 #ifdef _LP64
127
128 Address Address::make_array(ArrayAddress adr) {
129 // Not implementable on 64bit machines
130 // Should have been handled higher up the call chain.
131 ShouldNotReachHere();
132 return Address();
133 }
134
135 // exceedingly dangerous constructor
136 Address::Address(int disp, address loc, relocInfo::relocType rtype) {
137 _base = noreg;
138 _index = noreg;
139 _scale = no_scale;
140 _disp = disp;
141 switch (rtype) {
142 case relocInfo::external_word_type:
143 _rspec = external_word_Relocation::spec(loc);
144 break;
145 case relocInfo::internal_word_type:
146 _rspec = internal_word_Relocation::spec(loc);
147 break;
148 case relocInfo::runtime_call_type:
149 // HMM
150 _rspec = runtime_call_Relocation::spec();
151 break;
152 case relocInfo::poll_type:
153 case relocInfo::poll_return_type:
154 _rspec = Relocation::spec_simple(rtype);
155 break;
156 case relocInfo::none:
157 break;
158 default:
159 ShouldNotReachHere();
160 }
161 }
162 #else // LP64
163
164 Address Address::make_array(ArrayAddress adr) {
165 AddressLiteral base = adr.base();
166 Address index = adr.index();
167 assert(index._disp == 0, "must not have disp"); // maybe it can?
168 Address array(index._base, index._index, index._scale, (intptr_t) base.target());
169 array._rspec = base._rspec;
170 return array;
171 }
172
173 // exceedingly dangerous constructor
174 Address::Address(address loc, RelocationHolder spec) {
175 _base = noreg;
176 _index = noreg;
177 _scale = no_scale;
178 _disp = (intptr_t) loc;
179 _rspec = spec;
180 }
181
182 #endif // _LP64
183
184
185
186 // Convert the raw encoding form into the form expected by the constructor for
187 // Address. An index of 4 (rsp) corresponds to having no index, so convert
188 // that to noreg for the Address constructor.
189 Address Address::make_raw(int base, int index, int scale, int disp, relocInfo::relocType disp_reloc) {
190 RelocationHolder rspec;
191 if (disp_reloc != relocInfo::none) {
192 rspec = Relocation::spec_simple(disp_reloc);
193 }
194 bool valid_index = index != rsp->encoding();
195 if (valid_index) {
196 Address madr(as_Register(base), as_Register(index), (Address::ScaleFactor)scale, in_ByteSize(disp));
197 madr._rspec = rspec;
198 return madr;
199 } else {
200 Address madr(as_Register(base), noreg, Address::no_scale, in_ByteSize(disp));
201 madr._rspec = rspec;
202 return madr;
203 }
204 }
205
206 // Implementation of Assembler
207
208 int AbstractAssembler::code_fill_byte() {
209 return (u_char)'\xF4'; // hlt
210 }
211
212 // make this go away someday
213 void Assembler::emit_data(jint data, relocInfo::relocType rtype, int format) {
214 if (rtype == relocInfo::none)
215 emit_int32(data);
216 else
217 emit_data(data, Relocation::spec_simple(rtype), format);
218 }
219
220 void Assembler::emit_data(jint data, RelocationHolder const& rspec, int format) {
221 assert(imm_operand == 0, "default format must be immediate in this file");
222 assert(inst_mark() != NULL, "must be inside InstructionMark");
223 if (rspec.type() != relocInfo::none) {
224 #ifdef ASSERT
225 check_relocation(rspec, format);
226 #endif
227 // Do not use AbstractAssembler::relocate, which is not intended for
228 // embedded words. Instead, relocate to the enclosing instruction.
229
230 // hack. call32 is too wide for mask so use disp32
231 if (format == call32_operand)
232 code_section()->relocate(inst_mark(), rspec, disp32_operand);
233 else
234 code_section()->relocate(inst_mark(), rspec, format);
235 }
236 emit_int32(data);
237 }
238
239 static int encode(Register r) {
240 int enc = r->encoding();
241 if (enc >= 8) {
242 enc -= 8;
243 }
244 return enc;
245 }
246
247 void Assembler::emit_arith_b(int op1, int op2, Register dst, int imm8) {
248 assert(dst->has_byte_register(), "must have byte register");
249 assert(isByte(op1) && isByte(op2), "wrong opcode");
250 assert(isByte(imm8), "not a byte");
251 assert((op1 & 0x01) == 0, "should be 8bit operation");
252 emit_int8(op1);
253 emit_int8(op2 | encode(dst));
254 emit_int8(imm8);
255 }
256
257
258 void Assembler::emit_arith(int op1, int op2, Register dst, int32_t imm32) {
259 assert(isByte(op1) && isByte(op2), "wrong opcode");
260 assert((op1 & 0x01) == 1, "should be 32bit operation");
261 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
262 if (is8bit(imm32)) {
263 emit_int8(op1 | 0x02); // set sign bit
264 emit_int8(op2 | encode(dst));
265 emit_int8(imm32 & 0xFF);
266 } else {
267 emit_int8(op1);
268 emit_int8(op2 | encode(dst));
269 emit_int32(imm32);
270 }
271 }
272
273 // Force generation of a 4 byte immediate value even if it fits into 8bit
274 void Assembler::emit_arith_imm32(int op1, int op2, Register dst, int32_t imm32) {
275 assert(isByte(op1) && isByte(op2), "wrong opcode");
276 assert((op1 & 0x01) == 1, "should be 32bit operation");
277 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
278 emit_int8(op1);
279 emit_int8(op2 | encode(dst));
280 emit_int32(imm32);
281 }
282
283 // immediate-to-memory forms
284 void Assembler::emit_arith_operand(int op1, Register rm, Address adr, int32_t imm32) {
285 assert((op1 & 0x01) == 1, "should be 32bit operation");
286 assert((op1 & 0x02) == 0, "sign-extension bit should not be set");
287 if (is8bit(imm32)) {
288 emit_int8(op1 | 0x02); // set sign bit
289 emit_operand(rm, adr, 1);
290 emit_int8(imm32 & 0xFF);
291 } else {
292 emit_int8(op1);
293 emit_operand(rm, adr, 4);
294 emit_int32(imm32);
295 }
296 }
297
298
299 void Assembler::emit_arith(int op1, int op2, Register dst, Register src) {
300 assert(isByte(op1) && isByte(op2), "wrong opcode");
301 emit_int8(op1);
302 emit_int8(op2 | encode(dst) << 3 | encode(src));
303 }
304
305
306 bool Assembler::query_compressed_disp_byte(int disp, bool is_evex_inst, int vector_len,
307 int cur_tuple_type, int in_size_in_bits, int cur_encoding) {
308 int mod_idx = 0;
309 // We will test if the displacement fits the compressed format and if so
310 // apply the compression to the displacment iff the result is8bit.
311 if (VM_Version::supports_evex() && is_evex_inst) {
312 switch (cur_tuple_type) {
313 case EVEX_FV:
314 if ((cur_encoding & VEX_W) == VEX_W) {
315 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
316 } else {
317 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
318 }
319 break;
320
321 case EVEX_HV:
322 mod_idx = ((cur_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
323 break;
324
325 case EVEX_FVM:
326 break;
327
328 case EVEX_T1S:
329 switch (in_size_in_bits) {
330 case EVEX_8bit:
331 break;
332
333 case EVEX_16bit:
334 mod_idx = 1;
335 break;
336
337 case EVEX_32bit:
338 mod_idx = 2;
339 break;
340
341 case EVEX_64bit:
342 mod_idx = 3;
343 break;
344 }
345 break;
346
347 case EVEX_T1F:
348 case EVEX_T2:
349 case EVEX_T4:
350 mod_idx = (in_size_in_bits == EVEX_64bit) ? 1 : 0;
351 break;
352
353 case EVEX_T8:
354 break;
355
356 case EVEX_HVM:
357 break;
358
359 case EVEX_QVM:
360 break;
361
362 case EVEX_OVM:
363 break;
364
365 case EVEX_M128:
366 break;
367
368 case EVEX_DUP:
369 break;
370
371 default:
372 assert(0, "no valid evex tuple_table entry");
373 break;
374 }
375
376 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
377 int disp_factor = tuple_table[cur_tuple_type + mod_idx][vector_len];
378 if ((disp % disp_factor) == 0) {
379 int new_disp = disp / disp_factor;
380 if ((-0x80 <= new_disp && new_disp < 0x80)) {
381 disp = new_disp;
382 }
383 } else {
384 return false;
385 }
386 }
387 }
388 return (-0x80 <= disp && disp < 0x80);
389 }
390
391
392 bool Assembler::emit_compressed_disp_byte(int &disp) {
393 int mod_idx = 0;
394 // We will test if the displacement fits the compressed format and if so
395 // apply the compression to the displacment iff the result is8bit.
396 if (VM_Version::supports_evex() && _attributes && _attributes->is_evex_instruction()) {
397 int evex_encoding = _attributes->get_evex_encoding();
398 int tuple_type = _attributes->get_tuple_type();
399 switch (tuple_type) {
400 case EVEX_FV:
401 if ((evex_encoding & VEX_W) == VEX_W) {
402 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 3 : 2;
403 } else {
404 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
405 }
406 break;
407
408 case EVEX_HV:
409 mod_idx = ((evex_encoding & EVEX_Rb) == EVEX_Rb) ? 1 : 0;
410 break;
411
412 case EVEX_FVM:
413 break;
414
415 case EVEX_T1S:
416 switch (_attributes->get_input_size()) {
417 case EVEX_8bit:
418 break;
419
420 case EVEX_16bit:
421 mod_idx = 1;
422 break;
423
424 case EVEX_32bit:
425 mod_idx = 2;
426 break;
427
428 case EVEX_64bit:
429 mod_idx = 3;
430 break;
431 }
432 break;
433
434 case EVEX_T1F:
435 case EVEX_T2:
436 case EVEX_T4:
437 mod_idx = (_attributes->get_input_size() == EVEX_64bit) ? 1 : 0;
438 break;
439
440 case EVEX_T8:
441 break;
442
443 case EVEX_HVM:
444 break;
445
446 case EVEX_QVM:
447 break;
448
449 case EVEX_OVM:
450 break;
451
452 case EVEX_M128:
453 break;
454
455 case EVEX_DUP:
456 break;
457
458 default:
459 assert(0, "no valid evex tuple_table entry");
460 break;
461 }
462
463 int vector_len = _attributes->get_vector_len();
464 if (vector_len >= AVX_128bit && vector_len <= AVX_512bit) {
465 int disp_factor = tuple_table[tuple_type + mod_idx][vector_len];
466 if ((disp % disp_factor) == 0) {
467 int new_disp = disp / disp_factor;
468 if (is8bit(new_disp)) {
469 disp = new_disp;
470 }
471 } else {
472 return false;
473 }
474 }
475 }
476 return is8bit(disp);
477 }
478
479
480 void Assembler::emit_operand(Register reg, Register base, Register index,
481 Address::ScaleFactor scale, int disp,
482 RelocationHolder const& rspec,
483 int rip_relative_correction) {
484 relocInfo::relocType rtype = (relocInfo::relocType) rspec.type();
485
486 // Encode the registers as needed in the fields they are used in
487
488 int regenc = encode(reg) << 3;
489 int indexenc = index->is_valid() ? encode(index) << 3 : 0;
490 int baseenc = base->is_valid() ? encode(base) : 0;
491
492 if (base->is_valid()) {
493 if (index->is_valid()) {
494 assert(scale != Address::no_scale, "inconsistent address");
495 // [base + index*scale + disp]
496 if (disp == 0 && rtype == relocInfo::none &&
497 base != rbp LP64_ONLY(&& base != r13)) {
498 // [base + index*scale]
499 // [00 reg 100][ss index base]
500 assert(index != rsp, "illegal addressing mode");
501 emit_int8(0x04 | regenc);
502 emit_int8(scale << 6 | indexenc | baseenc);
503 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
504 // [base + index*scale + imm8]
505 // [01 reg 100][ss index base] imm8
506 assert(index != rsp, "illegal addressing mode");
507 emit_int8(0x44 | regenc);
508 emit_int8(scale << 6 | indexenc | baseenc);
509 emit_int8(disp & 0xFF);
510 } else {
511 // [base + index*scale + disp32]
512 // [10 reg 100][ss index base] disp32
513 assert(index != rsp, "illegal addressing mode");
514 emit_int8(0x84 | regenc);
515 emit_int8(scale << 6 | indexenc | baseenc);
516 emit_data(disp, rspec, disp32_operand);
517 }
518 } else if (base == rsp LP64_ONLY(|| base == r12)) {
519 // [rsp + disp]
520 if (disp == 0 && rtype == relocInfo::none) {
521 // [rsp]
522 // [00 reg 100][00 100 100]
523 emit_int8(0x04 | regenc);
524 emit_int8(0x24);
525 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
526 // [rsp + imm8]
527 // [01 reg 100][00 100 100] disp8
528 emit_int8(0x44 | regenc);
529 emit_int8(0x24);
530 emit_int8(disp & 0xFF);
531 } else {
532 // [rsp + imm32]
533 // [10 reg 100][00 100 100] disp32
534 emit_int8(0x84 | regenc);
535 emit_int8(0x24);
536 emit_data(disp, rspec, disp32_operand);
537 }
538 } else {
539 // [base + disp]
540 assert(base != rsp LP64_ONLY(&& base != r12), "illegal addressing mode");
541 if (disp == 0 && rtype == relocInfo::none &&
542 base != rbp LP64_ONLY(&& base != r13)) {
543 // [base]
544 // [00 reg base]
545 emit_int8(0x00 | regenc | baseenc);
546 } else if (emit_compressed_disp_byte(disp) && rtype == relocInfo::none) {
547 // [base + disp8]
548 // [01 reg base] disp8
549 emit_int8(0x40 | regenc | baseenc);
550 emit_int8(disp & 0xFF);
551 } else {
552 // [base + disp32]
553 // [10 reg base] disp32
554 emit_int8(0x80 | regenc | baseenc);
555 emit_data(disp, rspec, disp32_operand);
556 }
557 }
558 } else {
559 if (index->is_valid()) {
560 assert(scale != Address::no_scale, "inconsistent address");
561 // [index*scale + disp]
562 // [00 reg 100][ss index 101] disp32
563 assert(index != rsp, "illegal addressing mode");
564 emit_int8(0x04 | regenc);
565 emit_int8(scale << 6 | indexenc | 0x05);
566 emit_data(disp, rspec, disp32_operand);
567 } else if (rtype != relocInfo::none ) {
568 // [disp] (64bit) RIP-RELATIVE (32bit) abs
569 // [00 000 101] disp32
570
571 emit_int8(0x05 | regenc);
572 // Note that the RIP-rel. correction applies to the generated
573 // disp field, but _not_ to the target address in the rspec.
574
575 // disp was created by converting the target address minus the pc
576 // at the start of the instruction. That needs more correction here.
577 // intptr_t disp = target - next_ip;
578 assert(inst_mark() != NULL, "must be inside InstructionMark");
579 address next_ip = pc() + sizeof(int32_t) + rip_relative_correction;
580 int64_t adjusted = disp;
581 // Do rip-rel adjustment for 64bit
582 LP64_ONLY(adjusted -= (next_ip - inst_mark()));
583 assert(is_simm32(adjusted),
584 "must be 32bit offset (RIP relative address)");
585 emit_data((int32_t) adjusted, rspec, disp32_operand);
586
587 } else {
588 // 32bit never did this, did everything as the rip-rel/disp code above
589 // [disp] ABSOLUTE
590 // [00 reg 100][00 100 101] disp32
591 emit_int8(0x04 | regenc);
592 emit_int8(0x25);
593 emit_data(disp, rspec, disp32_operand);
594 }
595 }
596 }
597
598 void Assembler::emit_operand(XMMRegister reg, Register base, Register index,
599 Address::ScaleFactor scale, int disp,
600 RelocationHolder const& rspec) {
601 if (UseAVX > 2) {
602 int xreg_enc = reg->encoding();
603 if (xreg_enc > 15) {
604 XMMRegister new_reg = as_XMMRegister(xreg_enc & 0xf);
605 emit_operand((Register)new_reg, base, index, scale, disp, rspec);
606 return;
607 }
608 }
609 emit_operand((Register)reg, base, index, scale, disp, rspec);
610 }
611
612 // Secret local extension to Assembler::WhichOperand:
613 #define end_pc_operand (_WhichOperand_limit)
614
615 address Assembler::locate_operand(address inst, WhichOperand which) {
616 // Decode the given instruction, and return the address of
617 // an embedded 32-bit operand word.
618
619 // If "which" is disp32_operand, selects the displacement portion
620 // of an effective address specifier.
621 // If "which" is imm64_operand, selects the trailing immediate constant.
622 // If "which" is call32_operand, selects the displacement of a call or jump.
623 // Caller is responsible for ensuring that there is such an operand,
624 // and that it is 32/64 bits wide.
625
626 // If "which" is end_pc_operand, find the end of the instruction.
627
628 address ip = inst;
629 bool is_64bit = false;
630
631 debug_only(bool has_disp32 = false);
632 int tail_size = 0; // other random bytes (#32, #16, etc.) at end of insn
633
634 again_after_prefix:
635 switch (0xFF & *ip++) {
636
637 // These convenience macros generate groups of "case" labels for the switch.
638 #define REP4(x) (x)+0: case (x)+1: case (x)+2: case (x)+3
639 #define REP8(x) (x)+0: case (x)+1: case (x)+2: case (x)+3: \
640 case (x)+4: case (x)+5: case (x)+6: case (x)+7
641 #define REP16(x) REP8((x)+0): \
642 case REP8((x)+8)
643
644 case CS_segment:
645 case SS_segment:
646 case DS_segment:
647 case ES_segment:
648 case FS_segment:
649 case GS_segment:
650 // Seems dubious
651 LP64_ONLY(assert(false, "shouldn't have that prefix"));
652 assert(ip == inst+1, "only one prefix allowed");
653 goto again_after_prefix;
654
655 case 0x67:
656 case REX:
657 case REX_B:
658 case REX_X:
659 case REX_XB:
660 case REX_R:
661 case REX_RB:
662 case REX_RX:
663 case REX_RXB:
664 NOT_LP64(assert(false, "64bit prefixes"));
665 goto again_after_prefix;
666
667 case REX_W:
668 case REX_WB:
669 case REX_WX:
670 case REX_WXB:
671 case REX_WR:
672 case REX_WRB:
673 case REX_WRX:
674 case REX_WRXB:
675 NOT_LP64(assert(false, "64bit prefixes"));
676 is_64bit = true;
677 goto again_after_prefix;
678
679 case 0xFF: // pushq a; decl a; incl a; call a; jmp a
680 case 0x88: // movb a, r
681 case 0x89: // movl a, r
682 case 0x8A: // movb r, a
683 case 0x8B: // movl r, a
684 case 0x8F: // popl a
685 debug_only(has_disp32 = true);
686 break;
687
688 case 0x68: // pushq #32
689 if (which == end_pc_operand) {
690 return ip + 4;
691 }
692 assert(which == imm_operand && !is_64bit, "pushl has no disp32 or 64bit immediate");
693 return ip; // not produced by emit_operand
694
695 case 0x66: // movw ... (size prefix)
696 again_after_size_prefix2:
697 switch (0xFF & *ip++) {
698 case REX:
699 case REX_B:
700 case REX_X:
701 case REX_XB:
702 case REX_R:
703 case REX_RB:
704 case REX_RX:
705 case REX_RXB:
706 case REX_W:
707 case REX_WB:
708 case REX_WX:
709 case REX_WXB:
710 case REX_WR:
711 case REX_WRB:
712 case REX_WRX:
713 case REX_WRXB:
714 NOT_LP64(assert(false, "64bit prefix found"));
715 goto again_after_size_prefix2;
716 case 0x8B: // movw r, a
717 case 0x89: // movw a, r
718 debug_only(has_disp32 = true);
719 break;
720 case 0xC7: // movw a, #16
721 debug_only(has_disp32 = true);
722 tail_size = 2; // the imm16
723 break;
724 case 0x0F: // several SSE/SSE2 variants
725 ip--; // reparse the 0x0F
726 goto again_after_prefix;
727 default:
728 ShouldNotReachHere();
729 }
730 break;
731
732 case REP8(0xB8): // movl/q r, #32/#64(oop?)
733 if (which == end_pc_operand) return ip + (is_64bit ? 8 : 4);
734 // these asserts are somewhat nonsensical
735 #ifndef _LP64
736 assert(which == imm_operand || which == disp32_operand,
737 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
738 #else
739 assert((which == call32_operand || which == imm_operand) && is_64bit ||
740 which == narrow_oop_operand && !is_64bit,
741 "which %d is_64_bit %d ip " INTPTR_FORMAT, which, is_64bit, p2i(ip));
742 #endif // _LP64
743 return ip;
744
745 case 0x69: // imul r, a, #32
746 case 0xC7: // movl a, #32(oop?)
747 tail_size = 4;
748 debug_only(has_disp32 = true); // has both kinds of operands!
749 break;
750
751 case 0x0F: // movx..., etc.
752 switch (0xFF & *ip++) {
753 case 0x3A: // pcmpestri
754 tail_size = 1;
755 case 0x38: // ptest, pmovzxbw
756 ip++; // skip opcode
757 debug_only(has_disp32 = true); // has both kinds of operands!
758 break;
759
760 case 0x70: // pshufd r, r/a, #8
761 debug_only(has_disp32 = true); // has both kinds of operands!
762 case 0x73: // psrldq r, #8
763 tail_size = 1;
764 break;
765
766 case 0x12: // movlps
767 case 0x28: // movaps
768 case 0x2E: // ucomiss
769 case 0x2F: // comiss
770 case 0x54: // andps
771 case 0x55: // andnps
772 case 0x56: // orps
773 case 0x57: // xorps
774 case 0x58: // addpd
775 case 0x59: // mulpd
776 case 0x6E: // movd
777 case 0x7E: // movd
778 case 0xAE: // ldmxcsr, stmxcsr, fxrstor, fxsave, clflush
779 case 0xFE: // paddd
780 debug_only(has_disp32 = true);
781 break;
782
783 case 0xAD: // shrd r, a, %cl
784 case 0xAF: // imul r, a
785 case 0xBE: // movsbl r, a (movsxb)
786 case 0xBF: // movswl r, a (movsxw)
787 case 0xB6: // movzbl r, a (movzxb)
788 case 0xB7: // movzwl r, a (movzxw)
789 case REP16(0x40): // cmovl cc, r, a
790 case 0xB0: // cmpxchgb
791 case 0xB1: // cmpxchg
792 case 0xC1: // xaddl
793 case 0xC7: // cmpxchg8
794 case REP16(0x90): // setcc a
795 debug_only(has_disp32 = true);
796 // fall out of the switch to decode the address
797 break;
798
799 case 0xC4: // pinsrw r, a, #8
800 debug_only(has_disp32 = true);
801 case 0xC5: // pextrw r, r, #8
802 tail_size = 1; // the imm8
803 break;
804
805 case 0xAC: // shrd r, a, #8
806 debug_only(has_disp32 = true);
807 tail_size = 1; // the imm8
808 break;
809
810 case REP16(0x80): // jcc rdisp32
811 if (which == end_pc_operand) return ip + 4;
812 assert(which == call32_operand, "jcc has no disp32 or imm");
813 return ip;
814 default:
815 ShouldNotReachHere();
816 }
817 break;
818
819 case 0x81: // addl a, #32; addl r, #32
820 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
821 // on 32bit in the case of cmpl, the imm might be an oop
822 tail_size = 4;
823 debug_only(has_disp32 = true); // has both kinds of operands!
824 break;
825
826 case 0x83: // addl a, #8; addl r, #8
827 // also: orl, adcl, sbbl, andl, subl, xorl, cmpl
828 debug_only(has_disp32 = true); // has both kinds of operands!
829 tail_size = 1;
830 break;
831
832 case 0x9B:
833 switch (0xFF & *ip++) {
834 case 0xD9: // fnstcw a
835 debug_only(has_disp32 = true);
836 break;
837 default:
838 ShouldNotReachHere();
839 }
840 break;
841
842 case REP4(0x00): // addb a, r; addl a, r; addb r, a; addl r, a
843 case REP4(0x10): // adc...
844 case REP4(0x20): // and...
845 case REP4(0x30): // xor...
846 case REP4(0x08): // or...
847 case REP4(0x18): // sbb...
848 case REP4(0x28): // sub...
849 case 0xF7: // mull a
850 case 0x8D: // lea r, a
851 case 0x87: // xchg r, a
852 case REP4(0x38): // cmp...
853 case 0x85: // test r, a
854 debug_only(has_disp32 = true); // has both kinds of operands!
855 break;
856
857 case 0xC1: // sal a, #8; sar a, #8; shl a, #8; shr a, #8
858 case 0xC6: // movb a, #8
859 case 0x80: // cmpb a, #8
860 case 0x6B: // imul r, a, #8
861 debug_only(has_disp32 = true); // has both kinds of operands!
862 tail_size = 1; // the imm8
863 break;
864
865 case 0xC4: // VEX_3bytes
866 case 0xC5: // VEX_2bytes
867 assert((UseAVX > 0), "shouldn't have VEX prefix");
868 assert(ip == inst+1, "no prefixes allowed");
869 // C4 and C5 are also used as opcodes for PINSRW and PEXTRW instructions
870 // but they have prefix 0x0F and processed when 0x0F processed above.
871 //
872 // In 32-bit mode the VEX first byte C4 and C5 alias onto LDS and LES
873 // instructions (these instructions are not supported in 64-bit mode).
874 // To distinguish them bits [7:6] are set in the VEX second byte since
875 // ModRM byte can not be of the form 11xxxxxx in 32-bit mode. To set
876 // those VEX bits REX and vvvv bits are inverted.
877 //
878 // Fortunately C2 doesn't generate these instructions so we don't need
879 // to check for them in product version.
880
881 // Check second byte
882 NOT_LP64(assert((0xC0 & *ip) == 0xC0, "shouldn't have LDS and LES instructions"));
883
884 int vex_opcode;
885 // First byte
886 if ((0xFF & *inst) == VEX_3bytes) {
887 vex_opcode = VEX_OPCODE_MASK & *ip;
888 ip++; // third byte
889 is_64bit = ((VEX_W & *ip) == VEX_W);
890 } else {
891 vex_opcode = VEX_OPCODE_0F;
892 }
893 ip++; // opcode
894 // To find the end of instruction (which == end_pc_operand).
895 switch (vex_opcode) {
896 case VEX_OPCODE_0F:
897 switch (0xFF & *ip) {
898 case 0x70: // pshufd r, r/a, #8
899 case 0x71: // ps[rl|ra|ll]w r, #8
900 case 0x72: // ps[rl|ra|ll]d r, #8
901 case 0x73: // ps[rl|ra|ll]q r, #8
902 case 0xC2: // cmp[ps|pd|ss|sd] r, r, r/a, #8
903 case 0xC4: // pinsrw r, r, r/a, #8
904 case 0xC5: // pextrw r/a, r, #8
905 case 0xC6: // shufp[s|d] r, r, r/a, #8
906 tail_size = 1; // the imm8
907 break;
908 }
909 break;
910 case VEX_OPCODE_0F_3A:
911 tail_size = 1;
912 break;
913 }
914 ip++; // skip opcode
915 debug_only(has_disp32 = true); // has both kinds of operands!
916 break;
917
918 case 0x62: // EVEX_4bytes
919 assert(VM_Version::supports_evex(), "shouldn't have EVEX prefix");
920 assert(ip == inst+1, "no prefixes allowed");
921 // no EVEX collisions, all instructions that have 0x62 opcodes
922 // have EVEX versions and are subopcodes of 0x66
923 ip++; // skip P0 and exmaine W in P1
924 is_64bit = ((VEX_W & *ip) == VEX_W);
925 ip++; // move to P2
926 ip++; // skip P2, move to opcode
927 // To find the end of instruction (which == end_pc_operand).
928 switch (0xFF & *ip) {
929 case 0x22: // pinsrd r, r/a, #8
930 case 0x61: // pcmpestri r, r/a, #8
931 case 0x70: // pshufd r, r/a, #8
932 case 0x73: // psrldq r, #8
933 tail_size = 1; // the imm8
934 break;
935 default:
936 break;
937 }
938 ip++; // skip opcode
939 debug_only(has_disp32 = true); // has both kinds of operands!
940 break;
941
942 case 0xD1: // sal a, 1; sar a, 1; shl a, 1; shr a, 1
943 case 0xD3: // sal a, %cl; sar a, %cl; shl a, %cl; shr a, %cl
944 case 0xD9: // fld_s a; fst_s a; fstp_s a; fldcw a
945 case 0xDD: // fld_d a; fst_d a; fstp_d a
946 case 0xDB: // fild_s a; fistp_s a; fld_x a; fstp_x a
947 case 0xDF: // fild_d a; fistp_d a
948 case 0xD8: // fadd_s a; fsubr_s a; fmul_s a; fdivr_s a; fcomp_s a
949 case 0xDC: // fadd_d a; fsubr_d a; fmul_d a; fdivr_d a; fcomp_d a
950 case 0xDE: // faddp_d a; fsubrp_d a; fmulp_d a; fdivrp_d a; fcompp_d a
951 debug_only(has_disp32 = true);
952 break;
953
954 case 0xE8: // call rdisp32
955 case 0xE9: // jmp rdisp32
956 if (which == end_pc_operand) return ip + 4;
957 assert(which == call32_operand, "call has no disp32 or imm");
958 return ip;
959
960 case 0xF0: // Lock
961 assert(os::is_MP(), "only on MP");
962 goto again_after_prefix;
963
964 case 0xF3: // For SSE
965 case 0xF2: // For SSE2
966 switch (0xFF & *ip++) {
967 case REX:
968 case REX_B:
969 case REX_X:
970 case REX_XB:
971 case REX_R:
972 case REX_RB:
973 case REX_RX:
974 case REX_RXB:
975 case REX_W:
976 case REX_WB:
977 case REX_WX:
978 case REX_WXB:
979 case REX_WR:
980 case REX_WRB:
981 case REX_WRX:
982 case REX_WRXB:
983 NOT_LP64(assert(false, "found 64bit prefix"));
984 ip++;
985 default:
986 ip++;
987 }
988 debug_only(has_disp32 = true); // has both kinds of operands!
989 break;
990
991 default:
992 ShouldNotReachHere();
993
994 #undef REP8
995 #undef REP16
996 }
997
998 assert(which != call32_operand, "instruction is not a call, jmp, or jcc");
999 #ifdef _LP64
1000 assert(which != imm_operand, "instruction is not a movq reg, imm64");
1001 #else
1002 // assert(which != imm_operand || has_imm32, "instruction has no imm32 field");
1003 assert(which != imm_operand || has_disp32, "instruction has no imm32 field");
1004 #endif // LP64
1005 assert(which != disp32_operand || has_disp32, "instruction has no disp32 field");
1006
1007 // parse the output of emit_operand
1008 int op2 = 0xFF & *ip++;
1009 int base = op2 & 0x07;
1010 int op3 = -1;
1011 const int b100 = 4;
1012 const int b101 = 5;
1013 if (base == b100 && (op2 >> 6) != 3) {
1014 op3 = 0xFF & *ip++;
1015 base = op3 & 0x07; // refetch the base
1016 }
1017 // now ip points at the disp (if any)
1018
1019 switch (op2 >> 6) {
1020 case 0:
1021 // [00 reg 100][ss index base]
1022 // [00 reg 100][00 100 esp]
1023 // [00 reg base]
1024 // [00 reg 100][ss index 101][disp32]
1025 // [00 reg 101] [disp32]
1026
1027 if (base == b101) {
1028 if (which == disp32_operand)
1029 return ip; // caller wants the disp32
1030 ip += 4; // skip the disp32
1031 }
1032 break;
1033
1034 case 1:
1035 // [01 reg 100][ss index base][disp8]
1036 // [01 reg 100][00 100 esp][disp8]
1037 // [01 reg base] [disp8]
1038 ip += 1; // skip the disp8
1039 break;
1040
1041 case 2:
1042 // [10 reg 100][ss index base][disp32]
1043 // [10 reg 100][00 100 esp][disp32]
1044 // [10 reg base] [disp32]
1045 if (which == disp32_operand)
1046 return ip; // caller wants the disp32
1047 ip += 4; // skip the disp32
1048 break;
1049
1050 case 3:
1051 // [11 reg base] (not a memory addressing mode)
1052 break;
1053 }
1054
1055 if (which == end_pc_operand) {
1056 return ip + tail_size;
1057 }
1058
1059 #ifdef _LP64
1060 assert(which == narrow_oop_operand && !is_64bit, "instruction is not a movl adr, imm32");
1061 #else
1062 assert(which == imm_operand, "instruction has only an imm field");
1063 #endif // LP64
1064 return ip;
1065 }
1066
1067 address Assembler::locate_next_instruction(address inst) {
1068 // Secretly share code with locate_operand:
1069 return locate_operand(inst, end_pc_operand);
1070 }
1071
1072
1073 #ifdef ASSERT
1074 void Assembler::check_relocation(RelocationHolder const& rspec, int format) {
1075 address inst = inst_mark();
1076 assert(inst != NULL && inst < pc(), "must point to beginning of instruction");
1077 address opnd;
1078
1079 Relocation* r = rspec.reloc();
1080 if (r->type() == relocInfo::none) {
1081 return;
1082 } else if (r->is_call() || format == call32_operand) {
1083 // assert(format == imm32_operand, "cannot specify a nonzero format");
1084 opnd = locate_operand(inst, call32_operand);
1085 } else if (r->is_data()) {
1086 assert(format == imm_operand || format == disp32_operand
1087 LP64_ONLY(|| format == narrow_oop_operand), "format ok");
1088 opnd = locate_operand(inst, (WhichOperand)format);
1089 } else {
1090 assert(format == imm_operand, "cannot specify a format");
1091 return;
1092 }
1093 assert(opnd == pc(), "must put operand where relocs can find it");
1094 }
1095 #endif // ASSERT
1096
1097 void Assembler::emit_operand32(Register reg, Address adr) {
1098 assert(reg->encoding() < 8, "no extended registers");
1099 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1100 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1101 adr._rspec);
1102 }
1103
1104 void Assembler::emit_operand(Register reg, Address adr,
1105 int rip_relative_correction) {
1106 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1107 adr._rspec,
1108 rip_relative_correction);
1109 }
1110
1111 void Assembler::emit_operand(XMMRegister reg, Address adr) {
1112 emit_operand(reg, adr._base, adr._index, adr._scale, adr._disp,
1113 adr._rspec);
1114 }
1115
1116 // MMX operations
1117 void Assembler::emit_operand(MMXRegister reg, Address adr) {
1118 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1119 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1120 }
1121
1122 // work around gcc (3.2.1-7a) bug
1123 void Assembler::emit_operand(Address adr, MMXRegister reg) {
1124 assert(!adr.base_needs_rex() && !adr.index_needs_rex(), "no extended registers");
1125 emit_operand((Register)reg, adr._base, adr._index, adr._scale, adr._disp, adr._rspec);
1126 }
1127
1128
1129 void Assembler::emit_farith(int b1, int b2, int i) {
1130 assert(isByte(b1) && isByte(b2), "wrong opcode");
1131 assert(0 <= i && i < 8, "illegal stack offset");
1132 emit_int8(b1);
1133 emit_int8(b2 + i);
1134 }
1135
1136
1137 // Now the Assembler instructions (identical for 32/64 bits)
1138
1139 void Assembler::adcl(Address dst, int32_t imm32) {
1140 InstructionMark im(this);
1141 prefix(dst);
1142 emit_arith_operand(0x81, rdx, dst, imm32);
1143 }
1144
1145 void Assembler::adcl(Address dst, Register src) {
1146 InstructionMark im(this);
1147 prefix(dst, src);
1148 emit_int8(0x11);
1149 emit_operand(src, dst);
1150 }
1151
1152 void Assembler::adcl(Register dst, int32_t imm32) {
1153 prefix(dst);
1154 emit_arith(0x81, 0xD0, dst, imm32);
1155 }
1156
1157 void Assembler::adcl(Register dst, Address src) {
1158 InstructionMark im(this);
1159 prefix(src, dst);
1160 emit_int8(0x13);
1161 emit_operand(dst, src);
1162 }
1163
1164 void Assembler::adcl(Register dst, Register src) {
1165 (void) prefix_and_encode(dst->encoding(), src->encoding());
1166 emit_arith(0x13, 0xC0, dst, src);
1167 }
1168
1169 void Assembler::addl(Address dst, int32_t imm32) {
1170 InstructionMark im(this);
1171 prefix(dst);
1172 emit_arith_operand(0x81, rax, dst, imm32);
1173 }
1174
1175 void Assembler::addb(Register dst, Register src) {
1176 (void)prefix_and_encode(dst->encoding(), src->encoding());
1177 emit_arith(0x02, 0xC0, dst, src);
1178 }
1179
1180 void Assembler::addb(Address dst, int imm8) {
1181 InstructionMark im(this);
1182 prefix(dst);
1183 emit_int8((unsigned char)0x80);
1184 emit_operand(rax, dst, 1);
1185 emit_int8(imm8);
1186 }
1187
1188 void Assembler::addw(Register dst, Register src) {
1189 (void)prefix_and_encode(dst->encoding(), src->encoding());
1190 emit_arith(0x03, 0xC0, dst, src);
1191 }
1192
1193 void Assembler::addw(Address dst, int imm16) {
1194 InstructionMark im(this);
1195 emit_int8(0x66);
1196 prefix(dst);
1197 emit_int8((unsigned char)0x81);
1198 emit_operand(rax, dst, 2);
1199 emit_int16(imm16);
1200 }
1201
1202 void Assembler::addl(Address dst, Register src) {
1203 InstructionMark im(this);
1204 prefix(dst, src);
1205 emit_int8(0x01);
1206 emit_operand(src, dst);
1207 }
1208
1209 void Assembler::addl(Register dst, int32_t imm32) {
1210 prefix(dst);
1211 emit_arith(0x81, 0xC0, dst, imm32);
1212 }
1213
1214 void Assembler::addl(Register dst, Address src) {
1215 InstructionMark im(this);
1216 prefix(src, dst);
1217 emit_int8(0x03);
1218 emit_operand(dst, src);
1219 }
1220
1221 void Assembler::addl(Register dst, Register src) {
1222 (void) prefix_and_encode(dst->encoding(), src->encoding());
1223 emit_arith(0x03, 0xC0, dst, src);
1224 }
1225
1226 void Assembler::addr_nop_4() {
1227 assert(UseAddressNop, "no CPU support");
1228 // 4 bytes: NOP DWORD PTR [EAX+0]
1229 emit_int8(0x0F);
1230 emit_int8(0x1F);
1231 emit_int8(0x40); // emit_rm(cbuf, 0x1, EAX_enc, EAX_enc);
1232 emit_int8(0); // 8-bits offset (1 byte)
1233 }
1234
1235 void Assembler::addr_nop_5() {
1236 assert(UseAddressNop, "no CPU support");
1237 // 5 bytes: NOP DWORD PTR [EAX+EAX*0+0] 8-bits offset
1238 emit_int8(0x0F);
1239 emit_int8(0x1F);
1240 emit_int8(0x44); // emit_rm(cbuf, 0x1, EAX_enc, 0x4);
1241 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1242 emit_int8(0); // 8-bits offset (1 byte)
1243 }
1244
1245 void Assembler::addr_nop_7() {
1246 assert(UseAddressNop, "no CPU support");
1247 // 7 bytes: NOP DWORD PTR [EAX+0] 32-bits offset
1248 emit_int8(0x0F);
1249 emit_int8(0x1F);
1250 emit_int8((unsigned char)0x80);
1251 // emit_rm(cbuf, 0x2, EAX_enc, EAX_enc);
1252 emit_int32(0); // 32-bits offset (4 bytes)
1253 }
1254
1255 void Assembler::addr_nop_8() {
1256 assert(UseAddressNop, "no CPU support");
1257 // 8 bytes: NOP DWORD PTR [EAX+EAX*0+0] 32-bits offset
1258 emit_int8(0x0F);
1259 emit_int8(0x1F);
1260 emit_int8((unsigned char)0x84);
1261 // emit_rm(cbuf, 0x2, EAX_enc, 0x4);
1262 emit_int8(0x00); // emit_rm(cbuf, 0x0, EAX_enc, EAX_enc);
1263 emit_int32(0); // 32-bits offset (4 bytes)
1264 }
1265
1266 void Assembler::addsd(XMMRegister dst, XMMRegister src) {
1267 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1268 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1269 attributes.set_rex_vex_w_reverted();
1270 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1271 emit_int8(0x58);
1272 emit_int8((unsigned char)(0xC0 | encode));
1273 }
1274
1275 void Assembler::addsd(XMMRegister dst, Address src) {
1276 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1277 InstructionMark im(this);
1278 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1279 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1280 attributes.set_rex_vex_w_reverted();
1281 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1282 emit_int8(0x58);
1283 emit_operand(dst, src);
1284 }
1285
1286 void Assembler::addss(XMMRegister dst, XMMRegister src) {
1287 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1288 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1289 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1290 emit_int8(0x58);
1291 emit_int8((unsigned char)(0xC0 | encode));
1292 }
1293
1294 void Assembler::addss(XMMRegister dst, Address src) {
1295 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1296 InstructionMark im(this);
1297 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1298 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1299 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1300 emit_int8(0x58);
1301 emit_operand(dst, src);
1302 }
1303
1304 void Assembler::aesdec(XMMRegister dst, Address src) {
1305 assert(VM_Version::supports_aes(), "");
1306 InstructionMark im(this);
1307 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1308 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1309 emit_int8((unsigned char)0xDE);
1310 emit_operand(dst, src);
1311 }
1312
1313 void Assembler::aesdec(XMMRegister dst, XMMRegister src) {
1314 assert(VM_Version::supports_aes(), "");
1315 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1316 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1317 emit_int8((unsigned char)0xDE);
1318 emit_int8(0xC0 | encode);
1319 }
1320
1321 void Assembler::aesdeclast(XMMRegister dst, Address src) {
1322 assert(VM_Version::supports_aes(), "");
1323 InstructionMark im(this);
1324 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1325 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1326 emit_int8((unsigned char)0xDF);
1327 emit_operand(dst, src);
1328 }
1329
1330 void Assembler::aesdeclast(XMMRegister dst, XMMRegister src) {
1331 assert(VM_Version::supports_aes(), "");
1332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1333 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1334 emit_int8((unsigned char)0xDF);
1335 emit_int8((unsigned char)(0xC0 | encode));
1336 }
1337
1338 void Assembler::aesenc(XMMRegister dst, Address src) {
1339 assert(VM_Version::supports_aes(), "");
1340 InstructionMark im(this);
1341 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1342 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1343 emit_int8((unsigned char)0xDC);
1344 emit_operand(dst, src);
1345 }
1346
1347 void Assembler::aesenc(XMMRegister dst, XMMRegister src) {
1348 assert(VM_Version::supports_aes(), "");
1349 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1350 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1351 emit_int8((unsigned char)0xDC);
1352 emit_int8(0xC0 | encode);
1353 }
1354
1355 void Assembler::aesenclast(XMMRegister dst, Address src) {
1356 assert(VM_Version::supports_aes(), "");
1357 InstructionMark im(this);
1358 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1359 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1360 emit_int8((unsigned char)0xDD);
1361 emit_operand(dst, src);
1362 }
1363
1364 void Assembler::aesenclast(XMMRegister dst, XMMRegister src) {
1365 assert(VM_Version::supports_aes(), "");
1366 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1367 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1368 emit_int8((unsigned char)0xDD);
1369 emit_int8((unsigned char)(0xC0 | encode));
1370 }
1371
1372 void Assembler::andb(Register dst, Register src) {
1373 (void)prefix_and_encode(dst->encoding(), src->encoding());
1374 emit_arith(0x22, 0xC0, dst, src);
1375 }
1376
1377 void Assembler::andw(Register dst, Register src) {
1378 (void)prefix_and_encode(dst->encoding(), src->encoding());
1379 emit_arith(0x23, 0xC0, dst, src);
1380 }
1381
1382 void Assembler::andl(Address dst, int32_t imm32) {
1383 InstructionMark im(this);
1384 prefix(dst);
1385 emit_int8((unsigned char)0x81);
1386 emit_operand(rsp, dst, 4);
1387 emit_int32(imm32);
1388 }
1389
1390 void Assembler::andl(Register dst, int32_t imm32) {
1391 prefix(dst);
1392 emit_arith(0x81, 0xE0, dst, imm32);
1393 }
1394
1395 void Assembler::andl(Register dst, Address src) {
1396 InstructionMark im(this);
1397 prefix(src, dst);
1398 emit_int8(0x23);
1399 emit_operand(dst, src);
1400 }
1401
1402 void Assembler::andl(Register dst, Register src) {
1403 (void) prefix_and_encode(dst->encoding(), src->encoding());
1404 emit_arith(0x23, 0xC0, dst, src);
1405 }
1406
1407 void Assembler::andnl(Register dst, Register src1, Register src2) {
1408 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1409 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1410 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1411 emit_int8((unsigned char)0xF2);
1412 emit_int8((unsigned char)(0xC0 | encode));
1413 }
1414
1415 void Assembler::andnl(Register dst, Register src1, Address src2) {
1416 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1417 InstructionMark im(this);
1418 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1419 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1420 emit_int8((unsigned char)0xF2);
1421 emit_operand(dst, src2);
1422 }
1423
1424 void Assembler::bsfl(Register dst, Register src) {
1425 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1426 emit_int8(0x0F);
1427 emit_int8((unsigned char)0xBC);
1428 emit_int8((unsigned char)(0xC0 | encode));
1429 }
1430
1431 void Assembler::bsrl(Register dst, Register src) {
1432 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1433 emit_int8(0x0F);
1434 emit_int8((unsigned char)0xBD);
1435 emit_int8((unsigned char)(0xC0 | encode));
1436 }
1437
1438 void Assembler::bswapl(Register reg) { // bswap
1439 int encode = prefix_and_encode(reg->encoding());
1440 emit_int8(0x0F);
1441 emit_int8((unsigned char)(0xC8 | encode));
1442 }
1443
1444 void Assembler::blsil(Register dst, Register src) {
1445 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1446 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1447 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1448 emit_int8((unsigned char)0xF3);
1449 emit_int8((unsigned char)(0xC0 | encode));
1450 }
1451
1452 void Assembler::blsil(Register dst, Address src) {
1453 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1454 InstructionMark im(this);
1455 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1456 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1457 emit_int8((unsigned char)0xF3);
1458 emit_operand(rbx, src);
1459 }
1460
1461 void Assembler::blsmskl(Register dst, Register src) {
1462 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1463 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1464 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1465 emit_int8((unsigned char)0xF3);
1466 emit_int8((unsigned char)(0xC0 | encode));
1467 }
1468
1469 void Assembler::blsmskl(Register dst, Address src) {
1470 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1471 InstructionMark im(this);
1472 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1473 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1474 emit_int8((unsigned char)0xF3);
1475 emit_operand(rdx, src);
1476 }
1477
1478 void Assembler::blsrl(Register dst, Register src) {
1479 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1480 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1481 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1482 emit_int8((unsigned char)0xF3);
1483 emit_int8((unsigned char)(0xC0 | encode));
1484 }
1485
1486 void Assembler::blsrl(Register dst, Address src) {
1487 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
1488 InstructionMark im(this);
1489 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
1490 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
1491 emit_int8((unsigned char)0xF3);
1492 emit_operand(rcx, src);
1493 }
1494
1495 void Assembler::call(Label& L, relocInfo::relocType rtype) {
1496 // suspect disp32 is always good
1497 int operand = LP64_ONLY(disp32_operand) NOT_LP64(imm_operand);
1498
1499 if (L.is_bound()) {
1500 const int long_size = 5;
1501 int offs = (int)( target(L) - pc() );
1502 assert(offs <= 0, "assembler error");
1503 InstructionMark im(this);
1504 // 1110 1000 #32-bit disp
1505 emit_int8((unsigned char)0xE8);
1506 emit_data(offs - long_size, rtype, operand);
1507 } else {
1508 InstructionMark im(this);
1509 // 1110 1000 #32-bit disp
1510 L.add_patch_at(code(), locator());
1511
1512 emit_int8((unsigned char)0xE8);
1513 emit_data(int(0), rtype, operand);
1514 }
1515 }
1516
1517 void Assembler::call(Register dst) {
1518 int encode = prefix_and_encode(dst->encoding());
1519 emit_int8((unsigned char)0xFF);
1520 emit_int8((unsigned char)(0xD0 | encode));
1521 }
1522
1523
1524 void Assembler::call(Address adr) {
1525 InstructionMark im(this);
1526 prefix(adr);
1527 emit_int8((unsigned char)0xFF);
1528 emit_operand(rdx, adr);
1529 }
1530
1531 void Assembler::call_literal(address entry, RelocationHolder const& rspec) {
1532 InstructionMark im(this);
1533 emit_int8((unsigned char)0xE8);
1534 intptr_t disp = entry - (pc() + sizeof(int32_t));
1535 // Entry is NULL in case of a scratch emit.
1536 assert(entry == NULL || is_simm32(disp), "disp=" INTPTR_FORMAT " must be 32bit offset (call2)", disp);
1537 // Technically, should use call32_operand, but this format is
1538 // implied by the fact that we're emitting a call instruction.
1539
1540 int operand = LP64_ONLY(disp32_operand) NOT_LP64(call32_operand);
1541 emit_data((int) disp, rspec, operand);
1542 }
1543
1544 void Assembler::cdql() {
1545 emit_int8((unsigned char)0x99);
1546 }
1547
1548 void Assembler::cld() {
1549 emit_int8((unsigned char)0xFC);
1550 }
1551
1552 void Assembler::cmovl(Condition cc, Register dst, Register src) {
1553 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1554 int encode = prefix_and_encode(dst->encoding(), src->encoding());
1555 emit_int8(0x0F);
1556 emit_int8(0x40 | cc);
1557 emit_int8((unsigned char)(0xC0 | encode));
1558 }
1559
1560
1561 void Assembler::cmovl(Condition cc, Register dst, Address src) {
1562 NOT_LP64(guarantee(VM_Version::supports_cmov(), "illegal instruction"));
1563 prefix(src, dst);
1564 emit_int8(0x0F);
1565 emit_int8(0x40 | cc);
1566 emit_operand(dst, src);
1567 }
1568
1569 void Assembler::cmpb(Address dst, int imm8) {
1570 InstructionMark im(this);
1571 prefix(dst);
1572 emit_int8((unsigned char)0x80);
1573 emit_operand(rdi, dst, 1);
1574 emit_int8(imm8);
1575 }
1576
1577 void Assembler::cmpl(Address dst, int32_t imm32) {
1578 InstructionMark im(this);
1579 prefix(dst);
1580 emit_int8((unsigned char)0x81);
1581 emit_operand(rdi, dst, 4);
1582 emit_int32(imm32);
1583 }
1584
1585 void Assembler::cmpl(Register dst, int32_t imm32) {
1586 prefix(dst);
1587 emit_arith(0x81, 0xF8, dst, imm32);
1588 }
1589
1590 void Assembler::cmpl(Register dst, Register src) {
1591 (void) prefix_and_encode(dst->encoding(), src->encoding());
1592 emit_arith(0x3B, 0xC0, dst, src);
1593 }
1594
1595 void Assembler::cmpl(Register dst, Address src) {
1596 InstructionMark im(this);
1597 prefix(src, dst);
1598 emit_int8((unsigned char)0x3B);
1599 emit_operand(dst, src);
1600 }
1601
1602 void Assembler::cmpw(Address dst, int imm16) {
1603 InstructionMark im(this);
1604 assert(!dst.base_needs_rex() && !dst.index_needs_rex(), "no extended registers");
1605 emit_int8(0x66);
1606 emit_int8((unsigned char)0x81);
1607 emit_operand(rdi, dst, 2);
1608 emit_int16(imm16);
1609 }
1610
1611 // The 32-bit cmpxchg compares the value at adr with the contents of rax,
1612 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1613 // The ZF is set if the compared values were equal, and cleared otherwise.
1614 void Assembler::cmpxchgl(Register reg, Address adr) { // cmpxchg
1615 InstructionMark im(this);
1616 prefix(adr, reg);
1617 emit_int8(0x0F);
1618 emit_int8((unsigned char)0xB1);
1619 emit_operand(reg, adr);
1620 }
1621
1622 // The 8-bit cmpxchg compares the value at adr with the contents of rax,
1623 // and stores reg into adr if so; otherwise, the value at adr is loaded into rax,.
1624 // The ZF is set if the compared values were equal, and cleared otherwise.
1625 void Assembler::cmpxchgb(Register reg, Address adr) { // cmpxchg
1626 InstructionMark im(this);
1627 prefix(adr, reg, true);
1628 emit_int8(0x0F);
1629 emit_int8((unsigned char)0xB0);
1630 emit_operand(reg, adr);
1631 }
1632
1633 void Assembler::comisd(XMMRegister dst, Address src) {
1634 // NOTE: dbx seems to decode this as comiss even though the
1635 // 0x66 is there. Strangly ucomisd comes out correct
1636 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1637 InstructionMark im(this);
1638 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);;
1639 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1640 attributes.set_rex_vex_w_reverted();
1641 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1642 emit_int8(0x2F);
1643 emit_operand(dst, src);
1644 }
1645
1646 void Assembler::comisd(XMMRegister dst, XMMRegister src) {
1647 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1648 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1649 attributes.set_rex_vex_w_reverted();
1650 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1651 emit_int8(0x2F);
1652 emit_int8((unsigned char)(0xC0 | encode));
1653 }
1654
1655 void Assembler::comiss(XMMRegister dst, Address src) {
1656 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1657 InstructionMark im(this);
1658 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1659 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1660 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1661 emit_int8(0x2F);
1662 emit_operand(dst, src);
1663 }
1664
1665 void Assembler::comiss(XMMRegister dst, XMMRegister src) {
1666 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1667 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1668 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1669 emit_int8(0x2F);
1670 emit_int8((unsigned char)(0xC0 | encode));
1671 }
1672
1673 void Assembler::cpuid() {
1674 emit_int8(0x0F);
1675 emit_int8((unsigned char)0xA2);
1676 }
1677
1678 // Opcode / Instruction Op / En 64 - Bit Mode Compat / Leg Mode Description Implemented
1679 // F2 0F 38 F0 / r CRC32 r32, r / m8 RM Valid Valid Accumulate CRC32 on r / m8. v
1680 // F2 REX 0F 38 F0 / r CRC32 r32, r / m8* RM Valid N.E. Accumulate CRC32 on r / m8. -
1681 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E. Accumulate CRC32 on r / m8. -
1682 //
1683 // F2 0F 38 F1 / r CRC32 r32, r / m16 RM Valid Valid Accumulate CRC32 on r / m16. v
1684 //
1685 // F2 0F 38 F1 / r CRC32 r32, r / m32 RM Valid Valid Accumulate CRC32 on r / m32. v
1686 //
1687 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E. Accumulate CRC32 on r / m64. v
1688 void Assembler::crc32(Register crc, Register v, int8_t sizeInBytes) {
1689 assert(VM_Version::supports_sse4_2(), "");
1690 int8_t w = 0x01;
1691 Prefix p = Prefix_EMPTY;
1692
1693 emit_int8((int8_t)0xF2);
1694 switch (sizeInBytes) {
1695 case 1:
1696 w = 0;
1697 break;
1698 case 2:
1699 case 4:
1700 break;
1701 LP64_ONLY(case 8:)
1702 // This instruction is not valid in 32 bits
1703 // Note:
1704 // http://www.intel.com/content/dam/www/public/us/en/documents/manuals/64-ia-32-architectures-software-developer-instruction-set-reference-manual-325383.pdf
1705 //
1706 // Page B - 72 Vol. 2C says
1707 // qwreg2 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : 11 qwreg1 qwreg2
1708 // mem64 to qwreg 1111 0010 : 0100 1R0B : 0000 1111 : 0011 1000 : 1111 0000 : mod qwreg r / m
1709 // F0!!!
1710 // while 3 - 208 Vol. 2A
1711 // F2 REX.W 0F 38 F1 / r CRC32 r64, r / m64 RM Valid N.E.Accumulate CRC32 on r / m64.
1712 //
1713 // the 0 on a last bit is reserved for a different flavor of this instruction :
1714 // F2 REX.W 0F 38 F0 / r CRC32 r64, r / m8 RM Valid N.E.Accumulate CRC32 on r / m8.
1715 p = REX_W;
1716 break;
1717 default:
1718 assert(0, "Unsupported value for a sizeInBytes argument");
1719 break;
1720 }
1721 LP64_ONLY(prefix(crc, v, p);)
1722 emit_int8((int8_t)0x0F);
1723 emit_int8(0x38);
1724 emit_int8((int8_t)(0xF0 | w));
1725 emit_int8(0xC0 | ((crc->encoding() & 0x7) << 3) | (v->encoding() & 7));
1726 }
1727
1728 void Assembler::crc32(Register crc, Address adr, int8_t sizeInBytes) {
1729 assert(VM_Version::supports_sse4_2(), "");
1730 InstructionMark im(this);
1731 int8_t w = 0x01;
1732 Prefix p = Prefix_EMPTY;
1733
1734 emit_int8((int8_t)0xF2);
1735 switch (sizeInBytes) {
1736 case 1:
1737 w = 0;
1738 break;
1739 case 2:
1740 case 4:
1741 break;
1742 LP64_ONLY(case 8:)
1743 // This instruction is not valid in 32 bits
1744 p = REX_W;
1745 break;
1746 default:
1747 assert(0, "Unsupported value for a sizeInBytes argument");
1748 break;
1749 }
1750 LP64_ONLY(prefix(crc, adr, p);)
1751 emit_int8((int8_t)0x0F);
1752 emit_int8(0x38);
1753 emit_int8((int8_t)(0xF0 | w));
1754 emit_operand(crc, adr);
1755 }
1756
1757 void Assembler::cvtdq2pd(XMMRegister dst, XMMRegister src) {
1758 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1759 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1760 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1761 emit_int8((unsigned char)0xE6);
1762 emit_int8((unsigned char)(0xC0 | encode));
1763 }
1764
1765 void Assembler::cvtdq2ps(XMMRegister dst, XMMRegister src) {
1766 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1767 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1768 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1769 emit_int8(0x5B);
1770 emit_int8((unsigned char)(0xC0 | encode));
1771 }
1772
1773 void Assembler::cvtsd2ss(XMMRegister dst, XMMRegister src) {
1774 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1775 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1776 attributes.set_rex_vex_w_reverted();
1777 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1778 emit_int8(0x5A);
1779 emit_int8((unsigned char)(0xC0 | encode));
1780 }
1781
1782 void Assembler::cvtsd2ss(XMMRegister dst, Address src) {
1783 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1784 InstructionMark im(this);
1785 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1786 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1787 attributes.set_rex_vex_w_reverted();
1788 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1789 emit_int8(0x5A);
1790 emit_operand(dst, src);
1791 }
1792
1793 void Assembler::cvtsi2sdl(XMMRegister dst, Register src) {
1794 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1795 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1796 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1797 emit_int8(0x2A);
1798 emit_int8((unsigned char)(0xC0 | encode));
1799 }
1800
1801 void Assembler::cvtsi2sdl(XMMRegister dst, Address src) {
1802 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1803 InstructionMark im(this);
1804 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1805 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1806 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1807 emit_int8(0x2A);
1808 emit_operand(dst, src);
1809 }
1810
1811 void Assembler::cvtsi2ssl(XMMRegister dst, Register src) {
1812 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1813 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1814 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1815 emit_int8(0x2A);
1816 emit_int8((unsigned char)(0xC0 | encode));
1817 }
1818
1819 void Assembler::cvtsi2ssl(XMMRegister dst, Address src) {
1820 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1821 InstructionMark im(this);
1822 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1823 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1824 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1825 emit_int8(0x2A);
1826 emit_operand(dst, src);
1827 }
1828
1829 void Assembler::cvtsi2ssq(XMMRegister dst, Register src) {
1830 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1831 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1832 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1833 emit_int8(0x2A);
1834 emit_int8((unsigned char)(0xC0 | encode));
1835 }
1836
1837 void Assembler::cvtss2sd(XMMRegister dst, XMMRegister src) {
1838 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1839 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1840 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1841 emit_int8(0x5A);
1842 emit_int8((unsigned char)(0xC0 | encode));
1843 }
1844
1845 void Assembler::cvtss2sd(XMMRegister dst, Address src) {
1846 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1847 InstructionMark im(this);
1848 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1849 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1850 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1851 emit_int8(0x5A);
1852 emit_operand(dst, src);
1853 }
1854
1855
1856 void Assembler::cvttsd2sil(Register dst, XMMRegister src) {
1857 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1858 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1859 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1860 emit_int8(0x2C);
1861 emit_int8((unsigned char)(0xC0 | encode));
1862 }
1863
1864 void Assembler::cvttss2sil(Register dst, XMMRegister src) {
1865 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1866 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1867 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1868 emit_int8(0x2C);
1869 emit_int8((unsigned char)(0xC0 | encode));
1870 }
1871
1872 void Assembler::cvttpd2dq(XMMRegister dst, XMMRegister src) {
1873 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1874 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
1875 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1876 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
1877 emit_int8((unsigned char)0xE6);
1878 emit_int8((unsigned char)(0xC0 | encode));
1879 }
1880
1881 void Assembler::vcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len) {
1882 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
1883 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1884 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1885 emit_int8((unsigned char)0x5A);
1886 emit_int8((unsigned char)(0xC0 | encode));
1887
1888 }
1889
1890 void Assembler::evcvtps2pd(XMMRegister dst, XMMRegister src, int vector_len) {
1891 assert(UseAVX > 2, "");
1892 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
1893 attributes.set_is_evex_instruction();
1894 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
1895 emit_int8((unsigned char)0x5A);
1896 emit_int8((unsigned char)(0xC0 | encode));
1897 }
1898
1899 void Assembler::pabsd(XMMRegister dst, XMMRegister src) {
1900 assert(VM_Version::supports_ssse3(), "");
1901 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1902 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1903 emit_int8(0x1E);
1904 emit_int8((unsigned char)(0xC0 | encode));
1905 }
1906
1907 void Assembler::vpabsb(XMMRegister dst, XMMRegister src, int vector_len) {
1908 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
1909 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1910 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1911 emit_int8((unsigned char)0x1C);
1912 emit_int8((unsigned char)(0xC0 | encode));
1913 }
1914
1915 void Assembler::vpabsw(XMMRegister dst, XMMRegister src, int vector_len) {
1916 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
1917 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1918 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1919 emit_int8((unsigned char)0x1D);
1920 emit_int8((unsigned char)(0xC0 | encode));
1921 }
1922
1923 void Assembler::vpabsd(XMMRegister dst, XMMRegister src, int vector_len) {
1924 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
1925 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1926 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1927 emit_int8((unsigned char)0x1E);
1928 emit_int8((unsigned char)(0xC0 | encode));
1929 }
1930
1931 void Assembler::evpabsd(XMMRegister dst, XMMRegister src, int vector_len) {
1932 assert(UseAVX > 2, "");
1933 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
1934 attributes.set_is_evex_instruction();
1935 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
1936 emit_int8((unsigned char)0x1E);
1937 emit_int8((unsigned char)(0xC0 | encode));
1938 }
1939
1940 void Assembler::decl(Address dst) {
1941 // Don't use it directly. Use MacroAssembler::decrement() instead.
1942 InstructionMark im(this);
1943 prefix(dst);
1944 emit_int8((unsigned char)0xFF);
1945 emit_operand(rcx, dst);
1946 }
1947
1948 void Assembler::divsd(XMMRegister dst, Address src) {
1949 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1950 InstructionMark im(this);
1951 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1952 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
1953 attributes.set_rex_vex_w_reverted();
1954 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1955 emit_int8(0x5E);
1956 emit_operand(dst, src);
1957 }
1958
1959 void Assembler::divsd(XMMRegister dst, XMMRegister src) {
1960 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
1961 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1962 attributes.set_rex_vex_w_reverted();
1963 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
1964 emit_int8(0x5E);
1965 emit_int8((unsigned char)(0xC0 | encode));
1966 }
1967
1968 void Assembler::divss(XMMRegister dst, Address src) {
1969 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1970 InstructionMark im(this);
1971 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1972 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
1973 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1974 emit_int8(0x5E);
1975 emit_operand(dst, src);
1976 }
1977
1978 void Assembler::divss(XMMRegister dst, XMMRegister src) {
1979 NOT_LP64(assert(VM_Version::supports_sse(), ""));
1980 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
1981 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
1982 emit_int8(0x5E);
1983 emit_int8((unsigned char)(0xC0 | encode));
1984 }
1985
1986 void Assembler::emms() {
1987 NOT_LP64(assert(VM_Version::supports_mmx(), ""));
1988 emit_int8(0x0F);
1989 emit_int8(0x77);
1990 }
1991
1992 void Assembler::hlt() {
1993 emit_int8((unsigned char)0xF4);
1994 }
1995
1996 void Assembler::idivl(Register src) {
1997 int encode = prefix_and_encode(src->encoding());
1998 emit_int8((unsigned char)0xF7);
1999 emit_int8((unsigned char)(0xF8 | encode));
2000 }
2001
2002 void Assembler::divl(Register src) { // Unsigned
2003 int encode = prefix_and_encode(src->encoding());
2004 emit_int8((unsigned char)0xF7);
2005 emit_int8((unsigned char)(0xF0 | encode));
2006 }
2007
2008 void Assembler::imull(Register src) {
2009 int encode = prefix_and_encode(src->encoding());
2010 emit_int8((unsigned char)0xF7);
2011 emit_int8((unsigned char)(0xE8 | encode));
2012 }
2013
2014 void Assembler::imull(Register dst, Register src) {
2015 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2016 emit_int8(0x0F);
2017 emit_int8((unsigned char)0xAF);
2018 emit_int8((unsigned char)(0xC0 | encode));
2019 }
2020
2021
2022 void Assembler::imull(Register dst, Register src, int value) {
2023 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2024 if (is8bit(value)) {
2025 emit_int8(0x6B);
2026 emit_int8((unsigned char)(0xC0 | encode));
2027 emit_int8(value & 0xFF);
2028 } else {
2029 emit_int8(0x69);
2030 emit_int8((unsigned char)(0xC0 | encode));
2031 emit_int32(value);
2032 }
2033 }
2034
2035 void Assembler::imull(Register dst, Address src) {
2036 InstructionMark im(this);
2037 prefix(src, dst);
2038 emit_int8(0x0F);
2039 emit_int8((unsigned char) 0xAF);
2040 emit_operand(dst, src);
2041 }
2042
2043
2044 void Assembler::incl(Address dst) {
2045 // Don't use it directly. Use MacroAssembler::increment() instead.
2046 InstructionMark im(this);
2047 prefix(dst);
2048 emit_int8((unsigned char)0xFF);
2049 emit_operand(rax, dst);
2050 }
2051
2052 void Assembler::jcc(Condition cc, Label& L, bool maybe_short) {
2053 InstructionMark im(this);
2054 assert((0 <= cc) && (cc < 16), "illegal cc");
2055 if (L.is_bound()) {
2056 address dst = target(L);
2057 assert(dst != NULL, "jcc most probably wrong");
2058
2059 const int short_size = 2;
2060 const int long_size = 6;
2061 intptr_t offs = (intptr_t)dst - (intptr_t)pc();
2062 if (maybe_short && is8bit(offs - short_size)) {
2063 // 0111 tttn #8-bit disp
2064 emit_int8(0x70 | cc);
2065 emit_int8((offs - short_size) & 0xFF);
2066 } else {
2067 // 0000 1111 1000 tttn #32-bit disp
2068 assert(is_simm32(offs - long_size),
2069 "must be 32bit offset (call4)");
2070 emit_int8(0x0F);
2071 emit_int8((unsigned char)(0x80 | cc));
2072 emit_int32(offs - long_size);
2073 }
2074 } else {
2075 // Note: could eliminate cond. jumps to this jump if condition
2076 // is the same however, seems to be rather unlikely case.
2077 // Note: use jccb() if label to be bound is very close to get
2078 // an 8-bit displacement
2079 L.add_patch_at(code(), locator());
2080 emit_int8(0x0F);
2081 emit_int8((unsigned char)(0x80 | cc));
2082 emit_int32(0);
2083 }
2084 }
2085
2086 void Assembler::jccb(Condition cc, Label& L) {
2087 if (L.is_bound()) {
2088 const int short_size = 2;
2089 address entry = target(L);
2090 #ifdef ASSERT
2091 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2092 intptr_t delta = short_branch_delta();
2093 if (delta != 0) {
2094 dist += (dist < 0 ? (-delta) :delta);
2095 }
2096 assert(is8bit(dist), "Dispacement too large for a short jmp");
2097 #endif
2098 intptr_t offs = (intptr_t)entry - (intptr_t)pc();
2099 // 0111 tttn #8-bit disp
2100 emit_int8(0x70 | cc);
2101 emit_int8((offs - short_size) & 0xFF);
2102 } else {
2103 InstructionMark im(this);
2104 L.add_patch_at(code(), locator());
2105 emit_int8(0x70 | cc);
2106 emit_int8(0);
2107 }
2108 }
2109
2110 void Assembler::jmp(Address adr) {
2111 InstructionMark im(this);
2112 prefix(adr);
2113 emit_int8((unsigned char)0xFF);
2114 emit_operand(rsp, adr);
2115 }
2116
2117 void Assembler::jmp(Label& L, bool maybe_short) {
2118 if (L.is_bound()) {
2119 address entry = target(L);
2120 assert(entry != NULL, "jmp most probably wrong");
2121 InstructionMark im(this);
2122 const int short_size = 2;
2123 const int long_size = 5;
2124 intptr_t offs = entry - pc();
2125 if (maybe_short && is8bit(offs - short_size)) {
2126 emit_int8((unsigned char)0xEB);
2127 emit_int8((offs - short_size) & 0xFF);
2128 } else {
2129 emit_int8((unsigned char)0xE9);
2130 emit_int32(offs - long_size);
2131 }
2132 } else {
2133 // By default, forward jumps are always 32-bit displacements, since
2134 // we can't yet know where the label will be bound. If you're sure that
2135 // the forward jump will not run beyond 256 bytes, use jmpb to
2136 // force an 8-bit displacement.
2137 InstructionMark im(this);
2138 L.add_patch_at(code(), locator());
2139 emit_int8((unsigned char)0xE9);
2140 emit_int32(0);
2141 }
2142 }
2143
2144 void Assembler::jmp(Register entry) {
2145 int encode = prefix_and_encode(entry->encoding());
2146 emit_int8((unsigned char)0xFF);
2147 emit_int8((unsigned char)(0xE0 | encode));
2148 }
2149
2150 void Assembler::jmp_literal(address dest, RelocationHolder const& rspec) {
2151 InstructionMark im(this);
2152 emit_int8((unsigned char)0xE9);
2153 assert(dest != NULL, "must have a target");
2154 intptr_t disp = dest - (pc() + sizeof(int32_t));
2155 assert(is_simm32(disp), "must be 32bit offset (jmp)");
2156 emit_data(disp, rspec.reloc(), call32_operand);
2157 }
2158
2159 void Assembler::jmpb(Label& L) {
2160 if (L.is_bound()) {
2161 const int short_size = 2;
2162 address entry = target(L);
2163 assert(entry != NULL, "jmp most probably wrong");
2164 #ifdef ASSERT
2165 intptr_t dist = (intptr_t)entry - ((intptr_t)pc() + short_size);
2166 intptr_t delta = short_branch_delta();
2167 if (delta != 0) {
2168 dist += (dist < 0 ? (-delta) :delta);
2169 }
2170 assert(is8bit(dist), "Dispacement too large for a short jmp");
2171 #endif
2172 intptr_t offs = entry - pc();
2173 emit_int8((unsigned char)0xEB);
2174 emit_int8((offs - short_size) & 0xFF);
2175 } else {
2176 InstructionMark im(this);
2177 L.add_patch_at(code(), locator());
2178 emit_int8((unsigned char)0xEB);
2179 emit_int8(0);
2180 }
2181 }
2182
2183 void Assembler::ldmxcsr( Address src) {
2184 if (UseAVX > 0 ) {
2185 InstructionMark im(this);
2186 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2187 vex_prefix(src, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2188 emit_int8((unsigned char)0xAE);
2189 emit_operand(as_Register(2), src);
2190 } else {
2191 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2192 InstructionMark im(this);
2193 prefix(src);
2194 emit_int8(0x0F);
2195 emit_int8((unsigned char)0xAE);
2196 emit_operand(as_Register(2), src);
2197 }
2198 }
2199
2200 void Assembler::leal(Register dst, Address src) {
2201 InstructionMark im(this);
2202 #ifdef _LP64
2203 emit_int8(0x67); // addr32
2204 prefix(src, dst);
2205 #endif // LP64
2206 emit_int8((unsigned char)0x8D);
2207 emit_operand(dst, src);
2208 }
2209
2210 void Assembler::lfence() {
2211 emit_int8(0x0F);
2212 emit_int8((unsigned char)0xAE);
2213 emit_int8((unsigned char)0xE8);
2214 }
2215
2216 void Assembler::lock() {
2217 emit_int8((unsigned char)0xF0);
2218 }
2219
2220 void Assembler::lzcntl(Register dst, Register src) {
2221 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
2222 emit_int8((unsigned char)0xF3);
2223 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2224 emit_int8(0x0F);
2225 emit_int8((unsigned char)0xBD);
2226 emit_int8((unsigned char)(0xC0 | encode));
2227 }
2228
2229 // Emit mfence instruction
2230 void Assembler::mfence() {
2231 NOT_LP64(assert(VM_Version::supports_sse2(), "unsupported");)
2232 emit_int8(0x0F);
2233 emit_int8((unsigned char)0xAE);
2234 emit_int8((unsigned char)0xF0);
2235 }
2236
2237 void Assembler::mov(Register dst, Register src) {
2238 LP64_ONLY(movq(dst, src)) NOT_LP64(movl(dst, src));
2239 }
2240
2241 void Assembler::movapd(XMMRegister dst, XMMRegister src) {
2242 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2243 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2244 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2245 attributes.set_rex_vex_w_reverted();
2246 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2247 emit_int8(0x28);
2248 emit_int8((unsigned char)(0xC0 | encode));
2249 }
2250
2251 void Assembler::movaps(XMMRegister dst, XMMRegister src) {
2252 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2253 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2254 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
2255 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2256 emit_int8(0x28);
2257 emit_int8((unsigned char)(0xC0 | encode));
2258 }
2259
2260 void Assembler::movlhps(XMMRegister dst, XMMRegister src) {
2261 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2262 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2263 int encode = simd_prefix_and_encode(dst, src, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2264 emit_int8(0x16);
2265 emit_int8((unsigned char)(0xC0 | encode));
2266 }
2267
2268 void Assembler::movb(Register dst, Address src) {
2269 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
2270 InstructionMark im(this);
2271 prefix(src, dst, true);
2272 emit_int8((unsigned char)0x8A);
2273 emit_operand(dst, src);
2274 }
2275
2276 void Assembler::movddup(XMMRegister dst, XMMRegister src) {
2277 NOT_LP64(assert(VM_Version::supports_sse3(), ""));
2278 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2279 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2280 attributes.set_rex_vex_w_reverted();
2281 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2282 emit_int8(0x12);
2283 emit_int8(0xC0 | encode);
2284 }
2285
2286 void Assembler::kmovbl(KRegister dst, Register src) {
2287 assert(VM_Version::supports_avx512dq(), "");
2288 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2289 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2290 emit_int8((unsigned char)0x92);
2291 emit_int8((unsigned char)(0xC0 | encode));
2292 }
2293
2294 void Assembler::kmovbl(Register dst, KRegister src) {
2295 assert(VM_Version::supports_avx512dq(), "");
2296 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2297 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2298 emit_int8((unsigned char)0x93);
2299 emit_int8((unsigned char)(0xC0 | encode));
2300 }
2301
2302 void Assembler::kmovwl(KRegister dst, Register src) {
2303 assert(VM_Version::supports_evex(), "");
2304 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2305 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2306 emit_int8((unsigned char)0x92);
2307 emit_int8((unsigned char)(0xC0 | encode));
2308 }
2309
2310 void Assembler::kmovwl(Register dst, KRegister src) {
2311 assert(VM_Version::supports_evex(), "");
2312 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2313 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2314 emit_int8((unsigned char)0x93);
2315 emit_int8((unsigned char)(0xC0 | encode));
2316 }
2317
2318 void Assembler::kmovwl(KRegister dst, Address src) {
2319 assert(VM_Version::supports_evex(), "");
2320 InstructionMark im(this);
2321 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2322 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2323 emit_int8((unsigned char)0x90);
2324 emit_operand((Register)dst, src);
2325 }
2326
2327 void Assembler::kmovdl(KRegister dst, Register src) {
2328 assert(VM_Version::supports_avx512bw(), "");
2329 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2330 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2331 emit_int8((unsigned char)0x92);
2332 emit_int8((unsigned char)(0xC0 | encode));
2333 }
2334
2335 void Assembler::kmovdl(Register dst, KRegister src) {
2336 assert(VM_Version::supports_avx512bw(), "");
2337 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2338 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2339 emit_int8((unsigned char)0x93);
2340 emit_int8((unsigned char)(0xC0 | encode));
2341 }
2342
2343 void Assembler::kmovql(KRegister dst, KRegister src) {
2344 assert(VM_Version::supports_avx512bw(), "");
2345 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2346 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2347 emit_int8((unsigned char)0x90);
2348 emit_int8((unsigned char)(0xC0 | encode));
2349 }
2350
2351 void Assembler::kmovql(KRegister dst, Address src) {
2352 assert(VM_Version::supports_avx512bw(), "");
2353 InstructionMark im(this);
2354 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2355 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2356 emit_int8((unsigned char)0x90);
2357 emit_operand((Register)dst, src);
2358 }
2359
2360 void Assembler::kmovql(Address dst, KRegister src) {
2361 assert(VM_Version::supports_avx512bw(), "");
2362 InstructionMark im(this);
2363 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2364 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2365 emit_int8((unsigned char)0x90);
2366 emit_operand((Register)src, dst);
2367 }
2368
2369 void Assembler::kmovql(KRegister dst, Register src) {
2370 assert(VM_Version::supports_avx512bw(), "");
2371 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2372 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2373 emit_int8((unsigned char)0x92);
2374 emit_int8((unsigned char)(0xC0 | encode));
2375 }
2376
2377 void Assembler::kmovql(Register dst, KRegister src) {
2378 assert(VM_Version::supports_avx512bw(), "");
2379 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2380 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2381 emit_int8((unsigned char)0x93);
2382 emit_int8((unsigned char)(0xC0 | encode));
2383 }
2384
2385 void Assembler::knotwl(KRegister dst, KRegister src) {
2386 assert(VM_Version::supports_evex(), "");
2387 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2388 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2389 emit_int8((unsigned char)0x44);
2390 emit_int8((unsigned char)(0xC0 | encode));
2391 }
2392
2393 // This instruction produces ZF or CF flags
2394 void Assembler::kortestbl(KRegister src1, KRegister src2) {
2395 assert(VM_Version::supports_avx512dq(), "");
2396 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2397 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2398 emit_int8((unsigned char)0x98);
2399 emit_int8((unsigned char)(0xC0 | encode));
2400 }
2401
2402 // This instruction produces ZF or CF flags
2403 void Assembler::kortestwl(KRegister src1, KRegister src2) {
2404 assert(VM_Version::supports_evex(), "");
2405 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2406 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2407 emit_int8((unsigned char)0x98);
2408 emit_int8((unsigned char)(0xC0 | encode));
2409 }
2410
2411 // This instruction produces ZF or CF flags
2412 void Assembler::kortestdl(KRegister src1, KRegister src2) {
2413 assert(VM_Version::supports_avx512bw(), "");
2414 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2415 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2416 emit_int8((unsigned char)0x98);
2417 emit_int8((unsigned char)(0xC0 | encode));
2418 }
2419
2420 // This instruction produces ZF or CF flags
2421 void Assembler::kortestql(KRegister src1, KRegister src2) {
2422 assert(VM_Version::supports_avx512bw(), "");
2423 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2424 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2425 emit_int8((unsigned char)0x98);
2426 emit_int8((unsigned char)(0xC0 | encode));
2427 }
2428
2429 // This instruction produces ZF or CF flags
2430 void Assembler::ktestql(KRegister src1, KRegister src2) {
2431 assert(VM_Version::supports_avx512bw(), "");
2432 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2433 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2434 emit_int8((unsigned char)0x99);
2435 emit_int8((unsigned char)(0xC0 | encode));
2436 }
2437
2438 void Assembler::ktestq(KRegister src1, KRegister src2) {
2439 assert(VM_Version::supports_avx512bw(), "");
2440 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2441 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
2442 emit_int8((unsigned char)0x99);
2443 emit_int8((unsigned char)(0xC0 | encode));
2444 }
2445
2446 void Assembler::ktestd(KRegister src1, KRegister src2) {
2447 assert(VM_Version::supports_avx512bw(), "");
2448 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
2449 int encode = vex_prefix_and_encode(src1->encoding(), 0, src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2450 emit_int8((unsigned char)0x99);
2451 emit_int8((unsigned char)(0xC0 | encode));
2452 }
2453
2454 void Assembler::movb(Address dst, int imm8) {
2455 InstructionMark im(this);
2456 prefix(dst);
2457 emit_int8((unsigned char)0xC6);
2458 emit_operand(rax, dst, 1);
2459 emit_int8(imm8);
2460 }
2461
2462
2463 void Assembler::movb(Address dst, Register src) {
2464 assert(src->has_byte_register(), "must have byte register");
2465 InstructionMark im(this);
2466 prefix(dst, src, true);
2467 emit_int8((unsigned char)0x88);
2468 emit_operand(src, dst);
2469 }
2470
2471 void Assembler::movdl(XMMRegister dst, Register src) {
2472 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2473 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2474 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2475 emit_int8(0x6E);
2476 emit_int8((unsigned char)(0xC0 | encode));
2477 }
2478
2479 void Assembler::movdl(Register dst, XMMRegister src) {
2480 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2481 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2482 // swap src/dst to get correct prefix
2483 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2484 emit_int8(0x7E);
2485 emit_int8((unsigned char)(0xC0 | encode));
2486 }
2487
2488 void Assembler::movdl(XMMRegister dst, Address src) {
2489 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2490 InstructionMark im(this);
2491 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2492 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2493 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2494 emit_int8(0x6E);
2495 emit_operand(dst, src);
2496 }
2497
2498 void Assembler::movdl(Address dst, XMMRegister src) {
2499 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2500 InstructionMark im(this);
2501 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2502 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2503 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2504 emit_int8(0x7E);
2505 emit_operand(src, dst);
2506 }
2507
2508 void Assembler::movdqa(XMMRegister dst, XMMRegister src) {
2509 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2510 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
2511 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2512 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2513 emit_int8(0x6F);
2514 emit_int8((unsigned char)(0xC0 | encode));
2515 }
2516
2517 void Assembler::movdqa(XMMRegister dst, Address src) {
2518 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2519 InstructionMark im(this);
2520 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2521 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2522 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2523 emit_int8(0x6F);
2524 emit_operand(dst, src);
2525 }
2526
2527 void Assembler::movdqu(XMMRegister dst, Address src) {
2528 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2529 InstructionMark im(this);
2530 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2531 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2532 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2533 emit_int8(0x6F);
2534 emit_operand(dst, src);
2535 }
2536
2537 void Assembler::movdqu(XMMRegister dst, XMMRegister src) {
2538 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2539 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2540 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2541 emit_int8(0x6F);
2542 emit_int8((unsigned char)(0xC0 | encode));
2543 }
2544
2545 void Assembler::movdqu(Address dst, XMMRegister src) {
2546 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2547 InstructionMark im(this);
2548 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2549 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2550 attributes.reset_is_clear_context();
2551 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2552 emit_int8(0x7F);
2553 emit_operand(src, dst);
2554 }
2555
2556 // Move Unaligned 256bit Vector
2557 void Assembler::vmovdqu(XMMRegister dst, XMMRegister src) {
2558 assert(UseAVX > 0, "");
2559 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2560 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2561 emit_int8(0x6F);
2562 emit_int8((unsigned char)(0xC0 | encode));
2563 }
2564
2565 void Assembler::vmovdqu(XMMRegister dst, Address src) {
2566 assert(UseAVX > 0, "");
2567 InstructionMark im(this);
2568 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2569 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2570 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2571 emit_int8(0x6F);
2572 emit_operand(dst, src);
2573 }
2574
2575 void Assembler::vmovdqu(Address dst, XMMRegister src) {
2576 assert(UseAVX > 0, "");
2577 InstructionMark im(this);
2578 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2579 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2580 attributes.reset_is_clear_context();
2581 // swap src<->dst for encoding
2582 assert(src != xnoreg, "sanity");
2583 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2584 emit_int8(0x7F);
2585 emit_operand(src, dst);
2586 }
2587
2588 // Move Unaligned EVEX enabled Vector (programmable : 8,16,32,64)
2589 void Assembler::evmovdqub(XMMRegister dst, XMMRegister src, bool merge, int vector_len) {
2590 assert(VM_Version::supports_evex(), "");
2591 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2592 attributes.set_is_evex_instruction();
2593 if (merge) {
2594 attributes.reset_is_clear_context();
2595 }
2596 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2597 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2598 emit_int8(0x6F);
2599 emit_int8((unsigned char)(0xC0 | encode));
2600 }
2601
2602 void Assembler::evmovdqub(XMMRegister dst, Address src, bool merge, int vector_len) {
2603 assert(VM_Version::supports_evex(), "");
2604 InstructionMark im(this);
2605 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2606 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2607 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2608 attributes.set_is_evex_instruction();
2609 if (merge) {
2610 attributes.reset_is_clear_context();
2611 }
2612 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2613 emit_int8(0x6F);
2614 emit_operand(dst, src);
2615 }
2616
2617 void Assembler::evmovdqub(Address dst, XMMRegister src, bool merge, int vector_len) {
2618 assert(VM_Version::supports_evex(), "");
2619 assert(src != xnoreg, "sanity");
2620 InstructionMark im(this);
2621 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2622 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2623 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2624 attributes.set_is_evex_instruction();
2625 if (merge) {
2626 attributes.reset_is_clear_context();
2627 }
2628 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2629 emit_int8(0x7F);
2630 emit_operand(src, dst);
2631 }
2632
2633 void Assembler::evmovdqub(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
2634 assert(VM_Version::supports_avx512vlbw(), "");
2635 InstructionMark im(this);
2636 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2637 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2638 attributes.set_embedded_opmask_register_specifier(mask);
2639 attributes.set_is_evex_instruction();
2640 if (merge) {
2641 attributes.reset_is_clear_context();
2642 }
2643 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2644 emit_int8(0x6F);
2645 emit_operand(dst, src);
2646 }
2647
2648 void Assembler::evmovdquw(XMMRegister dst, Address src, bool merge, int vector_len) {
2649 assert(VM_Version::supports_evex(), "");
2650 InstructionMark im(this);
2651 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2652 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2653 attributes.set_is_evex_instruction();
2654 if (merge) {
2655 attributes.reset_is_clear_context();
2656 }
2657 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2658 vex_prefix(src, 0, dst->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2659 emit_int8(0x6F);
2660 emit_operand(dst, src);
2661 }
2662
2663 void Assembler::evmovdquw(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
2664 assert(VM_Version::supports_avx512vlbw(), "");
2665 InstructionMark im(this);
2666 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
2667 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2668 attributes.set_embedded_opmask_register_specifier(mask);
2669 attributes.set_is_evex_instruction();
2670 if (merge) {
2671 attributes.reset_is_clear_context();
2672 }
2673 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2674 emit_int8(0x6F);
2675 emit_operand(dst, src);
2676 }
2677
2678 void Assembler::evmovdquw(Address dst, XMMRegister src, bool merge, int vector_len) {
2679 assert(VM_Version::supports_evex(), "");
2680 assert(src != xnoreg, "sanity");
2681 InstructionMark im(this);
2682 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
2683 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2684 attributes.set_is_evex_instruction();
2685 if (merge) {
2686 attributes.reset_is_clear_context();
2687 }
2688 int prefix = (_legacy_mode_bw) ? VEX_SIMD_F2 : VEX_SIMD_F3;
2689 vex_prefix(dst, 0, src->encoding(), (Assembler::VexSimdPrefix)prefix, VEX_OPCODE_0F, &attributes);
2690 emit_int8(0x7F);
2691 emit_operand(src, dst);
2692 }
2693
2694 void Assembler::evmovdquw(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
2695 assert(VM_Version::supports_avx512vlbw(), "");
2696 assert(src != xnoreg, "sanity");
2697 InstructionMark im(this);
2698 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2699 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2700 attributes.set_embedded_opmask_register_specifier(mask);
2701 attributes.set_is_evex_instruction();
2702 if (merge) {
2703 attributes.reset_is_clear_context();
2704 }
2705 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2706 emit_int8(0x7F);
2707 emit_operand(src, dst);
2708 }
2709
2710 void Assembler::evmovdqul(XMMRegister dst, XMMRegister src, int vector_len) {
2711 // Users of this routine assume k1 usage.
2712 evmovdqul(dst, k1, src, /*merge*/ false, vector_len);
2713 }
2714
2715 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
2716 assert(VM_Version::supports_evex(), "");
2717 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2718 attributes.set_embedded_opmask_register_specifier(mask);
2719 attributes.set_is_evex_instruction();
2720 if (merge) {
2721 attributes.reset_is_clear_context();
2722 }
2723 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2724 emit_int8(0x6F);
2725 emit_int8((unsigned char)(0xC0 | encode));
2726 }
2727
2728 void Assembler::evmovdqul(XMMRegister dst, Address src, int vector_len) {
2729 // Users of this routine assume k1 usage.
2730 evmovdqul(dst, k1, src, /*merge*/ false, vector_len);
2731 }
2732
2733 void Assembler::evmovdqul(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
2734 assert(VM_Version::supports_evex(), "");
2735 InstructionMark im(this);
2736 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false , /* uses_vl */ true);
2737 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2738 attributes.set_embedded_opmask_register_specifier(mask);
2739 attributes.set_is_evex_instruction();
2740 if (merge) {
2741 attributes.reset_is_clear_context();
2742 }
2743 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2744 emit_int8(0x6F);
2745 emit_operand(dst, src);
2746 }
2747
2748 void Assembler::evmovdqul(Address dst, XMMRegister src, int vector_len) {
2749 // Users of this routine assume k1 usage.
2750 evmovdqul(dst, k1, src, /*merge*/ true, vector_len);
2751 }
2752
2753 void Assembler::evmovdqul(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
2754 assert(VM_Version::supports_evex(), "");
2755 assert(src != xnoreg, "sanity");
2756 InstructionMark im(this);
2757 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2758 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2759 attributes.set_embedded_opmask_register_specifier(mask);
2760 attributes.set_is_evex_instruction();
2761 if (merge) {
2762 attributes.reset_is_clear_context();
2763 }
2764 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2765 emit_int8(0x7F);
2766 emit_operand(src, dst);
2767 }
2768
2769 void Assembler::evmovdquq(XMMRegister dst, XMMRegister src, int vector_len) {
2770 // Users of this routine assume k1 usage.
2771 evmovdquq(dst, k1, src, /*merge*/ false, vector_len);
2772 }
2773
2774 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
2775 assert(VM_Version::supports_evex(), "");
2776 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2777 attributes.set_embedded_opmask_register_specifier(mask);
2778 attributes.set_is_evex_instruction();
2779 if (merge) {
2780 attributes.reset_is_clear_context();
2781 }
2782 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2783 emit_int8(0x6F);
2784 emit_int8((unsigned char)(0xC0 | encode));
2785 }
2786
2787 void Assembler::evmovdquq(XMMRegister dst, Address src, int vector_len) {
2788 // Users of this routine assume k1 usage.
2789 evmovdquq(dst, k1, src, /*merge*/ false, vector_len);
2790 }
2791
2792 void Assembler::evmovdquq(XMMRegister dst, KRegister mask, Address src, bool merge, int vector_len) {
2793 assert(VM_Version::supports_evex(), "");
2794 InstructionMark im(this);
2795 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2796 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2797 attributes.set_embedded_opmask_register_specifier(mask);
2798 attributes.set_is_evex_instruction();
2799 if (merge) {
2800 attributes.reset_is_clear_context();
2801 }
2802 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2803 emit_int8(0x6F);
2804 emit_operand(dst, src);
2805 }
2806
2807 void Assembler::evmovdquq(Address dst, XMMRegister src, int vector_len) {
2808 // Users of this routine assume k1 usage.
2809 evmovdquq(dst, k1, src, /*merge*/ true, vector_len);
2810 }
2811
2812 void Assembler::evmovdquq(Address dst, KRegister mask, XMMRegister src, bool merge, int vector_len) {
2813 assert(VM_Version::supports_evex(), "");
2814 assert(src != xnoreg, "sanity");
2815 InstructionMark im(this);
2816 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
2817 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
2818 attributes.set_embedded_opmask_register_specifier(mask);
2819 if (merge) {
2820 attributes.reset_is_clear_context();
2821 }
2822 attributes.set_is_evex_instruction();
2823 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2824 emit_int8(0x7F);
2825 emit_operand(src, dst);
2826 }
2827
2828 // Uses zero extension on 64bit
2829
2830 void Assembler::movl(Register dst, int32_t imm32) {
2831 int encode = prefix_and_encode(dst->encoding());
2832 emit_int8((unsigned char)(0xB8 | encode));
2833 emit_int32(imm32);
2834 }
2835
2836 void Assembler::movl(Register dst, Register src) {
2837 int encode = prefix_and_encode(dst->encoding(), src->encoding());
2838 emit_int8((unsigned char)0x8B);
2839 emit_int8((unsigned char)(0xC0 | encode));
2840 }
2841
2842 void Assembler::movl(Register dst, Address src) {
2843 InstructionMark im(this);
2844 prefix(src, dst);
2845 emit_int8((unsigned char)0x8B);
2846 emit_operand(dst, src);
2847 }
2848
2849 void Assembler::movl(Address dst, int32_t imm32) {
2850 InstructionMark im(this);
2851 prefix(dst);
2852 emit_int8((unsigned char)0xC7);
2853 emit_operand(rax, dst, 4);
2854 emit_int32(imm32);
2855 }
2856
2857 void Assembler::movl(Address dst, Register src) {
2858 InstructionMark im(this);
2859 prefix(dst, src);
2860 emit_int8((unsigned char)0x89);
2861 emit_operand(src, dst);
2862 }
2863
2864 // New cpus require to use movsd and movss to avoid partial register stall
2865 // when loading from memory. But for old Opteron use movlpd instead of movsd.
2866 // The selection is done in MacroAssembler::movdbl() and movflt().
2867 void Assembler::movlpd(XMMRegister dst, Address src) {
2868 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2869 InstructionMark im(this);
2870 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2871 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2872 attributes.set_rex_vex_w_reverted();
2873 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2874 emit_int8(0x12);
2875 emit_operand(dst, src);
2876 }
2877
2878 void Assembler::movq( MMXRegister dst, Address src ) {
2879 assert( VM_Version::supports_mmx(), "" );
2880 emit_int8(0x0F);
2881 emit_int8(0x6F);
2882 emit_operand(dst, src);
2883 }
2884
2885 void Assembler::movq( Address dst, MMXRegister src ) {
2886 assert( VM_Version::supports_mmx(), "" );
2887 emit_int8(0x0F);
2888 emit_int8(0x7F);
2889 // workaround gcc (3.2.1-7a) bug
2890 // In that version of gcc with only an emit_operand(MMX, Address)
2891 // gcc will tail jump and try and reverse the parameters completely
2892 // obliterating dst in the process. By having a version available
2893 // that doesn't need to swap the args at the tail jump the bug is
2894 // avoided.
2895 emit_operand(dst, src);
2896 }
2897
2898 void Assembler::movq(XMMRegister dst, Address src) {
2899 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2900 InstructionMark im(this);
2901 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2902 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2903 attributes.set_rex_vex_w_reverted();
2904 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2905 emit_int8(0x7E);
2906 emit_operand(dst, src);
2907 }
2908
2909 void Assembler::movq(Address dst, XMMRegister src) {
2910 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2911 InstructionMark im(this);
2912 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2913 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2914 attributes.set_rex_vex_w_reverted();
2915 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2916 emit_int8((unsigned char)0xD6);
2917 emit_operand(src, dst);
2918 }
2919
2920 void Assembler::movq(Register dst, XMMRegister src) {
2921 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2922 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2923 // swap src/dst to get correct prefix
2924 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2925 emit_int8(0x7E);
2926 emit_int8((unsigned char)(0xC0 | encode));
2927 }
2928
2929 void Assembler::movq(XMMRegister dst, Register src) {
2930 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2931 InstructionAttr attributes(AVX_128bit, /* rex_w */true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2932 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
2933 emit_int8(0x6E);
2934 emit_int8((unsigned char)(0xC0 | encode));
2935 }
2936
2937 void Assembler::movsbl(Register dst, Address src) { // movsxb
2938 InstructionMark im(this);
2939 prefix(src, dst);
2940 emit_int8(0x0F);
2941 emit_int8((unsigned char)0xBE);
2942 emit_operand(dst, src);
2943 }
2944
2945 void Assembler::movsbl(Register dst, Register src) { // movsxb
2946 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
2947 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
2948 emit_int8(0x0F);
2949 emit_int8((unsigned char)0xBE);
2950 emit_int8((unsigned char)(0xC0 | encode));
2951 }
2952
2953 void Assembler::movsd(XMMRegister dst, XMMRegister src) {
2954 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2955 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2956 attributes.set_rex_vex_w_reverted();
2957 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2958 emit_int8(0x10);
2959 emit_int8((unsigned char)(0xC0 | encode));
2960 }
2961
2962 void Assembler::movsd(XMMRegister dst, Address src) {
2963 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2964 InstructionMark im(this);
2965 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2966 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2967 attributes.set_rex_vex_w_reverted();
2968 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2969 emit_int8(0x10);
2970 emit_operand(dst, src);
2971 }
2972
2973 void Assembler::movsd(Address dst, XMMRegister src) {
2974 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
2975 InstructionMark im(this);
2976 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2977 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
2978 attributes.reset_is_clear_context();
2979 attributes.set_rex_vex_w_reverted();
2980 simd_prefix(src, xnoreg, dst, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
2981 emit_int8(0x11);
2982 emit_operand(src, dst);
2983 }
2984
2985 void Assembler::movss(XMMRegister dst, XMMRegister src) {
2986 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2987 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2988 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2989 emit_int8(0x10);
2990 emit_int8((unsigned char)(0xC0 | encode));
2991 }
2992
2993 void Assembler::movss(XMMRegister dst, Address src) {
2994 NOT_LP64(assert(VM_Version::supports_sse(), ""));
2995 InstructionMark im(this);
2996 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
2997 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
2998 simd_prefix(dst, xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
2999 emit_int8(0x10);
3000 emit_operand(dst, src);
3001 }
3002
3003 void Assembler::movss(Address dst, XMMRegister src) {
3004 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3005 InstructionMark im(this);
3006 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3007 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3008 attributes.reset_is_clear_context();
3009 simd_prefix(src, xnoreg, dst, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3010 emit_int8(0x11);
3011 emit_operand(src, dst);
3012 }
3013
3014 void Assembler::movswl(Register dst, Address src) { // movsxw
3015 InstructionMark im(this);
3016 prefix(src, dst);
3017 emit_int8(0x0F);
3018 emit_int8((unsigned char)0xBF);
3019 emit_operand(dst, src);
3020 }
3021
3022 void Assembler::movswl(Register dst, Register src) { // movsxw
3023 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3024 emit_int8(0x0F);
3025 emit_int8((unsigned char)0xBF);
3026 emit_int8((unsigned char)(0xC0 | encode));
3027 }
3028
3029 void Assembler::movw(Address dst, int imm16) {
3030 InstructionMark im(this);
3031
3032 emit_int8(0x66); // switch to 16-bit mode
3033 prefix(dst);
3034 emit_int8((unsigned char)0xC7);
3035 emit_operand(rax, dst, 2);
3036 emit_int16(imm16);
3037 }
3038
3039 void Assembler::movw(Register dst, Address src) {
3040 InstructionMark im(this);
3041 emit_int8(0x66);
3042 prefix(src, dst);
3043 emit_int8((unsigned char)0x8B);
3044 emit_operand(dst, src);
3045 }
3046
3047 void Assembler::movw(Address dst, Register src) {
3048 InstructionMark im(this);
3049 emit_int8(0x66);
3050 prefix(dst, src);
3051 emit_int8((unsigned char)0x89);
3052 emit_operand(src, dst);
3053 }
3054
3055 void Assembler::movzbl(Register dst, Address src) { // movzxb
3056 InstructionMark im(this);
3057 prefix(src, dst);
3058 emit_int8(0x0F);
3059 emit_int8((unsigned char)0xB6);
3060 emit_operand(dst, src);
3061 }
3062
3063 void Assembler::movzbl(Register dst, Register src) { // movzxb
3064 NOT_LP64(assert(src->has_byte_register(), "must have byte register"));
3065 int encode = prefix_and_encode(dst->encoding(), false, src->encoding(), true);
3066 emit_int8(0x0F);
3067 emit_int8((unsigned char)0xB6);
3068 emit_int8(0xC0 | encode);
3069 }
3070
3071 void Assembler::movzwl(Register dst, Address src) { // movzxw
3072 InstructionMark im(this);
3073 prefix(src, dst);
3074 emit_int8(0x0F);
3075 emit_int8((unsigned char)0xB7);
3076 emit_operand(dst, src);
3077 }
3078
3079 void Assembler::movzwl(Register dst, Register src) { // movzxw
3080 int encode = prefix_and_encode(dst->encoding(), src->encoding());
3081 emit_int8(0x0F);
3082 emit_int8((unsigned char)0xB7);
3083 emit_int8(0xC0 | encode);
3084 }
3085
3086 void Assembler::mull(Address src) {
3087 InstructionMark im(this);
3088 prefix(src);
3089 emit_int8((unsigned char)0xF7);
3090 emit_operand(rsp, src);
3091 }
3092
3093 void Assembler::mull(Register src) {
3094 int encode = prefix_and_encode(src->encoding());
3095 emit_int8((unsigned char)0xF7);
3096 emit_int8((unsigned char)(0xE0 | encode));
3097 }
3098
3099 void Assembler::mulsd(XMMRegister dst, Address src) {
3100 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3101 InstructionMark im(this);
3102 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3103 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3104 attributes.set_rex_vex_w_reverted();
3105 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3106 emit_int8(0x59);
3107 emit_operand(dst, src);
3108 }
3109
3110 void Assembler::mulsd(XMMRegister dst, XMMRegister src) {
3111 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3112 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3113 attributes.set_rex_vex_w_reverted();
3114 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
3115 emit_int8(0x59);
3116 emit_int8((unsigned char)(0xC0 | encode));
3117 }
3118
3119 void Assembler::mulss(XMMRegister dst, Address src) {
3120 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3121 InstructionMark im(this);
3122 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3123 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3124 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3125 emit_int8(0x59);
3126 emit_operand(dst, src);
3127 }
3128
3129 void Assembler::mulss(XMMRegister dst, XMMRegister src) {
3130 NOT_LP64(assert(VM_Version::supports_sse(), ""));
3131 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3132 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
3133 emit_int8(0x59);
3134 emit_int8((unsigned char)(0xC0 | encode));
3135 }
3136
3137 void Assembler::negl(Register dst) {
3138 int encode = prefix_and_encode(dst->encoding());
3139 emit_int8((unsigned char)0xF7);
3140 emit_int8((unsigned char)(0xD8 | encode));
3141 }
3142
3143 void Assembler::nop(int i) {
3144 #ifdef ASSERT
3145 assert(i > 0, " ");
3146 // The fancy nops aren't currently recognized by debuggers making it a
3147 // pain to disassemble code while debugging. If asserts are on clearly
3148 // speed is not an issue so simply use the single byte traditional nop
3149 // to do alignment.
3150
3151 for (; i > 0 ; i--) emit_int8((unsigned char)0x90);
3152 return;
3153
3154 #endif // ASSERT
3155
3156 if (UseAddressNop && VM_Version::is_intel()) {
3157 //
3158 // Using multi-bytes nops "0x0F 0x1F [address]" for Intel
3159 // 1: 0x90
3160 // 2: 0x66 0x90
3161 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3162 // 4: 0x0F 0x1F 0x40 0x00
3163 // 5: 0x0F 0x1F 0x44 0x00 0x00
3164 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3165 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3166 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3167 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3168 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3169 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3170
3171 // The rest coding is Intel specific - don't use consecutive address nops
3172
3173 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3174 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3175 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3176 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3177
3178 while(i >= 15) {
3179 // For Intel don't generate consecutive addess nops (mix with regular nops)
3180 i -= 15;
3181 emit_int8(0x66); // size prefix
3182 emit_int8(0x66); // size prefix
3183 emit_int8(0x66); // size prefix
3184 addr_nop_8();
3185 emit_int8(0x66); // size prefix
3186 emit_int8(0x66); // size prefix
3187 emit_int8(0x66); // size prefix
3188 emit_int8((unsigned char)0x90);
3189 // nop
3190 }
3191 switch (i) {
3192 case 14:
3193 emit_int8(0x66); // size prefix
3194 case 13:
3195 emit_int8(0x66); // size prefix
3196 case 12:
3197 addr_nop_8();
3198 emit_int8(0x66); // size prefix
3199 emit_int8(0x66); // size prefix
3200 emit_int8(0x66); // size prefix
3201 emit_int8((unsigned char)0x90);
3202 // nop
3203 break;
3204 case 11:
3205 emit_int8(0x66); // size prefix
3206 case 10:
3207 emit_int8(0x66); // size prefix
3208 case 9:
3209 emit_int8(0x66); // size prefix
3210 case 8:
3211 addr_nop_8();
3212 break;
3213 case 7:
3214 addr_nop_7();
3215 break;
3216 case 6:
3217 emit_int8(0x66); // size prefix
3218 case 5:
3219 addr_nop_5();
3220 break;
3221 case 4:
3222 addr_nop_4();
3223 break;
3224 case 3:
3225 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3226 emit_int8(0x66); // size prefix
3227 case 2:
3228 emit_int8(0x66); // size prefix
3229 case 1:
3230 emit_int8((unsigned char)0x90);
3231 // nop
3232 break;
3233 default:
3234 assert(i == 0, " ");
3235 }
3236 return;
3237 }
3238 if (UseAddressNop && VM_Version::is_amd()) {
3239 //
3240 // Using multi-bytes nops "0x0F 0x1F [address]" for AMD.
3241 // 1: 0x90
3242 // 2: 0x66 0x90
3243 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3244 // 4: 0x0F 0x1F 0x40 0x00
3245 // 5: 0x0F 0x1F 0x44 0x00 0x00
3246 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3247 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3248 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3249 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3250 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3251 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3252
3253 // The rest coding is AMD specific - use consecutive address nops
3254
3255 // 12: 0x66 0x0F 0x1F 0x44 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3256 // 13: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x66 0x0F 0x1F 0x44 0x00 0x00
3257 // 14: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3258 // 15: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3259 // 16: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3260 // Size prefixes (0x66) are added for larger sizes
3261
3262 while(i >= 22) {
3263 i -= 11;
3264 emit_int8(0x66); // size prefix
3265 emit_int8(0x66); // size prefix
3266 emit_int8(0x66); // size prefix
3267 addr_nop_8();
3268 }
3269 // Generate first nop for size between 21-12
3270 switch (i) {
3271 case 21:
3272 i -= 1;
3273 emit_int8(0x66); // size prefix
3274 case 20:
3275 case 19:
3276 i -= 1;
3277 emit_int8(0x66); // size prefix
3278 case 18:
3279 case 17:
3280 i -= 1;
3281 emit_int8(0x66); // size prefix
3282 case 16:
3283 case 15:
3284 i -= 8;
3285 addr_nop_8();
3286 break;
3287 case 14:
3288 case 13:
3289 i -= 7;
3290 addr_nop_7();
3291 break;
3292 case 12:
3293 i -= 6;
3294 emit_int8(0x66); // size prefix
3295 addr_nop_5();
3296 break;
3297 default:
3298 assert(i < 12, " ");
3299 }
3300
3301 // Generate second nop for size between 11-1
3302 switch (i) {
3303 case 11:
3304 emit_int8(0x66); // size prefix
3305 case 10:
3306 emit_int8(0x66); // size prefix
3307 case 9:
3308 emit_int8(0x66); // size prefix
3309 case 8:
3310 addr_nop_8();
3311 break;
3312 case 7:
3313 addr_nop_7();
3314 break;
3315 case 6:
3316 emit_int8(0x66); // size prefix
3317 case 5:
3318 addr_nop_5();
3319 break;
3320 case 4:
3321 addr_nop_4();
3322 break;
3323 case 3:
3324 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3325 emit_int8(0x66); // size prefix
3326 case 2:
3327 emit_int8(0x66); // size prefix
3328 case 1:
3329 emit_int8((unsigned char)0x90);
3330 // nop
3331 break;
3332 default:
3333 assert(i == 0, " ");
3334 }
3335 return;
3336 }
3337
3338 if (UseAddressNop && VM_Version::is_zx()) {
3339 //
3340 // Using multi-bytes nops "0x0F 0x1F [address]" for ZX
3341 // 1: 0x90
3342 // 2: 0x66 0x90
3343 // 3: 0x66 0x66 0x90 (don't use "0x0F 0x1F 0x00" - need patching safe padding)
3344 // 4: 0x0F 0x1F 0x40 0x00
3345 // 5: 0x0F 0x1F 0x44 0x00 0x00
3346 // 6: 0x66 0x0F 0x1F 0x44 0x00 0x00
3347 // 7: 0x0F 0x1F 0x80 0x00 0x00 0x00 0x00
3348 // 8: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3349 // 9: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3350 // 10: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3351 // 11: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00
3352
3353 // The rest coding is ZX specific - don't use consecutive address nops
3354
3355 // 12: 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3356 // 13: 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3357 // 14: 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3358 // 15: 0x66 0x66 0x66 0x0F 0x1F 0x84 0x00 0x00 0x00 0x00 0x00 0x66 0x66 0x66 0x90
3359
3360 while (i >= 15) {
3361 // For ZX don't generate consecutive addess nops (mix with regular nops)
3362 i -= 15;
3363 emit_int8(0x66); // size prefix
3364 emit_int8(0x66); // size prefix
3365 emit_int8(0x66); // size prefix
3366 addr_nop_8();
3367 emit_int8(0x66); // size prefix
3368 emit_int8(0x66); // size prefix
3369 emit_int8(0x66); // size prefix
3370 emit_int8((unsigned char)0x90);
3371 // nop
3372 }
3373 switch (i) {
3374 case 14:
3375 emit_int8(0x66); // size prefix
3376 case 13:
3377 emit_int8(0x66); // size prefix
3378 case 12:
3379 addr_nop_8();
3380 emit_int8(0x66); // size prefix
3381 emit_int8(0x66); // size prefix
3382 emit_int8(0x66); // size prefix
3383 emit_int8((unsigned char)0x90);
3384 // nop
3385 break;
3386 case 11:
3387 emit_int8(0x66); // size prefix
3388 case 10:
3389 emit_int8(0x66); // size prefix
3390 case 9:
3391 emit_int8(0x66); // size prefix
3392 case 8:
3393 addr_nop_8();
3394 break;
3395 case 7:
3396 addr_nop_7();
3397 break;
3398 case 6:
3399 emit_int8(0x66); // size prefix
3400 case 5:
3401 addr_nop_5();
3402 break;
3403 case 4:
3404 addr_nop_4();
3405 break;
3406 case 3:
3407 // Don't use "0x0F 0x1F 0x00" - need patching safe padding
3408 emit_int8(0x66); // size prefix
3409 case 2:
3410 emit_int8(0x66); // size prefix
3411 case 1:
3412 emit_int8((unsigned char)0x90);
3413 // nop
3414 break;
3415 default:
3416 assert(i == 0, " ");
3417 }
3418 return;
3419 }
3420
3421 // Using nops with size prefixes "0x66 0x90".
3422 // From AMD Optimization Guide:
3423 // 1: 0x90
3424 // 2: 0x66 0x90
3425 // 3: 0x66 0x66 0x90
3426 // 4: 0x66 0x66 0x66 0x90
3427 // 5: 0x66 0x66 0x90 0x66 0x90
3428 // 6: 0x66 0x66 0x90 0x66 0x66 0x90
3429 // 7: 0x66 0x66 0x66 0x90 0x66 0x66 0x90
3430 // 8: 0x66 0x66 0x66 0x90 0x66 0x66 0x66 0x90
3431 // 9: 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3432 // 10: 0x66 0x66 0x66 0x90 0x66 0x66 0x90 0x66 0x66 0x90
3433 //
3434 while(i > 12) {
3435 i -= 4;
3436 emit_int8(0x66); // size prefix
3437 emit_int8(0x66);
3438 emit_int8(0x66);
3439 emit_int8((unsigned char)0x90);
3440 // nop
3441 }
3442 // 1 - 12 nops
3443 if(i > 8) {
3444 if(i > 9) {
3445 i -= 1;
3446 emit_int8(0x66);
3447 }
3448 i -= 3;
3449 emit_int8(0x66);
3450 emit_int8(0x66);
3451 emit_int8((unsigned char)0x90);
3452 }
3453 // 1 - 8 nops
3454 if(i > 4) {
3455 if(i > 6) {
3456 i -= 1;
3457 emit_int8(0x66);
3458 }
3459 i -= 3;
3460 emit_int8(0x66);
3461 emit_int8(0x66);
3462 emit_int8((unsigned char)0x90);
3463 }
3464 switch (i) {
3465 case 4:
3466 emit_int8(0x66);
3467 case 3:
3468 emit_int8(0x66);
3469 case 2:
3470 emit_int8(0x66);
3471 case 1:
3472 emit_int8((unsigned char)0x90);
3473 break;
3474 default:
3475 assert(i == 0, " ");
3476 }
3477 }
3478
3479 void Assembler::notl(Register dst) {
3480 int encode = prefix_and_encode(dst->encoding());
3481 emit_int8((unsigned char)0xF7);
3482 emit_int8((unsigned char)(0xD0 | encode));
3483 }
3484
3485 void Assembler::orl(Address dst, int32_t imm32) {
3486 InstructionMark im(this);
3487 prefix(dst);
3488 emit_arith_operand(0x81, rcx, dst, imm32);
3489 }
3490
3491 void Assembler::orl(Register dst, int32_t imm32) {
3492 prefix(dst);
3493 emit_arith(0x81, 0xC8, dst, imm32);
3494 }
3495
3496 void Assembler::orl(Register dst, Address src) {
3497 InstructionMark im(this);
3498 prefix(src, dst);
3499 emit_int8(0x0B);
3500 emit_operand(dst, src);
3501 }
3502
3503 void Assembler::orl(Register dst, Register src) {
3504 (void) prefix_and_encode(dst->encoding(), src->encoding());
3505 emit_arith(0x0B, 0xC0, dst, src);
3506 }
3507
3508 void Assembler::orl(Address dst, Register src) {
3509 InstructionMark im(this);
3510 prefix(dst, src);
3511 emit_int8(0x09);
3512 emit_operand(src, dst);
3513 }
3514
3515 void Assembler::packuswb(XMMRegister dst, Address src) {
3516 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3517 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
3518 InstructionMark im(this);
3519 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3520 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3521 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3522 emit_int8(0x67);
3523 emit_operand(dst, src);
3524 }
3525
3526 void Assembler::packuswb(XMMRegister dst, XMMRegister src) {
3527 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
3528 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3529 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3530 emit_int8(0x67);
3531 emit_int8((unsigned char)(0xC0 | encode));
3532 }
3533
3534 void Assembler::vpackuswb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3535 assert(UseAVX > 0, "some form of AVX must be enabled");
3536 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3537 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3538 emit_int8(0x67);
3539 emit_int8((unsigned char)(0xC0 | encode));
3540 }
3541
3542 void Assembler::vpackusdw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3543 assert(UseAVX > 0, "some form of AVX must be enabled");
3544 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
3545 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3546 emit_int8(0x2B);
3547 emit_int8((unsigned char)(0xC0 | encode));
3548 }
3549
3550 void Assembler::vpermq(XMMRegister dst, XMMRegister src, int imm8, int vector_len) {
3551 assert(VM_Version::supports_avx2(), "");
3552 // VEX.256.66.0F3A.W1 00 /r ib
3553 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3554 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3555 emit_int8(0x00);
3556 emit_int8(0xC0 | encode);
3557 emit_int8(imm8);
3558 }
3559
3560 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
3561 assert(VM_Version::supports_avx2(), "");
3562 // VEX.NDS.256.66.0F38.W0 36 /r
3563 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3564 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3565 emit_int8(0x36);
3566 emit_int8(0xC0 | encode);
3567 }
3568
3569 void Assembler::vpermd(XMMRegister dst, XMMRegister nds, Address src) {
3570 assert(VM_Version::supports_avx2(), "");
3571 // VEX.NDS.256.66.0F38.W0 36 /r
3572 InstructionMark im(this);
3573 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3574 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3575 emit_int8(0x36);
3576 emit_operand(dst, src);
3577 }
3578
3579 void Assembler::vperm2i128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3580 assert(VM_Version::supports_avx2(), "");
3581 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3582 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3583 emit_int8(0x46);
3584 emit_int8(0xC0 | encode);
3585 emit_int8(imm8);
3586 }
3587
3588 void Assembler::vperm2f128(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8) {
3589 assert(VM_Version::supports_avx(), "");
3590 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3591 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3592 emit_int8(0x06);
3593 emit_int8(0xC0 | encode);
3594 emit_int8(imm8);
3595 }
3596
3597
3598 void Assembler::pause() {
3599 emit_int8((unsigned char)0xF3);
3600 emit_int8((unsigned char)0x90);
3601 }
3602
3603 void Assembler::ud2() {
3604 emit_int8(0x0F);
3605 emit_int8(0x0B);
3606 }
3607
3608 void Assembler::pcmpestri(XMMRegister dst, Address src, int imm8) {
3609 assert(VM_Version::supports_sse4_2(), "");
3610 InstructionMark im(this);
3611 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3612 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3613 emit_int8(0x61);
3614 emit_operand(dst, src);
3615 emit_int8(imm8);
3616 }
3617
3618 void Assembler::pcmpestri(XMMRegister dst, XMMRegister src, int imm8) {
3619 assert(VM_Version::supports_sse4_2(), "");
3620 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3621 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3622 emit_int8(0x61);
3623 emit_int8((unsigned char)(0xC0 | encode));
3624 emit_int8(imm8);
3625 }
3626
3627 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3628 void Assembler::pcmpeqb(XMMRegister dst, XMMRegister src) {
3629 assert(VM_Version::supports_sse2(), "");
3630 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3631 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3632 emit_int8(0x74);
3633 emit_int8((unsigned char)(0xC0 | encode));
3634 }
3635
3636 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3637 void Assembler::vpcmpeqb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3638 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
3639 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
3640 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3641 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3642 emit_int8(0x74);
3643 emit_int8((unsigned char)(0xC0 | encode));
3644 }
3645
3646 // In this context, kdst is written the mask used to process the equal components
3647 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3648 assert(VM_Version::supports_avx512bw(), "");
3649 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3650 attributes.set_is_evex_instruction();
3651 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3652 emit_int8(0x74);
3653 emit_int8((unsigned char)(0xC0 | encode));
3654 }
3655
3656 void Assembler::evpcmpgtb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3657 assert(VM_Version::supports_avx512vlbw(), "");
3658 InstructionMark im(this);
3659 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3660 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3661 attributes.set_is_evex_instruction();
3662 int dst_enc = kdst->encoding();
3663 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3664 emit_int8(0x64);
3665 emit_operand(as_Register(dst_enc), src);
3666 }
3667
3668 void Assembler::evpcmpgtb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3669 assert(is_vector_masking(), "");
3670 assert(VM_Version::supports_avx512vlbw(), "");
3671 InstructionMark im(this);
3672 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3673 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3674 attributes.reset_is_clear_context();
3675 attributes.set_embedded_opmask_register_specifier(mask);
3676 attributes.set_is_evex_instruction();
3677 int dst_enc = kdst->encoding();
3678 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3679 emit_int8(0x64);
3680 emit_operand(as_Register(dst_enc), src);
3681 }
3682
3683 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3684 assert(VM_Version::supports_avx512vlbw(), "");
3685 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3686 attributes.set_is_evex_instruction();
3687 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3688 emit_int8(0x3E);
3689 emit_int8((unsigned char)(0xC0 | encode));
3690 emit_int8(vcc);
3691 }
3692
3693 void Assembler::evpcmpuw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, ComparisonPredicate vcc, int vector_len) {
3694 assert(is_vector_masking(), "");
3695 assert(VM_Version::supports_avx512vlbw(), "");
3696 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
3697 attributes.reset_is_clear_context();
3698 attributes.set_embedded_opmask_register_specifier(mask);
3699 attributes.set_is_evex_instruction();
3700 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3701 emit_int8(0x3E);
3702 emit_int8((unsigned char)(0xC0 | encode));
3703 emit_int8(vcc);
3704 }
3705
3706 void Assembler::evpcmpuw(KRegister kdst, XMMRegister nds, Address src, ComparisonPredicate vcc, int vector_len) {
3707 assert(VM_Version::supports_avx512vlbw(), "");
3708 InstructionMark im(this);
3709 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3710 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3711 attributes.set_is_evex_instruction();
3712 int dst_enc = kdst->encoding();
3713 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3714 emit_int8(0x3E);
3715 emit_operand(as_Register(dst_enc), src);
3716 emit_int8(vcc);
3717 }
3718
3719 void Assembler::evpcmpeqb(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3720 assert(VM_Version::supports_avx512bw(), "");
3721 InstructionMark im(this);
3722 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
3723 attributes.set_is_evex_instruction();
3724 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3725 int dst_enc = kdst->encoding();
3726 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3727 emit_int8(0x74);
3728 emit_operand(as_Register(dst_enc), src);
3729 }
3730
3731 void Assembler::evpcmpeqb(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3732 assert(VM_Version::supports_avx512vlbw(), "");
3733 assert(is_vector_masking(), ""); // For stub code use only
3734 InstructionMark im(this);
3735 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_reg_mask */ false, /* uses_vl */ false);
3736 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3737 attributes.reset_is_clear_context();
3738 attributes.set_embedded_opmask_register_specifier(mask);
3739 attributes.set_is_evex_instruction();
3740 vex_prefix(src, nds->encoding(), kdst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3741 emit_int8(0x74);
3742 emit_operand(as_Register(kdst->encoding()), src);
3743 }
3744
3745 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3746 void Assembler::pcmpeqw(XMMRegister dst, XMMRegister src) {
3747 assert(VM_Version::supports_sse2(), "");
3748 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3749 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3750 emit_int8(0x75);
3751 emit_int8((unsigned char)(0xC0 | encode));
3752 }
3753
3754 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3755 void Assembler::vpcmpeqw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3756 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
3757 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
3758 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3759 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3760 emit_int8(0x75);
3761 emit_int8((unsigned char)(0xC0 | encode));
3762 }
3763
3764 // In this context, kdst is written the mask used to process the equal components
3765 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3766 assert(VM_Version::supports_avx512bw(), "");
3767 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3768 attributes.set_is_evex_instruction();
3769 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3770 emit_int8(0x75);
3771 emit_int8((unsigned char)(0xC0 | encode));
3772 }
3773
3774 void Assembler::evpcmpeqw(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3775 assert(VM_Version::supports_avx512bw(), "");
3776 InstructionMark im(this);
3777 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ true);
3778 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
3779 attributes.set_is_evex_instruction();
3780 int dst_enc = kdst->encoding();
3781 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3782 emit_int8(0x75);
3783 emit_operand(as_Register(dst_enc), src);
3784 }
3785
3786 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3787 void Assembler::pcmpeqd(XMMRegister dst, XMMRegister src) {
3788 assert(VM_Version::supports_sse2(), "");
3789 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3790 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3791 emit_int8(0x76);
3792 emit_int8((unsigned char)(0xC0 | encode));
3793 }
3794
3795 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3796 void Assembler::vpcmpeqd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3797 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
3798 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
3799 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
3800 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3801 emit_int8((unsigned char)0x76);
3802 emit_int8((unsigned char)(0xC0 | encode));
3803 }
3804
3805 // In this context, kdst is written the mask used to process the equal components
3806 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src, int vector_len) {
3807 assert(VM_Version::supports_evex(), "");
3808 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3809 attributes.set_is_evex_instruction();
3810 attributes.reset_is_clear_context();
3811 attributes.set_embedded_opmask_register_specifier(mask);
3812 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3813 emit_int8(0x76);
3814 emit_int8((unsigned char)(0xC0 | encode));
3815 }
3816
3817 void Assembler::evpcmpeqd(KRegister kdst, KRegister mask, XMMRegister nds, Address src, int vector_len) {
3818 assert(VM_Version::supports_evex(), "");
3819 InstructionMark im(this);
3820 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3821 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
3822 attributes.set_is_evex_instruction();
3823 attributes.reset_is_clear_context();
3824 attributes.set_embedded_opmask_register_specifier(mask);
3825 int dst_enc = kdst->encoding();
3826 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3827 emit_int8(0x76);
3828 emit_operand(as_Register(dst_enc), src);
3829 }
3830
3831 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3832 void Assembler::pcmpeqq(XMMRegister dst, XMMRegister src) {
3833 assert(VM_Version::supports_sse4_1(), "");
3834 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3835 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3836 emit_int8(0x29);
3837 emit_int8((unsigned char)(0xC0 | encode));
3838 }
3839
3840 // In this context, the dst vector contains the components that are equal, non equal components are zeroed in dst
3841 void Assembler::vpcmpeqq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
3842 assert(VM_Version::supports_avx(), "");
3843 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3844 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3845 emit_int8(0x29);
3846 emit_int8((unsigned char)(0xC0 | encode));
3847 }
3848
3849 // In this context, kdst is written the mask used to process the equal components
3850 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, XMMRegister src, int vector_len) {
3851 assert(VM_Version::supports_evex(), "");
3852 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3853 attributes.reset_is_clear_context();
3854 attributes.set_is_evex_instruction();
3855 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3856 emit_int8(0x29);
3857 emit_int8((unsigned char)(0xC0 | encode));
3858 }
3859
3860 // In this context, kdst is written the mask used to process the equal components
3861 void Assembler::evpcmpeqq(KRegister kdst, XMMRegister nds, Address src, int vector_len) {
3862 assert(VM_Version::supports_evex(), "");
3863 InstructionMark im(this);
3864 InstructionAttr attributes(vector_len, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
3865 attributes.reset_is_clear_context();
3866 attributes.set_is_evex_instruction();
3867 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
3868 int dst_enc = kdst->encoding();
3869 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3870 emit_int8(0x29);
3871 emit_operand(as_Register(dst_enc), src);
3872 }
3873
3874 void Assembler::pcmpgtq(XMMRegister dst, XMMRegister src) {
3875 assert(VM_Version::supports_sse4_1(), "");
3876 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3877 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
3878 emit_int8(0x37);
3879 emit_int8((unsigned char)(0xC0 | encode));
3880 }
3881
3882 void Assembler::pmovmskb(Register dst, XMMRegister src) {
3883 assert(VM_Version::supports_sse2(), "");
3884 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3885 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3886 emit_int8((unsigned char)0xD7);
3887 emit_int8((unsigned char)(0xC0 | encode));
3888 }
3889
3890 void Assembler::vpmovmskb(Register dst, XMMRegister src) {
3891 assert(VM_Version::supports_avx2(), "");
3892 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
3893 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3894 emit_int8((unsigned char)0xD7);
3895 emit_int8((unsigned char)(0xC0 | encode));
3896 }
3897
3898 void Assembler::pextrd(Register dst, XMMRegister src, int imm8) {
3899 assert(VM_Version::supports_sse4_1(), "");
3900 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3901 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3902 emit_int8(0x16);
3903 emit_int8((unsigned char)(0xC0 | encode));
3904 emit_int8(imm8);
3905 }
3906
3907 void Assembler::pextrd(Address dst, XMMRegister src, int imm8) {
3908 assert(VM_Version::supports_sse4_1(), "");
3909 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3910 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3911 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3912 emit_int8(0x16);
3913 emit_operand(src, dst);
3914 emit_int8(imm8);
3915 }
3916
3917 void Assembler::pextrq(Register dst, XMMRegister src, int imm8) {
3918 assert(VM_Version::supports_sse4_1(), "");
3919 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3920 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3921 emit_int8(0x16);
3922 emit_int8((unsigned char)(0xC0 | encode));
3923 emit_int8(imm8);
3924 }
3925
3926 void Assembler::pextrq(Address dst, XMMRegister src, int imm8) {
3927 assert(VM_Version::supports_sse4_1(), "");
3928 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3929 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
3930 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3931 emit_int8(0x16);
3932 emit_operand(src, dst);
3933 emit_int8(imm8);
3934 }
3935
3936 void Assembler::pextrw(Register dst, XMMRegister src, int imm8) {
3937 assert(VM_Version::supports_sse2(), "");
3938 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3939 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
3940 emit_int8((unsigned char)0xC5);
3941 emit_int8((unsigned char)(0xC0 | encode));
3942 emit_int8(imm8);
3943 }
3944
3945 void Assembler::pextrw(Address dst, XMMRegister src, int imm8) {
3946 assert(VM_Version::supports_sse4_1(), "");
3947 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3948 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
3949 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3950 emit_int8((unsigned char)0x15);
3951 emit_operand(src, dst);
3952 emit_int8(imm8);
3953 }
3954
3955 void Assembler::pextrb(Register dst, XMMRegister src, int imm8) {
3956 assert(VM_Version::supports_sse4_1(), "");
3957 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3958 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3959 emit_int8(0x14);
3960 emit_int8((unsigned char)(0xC0 | encode));
3961 emit_int8(imm8);
3962 }
3963
3964 void Assembler::pextrb(Address dst, XMMRegister src, int imm8) {
3965 assert(VM_Version::supports_sse4_1(), "");
3966 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
3967 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
3968 simd_prefix(src, xnoreg, dst, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3969 emit_int8(0x14);
3970 emit_operand(src, dst);
3971 emit_int8(imm8);
3972 }
3973
3974 void Assembler::pinsrd(XMMRegister dst, Register src, int imm8) {
3975 assert(VM_Version::supports_sse4_1(), "");
3976 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3977 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3978 emit_int8(0x22);
3979 emit_int8((unsigned char)(0xC0 | encode));
3980 emit_int8(imm8);
3981 }
3982
3983 void Assembler::pinsrd(XMMRegister dst, Address src, int imm8) {
3984 assert(VM_Version::supports_sse4_1(), "");
3985 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3986 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
3987 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3988 emit_int8(0x22);
3989 emit_operand(dst,src);
3990 emit_int8(imm8);
3991 }
3992
3993 void Assembler::pinsrq(XMMRegister dst, Register src, int imm8) {
3994 assert(VM_Version::supports_sse4_1(), "");
3995 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
3996 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
3997 emit_int8(0x22);
3998 emit_int8((unsigned char)(0xC0 | encode));
3999 emit_int8(imm8);
4000 }
4001
4002 void Assembler::pinsrq(XMMRegister dst, Address src, int imm8) {
4003 assert(VM_Version::supports_sse4_1(), "");
4004 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ true, /* uses_vl */ false);
4005 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4006 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4007 emit_int8(0x22);
4008 emit_operand(dst, src);
4009 emit_int8(imm8);
4010 }
4011
4012 void Assembler::pinsrw(XMMRegister dst, Register src, int imm8) {
4013 assert(VM_Version::supports_sse2(), "");
4014 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4015 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4016 emit_int8((unsigned char)0xC4);
4017 emit_int8((unsigned char)(0xC0 | encode));
4018 emit_int8(imm8);
4019 }
4020
4021 void Assembler::pinsrw(XMMRegister dst, Address src, int imm8) {
4022 assert(VM_Version::supports_sse2(), "");
4023 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4024 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
4025 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4026 emit_int8((unsigned char)0xC4);
4027 emit_operand(dst, src);
4028 emit_int8(imm8);
4029 }
4030
4031 void Assembler::pinsrb(XMMRegister dst, Address src, int imm8) {
4032 assert(VM_Version::supports_sse4_1(), "");
4033 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4034 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
4035 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4036 emit_int8(0x20);
4037 emit_operand(dst, src);
4038 emit_int8(imm8);
4039 }
4040
4041 void Assembler::pmovzxbw(XMMRegister dst, Address src) {
4042 assert(VM_Version::supports_sse4_1(), "");
4043 InstructionMark im(this);
4044 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4045 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4046 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4047 emit_int8(0x30);
4048 emit_operand(dst, src);
4049 }
4050
4051 void Assembler::pmovzxbw(XMMRegister dst, XMMRegister src) {
4052 assert(VM_Version::supports_sse4_1(), "");
4053 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4054 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4055 emit_int8(0x30);
4056 emit_int8((unsigned char)(0xC0 | encode));
4057 }
4058
4059 void Assembler::pmovzxdq(XMMRegister dst, XMMRegister src) {
4060 assert(VM_Version::supports_sse4_1(), "");
4061 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4062 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4063 emit_int8(0x35);
4064 emit_int8((unsigned char)(0xC0 | encode));
4065 }
4066
4067 void Assembler::pmovsxbw(XMMRegister dst, XMMRegister src) {
4068 assert(VM_Version::supports_sse4_1(), "");
4069 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4070 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4071 emit_int8(0x20);
4072 emit_int8((unsigned char)(0xC0 | encode));
4073 }
4074
4075 void Assembler::pmovsxbd(XMMRegister dst, XMMRegister src) {
4076 assert(VM_Version::supports_sse4_1(), "");
4077 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4078 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4079 emit_int8(0x21);
4080 emit_int8((unsigned char)(0xC0 | encode));
4081 }
4082
4083 void Assembler::pmovsxbq(XMMRegister dst, XMMRegister src) {
4084 assert(VM_Version::supports_sse4_1(), "");
4085 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4086 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4087 emit_int8(0x22);
4088 emit_int8((unsigned char)(0xC0 | encode));
4089 }
4090
4091 void Assembler::vpmovzxbw(XMMRegister dst, Address src, int vector_len) {
4092 assert(VM_Version::supports_avx(), "");
4093 InstructionMark im(this);
4094 assert(dst != xnoreg, "sanity");
4095 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4096 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4097 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4098 emit_int8(0x30);
4099 emit_operand(dst, src);
4100 }
4101
4102 void Assembler::evpmovzxbw(XMMRegister dst, KRegister mask, Address src, int vector_len) {
4103 assert(is_vector_masking(), "");
4104 assert(VM_Version::supports_avx512vlbw(), "");
4105 assert(dst != xnoreg, "sanity");
4106 InstructionMark im(this);
4107 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4108 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4109 attributes.set_embedded_opmask_register_specifier(mask);
4110 attributes.set_is_evex_instruction();
4111 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4112 emit_int8(0x30);
4113 emit_operand(dst, src);
4114 }
4115
4116 void Assembler::vpmovzxdq(XMMRegister dst, XMMRegister src, int vector_len) {
4117 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4118 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4119 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4120 emit_int8(0x35);
4121 emit_int8((unsigned char)(0xC0 | encode));
4122 }
4123
4124 void Assembler::vpmovzxbd(XMMRegister dst, XMMRegister src, int vector_len) {
4125 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4126 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4127 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4128 emit_int8(0x31);
4129 emit_int8((unsigned char)(0xC0 | encode));
4130 }
4131
4132 void Assembler::vpmovzxbq(XMMRegister dst, XMMRegister src, int vector_len) {
4133 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4134 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4135 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4136 emit_int8(0x32);
4137 emit_int8((unsigned char)(0xC0 | encode));
4138 }
4139
4140 void Assembler::vpmovsxbd(XMMRegister dst, XMMRegister src, int vector_len) {
4141 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4142 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4143 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4144 emit_int8(0x21);
4145 emit_int8((unsigned char)(0xC0 | encode));
4146 }
4147
4148 void Assembler::vpmovsxbq(XMMRegister dst, XMMRegister src, int vector_len) {
4149 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4150 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4151 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4152 emit_int8(0x22);
4153 emit_int8((unsigned char)(0xC0 | encode));
4154 }
4155
4156 void Assembler::vpmovsxbw(XMMRegister dst, XMMRegister src, int vector_len) {
4157 assert(vector_len > AVX_128bit ? VM_Version::supports_avx2() : VM_Version::supports_avx(), "");
4158 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4159 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4160 emit_int8(0x20);
4161 emit_int8((unsigned char)(0xC0 | encode));
4162 }
4163
4164 void Assembler::evpmovwb(Address dst, XMMRegister src, int vector_len) {
4165 assert(VM_Version::supports_avx512vlbw(), "");
4166 assert(src != xnoreg, "sanity");
4167 InstructionMark im(this);
4168 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4169 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4170 attributes.set_is_evex_instruction();
4171 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
4172 emit_int8(0x30);
4173 emit_operand(src, dst);
4174 }
4175
4176 void Assembler::evpmovwb(Address dst, KRegister mask, XMMRegister src, int vector_len) {
4177 assert(is_vector_masking(), "");
4178 assert(VM_Version::supports_avx512vlbw(), "");
4179 assert(src != xnoreg, "sanity");
4180 InstructionMark im(this);
4181 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
4182 attributes.set_address_attributes(/* tuple_type */ EVEX_HVM, /* input_size_in_bits */ EVEX_NObit);
4183 attributes.reset_is_clear_context();
4184 attributes.set_embedded_opmask_register_specifier(mask);
4185 attributes.set_is_evex_instruction();
4186 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F_38, &attributes);
4187 emit_int8(0x30);
4188 emit_operand(src, dst);
4189 }
4190
4191 // generic
4192 void Assembler::pop(Register dst) {
4193 int encode = prefix_and_encode(dst->encoding());
4194 emit_int8(0x58 | encode);
4195 }
4196
4197 void Assembler::popcntl(Register dst, Address src) {
4198 assert(VM_Version::supports_popcnt(), "must support");
4199 InstructionMark im(this);
4200 emit_int8((unsigned char)0xF3);
4201 prefix(src, dst);
4202 emit_int8(0x0F);
4203 emit_int8((unsigned char)0xB8);
4204 emit_operand(dst, src);
4205 }
4206
4207 void Assembler::popcntl(Register dst, Register src) {
4208 assert(VM_Version::supports_popcnt(), "must support");
4209 emit_int8((unsigned char)0xF3);
4210 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4211 emit_int8(0x0F);
4212 emit_int8((unsigned char)0xB8);
4213 emit_int8((unsigned char)(0xC0 | encode));
4214 }
4215
4216 void Assembler::vpopcntd(XMMRegister dst, XMMRegister src, int vector_len) {
4217 assert(VM_Version::supports_vpopcntdq(), "must support vpopcntdq feature");
4218 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4219 attributes.set_is_evex_instruction();
4220 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4221 emit_int8(0x55);
4222 emit_int8((unsigned char)(0xC0 | encode));
4223 }
4224
4225 void Assembler::popf() {
4226 emit_int8((unsigned char)0x9D);
4227 }
4228
4229 #ifndef _LP64 // no 32bit push/pop on amd64
4230 void Assembler::popl(Address dst) {
4231 // NOTE: this will adjust stack by 8byte on 64bits
4232 InstructionMark im(this);
4233 prefix(dst);
4234 emit_int8((unsigned char)0x8F);
4235 emit_operand(rax, dst);
4236 }
4237 #endif
4238
4239 void Assembler::prefetch_prefix(Address src) {
4240 prefix(src);
4241 emit_int8(0x0F);
4242 }
4243
4244 void Assembler::prefetchnta(Address src) {
4245 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4246 InstructionMark im(this);
4247 prefetch_prefix(src);
4248 emit_int8(0x18);
4249 emit_operand(rax, src); // 0, src
4250 }
4251
4252 void Assembler::prefetchr(Address src) {
4253 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4254 InstructionMark im(this);
4255 prefetch_prefix(src);
4256 emit_int8(0x0D);
4257 emit_operand(rax, src); // 0, src
4258 }
4259
4260 void Assembler::prefetcht0(Address src) {
4261 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4262 InstructionMark im(this);
4263 prefetch_prefix(src);
4264 emit_int8(0x18);
4265 emit_operand(rcx, src); // 1, src
4266 }
4267
4268 void Assembler::prefetcht1(Address src) {
4269 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4270 InstructionMark im(this);
4271 prefetch_prefix(src);
4272 emit_int8(0x18);
4273 emit_operand(rdx, src); // 2, src
4274 }
4275
4276 void Assembler::prefetcht2(Address src) {
4277 NOT_LP64(assert(VM_Version::supports_sse(), "must support"));
4278 InstructionMark im(this);
4279 prefetch_prefix(src);
4280 emit_int8(0x18);
4281 emit_operand(rbx, src); // 3, src
4282 }
4283
4284 void Assembler::prefetchw(Address src) {
4285 assert(VM_Version::supports_3dnow_prefetch(), "must support");
4286 InstructionMark im(this);
4287 prefetch_prefix(src);
4288 emit_int8(0x0D);
4289 emit_operand(rcx, src); // 1, src
4290 }
4291
4292 void Assembler::prefix(Prefix p) {
4293 emit_int8(p);
4294 }
4295
4296 void Assembler::pshufb(XMMRegister dst, XMMRegister src) {
4297 assert(VM_Version::supports_ssse3(), "");
4298 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4299 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4300 emit_int8(0x00);
4301 emit_int8((unsigned char)(0xC0 | encode));
4302 }
4303
4304 void Assembler::vpshufb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
4305 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4306 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4307 0, "");
4308 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
4309 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4310 emit_int8(0x00);
4311 emit_int8((unsigned char)(0xC0 | encode));
4312 }
4313
4314 void Assembler::pshufb(XMMRegister dst, Address src) {
4315 assert(VM_Version::supports_ssse3(), "");
4316 InstructionMark im(this);
4317 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4318 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4319 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4320 emit_int8(0x00);
4321 emit_operand(dst, src);
4322 }
4323
4324 void Assembler::pshufd(XMMRegister dst, XMMRegister src, int mode) {
4325 assert(isByte(mode), "invalid value");
4326 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4327 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_128bit;
4328 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4329 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4330 emit_int8(0x70);
4331 emit_int8((unsigned char)(0xC0 | encode));
4332 emit_int8(mode & 0xFF);
4333 }
4334
4335 void Assembler::vpshufd(XMMRegister dst, XMMRegister src, int mode, int vector_len) {
4336 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4337 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4338 0, "");
4339 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4340 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4341 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4342 emit_int8(0x70);
4343 emit_int8((unsigned char)(0xC0 | encode));
4344 emit_int8(mode & 0xFF);
4345 }
4346
4347 void Assembler::pshufd(XMMRegister dst, Address src, int mode) {
4348 assert(isByte(mode), "invalid value");
4349 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4350 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4351 InstructionMark im(this);
4352 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4353 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4354 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4355 emit_int8(0x70);
4356 emit_operand(dst, src);
4357 emit_int8(mode & 0xFF);
4358 }
4359
4360 void Assembler::pshuflw(XMMRegister dst, XMMRegister src, int mode) {
4361 assert(isByte(mode), "invalid value");
4362 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4363 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4364 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4365 emit_int8(0x70);
4366 emit_int8((unsigned char)(0xC0 | encode));
4367 emit_int8(mode & 0xFF);
4368 }
4369
4370 void Assembler::pshuflw(XMMRegister dst, Address src, int mode) {
4371 assert(isByte(mode), "invalid value");
4372 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4373 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4374 InstructionMark im(this);
4375 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4376 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4377 simd_prefix(dst, xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4378 emit_int8(0x70);
4379 emit_operand(dst, src);
4380 emit_int8(mode & 0xFF);
4381 }
4382
4383 void Assembler::psrldq(XMMRegister dst, int shift) {
4384 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4385 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4386 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4387 int encode = simd_prefix_and_encode(xmm3, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4388 emit_int8(0x73);
4389 emit_int8((unsigned char)(0xC0 | encode));
4390 emit_int8(shift);
4391 }
4392
4393 void Assembler::pslldq(XMMRegister dst, int shift) {
4394 // Shift left 128 bit value in dst XMMRegister by shift number of bytes.
4395 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4396 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
4397 // XMM7 is for /7 encoding: 66 0F 73 /7 ib
4398 int encode = simd_prefix_and_encode(xmm7, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4399 emit_int8(0x73);
4400 emit_int8((unsigned char)(0xC0 | encode));
4401 emit_int8(shift);
4402 }
4403
4404 void Assembler::ptest(XMMRegister dst, Address src) {
4405 assert(VM_Version::supports_sse4_1(), "");
4406 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4407 InstructionMark im(this);
4408 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4409 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4410 emit_int8(0x17);
4411 emit_operand(dst, src);
4412 }
4413
4414 void Assembler::ptest(XMMRegister dst, XMMRegister src) {
4415 assert(VM_Version::supports_sse4_1(), "");
4416 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4417 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4418 emit_int8(0x17);
4419 emit_int8((unsigned char)(0xC0 | encode));
4420 }
4421
4422 void Assembler::vptest(XMMRegister dst, Address src) {
4423 assert(VM_Version::supports_avx(), "");
4424 InstructionMark im(this);
4425 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4426 assert(dst != xnoreg, "sanity");
4427 // swap src<->dst for encoding
4428 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4429 emit_int8(0x17);
4430 emit_operand(dst, src);
4431 }
4432
4433 void Assembler::vptest(XMMRegister dst, XMMRegister src) {
4434 assert(VM_Version::supports_avx(), "");
4435 InstructionAttr attributes(AVX_256bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4436 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4437 emit_int8(0x17);
4438 emit_int8((unsigned char)(0xC0 | encode));
4439 }
4440
4441 void Assembler::vptest(XMMRegister dst, XMMRegister src, int vector_len) {
4442 assert(VM_Version::supports_avx(), "");
4443 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4444 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
4445 emit_int8(0x17);
4446 emit_int8((unsigned char)(0xC0 | encode));
4447 }
4448
4449 void Assembler::punpcklbw(XMMRegister dst, Address src) {
4450 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4451 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4452 InstructionMark im(this);
4453 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4454 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
4455 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4456 emit_int8(0x60);
4457 emit_operand(dst, src);
4458 }
4459
4460 void Assembler::punpcklbw(XMMRegister dst, XMMRegister src) {
4461 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4462 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_vlbw, /* no_mask_reg */ false, /* uses_vl */ true);
4463 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4464 emit_int8(0x60);
4465 emit_int8((unsigned char)(0xC0 | encode));
4466 }
4467
4468 void Assembler::punpckldq(XMMRegister dst, Address src) {
4469 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4470 assert((UseAVX > 0), "SSE mode requires address alignment 16 bytes");
4471 InstructionMark im(this);
4472 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4473 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
4474 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4475 emit_int8(0x62);
4476 emit_operand(dst, src);
4477 }
4478
4479 void Assembler::punpckldq(XMMRegister dst, XMMRegister src) {
4480 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4481 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4482 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4483 emit_int8(0x62);
4484 emit_int8((unsigned char)(0xC0 | encode));
4485 }
4486
4487 void Assembler::punpcklqdq(XMMRegister dst, XMMRegister src) {
4488 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4489 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
4490 attributes.set_rex_vex_w_reverted();
4491 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4492 emit_int8(0x6C);
4493 emit_int8((unsigned char)(0xC0 | encode));
4494 }
4495
4496 void Assembler::push(int32_t imm32) {
4497 // in 64bits we push 64bits onto the stack but only
4498 // take a 32bit immediate
4499 emit_int8(0x68);
4500 emit_int32(imm32);
4501 }
4502
4503 void Assembler::push(Register src) {
4504 int encode = prefix_and_encode(src->encoding());
4505
4506 emit_int8(0x50 | encode);
4507 }
4508
4509 void Assembler::pushf() {
4510 emit_int8((unsigned char)0x9C);
4511 }
4512
4513 #ifndef _LP64 // no 32bit push/pop on amd64
4514 void Assembler::pushl(Address src) {
4515 // Note this will push 64bit on 64bit
4516 InstructionMark im(this);
4517 prefix(src);
4518 emit_int8((unsigned char)0xFF);
4519 emit_operand(rsi, src);
4520 }
4521 #endif
4522
4523 void Assembler::rcll(Register dst, int imm8) {
4524 assert(isShiftCount(imm8), "illegal shift count");
4525 int encode = prefix_and_encode(dst->encoding());
4526 if (imm8 == 1) {
4527 emit_int8((unsigned char)0xD1);
4528 emit_int8((unsigned char)(0xD0 | encode));
4529 } else {
4530 emit_int8((unsigned char)0xC1);
4531 emit_int8((unsigned char)0xD0 | encode);
4532 emit_int8(imm8);
4533 }
4534 }
4535
4536 void Assembler::rcpps(XMMRegister dst, XMMRegister src) {
4537 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4538 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4539 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4540 emit_int8(0x53);
4541 emit_int8((unsigned char)(0xC0 | encode));
4542 }
4543
4544 void Assembler::rcpss(XMMRegister dst, XMMRegister src) {
4545 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4546 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4547 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4548 emit_int8(0x53);
4549 emit_int8((unsigned char)(0xC0 | encode));
4550 }
4551
4552 void Assembler::rdtsc() {
4553 emit_int8((unsigned char)0x0F);
4554 emit_int8((unsigned char)0x31);
4555 }
4556
4557 // copies data from [esi] to [edi] using rcx pointer sized words
4558 // generic
4559 void Assembler::rep_mov() {
4560 emit_int8((unsigned char)0xF3);
4561 // MOVSQ
4562 LP64_ONLY(prefix(REX_W));
4563 emit_int8((unsigned char)0xA5);
4564 }
4565
4566 // sets rcx bytes with rax, value at [edi]
4567 void Assembler::rep_stosb() {
4568 emit_int8((unsigned char)0xF3); // REP
4569 LP64_ONLY(prefix(REX_W));
4570 emit_int8((unsigned char)0xAA); // STOSB
4571 }
4572
4573 // sets rcx pointer sized words with rax, value at [edi]
4574 // generic
4575 void Assembler::rep_stos() {
4576 emit_int8((unsigned char)0xF3); // REP
4577 LP64_ONLY(prefix(REX_W)); // LP64:STOSQ, LP32:STOSD
4578 emit_int8((unsigned char)0xAB);
4579 }
4580
4581 // scans rcx pointer sized words at [edi] for occurance of rax,
4582 // generic
4583 void Assembler::repne_scan() { // repne_scan
4584 emit_int8((unsigned char)0xF2);
4585 // SCASQ
4586 LP64_ONLY(prefix(REX_W));
4587 emit_int8((unsigned char)0xAF);
4588 }
4589
4590 #ifdef _LP64
4591 // scans rcx 4 byte words at [edi] for occurance of rax,
4592 // generic
4593 void Assembler::repne_scanl() { // repne_scan
4594 emit_int8((unsigned char)0xF2);
4595 // SCASL
4596 emit_int8((unsigned char)0xAF);
4597 }
4598 #endif
4599
4600 void Assembler::ret(int imm16) {
4601 if (imm16 == 0) {
4602 emit_int8((unsigned char)0xC3);
4603 } else {
4604 emit_int8((unsigned char)0xC2);
4605 emit_int16(imm16);
4606 }
4607 }
4608
4609 void Assembler::sahf() {
4610 #ifdef _LP64
4611 // Not supported in 64bit mode
4612 ShouldNotReachHere();
4613 #endif
4614 emit_int8((unsigned char)0x9E);
4615 }
4616
4617 void Assembler::sarl(Register dst, int imm8) {
4618 int encode = prefix_and_encode(dst->encoding());
4619 assert(isShiftCount(imm8), "illegal shift count");
4620 if (imm8 == 1) {
4621 emit_int8((unsigned char)0xD1);
4622 emit_int8((unsigned char)(0xF8 | encode));
4623 } else {
4624 emit_int8((unsigned char)0xC1);
4625 emit_int8((unsigned char)(0xF8 | encode));
4626 emit_int8(imm8);
4627 }
4628 }
4629
4630 void Assembler::sarl(Register dst) {
4631 int encode = prefix_and_encode(dst->encoding());
4632 emit_int8((unsigned char)0xD3);
4633 emit_int8((unsigned char)(0xF8 | encode));
4634 }
4635
4636 void Assembler::sbbl(Address dst, int32_t imm32) {
4637 InstructionMark im(this);
4638 prefix(dst);
4639 emit_arith_operand(0x81, rbx, dst, imm32);
4640 }
4641
4642 void Assembler::sbbl(Register dst, int32_t imm32) {
4643 prefix(dst);
4644 emit_arith(0x81, 0xD8, dst, imm32);
4645 }
4646
4647
4648 void Assembler::sbbl(Register dst, Address src) {
4649 InstructionMark im(this);
4650 prefix(src, dst);
4651 emit_int8(0x1B);
4652 emit_operand(dst, src);
4653 }
4654
4655 void Assembler::sbbl(Register dst, Register src) {
4656 (void) prefix_and_encode(dst->encoding(), src->encoding());
4657 emit_arith(0x1B, 0xC0, dst, src);
4658 }
4659
4660 void Assembler::setb(Condition cc, Register dst) {
4661 assert(0 <= cc && cc < 16, "illegal cc");
4662 int encode = prefix_and_encode(dst->encoding(), true);
4663 emit_int8(0x0F);
4664 emit_int8((unsigned char)0x90 | cc);
4665 emit_int8((unsigned char)(0xC0 | encode));
4666 }
4667
4668 void Assembler::palignr(XMMRegister dst, XMMRegister src, int imm8) {
4669 assert(VM_Version::supports_ssse3(), "");
4670 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ false);
4671 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4672 emit_int8((unsigned char)0x0F);
4673 emit_int8((unsigned char)(0xC0 | encode));
4674 emit_int8(imm8);
4675 }
4676
4677 void Assembler::vpalignr(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
4678 assert(vector_len == AVX_128bit? VM_Version::supports_avx() :
4679 vector_len == AVX_256bit? VM_Version::supports_avx2() :
4680 0, "");
4681 InstructionAttr attributes(vector_len, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
4682 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4683 emit_int8((unsigned char)0x0F);
4684 emit_int8((unsigned char)(0xC0 | encode));
4685 emit_int8(imm8);
4686 }
4687
4688 void Assembler::pblendw(XMMRegister dst, XMMRegister src, int imm8) {
4689 assert(VM_Version::supports_sse4_1(), "");
4690 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
4691 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
4692 emit_int8((unsigned char)0x0E);
4693 emit_int8((unsigned char)(0xC0 | encode));
4694 emit_int8(imm8);
4695 }
4696
4697 void Assembler::sha1rnds4(XMMRegister dst, XMMRegister src, int imm8) {
4698 assert(VM_Version::supports_sha(), "");
4699 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_3A, /* rex_w */ false);
4700 emit_int8((unsigned char)0xCC);
4701 emit_int8((unsigned char)(0xC0 | encode));
4702 emit_int8((unsigned char)imm8);
4703 }
4704
4705 void Assembler::sha1nexte(XMMRegister dst, XMMRegister src) {
4706 assert(VM_Version::supports_sha(), "");
4707 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4708 emit_int8((unsigned char)0xC8);
4709 emit_int8((unsigned char)(0xC0 | encode));
4710 }
4711
4712 void Assembler::sha1msg1(XMMRegister dst, XMMRegister src) {
4713 assert(VM_Version::supports_sha(), "");
4714 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4715 emit_int8((unsigned char)0xC9);
4716 emit_int8((unsigned char)(0xC0 | encode));
4717 }
4718
4719 void Assembler::sha1msg2(XMMRegister dst, XMMRegister src) {
4720 assert(VM_Version::supports_sha(), "");
4721 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4722 emit_int8((unsigned char)0xCA);
4723 emit_int8((unsigned char)(0xC0 | encode));
4724 }
4725
4726 // xmm0 is implicit additional source to this instruction.
4727 void Assembler::sha256rnds2(XMMRegister dst, XMMRegister src) {
4728 assert(VM_Version::supports_sha(), "");
4729 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4730 emit_int8((unsigned char)0xCB);
4731 emit_int8((unsigned char)(0xC0 | encode));
4732 }
4733
4734 void Assembler::sha256msg1(XMMRegister dst, XMMRegister src) {
4735 assert(VM_Version::supports_sha(), "");
4736 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4737 emit_int8((unsigned char)0xCC);
4738 emit_int8((unsigned char)(0xC0 | encode));
4739 }
4740
4741 void Assembler::sha256msg2(XMMRegister dst, XMMRegister src) {
4742 assert(VM_Version::supports_sha(), "");
4743 int encode = rex_prefix_and_encode(dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, /* rex_w */ false);
4744 emit_int8((unsigned char)0xCD);
4745 emit_int8((unsigned char)(0xC0 | encode));
4746 }
4747
4748
4749 void Assembler::shll(Register dst, int imm8) {
4750 assert(isShiftCount(imm8), "illegal shift count");
4751 int encode = prefix_and_encode(dst->encoding());
4752 if (imm8 == 1 ) {
4753 emit_int8((unsigned char)0xD1);
4754 emit_int8((unsigned char)(0xE0 | encode));
4755 } else {
4756 emit_int8((unsigned char)0xC1);
4757 emit_int8((unsigned char)(0xE0 | encode));
4758 emit_int8(imm8);
4759 }
4760 }
4761
4762 void Assembler::shll(Register dst) {
4763 int encode = prefix_and_encode(dst->encoding());
4764 emit_int8((unsigned char)0xD3);
4765 emit_int8((unsigned char)(0xE0 | encode));
4766 }
4767
4768 void Assembler::shrl(Register dst, int imm8) {
4769 assert(isShiftCount(imm8), "illegal shift count");
4770 int encode = prefix_and_encode(dst->encoding());
4771 emit_int8((unsigned char)0xC1);
4772 emit_int8((unsigned char)(0xE8 | encode));
4773 emit_int8(imm8);
4774 }
4775
4776 void Assembler::shrl(Register dst) {
4777 int encode = prefix_and_encode(dst->encoding());
4778 emit_int8((unsigned char)0xD3);
4779 emit_int8((unsigned char)(0xE8 | encode));
4780 }
4781
4782 // copies a single word from [esi] to [edi]
4783 void Assembler::smovl() {
4784 emit_int8((unsigned char)0xA5);
4785 }
4786
4787 void Assembler::sqrtsd(XMMRegister dst, XMMRegister src) {
4788 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4789 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4790 attributes.set_rex_vex_w_reverted();
4791 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4792 emit_int8(0x51);
4793 emit_int8((unsigned char)(0xC0 | encode));
4794 }
4795
4796 void Assembler::sqrtsd(XMMRegister dst, Address src) {
4797 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4798 InstructionMark im(this);
4799 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4800 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4801 attributes.set_rex_vex_w_reverted();
4802 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4803 emit_int8(0x51);
4804 emit_operand(dst, src);
4805 }
4806
4807 void Assembler::sqrtss(XMMRegister dst, XMMRegister src) {
4808 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4809 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4810 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4811 emit_int8(0x51);
4812 emit_int8((unsigned char)(0xC0 | encode));
4813 }
4814
4815 void Assembler::std() {
4816 emit_int8((unsigned char)0xFD);
4817 }
4818
4819 void Assembler::sqrtss(XMMRegister dst, Address src) {
4820 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4821 InstructionMark im(this);
4822 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4823 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4824 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4825 emit_int8(0x51);
4826 emit_operand(dst, src);
4827 }
4828
4829 void Assembler::stmxcsr( Address dst) {
4830 if (UseAVX > 0 ) {
4831 assert(VM_Version::supports_avx(), "");
4832 InstructionMark im(this);
4833 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
4834 vex_prefix(dst, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
4835 emit_int8((unsigned char)0xAE);
4836 emit_operand(as_Register(3), dst);
4837 } else {
4838 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4839 InstructionMark im(this);
4840 prefix(dst);
4841 emit_int8(0x0F);
4842 emit_int8((unsigned char)0xAE);
4843 emit_operand(as_Register(3), dst);
4844 }
4845 }
4846
4847 void Assembler::subl(Address dst, int32_t imm32) {
4848 InstructionMark im(this);
4849 prefix(dst);
4850 emit_arith_operand(0x81, rbp, dst, imm32);
4851 }
4852
4853 void Assembler::subl(Address dst, Register src) {
4854 InstructionMark im(this);
4855 prefix(dst, src);
4856 emit_int8(0x29);
4857 emit_operand(src, dst);
4858 }
4859
4860 void Assembler::subl(Register dst, int32_t imm32) {
4861 prefix(dst);
4862 emit_arith(0x81, 0xE8, dst, imm32);
4863 }
4864
4865 // Force generation of a 4 byte immediate value even if it fits into 8bit
4866 void Assembler::subl_imm32(Register dst, int32_t imm32) {
4867 prefix(dst);
4868 emit_arith_imm32(0x81, 0xE8, dst, imm32);
4869 }
4870
4871 void Assembler::subl(Register dst, Address src) {
4872 InstructionMark im(this);
4873 prefix(src, dst);
4874 emit_int8(0x2B);
4875 emit_operand(dst, src);
4876 }
4877
4878 void Assembler::subl(Register dst, Register src) {
4879 (void) prefix_and_encode(dst->encoding(), src->encoding());
4880 emit_arith(0x2B, 0xC0, dst, src);
4881 }
4882
4883 void Assembler::subsd(XMMRegister dst, XMMRegister src) {
4884 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4885 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4886 attributes.set_rex_vex_w_reverted();
4887 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4888 emit_int8(0x5C);
4889 emit_int8((unsigned char)(0xC0 | encode));
4890 }
4891
4892 void Assembler::subsd(XMMRegister dst, Address src) {
4893 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4894 InstructionMark im(this);
4895 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4896 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4897 attributes.set_rex_vex_w_reverted();
4898 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
4899 emit_int8(0x5C);
4900 emit_operand(dst, src);
4901 }
4902
4903 void Assembler::subss(XMMRegister dst, XMMRegister src) {
4904 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4905 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true , /* uses_vl */ false);
4906 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4907 emit_int8(0x5C);
4908 emit_int8((unsigned char)(0xC0 | encode));
4909 }
4910
4911 void Assembler::subss(XMMRegister dst, Address src) {
4912 NOT_LP64(assert(VM_Version::supports_sse(), ""));
4913 InstructionMark im(this);
4914 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4915 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
4916 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
4917 emit_int8(0x5C);
4918 emit_operand(dst, src);
4919 }
4920
4921 void Assembler::testb(Register dst, int imm8) {
4922 NOT_LP64(assert(dst->has_byte_register(), "must have byte register"));
4923 (void) prefix_and_encode(dst->encoding(), true);
4924 emit_arith_b(0xF6, 0xC0, dst, imm8);
4925 }
4926
4927 void Assembler::testb(Address dst, int imm8) {
4928 InstructionMark im(this);
4929 prefix(dst);
4930 emit_int8((unsigned char)0xF6);
4931 emit_operand(rax, dst, 1);
4932 emit_int8(imm8);
4933 }
4934
4935 void Assembler::testl(Register dst, int32_t imm32) {
4936 // not using emit_arith because test
4937 // doesn't support sign-extension of
4938 // 8bit operands
4939 int encode = dst->encoding();
4940 if (encode == 0) {
4941 emit_int8((unsigned char)0xA9);
4942 } else {
4943 encode = prefix_and_encode(encode);
4944 emit_int8((unsigned char)0xF7);
4945 emit_int8((unsigned char)(0xC0 | encode));
4946 }
4947 emit_int32(imm32);
4948 }
4949
4950 void Assembler::testl(Register dst, Register src) {
4951 (void) prefix_and_encode(dst->encoding(), src->encoding());
4952 emit_arith(0x85, 0xC0, dst, src);
4953 }
4954
4955 void Assembler::testl(Register dst, Address src) {
4956 InstructionMark im(this);
4957 prefix(src, dst);
4958 emit_int8((unsigned char)0x85);
4959 emit_operand(dst, src);
4960 }
4961
4962 void Assembler::tzcntl(Register dst, Register src) {
4963 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4964 emit_int8((unsigned char)0xF3);
4965 int encode = prefix_and_encode(dst->encoding(), src->encoding());
4966 emit_int8(0x0F);
4967 emit_int8((unsigned char)0xBC);
4968 emit_int8((unsigned char)0xC0 | encode);
4969 }
4970
4971 void Assembler::tzcntq(Register dst, Register src) {
4972 assert(VM_Version::supports_bmi1(), "tzcnt instruction not supported");
4973 emit_int8((unsigned char)0xF3);
4974 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
4975 emit_int8(0x0F);
4976 emit_int8((unsigned char)0xBC);
4977 emit_int8((unsigned char)(0xC0 | encode));
4978 }
4979
4980 void Assembler::ucomisd(XMMRegister dst, Address src) {
4981 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4982 InstructionMark im(this);
4983 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4984 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
4985 attributes.set_rex_vex_w_reverted();
4986 simd_prefix(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4987 emit_int8(0x2E);
4988 emit_operand(dst, src);
4989 }
4990
4991 void Assembler::ucomisd(XMMRegister dst, XMMRegister src) {
4992 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
4993 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
4994 attributes.set_rex_vex_w_reverted();
4995 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
4996 emit_int8(0x2E);
4997 emit_int8((unsigned char)(0xC0 | encode));
4998 }
4999
5000 void Assembler::ucomiss(XMMRegister dst, Address src) {
5001 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5002 InstructionMark im(this);
5003 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5004 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5005 simd_prefix(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5006 emit_int8(0x2E);
5007 emit_operand(dst, src);
5008 }
5009
5010 void Assembler::ucomiss(XMMRegister dst, XMMRegister src) {
5011 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5012 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5013 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5014 emit_int8(0x2E);
5015 emit_int8((unsigned char)(0xC0 | encode));
5016 }
5017
5018 void Assembler::xabort(int8_t imm8) {
5019 emit_int8((unsigned char)0xC6);
5020 emit_int8((unsigned char)0xF8);
5021 emit_int8((unsigned char)(imm8 & 0xFF));
5022 }
5023
5024 void Assembler::xaddb(Address dst, Register src) {
5025 InstructionMark im(this);
5026 prefix(dst, src, true);
5027 emit_int8(0x0F);
5028 emit_int8((unsigned char)0xC0);
5029 emit_operand(src, dst);
5030 }
5031
5032 void Assembler::xaddw(Address dst, Register src) {
5033 InstructionMark im(this);
5034 emit_int8(0x66);
5035 prefix(dst, src);
5036 emit_int8(0x0F);
5037 emit_int8((unsigned char)0xC1);
5038 emit_operand(src, dst);
5039 }
5040
5041 void Assembler::xaddl(Address dst, Register src) {
5042 InstructionMark im(this);
5043 prefix(dst, src);
5044 emit_int8(0x0F);
5045 emit_int8((unsigned char)0xC1);
5046 emit_operand(src, dst);
5047 }
5048
5049 void Assembler::xbegin(Label& abort, relocInfo::relocType rtype) {
5050 InstructionMark im(this);
5051 relocate(rtype);
5052 if (abort.is_bound()) {
5053 address entry = target(abort);
5054 assert(entry != NULL, "abort entry NULL");
5055 intptr_t offset = entry - pc();
5056 emit_int8((unsigned char)0xC7);
5057 emit_int8((unsigned char)0xF8);
5058 emit_int32(offset - 6); // 2 opcode + 4 address
5059 } else {
5060 abort.add_patch_at(code(), locator());
5061 emit_int8((unsigned char)0xC7);
5062 emit_int8((unsigned char)0xF8);
5063 emit_int32(0);
5064 }
5065 }
5066
5067 void Assembler::xchgb(Register dst, Address src) { // xchg
5068 InstructionMark im(this);
5069 prefix(src, dst, true);
5070 emit_int8((unsigned char)0x86);
5071 emit_operand(dst, src);
5072 }
5073
5074 void Assembler::xchgw(Register dst, Address src) { // xchg
5075 InstructionMark im(this);
5076 emit_int8(0x66);
5077 prefix(src, dst);
5078 emit_int8((unsigned char)0x87);
5079 emit_operand(dst, src);
5080 }
5081
5082 void Assembler::xchgl(Register dst, Address src) { // xchg
5083 InstructionMark im(this);
5084 prefix(src, dst);
5085 emit_int8((unsigned char)0x87);
5086 emit_operand(dst, src);
5087 }
5088
5089 void Assembler::xchgl(Register dst, Register src) {
5090 int encode = prefix_and_encode(dst->encoding(), src->encoding());
5091 emit_int8((unsigned char)0x87);
5092 emit_int8((unsigned char)(0xC0 | encode));
5093 }
5094
5095 void Assembler::xend() {
5096 emit_int8((unsigned char)0x0F);
5097 emit_int8((unsigned char)0x01);
5098 emit_int8((unsigned char)0xD5);
5099 }
5100
5101 void Assembler::xgetbv() {
5102 emit_int8(0x0F);
5103 emit_int8(0x01);
5104 emit_int8((unsigned char)0xD0);
5105 }
5106
5107 void Assembler::xorl(Register dst, int32_t imm32) {
5108 prefix(dst);
5109 emit_arith(0x81, 0xF0, dst, imm32);
5110 }
5111
5112 void Assembler::xorl(Register dst, Address src) {
5113 InstructionMark im(this);
5114 prefix(src, dst);
5115 emit_int8(0x33);
5116 emit_operand(dst, src);
5117 }
5118
5119 void Assembler::xorl(Register dst, Register src) {
5120 (void) prefix_and_encode(dst->encoding(), src->encoding());
5121 emit_arith(0x33, 0xC0, dst, src);
5122 }
5123
5124 void Assembler::xorb(Register dst, Address src) {
5125 InstructionMark im(this);
5126 prefix(src, dst);
5127 emit_int8(0x32);
5128 emit_operand(dst, src);
5129 }
5130
5131 // AVX 3-operands scalar float-point arithmetic instructions
5132
5133 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, Address src) {
5134 assert(VM_Version::supports_avx(), "");
5135 InstructionMark im(this);
5136 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5137 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5138 attributes.set_rex_vex_w_reverted();
5139 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5140 emit_int8(0x58);
5141 emit_operand(dst, src);
5142 }
5143
5144 void Assembler::vaddsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5145 assert(VM_Version::supports_avx(), "");
5146 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5147 attributes.set_rex_vex_w_reverted();
5148 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5149 emit_int8(0x58);
5150 emit_int8((unsigned char)(0xC0 | encode));
5151 }
5152
5153 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, Address src) {
5154 assert(VM_Version::supports_avx(), "");
5155 InstructionMark im(this);
5156 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5157 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5158 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5159 emit_int8(0x58);
5160 emit_operand(dst, src);
5161 }
5162
5163 void Assembler::vaddss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5164 assert(VM_Version::supports_avx(), "");
5165 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5166 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5167 emit_int8(0x58);
5168 emit_int8((unsigned char)(0xC0 | encode));
5169 }
5170
5171 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, Address src) {
5172 assert(VM_Version::supports_avx(), "");
5173 InstructionMark im(this);
5174 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5175 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5176 attributes.set_rex_vex_w_reverted();
5177 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5178 emit_int8(0x5E);
5179 emit_operand(dst, src);
5180 }
5181
5182 void Assembler::vdivsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5183 assert(VM_Version::supports_avx(), "");
5184 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5185 attributes.set_rex_vex_w_reverted();
5186 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5187 emit_int8(0x5E);
5188 emit_int8((unsigned char)(0xC0 | encode));
5189 }
5190
5191 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, Address src) {
5192 assert(VM_Version::supports_avx(), "");
5193 InstructionMark im(this);
5194 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5195 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5196 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5197 emit_int8(0x5E);
5198 emit_operand(dst, src);
5199 }
5200
5201 void Assembler::vdivss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5202 assert(VM_Version::supports_avx(), "");
5203 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5204 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5205 emit_int8(0x5E);
5206 emit_int8((unsigned char)(0xC0 | encode));
5207 }
5208
5209 void Assembler::vfmadd231sd(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5210 assert(VM_Version::supports_fma(), "");
5211 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5212 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5213 emit_int8((unsigned char)0xB9);
5214 emit_int8((unsigned char)(0xC0 | encode));
5215 }
5216
5217 void Assembler::vfmadd231ss(XMMRegister dst, XMMRegister src1, XMMRegister src2) {
5218 assert(VM_Version::supports_fma(), "");
5219 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5220 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5221 emit_int8((unsigned char)0xB9);
5222 emit_int8((unsigned char)(0xC0 | encode));
5223 }
5224
5225 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, Address src) {
5226 assert(VM_Version::supports_avx(), "");
5227 InstructionMark im(this);
5228 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5229 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5230 attributes.set_rex_vex_w_reverted();
5231 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5232 emit_int8(0x59);
5233 emit_operand(dst, src);
5234 }
5235
5236 void Assembler::vmulsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5237 assert(VM_Version::supports_avx(), "");
5238 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5239 attributes.set_rex_vex_w_reverted();
5240 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5241 emit_int8(0x59);
5242 emit_int8((unsigned char)(0xC0 | encode));
5243 }
5244
5245 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, Address src) {
5246 assert(VM_Version::supports_avx(), "");
5247 InstructionMark im(this);
5248 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5249 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5250 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5251 emit_int8(0x59);
5252 emit_operand(dst, src);
5253 }
5254
5255 void Assembler::vmulss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5256 assert(VM_Version::supports_avx(), "");
5257 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5258 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5259 emit_int8(0x59);
5260 emit_int8((unsigned char)(0xC0 | encode));
5261 }
5262
5263 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, Address src) {
5264 assert(VM_Version::supports_avx(), "");
5265 InstructionMark im(this);
5266 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5267 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
5268 attributes.set_rex_vex_w_reverted();
5269 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5270 emit_int8(0x5C);
5271 emit_operand(dst, src);
5272 }
5273
5274 void Assembler::vsubsd(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5275 assert(VM_Version::supports_avx(), "");
5276 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5277 attributes.set_rex_vex_w_reverted();
5278 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
5279 emit_int8(0x5C);
5280 emit_int8((unsigned char)(0xC0 | encode));
5281 }
5282
5283 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, Address src) {
5284 assert(VM_Version::supports_avx(), "");
5285 InstructionMark im(this);
5286 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5287 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
5288 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5289 emit_int8(0x5C);
5290 emit_operand(dst, src);
5291 }
5292
5293 void Assembler::vsubss(XMMRegister dst, XMMRegister nds, XMMRegister src) {
5294 assert(VM_Version::supports_avx(), "");
5295 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
5296 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
5297 emit_int8(0x5C);
5298 emit_int8((unsigned char)(0xC0 | encode));
5299 }
5300
5301 //====================VECTOR ARITHMETIC=====================================
5302
5303 // Float-point vector arithmetic
5304
5305 void Assembler::addpd(XMMRegister dst, XMMRegister src) {
5306 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5307 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5308 attributes.set_rex_vex_w_reverted();
5309 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5310 emit_int8(0x58);
5311 emit_int8((unsigned char)(0xC0 | encode));
5312 }
5313
5314 void Assembler::addpd(XMMRegister dst, Address src) {
5315 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5316 InstructionMark im(this);
5317 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5318 attributes.set_rex_vex_w_reverted();
5319 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5320 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5321 emit_int8(0x58);
5322 emit_operand(dst, src);
5323 }
5324
5325
5326 void Assembler::addps(XMMRegister dst, XMMRegister src) {
5327 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5328 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5329 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5330 emit_int8(0x58);
5331 emit_int8((unsigned char)(0xC0 | encode));
5332 }
5333
5334 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5335 assert(VM_Version::supports_avx(), "");
5336 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5337 attributes.set_rex_vex_w_reverted();
5338 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5339 emit_int8(0x58);
5340 emit_int8((unsigned char)(0xC0 | encode));
5341 }
5342
5343 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5344 assert(VM_Version::supports_avx(), "");
5345 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5346 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5347 emit_int8(0x58);
5348 emit_int8((unsigned char)(0xC0 | encode));
5349 }
5350
5351 void Assembler::vaddpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5352 assert(VM_Version::supports_avx(), "");
5353 InstructionMark im(this);
5354 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5355 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5356 attributes.set_rex_vex_w_reverted();
5357 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5358 emit_int8(0x58);
5359 emit_operand(dst, src);
5360 }
5361
5362 void Assembler::vaddps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5363 assert(VM_Version::supports_avx(), "");
5364 InstructionMark im(this);
5365 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5366 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5367 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5368 emit_int8(0x58);
5369 emit_operand(dst, src);
5370 }
5371
5372 void Assembler::subpd(XMMRegister dst, XMMRegister src) {
5373 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5374 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5375 attributes.set_rex_vex_w_reverted();
5376 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5377 emit_int8(0x5C);
5378 emit_int8((unsigned char)(0xC0 | encode));
5379 }
5380
5381 void Assembler::subps(XMMRegister dst, XMMRegister src) {
5382 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5383 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5384 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5385 emit_int8(0x5C);
5386 emit_int8((unsigned char)(0xC0 | encode));
5387 }
5388
5389 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5390 assert(VM_Version::supports_avx(), "");
5391 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5392 attributes.set_rex_vex_w_reverted();
5393 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5394 emit_int8(0x5C);
5395 emit_int8((unsigned char)(0xC0 | encode));
5396 }
5397
5398 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5399 assert(VM_Version::supports_avx(), "");
5400 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5401 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5402 emit_int8(0x5C);
5403 emit_int8((unsigned char)(0xC0 | encode));
5404 }
5405
5406 void Assembler::vsubpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5407 assert(VM_Version::supports_avx(), "");
5408 InstructionMark im(this);
5409 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5410 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5411 attributes.set_rex_vex_w_reverted();
5412 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5413 emit_int8(0x5C);
5414 emit_operand(dst, src);
5415 }
5416
5417 void Assembler::vsubps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5418 assert(VM_Version::supports_avx(), "");
5419 InstructionMark im(this);
5420 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5421 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5422 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5423 emit_int8(0x5C);
5424 emit_operand(dst, src);
5425 }
5426
5427 void Assembler::mulpd(XMMRegister dst, XMMRegister src) {
5428 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5429 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5430 attributes.set_rex_vex_w_reverted();
5431 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5432 emit_int8(0x59);
5433 emit_int8((unsigned char)(0xC0 | encode));
5434 }
5435
5436 void Assembler::mulpd(XMMRegister dst, Address src) {
5437 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5438 InstructionMark im(this);
5439 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5440 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5441 attributes.set_rex_vex_w_reverted();
5442 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5443 emit_int8(0x59);
5444 emit_operand(dst, src);
5445 }
5446
5447 void Assembler::mulps(XMMRegister dst, XMMRegister src) {
5448 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5449 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5450 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5451 emit_int8(0x59);
5452 emit_int8((unsigned char)(0xC0 | encode));
5453 }
5454
5455 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5456 assert(VM_Version::supports_avx(), "");
5457 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5458 attributes.set_rex_vex_w_reverted();
5459 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5460 emit_int8(0x59);
5461 emit_int8((unsigned char)(0xC0 | encode));
5462 }
5463
5464 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5465 assert(VM_Version::supports_avx(), "");
5466 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5467 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5468 emit_int8(0x59);
5469 emit_int8((unsigned char)(0xC0 | encode));
5470 }
5471
5472 void Assembler::vmulpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5473 assert(VM_Version::supports_avx(), "");
5474 InstructionMark im(this);
5475 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5476 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5477 attributes.set_rex_vex_w_reverted();
5478 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5479 emit_int8(0x59);
5480 emit_operand(dst, src);
5481 }
5482
5483 void Assembler::vmulps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5484 assert(VM_Version::supports_avx(), "");
5485 InstructionMark im(this);
5486 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5487 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5488 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5489 emit_int8(0x59);
5490 emit_operand(dst, src);
5491 }
5492
5493 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5494 assert(VM_Version::supports_fma(), "");
5495 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5496 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5497 emit_int8((unsigned char)0xB8);
5498 emit_int8((unsigned char)(0xC0 | encode));
5499 }
5500
5501 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, XMMRegister src2, int vector_len) {
5502 assert(VM_Version::supports_fma(), "");
5503 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5504 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5505 emit_int8((unsigned char)0xB8);
5506 emit_int8((unsigned char)(0xC0 | encode));
5507 }
5508
5509 void Assembler::vfmadd231pd(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5510 assert(VM_Version::supports_fma(), "");
5511 InstructionMark im(this);
5512 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5513 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5514 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5515 emit_int8((unsigned char)0xB8);
5516 emit_operand(dst, src2);
5517 }
5518
5519 void Assembler::vfmadd231ps(XMMRegister dst, XMMRegister src1, Address src2, int vector_len) {
5520 assert(VM_Version::supports_fma(), "");
5521 InstructionMark im(this);
5522 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5523 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5524 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5525 emit_int8((unsigned char)0xB8);
5526 emit_operand(dst, src2);
5527 }
5528
5529 void Assembler::divpd(XMMRegister dst, XMMRegister src) {
5530 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5531 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5532 attributes.set_rex_vex_w_reverted();
5533 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5534 emit_int8(0x5E);
5535 emit_int8((unsigned char)(0xC0 | encode));
5536 }
5537
5538 void Assembler::divps(XMMRegister dst, XMMRegister src) {
5539 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5540 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5541 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5542 emit_int8(0x5E);
5543 emit_int8((unsigned char)(0xC0 | encode));
5544 }
5545
5546 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5547 assert(VM_Version::supports_avx(), "");
5548 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5549 attributes.set_rex_vex_w_reverted();
5550 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5551 emit_int8(0x5E);
5552 emit_int8((unsigned char)(0xC0 | encode));
5553 }
5554
5555 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5556 assert(VM_Version::supports_avx(), "");
5557 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5558 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5559 emit_int8(0x5E);
5560 emit_int8((unsigned char)(0xC0 | encode));
5561 }
5562
5563 void Assembler::vdivpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5564 assert(VM_Version::supports_avx(), "");
5565 InstructionMark im(this);
5566 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5567 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5568 attributes.set_rex_vex_w_reverted();
5569 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5570 emit_int8(0x5E);
5571 emit_operand(dst, src);
5572 }
5573
5574 void Assembler::vdivps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5575 assert(VM_Version::supports_avx(), "");
5576 InstructionMark im(this);
5577 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5578 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5579 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5580 emit_int8(0x5E);
5581 emit_operand(dst, src);
5582 }
5583
5584 void Assembler::vsqrtpd(XMMRegister dst, XMMRegister src, int vector_len) {
5585 assert(VM_Version::supports_avx(), "");
5586 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5587 attributes.set_rex_vex_w_reverted();
5588 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5589 emit_int8(0x51);
5590 emit_int8((unsigned char)(0xC0 | encode));
5591 }
5592
5593 void Assembler::vsqrtpd(XMMRegister dst, Address src, int vector_len) {
5594 assert(VM_Version::supports_avx(), "");
5595 InstructionMark im(this);
5596 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5597 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5598 attributes.set_rex_vex_w_reverted();
5599 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5600 emit_int8(0x51);
5601 emit_operand(dst, src);
5602 }
5603
5604 void Assembler::vsqrtps(XMMRegister dst, XMMRegister src, int vector_len) {
5605 assert(VM_Version::supports_avx(), "");
5606 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5607 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5608 emit_int8(0x51);
5609 emit_int8((unsigned char)(0xC0 | encode));
5610 }
5611
5612 void Assembler::vsqrtps(XMMRegister dst, Address src, int vector_len) {
5613 assert(VM_Version::supports_avx(), "");
5614 InstructionMark im(this);
5615 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5616 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5617 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5618 emit_int8(0x51);
5619 emit_operand(dst, src);
5620 }
5621
5622 void Assembler::andpd(XMMRegister dst, XMMRegister src) {
5623 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5624 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5625 attributes.set_rex_vex_w_reverted();
5626 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5627 emit_int8(0x54);
5628 emit_int8((unsigned char)(0xC0 | encode));
5629 }
5630
5631 void Assembler::andps(XMMRegister dst, XMMRegister src) {
5632 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5633 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5634 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5635 emit_int8(0x54);
5636 emit_int8((unsigned char)(0xC0 | encode));
5637 }
5638
5639 void Assembler::andps(XMMRegister dst, Address src) {
5640 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5641 InstructionMark im(this);
5642 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5643 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5644 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5645 emit_int8(0x54);
5646 emit_operand(dst, src);
5647 }
5648
5649 void Assembler::andpd(XMMRegister dst, Address src) {
5650 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5651 InstructionMark im(this);
5652 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5653 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5654 attributes.set_rex_vex_w_reverted();
5655 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5656 emit_int8(0x54);
5657 emit_operand(dst, src);
5658 }
5659
5660 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5661 assert(VM_Version::supports_avx(), "");
5662 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5663 attributes.set_rex_vex_w_reverted();
5664 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5665 emit_int8(0x54);
5666 emit_int8((unsigned char)(0xC0 | encode));
5667 }
5668
5669 void Assembler::vandps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5670 assert(VM_Version::supports_avx(), "");
5671 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5672 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5673 emit_int8(0x54);
5674 emit_int8((unsigned char)(0xC0 | encode));
5675 }
5676
5677 void Assembler::vandpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5678 assert(VM_Version::supports_avx(), "");
5679 InstructionMark im(this);
5680 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5681 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5682 attributes.set_rex_vex_w_reverted();
5683 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5684 emit_int8(0x54);
5685 emit_operand(dst, src);
5686 }
5687
5688 void Assembler::vandps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5689 assert(VM_Version::supports_avx(), "");
5690 InstructionMark im(this);
5691 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5692 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5693 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5694 emit_int8(0x54);
5695 emit_operand(dst, src);
5696 }
5697
5698 void Assembler::unpckhpd(XMMRegister dst, XMMRegister src) {
5699 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5700 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5701 attributes.set_rex_vex_w_reverted();
5702 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5703 emit_int8(0x15);
5704 emit_int8((unsigned char)(0xC0 | encode));
5705 }
5706
5707 void Assembler::unpcklpd(XMMRegister dst, XMMRegister src) {
5708 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5709 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5710 attributes.set_rex_vex_w_reverted();
5711 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5712 emit_int8(0x14);
5713 emit_int8((unsigned char)(0xC0 | encode));
5714 }
5715
5716 void Assembler::xorpd(XMMRegister dst, XMMRegister src) {
5717 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5718 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5719 attributes.set_rex_vex_w_reverted();
5720 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5721 emit_int8(0x57);
5722 emit_int8((unsigned char)(0xC0 | encode));
5723 }
5724
5725 void Assembler::xorps(XMMRegister dst, XMMRegister src) {
5726 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5727 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5728 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5729 emit_int8(0x57);
5730 emit_int8((unsigned char)(0xC0 | encode));
5731 }
5732
5733 void Assembler::xorpd(XMMRegister dst, Address src) {
5734 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5735 InstructionMark im(this);
5736 InstructionAttr attributes(AVX_128bit, /* rex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5737 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5738 attributes.set_rex_vex_w_reverted();
5739 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5740 emit_int8(0x57);
5741 emit_operand(dst, src);
5742 }
5743
5744 void Assembler::xorps(XMMRegister dst, Address src) {
5745 NOT_LP64(assert(VM_Version::supports_sse(), ""));
5746 InstructionMark im(this);
5747 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5748 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5749 simd_prefix(dst, dst, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5750 emit_int8(0x57);
5751 emit_operand(dst, src);
5752 }
5753
5754 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5755 assert(VM_Version::supports_avx(), "");
5756 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5757 attributes.set_rex_vex_w_reverted();
5758 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5759 emit_int8(0x57);
5760 emit_int8((unsigned char)(0xC0 | encode));
5761 }
5762
5763 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5764 assert(VM_Version::supports_avx(), "");
5765 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5766 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5767 emit_int8(0x57);
5768 emit_int8((unsigned char)(0xC0 | encode));
5769 }
5770
5771 void Assembler::vxorpd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5772 assert(VM_Version::supports_avx(), "");
5773 InstructionMark im(this);
5774 InstructionAttr attributes(vector_len, /* vex_w */ !_legacy_mode_dq, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5775 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5776 attributes.set_rex_vex_w_reverted();
5777 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5778 emit_int8(0x57);
5779 emit_operand(dst, src);
5780 }
5781
5782 void Assembler::vxorps(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5783 assert(VM_Version::supports_avx(), "");
5784 InstructionMark im(this);
5785 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
5786 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5787 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
5788 emit_int8(0x57);
5789 emit_operand(dst, src);
5790 }
5791
5792 // Integer vector arithmetic
5793 void Assembler::vphaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5794 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5795 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5796 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5797 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5798 emit_int8(0x01);
5799 emit_int8((unsigned char)(0xC0 | encode));
5800 }
5801
5802 void Assembler::vphaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5803 assert(VM_Version::supports_avx() && (vector_len == 0) ||
5804 VM_Version::supports_avx2(), "256 bit integer vectors requires AVX2");
5805 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5806 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5807 emit_int8(0x02);
5808 emit_int8((unsigned char)(0xC0 | encode));
5809 }
5810
5811 void Assembler::paddb(XMMRegister dst, XMMRegister src) {
5812 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5813 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5814 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5815 emit_int8((unsigned char)0xFC);
5816 emit_int8((unsigned char)(0xC0 | encode));
5817 }
5818
5819 void Assembler::paddw(XMMRegister dst, XMMRegister src) {
5820 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5821 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5822 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5823 emit_int8((unsigned char)0xFD);
5824 emit_int8((unsigned char)(0xC0 | encode));
5825 }
5826
5827 void Assembler::paddd(XMMRegister dst, XMMRegister src) {
5828 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5829 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5830 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5831 emit_int8((unsigned char)0xFE);
5832 emit_int8((unsigned char)(0xC0 | encode));
5833 }
5834
5835 void Assembler::paddd(XMMRegister dst, Address src) {
5836 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5837 InstructionMark im(this);
5838 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5839 simd_prefix(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5840 emit_int8((unsigned char)0xFE);
5841 emit_operand(dst, src);
5842 }
5843
5844 void Assembler::paddq(XMMRegister dst, XMMRegister src) {
5845 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5846 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5847 attributes.set_rex_vex_w_reverted();
5848 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5849 emit_int8((unsigned char)0xD4);
5850 emit_int8((unsigned char)(0xC0 | encode));
5851 }
5852
5853 void Assembler::phaddw(XMMRegister dst, XMMRegister src) {
5854 assert(VM_Version::supports_sse3(), "");
5855 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
5856 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5857 emit_int8(0x01);
5858 emit_int8((unsigned char)(0xC0 | encode));
5859 }
5860
5861 void Assembler::phaddd(XMMRegister dst, XMMRegister src) {
5862 assert(VM_Version::supports_sse3(), "");
5863 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
5864 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
5865 emit_int8(0x02);
5866 emit_int8((unsigned char)(0xC0 | encode));
5867 }
5868
5869 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5870 assert(UseAVX > 0, "requires some form of AVX");
5871 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5872 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5873 emit_int8((unsigned char)0xFC);
5874 emit_int8((unsigned char)(0xC0 | encode));
5875 }
5876
5877 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5878 assert(UseAVX > 0, "requires some form of AVX");
5879 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5880 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5881 emit_int8((unsigned char)0xFD);
5882 emit_int8((unsigned char)(0xC0 | encode));
5883 }
5884
5885 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5886 assert(UseAVX > 0, "requires some form of AVX");
5887 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5888 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5889 emit_int8((unsigned char)0xFE);
5890 emit_int8((unsigned char)(0xC0 | encode));
5891 }
5892
5893 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5894 assert(UseAVX > 0, "requires some form of AVX");
5895 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5896 attributes.set_rex_vex_w_reverted();
5897 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5898 emit_int8((unsigned char)0xD4);
5899 emit_int8((unsigned char)(0xC0 | encode));
5900 }
5901
5902 void Assembler::vpaddb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5903 assert(UseAVX > 0, "requires some form of AVX");
5904 InstructionMark im(this);
5905 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5906 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5907 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5908 emit_int8((unsigned char)0xFC);
5909 emit_operand(dst, src);
5910 }
5911
5912 void Assembler::vpaddw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5913 assert(UseAVX > 0, "requires some form of AVX");
5914 InstructionMark im(this);
5915 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5916 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
5917 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5918 emit_int8((unsigned char)0xFD);
5919 emit_operand(dst, src);
5920 }
5921
5922 void Assembler::vpaddd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5923 assert(UseAVX > 0, "requires some form of AVX");
5924 InstructionMark im(this);
5925 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5926 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
5927 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5928 emit_int8((unsigned char)0xFE);
5929 emit_operand(dst, src);
5930 }
5931
5932 void Assembler::vpaddq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
5933 assert(UseAVX > 0, "requires some form of AVX");
5934 InstructionMark im(this);
5935 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5936 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
5937 attributes.set_rex_vex_w_reverted();
5938 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5939 emit_int8((unsigned char)0xD4);
5940 emit_operand(dst, src);
5941 }
5942
5943 void Assembler::psubb(XMMRegister dst, XMMRegister src) {
5944 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5945 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5946 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5947 emit_int8((unsigned char)0xF8);
5948 emit_int8((unsigned char)(0xC0 | encode));
5949 }
5950
5951 void Assembler::psubw(XMMRegister dst, XMMRegister src) {
5952 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5953 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5954 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5955 emit_int8((unsigned char)0xF9);
5956 emit_int8((unsigned char)(0xC0 | encode));
5957 }
5958
5959 void Assembler::psubd(XMMRegister dst, XMMRegister src) {
5960 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5961 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5962 emit_int8((unsigned char)0xFA);
5963 emit_int8((unsigned char)(0xC0 | encode));
5964 }
5965
5966 void Assembler::psubq(XMMRegister dst, XMMRegister src) {
5967 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
5968 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5969 attributes.set_rex_vex_w_reverted();
5970 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5971 emit_int8((unsigned char)0xFB);
5972 emit_int8((unsigned char)(0xC0 | encode));
5973 }
5974
5975 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5976 assert(UseAVX > 0, "requires some form of AVX");
5977 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5978 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5979 emit_int8((unsigned char)0xF8);
5980 emit_int8((unsigned char)(0xC0 | encode));
5981 }
5982
5983 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5984 assert(UseAVX > 0, "requires some form of AVX");
5985 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
5986 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5987 emit_int8((unsigned char)0xF9);
5988 emit_int8((unsigned char)(0xC0 | encode));
5989 }
5990
5991 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
5992 assert(UseAVX > 0, "requires some form of AVX");
5993 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
5994 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
5995 emit_int8((unsigned char)0xFA);
5996 emit_int8((unsigned char)(0xC0 | encode));
5997 }
5998
5999 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6000 assert(UseAVX > 0, "requires some form of AVX");
6001 InstructionAttr attributes(vector_len, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6002 attributes.set_rex_vex_w_reverted();
6003 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6004 emit_int8((unsigned char)0xFB);
6005 emit_int8((unsigned char)(0xC0 | encode));
6006 }
6007
6008 void Assembler::vpsubb(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6009 assert(UseAVX > 0, "requires some form of AVX");
6010 InstructionMark im(this);
6011 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6012 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6013 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6014 emit_int8((unsigned char)0xF8);
6015 emit_operand(dst, src);
6016 }
6017
6018 void Assembler::vpsubw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6019 assert(UseAVX > 0, "requires some form of AVX");
6020 InstructionMark im(this);
6021 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6022 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6023 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6024 emit_int8((unsigned char)0xF9);
6025 emit_operand(dst, src);
6026 }
6027
6028 void Assembler::vpsubd(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6029 assert(UseAVX > 0, "requires some form of AVX");
6030 InstructionMark im(this);
6031 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6032 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6033 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6034 emit_int8((unsigned char)0xFA);
6035 emit_operand(dst, src);
6036 }
6037
6038 void Assembler::vpsubq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6039 assert(UseAVX > 0, "requires some form of AVX");
6040 InstructionMark im(this);
6041 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6042 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6043 attributes.set_rex_vex_w_reverted();
6044 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6045 emit_int8((unsigned char)0xFB);
6046 emit_operand(dst, src);
6047 }
6048
6049 void Assembler::pmullw(XMMRegister dst, XMMRegister src) {
6050 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6051 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6052 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6053 emit_int8((unsigned char)0xD5);
6054 emit_int8((unsigned char)(0xC0 | encode));
6055 }
6056
6057 void Assembler::pmulld(XMMRegister dst, XMMRegister src) {
6058 assert(VM_Version::supports_sse4_1(), "");
6059 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6060 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6061 emit_int8(0x40);
6062 emit_int8((unsigned char)(0xC0 | encode));
6063 }
6064
6065 void Assembler::pmuludq(XMMRegister dst, XMMRegister src) {
6066 assert(VM_Version::supports_sse2(), "");
6067 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6068 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6069 emit_int8((unsigned char)(0xF4));
6070 emit_int8((unsigned char)(0xC0 | encode));
6071 }
6072
6073 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6074 assert(UseAVX > 0, "requires some form of AVX");
6075 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6076 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6077 emit_int8((unsigned char)0xD5);
6078 emit_int8((unsigned char)(0xC0 | encode));
6079 }
6080
6081 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6082 assert(UseAVX > 0, "requires some form of AVX");
6083 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6084 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6085 emit_int8(0x40);
6086 emit_int8((unsigned char)(0xC0 | encode));
6087 }
6088
6089 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6090 assert(UseAVX > 2, "requires some form of EVEX");
6091 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6092 attributes.set_is_evex_instruction();
6093 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6094 emit_int8(0x40);
6095 emit_int8((unsigned char)(0xC0 | encode));
6096 }
6097
6098 void Assembler::vpmuludq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6099 assert(UseAVX > 0, "requires some form of AVX");
6100 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6101 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6102 emit_int8((unsigned char)(0xF4));
6103 emit_int8((unsigned char)(0xC0 | encode));
6104 }
6105
6106 void Assembler::vpmullw(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6107 assert(UseAVX > 0, "requires some form of AVX");
6108 InstructionMark im(this);
6109 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6110 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
6111 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6112 emit_int8((unsigned char)0xD5);
6113 emit_operand(dst, src);
6114 }
6115
6116 void Assembler::vpmulld(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6117 assert(UseAVX > 0, "requires some form of AVX");
6118 InstructionMark im(this);
6119 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6120 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6121 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6122 emit_int8(0x40);
6123 emit_operand(dst, src);
6124 }
6125
6126 void Assembler::vpmullq(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6127 assert(UseAVX > 2, "requires some form of EVEX");
6128 InstructionMark im(this);
6129 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ _legacy_mode_dq, /* no_mask_reg */ false, /* uses_vl */ true);
6130 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_64bit);
6131 attributes.set_is_evex_instruction();
6132 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6133 emit_int8(0x40);
6134 emit_operand(dst, src);
6135 }
6136
6137 // Min, max
6138 void Assembler::pminsb(XMMRegister dst, XMMRegister src) {
6139 assert(VM_Version::supports_sse4_1(), "");
6140 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6141 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6142 emit_int8(0x38);
6143 emit_int8((unsigned char)(0xC0 | encode));
6144 }
6145
6146 void Assembler::vpminsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6147 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6148 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
6149 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
6150 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6151 emit_int8(0x39);
6152 emit_int8((unsigned char)(0xC0 | encode));
6153 }
6154
6155 void Assembler::pminsw(XMMRegister dst, XMMRegister src) {
6156 assert(VM_Version::supports_sse2(), "");
6157 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6158 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6159 emit_int8((unsigned char)0xEA);
6160 emit_int8((unsigned char)(0xC0 | encode));
6161 }
6162
6163 void Assembler::vpminsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6164 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6165 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
6166 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
6167 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6168 emit_int8((unsigned char)0xEA);
6169 emit_int8((unsigned char)(0xC0 | encode));
6170 }
6171
6172 void Assembler::pminsd(XMMRegister dst, XMMRegister src) {
6173 assert(VM_Version::supports_sse4_1(), "");
6174 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
6175 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6176 emit_int8(0x39);
6177 emit_int8((unsigned char)(0xC0 | encode));
6178 }
6179
6180 void Assembler::vpminsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6181 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6182 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
6183 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true);
6184 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6185 emit_int8(0x39);
6186 emit_int8((unsigned char)(0xC0 | encode));
6187 }
6188
6189 void Assembler::vpminsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6190 assert(UseAVX > 2, "requires AVX512F");
6191 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6192 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6193 emit_int8(0x39);
6194 emit_int8((unsigned char)(0xC0 | encode));
6195 }
6196
6197 void Assembler::minps(XMMRegister dst, XMMRegister src) {
6198 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6199 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6200 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6201 emit_int8(0x5D);
6202 emit_int8((unsigned char)(0xC0 | encode));
6203 }
6204 void Assembler::vminps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6205 assert(vector_len >= AVX_512bit ? VM_Version::supports_avx512vl() : VM_Version::supports_avx(), "");
6206 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true);
6207 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6208 emit_int8(0x5D);
6209 emit_int8((unsigned char)(0xC0 | encode));
6210 }
6211
6212 void Assembler::minpd(XMMRegister dst, XMMRegister src) {
6213 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6214 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6215 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6216 emit_int8(0x5D);
6217 emit_int8((unsigned char)(0xC0 | encode));
6218 }
6219 void Assembler::vminpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6220 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6221 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
6222 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true);
6223 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6224 emit_int8(0x5D);
6225 emit_int8((unsigned char)(0xC0 | encode));
6226 }
6227
6228 void Assembler::pmaxsb(XMMRegister dst, XMMRegister src) {
6229 assert(VM_Version::supports_sse4_1(), "");
6230 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6231 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6232 emit_int8(0x3C);
6233 emit_int8((unsigned char)(0xC0 | encode));
6234 }
6235
6236 void Assembler::vpmaxsb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6237 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6238 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
6239 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
6240 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6241 emit_int8(0x3C);
6242 emit_int8((unsigned char)(0xC0 | encode));
6243 }
6244
6245 void Assembler::pmaxsw(XMMRegister dst, XMMRegister src) {
6246 assert(VM_Version::supports_sse2(), "");
6247 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
6248 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6249 emit_int8((unsigned char)0xEE);
6250 emit_int8((unsigned char)(0xC0 | encode));
6251 }
6252
6253 void Assembler::vpmaxsw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6254 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6255 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_avx512bw()), "");
6256 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ false, /* uses_vl */ true);
6257 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6258 emit_int8((unsigned char)0xEE);
6259 emit_int8((unsigned char)(0xC0 | encode));
6260 }
6261
6262 void Assembler::pmaxsd(XMMRegister dst, XMMRegister src) {
6263 assert(VM_Version::supports_sse4_1(), "");
6264 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ false);
6265 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6266 emit_int8(0x3D);
6267 emit_int8((unsigned char)(0xC0 | encode));
6268 }
6269
6270 void Assembler::vpmaxsd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6271 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() :
6272 (vector_len == AVX_256bit ? VM_Version::supports_avx2() : VM_Version::supports_evex()), "");
6273 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true);
6274 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6275 emit_int8(0x3D);
6276 emit_int8((unsigned char)(0xC0 | encode));
6277 }
6278
6279 void Assembler::vpmaxsq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6280 assert(UseAVX > 2, "requires AVX512F");
6281 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6282 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6283 emit_int8(0x3D);
6284 emit_int8((unsigned char)(0xC0 | encode));
6285 }
6286
6287 void Assembler::maxps(XMMRegister dst, XMMRegister src) {
6288 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6289 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6290 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6291 emit_int8(0x5F);
6292 emit_int8((unsigned char)(0xC0 | encode));
6293 }
6294
6295 void Assembler::vmaxps(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6296 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
6297 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true);
6298 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
6299 emit_int8(0x5F);
6300 emit_int8((unsigned char)(0xC0 | encode));
6301 }
6302
6303 void Assembler::maxpd(XMMRegister dst, XMMRegister src) {
6304 NOT_LP64(assert(VM_Version::supports_sse(), ""));
6305 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6306 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6307 emit_int8(0x5F);
6308 emit_int8((unsigned char)(0xC0 | encode));
6309 }
6310
6311 void Assembler::vmaxpd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6312 assert(vector_len >= AVX_512bit ? VM_Version::supports_evex() : VM_Version::supports_avx(), "");
6313 InstructionAttr attributes(vector_len, /* vex_w */true, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ true);
6314 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6315 emit_int8(0x5F);
6316 emit_int8((unsigned char)(0xC0 | encode));
6317 }
6318
6319 // Shift packed integers left by specified number of bits.
6320 void Assembler::psllw(XMMRegister dst, int shift) {
6321 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6322 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6323 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
6324 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6325 emit_int8(0x71);
6326 emit_int8((unsigned char)(0xC0 | encode));
6327 emit_int8(shift & 0xFF);
6328 }
6329
6330 void Assembler::pslld(XMMRegister dst, int shift) {
6331 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6332 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6333 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
6334 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6335 emit_int8(0x72);
6336 emit_int8((unsigned char)(0xC0 | encode));
6337 emit_int8(shift & 0xFF);
6338 }
6339
6340 void Assembler::psllq(XMMRegister dst, int shift) {
6341 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6342 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6343 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6344 int encode = simd_prefix_and_encode(xmm6, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6345 emit_int8(0x73);
6346 emit_int8((unsigned char)(0xC0 | encode));
6347 emit_int8(shift & 0xFF);
6348 }
6349
6350 void Assembler::psllw(XMMRegister dst, XMMRegister shift) {
6351 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6352 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6353 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6354 emit_int8((unsigned char)0xF1);
6355 emit_int8((unsigned char)(0xC0 | encode));
6356 }
6357
6358 void Assembler::pslld(XMMRegister dst, XMMRegister shift) {
6359 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6360 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6361 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6362 emit_int8((unsigned char)0xF2);
6363 emit_int8((unsigned char)(0xC0 | encode));
6364 }
6365
6366 void Assembler::psllq(XMMRegister dst, XMMRegister shift) {
6367 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6368 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6369 attributes.set_rex_vex_w_reverted();
6370 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6371 emit_int8((unsigned char)0xF3);
6372 emit_int8((unsigned char)(0xC0 | encode));
6373 }
6374
6375 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6376 assert(UseAVX > 0, "requires some form of AVX");
6377 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6378 // XMM6 is for /6 encoding: 66 0F 71 /6 ib
6379 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6380 emit_int8(0x71);
6381 emit_int8((unsigned char)(0xC0 | encode));
6382 emit_int8(shift & 0xFF);
6383 }
6384
6385 void Assembler::vpslld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6386 assert(UseAVX > 0, "requires some form of AVX");
6387 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6388 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6389 // XMM6 is for /6 encoding: 66 0F 72 /6 ib
6390 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6391 emit_int8(0x72);
6392 emit_int8((unsigned char)(0xC0 | encode));
6393 emit_int8(shift & 0xFF);
6394 }
6395
6396 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6397 assert(UseAVX > 0, "requires some form of AVX");
6398 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6399 attributes.set_rex_vex_w_reverted();
6400 // XMM6 is for /6 encoding: 66 0F 73 /6 ib
6401 int encode = vex_prefix_and_encode(xmm6->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6402 emit_int8(0x73);
6403 emit_int8((unsigned char)(0xC0 | encode));
6404 emit_int8(shift & 0xFF);
6405 }
6406
6407 void Assembler::vpsllw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6408 assert(UseAVX > 0, "requires some form of AVX");
6409 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6410 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6411 emit_int8((unsigned char)0xF1);
6412 emit_int8((unsigned char)(0xC0 | encode));
6413 }
6414
6415 void Assembler::vpslld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6416 assert(UseAVX > 0, "requires some form of AVX");
6417 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6418 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6419 emit_int8((unsigned char)0xF2);
6420 emit_int8((unsigned char)(0xC0 | encode));
6421 }
6422
6423 void Assembler::vpsllq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6424 assert(UseAVX > 0, "requires some form of AVX");
6425 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6426 attributes.set_rex_vex_w_reverted();
6427 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6428 emit_int8((unsigned char)0xF3);
6429 emit_int8((unsigned char)(0xC0 | encode));
6430 }
6431
6432 // Shift packed integers logically right by specified number of bits.
6433 void Assembler::psrlw(XMMRegister dst, int shift) {
6434 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6435 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6436 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6437 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6438 emit_int8(0x71);
6439 emit_int8((unsigned char)(0xC0 | encode));
6440 emit_int8(shift & 0xFF);
6441 }
6442
6443 void Assembler::psrld(XMMRegister dst, int shift) {
6444 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6445 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6446 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6447 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6448 emit_int8(0x72);
6449 emit_int8((unsigned char)(0xC0 | encode));
6450 emit_int8(shift & 0xFF);
6451 }
6452
6453 void Assembler::psrlq(XMMRegister dst, int shift) {
6454 // Do not confuse it with psrldq SSE2 instruction which
6455 // shifts 128 bit value in xmm register by number of bytes.
6456 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6457 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6458 attributes.set_rex_vex_w_reverted();
6459 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6460 int encode = simd_prefix_and_encode(xmm2, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6461 emit_int8(0x73);
6462 emit_int8((unsigned char)(0xC0 | encode));
6463 emit_int8(shift & 0xFF);
6464 }
6465
6466 void Assembler::psrlw(XMMRegister dst, XMMRegister shift) {
6467 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6468 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6469 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6470 emit_int8((unsigned char)0xD1);
6471 emit_int8((unsigned char)(0xC0 | encode));
6472 }
6473
6474 void Assembler::psrld(XMMRegister dst, XMMRegister shift) {
6475 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6476 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6477 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6478 emit_int8((unsigned char)0xD2);
6479 emit_int8((unsigned char)(0xC0 | encode));
6480 }
6481
6482 void Assembler::psrlq(XMMRegister dst, XMMRegister shift) {
6483 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6484 InstructionAttr attributes(AVX_128bit, /* rex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6485 attributes.set_rex_vex_w_reverted();
6486 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6487 emit_int8((unsigned char)0xD3);
6488 emit_int8((unsigned char)(0xC0 | encode));
6489 }
6490
6491 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6492 assert(UseAVX > 0, "requires some form of AVX");
6493 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6494 // XMM2 is for /2 encoding: 66 0F 71 /2 ib
6495 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6496 emit_int8(0x71);
6497 emit_int8((unsigned char)(0xC0 | encode));
6498 emit_int8(shift & 0xFF);
6499 }
6500
6501 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6502 assert(UseAVX > 0, "requires some form of AVX");
6503 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6504 // XMM2 is for /2 encoding: 66 0F 72 /2 ib
6505 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6506 emit_int8(0x72);
6507 emit_int8((unsigned char)(0xC0 | encode));
6508 emit_int8(shift & 0xFF);
6509 }
6510
6511 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6512 assert(UseAVX > 0, "requires some form of AVX");
6513 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6514 attributes.set_rex_vex_w_reverted();
6515 // XMM2 is for /2 encoding: 66 0F 73 /2 ib
6516 int encode = vex_prefix_and_encode(xmm2->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6517 emit_int8(0x73);
6518 emit_int8((unsigned char)(0xC0 | encode));
6519 emit_int8(shift & 0xFF);
6520 }
6521
6522 void Assembler::vpsrlw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6523 assert(UseAVX > 0, "requires some form of AVX");
6524 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6525 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6526 emit_int8((unsigned char)0xD1);
6527 emit_int8((unsigned char)(0xC0 | encode));
6528 }
6529
6530 void Assembler::vpsrld(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6531 assert(UseAVX > 0, "requires some form of AVX");
6532 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6533 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6534 emit_int8((unsigned char)0xD2);
6535 emit_int8((unsigned char)(0xC0 | encode));
6536 }
6537
6538 void Assembler::vpsrlq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6539 assert(UseAVX > 0, "requires some form of AVX");
6540 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6541 attributes.set_rex_vex_w_reverted();
6542 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6543 emit_int8((unsigned char)0xD3);
6544 emit_int8((unsigned char)(0xC0 | encode));
6545 }
6546
6547 // Shift packed integers arithmetically right by specified number of bits.
6548 void Assembler::psraw(XMMRegister dst, int shift) {
6549 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6550 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6551 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6552 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6553 emit_int8(0x71);
6554 emit_int8((unsigned char)(0xC0 | encode));
6555 emit_int8(shift & 0xFF);
6556 }
6557
6558 void Assembler::psrad(XMMRegister dst, int shift) {
6559 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6560 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6561 // XMM4 is for /4 encoding: 66 0F 72 /4 ib
6562 int encode = simd_prefix_and_encode(xmm4, dst, dst, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6563 emit_int8(0x72);
6564 emit_int8((unsigned char)(0xC0 | encode));
6565 emit_int8(shift & 0xFF);
6566 }
6567
6568 void Assembler::psraw(XMMRegister dst, XMMRegister shift) {
6569 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6570 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6571 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6572 emit_int8((unsigned char)0xE1);
6573 emit_int8((unsigned char)(0xC0 | encode));
6574 }
6575
6576 void Assembler::psrad(XMMRegister dst, XMMRegister shift) {
6577 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6578 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6579 int encode = simd_prefix_and_encode(dst, dst, shift, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6580 emit_int8((unsigned char)0xE2);
6581 emit_int8((unsigned char)(0xC0 | encode));
6582 }
6583
6584 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6585 assert(UseAVX > 0, "requires some form of AVX");
6586 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6587 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6588 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6589 emit_int8(0x71);
6590 emit_int8((unsigned char)(0xC0 | encode));
6591 emit_int8(shift & 0xFF);
6592 }
6593
6594 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, int shift, int vector_len) {
6595 assert(UseAVX > 0, "requires some form of AVX");
6596 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6597 // XMM4 is for /4 encoding: 66 0F 71 /4 ib
6598 int encode = vex_prefix_and_encode(xmm4->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6599 emit_int8(0x72);
6600 emit_int8((unsigned char)(0xC0 | encode));
6601 emit_int8(shift & 0xFF);
6602 }
6603
6604 void Assembler::vpsraw(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6605 assert(UseAVX > 0, "requires some form of AVX");
6606 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
6607 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6608 emit_int8((unsigned char)0xE1);
6609 emit_int8((unsigned char)(0xC0 | encode));
6610 }
6611
6612 void Assembler::vpsrad(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6613 assert(UseAVX > 0, "requires some form of AVX");
6614 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6615 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6616 emit_int8((unsigned char)0xE2);
6617 emit_int8((unsigned char)(0xC0 | encode));
6618 }
6619
6620 //Variable Shift packed integers logically left.
6621 void Assembler::vpsllvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6622 assert(UseAVX > 1, "requires AVX2");
6623 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6624 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6625 emit_int8(0x47);
6626 emit_int8((unsigned char)(0xC0 | encode));
6627 }
6628
6629 void Assembler::vpsllvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6630 assert(UseAVX > 1, "requires AVX2");
6631 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6632 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6633 emit_int8(0x47);
6634 emit_int8((unsigned char)(0xC0 | encode));
6635 }
6636
6637 //Variable Shift packed integers logically right.
6638 void Assembler::vpsrlvd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6639 assert(UseAVX > 1, "requires AVX2");
6640 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6641 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6642 emit_int8(0x45);
6643 emit_int8((unsigned char)(0xC0 | encode));
6644 }
6645
6646 void Assembler::vpsrlvq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6647 assert(UseAVX > 1, "requires AVX2");
6648 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6649 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6650 emit_int8(0x45);
6651 emit_int8((unsigned char)(0xC0 | encode));
6652 }
6653
6654 //Variable right Shift arithmetic packed integers .
6655 void Assembler::vpsravd(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6656 assert(UseAVX > 1, "requires AVX2");
6657 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6658 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6659 emit_int8(0x46);
6660 emit_int8((unsigned char)(0xC0 | encode));
6661 }
6662
6663 void Assembler::vpsravq(XMMRegister dst, XMMRegister src, XMMRegister shift, int vector_len) {
6664 assert(UseAVX > 1, "requires AVX2");
6665 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6666 int encode = vex_prefix_and_encode(dst->encoding(), src->encoding(), shift->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
6667 emit_int8(0x46);
6668 emit_int8((unsigned char)(0xC0 | encode));
6669 }
6670
6671 // logical operations packed integers
6672 void Assembler::pand(XMMRegister dst, XMMRegister src) {
6673 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6674 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6675 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6676 emit_int8((unsigned char)0xDB);
6677 emit_int8((unsigned char)(0xC0 | encode));
6678 }
6679
6680 void Assembler::vpand(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6681 assert(UseAVX > 0, "requires some form of AVX");
6682 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6683 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6684 emit_int8((unsigned char)0xDB);
6685 emit_int8((unsigned char)(0xC0 | encode));
6686 }
6687
6688 void Assembler::vpand(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6689 assert(UseAVX > 0, "requires some form of AVX");
6690 InstructionMark im(this);
6691 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6692 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6693 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6694 emit_int8((unsigned char)0xDB);
6695 emit_operand(dst, src);
6696 }
6697
6698 void Assembler::evpandd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
6699 assert(VM_Version::supports_evex(), "");
6700 // Encoding: EVEX.NDS.XXX.66.0F.W0 DB /r
6701 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6702 attributes.set_is_evex_instruction();
6703 attributes.set_embedded_opmask_register_specifier(mask);
6704 if (merge) {
6705 attributes.reset_is_clear_context();
6706 }
6707 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6708 emit_int8((unsigned char)0xDB);
6709 emit_int8((unsigned char)(0xC0 | encode));
6710 }
6711
6712 void Assembler::vpandq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6713 assert(UseAVX > 2, "requires some form of EVEX");
6714 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6715 attributes.set_rex_vex_w_reverted();
6716 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6717 emit_int8((unsigned char)0xDB);
6718 emit_int8((unsigned char)(0xC0 | encode));
6719 }
6720
6721 void Assembler::pandn(XMMRegister dst, XMMRegister src) {
6722 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6723 InstructionAttr attributes(AVX_128bit, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6724 attributes.set_rex_vex_w_reverted();
6725 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6726 emit_int8((unsigned char)0xDF);
6727 emit_int8((unsigned char)(0xC0 | encode));
6728 }
6729
6730 void Assembler::por(XMMRegister dst, XMMRegister src) {
6731 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6732 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6733 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6734 emit_int8((unsigned char)0xEB);
6735 emit_int8((unsigned char)(0xC0 | encode));
6736 }
6737
6738 void Assembler::vpor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6739 assert(UseAVX > 0, "requires some form of AVX");
6740 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6741 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6742 emit_int8((unsigned char)0xEB);
6743 emit_int8((unsigned char)(0xC0 | encode));
6744 }
6745
6746 void Assembler::vpor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6747 assert(UseAVX > 0, "requires some form of AVX");
6748 InstructionMark im(this);
6749 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6750 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6751 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6752 emit_int8((unsigned char)0xEB);
6753 emit_operand(dst, src);
6754 }
6755
6756 void Assembler::vporq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6757 assert(UseAVX > 2, "requires some form of EVEX");
6758 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6759 attributes.set_rex_vex_w_reverted();
6760 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6761 emit_int8((unsigned char)0xEB);
6762 emit_int8((unsigned char)(0xC0 | encode));
6763 }
6764
6765 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
6766 assert(VM_Version::supports_evex(), "");
6767 // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
6768 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6769 attributes.set_is_evex_instruction();
6770 attributes.set_embedded_opmask_register_specifier(mask);
6771 if (merge) {
6772 attributes.reset_is_clear_context();
6773 }
6774 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6775 emit_int8((unsigned char)0xEB);
6776 emit_int8((unsigned char)(0xC0 | encode));
6777 }
6778
6779 void Assembler::evpord(XMMRegister dst, KRegister mask, XMMRegister nds, Address src, bool merge, int vector_len) {
6780 assert(VM_Version::supports_evex(), "");
6781 // Encoding: EVEX.NDS.XXX.66.0F.W0 EB /r
6782 InstructionMark im(this);
6783 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6784 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
6785 attributes.set_is_evex_instruction();
6786 attributes.set_embedded_opmask_register_specifier(mask);
6787 if (merge) {
6788 attributes.reset_is_clear_context();
6789 }
6790 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6791 emit_int8((unsigned char)0xEB);
6792 emit_operand(dst, src);
6793 }
6794
6795 void Assembler::pxor(XMMRegister dst, XMMRegister src) {
6796 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
6797 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6798 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6799 emit_int8((unsigned char)0xEF);
6800 emit_int8((unsigned char)(0xC0 | encode));
6801 }
6802
6803 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6804 assert(UseAVX > 0, "requires some form of AVX");
6805 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6806 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6807 emit_int8((unsigned char)0xEF);
6808 emit_int8((unsigned char)(0xC0 | encode));
6809 }
6810
6811 void Assembler::vpxor(XMMRegister dst, XMMRegister nds, Address src, int vector_len) {
6812 assert(UseAVX > 0, "requires some form of AVX");
6813 InstructionMark im(this);
6814 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6815 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_32bit);
6816 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6817 emit_int8((unsigned char)0xEF);
6818 emit_operand(dst, src);
6819 }
6820
6821 void Assembler::vpxorq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
6822 assert(UseAVX > 2, "requires some form of EVEX");
6823 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6824 attributes.set_rex_vex_w_reverted();
6825 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6826 emit_int8((unsigned char)0xEF);
6827 emit_int8((unsigned char)(0xC0 | encode));
6828 }
6829
6830 void Assembler::evpxord(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
6831 assert(VM_Version::supports_evex(), "");
6832 // Encoding: EVEX.NDS.XXX.66.0F.W0 EF /r
6833 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
6834 attributes.set_is_evex_instruction();
6835 attributes.set_embedded_opmask_register_specifier(mask);
6836 if (merge) {
6837 attributes.reset_is_clear_context();
6838 }
6839 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
6840 emit_int8((unsigned char)0xEF);
6841 emit_int8((unsigned char)(0xC0 | encode));
6842 }
6843
6844 // vinserti forms
6845
6846 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6847 assert(VM_Version::supports_avx2(), "");
6848 assert(imm8 <= 0x01, "imm8: %u", imm8);
6849 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6850 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6851 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6852 emit_int8(0x38);
6853 emit_int8((unsigned char)(0xC0 | encode));
6854 // 0x00 - insert into lower 128 bits
6855 // 0x01 - insert into upper 128 bits
6856 emit_int8(imm8 & 0x01);
6857 }
6858
6859 void Assembler::vinserti128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6860 assert(VM_Version::supports_avx2(), "");
6861 assert(dst != xnoreg, "sanity");
6862 assert(imm8 <= 0x01, "imm8: %u", imm8);
6863 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6864 InstructionMark im(this);
6865 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6866 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6867 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6868 emit_int8(0x38);
6869 emit_operand(dst, src);
6870 // 0x00 - insert into lower 128 bits
6871 // 0x01 - insert into upper 128 bits
6872 emit_int8(imm8 & 0x01);
6873 }
6874
6875 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6876 assert(VM_Version::supports_evex(), "");
6877 assert(imm8 <= 0x03, "imm8: %u", imm8);
6878 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6879 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6880 emit_int8(0x38);
6881 emit_int8((unsigned char)(0xC0 | encode));
6882 // 0x00 - insert into q0 128 bits (0..127)
6883 // 0x01 - insert into q1 128 bits (128..255)
6884 // 0x02 - insert into q2 128 bits (256..383)
6885 // 0x03 - insert into q3 128 bits (384..511)
6886 emit_int8(imm8 & 0x03);
6887 }
6888
6889 void Assembler::vinserti32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6890 assert(VM_Version::supports_avx(), "");
6891 assert(dst != xnoreg, "sanity");
6892 assert(imm8 <= 0x03, "imm8: %u", imm8);
6893 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6894 InstructionMark im(this);
6895 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6896 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6897 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6898 emit_int8(0x18);
6899 emit_operand(dst, src);
6900 // 0x00 - insert into q0 128 bits (0..127)
6901 // 0x01 - insert into q1 128 bits (128..255)
6902 // 0x02 - insert into q2 128 bits (256..383)
6903 // 0x03 - insert into q3 128 bits (384..511)
6904 emit_int8(imm8 & 0x03);
6905 }
6906
6907 void Assembler::vinserti64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6908 assert(VM_Version::supports_evex(), "");
6909 assert(imm8 <= 0x01, "imm8: %u", imm8);
6910 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6911 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6912 emit_int8(0x38);
6913 emit_int8((unsigned char)(0xC0 | encode));
6914 // 0x00 - insert into lower 256 bits
6915 // 0x01 - insert into upper 256 bits
6916 emit_int8(imm8 & 0x01);
6917 }
6918
6919
6920 // vinsertf forms
6921
6922 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6923 assert(VM_Version::supports_avx(), "");
6924 assert(imm8 <= 0x01, "imm8: %u", imm8);
6925 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6926 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6927 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6928 emit_int8(0x18);
6929 emit_int8((unsigned char)(0xC0 | encode));
6930 // 0x00 - insert into lower 128 bits
6931 // 0x01 - insert into upper 128 bits
6932 emit_int8(imm8 & 0x01);
6933 }
6934
6935 void Assembler::vinsertf128(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6936 assert(VM_Version::supports_avx(), "");
6937 assert(dst != xnoreg, "sanity");
6938 assert(imm8 <= 0x01, "imm8: %u", imm8);
6939 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
6940 InstructionMark im(this);
6941 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6942 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6943 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6944 emit_int8(0x18);
6945 emit_operand(dst, src);
6946 // 0x00 - insert into lower 128 bits
6947 // 0x01 - insert into upper 128 bits
6948 emit_int8(imm8 & 0x01);
6949 }
6950
6951 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6952 assert(VM_Version::supports_evex(), "");
6953 assert(imm8 <= 0x03, "imm8: %u", imm8);
6954 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6955 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6956 emit_int8(0x18);
6957 emit_int8((unsigned char)(0xC0 | encode));
6958 // 0x00 - insert into q0 128 bits (0..127)
6959 // 0x01 - insert into q1 128 bits (128..255)
6960 // 0x02 - insert into q2 128 bits (256..383)
6961 // 0x03 - insert into q3 128 bits (384..511)
6962 emit_int8(imm8 & 0x03);
6963 }
6964
6965 void Assembler::vinsertf32x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6966 assert(VM_Version::supports_avx(), "");
6967 assert(dst != xnoreg, "sanity");
6968 assert(imm8 <= 0x03, "imm8: %u", imm8);
6969 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
6970 InstructionMark im(this);
6971 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6972 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
6973 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6974 emit_int8(0x18);
6975 emit_operand(dst, src);
6976 // 0x00 - insert into q0 128 bits (0..127)
6977 // 0x01 - insert into q1 128 bits (128..255)
6978 // 0x02 - insert into q2 128 bits (256..383)
6979 // 0x03 - insert into q3 128 bits (384..511)
6980 emit_int8(imm8 & 0x03);
6981 }
6982
6983 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, XMMRegister src, uint8_t imm8) {
6984 assert(VM_Version::supports_evex(), "");
6985 assert(imm8 <= 0x01, "imm8: %u", imm8);
6986 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
6987 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
6988 emit_int8(0x1A);
6989 emit_int8((unsigned char)(0xC0 | encode));
6990 // 0x00 - insert into lower 256 bits
6991 // 0x01 - insert into upper 256 bits
6992 emit_int8(imm8 & 0x01);
6993 }
6994
6995 void Assembler::vinsertf64x4(XMMRegister dst, XMMRegister nds, Address src, uint8_t imm8) {
6996 assert(VM_Version::supports_evex(), "");
6997 assert(dst != xnoreg, "sanity");
6998 assert(imm8 <= 0x01, "imm8: %u", imm8);
6999 InstructionMark im(this);
7000 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7001 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_64bit);
7002 vex_prefix(src, nds->encoding(), dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7003 emit_int8(0x1A);
7004 emit_operand(dst, src);
7005 // 0x00 - insert into lower 256 bits
7006 // 0x01 - insert into upper 256 bits
7007 emit_int8(imm8 & 0x01);
7008 }
7009
7010
7011 // vextracti forms
7012
7013 void Assembler::vextracti128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7014 assert(VM_Version::supports_avx(), "");
7015 assert(imm8 <= 0x01, "imm8: %u", imm8);
7016 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7017 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7018 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7019 emit_int8(0x39);
7020 emit_int8((unsigned char)(0xC0 | encode));
7021 // 0x00 - extract from lower 128 bits
7022 // 0x01 - extract from upper 128 bits
7023 emit_int8(imm8 & 0x01);
7024 }
7025
7026 void Assembler::vextracti128(Address dst, XMMRegister src, uint8_t imm8) {
7027 assert(VM_Version::supports_avx2(), "");
7028 assert(src != xnoreg, "sanity");
7029 assert(imm8 <= 0x01, "imm8: %u", imm8);
7030 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7031 InstructionMark im(this);
7032 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7033 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7034 attributes.reset_is_clear_context();
7035 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7036 emit_int8(0x39);
7037 emit_operand(src, dst);
7038 // 0x00 - extract from lower 128 bits
7039 // 0x01 - extract from upper 128 bits
7040 emit_int8(imm8 & 0x01);
7041 }
7042
7043 void Assembler::vextracti32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7044 assert(VM_Version::supports_avx(), "");
7045 assert(imm8 <= 0x03, "imm8: %u", imm8);
7046 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
7047 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7048 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7049 emit_int8(0x39);
7050 emit_int8((unsigned char)(0xC0 | encode));
7051 // 0x00 - extract from bits 127:0
7052 // 0x01 - extract from bits 255:128
7053 // 0x02 - extract from bits 383:256
7054 // 0x03 - extract from bits 511:384
7055 emit_int8(imm8 & 0x03);
7056 }
7057
7058 void Assembler::vextracti32x4(Address dst, XMMRegister src, uint8_t imm8) {
7059 assert(VM_Version::supports_evex(), "");
7060 assert(src != xnoreg, "sanity");
7061 assert(imm8 <= 0x03, "imm8: %u", imm8);
7062 InstructionMark im(this);
7063 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7064 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7065 attributes.reset_is_clear_context();
7066 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7067 emit_int8(0x39);
7068 emit_operand(src, dst);
7069 // 0x00 - extract from bits 127:0
7070 // 0x01 - extract from bits 255:128
7071 // 0x02 - extract from bits 383:256
7072 // 0x03 - extract from bits 511:384
7073 emit_int8(imm8 & 0x03);
7074 }
7075
7076 void Assembler::vextracti64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7077 assert(VM_Version::supports_avx512dq(), "");
7078 assert(imm8 <= 0x03, "imm8: %u", imm8);
7079 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7080 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7081 emit_int8(0x39);
7082 emit_int8((unsigned char)(0xC0 | encode));
7083 // 0x00 - extract from bits 127:0
7084 // 0x01 - extract from bits 255:128
7085 // 0x02 - extract from bits 383:256
7086 // 0x03 - extract from bits 511:384
7087 emit_int8(imm8 & 0x03);
7088 }
7089
7090 void Assembler::vextracti64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7091 assert(VM_Version::supports_evex(), "");
7092 assert(imm8 <= 0x01, "imm8: %u", imm8);
7093 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7094 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7095 emit_int8(0x3B);
7096 emit_int8((unsigned char)(0xC0 | encode));
7097 // 0x00 - extract from lower 256 bits
7098 // 0x01 - extract from upper 256 bits
7099 emit_int8(imm8 & 0x01);
7100 }
7101
7102
7103 // vextractf forms
7104
7105 void Assembler::vextractf128(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7106 assert(VM_Version::supports_avx(), "");
7107 assert(imm8 <= 0x01, "imm8: %u", imm8);
7108 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7109 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7110 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7111 emit_int8(0x19);
7112 emit_int8((unsigned char)(0xC0 | encode));
7113 // 0x00 - extract from lower 128 bits
7114 // 0x01 - extract from upper 128 bits
7115 emit_int8(imm8 & 0x01);
7116 }
7117
7118 void Assembler::vextractf128(Address dst, XMMRegister src, uint8_t imm8) {
7119 assert(VM_Version::supports_avx(), "");
7120 assert(src != xnoreg, "sanity");
7121 assert(imm8 <= 0x01, "imm8: %u", imm8);
7122 int vector_len = VM_Version::supports_avx512novl() ? AVX_512bit : AVX_256bit;
7123 InstructionMark im(this);
7124 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7125 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7126 attributes.reset_is_clear_context();
7127 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7128 emit_int8(0x19);
7129 emit_operand(src, dst);
7130 // 0x00 - extract from lower 128 bits
7131 // 0x01 - extract from upper 128 bits
7132 emit_int8(imm8 & 0x01);
7133 }
7134
7135 void Assembler::vextractf32x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7136 assert(VM_Version::supports_avx(), "");
7137 assert(imm8 <= 0x03, "imm8: %u", imm8);
7138 int vector_len = VM_Version::supports_evex() ? AVX_512bit : AVX_256bit;
7139 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7140 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7141 emit_int8(0x19);
7142 emit_int8((unsigned char)(0xC0 | encode));
7143 // 0x00 - extract from bits 127:0
7144 // 0x01 - extract from bits 255:128
7145 // 0x02 - extract from bits 383:256
7146 // 0x03 - extract from bits 511:384
7147 emit_int8(imm8 & 0x03);
7148 }
7149
7150 void Assembler::vextractf32x4(Address dst, XMMRegister src, uint8_t imm8) {
7151 assert(VM_Version::supports_evex(), "");
7152 assert(src != xnoreg, "sanity");
7153 assert(imm8 <= 0x03, "imm8: %u", imm8);
7154 InstructionMark im(this);
7155 InstructionAttr attributes(AVX_512bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7156 attributes.set_address_attributes(/* tuple_type */ EVEX_T4, /* input_size_in_bits */ EVEX_32bit);
7157 attributes.reset_is_clear_context();
7158 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7159 emit_int8(0x19);
7160 emit_operand(src, dst);
7161 // 0x00 - extract from bits 127:0
7162 // 0x01 - extract from bits 255:128
7163 // 0x02 - extract from bits 383:256
7164 // 0x03 - extract from bits 511:384
7165 emit_int8(imm8 & 0x03);
7166 }
7167
7168 void Assembler::vextractf64x2(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7169 assert(VM_Version::supports_avx512dq(), "");
7170 assert(imm8 <= 0x03, "imm8: %u", imm8);
7171 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7172 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7173 emit_int8(0x19);
7174 emit_int8((unsigned char)(0xC0 | encode));
7175 // 0x00 - extract from bits 127:0
7176 // 0x01 - extract from bits 255:128
7177 // 0x02 - extract from bits 383:256
7178 // 0x03 - extract from bits 511:384
7179 emit_int8(imm8 & 0x03);
7180 }
7181
7182 void Assembler::vextractf64x4(XMMRegister dst, XMMRegister src, uint8_t imm8) {
7183 assert(VM_Version::supports_evex(), "");
7184 assert(imm8 <= 0x01, "imm8: %u", imm8);
7185 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7186 int encode = vex_prefix_and_encode(src->encoding(), 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7187 emit_int8(0x1B);
7188 emit_int8((unsigned char)(0xC0 | encode));
7189 // 0x00 - extract from lower 256 bits
7190 // 0x01 - extract from upper 256 bits
7191 emit_int8(imm8 & 0x01);
7192 }
7193
7194 void Assembler::vextractf64x4(Address dst, XMMRegister src, uint8_t imm8) {
7195 assert(VM_Version::supports_evex(), "");
7196 assert(src != xnoreg, "sanity");
7197 assert(imm8 <= 0x01, "imm8: %u", imm8);
7198 InstructionMark im(this);
7199 InstructionAttr attributes(AVX_512bit, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ false);
7200 attributes.set_address_attributes(/* tuple_type */ EVEX_T4,/* input_size_in_bits */ EVEX_64bit);
7201 attributes.reset_is_clear_context();
7202 vex_prefix(dst, 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7203 emit_int8(0x1B);
7204 emit_operand(src, dst);
7205 // 0x00 - extract from lower 256 bits
7206 // 0x01 - extract from upper 256 bits
7207 emit_int8(imm8 & 0x01);
7208 }
7209
7210
7211 // legacy word/dword replicate
7212 void Assembler::vpbroadcastw(XMMRegister dst, XMMRegister src) {
7213 assert(VM_Version::supports_avx2(), "");
7214 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7215 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7216 emit_int8(0x79);
7217 emit_int8((unsigned char)(0xC0 | encode));
7218 }
7219
7220 void Assembler::vpbroadcastd(XMMRegister dst, XMMRegister src) {
7221 assert(VM_Version::supports_avx2(), "");
7222 InstructionAttr attributes(AVX_256bit, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7223 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7224 emit_int8(0x58);
7225 emit_int8((unsigned char)(0xC0 | encode));
7226 }
7227
7228
7229 // xmm/mem sourced byte/word/dword/qword replicate
7230
7231 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7232 void Assembler::evpbroadcastb(XMMRegister dst, XMMRegister src, int vector_len) {
7233 assert(VM_Version::supports_evex(), "");
7234 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7235 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7236 emit_int8(0x78);
7237 emit_int8((unsigned char)(0xC0 | encode));
7238 }
7239
7240 void Assembler::evpbroadcastb(XMMRegister dst, Address src, int vector_len) {
7241 assert(VM_Version::supports_evex(), "");
7242 assert(dst != xnoreg, "sanity");
7243 InstructionMark im(this);
7244 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7245 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_8bit);
7246 // swap src<->dst for encoding
7247 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7248 emit_int8(0x78);
7249 emit_operand(dst, src);
7250 }
7251
7252 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7253 void Assembler::evpbroadcastw(XMMRegister dst, XMMRegister src, int vector_len) {
7254 assert(VM_Version::supports_evex(), "");
7255 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7256 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7257 emit_int8(0x79);
7258 emit_int8((unsigned char)(0xC0 | encode));
7259 }
7260
7261 void Assembler::evpbroadcastw(XMMRegister dst, Address src, int vector_len) {
7262 assert(VM_Version::supports_evex(), "");
7263 assert(dst != xnoreg, "sanity");
7264 InstructionMark im(this);
7265 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7266 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_16bit);
7267 // swap src<->dst for encoding
7268 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7269 emit_int8(0x79);
7270 emit_operand(dst, src);
7271 }
7272
7273 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
7274 void Assembler::evpbroadcastd(XMMRegister dst, XMMRegister src, int vector_len) {
7275 assert(VM_Version::supports_evex(), "");
7276 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7277 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7278 emit_int8(0x58);
7279 emit_int8((unsigned char)(0xC0 | encode));
7280 }
7281
7282 void Assembler::evpbroadcastd(XMMRegister dst, Address src, int vector_len) {
7283 assert(VM_Version::supports_evex(), "");
7284 assert(dst != xnoreg, "sanity");
7285 InstructionMark im(this);
7286 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7287 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
7288 // swap src<->dst for encoding
7289 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7290 emit_int8(0x58);
7291 emit_operand(dst, src);
7292 }
7293
7294 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
7295 void Assembler::evpbroadcastq(XMMRegister dst, XMMRegister src, int vector_len) {
7296 assert(VM_Version::supports_evex(), "");
7297 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7298 attributes.set_rex_vex_w_reverted();
7299 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7300 emit_int8(0x59);
7301 emit_int8((unsigned char)(0xC0 | encode));
7302 }
7303
7304 void Assembler::evpbroadcastq(XMMRegister dst, Address src, int vector_len) {
7305 assert(VM_Version::supports_evex(), "");
7306 assert(dst != xnoreg, "sanity");
7307 InstructionMark im(this);
7308 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7309 attributes.set_rex_vex_w_reverted();
7310 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7311 // swap src<->dst for encoding
7312 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7313 emit_int8(0x59);
7314 emit_operand(dst, src);
7315 }
7316
7317
7318 // scalar single/double precision replicate
7319
7320 // duplicate single precision data from src into programmed locations in dest : requires AVX512VL
7321 void Assembler::evpbroadcastss(XMMRegister dst, XMMRegister src, int vector_len) {
7322 assert(VM_Version::supports_evex(), "");
7323 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7324 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7325 emit_int8(0x18);
7326 emit_int8((unsigned char)(0xC0 | encode));
7327 }
7328
7329 void Assembler::evpbroadcastss(XMMRegister dst, Address src, int vector_len) {
7330 assert(VM_Version::supports_evex(), "");
7331 assert(dst != xnoreg, "sanity");
7332 InstructionMark im(this);
7333 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7334 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_32bit);
7335 // swap src<->dst for encoding
7336 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7337 emit_int8(0x18);
7338 emit_operand(dst, src);
7339 }
7340
7341 // duplicate double precision data from src into programmed locations in dest : requires AVX512VL
7342 void Assembler::evpbroadcastsd(XMMRegister dst, XMMRegister src, int vector_len) {
7343 assert(VM_Version::supports_evex(), "");
7344 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7345 attributes.set_rex_vex_w_reverted();
7346 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7347 emit_int8(0x19);
7348 emit_int8((unsigned char)(0xC0 | encode));
7349 }
7350
7351 void Assembler::evpbroadcastsd(XMMRegister dst, Address src, int vector_len) {
7352 assert(VM_Version::supports_evex(), "");
7353 assert(dst != xnoreg, "sanity");
7354 InstructionMark im(this);
7355 InstructionAttr attributes(vector_len, /* vex_w */ VM_Version::supports_evex(), /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7356 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
7357 attributes.set_rex_vex_w_reverted();
7358 // swap src<->dst for encoding
7359 vex_prefix(src, 0, dst->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7360 emit_int8(0x19);
7361 emit_operand(dst, src);
7362 }
7363
7364
7365 // gpr source broadcast forms
7366
7367 // duplicate 1-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7368 void Assembler::evpbroadcastb(XMMRegister dst, Register src, int vector_len) {
7369 assert(VM_Version::supports_evex(), "");
7370 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7371 attributes.set_is_evex_instruction();
7372 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7373 emit_int8(0x7A);
7374 emit_int8((unsigned char)(0xC0 | encode));
7375 }
7376
7377 // duplicate 2-byte integer data from src into programmed locations in dest : requires AVX512BW and AVX512VL
7378 void Assembler::evpbroadcastw(XMMRegister dst, Register src, int vector_len) {
7379 assert(VM_Version::supports_evex(), "");
7380 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ _legacy_mode_bw, /* no_mask_reg */ true, /* uses_vl */ true);
7381 attributes.set_is_evex_instruction();
7382 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7383 emit_int8(0x7B);
7384 emit_int8((unsigned char)(0xC0 | encode));
7385 }
7386
7387 // duplicate 4-byte integer data from src into programmed locations in dest : requires AVX512VL
7388 void Assembler::evpbroadcastd(XMMRegister dst, Register src, int vector_len) {
7389 assert(VM_Version::supports_evex(), "");
7390 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7391 attributes.set_is_evex_instruction();
7392 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7393 emit_int8(0x7C);
7394 emit_int8((unsigned char)(0xC0 | encode));
7395 }
7396
7397 // duplicate 8-byte integer data from src into programmed locations in dest : requires AVX512VL
7398 void Assembler::evpbroadcastq(XMMRegister dst, Register src, int vector_len) {
7399 assert(VM_Version::supports_evex(), "");
7400 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
7401 attributes.set_is_evex_instruction();
7402 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
7403 emit_int8(0x7C);
7404 emit_int8((unsigned char)(0xC0 | encode));
7405 }
7406
7407
7408 // Carry-Less Multiplication Quadword
7409 void Assembler::pclmulqdq(XMMRegister dst, XMMRegister src, int mask) {
7410 assert(VM_Version::supports_clmul(), "");
7411 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7412 int encode = simd_prefix_and_encode(dst, dst, src, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7413 emit_int8(0x44);
7414 emit_int8((unsigned char)(0xC0 | encode));
7415 emit_int8((unsigned char)mask);
7416 }
7417
7418 // Carry-Less Multiplication Quadword
7419 void Assembler::vpclmulqdq(XMMRegister dst, XMMRegister nds, XMMRegister src, int mask) {
7420 assert(VM_Version::supports_avx() && VM_Version::supports_clmul(), "");
7421 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
7422 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
7423 emit_int8(0x44);
7424 emit_int8((unsigned char)(0xC0 | encode));
7425 emit_int8((unsigned char)mask);
7426 }
7427
7428 void Assembler::vzeroupper() {
7429 if (VM_Version::supports_vzeroupper()) {
7430 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
7431 (void)vex_prefix_and_encode(0, 0, 0, VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
7432 emit_int8(0x77);
7433 }
7434 }
7435
7436 #ifndef _LP64
7437 // 32bit only pieces of the assembler
7438
7439 void Assembler::cmp_literal32(Register src1, int32_t imm32, RelocationHolder const& rspec) {
7440 // NO PREFIX AS NEVER 64BIT
7441 InstructionMark im(this);
7442 emit_int8((unsigned char)0x81);
7443 emit_int8((unsigned char)(0xF8 | src1->encoding()));
7444 emit_data(imm32, rspec, 0);
7445 }
7446
7447 void Assembler::cmp_literal32(Address src1, int32_t imm32, RelocationHolder const& rspec) {
7448 // NO PREFIX AS NEVER 64BIT (not even 32bit versions of 64bit regs
7449 InstructionMark im(this);
7450 emit_int8((unsigned char)0x81);
7451 emit_operand(rdi, src1);
7452 emit_data(imm32, rspec, 0);
7453 }
7454
7455 // The 64-bit (32bit platform) cmpxchg compares the value at adr with the contents of rdx:rax,
7456 // and stores rcx:rbx into adr if so; otherwise, the value at adr is loaded
7457 // into rdx:rax. The ZF is set if the compared values were equal, and cleared otherwise.
7458 void Assembler::cmpxchg8(Address adr) {
7459 InstructionMark im(this);
7460 emit_int8(0x0F);
7461 emit_int8((unsigned char)0xC7);
7462 emit_operand(rcx, adr);
7463 }
7464
7465 void Assembler::decl(Register dst) {
7466 // Don't use it directly. Use MacroAssembler::decrementl() instead.
7467 emit_int8(0x48 | dst->encoding());
7468 }
7469
7470 #endif // _LP64
7471
7472 // 64bit typically doesn't use the x87 but needs to for the trig funcs
7473
7474 void Assembler::fabs() {
7475 emit_int8((unsigned char)0xD9);
7476 emit_int8((unsigned char)0xE1);
7477 }
7478
7479 void Assembler::fadd(int i) {
7480 emit_farith(0xD8, 0xC0, i);
7481 }
7482
7483 void Assembler::fadd_d(Address src) {
7484 InstructionMark im(this);
7485 emit_int8((unsigned char)0xDC);
7486 emit_operand32(rax, src);
7487 }
7488
7489 void Assembler::fadd_s(Address src) {
7490 InstructionMark im(this);
7491 emit_int8((unsigned char)0xD8);
7492 emit_operand32(rax, src);
7493 }
7494
7495 void Assembler::fadda(int i) {
7496 emit_farith(0xDC, 0xC0, i);
7497 }
7498
7499 void Assembler::faddp(int i) {
7500 emit_farith(0xDE, 0xC0, i);
7501 }
7502
7503 void Assembler::fchs() {
7504 emit_int8((unsigned char)0xD9);
7505 emit_int8((unsigned char)0xE0);
7506 }
7507
7508 void Assembler::fcom(int i) {
7509 emit_farith(0xD8, 0xD0, i);
7510 }
7511
7512 void Assembler::fcomp(int i) {
7513 emit_farith(0xD8, 0xD8, i);
7514 }
7515
7516 void Assembler::fcomp_d(Address src) {
7517 InstructionMark im(this);
7518 emit_int8((unsigned char)0xDC);
7519 emit_operand32(rbx, src);
7520 }
7521
7522 void Assembler::fcomp_s(Address src) {
7523 InstructionMark im(this);
7524 emit_int8((unsigned char)0xD8);
7525 emit_operand32(rbx, src);
7526 }
7527
7528 void Assembler::fcompp() {
7529 emit_int8((unsigned char)0xDE);
7530 emit_int8((unsigned char)0xD9);
7531 }
7532
7533 void Assembler::fcos() {
7534 emit_int8((unsigned char)0xD9);
7535 emit_int8((unsigned char)0xFF);
7536 }
7537
7538 void Assembler::fdecstp() {
7539 emit_int8((unsigned char)0xD9);
7540 emit_int8((unsigned char)0xF6);
7541 }
7542
7543 void Assembler::fdiv(int i) {
7544 emit_farith(0xD8, 0xF0, i);
7545 }
7546
7547 void Assembler::fdiv_d(Address src) {
7548 InstructionMark im(this);
7549 emit_int8((unsigned char)0xDC);
7550 emit_operand32(rsi, src);
7551 }
7552
7553 void Assembler::fdiv_s(Address src) {
7554 InstructionMark im(this);
7555 emit_int8((unsigned char)0xD8);
7556 emit_operand32(rsi, src);
7557 }
7558
7559 void Assembler::fdiva(int i) {
7560 emit_farith(0xDC, 0xF8, i);
7561 }
7562
7563 // Note: The Intel manual (Pentium Processor User's Manual, Vol.3, 1994)
7564 // is erroneous for some of the floating-point instructions below.
7565
7566 void Assembler::fdivp(int i) {
7567 emit_farith(0xDE, 0xF8, i); // ST(0) <- ST(0) / ST(1) and pop (Intel manual wrong)
7568 }
7569
7570 void Assembler::fdivr(int i) {
7571 emit_farith(0xD8, 0xF8, i);
7572 }
7573
7574 void Assembler::fdivr_d(Address src) {
7575 InstructionMark im(this);
7576 emit_int8((unsigned char)0xDC);
7577 emit_operand32(rdi, src);
7578 }
7579
7580 void Assembler::fdivr_s(Address src) {
7581 InstructionMark im(this);
7582 emit_int8((unsigned char)0xD8);
7583 emit_operand32(rdi, src);
7584 }
7585
7586 void Assembler::fdivra(int i) {
7587 emit_farith(0xDC, 0xF0, i);
7588 }
7589
7590 void Assembler::fdivrp(int i) {
7591 emit_farith(0xDE, 0xF0, i); // ST(0) <- ST(1) / ST(0) and pop (Intel manual wrong)
7592 }
7593
7594 void Assembler::ffree(int i) {
7595 emit_farith(0xDD, 0xC0, i);
7596 }
7597
7598 void Assembler::fild_d(Address adr) {
7599 InstructionMark im(this);
7600 emit_int8((unsigned char)0xDF);
7601 emit_operand32(rbp, adr);
7602 }
7603
7604 void Assembler::fild_s(Address adr) {
7605 InstructionMark im(this);
7606 emit_int8((unsigned char)0xDB);
7607 emit_operand32(rax, adr);
7608 }
7609
7610 void Assembler::fincstp() {
7611 emit_int8((unsigned char)0xD9);
7612 emit_int8((unsigned char)0xF7);
7613 }
7614
7615 void Assembler::finit() {
7616 emit_int8((unsigned char)0x9B);
7617 emit_int8((unsigned char)0xDB);
7618 emit_int8((unsigned char)0xE3);
7619 }
7620
7621 void Assembler::fist_s(Address adr) {
7622 InstructionMark im(this);
7623 emit_int8((unsigned char)0xDB);
7624 emit_operand32(rdx, adr);
7625 }
7626
7627 void Assembler::fistp_d(Address adr) {
7628 InstructionMark im(this);
7629 emit_int8((unsigned char)0xDF);
7630 emit_operand32(rdi, adr);
7631 }
7632
7633 void Assembler::fistp_s(Address adr) {
7634 InstructionMark im(this);
7635 emit_int8((unsigned char)0xDB);
7636 emit_operand32(rbx, adr);
7637 }
7638
7639 void Assembler::fld1() {
7640 emit_int8((unsigned char)0xD9);
7641 emit_int8((unsigned char)0xE8);
7642 }
7643
7644 void Assembler::fld_d(Address adr) {
7645 InstructionMark im(this);
7646 emit_int8((unsigned char)0xDD);
7647 emit_operand32(rax, adr);
7648 }
7649
7650 void Assembler::fld_s(Address adr) {
7651 InstructionMark im(this);
7652 emit_int8((unsigned char)0xD9);
7653 emit_operand32(rax, adr);
7654 }
7655
7656
7657 void Assembler::fld_s(int index) {
7658 emit_farith(0xD9, 0xC0, index);
7659 }
7660
7661 void Assembler::fld_x(Address adr) {
7662 InstructionMark im(this);
7663 emit_int8((unsigned char)0xDB);
7664 emit_operand32(rbp, adr);
7665 }
7666
7667 void Assembler::fldcw(Address src) {
7668 InstructionMark im(this);
7669 emit_int8((unsigned char)0xD9);
7670 emit_operand32(rbp, src);
7671 }
7672
7673 void Assembler::fldenv(Address src) {
7674 InstructionMark im(this);
7675 emit_int8((unsigned char)0xD9);
7676 emit_operand32(rsp, src);
7677 }
7678
7679 void Assembler::fldlg2() {
7680 emit_int8((unsigned char)0xD9);
7681 emit_int8((unsigned char)0xEC);
7682 }
7683
7684 void Assembler::fldln2() {
7685 emit_int8((unsigned char)0xD9);
7686 emit_int8((unsigned char)0xED);
7687 }
7688
7689 void Assembler::fldz() {
7690 emit_int8((unsigned char)0xD9);
7691 emit_int8((unsigned char)0xEE);
7692 }
7693
7694 void Assembler::flog() {
7695 fldln2();
7696 fxch();
7697 fyl2x();
7698 }
7699
7700 void Assembler::flog10() {
7701 fldlg2();
7702 fxch();
7703 fyl2x();
7704 }
7705
7706 void Assembler::fmul(int i) {
7707 emit_farith(0xD8, 0xC8, i);
7708 }
7709
7710 void Assembler::fmul_d(Address src) {
7711 InstructionMark im(this);
7712 emit_int8((unsigned char)0xDC);
7713 emit_operand32(rcx, src);
7714 }
7715
7716 void Assembler::fmul_s(Address src) {
7717 InstructionMark im(this);
7718 emit_int8((unsigned char)0xD8);
7719 emit_operand32(rcx, src);
7720 }
7721
7722 void Assembler::fmula(int i) {
7723 emit_farith(0xDC, 0xC8, i);
7724 }
7725
7726 void Assembler::fmulp(int i) {
7727 emit_farith(0xDE, 0xC8, i);
7728 }
7729
7730 void Assembler::fnsave(Address dst) {
7731 InstructionMark im(this);
7732 emit_int8((unsigned char)0xDD);
7733 emit_operand32(rsi, dst);
7734 }
7735
7736 void Assembler::fnstcw(Address src) {
7737 InstructionMark im(this);
7738 emit_int8((unsigned char)0x9B);
7739 emit_int8((unsigned char)0xD9);
7740 emit_operand32(rdi, src);
7741 }
7742
7743 void Assembler::fnstsw_ax() {
7744 emit_int8((unsigned char)0xDF);
7745 emit_int8((unsigned char)0xE0);
7746 }
7747
7748 void Assembler::fprem() {
7749 emit_int8((unsigned char)0xD9);
7750 emit_int8((unsigned char)0xF8);
7751 }
7752
7753 void Assembler::fprem1() {
7754 emit_int8((unsigned char)0xD9);
7755 emit_int8((unsigned char)0xF5);
7756 }
7757
7758 void Assembler::frstor(Address src) {
7759 InstructionMark im(this);
7760 emit_int8((unsigned char)0xDD);
7761 emit_operand32(rsp, src);
7762 }
7763
7764 void Assembler::fsin() {
7765 emit_int8((unsigned char)0xD9);
7766 emit_int8((unsigned char)0xFE);
7767 }
7768
7769 void Assembler::fsqrt() {
7770 emit_int8((unsigned char)0xD9);
7771 emit_int8((unsigned char)0xFA);
7772 }
7773
7774 void Assembler::fst_d(Address adr) {
7775 InstructionMark im(this);
7776 emit_int8((unsigned char)0xDD);
7777 emit_operand32(rdx, adr);
7778 }
7779
7780 void Assembler::fst_s(Address adr) {
7781 InstructionMark im(this);
7782 emit_int8((unsigned char)0xD9);
7783 emit_operand32(rdx, adr);
7784 }
7785
7786 void Assembler::fstp_d(Address adr) {
7787 InstructionMark im(this);
7788 emit_int8((unsigned char)0xDD);
7789 emit_operand32(rbx, adr);
7790 }
7791
7792 void Assembler::fstp_d(int index) {
7793 emit_farith(0xDD, 0xD8, index);
7794 }
7795
7796 void Assembler::fstp_s(Address adr) {
7797 InstructionMark im(this);
7798 emit_int8((unsigned char)0xD9);
7799 emit_operand32(rbx, adr);
7800 }
7801
7802 void Assembler::fstp_x(Address adr) {
7803 InstructionMark im(this);
7804 emit_int8((unsigned char)0xDB);
7805 emit_operand32(rdi, adr);
7806 }
7807
7808 void Assembler::fsub(int i) {
7809 emit_farith(0xD8, 0xE0, i);
7810 }
7811
7812 void Assembler::fsub_d(Address src) {
7813 InstructionMark im(this);
7814 emit_int8((unsigned char)0xDC);
7815 emit_operand32(rsp, src);
7816 }
7817
7818 void Assembler::fsub_s(Address src) {
7819 InstructionMark im(this);
7820 emit_int8((unsigned char)0xD8);
7821 emit_operand32(rsp, src);
7822 }
7823
7824 void Assembler::fsuba(int i) {
7825 emit_farith(0xDC, 0xE8, i);
7826 }
7827
7828 void Assembler::fsubp(int i) {
7829 emit_farith(0xDE, 0xE8, i); // ST(0) <- ST(0) - ST(1) and pop (Intel manual wrong)
7830 }
7831
7832 void Assembler::fsubr(int i) {
7833 emit_farith(0xD8, 0xE8, i);
7834 }
7835
7836 void Assembler::fsubr_d(Address src) {
7837 InstructionMark im(this);
7838 emit_int8((unsigned char)0xDC);
7839 emit_operand32(rbp, src);
7840 }
7841
7842 void Assembler::fsubr_s(Address src) {
7843 InstructionMark im(this);
7844 emit_int8((unsigned char)0xD8);
7845 emit_operand32(rbp, src);
7846 }
7847
7848 void Assembler::fsubra(int i) {
7849 emit_farith(0xDC, 0xE0, i);
7850 }
7851
7852 void Assembler::fsubrp(int i) {
7853 emit_farith(0xDE, 0xE0, i); // ST(0) <- ST(1) - ST(0) and pop (Intel manual wrong)
7854 }
7855
7856 void Assembler::ftan() {
7857 emit_int8((unsigned char)0xD9);
7858 emit_int8((unsigned char)0xF2);
7859 emit_int8((unsigned char)0xDD);
7860 emit_int8((unsigned char)0xD8);
7861 }
7862
7863 void Assembler::ftst() {
7864 emit_int8((unsigned char)0xD9);
7865 emit_int8((unsigned char)0xE4);
7866 }
7867
7868 void Assembler::fucomi(int i) {
7869 // make sure the instruction is supported (introduced for P6, together with cmov)
7870 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7871 emit_farith(0xDB, 0xE8, i);
7872 }
7873
7874 void Assembler::fucomip(int i) {
7875 // make sure the instruction is supported (introduced for P6, together with cmov)
7876 guarantee(VM_Version::supports_cmov(), "illegal instruction");
7877 emit_farith(0xDF, 0xE8, i);
7878 }
7879
7880 void Assembler::fwait() {
7881 emit_int8((unsigned char)0x9B);
7882 }
7883
7884 void Assembler::fxch(int i) {
7885 emit_farith(0xD9, 0xC8, i);
7886 }
7887
7888 void Assembler::fyl2x() {
7889 emit_int8((unsigned char)0xD9);
7890 emit_int8((unsigned char)0xF1);
7891 }
7892
7893 void Assembler::frndint() {
7894 emit_int8((unsigned char)0xD9);
7895 emit_int8((unsigned char)0xFC);
7896 }
7897
7898 void Assembler::f2xm1() {
7899 emit_int8((unsigned char)0xD9);
7900 emit_int8((unsigned char)0xF0);
7901 }
7902
7903 void Assembler::fldl2e() {
7904 emit_int8((unsigned char)0xD9);
7905 emit_int8((unsigned char)0xEA);
7906 }
7907
7908 // SSE SIMD prefix byte values corresponding to VexSimdPrefix encoding.
7909 static int simd_pre[4] = { 0, 0x66, 0xF3, 0xF2 };
7910 // SSE opcode second byte values (first is 0x0F) corresponding to VexOpcode encoding.
7911 static int simd_opc[4] = { 0, 0, 0x38, 0x3A };
7912
7913 // Generate SSE legacy REX prefix and SIMD opcode based on VEX encoding.
7914 void Assembler::rex_prefix(Address adr, XMMRegister xreg, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7915 if (pre > 0) {
7916 emit_int8(simd_pre[pre]);
7917 }
7918 if (rex_w) {
7919 prefixq(adr, xreg);
7920 } else {
7921 prefix(adr, xreg);
7922 }
7923 if (opc > 0) {
7924 emit_int8(0x0F);
7925 int opc2 = simd_opc[opc];
7926 if (opc2 > 0) {
7927 emit_int8(opc2);
7928 }
7929 }
7930 }
7931
7932 int Assembler::rex_prefix_and_encode(int dst_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, bool rex_w) {
7933 if (pre > 0) {
7934 emit_int8(simd_pre[pre]);
7935 }
7936 int encode = (rex_w) ? prefixq_and_encode(dst_enc, src_enc) : prefix_and_encode(dst_enc, src_enc);
7937 if (opc > 0) {
7938 emit_int8(0x0F);
7939 int opc2 = simd_opc[opc];
7940 if (opc2 > 0) {
7941 emit_int8(opc2);
7942 }
7943 }
7944 return encode;
7945 }
7946
7947
7948 void Assembler::vex_prefix(bool vex_r, bool vex_b, bool vex_x, int nds_enc, VexSimdPrefix pre, VexOpcode opc) {
7949 int vector_len = _attributes->get_vector_len();
7950 bool vex_w = _attributes->is_rex_vex_w();
7951 if (vex_b || vex_x || vex_w || (opc == VEX_OPCODE_0F_38) || (opc == VEX_OPCODE_0F_3A)) {
7952 prefix(VEX_3bytes);
7953
7954 int byte1 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0);
7955 byte1 = (~byte1) & 0xE0;
7956 byte1 |= opc;
7957 emit_int8(byte1);
7958
7959 int byte2 = ((~nds_enc) & 0xf) << 3;
7960 byte2 |= (vex_w ? VEX_W : 0) | ((vector_len > 0) ? 4 : 0) | pre;
7961 emit_int8(byte2);
7962 } else {
7963 prefix(VEX_2bytes);
7964
7965 int byte1 = vex_r ? VEX_R : 0;
7966 byte1 = (~byte1) & 0x80;
7967 byte1 |= ((~nds_enc) & 0xf) << 3;
7968 byte1 |= ((vector_len > 0 ) ? 4 : 0) | pre;
7969 emit_int8(byte1);
7970 }
7971 }
7972
7973 // This is a 4 byte encoding
7974 void Assembler::evex_prefix(bool vex_r, bool vex_b, bool vex_x, bool evex_r, bool evex_v, int nds_enc, VexSimdPrefix pre, VexOpcode opc){
7975 // EVEX 0x62 prefix
7976 prefix(EVEX_4bytes);
7977 bool vex_w = _attributes->is_rex_vex_w();
7978 int evex_encoding = (vex_w ? VEX_W : 0);
7979 // EVEX.b is not currently used for broadcast of single element or data rounding modes
7980 _attributes->set_evex_encoding(evex_encoding);
7981
7982 // P0: byte 2, initialized to RXBR`00mm
7983 // instead of not'd
7984 int byte2 = (vex_r ? VEX_R : 0) | (vex_x ? VEX_X : 0) | (vex_b ? VEX_B : 0) | (evex_r ? EVEX_Rb : 0);
7985 byte2 = (~byte2) & 0xF0;
7986 // confine opc opcode extensions in mm bits to lower two bits
7987 // of form {0F, 0F_38, 0F_3A}
7988 byte2 |= opc;
7989 emit_int8(byte2);
7990
7991 // P1: byte 3 as Wvvvv1pp
7992 int byte3 = ((~nds_enc) & 0xf) << 3;
7993 // p[10] is always 1
7994 byte3 |= EVEX_F;
7995 byte3 |= (vex_w & 1) << 7;
7996 // confine pre opcode extensions in pp bits to lower two bits
7997 // of form {66, F3, F2}
7998 byte3 |= pre;
7999 emit_int8(byte3);
8000
8001 // P2: byte 4 as zL'Lbv'aaa
8002 // kregs are implemented in the low 3 bits as aaa (hard code k1, it will be initialized for now)
8003 int byte4 = (_attributes->is_no_reg_mask()) ?
8004 0 :
8005 _attributes->get_embedded_opmask_register_specifier();
8006 // EVEX.v` for extending EVEX.vvvv or VIDX
8007 byte4 |= (evex_v ? 0: EVEX_V);
8008 // third EXEC.b for broadcast actions
8009 byte4 |= (_attributes->is_extended_context() ? EVEX_Rb : 0);
8010 // fourth EVEX.L'L for vector length : 0 is 128, 1 is 256, 2 is 512, currently we do not support 1024
8011 byte4 |= ((_attributes->get_vector_len())& 0x3) << 5;
8012 // last is EVEX.z for zero/merge actions
8013 if (_attributes->is_no_reg_mask() == false) {
8014 byte4 |= (_attributes->is_clear_context() ? EVEX_Z : 0);
8015 }
8016 emit_int8(byte4);
8017 }
8018
8019 void Assembler::vex_prefix(Address adr, int nds_enc, int xreg_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
8020 bool vex_r = ((xreg_enc & 8) == 8) ? 1 : 0;
8021 bool vex_b = adr.base_needs_rex();
8022 bool vex_x = adr.index_needs_rex();
8023 set_attributes(attributes);
8024 attributes->set_current_assembler(this);
8025
8026 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
8027 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
8028 switch (attributes->get_vector_len()) {
8029 case AVX_128bit:
8030 case AVX_256bit:
8031 attributes->set_is_legacy_mode();
8032 break;
8033 }
8034 }
8035
8036 // For pure EVEX check and see if this instruction
8037 // is allowed in legacy mode and has resources which will
8038 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
8039 // else that field is set when we encode to EVEX
8040 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
8041 !_is_managed && !attributes->is_evex_instruction()) {
8042 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
8043 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
8044 if (check_register_bank) {
8045 // check nds_enc and xreg_enc for upper bank usage
8046 if (nds_enc < 16 && xreg_enc < 16) {
8047 attributes->set_is_legacy_mode();
8048 }
8049 } else {
8050 attributes->set_is_legacy_mode();
8051 }
8052 }
8053 }
8054
8055 _is_managed = false;
8056 if (UseAVX > 2 && !attributes->is_legacy_mode())
8057 {
8058 bool evex_r = (xreg_enc >= 16);
8059 bool evex_v = (nds_enc >= 16);
8060 attributes->set_is_evex_instruction();
8061 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
8062 } else {
8063 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
8064 attributes->set_rex_vex_w(false);
8065 }
8066 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
8067 }
8068 }
8069
8070 int Assembler::vex_prefix_and_encode(int dst_enc, int nds_enc, int src_enc, VexSimdPrefix pre, VexOpcode opc, InstructionAttr *attributes) {
8071 bool vex_r = ((dst_enc & 8) == 8) ? 1 : 0;
8072 bool vex_b = ((src_enc & 8) == 8) ? 1 : 0;
8073 bool vex_x = false;
8074 set_attributes(attributes);
8075 attributes->set_current_assembler(this);
8076 bool check_register_bank = NOT_IA32(true) IA32_ONLY(false);
8077
8078 // if vector length is turned off, revert to AVX for vectors smaller than 512-bit
8079 if (UseAVX > 2 && _legacy_mode_vl && attributes->uses_vl()) {
8080 switch (attributes->get_vector_len()) {
8081 case AVX_128bit:
8082 case AVX_256bit:
8083 if (check_register_bank) {
8084 if (dst_enc >= 16 || nds_enc >= 16 || src_enc >= 16) {
8085 // up propagate arithmetic instructions to meet RA requirements
8086 attributes->set_vector_len(AVX_512bit);
8087 } else {
8088 attributes->set_is_legacy_mode();
8089 }
8090 } else {
8091 attributes->set_is_legacy_mode();
8092 }
8093 break;
8094 }
8095 }
8096
8097 // For pure EVEX check and see if this instruction
8098 // is allowed in legacy mode and has resources which will
8099 // fit in it. Pure EVEX instructions will use set_is_evex_instruction in their definition,
8100 // else that field is set when we encode to EVEX
8101 if (UseAVX > 2 && !attributes->is_legacy_mode() &&
8102 !_is_managed && !attributes->is_evex_instruction()) {
8103 if (!_legacy_mode_vl && attributes->get_vector_len() != AVX_512bit) {
8104 if (check_register_bank) {
8105 // check dst_enc, nds_enc and src_enc for upper bank usage
8106 if (dst_enc < 16 && nds_enc < 16 && src_enc < 16) {
8107 attributes->set_is_legacy_mode();
8108 }
8109 } else {
8110 attributes->set_is_legacy_mode();
8111 }
8112 }
8113 }
8114
8115 _is_managed = false;
8116 if (UseAVX > 2 && !attributes->is_legacy_mode())
8117 {
8118 bool evex_r = (dst_enc >= 16);
8119 bool evex_v = (nds_enc >= 16);
8120 // can use vex_x as bank extender on rm encoding
8121 vex_x = (src_enc >= 16);
8122 attributes->set_is_evex_instruction();
8123 evex_prefix(vex_r, vex_b, vex_x, evex_r, evex_v, nds_enc, pre, opc);
8124 } else {
8125 if (UseAVX > 2 && attributes->is_rex_vex_w_reverted()) {
8126 attributes->set_rex_vex_w(false);
8127 }
8128 vex_prefix(vex_r, vex_b, vex_x, nds_enc, pre, opc);
8129 }
8130
8131 // return modrm byte components for operands
8132 return (((dst_enc & 7) << 3) | (src_enc & 7));
8133 }
8134
8135
8136 void Assembler::simd_prefix(XMMRegister xreg, XMMRegister nds, Address adr, VexSimdPrefix pre,
8137 VexOpcode opc, InstructionAttr *attributes) {
8138 if (UseAVX > 0) {
8139 int xreg_enc = xreg->encoding();
8140 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
8141 vex_prefix(adr, nds_enc, xreg_enc, pre, opc, attributes);
8142 } else {
8143 assert((nds == xreg) || (nds == xnoreg), "wrong sse encoding");
8144 rex_prefix(adr, xreg, pre, opc, attributes->is_rex_vex_w());
8145 }
8146 }
8147
8148 int Assembler::simd_prefix_and_encode(XMMRegister dst, XMMRegister nds, XMMRegister src, VexSimdPrefix pre,
8149 VexOpcode opc, InstructionAttr *attributes) {
8150 int dst_enc = dst->encoding();
8151 int src_enc = src->encoding();
8152 if (UseAVX > 0) {
8153 int nds_enc = nds->is_valid() ? nds->encoding() : 0;
8154 return vex_prefix_and_encode(dst_enc, nds_enc, src_enc, pre, opc, attributes);
8155 } else {
8156 assert((nds == dst) || (nds == src) || (nds == xnoreg), "wrong sse encoding");
8157 return rex_prefix_and_encode(dst_enc, src_enc, pre, opc, attributes->is_rex_vex_w());
8158 }
8159 }
8160
8161 void Assembler::vcmppd(XMMRegister dst, XMMRegister nds, XMMRegister src, int cop, int vector_len) {
8162 assert(VM_Version::supports_avx(), "");
8163 assert(!VM_Version::supports_evex(), "");
8164 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8165 int encode = simd_prefix_and_encode(dst, nds, src, VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8166 emit_int8((unsigned char)0xC2);
8167 emit_int8((unsigned char)(0xC0 | encode));
8168 emit_int8((unsigned char)(0x1F & cop));
8169 }
8170
8171 void Assembler::vblendvpd(XMMRegister dst, XMMRegister nds, XMMRegister src1, XMMRegister src2, int vector_len) {
8172 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
8173 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8174 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8175 emit_int8((unsigned char)0x4B);
8176 emit_int8((unsigned char)(0xC0 | encode));
8177 int src2_enc = src2->encoding();
8178 emit_int8((unsigned char)(0xF0 & src2_enc<<4));
8179 }
8180
8181 void Assembler::vpblendd(XMMRegister dst, XMMRegister nds, XMMRegister src, int imm8, int vector_len) {
8182 assert(VM_Version::supports_avx2(), "");
8183 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8184 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8185 emit_int8((unsigned char)0x02);
8186 emit_int8((unsigned char)(0xC0 | encode));
8187 emit_int8((unsigned char)imm8);
8188 }
8189
8190 void Assembler::vcmpps(XMMRegister dst, XMMRegister nds, XMMRegister src, int comparison, int vector_len) {
8191 assert(VM_Version::supports_avx(), "");
8192 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8193 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
8194 emit_int8((unsigned char)0xC2);
8195 emit_int8((unsigned char)(0xC0 | encode));
8196 emit_int8((unsigned char)comparison);
8197 }
8198
8199 void Assembler::evcmpps(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8200 ComparisonPredicateFP comparison, int vector_len) {
8201 assert(VM_Version::supports_evex(), "");
8202 // Encoding: EVEX.NDS.XXX.0F.W0 C2 /r ib
8203 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8204 attributes.set_is_evex_instruction();
8205 attributes.set_embedded_opmask_register_specifier(mask);
8206 attributes.reset_is_clear_context();
8207 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F, &attributes);
8208 emit_int8((unsigned char)0xC2);
8209 emit_int8((unsigned char)(0xC0 | encode));
8210 emit_int8((unsigned char)comparison);
8211 }
8212
8213 void Assembler::evcmppd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8214 ComparisonPredicateFP comparison, int vector_len) {
8215 assert(VM_Version::supports_evex(), "");
8216 // Encoding: EVEX.NDS.XXX.66.0F.W1 C2 /r ib
8217 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8218 attributes.set_is_evex_instruction();
8219 attributes.set_embedded_opmask_register_specifier(mask);
8220 attributes.reset_is_clear_context();
8221 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8222 emit_int8((unsigned char)0xC2);
8223 emit_int8((unsigned char)(0xC0 | encode));
8224 emit_int8((unsigned char)comparison);
8225 }
8226
8227 void Assembler::blendvps(XMMRegister dst, XMMRegister src) {
8228 assert(VM_Version::supports_sse4_1(), "");
8229 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
8230 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8231 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8232 emit_int8(0x14);
8233 emit_int8((unsigned char)(0xC0 | encode));
8234 }
8235
8236 void Assembler::blendvpd(XMMRegister dst, XMMRegister src) {
8237 assert(VM_Version::supports_sse4_1(), "");
8238 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
8239 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8240 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8241 emit_int8(0x15);
8242 emit_int8((unsigned char)(0xC0 | encode));
8243 }
8244
8245 void Assembler::pblendvb(XMMRegister dst, XMMRegister src) {
8246 assert(VM_Version::supports_sse4_1(), "");
8247 assert(UseAVX <= 0, "sse encoding is inconsistent with avx encoding");
8248 InstructionAttr attributes(AVX_128bit, /* rex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ false, /* uses_vl */ false);
8249 int encode = simd_prefix_and_encode(dst, xnoreg, src, VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8250 emit_int8(0x10);
8251 emit_int8((unsigned char)(0xC0 | encode));
8252 }
8253
8254 void Assembler::vblendvps(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len) {
8255 assert(UseAVX > 0 && (vector_len == AVX_128bit || vector_len == AVX_256bit), "");
8256 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8257 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8258 emit_int8((unsigned char)0x4A);
8259 emit_int8((unsigned char)(0xC0 | encode));
8260 int mask_enc = mask->encoding();
8261 emit_int8((unsigned char)(0xF0 & mask_enc<<4));
8262 }
8263
8264 void Assembler::vpcmpgtb(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8265 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
8266 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
8267 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8268 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8269 emit_int8((unsigned char)0x64);
8270 emit_int8((unsigned char)(0xC0 | encode));
8271 }
8272
8273 void Assembler::vpcmpgtw(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8274 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
8275 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
8276 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8277 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8278 emit_int8((unsigned char)0x65);
8279 emit_int8((unsigned char)(0xC0 | encode));
8280 }
8281
8282 void Assembler::vpcmpgtd(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8283 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
8284 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
8285 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8286 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
8287 emit_int8((unsigned char)0x66);
8288 emit_int8((unsigned char)(0xC0 | encode));
8289 }
8290
8291 void Assembler::vpcmpgtq(XMMRegister dst, XMMRegister nds, XMMRegister src, int vector_len) {
8292 assert(vector_len == AVX_128bit ? VM_Version::supports_avx() : VM_Version::supports_avx2(), "");
8293 assert(vector_len <= AVX_256bit, "evex encoding is different - has k register as dest");
8294 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ true);
8295 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8296 emit_int8((unsigned char)0x37);
8297 emit_int8((unsigned char)(0xC0 | encode));
8298 }
8299
8300 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8301 int comparison, int vector_len) {
8302 assert(VM_Version::supports_evex(), "");
8303 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8304 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
8305 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8306 attributes.set_is_evex_instruction();
8307 attributes.set_embedded_opmask_register_specifier(mask);
8308 attributes.reset_is_clear_context();
8309 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8310 emit_int8((unsigned char)0x1F);
8311 emit_int8((unsigned char)(0xC0 | encode));
8312 emit_int8((unsigned char)comparison);
8313 }
8314
8315 void Assembler::evpcmpd(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
8316 int comparison, int vector_len) {
8317 assert(VM_Version::supports_evex(), "");
8318 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8319 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 1F /r ib
8320 InstructionMark im(this);
8321 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8322 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
8323 attributes.set_is_evex_instruction();
8324 attributes.set_embedded_opmask_register_specifier(mask);
8325 attributes.reset_is_clear_context();
8326 int dst_enc = kdst->encoding();
8327 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8328 emit_int8((unsigned char)0x1F);
8329 emit_operand(as_Register(dst_enc), src);
8330 emit_int8((unsigned char)comparison);
8331 }
8332
8333 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8334 int comparison, int vector_len) {
8335 assert(VM_Version::supports_evex(), "");
8336 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8337 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
8338 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8339 attributes.set_is_evex_instruction();
8340 attributes.set_embedded_opmask_register_specifier(mask);
8341 attributes.reset_is_clear_context();
8342 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8343 emit_int8((unsigned char)0x1F);
8344 emit_int8((unsigned char)(0xC0 | encode));
8345 emit_int8((unsigned char)comparison);
8346 }
8347
8348 void Assembler::evpcmpq(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
8349 int comparison, int vector_len) {
8350 assert(VM_Version::supports_evex(), "");
8351 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8352 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 1F /r ib
8353 InstructionMark im(this);
8354 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8355 attributes.set_address_attributes(/* tuple_type */ EVEX_FV, /* input_size_in_bits */ EVEX_NObit);
8356 attributes.set_is_evex_instruction();
8357 attributes.set_embedded_opmask_register_specifier(mask);
8358 attributes.reset_is_clear_context();
8359 int dst_enc = kdst->encoding();
8360 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8361 emit_int8((unsigned char)0x1F);
8362 emit_operand(as_Register(dst_enc), src);
8363 emit_int8((unsigned char)comparison);
8364 }
8365
8366 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8367 int comparison, int vector_len) {
8368 assert(VM_Version::supports_evex(), "");
8369 assert(VM_Version::supports_avx512bw(), "");
8370 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8371 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
8372 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8373 attributes.set_is_evex_instruction();
8374 attributes.set_embedded_opmask_register_specifier(mask);
8375 attributes.reset_is_clear_context();
8376 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8377 emit_int8((unsigned char)0x3F);
8378 emit_int8((unsigned char)(0xC0 | encode));
8379 emit_int8((unsigned char)comparison);
8380 }
8381
8382 void Assembler::evpcmpb(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
8383 int comparison, int vector_len) {
8384 assert(VM_Version::supports_evex(), "");
8385 assert(VM_Version::supports_avx512bw(), "");
8386 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8387 // Encoding: EVEX.NDS.XXX.66.0F3A.W0 3F /r ib
8388 InstructionMark im(this);
8389 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8390 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
8391 attributes.set_is_evex_instruction();
8392 attributes.set_embedded_opmask_register_specifier(mask);
8393 attributes.reset_is_clear_context();
8394 int dst_enc = kdst->encoding();
8395 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8396 emit_int8((unsigned char)0x3F);
8397 emit_operand(as_Register(dst_enc), src);
8398 emit_int8((unsigned char)comparison);
8399 }
8400
8401 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, XMMRegister src,
8402 int comparison, int vector_len) {
8403 assert(VM_Version::supports_evex(), "");
8404 assert(VM_Version::supports_avx512bw(), "");
8405 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8406 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
8407 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8408 attributes.set_is_evex_instruction();
8409 attributes.set_embedded_opmask_register_specifier(mask);
8410 attributes.reset_is_clear_context();
8411 int encode = vex_prefix_and_encode(kdst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8412 emit_int8((unsigned char)0x3F);
8413 emit_int8((unsigned char)(0xC0 | encode));
8414 emit_int8((unsigned char)comparison);
8415 }
8416
8417 void Assembler::evpcmpw(KRegister kdst, KRegister mask, XMMRegister nds, Address src,
8418 int comparison, int vector_len) {
8419 assert(VM_Version::supports_evex(), "");
8420 assert(VM_Version::supports_avx512bw(), "");
8421 assert(comparison >= Assembler::eq && comparison <= Assembler::_true, "");
8422 // Encoding: EVEX.NDS.XXX.66.0F3A.W1 3F /r ib
8423 InstructionMark im(this);
8424 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8425 attributes.set_address_attributes(/* tuple_type */ EVEX_FVM, /* input_size_in_bits */ EVEX_NObit);
8426 attributes.set_is_evex_instruction();
8427 attributes.set_embedded_opmask_register_specifier(mask);
8428 attributes.reset_is_clear_context();
8429 int dst_enc = kdst->encoding();
8430 vex_prefix(src, nds->encoding(), dst_enc, VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8431 emit_int8((unsigned char)0x3F);
8432 emit_operand(as_Register(dst_enc), src);
8433 emit_int8((unsigned char)comparison);
8434 }
8435
8436 void Assembler::vpblendvb(XMMRegister dst, XMMRegister nds, XMMRegister src, XMMRegister mask, int vector_len) {
8437 assert(VM_Version::supports_avx(), "");
8438 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8439 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_3A, &attributes);
8440 emit_int8((unsigned char)0x4C);
8441 emit_int8((unsigned char)(0xC0 | encode));
8442 int mask_enc = mask->encoding();
8443 emit_int8((unsigned char)(0xF0 & mask_enc << 4));
8444 }
8445
8446 void Assembler::evblendmpd(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8447 assert(VM_Version::supports_evex(), "");
8448 // Encoding: EVEX.NDS.XXX.66.0F38.W1 65 /r
8449 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8450 attributes.set_is_evex_instruction();
8451 attributes.set_embedded_opmask_register_specifier(mask);
8452 if (merge) {
8453 attributes.reset_is_clear_context();
8454 }
8455 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8456 emit_int8((unsigned char)0x65);
8457 emit_int8((unsigned char)(0xC0 | encode));
8458 }
8459
8460 void Assembler::evblendmps(XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8461 assert(VM_Version::supports_evex(), "");
8462 // Encoding: EVEX.NDS.XXX.66.0F38.W0 65 /r
8463 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8464 attributes.set_is_evex_instruction();
8465 attributes.set_embedded_opmask_register_specifier(mask);
8466 if (merge) {
8467 attributes.reset_is_clear_context();
8468 }
8469 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8470 emit_int8((unsigned char)0x65);
8471 emit_int8((unsigned char)(0xC0 | encode));
8472 }
8473
8474 void Assembler::evpblendmb (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8475 assert(VM_Version::supports_evex(), "");
8476 assert(VM_Version::supports_avx512bw(), "");
8477 // Encoding: EVEX.NDS.512.66.0F38.W0 66 /r
8478 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8479 attributes.set_is_evex_instruction();
8480 attributes.set_embedded_opmask_register_specifier(mask);
8481 if (merge) {
8482 attributes.reset_is_clear_context();
8483 }
8484 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8485 emit_int8((unsigned char)0x66);
8486 emit_int8((unsigned char)(0xC0 | encode));
8487 }
8488
8489 void Assembler::evpblendmw (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8490 assert(VM_Version::supports_evex(), "");
8491 assert(VM_Version::supports_avx512bw(), "");
8492 // Encoding: EVEX.NDS.512.66.0F38.W1 66 /r
8493 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8494 attributes.set_is_evex_instruction();
8495 attributes.set_embedded_opmask_register_specifier(mask);
8496 if (merge) {
8497 attributes.reset_is_clear_context();
8498 }
8499 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8500 emit_int8((unsigned char)0x66);
8501 emit_int8((unsigned char)(0xC0 | encode));
8502 }
8503
8504 void Assembler::evpblendmd (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8505 assert(VM_Version::supports_evex(), "");
8506 //Encoding: EVEX.NDS.512.66.0F38.W0 64 /r
8507 InstructionAttr attributes(vector_len, /* vex_w */ false, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8508 attributes.set_is_evex_instruction();
8509 attributes.set_embedded_opmask_register_specifier(mask);
8510 if (merge) {
8511 attributes.reset_is_clear_context();
8512 }
8513 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8514 emit_int8((unsigned char)0x64);
8515 emit_int8((unsigned char)(0xC0 | encode));
8516 }
8517
8518 void Assembler::evpblendmq (XMMRegister dst, KRegister mask, XMMRegister nds, XMMRegister src, bool merge, int vector_len) {
8519 assert(VM_Version::supports_evex(), "");
8520 //Encoding: EVEX.NDS.512.66.0F38.W1 64 /r
8521 InstructionAttr attributes(vector_len, /* vex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ false, /* uses_vl */ true);
8522 attributes.set_is_evex_instruction();
8523 attributes.set_embedded_opmask_register_specifier(mask);
8524 if (merge) {
8525 attributes.reset_is_clear_context();
8526 }
8527 int encode = vex_prefix_and_encode(dst->encoding(), nds->encoding(), src->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8528 emit_int8((unsigned char)0x64);
8529 emit_int8((unsigned char)(0xC0 | encode));
8530 }
8531
8532 void Assembler::shlxl(Register dst, Register src1, Register src2) {
8533 assert(VM_Version::supports_bmi2(), "");
8534 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8535 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8536 emit_int8((unsigned char)0xF7);
8537 emit_int8((unsigned char)(0xC0 | encode));
8538 }
8539
8540 void Assembler::shlxq(Register dst, Register src1, Register src2) {
8541 assert(VM_Version::supports_bmi2(), "");
8542 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
8543 int encode = vex_prefix_and_encode(dst->encoding(), src2->encoding(), src1->encoding(), VEX_SIMD_66, VEX_OPCODE_0F_38, &attributes);
8544 emit_int8((unsigned char)0xF7);
8545 emit_int8((unsigned char)(0xC0 | encode));
8546 }
8547
8548 #ifndef _LP64
8549
8550 void Assembler::incl(Register dst) {
8551 // Don't use it directly. Use MacroAssembler::incrementl() instead.
8552 emit_int8(0x40 | dst->encoding());
8553 }
8554
8555 void Assembler::lea(Register dst, Address src) {
8556 leal(dst, src);
8557 }
8558
8559 void Assembler::mov_literal32(Address dst, int32_t imm32, RelocationHolder const& rspec) {
8560 InstructionMark im(this);
8561 emit_int8((unsigned char)0xC7);
8562 emit_operand(rax, dst);
8563 emit_data((int)imm32, rspec, 0);
8564 }
8565
8566 void Assembler::mov_literal32(Register dst, int32_t imm32, RelocationHolder const& rspec) {
8567 InstructionMark im(this);
8568 int encode = prefix_and_encode(dst->encoding());
8569 emit_int8((unsigned char)(0xB8 | encode));
8570 emit_data((int)imm32, rspec, 0);
8571 }
8572
8573 void Assembler::popa() { // 32bit
8574 emit_int8(0x61);
8575 }
8576
8577 void Assembler::push_literal32(int32_t imm32, RelocationHolder const& rspec) {
8578 InstructionMark im(this);
8579 emit_int8(0x68);
8580 emit_data(imm32, rspec, 0);
8581 }
8582
8583 void Assembler::pusha() { // 32bit
8584 emit_int8(0x60);
8585 }
8586
8587 void Assembler::set_byte_if_not_zero(Register dst) {
8588 emit_int8(0x0F);
8589 emit_int8((unsigned char)0x95);
8590 emit_int8((unsigned char)(0xE0 | dst->encoding()));
8591 }
8592
8593 void Assembler::shldl(Register dst, Register src) {
8594 emit_int8(0x0F);
8595 emit_int8((unsigned char)0xA5);
8596 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
8597 }
8598
8599 // 0F A4 / r ib
8600 void Assembler::shldl(Register dst, Register src, int8_t imm8) {
8601 emit_int8(0x0F);
8602 emit_int8((unsigned char)0xA4);
8603 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
8604 emit_int8(imm8);
8605 }
8606
8607 void Assembler::shrdl(Register dst, Register src) {
8608 emit_int8(0x0F);
8609 emit_int8((unsigned char)0xAD);
8610 emit_int8((unsigned char)(0xC0 | src->encoding() << 3 | dst->encoding()));
8611 }
8612
8613 #else // LP64
8614
8615 void Assembler::set_byte_if_not_zero(Register dst) {
8616 int enc = prefix_and_encode(dst->encoding(), true);
8617 emit_int8(0x0F);
8618 emit_int8((unsigned char)0x95);
8619 emit_int8((unsigned char)(0xE0 | enc));
8620 }
8621
8622 // 64bit only pieces of the assembler
8623 // This should only be used by 64bit instructions that can use rip-relative
8624 // it cannot be used by instructions that want an immediate value.
8625
8626 bool Assembler::reachable(AddressLiteral adr) {
8627 int64_t disp;
8628 // None will force a 64bit literal to the code stream. Likely a placeholder
8629 // for something that will be patched later and we need to certain it will
8630 // always be reachable.
8631 if (adr.reloc() == relocInfo::none) {
8632 return false;
8633 }
8634 if (adr.reloc() == relocInfo::internal_word_type) {
8635 // This should be rip relative and easily reachable.
8636 return true;
8637 }
8638 if (adr.reloc() == relocInfo::virtual_call_type ||
8639 adr.reloc() == relocInfo::opt_virtual_call_type ||
8640 adr.reloc() == relocInfo::static_call_type ||
8641 adr.reloc() == relocInfo::static_stub_type ) {
8642 // This should be rip relative within the code cache and easily
8643 // reachable until we get huge code caches. (At which point
8644 // ic code is going to have issues).
8645 return true;
8646 }
8647 if (adr.reloc() != relocInfo::external_word_type &&
8648 adr.reloc() != relocInfo::poll_return_type && // these are really external_word but need special
8649 adr.reloc() != relocInfo::poll_type && // relocs to identify them
8650 adr.reloc() != relocInfo::runtime_call_type ) {
8651 return false;
8652 }
8653
8654 // Stress the correction code
8655 if (ForceUnreachable) {
8656 // Must be runtimecall reloc, see if it is in the codecache
8657 // Flipping stuff in the codecache to be unreachable causes issues
8658 // with things like inline caches where the additional instructions
8659 // are not handled.
8660 if (CodeCache::find_blob(adr._target) == NULL) {
8661 return false;
8662 }
8663 }
8664 // For external_word_type/runtime_call_type if it is reachable from where we
8665 // are now (possibly a temp buffer) and where we might end up
8666 // anywhere in the codeCache then we are always reachable.
8667 // This would have to change if we ever save/restore shared code
8668 // to be more pessimistic.
8669 disp = (int64_t)adr._target - ((int64_t)CodeCache::low_bound() + sizeof(int));
8670 if (!is_simm32(disp)) return false;
8671 disp = (int64_t)adr._target - ((int64_t)CodeCache::high_bound() + sizeof(int));
8672 if (!is_simm32(disp)) return false;
8673
8674 disp = (int64_t)adr._target - ((int64_t)pc() + sizeof(int));
8675
8676 // Because rip relative is a disp + address_of_next_instruction and we
8677 // don't know the value of address_of_next_instruction we apply a fudge factor
8678 // to make sure we will be ok no matter the size of the instruction we get placed into.
8679 // We don't have to fudge the checks above here because they are already worst case.
8680
8681 // 12 == override/rex byte, opcode byte, rm byte, sib byte, a 4-byte disp , 4-byte literal
8682 // + 4 because better safe than sorry.
8683 const int fudge = 12 + 4;
8684 if (disp < 0) {
8685 disp -= fudge;
8686 } else {
8687 disp += fudge;
8688 }
8689 return is_simm32(disp);
8690 }
8691
8692 // Check if the polling page is not reachable from the code cache using rip-relative
8693 // addressing.
8694 bool Assembler::is_polling_page_far() {
8695 intptr_t addr = (intptr_t)os::get_polling_page();
8696 return ForceUnreachable ||
8697 !is_simm32(addr - (intptr_t)CodeCache::low_bound()) ||
8698 !is_simm32(addr - (intptr_t)CodeCache::high_bound());
8699 }
8700
8701 void Assembler::emit_data64(jlong data,
8702 relocInfo::relocType rtype,
8703 int format) {
8704 if (rtype == relocInfo::none) {
8705 emit_int64(data);
8706 } else {
8707 emit_data64(data, Relocation::spec_simple(rtype), format);
8708 }
8709 }
8710
8711 void Assembler::emit_data64(jlong data,
8712 RelocationHolder const& rspec,
8713 int format) {
8714 assert(imm_operand == 0, "default format must be immediate in this file");
8715 assert(imm_operand == format, "must be immediate");
8716 assert(inst_mark() != NULL, "must be inside InstructionMark");
8717 // Do not use AbstractAssembler::relocate, which is not intended for
8718 // embedded words. Instead, relocate to the enclosing instruction.
8719 code_section()->relocate(inst_mark(), rspec, format);
8720 #ifdef ASSERT
8721 check_relocation(rspec, format);
8722 #endif
8723 emit_int64(data);
8724 }
8725
8726 int Assembler::prefix_and_encode(int reg_enc, bool byteinst) {
8727 if (reg_enc >= 8) {
8728 prefix(REX_B);
8729 reg_enc -= 8;
8730 } else if (byteinst && reg_enc >= 4) {
8731 prefix(REX);
8732 }
8733 return reg_enc;
8734 }
8735
8736 int Assembler::prefixq_and_encode(int reg_enc) {
8737 if (reg_enc < 8) {
8738 prefix(REX_W);
8739 } else {
8740 prefix(REX_WB);
8741 reg_enc -= 8;
8742 }
8743 return reg_enc;
8744 }
8745
8746 int Assembler::prefix_and_encode(int dst_enc, bool dst_is_byte, int src_enc, bool src_is_byte) {
8747 if (dst_enc < 8) {
8748 if (src_enc >= 8) {
8749 prefix(REX_B);
8750 src_enc -= 8;
8751 } else if ((src_is_byte && src_enc >= 4) || (dst_is_byte && dst_enc >= 4)) {
8752 prefix(REX);
8753 }
8754 } else {
8755 if (src_enc < 8) {
8756 prefix(REX_R);
8757 } else {
8758 prefix(REX_RB);
8759 src_enc -= 8;
8760 }
8761 dst_enc -= 8;
8762 }
8763 return dst_enc << 3 | src_enc;
8764 }
8765
8766 int Assembler::prefixq_and_encode(int dst_enc, int src_enc) {
8767 if (dst_enc < 8) {
8768 if (src_enc < 8) {
8769 prefix(REX_W);
8770 } else {
8771 prefix(REX_WB);
8772 src_enc -= 8;
8773 }
8774 } else {
8775 if (src_enc < 8) {
8776 prefix(REX_WR);
8777 } else {
8778 prefix(REX_WRB);
8779 src_enc -= 8;
8780 }
8781 dst_enc -= 8;
8782 }
8783 return dst_enc << 3 | src_enc;
8784 }
8785
8786 void Assembler::prefix(Register reg) {
8787 if (reg->encoding() >= 8) {
8788 prefix(REX_B);
8789 }
8790 }
8791
8792 void Assembler::prefix(Register dst, Register src, Prefix p) {
8793 if (src->encoding() >= 8) {
8794 p = (Prefix)(p | REX_B);
8795 }
8796 if (dst->encoding() >= 8) {
8797 p = (Prefix)( p | REX_R);
8798 }
8799 if (p != Prefix_EMPTY) {
8800 // do not generate an empty prefix
8801 prefix(p);
8802 }
8803 }
8804
8805 void Assembler::prefix(Register dst, Address adr, Prefix p) {
8806 if (adr.base_needs_rex()) {
8807 if (adr.index_needs_rex()) {
8808 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8809 } else {
8810 prefix(REX_B);
8811 }
8812 } else {
8813 if (adr.index_needs_rex()) {
8814 assert(false, "prefix(Register dst, Address adr, Prefix p) does not support handling of an X");
8815 }
8816 }
8817 if (dst->encoding() >= 8) {
8818 p = (Prefix)(p | REX_R);
8819 }
8820 if (p != Prefix_EMPTY) {
8821 // do not generate an empty prefix
8822 prefix(p);
8823 }
8824 }
8825
8826 void Assembler::prefix(Address adr) {
8827 if (adr.base_needs_rex()) {
8828 if (adr.index_needs_rex()) {
8829 prefix(REX_XB);
8830 } else {
8831 prefix(REX_B);
8832 }
8833 } else {
8834 if (adr.index_needs_rex()) {
8835 prefix(REX_X);
8836 }
8837 }
8838 }
8839
8840 void Assembler::prefixq(Address adr) {
8841 if (adr.base_needs_rex()) {
8842 if (adr.index_needs_rex()) {
8843 prefix(REX_WXB);
8844 } else {
8845 prefix(REX_WB);
8846 }
8847 } else {
8848 if (adr.index_needs_rex()) {
8849 prefix(REX_WX);
8850 } else {
8851 prefix(REX_W);
8852 }
8853 }
8854 }
8855
8856
8857 void Assembler::prefix(Address adr, Register reg, bool byteinst) {
8858 if (reg->encoding() < 8) {
8859 if (adr.base_needs_rex()) {
8860 if (adr.index_needs_rex()) {
8861 prefix(REX_XB);
8862 } else {
8863 prefix(REX_B);
8864 }
8865 } else {
8866 if (adr.index_needs_rex()) {
8867 prefix(REX_X);
8868 } else if (byteinst && reg->encoding() >= 4 ) {
8869 prefix(REX);
8870 }
8871 }
8872 } else {
8873 if (adr.base_needs_rex()) {
8874 if (adr.index_needs_rex()) {
8875 prefix(REX_RXB);
8876 } else {
8877 prefix(REX_RB);
8878 }
8879 } else {
8880 if (adr.index_needs_rex()) {
8881 prefix(REX_RX);
8882 } else {
8883 prefix(REX_R);
8884 }
8885 }
8886 }
8887 }
8888
8889 void Assembler::prefixq(Address adr, Register src) {
8890 if (src->encoding() < 8) {
8891 if (adr.base_needs_rex()) {
8892 if (adr.index_needs_rex()) {
8893 prefix(REX_WXB);
8894 } else {
8895 prefix(REX_WB);
8896 }
8897 } else {
8898 if (adr.index_needs_rex()) {
8899 prefix(REX_WX);
8900 } else {
8901 prefix(REX_W);
8902 }
8903 }
8904 } else {
8905 if (adr.base_needs_rex()) {
8906 if (adr.index_needs_rex()) {
8907 prefix(REX_WRXB);
8908 } else {
8909 prefix(REX_WRB);
8910 }
8911 } else {
8912 if (adr.index_needs_rex()) {
8913 prefix(REX_WRX);
8914 } else {
8915 prefix(REX_WR);
8916 }
8917 }
8918 }
8919 }
8920
8921 void Assembler::prefix(Address adr, XMMRegister reg) {
8922 if (reg->encoding() < 8) {
8923 if (adr.base_needs_rex()) {
8924 if (adr.index_needs_rex()) {
8925 prefix(REX_XB);
8926 } else {
8927 prefix(REX_B);
8928 }
8929 } else {
8930 if (adr.index_needs_rex()) {
8931 prefix(REX_X);
8932 }
8933 }
8934 } else {
8935 if (adr.base_needs_rex()) {
8936 if (adr.index_needs_rex()) {
8937 prefix(REX_RXB);
8938 } else {
8939 prefix(REX_RB);
8940 }
8941 } else {
8942 if (adr.index_needs_rex()) {
8943 prefix(REX_RX);
8944 } else {
8945 prefix(REX_R);
8946 }
8947 }
8948 }
8949 }
8950
8951 void Assembler::prefixq(Address adr, XMMRegister src) {
8952 if (src->encoding() < 8) {
8953 if (adr.base_needs_rex()) {
8954 if (adr.index_needs_rex()) {
8955 prefix(REX_WXB);
8956 } else {
8957 prefix(REX_WB);
8958 }
8959 } else {
8960 if (adr.index_needs_rex()) {
8961 prefix(REX_WX);
8962 } else {
8963 prefix(REX_W);
8964 }
8965 }
8966 } else {
8967 if (adr.base_needs_rex()) {
8968 if (adr.index_needs_rex()) {
8969 prefix(REX_WRXB);
8970 } else {
8971 prefix(REX_WRB);
8972 }
8973 } else {
8974 if (adr.index_needs_rex()) {
8975 prefix(REX_WRX);
8976 } else {
8977 prefix(REX_WR);
8978 }
8979 }
8980 }
8981 }
8982
8983 void Assembler::adcq(Register dst, int32_t imm32) {
8984 (void) prefixq_and_encode(dst->encoding());
8985 emit_arith(0x81, 0xD0, dst, imm32);
8986 }
8987
8988 void Assembler::adcq(Register dst, Address src) {
8989 InstructionMark im(this);
8990 prefixq(src, dst);
8991 emit_int8(0x13);
8992 emit_operand(dst, src);
8993 }
8994
8995 void Assembler::adcq(Register dst, Register src) {
8996 (void) prefixq_and_encode(dst->encoding(), src->encoding());
8997 emit_arith(0x13, 0xC0, dst, src);
8998 }
8999
9000 void Assembler::addq(Address dst, int32_t imm32) {
9001 InstructionMark im(this);
9002 prefixq(dst);
9003 emit_arith_operand(0x81, rax, dst,imm32);
9004 }
9005
9006 void Assembler::addq(Address dst, Register src) {
9007 InstructionMark im(this);
9008 prefixq(dst, src);
9009 emit_int8(0x01);
9010 emit_operand(src, dst);
9011 }
9012
9013 void Assembler::addq(Register dst, int32_t imm32) {
9014 (void) prefixq_and_encode(dst->encoding());
9015 emit_arith(0x81, 0xC0, dst, imm32);
9016 }
9017
9018 void Assembler::addq(Register dst, Address src) {
9019 InstructionMark im(this);
9020 prefixq(src, dst);
9021 emit_int8(0x03);
9022 emit_operand(dst, src);
9023 }
9024
9025 void Assembler::addq(Register dst, Register src) {
9026 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9027 emit_arith(0x03, 0xC0, dst, src);
9028 }
9029
9030 void Assembler::adcxq(Register dst, Register src) {
9031 //assert(VM_Version::supports_adx(), "adx instructions not supported");
9032 emit_int8((unsigned char)0x66);
9033 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9034 emit_int8(0x0F);
9035 emit_int8(0x38);
9036 emit_int8((unsigned char)0xF6);
9037 emit_int8((unsigned char)(0xC0 | encode));
9038 }
9039
9040 void Assembler::adoxq(Register dst, Register src) {
9041 //assert(VM_Version::supports_adx(), "adx instructions not supported");
9042 emit_int8((unsigned char)0xF3);
9043 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9044 emit_int8(0x0F);
9045 emit_int8(0x38);
9046 emit_int8((unsigned char)0xF6);
9047 emit_int8((unsigned char)(0xC0 | encode));
9048 }
9049
9050 void Assembler::andq(Address dst, int32_t imm32) {
9051 InstructionMark im(this);
9052 prefixq(dst);
9053 emit_int8((unsigned char)0x81);
9054 emit_operand(rsp, dst, 4);
9055 emit_int32(imm32);
9056 }
9057
9058 void Assembler::andq(Register dst, int32_t imm32) {
9059 (void) prefixq_and_encode(dst->encoding());
9060 emit_arith(0x81, 0xE0, dst, imm32);
9061 }
9062
9063 void Assembler::andq(Register dst, Address src) {
9064 InstructionMark im(this);
9065 prefixq(src, dst);
9066 emit_int8(0x23);
9067 emit_operand(dst, src);
9068 }
9069
9070 void Assembler::andq(Register dst, Register src) {
9071 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9072 emit_arith(0x23, 0xC0, dst, src);
9073 }
9074
9075 void Assembler::andnq(Register dst, Register src1, Register src2) {
9076 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9077 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9078 int encode = vex_prefix_and_encode(dst->encoding(), src1->encoding(), src2->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9079 emit_int8((unsigned char)0xF2);
9080 emit_int8((unsigned char)(0xC0 | encode));
9081 }
9082
9083 void Assembler::andnq(Register dst, Register src1, Address src2) {
9084 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9085 InstructionMark im(this);
9086 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9087 vex_prefix(src2, src1->encoding(), dst->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9088 emit_int8((unsigned char)0xF2);
9089 emit_operand(dst, src2);
9090 }
9091
9092 void Assembler::bsfq(Register dst, Register src) {
9093 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9094 emit_int8(0x0F);
9095 emit_int8((unsigned char)0xBC);
9096 emit_int8((unsigned char)(0xC0 | encode));
9097 }
9098
9099 void Assembler::bsrq(Register dst, Register src) {
9100 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9101 emit_int8(0x0F);
9102 emit_int8((unsigned char)0xBD);
9103 emit_int8((unsigned char)(0xC0 | encode));
9104 }
9105
9106 void Assembler::bswapq(Register reg) {
9107 int encode = prefixq_and_encode(reg->encoding());
9108 emit_int8(0x0F);
9109 emit_int8((unsigned char)(0xC8 | encode));
9110 }
9111
9112 void Assembler::blsiq(Register dst, Register src) {
9113 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9114 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9115 int encode = vex_prefix_and_encode(rbx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9116 emit_int8((unsigned char)0xF3);
9117 emit_int8((unsigned char)(0xC0 | encode));
9118 }
9119
9120 void Assembler::blsiq(Register dst, Address src) {
9121 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9122 InstructionMark im(this);
9123 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9124 vex_prefix(src, dst->encoding(), rbx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9125 emit_int8((unsigned char)0xF3);
9126 emit_operand(rbx, src);
9127 }
9128
9129 void Assembler::blsmskq(Register dst, Register src) {
9130 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9131 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9132 int encode = vex_prefix_and_encode(rdx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9133 emit_int8((unsigned char)0xF3);
9134 emit_int8((unsigned char)(0xC0 | encode));
9135 }
9136
9137 void Assembler::blsmskq(Register dst, Address src) {
9138 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9139 InstructionMark im(this);
9140 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9141 vex_prefix(src, dst->encoding(), rdx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9142 emit_int8((unsigned char)0xF3);
9143 emit_operand(rdx, src);
9144 }
9145
9146 void Assembler::blsrq(Register dst, Register src) {
9147 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9148 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9149 int encode = vex_prefix_and_encode(rcx->encoding(), dst->encoding(), src->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9150 emit_int8((unsigned char)0xF3);
9151 emit_int8((unsigned char)(0xC0 | encode));
9152 }
9153
9154 void Assembler::blsrq(Register dst, Address src) {
9155 assert(VM_Version::supports_bmi1(), "bit manipulation instructions not supported");
9156 InstructionMark im(this);
9157 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9158 vex_prefix(src, dst->encoding(), rcx->encoding(), VEX_SIMD_NONE, VEX_OPCODE_0F_38, &attributes);
9159 emit_int8((unsigned char)0xF3);
9160 emit_operand(rcx, src);
9161 }
9162
9163 void Assembler::cdqq() {
9164 prefix(REX_W);
9165 emit_int8((unsigned char)0x99);
9166 }
9167
9168 void Assembler::clflush(Address adr) {
9169 prefix(adr);
9170 emit_int8(0x0F);
9171 emit_int8((unsigned char)0xAE);
9172 emit_operand(rdi, adr);
9173 }
9174
9175 void Assembler::cmovq(Condition cc, Register dst, Register src) {
9176 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9177 emit_int8(0x0F);
9178 emit_int8(0x40 | cc);
9179 emit_int8((unsigned char)(0xC0 | encode));
9180 }
9181
9182 void Assembler::cmovq(Condition cc, Register dst, Address src) {
9183 InstructionMark im(this);
9184 prefixq(src, dst);
9185 emit_int8(0x0F);
9186 emit_int8(0x40 | cc);
9187 emit_operand(dst, src);
9188 }
9189
9190 void Assembler::cmpq(Address dst, int32_t imm32) {
9191 InstructionMark im(this);
9192 prefixq(dst);
9193 emit_int8((unsigned char)0x81);
9194 emit_operand(rdi, dst, 4);
9195 emit_int32(imm32);
9196 }
9197
9198 void Assembler::cmpq(Register dst, int32_t imm32) {
9199 (void) prefixq_and_encode(dst->encoding());
9200 emit_arith(0x81, 0xF8, dst, imm32);
9201 }
9202
9203 void Assembler::cmpq(Address dst, Register src) {
9204 InstructionMark im(this);
9205 prefixq(dst, src);
9206 emit_int8(0x3B);
9207 emit_operand(src, dst);
9208 }
9209
9210 void Assembler::cmpq(Register dst, Register src) {
9211 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9212 emit_arith(0x3B, 0xC0, dst, src);
9213 }
9214
9215 void Assembler::cmpq(Register dst, Address src) {
9216 InstructionMark im(this);
9217 prefixq(src, dst);
9218 emit_int8(0x3B);
9219 emit_operand(dst, src);
9220 }
9221
9222 void Assembler::cmpxchgq(Register reg, Address adr) {
9223 InstructionMark im(this);
9224 prefixq(adr, reg);
9225 emit_int8(0x0F);
9226 emit_int8((unsigned char)0xB1);
9227 emit_operand(reg, adr);
9228 }
9229
9230 void Assembler::cvtsi2sdq(XMMRegister dst, Register src) {
9231 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9232 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9233 int encode = simd_prefix_and_encode(dst, dst, as_XMMRegister(src->encoding()), VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
9234 emit_int8(0x2A);
9235 emit_int8((unsigned char)(0xC0 | encode));
9236 }
9237
9238 void Assembler::cvtsi2sdq(XMMRegister dst, Address src) {
9239 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9240 InstructionMark im(this);
9241 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9242 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
9243 simd_prefix(dst, dst, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
9244 emit_int8(0x2A);
9245 emit_operand(dst, src);
9246 }
9247
9248 void Assembler::cvtsi2ssq(XMMRegister dst, Address src) {
9249 NOT_LP64(assert(VM_Version::supports_sse(), ""));
9250 InstructionMark im(this);
9251 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9252 attributes.set_address_attributes(/* tuple_type */ EVEX_T1S, /* input_size_in_bits */ EVEX_64bit);
9253 simd_prefix(dst, dst, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
9254 emit_int8(0x2A);
9255 emit_operand(dst, src);
9256 }
9257
9258 void Assembler::cvttsd2siq(Register dst, XMMRegister src) {
9259 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9260 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9261 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F2, VEX_OPCODE_0F, &attributes);
9262 emit_int8(0x2C);
9263 emit_int8((unsigned char)(0xC0 | encode));
9264 }
9265
9266 void Assembler::cvttss2siq(Register dst, XMMRegister src) {
9267 NOT_LP64(assert(VM_Version::supports_sse(), ""));
9268 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9269 int encode = simd_prefix_and_encode(as_XMMRegister(dst->encoding()), xnoreg, src, VEX_SIMD_F3, VEX_OPCODE_0F, &attributes);
9270 emit_int8(0x2C);
9271 emit_int8((unsigned char)(0xC0 | encode));
9272 }
9273
9274 void Assembler::decl(Register dst) {
9275 // Don't use it directly. Use MacroAssembler::decrementl() instead.
9276 // Use two-byte form (one-byte form is a REX prefix in 64-bit mode)
9277 int encode = prefix_and_encode(dst->encoding());
9278 emit_int8((unsigned char)0xFF);
9279 emit_int8((unsigned char)(0xC8 | encode));
9280 }
9281
9282 void Assembler::decq(Register dst) {
9283 // Don't use it directly. Use MacroAssembler::decrementq() instead.
9284 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
9285 int encode = prefixq_and_encode(dst->encoding());
9286 emit_int8((unsigned char)0xFF);
9287 emit_int8(0xC8 | encode);
9288 }
9289
9290 void Assembler::decq(Address dst) {
9291 // Don't use it directly. Use MacroAssembler::decrementq() instead.
9292 InstructionMark im(this);
9293 prefixq(dst);
9294 emit_int8((unsigned char)0xFF);
9295 emit_operand(rcx, dst);
9296 }
9297
9298 void Assembler::fxrstor(Address src) {
9299 prefixq(src);
9300 emit_int8(0x0F);
9301 emit_int8((unsigned char)0xAE);
9302 emit_operand(as_Register(1), src);
9303 }
9304
9305 void Assembler::xrstor(Address src) {
9306 prefixq(src);
9307 emit_int8(0x0F);
9308 emit_int8((unsigned char)0xAE);
9309 emit_operand(as_Register(5), src);
9310 }
9311
9312 void Assembler::fxsave(Address dst) {
9313 prefixq(dst);
9314 emit_int8(0x0F);
9315 emit_int8((unsigned char)0xAE);
9316 emit_operand(as_Register(0), dst);
9317 }
9318
9319 void Assembler::xsave(Address dst) {
9320 prefixq(dst);
9321 emit_int8(0x0F);
9322 emit_int8((unsigned char)0xAE);
9323 emit_operand(as_Register(4), dst);
9324 }
9325
9326 void Assembler::idivq(Register src) {
9327 int encode = prefixq_and_encode(src->encoding());
9328 emit_int8((unsigned char)0xF7);
9329 emit_int8((unsigned char)(0xF8 | encode));
9330 }
9331
9332 void Assembler::imulq(Register dst, Register src) {
9333 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9334 emit_int8(0x0F);
9335 emit_int8((unsigned char)0xAF);
9336 emit_int8((unsigned char)(0xC0 | encode));
9337 }
9338
9339 void Assembler::imulq(Register dst, Register src, int value) {
9340 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9341 if (is8bit(value)) {
9342 emit_int8(0x6B);
9343 emit_int8((unsigned char)(0xC0 | encode));
9344 emit_int8(value & 0xFF);
9345 } else {
9346 emit_int8(0x69);
9347 emit_int8((unsigned char)(0xC0 | encode));
9348 emit_int32(value);
9349 }
9350 }
9351
9352 void Assembler::imulq(Register dst, Address src) {
9353 InstructionMark im(this);
9354 prefixq(src, dst);
9355 emit_int8(0x0F);
9356 emit_int8((unsigned char) 0xAF);
9357 emit_operand(dst, src);
9358 }
9359
9360 void Assembler::incl(Register dst) {
9361 // Don't use it directly. Use MacroAssembler::incrementl() instead.
9362 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
9363 int encode = prefix_and_encode(dst->encoding());
9364 emit_int8((unsigned char)0xFF);
9365 emit_int8((unsigned char)(0xC0 | encode));
9366 }
9367
9368 void Assembler::incq(Register dst) {
9369 // Don't use it directly. Use MacroAssembler::incrementq() instead.
9370 // Use two-byte form (one-byte from is a REX prefix in 64-bit mode)
9371 int encode = prefixq_and_encode(dst->encoding());
9372 emit_int8((unsigned char)0xFF);
9373 emit_int8((unsigned char)(0xC0 | encode));
9374 }
9375
9376 void Assembler::incq(Address dst) {
9377 // Don't use it directly. Use MacroAssembler::incrementq() instead.
9378 InstructionMark im(this);
9379 prefixq(dst);
9380 emit_int8((unsigned char)0xFF);
9381 emit_operand(rax, dst);
9382 }
9383
9384 void Assembler::lea(Register dst, Address src) {
9385 leaq(dst, src);
9386 }
9387
9388 void Assembler::leaq(Register dst, Address src) {
9389 InstructionMark im(this);
9390 prefixq(src, dst);
9391 emit_int8((unsigned char)0x8D);
9392 emit_operand(dst, src);
9393 }
9394
9395 void Assembler::mov64(Register dst, int64_t imm64) {
9396 InstructionMark im(this);
9397 int encode = prefixq_and_encode(dst->encoding());
9398 emit_int8((unsigned char)(0xB8 | encode));
9399 emit_int64(imm64);
9400 }
9401
9402 void Assembler::mov_literal64(Register dst, intptr_t imm64, RelocationHolder const& rspec) {
9403 InstructionMark im(this);
9404 int encode = prefixq_and_encode(dst->encoding());
9405 emit_int8(0xB8 | encode);
9406 emit_data64(imm64, rspec);
9407 }
9408
9409 void Assembler::mov_narrow_oop(Register dst, int32_t imm32, RelocationHolder const& rspec) {
9410 InstructionMark im(this);
9411 int encode = prefix_and_encode(dst->encoding());
9412 emit_int8((unsigned char)(0xB8 | encode));
9413 emit_data((int)imm32, rspec, narrow_oop_operand);
9414 }
9415
9416 void Assembler::mov_narrow_oop(Address dst, int32_t imm32, RelocationHolder const& rspec) {
9417 InstructionMark im(this);
9418 prefix(dst);
9419 emit_int8((unsigned char)0xC7);
9420 emit_operand(rax, dst, 4);
9421 emit_data((int)imm32, rspec, narrow_oop_operand);
9422 }
9423
9424 void Assembler::cmp_narrow_oop(Register src1, int32_t imm32, RelocationHolder const& rspec) {
9425 InstructionMark im(this);
9426 int encode = prefix_and_encode(src1->encoding());
9427 emit_int8((unsigned char)0x81);
9428 emit_int8((unsigned char)(0xF8 | encode));
9429 emit_data((int)imm32, rspec, narrow_oop_operand);
9430 }
9431
9432 void Assembler::cmp_narrow_oop(Address src1, int32_t imm32, RelocationHolder const& rspec) {
9433 InstructionMark im(this);
9434 prefix(src1);
9435 emit_int8((unsigned char)0x81);
9436 emit_operand(rax, src1, 4);
9437 emit_data((int)imm32, rspec, narrow_oop_operand);
9438 }
9439
9440 void Assembler::lzcntq(Register dst, Register src) {
9441 assert(VM_Version::supports_lzcnt(), "encoding is treated as BSR");
9442 emit_int8((unsigned char)0xF3);
9443 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9444 emit_int8(0x0F);
9445 emit_int8((unsigned char)0xBD);
9446 emit_int8((unsigned char)(0xC0 | encode));
9447 }
9448
9449 void Assembler::movdq(XMMRegister dst, Register src) {
9450 // table D-1 says MMX/SSE2
9451 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9452 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9453 int encode = simd_prefix_and_encode(dst, xnoreg, as_XMMRegister(src->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9454 emit_int8(0x6E);
9455 emit_int8((unsigned char)(0xC0 | encode));
9456 }
9457
9458 void Assembler::movdq(Register dst, XMMRegister src) {
9459 // table D-1 says MMX/SSE2
9460 NOT_LP64(assert(VM_Version::supports_sse2(), ""));
9461 InstructionAttr attributes(AVX_128bit, /* rex_w */ true, /* legacy_mode */ false, /* no_mask_reg */ true, /* uses_vl */ false);
9462 // swap src/dst to get correct prefix
9463 int encode = simd_prefix_and_encode(src, xnoreg, as_XMMRegister(dst->encoding()), VEX_SIMD_66, VEX_OPCODE_0F, &attributes);
9464 emit_int8(0x7E);
9465 emit_int8((unsigned char)(0xC0 | encode));
9466 }
9467
9468 void Assembler::movq(Register dst, Register src) {
9469 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9470 emit_int8((unsigned char)0x8B);
9471 emit_int8((unsigned char)(0xC0 | encode));
9472 }
9473
9474 void Assembler::movq(Register dst, Address src) {
9475 InstructionMark im(this);
9476 prefixq(src, dst);
9477 emit_int8((unsigned char)0x8B);
9478 emit_operand(dst, src);
9479 }
9480
9481 void Assembler::movq(Address dst, Register src) {
9482 InstructionMark im(this);
9483 prefixq(dst, src);
9484 emit_int8((unsigned char)0x89);
9485 emit_operand(src, dst);
9486 }
9487
9488 void Assembler::movsbq(Register dst, Address src) {
9489 InstructionMark im(this);
9490 prefixq(src, dst);
9491 emit_int8(0x0F);
9492 emit_int8((unsigned char)0xBE);
9493 emit_operand(dst, src);
9494 }
9495
9496 void Assembler::movsbq(Register dst, Register src) {
9497 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9498 emit_int8(0x0F);
9499 emit_int8((unsigned char)0xBE);
9500 emit_int8((unsigned char)(0xC0 | encode));
9501 }
9502
9503 void Assembler::movslq(Register dst, int32_t imm32) {
9504 // dbx shows movslq(rcx, 3) as movq $0x0000000049000000,(%rbx)
9505 // and movslq(r8, 3); as movl $0x0000000048000000,(%rbx)
9506 // as a result we shouldn't use until tested at runtime...
9507 ShouldNotReachHere();
9508 InstructionMark im(this);
9509 int encode = prefixq_and_encode(dst->encoding());
9510 emit_int8((unsigned char)(0xC7 | encode));
9511 emit_int32(imm32);
9512 }
9513
9514 void Assembler::movslq(Address dst, int32_t imm32) {
9515 assert(is_simm32(imm32), "lost bits");
9516 InstructionMark im(this);
9517 prefixq(dst);
9518 emit_int8((unsigned char)0xC7);
9519 emit_operand(rax, dst, 4);
9520 emit_int32(imm32);
9521 }
9522
9523 void Assembler::movslq(Register dst, Address src) {
9524 InstructionMark im(this);
9525 prefixq(src, dst);
9526 emit_int8(0x63);
9527 emit_operand(dst, src);
9528 }
9529
9530 void Assembler::movslq(Register dst, Register src) {
9531 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9532 emit_int8(0x63);
9533 emit_int8((unsigned char)(0xC0 | encode));
9534 }
9535
9536 void Assembler::movswq(Register dst, Address src) {
9537 InstructionMark im(this);
9538 prefixq(src, dst);
9539 emit_int8(0x0F);
9540 emit_int8((unsigned char)0xBF);
9541 emit_operand(dst, src);
9542 }
9543
9544 void Assembler::movswq(Register dst, Register src) {
9545 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9546 emit_int8((unsigned char)0x0F);
9547 emit_int8((unsigned char)0xBF);
9548 emit_int8((unsigned char)(0xC0 | encode));
9549 }
9550
9551 void Assembler::movzbq(Register dst, Address src) {
9552 InstructionMark im(this);
9553 prefixq(src, dst);
9554 emit_int8((unsigned char)0x0F);
9555 emit_int8((unsigned char)0xB6);
9556 emit_operand(dst, src);
9557 }
9558
9559 void Assembler::movzbq(Register dst, Register src) {
9560 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9561 emit_int8(0x0F);
9562 emit_int8((unsigned char)0xB6);
9563 emit_int8(0xC0 | encode);
9564 }
9565
9566 void Assembler::movzwq(Register dst, Address src) {
9567 InstructionMark im(this);
9568 prefixq(src, dst);
9569 emit_int8((unsigned char)0x0F);
9570 emit_int8((unsigned char)0xB7);
9571 emit_operand(dst, src);
9572 }
9573
9574 void Assembler::movzwq(Register dst, Register src) {
9575 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9576 emit_int8((unsigned char)0x0F);
9577 emit_int8((unsigned char)0xB7);
9578 emit_int8((unsigned char)(0xC0 | encode));
9579 }
9580
9581 void Assembler::mulq(Address src) {
9582 InstructionMark im(this);
9583 prefixq(src);
9584 emit_int8((unsigned char)0xF7);
9585 emit_operand(rsp, src);
9586 }
9587
9588 void Assembler::mulq(Register src) {
9589 int encode = prefixq_and_encode(src->encoding());
9590 emit_int8((unsigned char)0xF7);
9591 emit_int8((unsigned char)(0xE0 | encode));
9592 }
9593
9594 void Assembler::mulxq(Register dst1, Register dst2, Register src) {
9595 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9596 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9597 int encode = vex_prefix_and_encode(dst1->encoding(), dst2->encoding(), src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_38, &attributes);
9598 emit_int8((unsigned char)0xF6);
9599 emit_int8((unsigned char)(0xC0 | encode));
9600 }
9601
9602 void Assembler::negq(Register dst) {
9603 int encode = prefixq_and_encode(dst->encoding());
9604 emit_int8((unsigned char)0xF7);
9605 emit_int8((unsigned char)(0xD8 | encode));
9606 }
9607
9608 void Assembler::notq(Register dst) {
9609 int encode = prefixq_and_encode(dst->encoding());
9610 emit_int8((unsigned char)0xF7);
9611 emit_int8((unsigned char)(0xD0 | encode));
9612 }
9613
9614 void Assembler::orq(Address dst, int32_t imm32) {
9615 InstructionMark im(this);
9616 prefixq(dst);
9617 emit_int8((unsigned char)0x81);
9618 emit_operand(rcx, dst, 4);
9619 emit_int32(imm32);
9620 }
9621
9622 void Assembler::orq(Register dst, int32_t imm32) {
9623 (void) prefixq_and_encode(dst->encoding());
9624 emit_arith(0x81, 0xC8, dst, imm32);
9625 }
9626
9627 void Assembler::orq(Register dst, Address src) {
9628 InstructionMark im(this);
9629 prefixq(src, dst);
9630 emit_int8(0x0B);
9631 emit_operand(dst, src);
9632 }
9633
9634 void Assembler::orq(Register dst, Register src) {
9635 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9636 emit_arith(0x0B, 0xC0, dst, src);
9637 }
9638
9639 void Assembler::popa() { // 64bit
9640 movq(r15, Address(rsp, 0));
9641 movq(r14, Address(rsp, wordSize));
9642 movq(r13, Address(rsp, 2 * wordSize));
9643 movq(r12, Address(rsp, 3 * wordSize));
9644 movq(r11, Address(rsp, 4 * wordSize));
9645 movq(r10, Address(rsp, 5 * wordSize));
9646 movq(r9, Address(rsp, 6 * wordSize));
9647 movq(r8, Address(rsp, 7 * wordSize));
9648 movq(rdi, Address(rsp, 8 * wordSize));
9649 movq(rsi, Address(rsp, 9 * wordSize));
9650 movq(rbp, Address(rsp, 10 * wordSize));
9651 // skip rsp
9652 movq(rbx, Address(rsp, 12 * wordSize));
9653 movq(rdx, Address(rsp, 13 * wordSize));
9654 movq(rcx, Address(rsp, 14 * wordSize));
9655 movq(rax, Address(rsp, 15 * wordSize));
9656
9657 addq(rsp, 16 * wordSize);
9658 }
9659
9660 void Assembler::popcntq(Register dst, Address src) {
9661 assert(VM_Version::supports_popcnt(), "must support");
9662 InstructionMark im(this);
9663 emit_int8((unsigned char)0xF3);
9664 prefixq(src, dst);
9665 emit_int8((unsigned char)0x0F);
9666 emit_int8((unsigned char)0xB8);
9667 emit_operand(dst, src);
9668 }
9669
9670 void Assembler::popcntq(Register dst, Register src) {
9671 assert(VM_Version::supports_popcnt(), "must support");
9672 emit_int8((unsigned char)0xF3);
9673 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9674 emit_int8((unsigned char)0x0F);
9675 emit_int8((unsigned char)0xB8);
9676 emit_int8((unsigned char)(0xC0 | encode));
9677 }
9678
9679 void Assembler::popq(Address dst) {
9680 InstructionMark im(this);
9681 prefixq(dst);
9682 emit_int8((unsigned char)0x8F);
9683 emit_operand(rax, dst);
9684 }
9685
9686 void Assembler::pusha() { // 64bit
9687 // we have to store original rsp. ABI says that 128 bytes
9688 // below rsp are local scratch.
9689 movq(Address(rsp, -5 * wordSize), rsp);
9690
9691 subq(rsp, 16 * wordSize);
9692
9693 movq(Address(rsp, 15 * wordSize), rax);
9694 movq(Address(rsp, 14 * wordSize), rcx);
9695 movq(Address(rsp, 13 * wordSize), rdx);
9696 movq(Address(rsp, 12 * wordSize), rbx);
9697 // skip rsp
9698 movq(Address(rsp, 10 * wordSize), rbp);
9699 movq(Address(rsp, 9 * wordSize), rsi);
9700 movq(Address(rsp, 8 * wordSize), rdi);
9701 movq(Address(rsp, 7 * wordSize), r8);
9702 movq(Address(rsp, 6 * wordSize), r9);
9703 movq(Address(rsp, 5 * wordSize), r10);
9704 movq(Address(rsp, 4 * wordSize), r11);
9705 movq(Address(rsp, 3 * wordSize), r12);
9706 movq(Address(rsp, 2 * wordSize), r13);
9707 movq(Address(rsp, wordSize), r14);
9708 movq(Address(rsp, 0), r15);
9709 }
9710
9711 void Assembler::pushq(Address src) {
9712 InstructionMark im(this);
9713 prefixq(src);
9714 emit_int8((unsigned char)0xFF);
9715 emit_operand(rsi, src);
9716 }
9717
9718 void Assembler::rclq(Register dst, int imm8) {
9719 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9720 int encode = prefixq_and_encode(dst->encoding());
9721 if (imm8 == 1) {
9722 emit_int8((unsigned char)0xD1);
9723 emit_int8((unsigned char)(0xD0 | encode));
9724 } else {
9725 emit_int8((unsigned char)0xC1);
9726 emit_int8((unsigned char)(0xD0 | encode));
9727 emit_int8(imm8);
9728 }
9729 }
9730
9731 void Assembler::rcrq(Register dst, int imm8) {
9732 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9733 int encode = prefixq_and_encode(dst->encoding());
9734 if (imm8 == 1) {
9735 emit_int8((unsigned char)0xD1);
9736 emit_int8((unsigned char)(0xD8 | encode));
9737 } else {
9738 emit_int8((unsigned char)0xC1);
9739 emit_int8((unsigned char)(0xD8 | encode));
9740 emit_int8(imm8);
9741 }
9742 }
9743
9744 void Assembler::rorq(Register dst, int imm8) {
9745 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9746 int encode = prefixq_and_encode(dst->encoding());
9747 if (imm8 == 1) {
9748 emit_int8((unsigned char)0xD1);
9749 emit_int8((unsigned char)(0xC8 | encode));
9750 } else {
9751 emit_int8((unsigned char)0xC1);
9752 emit_int8((unsigned char)(0xc8 | encode));
9753 emit_int8(imm8);
9754 }
9755 }
9756
9757 void Assembler::rorxq(Register dst, Register src, int imm8) {
9758 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9759 InstructionAttr attributes(AVX_128bit, /* vex_w */ true, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9760 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9761 emit_int8((unsigned char)0xF0);
9762 emit_int8((unsigned char)(0xC0 | encode));
9763 emit_int8(imm8);
9764 }
9765
9766 void Assembler::rorxd(Register dst, Register src, int imm8) {
9767 assert(VM_Version::supports_bmi2(), "bit manipulation instructions not supported");
9768 InstructionAttr attributes(AVX_128bit, /* vex_w */ false, /* legacy_mode */ true, /* no_mask_reg */ true, /* uses_vl */ false);
9769 int encode = vex_prefix_and_encode(dst->encoding(), 0, src->encoding(), VEX_SIMD_F2, VEX_OPCODE_0F_3A, &attributes);
9770 emit_int8((unsigned char)0xF0);
9771 emit_int8((unsigned char)(0xC0 | encode));
9772 emit_int8(imm8);
9773 }
9774
9775 void Assembler::sarq(Register dst, int imm8) {
9776 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9777 int encode = prefixq_and_encode(dst->encoding());
9778 if (imm8 == 1) {
9779 emit_int8((unsigned char)0xD1);
9780 emit_int8((unsigned char)(0xF8 | encode));
9781 } else {
9782 emit_int8((unsigned char)0xC1);
9783 emit_int8((unsigned char)(0xF8 | encode));
9784 emit_int8(imm8);
9785 }
9786 }
9787
9788 void Assembler::sarq(Register dst) {
9789 int encode = prefixq_and_encode(dst->encoding());
9790 emit_int8((unsigned char)0xD3);
9791 emit_int8((unsigned char)(0xF8 | encode));
9792 }
9793
9794 void Assembler::sbbq(Address dst, int32_t imm32) {
9795 InstructionMark im(this);
9796 prefixq(dst);
9797 emit_arith_operand(0x81, rbx, dst, imm32);
9798 }
9799
9800 void Assembler::sbbq(Register dst, int32_t imm32) {
9801 (void) prefixq_and_encode(dst->encoding());
9802 emit_arith(0x81, 0xD8, dst, imm32);
9803 }
9804
9805 void Assembler::sbbq(Register dst, Address src) {
9806 InstructionMark im(this);
9807 prefixq(src, dst);
9808 emit_int8(0x1B);
9809 emit_operand(dst, src);
9810 }
9811
9812 void Assembler::sbbq(Register dst, Register src) {
9813 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9814 emit_arith(0x1B, 0xC0, dst, src);
9815 }
9816
9817 void Assembler::shlq(Register dst, int imm8) {
9818 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9819 int encode = prefixq_and_encode(dst->encoding());
9820 if (imm8 == 1) {
9821 emit_int8((unsigned char)0xD1);
9822 emit_int8((unsigned char)(0xE0 | encode));
9823 } else {
9824 emit_int8((unsigned char)0xC1);
9825 emit_int8((unsigned char)(0xE0 | encode));
9826 emit_int8(imm8);
9827 }
9828 }
9829
9830 void Assembler::shlq(Register dst) {
9831 int encode = prefixq_and_encode(dst->encoding());
9832 emit_int8((unsigned char)0xD3);
9833 emit_int8((unsigned char)(0xE0 | encode));
9834 }
9835
9836 void Assembler::shrq(Register dst, int imm8) {
9837 assert(isShiftCount(imm8 >> 1), "illegal shift count");
9838 int encode = prefixq_and_encode(dst->encoding());
9839 emit_int8((unsigned char)0xC1);
9840 emit_int8((unsigned char)(0xE8 | encode));
9841 emit_int8(imm8);
9842 }
9843
9844 void Assembler::shrq(Register dst) {
9845 int encode = prefixq_and_encode(dst->encoding());
9846 emit_int8((unsigned char)0xD3);
9847 emit_int8(0xE8 | encode);
9848 }
9849
9850 void Assembler::subq(Address dst, int32_t imm32) {
9851 InstructionMark im(this);
9852 prefixq(dst);
9853 emit_arith_operand(0x81, rbp, dst, imm32);
9854 }
9855
9856 void Assembler::subq(Address dst, Register src) {
9857 InstructionMark im(this);
9858 prefixq(dst, src);
9859 emit_int8(0x29);
9860 emit_operand(src, dst);
9861 }
9862
9863 void Assembler::subq(Register dst, int32_t imm32) {
9864 (void) prefixq_and_encode(dst->encoding());
9865 emit_arith(0x81, 0xE8, dst, imm32);
9866 }
9867
9868 // Force generation of a 4 byte immediate value even if it fits into 8bit
9869 void Assembler::subq_imm32(Register dst, int32_t imm32) {
9870 (void) prefixq_and_encode(dst->encoding());
9871 emit_arith_imm32(0x81, 0xE8, dst, imm32);
9872 }
9873
9874 void Assembler::subq(Register dst, Address src) {
9875 InstructionMark im(this);
9876 prefixq(src, dst);
9877 emit_int8(0x2B);
9878 emit_operand(dst, src);
9879 }
9880
9881 void Assembler::subq(Register dst, Register src) {
9882 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9883 emit_arith(0x2B, 0xC0, dst, src);
9884 }
9885
9886 void Assembler::testq(Register dst, int32_t imm32) {
9887 // not using emit_arith because test
9888 // doesn't support sign-extension of
9889 // 8bit operands
9890 int encode = dst->encoding();
9891 if (encode == 0) {
9892 prefix(REX_W);
9893 emit_int8((unsigned char)0xA9);
9894 } else {
9895 encode = prefixq_and_encode(encode);
9896 emit_int8((unsigned char)0xF7);
9897 emit_int8((unsigned char)(0xC0 | encode));
9898 }
9899 emit_int32(imm32);
9900 }
9901
9902 void Assembler::testq(Register dst, Register src) {
9903 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9904 emit_arith(0x85, 0xC0, dst, src);
9905 }
9906
9907 void Assembler::xaddq(Address dst, Register src) {
9908 InstructionMark im(this);
9909 prefixq(dst, src);
9910 emit_int8(0x0F);
9911 emit_int8((unsigned char)0xC1);
9912 emit_operand(src, dst);
9913 }
9914
9915 void Assembler::xchgq(Register dst, Address src) {
9916 InstructionMark im(this);
9917 prefixq(src, dst);
9918 emit_int8((unsigned char)0x87);
9919 emit_operand(dst, src);
9920 }
9921
9922 void Assembler::xchgq(Register dst, Register src) {
9923 int encode = prefixq_and_encode(dst->encoding(), src->encoding());
9924 emit_int8((unsigned char)0x87);
9925 emit_int8((unsigned char)(0xc0 | encode));
9926 }
9927
9928 void Assembler::xorq(Register dst, Register src) {
9929 (void) prefixq_and_encode(dst->encoding(), src->encoding());
9930 emit_arith(0x33, 0xC0, dst, src);
9931 }
9932
9933 void Assembler::xorq(Register dst, Address src) {
9934 InstructionMark im(this);
9935 prefixq(src, dst);
9936 emit_int8(0x33);
9937 emit_operand(dst, src);
9938 }
9939
9940 #endif // !LP64