src/hotspot/cpu/x86/x86.ad

*** 1304,1314 ****
    }
  
    return ret_value;  // Per default match rules are supported.
  }
  
! const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt) {
    // identify extra cases that we might want to provide match rules for
    // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
    bool ret_value = match_rule_supported(opcode);
    if (ret_value) {
      int size_in_bits = vlen * type2aelembytes(bt) * BitsPerByte;
--- 1304,1314 ----
    }
  
    return ret_value;  // Per default match rules are supported.
  }
  
! const bool Matcher::match_rule_supported_vector(int opcode, int vlen, BasicType bt, int meta) {
    // identify extra cases that we might want to provide match rules for
    // e.g. Op_ vector nodes and other intrinsics while guarding with vlen
    bool ret_value = match_rule_supported(opcode);
    if (ret_value) {
      int size_in_bits = vlen * type2aelembytes(bt) * BitsPerByte;
*** 1333,1342 ****
--- 1333,1354 ----
          case Op_MaxV:
          case Op_MinV:
            if ((UseSSE < 4 && (bt == T_BYTE || bt == T_INT)) || (UseAVX < 1 && bt == T_LONG))  
              ret_value = false;
            break;
+         case Op_LShiftVI:
+         case Op_RShiftVI:
+         case Op_URShiftVI:
+           if (meta == 2 && UseAVX <= 1)
+             ret_value  = false;
+           break;
+         case Op_LShiftVL:
+         case Op_RShiftVL:
+         case Op_URShiftVL:
+           if (meta == 2 && UseAVX <= 1)
+             ret_value  = false;
+           break;  
          case Op_URShiftVS:
          case Op_RShiftVS:
          case Op_LShiftVS:
          case Op_MulVS:
          case Op_AddVS:
*** 13045,13054 ****
--- 13057,13470 ----
    ins_pipe( pipe_slow );
  %}
  
  // There are no longs vector arithmetic right shift instructions.
  
+ // ------------------- Variable Bit Shift Left Logical -----------------------------
+ //Integer Variable left shift
+ instruct vsllv2I(vecD dst, vecD src, vecD shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 2 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVI src shift));
+   format %{ "vpsllvd  $dst,$src,$shift\t! variable bit shift left shift packed2I" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsllvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsllv4I_reg(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 4 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVI src shift));
+   format %{ "vpsllvd  $dst,$src,$shift\t! variable bit shift left shift packed4I" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsllvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsllv4I_reg_evex(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 4 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVI src shift));
+   format %{ "vpsllvd  $dst,$src,$shift\t! variable bit shift left shift packed4I" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsllvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsllv8I_reg(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 8 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVI src shift));
+   format %{ "vpsllvd  $dst,$src,$shift\t! variable bit shift left shift packed8I" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsllvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsllv8I_reg_evex(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 8 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVI src shift));
+   format %{ "vpsllvd  $dst,$src,$shift\t! variable bit shift left shift packed8I" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsllvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsllv16I_reg_evex(vecZ dst, vecZ src, vecZ shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 16 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVI src shift));
+   format %{ "vpsllvd  $dst,$src,$shift\t! variable bit shift left shift packed16I" %}
+   ins_encode %{
+     int vector_len = 2;
+     __ vpsllvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ //Long Variable left shift
+ instruct vsllv1L_reg(vecD dst, vecD src, vecD shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 1 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVL src shift));
+   format %{ "vpsllvq  $dst,$src,$shift\t! variable bit shift left shift packed1L" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsllvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsllv2L_reg(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 2 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVL src shift));
+   format %{ "vpsllvq  $dst,$src,$shift\t! variable bit shift left shift packed2L" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsllvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsllv2L_reg_evex(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 2 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVL src shift));
+   format %{ "vpsllvq  $dst,$src,$shift\t! variable bit shift left shift packed2L" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsllvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsllv4L_reg(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 4 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVL src shift));
+   format %{ "vpsllvq  $dst,$src,$shift\t! variable bit shift left shift packed4L" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsllvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsllv4L_reg_evex(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 8 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVL src shift));
+   format %{ "vpsllvq  $dst,$src,$shift\t! variable bit shift left shift packed4L" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsllvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsllv8L_reg_evex(vecZ dst, vecZ src, vecZ shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 8 && n->in(2)->Opcode() != Op_LShiftCntV);
+   match(Set dst (LShiftVL src shift));
+   format %{ "vpsllvq  $dst,$src,$shift\t! variable bit shift left shift packed16I" %}
+   ins_encode %{
+     int vector_len = 2;
+     __ vpsllvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ // ------------------- Variable Bit Shift Right Logical -----------------------------
+ //Integer Variable right shift
+ instruct vsrlv2I_reg(vecD dst, vecD src, vecD shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 2 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVI src shift));
+   format %{ "vpsrlvd  $dst,$src,$shift\t! variable bit shift right shift packed2I" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsrlvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrlv4I_reg(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 4 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVI src shift));
+   format %{ "vpsrlvd  $dst,$src,$shift\t! variable bit shift right shift packed4I" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsrlvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrlv4I_reg_evex(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 4 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVI src shift));
+   format %{ "vpsrlvd  $dst,$src,$shift\t! variable bit shift right shift packed4I" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsrlvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrlv8I_reg(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 8 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVI src shift));
+   format %{ "vpsrlvd  $dst,$src,$shift\t! variable bit shift right shift packed8I" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsrlvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrlv8I_reg_evex(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 8 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVI src shift));
+   format %{ "vpsrlvd  $dst,$src,$shift\t! variable bit shift right shift packed8I" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsrlvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrlv16I_reg_evex(vecZ dst, vecZ src, vecZ shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 16 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVI src shift));
+   format %{ "vpsrlvd  $dst,$src,$shift\t! variable bit shift right shift packed16I" %}
+   ins_encode %{
+     int vector_len = 2;
+     __ vpsrlvd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ //Long Variable right shift
+ instruct vsrlv1L_reg(vecD dst, vecD src, vecD shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 1 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVL src shift));
+   format %{ "vpsrlvq  $dst,$src,$shift\t! variable bit shift right shift packed1L" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsrlvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrlv2L_reg(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 2 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVL src shift));
+   format %{ "vpsrlvq  $dst,$src,$shift\t! variable bit shift right shift packed2L" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsrlvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrlv2L_reg_evex(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 2 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVL src shift));
+   format %{ "vpsrlvq  $dst,$src,$shift\t! variable bit shift right shift packed2L" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsrlvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrlv4L_reg(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 4 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVL src shift));
+   format %{ "vpsrlvq  $dst,$src,$shift\t! variable bit shift right shift packed4L" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsrlvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrlv4L_reg_evex(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 8 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVL src shift));
+   format %{ "vpsrlvq  $dst,$src,$shift\t! variable bit shift right shift packed4L" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsrlvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrlv8L_reg(vecZ dst, vecZ src, vecZ shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 8 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (URShiftVL src shift));
+   format %{ "vpsrlvq  $dst,$src,$shift\t! variable bit shift right shift packed8L" %}
+   ins_encode %{
+     int vector_len = 2;
+     __ vpsrlvq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ // ------------------- Variable Bit Shift Right Arithmetic -----------------------------
+ //Integer Variable right shift 
+ instruct vsrav2I_reg(vecD dst, vecD src, vecD shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 2 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVI src shift));
+   format %{ "vpsravd  $dst,$src,$shift\t! variable bit shift right shift packed2I" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsravd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrav4I_reg(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 4 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVI src shift));
+   format %{ "vpsravd  $dst,$src,$shift\t! variable bit shift right shift packed4I" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsravd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrav4I_reg_evex(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 4 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVI src shift));
+   format %{ "vpsravd  $dst,$src,$shift\t! variable bit shift right shift packed4I" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsravd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrav8I_reg(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 8 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVI src shift));
+   format %{ "vpsravd  $dst,$src,$shift\t! variable bit shift right shift packed8I" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsravd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrav8I_reg_evex(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 8 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVI src shift));
+   format %{ "vpsravd  $dst,$src,$shift\t! variable bit shift right shift packed8I" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsravd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrav16I_reg_evex(vecZ dst, vecZ src, vecZ shift) %{
+   predicate(UseAVX > 2 && n->as_Vector()->length() == 16 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVI src shift));
+   format %{ "vpsravd  $dst,$src,$shift\t! variable bit shift right shift packed16I" %}
+   ins_encode %{
+     int vector_len = 2;
+     __ vpsravd($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ //Long Variable right shift arithmetic
+ instruct vsrav1L_reg(vecD dst, vecD src, vecD shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 1 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVL src shift));
+   format %{ "vpsravq  $dst,$src,$shift\t! variable bit shift right shift packed1L" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsravq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrav2L_reg(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 2 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVL src shift));
+   format %{ "vpsravq  $dst,$src,$shift\t! variable bit shift right shift packed2L" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsravq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrav2L_reg_evex(vecX dst, vecX src, vecX shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 2 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVL src shift));
+   format %{ "vpsravq  $dst,$src,$shift\t! variable bit shift right shift packed2L" %}
+   ins_encode %{
+     int vector_len = 0;
+     __ vpsravq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrav4L_reg(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 4 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVL src shift));
+   format %{ "vpsravq  $dst,$src,$shift\t! variable bit shift right shift packed4L" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsravq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrav4L_reg_evex(vecY dst, vecY src, vecY shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 4 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVL src shift));
+   format %{ "vpsravq  $dst,$src,$shift\t! variable bit shift right shift packed4L" %}
+   ins_encode %{
+     int vector_len = 1;
+     __ vpsravq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
+ 
+ instruct vsrav8L_reg(vecZ dst, vecZ src, vecZ shift) %{
+   predicate(UseAVX > 1 && n->as_Vector()->length() == 8 && n->in(2)->Opcode() != Op_RShiftCntV);
+   match(Set dst (RShiftVL src shift));
+   format %{ "vpsravq  $dst,$src,$shift\t! variable bit shift right shift packed8L" %}
+   ins_encode %{
+     int vector_len = 2;
+     __ vpsravq($dst$$XMMRegister, $src$$XMMRegister, $shift$$XMMRegister, vector_len);
+   %}
+   ins_pipe( pipe_slow );
+ %}
  
  // --------------------------------- AND --------------------------------------
  
  instruct vand4B(vecS dst, vecS src) %{
    predicate(n->as_Vector()->length_in_bytes() == 4);