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 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
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 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
 * version 2 for more details (a copy is included in the LICENSE file that
 * accompanied this code).
 *
 * You should have received a copy of the GNU General Public License version
 * 2 along with this work; if not, write to the Free Software Foundation,
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#ifndef CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP
#define CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP

 private:

  //////////////////////////////////////////////////////////////////////////////////////////////////////////////////////////
  //
  // Sparc load/store emission
  //
  // The sparc ld/st instructions cannot accomodate displacements > 13 bits long.
  // The following "pseudo" sparc instructions (load/store) make it easier to use the indexed addressing mode
  // by allowing 32 bit displacements:
  //
  //    When disp <= 13 bits long, a single load or store instruction is emitted with (disp + [d]).
  //    When disp >  13 bits long, code is emitted to set the displacement into the O7 register,
  //       and then a load or store is emitted with ([O7] + [d]).
  //

  // some load/store variants return the code_offset for proper positioning of debug info for null checks

  // load/store with 32 bit displacement
  int load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
  void store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info = NULL);

  // loadf/storef with 32 bit displacement
  void load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
  void store(FloatRegister d, Register s1, int disp, BasicType st_type, CodeEmitInfo* info = NULL);

  // convienence methods for calling load/store with an Address
  void load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
  void store(Register d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);
  void load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL, int offset = 0);
  void store(FloatRegister d, const Address& a, BasicType st_type, CodeEmitInfo* info = NULL, int offset = 0);

  // convienence methods for calling load/store with an LIR_Address
  void load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo* info = NULL);
  void store(Register d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);
  void load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo* info = NULL);
  void store(FloatRegister d, LIR_Address* a, BasicType st_type, CodeEmitInfo* info = NULL);

  int store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned = false);
  int store(LIR_Opr from_reg, Register base, Register disp, BasicType type);

  int load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned = false);
  int load(Register base, Register disp, LIR_Opr to_reg, BasicType type);

  void monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no);

  int shift_amount(BasicType t);

  static bool is_single_instruction(LIR_Op* op);

  // Record the type of the receiver in ReceiverTypeData
  void type_profile_helper(Register mdo, int mdo_offset_bias,
                           ciMethodData *md, ciProfileData *data,
                           Register recv, Register tmp1, Label* update_done);
  // Setup pointers to MDO, MDO slot, also compute offset bias to access the slot.
  void setup_md_access(ciMethod* method, int bci,
                       ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias);
 public:
  void   pack64(LIR_Opr src, LIR_Opr dst);
  void unpack64(LIR_Opr src, LIR_Opr dst);

enum {
#ifdef _LP64
         call_stub_size = 68,
#else
         call_stub_size = 20,
#endif // _LP64
         exception_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4),
         deopt_handler_size = DEBUG_ONLY(1*K) NOT_DEBUG(10*4) };

#endif // CPU_SPARC_VM_C1_LIRASSEMBLER_SPARC_HPP