src/cpu/sparc/vm/assembler_sparc.inline.hpp

@@ -1,7 +1,7 @@
 /*
- * Copyright (c) 1997, 2009, Oracle and/or its affiliates. All rights reserved.
+ * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
  * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
  *
  * This code is free software; you can redistribute it and/or modify it
  * under the terms of the GNU General Public License version 2 only, as
  * published by the Free Software Foundation.

@@ -20,10 +20,18 @@
  * or visit www.oracle.com if you need additional information or have any
  * questions.
  *
  */
 
+#ifndef CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
+#define CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP
+
+#include "asm/assembler.inline.hpp"
+#include "asm/codeBuffer.hpp"
+#include "code/codeCache.hpp"
+#include "runtime/handles.inline.hpp"
+
 inline void MacroAssembler::pd_patch_instruction(address branch, address target) {
   jint& stub_inst = *(jint*) branch;
   stub_inst = patched_branch(target - branch, stub_inst, 0);
 }
 

@@ -815,5 +823,7 @@
     // Addendum.  Dave says that ldstub guarantees a write buffer flush to coherent
     // space.  Put one here to be on the safe side.
     Assembler::ldstub(SP, 0, G0);
   }
 }
+
+#endif // CPU_SPARC_VM_ASSEMBLER_SPARC_INLINE_HPP