1 /*
2 * Copyright (c) 2000, 2009, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 // native word offsets from memory address (big endian)
26 enum {
27 pd_lo_word_offset_in_bytes = BytesPerInt,
28 pd_hi_word_offset_in_bytes = 0
29 };
30
31
32 // explicit rounding operations are not required to implement the strictFP mode
33 enum {
34 pd_strict_fp_requires_explicit_rounding = false
35 };
36
37
38 // registers
39 enum {
40 pd_nof_cpu_regs_frame_map = 32, // number of registers used during code emission
41 pd_nof_caller_save_cpu_regs_frame_map = 10, // number of cpu registers killed by calls
42 pd_nof_cpu_regs_reg_alloc = 20, // number of registers that are visible to register allocator
43 pd_nof_cpu_regs_linearscan = 32,// number of registers visible linear scan
44 pd_first_cpu_reg = 0,
48 pd_last_callee_saved_reg = 13,
49
50 pd_nof_fpu_regs_frame_map = 32, // number of registers used during code emission
51 pd_nof_caller_save_fpu_regs_frame_map = 32, // number of fpu registers killed by calls
52 pd_nof_fpu_regs_reg_alloc = 32, // number of registers that are visible to register allocator
53 pd_nof_fpu_regs_linearscan = 32, // number of registers visible to linear scan
54 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
55 pd_last_fpu_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map - 1,
56
57 pd_nof_xmm_regs_linearscan = 0,
58 pd_nof_caller_save_xmm_regs = 0,
59 pd_first_xmm_reg = -1,
60 pd_last_xmm_reg = -1
61 };
62
63
64 // for debug info: a float value in a register is saved in single precision by runtime stubs
65 enum {
66 pd_float_saved_as_double = false
67 };
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1 /*
2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_SPARC_VM_C1_DEFS_SPARC_HPP
26 #define CPU_SPARC_VM_C1_DEFS_SPARC_HPP
27
28 // native word offsets from memory address (big endian)
29 enum {
30 pd_lo_word_offset_in_bytes = BytesPerInt,
31 pd_hi_word_offset_in_bytes = 0
32 };
33
34
35 // explicit rounding operations are not required to implement the strictFP mode
36 enum {
37 pd_strict_fp_requires_explicit_rounding = false
38 };
39
40
41 // registers
42 enum {
43 pd_nof_cpu_regs_frame_map = 32, // number of registers used during code emission
44 pd_nof_caller_save_cpu_regs_frame_map = 10, // number of cpu registers killed by calls
45 pd_nof_cpu_regs_reg_alloc = 20, // number of registers that are visible to register allocator
46 pd_nof_cpu_regs_linearscan = 32,// number of registers visible linear scan
47 pd_first_cpu_reg = 0,
51 pd_last_callee_saved_reg = 13,
52
53 pd_nof_fpu_regs_frame_map = 32, // number of registers used during code emission
54 pd_nof_caller_save_fpu_regs_frame_map = 32, // number of fpu registers killed by calls
55 pd_nof_fpu_regs_reg_alloc = 32, // number of registers that are visible to register allocator
56 pd_nof_fpu_regs_linearscan = 32, // number of registers visible to linear scan
57 pd_first_fpu_reg = pd_nof_cpu_regs_frame_map,
58 pd_last_fpu_reg = pd_nof_cpu_regs_frame_map + pd_nof_fpu_regs_frame_map - 1,
59
60 pd_nof_xmm_regs_linearscan = 0,
61 pd_nof_caller_save_xmm_regs = 0,
62 pd_first_xmm_reg = -1,
63 pd_last_xmm_reg = -1
64 };
65
66
67 // for debug info: a float value in a register is saved in single precision by runtime stubs
68 enum {
69 pd_float_saved_as_double = false
70 };
71
72 #endif // CPU_SPARC_VM_C1_DEFS_SPARC_HPP
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