1 /* 2 * Copyright (c) 1999, 2010, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 # include "incls/_precompiled.incl" 26 # include "incls/_c1_FrameMap_sparc.cpp.incl" 27 28 29 const int FrameMap::pd_c_runtime_reserved_arg_size = 7; 30 31 32 LIR_Opr FrameMap::map_to_opr(BasicType type, VMRegPair* reg, bool outgoing) { 33 LIR_Opr opr = LIR_OprFact::illegalOpr; 34 VMReg r_1 = reg->first(); 35 VMReg r_2 = reg->second(); 36 if (r_1->is_stack()) { 37 // Convert stack slot to an SP offset 38 // The calling convention does not count the SharedRuntime::out_preserve_stack_slots() value 39 // so we must add it in here. 40 int st_off = (r_1->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size; 41 opr = LIR_OprFact::address(new LIR_Address(SP_opr, st_off + STACK_BIAS, type)); 42 } else if (r_1->is_Register()) { 43 Register reg = r_1->as_Register(); 44 if (outgoing) { 45 assert(!reg->is_in(), "should be using I regs"); 46 } else { 47 assert(!reg->is_out(), "should be using O regs"); 48 } 49 if (r_2->is_Register() && (type == T_LONG || type == T_DOUBLE)) { 50 opr = as_long_opr(reg); 51 } else if (type == T_OBJECT || type == T_ARRAY) { 52 opr = as_oop_opr(reg); 53 } else { 54 opr = as_opr(reg); 55 } 56 } else if (r_1->is_FloatRegister()) { 57 assert(type == T_DOUBLE || type == T_FLOAT, "wrong type"); 58 FloatRegister f = r_1->as_FloatRegister(); 59 if (type == T_DOUBLE) { 60 opr = as_double_opr(f); 61 } else { 62 opr = as_float_opr(f); 63 } 64 } 65 return opr; 66 } 67 68 // FrameMap 69 //-------------------------------------------------------- 70 71 FloatRegister FrameMap::_fpu_regs [FrameMap::nof_fpu_regs]; 72 73 // some useful constant RInfo's: 74 LIR_Opr FrameMap::in_long_opr; 75 LIR_Opr FrameMap::out_long_opr; 76 LIR_Opr FrameMap::g1_long_single_opr; 77 78 LIR_Opr FrameMap::F0_opr; 79 LIR_Opr FrameMap::F0_double_opr; 80 81 LIR_Opr FrameMap::G0_opr; 82 LIR_Opr FrameMap::G1_opr; 83 LIR_Opr FrameMap::G2_opr; 84 LIR_Opr FrameMap::G3_opr; 85 LIR_Opr FrameMap::G4_opr; 86 LIR_Opr FrameMap::G5_opr; 87 LIR_Opr FrameMap::G6_opr; 88 LIR_Opr FrameMap::G7_opr; 89 LIR_Opr FrameMap::O0_opr; 90 LIR_Opr FrameMap::O1_opr; 91 LIR_Opr FrameMap::O2_opr; 92 LIR_Opr FrameMap::O3_opr; 93 LIR_Opr FrameMap::O4_opr; 94 LIR_Opr FrameMap::O5_opr; 95 LIR_Opr FrameMap::O6_opr; 96 LIR_Opr FrameMap::O7_opr; 97 LIR_Opr FrameMap::L0_opr; 98 LIR_Opr FrameMap::L1_opr; 99 LIR_Opr FrameMap::L2_opr; 100 LIR_Opr FrameMap::L3_opr; 101 LIR_Opr FrameMap::L4_opr; 102 LIR_Opr FrameMap::L5_opr; 103 LIR_Opr FrameMap::L6_opr; 104 LIR_Opr FrameMap::L7_opr; 105 LIR_Opr FrameMap::I0_opr; 106 LIR_Opr FrameMap::I1_opr; 107 LIR_Opr FrameMap::I2_opr; 108 LIR_Opr FrameMap::I3_opr; 109 LIR_Opr FrameMap::I4_opr; 110 LIR_Opr FrameMap::I5_opr; 111 LIR_Opr FrameMap::I6_opr; 112 LIR_Opr FrameMap::I7_opr; 113 114 LIR_Opr FrameMap::G0_oop_opr; 115 LIR_Opr FrameMap::G1_oop_opr; 116 LIR_Opr FrameMap::G2_oop_opr; 117 LIR_Opr FrameMap::G3_oop_opr; 118 LIR_Opr FrameMap::G4_oop_opr; 119 LIR_Opr FrameMap::G5_oop_opr; 120 LIR_Opr FrameMap::G6_oop_opr; 121 LIR_Opr FrameMap::G7_oop_opr; 122 LIR_Opr FrameMap::O0_oop_opr; 123 LIR_Opr FrameMap::O1_oop_opr; 124 LIR_Opr FrameMap::O2_oop_opr; 125 LIR_Opr FrameMap::O3_oop_opr; 126 LIR_Opr FrameMap::O4_oop_opr; 127 LIR_Opr FrameMap::O5_oop_opr; 128 LIR_Opr FrameMap::O6_oop_opr; 129 LIR_Opr FrameMap::O7_oop_opr; 130 LIR_Opr FrameMap::L0_oop_opr; 131 LIR_Opr FrameMap::L1_oop_opr; 132 LIR_Opr FrameMap::L2_oop_opr; 133 LIR_Opr FrameMap::L3_oop_opr; 134 LIR_Opr FrameMap::L4_oop_opr; 135 LIR_Opr FrameMap::L5_oop_opr; 136 LIR_Opr FrameMap::L6_oop_opr; 137 LIR_Opr FrameMap::L7_oop_opr; 138 LIR_Opr FrameMap::I0_oop_opr; 139 LIR_Opr FrameMap::I1_oop_opr; 140 LIR_Opr FrameMap::I2_oop_opr; 141 LIR_Opr FrameMap::I3_oop_opr; 142 LIR_Opr FrameMap::I4_oop_opr; 143 LIR_Opr FrameMap::I5_oop_opr; 144 LIR_Opr FrameMap::I6_oop_opr; 145 LIR_Opr FrameMap::I7_oop_opr; 146 147 LIR_Opr FrameMap::SP_opr; 148 LIR_Opr FrameMap::FP_opr; 149 150 LIR_Opr FrameMap::Oexception_opr; 151 LIR_Opr FrameMap::Oissuing_pc_opr; 152 153 LIR_Opr FrameMap::_caller_save_cpu_regs[] = { 0, }; 154 LIR_Opr FrameMap::_caller_save_fpu_regs[] = { 0, }; 155 156 157 FloatRegister FrameMap::nr2floatreg (int rnr) { 158 assert(_init_done, "tables not initialized"); 159 debug_only(fpu_range_check(rnr);) 160 return _fpu_regs[rnr]; 161 } 162 163 164 // returns true if reg could be smashed by a callee. 165 bool FrameMap::is_caller_save_register (LIR_Opr reg) { 166 if (reg->is_single_fpu() || reg->is_double_fpu()) { return true; } 167 if (reg->is_double_cpu()) { 168 return is_caller_save_register(reg->as_register_lo()) || 169 is_caller_save_register(reg->as_register_hi()); 170 } 171 return is_caller_save_register(reg->as_register()); 172 } 173 174 175 NEEDS_CLEANUP // once the new calling convention is enabled, we no 176 // longer need to treat I5, I4 and L0 specially 177 // Because the interpreter destroys caller's I5, I4 and L0, 178 // we must spill them before doing a Java call as we may land in 179 // interpreter. 180 bool FrameMap::is_caller_save_register (Register r) { 181 return (r->is_global() && (r != G0)) || r->is_out(); 182 } 183 184 185 void FrameMap::initialize() { 186 assert(!_init_done, "once"); 187 188 int i=0; 189 // Register usage: 190 // O6: sp 191 // I6: fp 192 // I7: return address 193 // G0: zero 194 // G2: thread 195 // G7: not available 196 // G6: not available 197 /* 0 */ map_register(i++, L0); 198 /* 1 */ map_register(i++, L1); 199 /* 2 */ map_register(i++, L2); 200 /* 3 */ map_register(i++, L3); 201 /* 4 */ map_register(i++, L4); 202 /* 5 */ map_register(i++, L5); 203 /* 6 */ map_register(i++, L6); 204 /* 7 */ map_register(i++, L7); 205 206 /* 8 */ map_register(i++, I0); 207 /* 9 */ map_register(i++, I1); 208 /* 10 */ map_register(i++, I2); 209 /* 11 */ map_register(i++, I3); 210 /* 12 */ map_register(i++, I4); 211 /* 13 */ map_register(i++, I5); 212 /* 14 */ map_register(i++, O0); 213 /* 15 */ map_register(i++, O1); 214 /* 16 */ map_register(i++, O2); 215 /* 17 */ map_register(i++, O3); 216 /* 18 */ map_register(i++, O4); 217 /* 19 */ map_register(i++, O5); // <- last register visible in RegAlloc (RegAlloc::nof+cpu_regs) 218 /* 20 */ map_register(i++, G1); 219 /* 21 */ map_register(i++, G3); 220 /* 22 */ map_register(i++, G4); 221 /* 23 */ map_register(i++, G5); 222 /* 24 */ map_register(i++, G0); 223 224 // the following registers are not normally available 225 /* 25 */ map_register(i++, O7); 226 /* 26 */ map_register(i++, G2); 227 /* 27 */ map_register(i++, O6); 228 /* 28 */ map_register(i++, I6); 229 /* 29 */ map_register(i++, I7); 230 /* 30 */ map_register(i++, G6); 231 /* 31 */ map_register(i++, G7); 232 assert(i == nof_cpu_regs, "number of CPU registers"); 233 234 for (i = 0; i < nof_fpu_regs; i++) { 235 _fpu_regs[i] = as_FloatRegister(i); 236 } 237 238 _init_done = true; 239 240 in_long_opr = as_long_opr(I0); 241 out_long_opr = as_long_opr(O0); 242 g1_long_single_opr = as_long_single_opr(G1); 243 244 G0_opr = as_opr(G0); 245 G1_opr = as_opr(G1); 246 G2_opr = as_opr(G2); 247 G3_opr = as_opr(G3); 248 G4_opr = as_opr(G4); 249 G5_opr = as_opr(G5); 250 G6_opr = as_opr(G6); 251 G7_opr = as_opr(G7); 252 O0_opr = as_opr(O0); 253 O1_opr = as_opr(O1); 254 O2_opr = as_opr(O2); 255 O3_opr = as_opr(O3); 256 O4_opr = as_opr(O4); 257 O5_opr = as_opr(O5); 258 O6_opr = as_opr(O6); 259 O7_opr = as_opr(O7); 260 L0_opr = as_opr(L0); 261 L1_opr = as_opr(L1); 262 L2_opr = as_opr(L2); 263 L3_opr = as_opr(L3); 264 L4_opr = as_opr(L4); 265 L5_opr = as_opr(L5); 266 L6_opr = as_opr(L6); 267 L7_opr = as_opr(L7); 268 I0_opr = as_opr(I0); 269 I1_opr = as_opr(I1); 270 I2_opr = as_opr(I2); 271 I3_opr = as_opr(I3); 272 I4_opr = as_opr(I4); 273 I5_opr = as_opr(I5); 274 I6_opr = as_opr(I6); 275 I7_opr = as_opr(I7); 276 277 G0_oop_opr = as_oop_opr(G0); 278 G1_oop_opr = as_oop_opr(G1); 279 G2_oop_opr = as_oop_opr(G2); 280 G3_oop_opr = as_oop_opr(G3); 281 G4_oop_opr = as_oop_opr(G4); 282 G5_oop_opr = as_oop_opr(G5); 283 G6_oop_opr = as_oop_opr(G6); 284 G7_oop_opr = as_oop_opr(G7); 285 O0_oop_opr = as_oop_opr(O0); 286 O1_oop_opr = as_oop_opr(O1); 287 O2_oop_opr = as_oop_opr(O2); 288 O3_oop_opr = as_oop_opr(O3); 289 O4_oop_opr = as_oop_opr(O4); 290 O5_oop_opr = as_oop_opr(O5); 291 O6_oop_opr = as_oop_opr(O6); 292 O7_oop_opr = as_oop_opr(O7); 293 L0_oop_opr = as_oop_opr(L0); 294 L1_oop_opr = as_oop_opr(L1); 295 L2_oop_opr = as_oop_opr(L2); 296 L3_oop_opr = as_oop_opr(L3); 297 L4_oop_opr = as_oop_opr(L4); 298 L5_oop_opr = as_oop_opr(L5); 299 L6_oop_opr = as_oop_opr(L6); 300 L7_oop_opr = as_oop_opr(L7); 301 I0_oop_opr = as_oop_opr(I0); 302 I1_oop_opr = as_oop_opr(I1); 303 I2_oop_opr = as_oop_opr(I2); 304 I3_oop_opr = as_oop_opr(I3); 305 I4_oop_opr = as_oop_opr(I4); 306 I5_oop_opr = as_oop_opr(I5); 307 I6_oop_opr = as_oop_opr(I6); 308 I7_oop_opr = as_oop_opr(I7); 309 310 FP_opr = as_pointer_opr(FP); 311 SP_opr = as_pointer_opr(SP); 312 313 F0_opr = as_float_opr(F0); 314 F0_double_opr = as_double_opr(F0); 315 316 Oexception_opr = as_oop_opr(Oexception); 317 Oissuing_pc_opr = as_opr(Oissuing_pc); 318 319 _caller_save_cpu_regs[0] = FrameMap::O0_opr; 320 _caller_save_cpu_regs[1] = FrameMap::O1_opr; 321 _caller_save_cpu_regs[2] = FrameMap::O2_opr; 322 _caller_save_cpu_regs[3] = FrameMap::O3_opr; 323 _caller_save_cpu_regs[4] = FrameMap::O4_opr; 324 _caller_save_cpu_regs[5] = FrameMap::O5_opr; 325 _caller_save_cpu_regs[6] = FrameMap::G1_opr; 326 _caller_save_cpu_regs[7] = FrameMap::G3_opr; 327 _caller_save_cpu_regs[8] = FrameMap::G4_opr; 328 _caller_save_cpu_regs[9] = FrameMap::G5_opr; 329 for (int i = 0; i < nof_caller_save_fpu_regs; i++) { 330 _caller_save_fpu_regs[i] = LIR_OprFact::single_fpu(i); 331 } 332 } 333 334 335 Address FrameMap::make_new_address(ByteSize sp_offset) const { 336 return Address(SP, STACK_BIAS + in_bytes(sp_offset)); 337 } 338 339 340 VMReg FrameMap::fpu_regname (int n) { 341 return as_FloatRegister(n)->as_VMReg(); 342 } 343 344 345 LIR_Opr FrameMap::stack_pointer() { 346 return SP_opr; 347 } 348 349 350 // JSR 292 351 LIR_Opr FrameMap::method_handle_invoke_SP_save_opr() { 352 assert(L7 == L7_mh_SP_save, "must be same register"); 353 return L7_opr; 354 } 355 356 357 bool FrameMap::validate_frame() { 358 int max_offset = in_bytes(framesize_in_bytes()); 359 int java_index = 0; 360 for (int i = 0; i < _incoming_arguments->length(); i++) { 361 LIR_Opr opr = _incoming_arguments->at(i); 362 if (opr->is_stack()) { 363 max_offset = MAX2(_argument_locations->at(java_index), max_offset); 364 } 365 java_index += type2size[opr->type()]; 366 } 367 return Assembler::is_simm13(max_offset + STACK_BIAS); 368 }