1 /* 2 * Copyright (c) 2000, 2010, Oracle and/or its affiliates. All rights reserved. 3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. 4 * 5 * This code is free software; you can redistribute it and/or modify it 6 * under the terms of the GNU General Public License version 2 only, as 7 * published by the Free Software Foundation. 8 * 9 * This code is distributed in the hope that it will be useful, but WITHOUT 10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or 11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License 12 * version 2 for more details (a copy is included in the LICENSE file that 13 * accompanied this code). 14 * 15 * You should have received a copy of the GNU General Public License version 16 * 2 along with this work; if not, write to the Free Software Foundation, 17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA. 18 * 19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA 20 * or visit www.oracle.com if you need additional information or have any 21 * questions. 22 * 23 */ 24 25 #include "precompiled.hpp" 26 #include "c1/c1_Compilation.hpp" 27 #include "c1/c1_LIRAssembler.hpp" 28 #include "c1/c1_MacroAssembler.hpp" 29 #include "c1/c1_Runtime1.hpp" 30 #include "c1/c1_ValueStack.hpp" 31 #include "ci/ciArrayKlass.hpp" 32 #include "ci/ciInstance.hpp" 33 #include "gc_interface/collectedHeap.hpp" 34 #include "memory/barrierSet.hpp" 35 #include "memory/cardTableModRefBS.hpp" 36 #include "nativeInst_sparc.hpp" 37 #include "oops/objArrayKlass.hpp" 38 #include "runtime/sharedRuntime.hpp" 39 40 #define __ _masm-> 41 42 43 //------------------------------------------------------------ 44 45 46 bool LIR_Assembler::is_small_constant(LIR_Opr opr) { 47 if (opr->is_constant()) { 48 LIR_Const* constant = opr->as_constant_ptr(); 49 switch (constant->type()) { 50 case T_INT: { 51 jint value = constant->as_jint(); 52 return Assembler::is_simm13(value); 53 } 54 55 default: 56 return false; 57 } 58 } 59 return false; 60 } 61 62 63 bool LIR_Assembler::is_single_instruction(LIR_Op* op) { 64 switch (op->code()) { 65 case lir_null_check: 66 return true; 67 68 69 case lir_add: 70 case lir_ushr: 71 case lir_shr: 72 case lir_shl: 73 // integer shifts and adds are always one instruction 74 return op->result_opr()->is_single_cpu(); 75 76 77 case lir_move: { 78 LIR_Op1* op1 = op->as_Op1(); 79 LIR_Opr src = op1->in_opr(); 80 LIR_Opr dst = op1->result_opr(); 81 82 if (src == dst) { 83 NEEDS_CLEANUP; 84 // this works around a problem where moves with the same src and dst 85 // end up in the delay slot and then the assembler swallows the mov 86 // since it has no effect and then it complains because the delay slot 87 // is empty. returning false stops the optimizer from putting this in 88 // the delay slot 89 return false; 90 } 91 92 // don't put moves involving oops into the delay slot since the VerifyOops code 93 // will make it much larger than a single instruction. 94 if (VerifyOops) { 95 return false; 96 } 97 98 if (src->is_double_cpu() || dst->is_double_cpu() || op1->patch_code() != lir_patch_none || 99 ((src->is_double_fpu() || dst->is_double_fpu()) && op1->move_kind() != lir_move_normal)) { 100 return false; 101 } 102 103 if (dst->is_register()) { 104 if (src->is_address() && Assembler::is_simm13(src->as_address_ptr()->disp())) { 105 return !PatchALot; 106 } else if (src->is_single_stack()) { 107 return true; 108 } 109 } 110 111 if (src->is_register()) { 112 if (dst->is_address() && Assembler::is_simm13(dst->as_address_ptr()->disp())) { 113 return !PatchALot; 114 } else if (dst->is_single_stack()) { 115 return true; 116 } 117 } 118 119 if (dst->is_register() && 120 ((src->is_register() && src->is_single_word() && src->is_same_type(dst)) || 121 (src->is_constant() && LIR_Assembler::is_small_constant(op->as_Op1()->in_opr())))) { 122 return true; 123 } 124 125 return false; 126 } 127 128 default: 129 return false; 130 } 131 ShouldNotReachHere(); 132 } 133 134 135 LIR_Opr LIR_Assembler::receiverOpr() { 136 return FrameMap::O0_oop_opr; 137 } 138 139 140 LIR_Opr LIR_Assembler::incomingReceiverOpr() { 141 return FrameMap::I0_oop_opr; 142 } 143 144 145 LIR_Opr LIR_Assembler::osrBufferPointer() { 146 return FrameMap::I0_opr; 147 } 148 149 150 int LIR_Assembler::initial_frame_size_in_bytes() { 151 return in_bytes(frame_map()->framesize_in_bytes()); 152 } 153 154 155 // inline cache check: the inline cached class is in G5_inline_cache_reg(G5); 156 // we fetch the class of the receiver (O0) and compare it with the cached class. 157 // If they do not match we jump to slow case. 158 int LIR_Assembler::check_icache() { 159 int offset = __ offset(); 160 __ inline_cache_check(O0, G5_inline_cache_reg); 161 return offset; 162 } 163 164 165 void LIR_Assembler::osr_entry() { 166 // On-stack-replacement entry sequence (interpreter frame layout described in interpreter_sparc.cpp): 167 // 168 // 1. Create a new compiled activation. 169 // 2. Initialize local variables in the compiled activation. The expression stack must be empty 170 // at the osr_bci; it is not initialized. 171 // 3. Jump to the continuation address in compiled code to resume execution. 172 173 // OSR entry point 174 offsets()->set_value(CodeOffsets::OSR_Entry, code_offset()); 175 BlockBegin* osr_entry = compilation()->hir()->osr_entry(); 176 ValueStack* entry_state = osr_entry->end()->state(); 177 int number_of_locks = entry_state->locks_size(); 178 179 // Create a frame for the compiled activation. 180 __ build_frame(initial_frame_size_in_bytes()); 181 182 // OSR buffer is 183 // 184 // locals[nlocals-1..0] 185 // monitors[number_of_locks-1..0] 186 // 187 // locals is a direct copy of the interpreter frame so in the osr buffer 188 // so first slot in the local array is the last local from the interpreter 189 // and last slot is local[0] (receiver) from the interpreter 190 // 191 // Similarly with locks. The first lock slot in the osr buffer is the nth lock 192 // from the interpreter frame, the nth lock slot in the osr buffer is 0th lock 193 // in the interpreter frame (the method lock if a sync method) 194 195 // Initialize monitors in the compiled activation. 196 // I0: pointer to osr buffer 197 // 198 // All other registers are dead at this point and the locals will be 199 // copied into place by code emitted in the IR. 200 201 Register OSR_buf = osrBufferPointer()->as_register(); 202 { assert(frame::interpreter_frame_monitor_size() == BasicObjectLock::size(), "adjust code below"); 203 int monitor_offset = BytesPerWord * method()->max_locals() + 204 (2 * BytesPerWord) * (number_of_locks - 1); 205 // SharedRuntime::OSR_migration_begin() packs BasicObjectLocks in 206 // the OSR buffer using 2 word entries: first the lock and then 207 // the oop. 208 for (int i = 0; i < number_of_locks; i++) { 209 int slot_offset = monitor_offset - ((i * 2) * BytesPerWord); 210 #ifdef ASSERT 211 // verify the interpreter's monitor has a non-null object 212 { 213 Label L; 214 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); 215 __ cmp(G0, O7); 216 __ br(Assembler::notEqual, false, Assembler::pt, L); 217 __ delayed()->nop(); 218 __ stop("locked object is NULL"); 219 __ bind(L); 220 } 221 #endif // ASSERT 222 // Copy the lock field into the compiled activation. 223 __ ld_ptr(OSR_buf, slot_offset + 0, O7); 224 __ st_ptr(O7, frame_map()->address_for_monitor_lock(i)); 225 __ ld_ptr(OSR_buf, slot_offset + 1*BytesPerWord, O7); 226 __ st_ptr(O7, frame_map()->address_for_monitor_object(i)); 227 } 228 } 229 } 230 231 232 // Optimized Library calls 233 // This is the fast version of java.lang.String.compare; it has not 234 // OSR-entry and therefore, we generate a slow version for OSR's 235 void LIR_Assembler::emit_string_compare(LIR_Opr left, LIR_Opr right, LIR_Opr dst, CodeEmitInfo* info) { 236 Register str0 = left->as_register(); 237 Register str1 = right->as_register(); 238 239 Label Ldone; 240 241 Register result = dst->as_register(); 242 { 243 // Get a pointer to the first character of string0 in tmp0 and get string0.count in str0 244 // Get a pointer to the first character of string1 in tmp1 and get string1.count in str1 245 // Also, get string0.count-string1.count in o7 and get the condition code set 246 // Note: some instructions have been hoisted for better instruction scheduling 247 248 Register tmp0 = L0; 249 Register tmp1 = L1; 250 Register tmp2 = L2; 251 252 int value_offset = java_lang_String:: value_offset_in_bytes(); // char array 253 int offset_offset = java_lang_String::offset_offset_in_bytes(); // first character position 254 int count_offset = java_lang_String:: count_offset_in_bytes(); 255 256 __ ld_ptr(str0, value_offset, tmp0); 257 __ ld(str0, offset_offset, tmp2); 258 __ add(tmp0, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp0); 259 __ ld(str0, count_offset, str0); 260 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); 261 262 // str1 may be null 263 add_debug_info_for_null_check_here(info); 264 265 __ ld_ptr(str1, value_offset, tmp1); 266 __ add(tmp0, tmp2, tmp0); 267 268 __ ld(str1, offset_offset, tmp2); 269 __ add(tmp1, arrayOopDesc::base_offset_in_bytes(T_CHAR), tmp1); 270 __ ld(str1, count_offset, str1); 271 __ sll(tmp2, exact_log2(sizeof(jchar)), tmp2); 272 __ subcc(str0, str1, O7); 273 __ add(tmp1, tmp2, tmp1); 274 } 275 276 { 277 // Compute the minimum of the string lengths, scale it and store it in limit 278 Register count0 = I0; 279 Register count1 = I1; 280 Register limit = L3; 281 282 Label Lskip; 283 __ sll(count0, exact_log2(sizeof(jchar)), limit); // string0 is shorter 284 __ br(Assembler::greater, true, Assembler::pt, Lskip); 285 __ delayed()->sll(count1, exact_log2(sizeof(jchar)), limit); // string1 is shorter 286 __ bind(Lskip); 287 288 // If either string is empty (or both of them) the result is the difference in lengths 289 __ cmp(limit, 0); 290 __ br(Assembler::equal, true, Assembler::pn, Ldone); 291 __ delayed()->mov(O7, result); // result is difference in lengths 292 } 293 294 { 295 // Neither string is empty 296 Label Lloop; 297 298 Register base0 = L0; 299 Register base1 = L1; 300 Register chr0 = I0; 301 Register chr1 = I1; 302 Register limit = L3; 303 304 // Shift base0 and base1 to the end of the arrays, negate limit 305 __ add(base0, limit, base0); 306 __ add(base1, limit, base1); 307 __ neg(limit); // limit = -min{string0.count, strin1.count} 308 309 __ lduh(base0, limit, chr0); 310 __ bind(Lloop); 311 __ lduh(base1, limit, chr1); 312 __ subcc(chr0, chr1, chr0); 313 __ br(Assembler::notZero, false, Assembler::pn, Ldone); 314 assert(chr0 == result, "result must be pre-placed"); 315 __ delayed()->inccc(limit, sizeof(jchar)); 316 __ br(Assembler::notZero, true, Assembler::pt, Lloop); 317 __ delayed()->lduh(base0, limit, chr0); 318 } 319 320 // If strings are equal up to min length, return the length difference. 321 __ mov(O7, result); 322 323 // Otherwise, return the difference between the first mismatched chars. 324 __ bind(Ldone); 325 } 326 327 328 // -------------------------------------------------------------------------------------------- 329 330 void LIR_Assembler::monitorexit(LIR_Opr obj_opr, LIR_Opr lock_opr, Register hdr, int monitor_no) { 331 if (!GenerateSynchronizationCode) return; 332 333 Register obj_reg = obj_opr->as_register(); 334 Register lock_reg = lock_opr->as_register(); 335 336 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 337 Register reg = mon_addr.base(); 338 int offset = mon_addr.disp(); 339 // compute pointer to BasicLock 340 if (mon_addr.is_simm13()) { 341 __ add(reg, offset, lock_reg); 342 } 343 else { 344 __ set(offset, lock_reg); 345 __ add(reg, lock_reg, lock_reg); 346 } 347 // unlock object 348 MonitorAccessStub* slow_case = new MonitorExitStub(lock_opr, UseFastLocking, monitor_no); 349 // _slow_case_stubs->append(slow_case); 350 // temporary fix: must be created after exceptionhandler, therefore as call stub 351 _slow_case_stubs->append(slow_case); 352 if (UseFastLocking) { 353 // try inlined fast unlocking first, revert to slow locking if it fails 354 // note: lock_reg points to the displaced header since the displaced header offset is 0! 355 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 356 __ unlock_object(hdr, obj_reg, lock_reg, *slow_case->entry()); 357 } else { 358 // always do slow unlocking 359 // note: the slow unlocking code could be inlined here, however if we use 360 // slow unlocking, speed doesn't matter anyway and this solution is 361 // simpler and requires less duplicated code - additionally, the 362 // slow unlocking code is the same in either case which simplifies 363 // debugging 364 __ br(Assembler::always, false, Assembler::pt, *slow_case->entry()); 365 __ delayed()->nop(); 366 } 367 // done 368 __ bind(*slow_case->continuation()); 369 } 370 371 372 int LIR_Assembler::emit_exception_handler() { 373 // if the last instruction is a call (typically to do a throw which 374 // is coming at the end after block reordering) the return address 375 // must still point into the code area in order to avoid assertion 376 // failures when searching for the corresponding bci => add a nop 377 // (was bug 5/14/1999 - gri) 378 __ nop(); 379 380 // generate code for exception handler 381 ciMethod* method = compilation()->method(); 382 383 address handler_base = __ start_a_stub(exception_handler_size); 384 385 if (handler_base == NULL) { 386 // not enough space left for the handler 387 bailout("exception handler overflow"); 388 return -1; 389 } 390 391 int offset = code_offset(); 392 393 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); 394 __ delayed()->nop(); 395 debug_only(__ stop("should have gone to the caller");) 396 assert(code_offset() - offset <= exception_handler_size, "overflow"); 397 __ end_a_stub(); 398 399 return offset; 400 } 401 402 403 // Emit the code to remove the frame from the stack in the exception 404 // unwind path. 405 int LIR_Assembler::emit_unwind_handler() { 406 #ifndef PRODUCT 407 if (CommentedAssembly) { 408 _masm->block_comment("Unwind handler"); 409 } 410 #endif 411 412 int offset = code_offset(); 413 414 // Fetch the exception from TLS and clear out exception related thread state 415 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), O0); 416 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset())); 417 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_pc_offset())); 418 419 __ bind(_unwind_handler_entry); 420 __ verify_not_null_oop(O0); 421 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 422 __ mov(O0, I0); // Preserve the exception 423 } 424 425 // Preform needed unlocking 426 MonitorExitStub* stub = NULL; 427 if (method()->is_synchronized()) { 428 monitor_address(0, FrameMap::I1_opr); 429 stub = new MonitorExitStub(FrameMap::I1_opr, true, 0); 430 __ unlock_object(I3, I2, I1, *stub->entry()); 431 __ bind(*stub->continuation()); 432 } 433 434 if (compilation()->env()->dtrace_method_probes()) { 435 __ mov(G2_thread, O0); 436 jobject2reg(method()->constant_encoding(), O1); 437 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit), relocInfo::runtime_call_type); 438 __ delayed()->nop(); 439 } 440 441 if (method()->is_synchronized() || compilation()->env()->dtrace_method_probes()) { 442 __ mov(I0, O0); // Restore the exception 443 } 444 445 // dispatch to the unwind logic 446 __ call(Runtime1::entry_for(Runtime1::unwind_exception_id), relocInfo::runtime_call_type); 447 __ delayed()->nop(); 448 449 // Emit the slow path assembly 450 if (stub != NULL) { 451 stub->emit_code(this); 452 } 453 454 return offset; 455 } 456 457 458 int LIR_Assembler::emit_deopt_handler() { 459 // if the last instruction is a call (typically to do a throw which 460 // is coming at the end after block reordering) the return address 461 // must still point into the code area in order to avoid assertion 462 // failures when searching for the corresponding bci => add a nop 463 // (was bug 5/14/1999 - gri) 464 __ nop(); 465 466 // generate code for deopt handler 467 ciMethod* method = compilation()->method(); 468 address handler_base = __ start_a_stub(deopt_handler_size); 469 if (handler_base == NULL) { 470 // not enough space left for the handler 471 bailout("deopt handler overflow"); 472 return -1; 473 } 474 475 int offset = code_offset(); 476 AddressLiteral deopt_blob(SharedRuntime::deopt_blob()->unpack()); 477 __ JUMP(deopt_blob, G3_scratch, 0); // sethi;jmp 478 __ delayed()->nop(); 479 assert(code_offset() - offset <= deopt_handler_size, "overflow"); 480 debug_only(__ stop("should have gone to the caller");) 481 __ end_a_stub(); 482 483 return offset; 484 } 485 486 487 void LIR_Assembler::jobject2reg(jobject o, Register reg) { 488 if (o == NULL) { 489 __ set(NULL_WORD, reg); 490 } else { 491 int oop_index = __ oop_recorder()->find_index(o); 492 RelocationHolder rspec = oop_Relocation::spec(oop_index); 493 __ set(NULL_WORD, reg, rspec); // Will be set when the nmethod is created 494 } 495 } 496 497 498 void LIR_Assembler::jobject2reg_with_patching(Register reg, CodeEmitInfo *info) { 499 // Allocate a new index in oop table to hold the oop once it's been patched 500 int oop_index = __ oop_recorder()->allocate_index((jobject)NULL); 501 PatchingStub* patch = new PatchingStub(_masm, PatchingStub::load_klass_id, oop_index); 502 503 AddressLiteral addrlit(NULL, oop_Relocation::spec(oop_index)); 504 assert(addrlit.rspec().type() == relocInfo::oop_type, "must be an oop reloc"); 505 // It may not seem necessary to use a sethi/add pair to load a NULL into dest, but the 506 // NULL will be dynamically patched later and the patched value may be large. We must 507 // therefore generate the sethi/add as a placeholders 508 __ patchable_set(addrlit, reg); 509 510 patching_epilog(patch, lir_patch_normal, reg, info); 511 } 512 513 514 void LIR_Assembler::emit_op3(LIR_Op3* op) { 515 Register Rdividend = op->in_opr1()->as_register(); 516 Register Rdivisor = noreg; 517 Register Rscratch = op->in_opr3()->as_register(); 518 Register Rresult = op->result_opr()->as_register(); 519 int divisor = -1; 520 521 if (op->in_opr2()->is_register()) { 522 Rdivisor = op->in_opr2()->as_register(); 523 } else { 524 divisor = op->in_opr2()->as_constant_ptr()->as_jint(); 525 assert(Assembler::is_simm13(divisor), "can only handle simm13"); 526 } 527 528 assert(Rdividend != Rscratch, ""); 529 assert(Rdivisor != Rscratch, ""); 530 assert(op->code() == lir_idiv || op->code() == lir_irem, "Must be irem or idiv"); 531 532 if (Rdivisor == noreg && is_power_of_2(divisor)) { 533 // convert division by a power of two into some shifts and logical operations 534 if (op->code() == lir_idiv) { 535 if (divisor == 2) { 536 __ srl(Rdividend, 31, Rscratch); 537 } else { 538 __ sra(Rdividend, 31, Rscratch); 539 __ and3(Rscratch, divisor - 1, Rscratch); 540 } 541 __ add(Rdividend, Rscratch, Rscratch); 542 __ sra(Rscratch, log2_intptr(divisor), Rresult); 543 return; 544 } else { 545 if (divisor == 2) { 546 __ srl(Rdividend, 31, Rscratch); 547 } else { 548 __ sra(Rdividend, 31, Rscratch); 549 __ and3(Rscratch, divisor - 1,Rscratch); 550 } 551 __ add(Rdividend, Rscratch, Rscratch); 552 __ andn(Rscratch, divisor - 1,Rscratch); 553 __ sub(Rdividend, Rscratch, Rresult); 554 return; 555 } 556 } 557 558 __ sra(Rdividend, 31, Rscratch); 559 __ wry(Rscratch); 560 if (!VM_Version::v9_instructions_work()) { 561 // v9 doesn't require these nops 562 __ nop(); 563 __ nop(); 564 __ nop(); 565 __ nop(); 566 } 567 568 add_debug_info_for_div0_here(op->info()); 569 570 if (Rdivisor != noreg) { 571 __ sdivcc(Rdividend, Rdivisor, (op->code() == lir_idiv ? Rresult : Rscratch)); 572 } else { 573 assert(Assembler::is_simm13(divisor), "can only handle simm13"); 574 __ sdivcc(Rdividend, divisor, (op->code() == lir_idiv ? Rresult : Rscratch)); 575 } 576 577 Label skip; 578 __ br(Assembler::overflowSet, true, Assembler::pn, skip); 579 __ delayed()->Assembler::sethi(0x80000000, (op->code() == lir_idiv ? Rresult : Rscratch)); 580 __ bind(skip); 581 582 if (op->code() == lir_irem) { 583 if (Rdivisor != noreg) { 584 __ smul(Rscratch, Rdivisor, Rscratch); 585 } else { 586 __ smul(Rscratch, divisor, Rscratch); 587 } 588 __ sub(Rdividend, Rscratch, Rresult); 589 } 590 } 591 592 593 void LIR_Assembler::emit_opBranch(LIR_OpBranch* op) { 594 #ifdef ASSERT 595 assert(op->block() == NULL || op->block()->label() == op->label(), "wrong label"); 596 if (op->block() != NULL) _branch_target_blocks.append(op->block()); 597 if (op->ublock() != NULL) _branch_target_blocks.append(op->ublock()); 598 #endif 599 assert(op->info() == NULL, "shouldn't have CodeEmitInfo"); 600 601 if (op->cond() == lir_cond_always) { 602 __ br(Assembler::always, false, Assembler::pt, *(op->label())); 603 } else if (op->code() == lir_cond_float_branch) { 604 assert(op->ublock() != NULL, "must have unordered successor"); 605 bool is_unordered = (op->ublock() == op->block()); 606 Assembler::Condition acond; 607 switch (op->cond()) { 608 case lir_cond_equal: acond = Assembler::f_equal; break; 609 case lir_cond_notEqual: acond = Assembler::f_notEqual; break; 610 case lir_cond_less: acond = (is_unordered ? Assembler::f_unorderedOrLess : Assembler::f_less); break; 611 case lir_cond_greater: acond = (is_unordered ? Assembler::f_unorderedOrGreater : Assembler::f_greater); break; 612 case lir_cond_lessEqual: acond = (is_unordered ? Assembler::f_unorderedOrLessOrEqual : Assembler::f_lessOrEqual); break; 613 case lir_cond_greaterEqual: acond = (is_unordered ? Assembler::f_unorderedOrGreaterOrEqual: Assembler::f_greaterOrEqual); break; 614 default : ShouldNotReachHere(); 615 }; 616 617 if (!VM_Version::v9_instructions_work()) { 618 __ nop(); 619 } 620 __ fb( acond, false, Assembler::pn, *(op->label())); 621 } else { 622 assert (op->code() == lir_branch, "just checking"); 623 624 Assembler::Condition acond; 625 switch (op->cond()) { 626 case lir_cond_equal: acond = Assembler::equal; break; 627 case lir_cond_notEqual: acond = Assembler::notEqual; break; 628 case lir_cond_less: acond = Assembler::less; break; 629 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 630 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 631 case lir_cond_greater: acond = Assembler::greater; break; 632 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 633 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 634 default: ShouldNotReachHere(); 635 }; 636 637 // sparc has different condition codes for testing 32-bit 638 // vs. 64-bit values. We could always test xcc is we could 639 // guarantee that 32-bit loads always sign extended but that isn't 640 // true and since sign extension isn't free, it would impose a 641 // slight cost. 642 #ifdef _LP64 643 if (op->type() == T_INT) { 644 __ br(acond, false, Assembler::pn, *(op->label())); 645 } else 646 #endif 647 __ brx(acond, false, Assembler::pn, *(op->label())); 648 } 649 // The peephole pass fills the delay slot 650 } 651 652 653 void LIR_Assembler::emit_opConvert(LIR_OpConvert* op) { 654 Bytecodes::Code code = op->bytecode(); 655 LIR_Opr dst = op->result_opr(); 656 657 switch(code) { 658 case Bytecodes::_i2l: { 659 Register rlo = dst->as_register_lo(); 660 Register rhi = dst->as_register_hi(); 661 Register rval = op->in_opr()->as_register(); 662 #ifdef _LP64 663 __ sra(rval, 0, rlo); 664 #else 665 __ mov(rval, rlo); 666 __ sra(rval, BitsPerInt-1, rhi); 667 #endif 668 break; 669 } 670 case Bytecodes::_i2d: 671 case Bytecodes::_i2f: { 672 bool is_double = (code == Bytecodes::_i2d); 673 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); 674 FloatRegisterImpl::Width w = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; 675 FloatRegister rsrc = op->in_opr()->as_float_reg(); 676 if (rsrc != rdst) { 677 __ fmov(FloatRegisterImpl::S, rsrc, rdst); 678 } 679 __ fitof(w, rdst, rdst); 680 break; 681 } 682 case Bytecodes::_f2i:{ 683 FloatRegister rsrc = op->in_opr()->as_float_reg(); 684 Address addr = frame_map()->address_for_slot(dst->single_stack_ix()); 685 Label L; 686 // result must be 0 if value is NaN; test by comparing value to itself 687 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, rsrc, rsrc); 688 if (!VM_Version::v9_instructions_work()) { 689 __ nop(); 690 } 691 __ fb(Assembler::f_unordered, true, Assembler::pn, L); 692 __ delayed()->st(G0, addr); // annuled if contents of rsrc is not NaN 693 __ ftoi(FloatRegisterImpl::S, rsrc, rsrc); 694 // move integer result from float register to int register 695 __ stf(FloatRegisterImpl::S, rsrc, addr.base(), addr.disp()); 696 __ bind (L); 697 break; 698 } 699 case Bytecodes::_l2i: { 700 Register rlo = op->in_opr()->as_register_lo(); 701 Register rhi = op->in_opr()->as_register_hi(); 702 Register rdst = dst->as_register(); 703 #ifdef _LP64 704 __ sra(rlo, 0, rdst); 705 #else 706 __ mov(rlo, rdst); 707 #endif 708 break; 709 } 710 case Bytecodes::_d2f: 711 case Bytecodes::_f2d: { 712 bool is_double = (code == Bytecodes::_f2d); 713 assert((!is_double && dst->is_single_fpu()) || (is_double && dst->is_double_fpu()), "check"); 714 LIR_Opr val = op->in_opr(); 715 FloatRegister rval = (code == Bytecodes::_d2f) ? val->as_double_reg() : val->as_float_reg(); 716 FloatRegister rdst = is_double ? dst->as_double_reg() : dst->as_float_reg(); 717 FloatRegisterImpl::Width vw = is_double ? FloatRegisterImpl::S : FloatRegisterImpl::D; 718 FloatRegisterImpl::Width dw = is_double ? FloatRegisterImpl::D : FloatRegisterImpl::S; 719 __ ftof(vw, dw, rval, rdst); 720 break; 721 } 722 case Bytecodes::_i2s: 723 case Bytecodes::_i2b: { 724 Register rval = op->in_opr()->as_register(); 725 Register rdst = dst->as_register(); 726 int shift = (code == Bytecodes::_i2b) ? (BitsPerInt - T_BYTE_aelem_bytes * BitsPerByte) : (BitsPerInt - BitsPerShort); 727 __ sll (rval, shift, rdst); 728 __ sra (rdst, shift, rdst); 729 break; 730 } 731 case Bytecodes::_i2c: { 732 Register rval = op->in_opr()->as_register(); 733 Register rdst = dst->as_register(); 734 int shift = BitsPerInt - T_CHAR_aelem_bytes * BitsPerByte; 735 __ sll (rval, shift, rdst); 736 __ srl (rdst, shift, rdst); 737 break; 738 } 739 740 default: ShouldNotReachHere(); 741 } 742 } 743 744 745 void LIR_Assembler::align_call(LIR_Code) { 746 // do nothing since all instructions are word aligned on sparc 747 } 748 749 750 void LIR_Assembler::call(LIR_OpJavaCall* op, relocInfo::relocType rtype) { 751 __ call(op->addr(), rtype); 752 // The peephole pass fills the delay slot, add_call_info is done in 753 // LIR_Assembler::emit_delay. 754 } 755 756 757 void LIR_Assembler::ic_call(LIR_OpJavaCall* op) { 758 RelocationHolder rspec = virtual_call_Relocation::spec(pc()); 759 __ set_oop((jobject)Universe::non_oop_word(), G5_inline_cache_reg); 760 __ relocate(rspec); 761 __ call(op->addr(), relocInfo::none); 762 // The peephole pass fills the delay slot, add_call_info is done in 763 // LIR_Assembler::emit_delay. 764 } 765 766 767 void LIR_Assembler::vtable_call(LIR_OpJavaCall* op) { 768 add_debug_info_for_null_check_here(op->info()); 769 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), G3_scratch); 770 if (__ is_simm13(op->vtable_offset())) { 771 __ ld_ptr(G3_scratch, op->vtable_offset(), G5_method); 772 } else { 773 // This will generate 2 instructions 774 __ set(op->vtable_offset(), G5_method); 775 // ld_ptr, set_hi, set 776 __ ld_ptr(G3_scratch, G5_method, G5_method); 777 } 778 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3_scratch); 779 __ callr(G3_scratch, G0); 780 // the peephole pass fills the delay slot 781 } 782 783 784 // load with 32-bit displacement 785 int LIR_Assembler::load(Register s, int disp, Register d, BasicType ld_type, CodeEmitInfo *info) { 786 int load_offset = code_offset(); 787 if (Assembler::is_simm13(disp)) { 788 if (info != NULL) add_debug_info_for_null_check_here(info); 789 switch(ld_type) { 790 case T_BOOLEAN: // fall through 791 case T_BYTE : __ ldsb(s, disp, d); break; 792 case T_CHAR : __ lduh(s, disp, d); break; 793 case T_SHORT : __ ldsh(s, disp, d); break; 794 case T_INT : __ ld(s, disp, d); break; 795 case T_ADDRESS:// fall through 796 case T_ARRAY : // fall through 797 case T_OBJECT: __ ld_ptr(s, disp, d); break; 798 default : ShouldNotReachHere(); 799 } 800 } else { 801 __ set(disp, O7); 802 if (info != NULL) add_debug_info_for_null_check_here(info); 803 load_offset = code_offset(); 804 switch(ld_type) { 805 case T_BOOLEAN: // fall through 806 case T_BYTE : __ ldsb(s, O7, d); break; 807 case T_CHAR : __ lduh(s, O7, d); break; 808 case T_SHORT : __ ldsh(s, O7, d); break; 809 case T_INT : __ ld(s, O7, d); break; 810 case T_ADDRESS:// fall through 811 case T_ARRAY : // fall through 812 case T_OBJECT: __ ld_ptr(s, O7, d); break; 813 default : ShouldNotReachHere(); 814 } 815 } 816 if (ld_type == T_ARRAY || ld_type == T_OBJECT) __ verify_oop(d); 817 return load_offset; 818 } 819 820 821 // store with 32-bit displacement 822 void LIR_Assembler::store(Register value, Register base, int offset, BasicType type, CodeEmitInfo *info) { 823 if (Assembler::is_simm13(offset)) { 824 if (info != NULL) add_debug_info_for_null_check_here(info); 825 switch (type) { 826 case T_BOOLEAN: // fall through 827 case T_BYTE : __ stb(value, base, offset); break; 828 case T_CHAR : __ sth(value, base, offset); break; 829 case T_SHORT : __ sth(value, base, offset); break; 830 case T_INT : __ stw(value, base, offset); break; 831 case T_ADDRESS:// fall through 832 case T_ARRAY : // fall through 833 case T_OBJECT: __ st_ptr(value, base, offset); break; 834 default : ShouldNotReachHere(); 835 } 836 } else { 837 __ set(offset, O7); 838 if (info != NULL) add_debug_info_for_null_check_here(info); 839 switch (type) { 840 case T_BOOLEAN: // fall through 841 case T_BYTE : __ stb(value, base, O7); break; 842 case T_CHAR : __ sth(value, base, O7); break; 843 case T_SHORT : __ sth(value, base, O7); break; 844 case T_INT : __ stw(value, base, O7); break; 845 case T_ADDRESS:// fall through 846 case T_ARRAY : //fall through 847 case T_OBJECT: __ st_ptr(value, base, O7); break; 848 default : ShouldNotReachHere(); 849 } 850 } 851 // Note: Do the store before verification as the code might be patched! 852 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(value); 853 } 854 855 856 // load float with 32-bit displacement 857 void LIR_Assembler::load(Register s, int disp, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { 858 FloatRegisterImpl::Width w; 859 switch(ld_type) { 860 case T_FLOAT : w = FloatRegisterImpl::S; break; 861 case T_DOUBLE: w = FloatRegisterImpl::D; break; 862 default : ShouldNotReachHere(); 863 } 864 865 if (Assembler::is_simm13(disp)) { 866 if (info != NULL) add_debug_info_for_null_check_here(info); 867 if (disp % BytesPerLong != 0 && w == FloatRegisterImpl::D) { 868 __ ldf(FloatRegisterImpl::S, s, disp + BytesPerWord, d->successor()); 869 __ ldf(FloatRegisterImpl::S, s, disp , d); 870 } else { 871 __ ldf(w, s, disp, d); 872 } 873 } else { 874 __ set(disp, O7); 875 if (info != NULL) add_debug_info_for_null_check_here(info); 876 __ ldf(w, s, O7, d); 877 } 878 } 879 880 881 // store float with 32-bit displacement 882 void LIR_Assembler::store(FloatRegister value, Register base, int offset, BasicType type, CodeEmitInfo *info) { 883 FloatRegisterImpl::Width w; 884 switch(type) { 885 case T_FLOAT : w = FloatRegisterImpl::S; break; 886 case T_DOUBLE: w = FloatRegisterImpl::D; break; 887 default : ShouldNotReachHere(); 888 } 889 890 if (Assembler::is_simm13(offset)) { 891 if (info != NULL) add_debug_info_for_null_check_here(info); 892 if (w == FloatRegisterImpl::D && offset % BytesPerLong != 0) { 893 __ stf(FloatRegisterImpl::S, value->successor(), base, offset + BytesPerWord); 894 __ stf(FloatRegisterImpl::S, value , base, offset); 895 } else { 896 __ stf(w, value, base, offset); 897 } 898 } else { 899 __ set(offset, O7); 900 if (info != NULL) add_debug_info_for_null_check_here(info); 901 __ stf(w, value, O7, base); 902 } 903 } 904 905 906 int LIR_Assembler::store(LIR_Opr from_reg, Register base, int offset, BasicType type, bool unaligned) { 907 int store_offset; 908 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { 909 assert(!unaligned, "can't handle this"); 910 // for offsets larger than a simm13 we setup the offset in O7 911 __ set(offset, O7); 912 store_offset = store(from_reg, base, O7, type); 913 } else { 914 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); 915 store_offset = code_offset(); 916 switch (type) { 917 case T_BOOLEAN: // fall through 918 case T_BYTE : __ stb(from_reg->as_register(), base, offset); break; 919 case T_CHAR : __ sth(from_reg->as_register(), base, offset); break; 920 case T_SHORT : __ sth(from_reg->as_register(), base, offset); break; 921 case T_INT : __ stw(from_reg->as_register(), base, offset); break; 922 case T_LONG : 923 #ifdef _LP64 924 if (unaligned || PatchALot) { 925 __ srax(from_reg->as_register_lo(), 32, O7); 926 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); 927 __ stw(O7, base, offset + hi_word_offset_in_bytes); 928 } else { 929 __ stx(from_reg->as_register_lo(), base, offset); 930 } 931 #else 932 assert(Assembler::is_simm13(offset + 4), "must be"); 933 __ stw(from_reg->as_register_lo(), base, offset + lo_word_offset_in_bytes); 934 __ stw(from_reg->as_register_hi(), base, offset + hi_word_offset_in_bytes); 935 #endif 936 break; 937 case T_ADDRESS:// fall through 938 case T_ARRAY : // fall through 939 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, offset); break; 940 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, offset); break; 941 case T_DOUBLE: 942 { 943 FloatRegister reg = from_reg->as_double_reg(); 944 // split unaligned stores 945 if (unaligned || PatchALot) { 946 assert(Assembler::is_simm13(offset + 4), "must be"); 947 __ stf(FloatRegisterImpl::S, reg->successor(), base, offset + 4); 948 __ stf(FloatRegisterImpl::S, reg, base, offset); 949 } else { 950 __ stf(FloatRegisterImpl::D, reg, base, offset); 951 } 952 break; 953 } 954 default : ShouldNotReachHere(); 955 } 956 } 957 return store_offset; 958 } 959 960 961 int LIR_Assembler::store(LIR_Opr from_reg, Register base, Register disp, BasicType type) { 962 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(from_reg->as_register()); 963 int store_offset = code_offset(); 964 switch (type) { 965 case T_BOOLEAN: // fall through 966 case T_BYTE : __ stb(from_reg->as_register(), base, disp); break; 967 case T_CHAR : __ sth(from_reg->as_register(), base, disp); break; 968 case T_SHORT : __ sth(from_reg->as_register(), base, disp); break; 969 case T_INT : __ stw(from_reg->as_register(), base, disp); break; 970 case T_LONG : 971 #ifdef _LP64 972 __ stx(from_reg->as_register_lo(), base, disp); 973 #else 974 assert(from_reg->as_register_hi()->successor() == from_reg->as_register_lo(), "must match"); 975 __ std(from_reg->as_register_hi(), base, disp); 976 #endif 977 break; 978 case T_ADDRESS:// fall through 979 case T_ARRAY : // fall through 980 case T_OBJECT: __ st_ptr(from_reg->as_register(), base, disp); break; 981 case T_FLOAT : __ stf(FloatRegisterImpl::S, from_reg->as_float_reg(), base, disp); break; 982 case T_DOUBLE: __ stf(FloatRegisterImpl::D, from_reg->as_double_reg(), base, disp); break; 983 default : ShouldNotReachHere(); 984 } 985 return store_offset; 986 } 987 988 989 int LIR_Assembler::load(Register base, int offset, LIR_Opr to_reg, BasicType type, bool unaligned) { 990 int load_offset; 991 if (!Assembler::is_simm13(offset + (type == T_LONG) ? wordSize : 0)) { 992 assert(base != O7, "destroying register"); 993 assert(!unaligned, "can't handle this"); 994 // for offsets larger than a simm13 we setup the offset in O7 995 __ set(offset, O7); 996 load_offset = load(base, O7, to_reg, type); 997 } else { 998 load_offset = code_offset(); 999 switch(type) { 1000 case T_BOOLEAN: // fall through 1001 case T_BYTE : __ ldsb(base, offset, to_reg->as_register()); break; 1002 case T_CHAR : __ lduh(base, offset, to_reg->as_register()); break; 1003 case T_SHORT : __ ldsh(base, offset, to_reg->as_register()); break; 1004 case T_INT : __ ld(base, offset, to_reg->as_register()); break; 1005 case T_LONG : 1006 if (!unaligned) { 1007 #ifdef _LP64 1008 __ ldx(base, offset, to_reg->as_register_lo()); 1009 #else 1010 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), 1011 "must be sequential"); 1012 __ ldd(base, offset, to_reg->as_register_hi()); 1013 #endif 1014 } else { 1015 #ifdef _LP64 1016 assert(base != to_reg->as_register_lo(), "can't handle this"); 1017 assert(O7 != to_reg->as_register_lo(), "can't handle this"); 1018 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_lo()); 1019 __ lduw(base, offset + lo_word_offset_in_bytes, O7); // in case O7 is base or offset, use it last 1020 __ sllx(to_reg->as_register_lo(), 32, to_reg->as_register_lo()); 1021 __ or3(to_reg->as_register_lo(), O7, to_reg->as_register_lo()); 1022 #else 1023 if (base == to_reg->as_register_lo()) { 1024 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); 1025 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); 1026 } else { 1027 __ ld(base, offset + lo_word_offset_in_bytes, to_reg->as_register_lo()); 1028 __ ld(base, offset + hi_word_offset_in_bytes, to_reg->as_register_hi()); 1029 } 1030 #endif 1031 } 1032 break; 1033 case T_ADDRESS:// fall through 1034 case T_ARRAY : // fall through 1035 case T_OBJECT: __ ld_ptr(base, offset, to_reg->as_register()); break; 1036 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, offset, to_reg->as_float_reg()); break; 1037 case T_DOUBLE: 1038 { 1039 FloatRegister reg = to_reg->as_double_reg(); 1040 // split unaligned loads 1041 if (unaligned || PatchALot) { 1042 __ ldf(FloatRegisterImpl::S, base, offset + 4, reg->successor()); 1043 __ ldf(FloatRegisterImpl::S, base, offset, reg); 1044 } else { 1045 __ ldf(FloatRegisterImpl::D, base, offset, to_reg->as_double_reg()); 1046 } 1047 break; 1048 } 1049 default : ShouldNotReachHere(); 1050 } 1051 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); 1052 } 1053 return load_offset; 1054 } 1055 1056 1057 int LIR_Assembler::load(Register base, Register disp, LIR_Opr to_reg, BasicType type) { 1058 int load_offset = code_offset(); 1059 switch(type) { 1060 case T_BOOLEAN: // fall through 1061 case T_BYTE : __ ldsb(base, disp, to_reg->as_register()); break; 1062 case T_CHAR : __ lduh(base, disp, to_reg->as_register()); break; 1063 case T_SHORT : __ ldsh(base, disp, to_reg->as_register()); break; 1064 case T_INT : __ ld(base, disp, to_reg->as_register()); break; 1065 case T_ADDRESS:// fall through 1066 case T_ARRAY : // fall through 1067 case T_OBJECT: __ ld_ptr(base, disp, to_reg->as_register()); break; 1068 case T_FLOAT: __ ldf(FloatRegisterImpl::S, base, disp, to_reg->as_float_reg()); break; 1069 case T_DOUBLE: __ ldf(FloatRegisterImpl::D, base, disp, to_reg->as_double_reg()); break; 1070 case T_LONG : 1071 #ifdef _LP64 1072 __ ldx(base, disp, to_reg->as_register_lo()); 1073 #else 1074 assert(to_reg->as_register_hi()->successor() == to_reg->as_register_lo(), 1075 "must be sequential"); 1076 __ ldd(base, disp, to_reg->as_register_hi()); 1077 #endif 1078 break; 1079 default : ShouldNotReachHere(); 1080 } 1081 if (type == T_ARRAY || type == T_OBJECT) __ verify_oop(to_reg->as_register()); 1082 return load_offset; 1083 } 1084 1085 1086 // load/store with an Address 1087 void LIR_Assembler::load(const Address& a, Register d, BasicType ld_type, CodeEmitInfo *info, int offset) { 1088 load(a.base(), a.disp() + offset, d, ld_type, info); 1089 } 1090 1091 1092 void LIR_Assembler::store(Register value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { 1093 store(value, dest.base(), dest.disp() + offset, type, info); 1094 } 1095 1096 1097 // loadf/storef with an Address 1098 void LIR_Assembler::load(const Address& a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info, int offset) { 1099 load(a.base(), a.disp() + offset, d, ld_type, info); 1100 } 1101 1102 1103 void LIR_Assembler::store(FloatRegister value, const Address& dest, BasicType type, CodeEmitInfo *info, int offset) { 1104 store(value, dest.base(), dest.disp() + offset, type, info); 1105 } 1106 1107 1108 // load/store with an Address 1109 void LIR_Assembler::load(LIR_Address* a, Register d, BasicType ld_type, CodeEmitInfo *info) { 1110 load(as_Address(a), d, ld_type, info); 1111 } 1112 1113 1114 void LIR_Assembler::store(Register value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { 1115 store(value, as_Address(dest), type, info); 1116 } 1117 1118 1119 // loadf/storef with an Address 1120 void LIR_Assembler::load(LIR_Address* a, FloatRegister d, BasicType ld_type, CodeEmitInfo *info) { 1121 load(as_Address(a), d, ld_type, info); 1122 } 1123 1124 1125 void LIR_Assembler::store(FloatRegister value, LIR_Address* dest, BasicType type, CodeEmitInfo *info) { 1126 store(value, as_Address(dest), type, info); 1127 } 1128 1129 1130 void LIR_Assembler::const2stack(LIR_Opr src, LIR_Opr dest) { 1131 LIR_Const* c = src->as_constant_ptr(); 1132 switch (c->type()) { 1133 case T_INT: 1134 case T_FLOAT: 1135 case T_ADDRESS: { 1136 Register src_reg = O7; 1137 int value = c->as_jint_bits(); 1138 if (value == 0) { 1139 src_reg = G0; 1140 } else { 1141 __ set(value, O7); 1142 } 1143 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1144 __ stw(src_reg, addr.base(), addr.disp()); 1145 break; 1146 } 1147 case T_OBJECT: { 1148 Register src_reg = O7; 1149 jobject2reg(c->as_jobject(), src_reg); 1150 Address addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1151 __ st_ptr(src_reg, addr.base(), addr.disp()); 1152 break; 1153 } 1154 case T_LONG: 1155 case T_DOUBLE: { 1156 Address addr = frame_map()->address_for_double_slot(dest->double_stack_ix()); 1157 1158 Register tmp = O7; 1159 int value_lo = c->as_jint_lo_bits(); 1160 if (value_lo == 0) { 1161 tmp = G0; 1162 } else { 1163 __ set(value_lo, O7); 1164 } 1165 __ stw(tmp, addr.base(), addr.disp() + lo_word_offset_in_bytes); 1166 int value_hi = c->as_jint_hi_bits(); 1167 if (value_hi == 0) { 1168 tmp = G0; 1169 } else { 1170 __ set(value_hi, O7); 1171 } 1172 __ stw(tmp, addr.base(), addr.disp() + hi_word_offset_in_bytes); 1173 break; 1174 } 1175 default: 1176 Unimplemented(); 1177 } 1178 } 1179 1180 1181 void LIR_Assembler::const2mem(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info ) { 1182 LIR_Const* c = src->as_constant_ptr(); 1183 LIR_Address* addr = dest->as_address_ptr(); 1184 Register base = addr->base()->as_pointer_register(); 1185 1186 if (info != NULL) { 1187 add_debug_info_for_null_check_here(info); 1188 } 1189 switch (c->type()) { 1190 case T_INT: 1191 case T_FLOAT: 1192 case T_ADDRESS: { 1193 LIR_Opr tmp = FrameMap::O7_opr; 1194 int value = c->as_jint_bits(); 1195 if (value == 0) { 1196 tmp = FrameMap::G0_opr; 1197 } else if (Assembler::is_simm13(value)) { 1198 __ set(value, O7); 1199 } 1200 if (addr->index()->is_valid()) { 1201 assert(addr->disp() == 0, "must be zero"); 1202 store(tmp, base, addr->index()->as_pointer_register(), type); 1203 } else { 1204 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); 1205 store(tmp, base, addr->disp(), type); 1206 } 1207 break; 1208 } 1209 case T_LONG: 1210 case T_DOUBLE: { 1211 assert(!addr->index()->is_valid(), "can't handle reg reg address here"); 1212 assert(Assembler::is_simm13(addr->disp()) && 1213 Assembler::is_simm13(addr->disp() + 4), "can't handle larger addresses"); 1214 1215 Register tmp = O7; 1216 int value_lo = c->as_jint_lo_bits(); 1217 if (value_lo == 0) { 1218 tmp = G0; 1219 } else { 1220 __ set(value_lo, O7); 1221 } 1222 store(tmp, base, addr->disp() + lo_word_offset_in_bytes, T_INT); 1223 int value_hi = c->as_jint_hi_bits(); 1224 if (value_hi == 0) { 1225 tmp = G0; 1226 } else { 1227 __ set(value_hi, O7); 1228 } 1229 store(tmp, base, addr->disp() + hi_word_offset_in_bytes, T_INT); 1230 break; 1231 } 1232 case T_OBJECT: { 1233 jobject obj = c->as_jobject(); 1234 LIR_Opr tmp; 1235 if (obj == NULL) { 1236 tmp = FrameMap::G0_opr; 1237 } else { 1238 tmp = FrameMap::O7_opr; 1239 jobject2reg(c->as_jobject(), O7); 1240 } 1241 // handle either reg+reg or reg+disp address 1242 if (addr->index()->is_valid()) { 1243 assert(addr->disp() == 0, "must be zero"); 1244 store(tmp, base, addr->index()->as_pointer_register(), type); 1245 } else { 1246 assert(Assembler::is_simm13(addr->disp()), "can't handle larger addresses"); 1247 store(tmp, base, addr->disp(), type); 1248 } 1249 1250 break; 1251 } 1252 default: 1253 Unimplemented(); 1254 } 1255 } 1256 1257 1258 void LIR_Assembler::const2reg(LIR_Opr src, LIR_Opr dest, LIR_PatchCode patch_code, CodeEmitInfo* info) { 1259 LIR_Const* c = src->as_constant_ptr(); 1260 LIR_Opr to_reg = dest; 1261 1262 switch (c->type()) { 1263 case T_INT: 1264 case T_ADDRESS: 1265 { 1266 jint con = c->as_jint(); 1267 if (to_reg->is_single_cpu()) { 1268 assert(patch_code == lir_patch_none, "no patching handled here"); 1269 __ set(con, to_reg->as_register()); 1270 } else { 1271 ShouldNotReachHere(); 1272 assert(to_reg->is_single_fpu(), "wrong register kind"); 1273 1274 __ set(con, O7); 1275 Address temp_slot(SP, (frame::register_save_words * wordSize) + STACK_BIAS); 1276 __ st(O7, temp_slot); 1277 __ ldf(FloatRegisterImpl::S, temp_slot, to_reg->as_float_reg()); 1278 } 1279 } 1280 break; 1281 1282 case T_LONG: 1283 { 1284 jlong con = c->as_jlong(); 1285 1286 if (to_reg->is_double_cpu()) { 1287 #ifdef _LP64 1288 __ set(con, to_reg->as_register_lo()); 1289 #else 1290 __ set(low(con), to_reg->as_register_lo()); 1291 __ set(high(con), to_reg->as_register_hi()); 1292 #endif 1293 #ifdef _LP64 1294 } else if (to_reg->is_single_cpu()) { 1295 __ set(con, to_reg->as_register()); 1296 #endif 1297 } else { 1298 ShouldNotReachHere(); 1299 assert(to_reg->is_double_fpu(), "wrong register kind"); 1300 Address temp_slot_lo(SP, ((frame::register_save_words ) * wordSize) + STACK_BIAS); 1301 Address temp_slot_hi(SP, ((frame::register_save_words) * wordSize) + (longSize/2) + STACK_BIAS); 1302 __ set(low(con), O7); 1303 __ st(O7, temp_slot_lo); 1304 __ set(high(con), O7); 1305 __ st(O7, temp_slot_hi); 1306 __ ldf(FloatRegisterImpl::D, temp_slot_lo, to_reg->as_double_reg()); 1307 } 1308 } 1309 break; 1310 1311 case T_OBJECT: 1312 { 1313 if (patch_code == lir_patch_none) { 1314 jobject2reg(c->as_jobject(), to_reg->as_register()); 1315 } else { 1316 jobject2reg_with_patching(to_reg->as_register(), info); 1317 } 1318 } 1319 break; 1320 1321 case T_FLOAT: 1322 { 1323 address const_addr = __ float_constant(c->as_jfloat()); 1324 if (const_addr == NULL) { 1325 bailout("const section overflow"); 1326 break; 1327 } 1328 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1329 AddressLiteral const_addrlit(const_addr, rspec); 1330 if (to_reg->is_single_fpu()) { 1331 __ patchable_sethi(const_addrlit, O7); 1332 __ relocate(rspec); 1333 __ ldf(FloatRegisterImpl::S, O7, const_addrlit.low10(), to_reg->as_float_reg()); 1334 1335 } else { 1336 assert(to_reg->is_single_cpu(), "Must be a cpu register."); 1337 1338 __ set(const_addrlit, O7); 1339 load(O7, 0, to_reg->as_register(), T_INT); 1340 } 1341 } 1342 break; 1343 1344 case T_DOUBLE: 1345 { 1346 address const_addr = __ double_constant(c->as_jdouble()); 1347 if (const_addr == NULL) { 1348 bailout("const section overflow"); 1349 break; 1350 } 1351 RelocationHolder rspec = internal_word_Relocation::spec(const_addr); 1352 1353 if (to_reg->is_double_fpu()) { 1354 AddressLiteral const_addrlit(const_addr, rspec); 1355 __ patchable_sethi(const_addrlit, O7); 1356 __ relocate(rspec); 1357 __ ldf (FloatRegisterImpl::D, O7, const_addrlit.low10(), to_reg->as_double_reg()); 1358 } else { 1359 assert(to_reg->is_double_cpu(), "Must be a long register."); 1360 #ifdef _LP64 1361 __ set(jlong_cast(c->as_jdouble()), to_reg->as_register_lo()); 1362 #else 1363 __ set(low(jlong_cast(c->as_jdouble())), to_reg->as_register_lo()); 1364 __ set(high(jlong_cast(c->as_jdouble())), to_reg->as_register_hi()); 1365 #endif 1366 } 1367 1368 } 1369 break; 1370 1371 default: 1372 ShouldNotReachHere(); 1373 } 1374 } 1375 1376 Address LIR_Assembler::as_Address(LIR_Address* addr) { 1377 Register reg = addr->base()->as_register(); 1378 return Address(reg, addr->disp()); 1379 } 1380 1381 1382 void LIR_Assembler::stack2stack(LIR_Opr src, LIR_Opr dest, BasicType type) { 1383 switch (type) { 1384 case T_INT: 1385 case T_FLOAT: { 1386 Register tmp = O7; 1387 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1388 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1389 __ lduw(from.base(), from.disp(), tmp); 1390 __ stw(tmp, to.base(), to.disp()); 1391 break; 1392 } 1393 case T_OBJECT: { 1394 Register tmp = O7; 1395 Address from = frame_map()->address_for_slot(src->single_stack_ix()); 1396 Address to = frame_map()->address_for_slot(dest->single_stack_ix()); 1397 __ ld_ptr(from.base(), from.disp(), tmp); 1398 __ st_ptr(tmp, to.base(), to.disp()); 1399 break; 1400 } 1401 case T_LONG: 1402 case T_DOUBLE: { 1403 Register tmp = O7; 1404 Address from = frame_map()->address_for_double_slot(src->double_stack_ix()); 1405 Address to = frame_map()->address_for_double_slot(dest->double_stack_ix()); 1406 __ lduw(from.base(), from.disp(), tmp); 1407 __ stw(tmp, to.base(), to.disp()); 1408 __ lduw(from.base(), from.disp() + 4, tmp); 1409 __ stw(tmp, to.base(), to.disp() + 4); 1410 break; 1411 } 1412 1413 default: 1414 ShouldNotReachHere(); 1415 } 1416 } 1417 1418 1419 Address LIR_Assembler::as_Address_hi(LIR_Address* addr) { 1420 Address base = as_Address(addr); 1421 return Address(base.base(), base.disp() + hi_word_offset_in_bytes); 1422 } 1423 1424 1425 Address LIR_Assembler::as_Address_lo(LIR_Address* addr) { 1426 Address base = as_Address(addr); 1427 return Address(base.base(), base.disp() + lo_word_offset_in_bytes); 1428 } 1429 1430 1431 void LIR_Assembler::mem2reg(LIR_Opr src_opr, LIR_Opr dest, BasicType type, 1432 LIR_PatchCode patch_code, CodeEmitInfo* info, bool unaligned) { 1433 1434 LIR_Address* addr = src_opr->as_address_ptr(); 1435 LIR_Opr to_reg = dest; 1436 1437 Register src = addr->base()->as_pointer_register(); 1438 Register disp_reg = noreg; 1439 int disp_value = addr->disp(); 1440 bool needs_patching = (patch_code != lir_patch_none); 1441 1442 if (addr->base()->type() == T_OBJECT) { 1443 __ verify_oop(src); 1444 } 1445 1446 PatchingStub* patch = NULL; 1447 if (needs_patching) { 1448 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1449 assert(!to_reg->is_double_cpu() || 1450 patch_code == lir_patch_none || 1451 patch_code == lir_patch_normal, "patching doesn't match register"); 1452 } 1453 1454 if (addr->index()->is_illegal()) { 1455 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { 1456 if (needs_patching) { 1457 __ patchable_set(0, O7); 1458 } else { 1459 __ set(disp_value, O7); 1460 } 1461 disp_reg = O7; 1462 } 1463 } else if (unaligned || PatchALot) { 1464 __ add(src, addr->index()->as_register(), O7); 1465 src = O7; 1466 } else { 1467 disp_reg = addr->index()->as_pointer_register(); 1468 assert(disp_value == 0, "can't handle 3 operand addresses"); 1469 } 1470 1471 // remember the offset of the load. The patching_epilog must be done 1472 // before the call to add_debug_info, otherwise the PcDescs don't get 1473 // entered in increasing order. 1474 int offset = code_offset(); 1475 1476 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); 1477 if (disp_reg == noreg) { 1478 offset = load(src, disp_value, to_reg, type, unaligned); 1479 } else { 1480 assert(!unaligned, "can't handle this"); 1481 offset = load(src, disp_reg, to_reg, type); 1482 } 1483 1484 if (patch != NULL) { 1485 patching_epilog(patch, patch_code, src, info); 1486 } 1487 1488 if (info != NULL) add_debug_info_for_null_check(offset, info); 1489 } 1490 1491 1492 void LIR_Assembler::prefetchr(LIR_Opr src) { 1493 LIR_Address* addr = src->as_address_ptr(); 1494 Address from_addr = as_Address(addr); 1495 1496 if (VM_Version::has_v9()) { 1497 __ prefetch(from_addr, Assembler::severalReads); 1498 } 1499 } 1500 1501 1502 void LIR_Assembler::prefetchw(LIR_Opr src) { 1503 LIR_Address* addr = src->as_address_ptr(); 1504 Address from_addr = as_Address(addr); 1505 1506 if (VM_Version::has_v9()) { 1507 __ prefetch(from_addr, Assembler::severalWritesAndPossiblyReads); 1508 } 1509 } 1510 1511 1512 void LIR_Assembler::stack2reg(LIR_Opr src, LIR_Opr dest, BasicType type) { 1513 Address addr; 1514 if (src->is_single_word()) { 1515 addr = frame_map()->address_for_slot(src->single_stack_ix()); 1516 } else if (src->is_double_word()) { 1517 addr = frame_map()->address_for_double_slot(src->double_stack_ix()); 1518 } 1519 1520 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1521 load(addr.base(), addr.disp(), dest, dest->type(), unaligned); 1522 } 1523 1524 1525 void LIR_Assembler::reg2stack(LIR_Opr from_reg, LIR_Opr dest, BasicType type, bool pop_fpu_stack) { 1526 Address addr; 1527 if (dest->is_single_word()) { 1528 addr = frame_map()->address_for_slot(dest->single_stack_ix()); 1529 } else if (dest->is_double_word()) { 1530 addr = frame_map()->address_for_slot(dest->double_stack_ix()); 1531 } 1532 bool unaligned = (addr.disp() - STACK_BIAS) % 8 != 0; 1533 store(from_reg, addr.base(), addr.disp(), from_reg->type(), unaligned); 1534 } 1535 1536 1537 void LIR_Assembler::reg2reg(LIR_Opr from_reg, LIR_Opr to_reg) { 1538 if (from_reg->is_float_kind() && to_reg->is_float_kind()) { 1539 if (from_reg->is_double_fpu()) { 1540 // double to double moves 1541 assert(to_reg->is_double_fpu(), "should match"); 1542 __ fmov(FloatRegisterImpl::D, from_reg->as_double_reg(), to_reg->as_double_reg()); 1543 } else { 1544 // float to float moves 1545 assert(to_reg->is_single_fpu(), "should match"); 1546 __ fmov(FloatRegisterImpl::S, from_reg->as_float_reg(), to_reg->as_float_reg()); 1547 } 1548 } else if (!from_reg->is_float_kind() && !to_reg->is_float_kind()) { 1549 if (from_reg->is_double_cpu()) { 1550 #ifdef _LP64 1551 __ mov(from_reg->as_pointer_register(), to_reg->as_pointer_register()); 1552 #else 1553 assert(to_reg->is_double_cpu() && 1554 from_reg->as_register_hi() != to_reg->as_register_lo() && 1555 from_reg->as_register_lo() != to_reg->as_register_hi(), 1556 "should both be long and not overlap"); 1557 // long to long moves 1558 __ mov(from_reg->as_register_hi(), to_reg->as_register_hi()); 1559 __ mov(from_reg->as_register_lo(), to_reg->as_register_lo()); 1560 #endif 1561 #ifdef _LP64 1562 } else if (to_reg->is_double_cpu()) { 1563 // int to int moves 1564 __ mov(from_reg->as_register(), to_reg->as_register_lo()); 1565 #endif 1566 } else { 1567 // int to int moves 1568 __ mov(from_reg->as_register(), to_reg->as_register()); 1569 } 1570 } else { 1571 ShouldNotReachHere(); 1572 } 1573 if (to_reg->type() == T_OBJECT || to_reg->type() == T_ARRAY) { 1574 __ verify_oop(to_reg->as_register()); 1575 } 1576 } 1577 1578 1579 void LIR_Assembler::reg2mem(LIR_Opr from_reg, LIR_Opr dest, BasicType type, 1580 LIR_PatchCode patch_code, CodeEmitInfo* info, bool pop_fpu_stack, 1581 bool unaligned) { 1582 LIR_Address* addr = dest->as_address_ptr(); 1583 1584 Register src = addr->base()->as_pointer_register(); 1585 Register disp_reg = noreg; 1586 int disp_value = addr->disp(); 1587 bool needs_patching = (patch_code != lir_patch_none); 1588 1589 if (addr->base()->is_oop_register()) { 1590 __ verify_oop(src); 1591 } 1592 1593 PatchingStub* patch = NULL; 1594 if (needs_patching) { 1595 patch = new PatchingStub(_masm, PatchingStub::access_field_id); 1596 assert(!from_reg->is_double_cpu() || 1597 patch_code == lir_patch_none || 1598 patch_code == lir_patch_normal, "patching doesn't match register"); 1599 } 1600 1601 if (addr->index()->is_illegal()) { 1602 if (!Assembler::is_simm13(disp_value) && (!unaligned || Assembler::is_simm13(disp_value + 4))) { 1603 if (needs_patching) { 1604 __ patchable_set(0, O7); 1605 } else { 1606 __ set(disp_value, O7); 1607 } 1608 disp_reg = O7; 1609 } 1610 } else if (unaligned || PatchALot) { 1611 __ add(src, addr->index()->as_register(), O7); 1612 src = O7; 1613 } else { 1614 disp_reg = addr->index()->as_pointer_register(); 1615 assert(disp_value == 0, "can't handle 3 operand addresses"); 1616 } 1617 1618 // remember the offset of the store. The patching_epilog must be done 1619 // before the call to add_debug_info_for_null_check, otherwise the PcDescs don't get 1620 // entered in increasing order. 1621 int offset; 1622 1623 assert(disp_reg != noreg || Assembler::is_simm13(disp_value), "should have set this up"); 1624 if (disp_reg == noreg) { 1625 offset = store(from_reg, src, disp_value, type, unaligned); 1626 } else { 1627 assert(!unaligned, "can't handle this"); 1628 offset = store(from_reg, src, disp_reg, type); 1629 } 1630 1631 if (patch != NULL) { 1632 patching_epilog(patch, patch_code, src, info); 1633 } 1634 1635 if (info != NULL) add_debug_info_for_null_check(offset, info); 1636 } 1637 1638 1639 void LIR_Assembler::return_op(LIR_Opr result) { 1640 // the poll may need a register so just pick one that isn't the return register 1641 #if defined(TIERED) && !defined(_LP64) 1642 if (result->type_field() == LIR_OprDesc::long_type) { 1643 // Must move the result to G1 1644 // Must leave proper result in O0,O1 and G1 (TIERED only) 1645 __ sllx(I0, 32, G1); // Shift bits into high G1 1646 __ srl (I1, 0, I1); // Zero extend O1 (harmless?) 1647 __ or3 (I1, G1, G1); // OR 64 bits into G1 1648 #ifdef ASSERT 1649 // mangle it so any problems will show up 1650 __ set(0xdeadbeef, I0); 1651 __ set(0xdeadbeef, I1); 1652 #endif 1653 } 1654 #endif // TIERED 1655 __ set((intptr_t)os::get_polling_page(), L0); 1656 __ relocate(relocInfo::poll_return_type); 1657 __ ld_ptr(L0, 0, G0); 1658 __ ret(); 1659 __ delayed()->restore(); 1660 } 1661 1662 1663 int LIR_Assembler::safepoint_poll(LIR_Opr tmp, CodeEmitInfo* info) { 1664 __ set((intptr_t)os::get_polling_page(), tmp->as_register()); 1665 if (info != NULL) { 1666 add_debug_info_for_branch(info); 1667 } else { 1668 __ relocate(relocInfo::poll_type); 1669 } 1670 1671 int offset = __ offset(); 1672 __ ld_ptr(tmp->as_register(), 0, G0); 1673 1674 return offset; 1675 } 1676 1677 1678 void LIR_Assembler::emit_static_call_stub() { 1679 address call_pc = __ pc(); 1680 address stub = __ start_a_stub(call_stub_size); 1681 if (stub == NULL) { 1682 bailout("static call stub overflow"); 1683 return; 1684 } 1685 1686 int start = __ offset(); 1687 __ relocate(static_stub_Relocation::spec(call_pc)); 1688 1689 __ set_oop(NULL, G5); 1690 // must be set to -1 at code generation time 1691 AddressLiteral addrlit(-1); 1692 __ jump_to(addrlit, G3); 1693 __ delayed()->nop(); 1694 1695 assert(__ offset() - start <= call_stub_size, "stub too big"); 1696 __ end_a_stub(); 1697 } 1698 1699 1700 void LIR_Assembler::comp_op(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Op2* op) { 1701 if (opr1->is_single_fpu()) { 1702 __ fcmp(FloatRegisterImpl::S, Assembler::fcc0, opr1->as_float_reg(), opr2->as_float_reg()); 1703 } else if (opr1->is_double_fpu()) { 1704 __ fcmp(FloatRegisterImpl::D, Assembler::fcc0, opr1->as_double_reg(), opr2->as_double_reg()); 1705 } else if (opr1->is_single_cpu()) { 1706 if (opr2->is_constant()) { 1707 switch (opr2->as_constant_ptr()->type()) { 1708 case T_INT: 1709 { jint con = opr2->as_constant_ptr()->as_jint(); 1710 if (Assembler::is_simm13(con)) { 1711 __ cmp(opr1->as_register(), con); 1712 } else { 1713 __ set(con, O7); 1714 __ cmp(opr1->as_register(), O7); 1715 } 1716 } 1717 break; 1718 1719 case T_OBJECT: 1720 // there are only equal/notequal comparisions on objects 1721 { jobject con = opr2->as_constant_ptr()->as_jobject(); 1722 if (con == NULL) { 1723 __ cmp(opr1->as_register(), 0); 1724 } else { 1725 jobject2reg(con, O7); 1726 __ cmp(opr1->as_register(), O7); 1727 } 1728 } 1729 break; 1730 1731 default: 1732 ShouldNotReachHere(); 1733 break; 1734 } 1735 } else { 1736 if (opr2->is_address()) { 1737 LIR_Address * addr = opr2->as_address_ptr(); 1738 BasicType type = addr->type(); 1739 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); 1740 else __ ld(as_Address(addr), O7); 1741 __ cmp(opr1->as_register(), O7); 1742 } else { 1743 __ cmp(opr1->as_register(), opr2->as_register()); 1744 } 1745 } 1746 } else if (opr1->is_double_cpu()) { 1747 Register xlo = opr1->as_register_lo(); 1748 Register xhi = opr1->as_register_hi(); 1749 if (opr2->is_constant() && opr2->as_jlong() == 0) { 1750 assert(condition == lir_cond_equal || condition == lir_cond_notEqual, "only handles these cases"); 1751 #ifdef _LP64 1752 __ orcc(xhi, G0, G0); 1753 #else 1754 __ orcc(xhi, xlo, G0); 1755 #endif 1756 } else if (opr2->is_register()) { 1757 Register ylo = opr2->as_register_lo(); 1758 Register yhi = opr2->as_register_hi(); 1759 #ifdef _LP64 1760 __ cmp(xlo, ylo); 1761 #else 1762 __ subcc(xlo, ylo, xlo); 1763 __ subccc(xhi, yhi, xhi); 1764 if (condition == lir_cond_equal || condition == lir_cond_notEqual) { 1765 __ orcc(xhi, xlo, G0); 1766 } 1767 #endif 1768 } else { 1769 ShouldNotReachHere(); 1770 } 1771 } else if (opr1->is_address()) { 1772 LIR_Address * addr = opr1->as_address_ptr(); 1773 BasicType type = addr->type(); 1774 assert (opr2->is_constant(), "Checking"); 1775 if ( type == T_OBJECT ) __ ld_ptr(as_Address(addr), O7); 1776 else __ ld(as_Address(addr), O7); 1777 __ cmp(O7, opr2->as_constant_ptr()->as_jint()); 1778 } else { 1779 ShouldNotReachHere(); 1780 } 1781 } 1782 1783 1784 void LIR_Assembler::comp_fl2i(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dst, LIR_Op2* op){ 1785 if (code == lir_cmp_fd2i || code == lir_ucmp_fd2i) { 1786 bool is_unordered_less = (code == lir_ucmp_fd2i); 1787 if (left->is_single_fpu()) { 1788 __ float_cmp(true, is_unordered_less ? -1 : 1, left->as_float_reg(), right->as_float_reg(), dst->as_register()); 1789 } else if (left->is_double_fpu()) { 1790 __ float_cmp(false, is_unordered_less ? -1 : 1, left->as_double_reg(), right->as_double_reg(), dst->as_register()); 1791 } else { 1792 ShouldNotReachHere(); 1793 } 1794 } else if (code == lir_cmp_l2i) { 1795 #ifdef _LP64 1796 __ lcmp(left->as_register_lo(), right->as_register_lo(), dst->as_register()); 1797 #else 1798 __ lcmp(left->as_register_hi(), left->as_register_lo(), 1799 right->as_register_hi(), right->as_register_lo(), 1800 dst->as_register()); 1801 #endif 1802 } else { 1803 ShouldNotReachHere(); 1804 } 1805 } 1806 1807 1808 void LIR_Assembler::cmove(LIR_Condition condition, LIR_Opr opr1, LIR_Opr opr2, LIR_Opr result) { 1809 1810 Assembler::Condition acond; 1811 switch (condition) { 1812 case lir_cond_equal: acond = Assembler::equal; break; 1813 case lir_cond_notEqual: acond = Assembler::notEqual; break; 1814 case lir_cond_less: acond = Assembler::less; break; 1815 case lir_cond_lessEqual: acond = Assembler::lessEqual; break; 1816 case lir_cond_greaterEqual: acond = Assembler::greaterEqual; break; 1817 case lir_cond_greater: acond = Assembler::greater; break; 1818 case lir_cond_aboveEqual: acond = Assembler::greaterEqualUnsigned; break; 1819 case lir_cond_belowEqual: acond = Assembler::lessEqualUnsigned; break; 1820 default: ShouldNotReachHere(); 1821 }; 1822 1823 if (opr1->is_constant() && opr1->type() == T_INT) { 1824 Register dest = result->as_register(); 1825 // load up first part of constant before branch 1826 // and do the rest in the delay slot. 1827 if (!Assembler::is_simm13(opr1->as_jint())) { 1828 __ sethi(opr1->as_jint(), dest); 1829 } 1830 } else if (opr1->is_constant()) { 1831 const2reg(opr1, result, lir_patch_none, NULL); 1832 } else if (opr1->is_register()) { 1833 reg2reg(opr1, result); 1834 } else if (opr1->is_stack()) { 1835 stack2reg(opr1, result, result->type()); 1836 } else { 1837 ShouldNotReachHere(); 1838 } 1839 Label skip; 1840 __ br(acond, false, Assembler::pt, skip); 1841 if (opr1->is_constant() && opr1->type() == T_INT) { 1842 Register dest = result->as_register(); 1843 if (Assembler::is_simm13(opr1->as_jint())) { 1844 __ delayed()->or3(G0, opr1->as_jint(), dest); 1845 } else { 1846 // the sethi has been done above, so just put in the low 10 bits 1847 __ delayed()->or3(dest, opr1->as_jint() & 0x3ff, dest); 1848 } 1849 } else { 1850 // can't do anything useful in the delay slot 1851 __ delayed()->nop(); 1852 } 1853 if (opr2->is_constant()) { 1854 const2reg(opr2, result, lir_patch_none, NULL); 1855 } else if (opr2->is_register()) { 1856 reg2reg(opr2, result); 1857 } else if (opr2->is_stack()) { 1858 stack2reg(opr2, result, result->type()); 1859 } else { 1860 ShouldNotReachHere(); 1861 } 1862 __ bind(skip); 1863 } 1864 1865 1866 void LIR_Assembler::arith_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest, CodeEmitInfo* info, bool pop_fpu_stack) { 1867 assert(info == NULL, "unused on this code path"); 1868 assert(left->is_register(), "wrong items state"); 1869 assert(dest->is_register(), "wrong items state"); 1870 1871 if (right->is_register()) { 1872 if (dest->is_float_kind()) { 1873 1874 FloatRegister lreg, rreg, res; 1875 FloatRegisterImpl::Width w; 1876 if (right->is_single_fpu()) { 1877 w = FloatRegisterImpl::S; 1878 lreg = left->as_float_reg(); 1879 rreg = right->as_float_reg(); 1880 res = dest->as_float_reg(); 1881 } else { 1882 w = FloatRegisterImpl::D; 1883 lreg = left->as_double_reg(); 1884 rreg = right->as_double_reg(); 1885 res = dest->as_double_reg(); 1886 } 1887 1888 switch (code) { 1889 case lir_add: __ fadd(w, lreg, rreg, res); break; 1890 case lir_sub: __ fsub(w, lreg, rreg, res); break; 1891 case lir_mul: // fall through 1892 case lir_mul_strictfp: __ fmul(w, lreg, rreg, res); break; 1893 case lir_div: // fall through 1894 case lir_div_strictfp: __ fdiv(w, lreg, rreg, res); break; 1895 default: ShouldNotReachHere(); 1896 } 1897 1898 } else if (dest->is_double_cpu()) { 1899 #ifdef _LP64 1900 Register dst_lo = dest->as_register_lo(); 1901 Register op1_lo = left->as_pointer_register(); 1902 Register op2_lo = right->as_pointer_register(); 1903 1904 switch (code) { 1905 case lir_add: 1906 __ add(op1_lo, op2_lo, dst_lo); 1907 break; 1908 1909 case lir_sub: 1910 __ sub(op1_lo, op2_lo, dst_lo); 1911 break; 1912 1913 default: ShouldNotReachHere(); 1914 } 1915 #else 1916 Register op1_lo = left->as_register_lo(); 1917 Register op1_hi = left->as_register_hi(); 1918 Register op2_lo = right->as_register_lo(); 1919 Register op2_hi = right->as_register_hi(); 1920 Register dst_lo = dest->as_register_lo(); 1921 Register dst_hi = dest->as_register_hi(); 1922 1923 switch (code) { 1924 case lir_add: 1925 __ addcc(op1_lo, op2_lo, dst_lo); 1926 __ addc (op1_hi, op2_hi, dst_hi); 1927 break; 1928 1929 case lir_sub: 1930 __ subcc(op1_lo, op2_lo, dst_lo); 1931 __ subc (op1_hi, op2_hi, dst_hi); 1932 break; 1933 1934 default: ShouldNotReachHere(); 1935 } 1936 #endif 1937 } else { 1938 assert (right->is_single_cpu(), "Just Checking"); 1939 1940 Register lreg = left->as_register(); 1941 Register res = dest->as_register(); 1942 Register rreg = right->as_register(); 1943 switch (code) { 1944 case lir_add: __ add (lreg, rreg, res); break; 1945 case lir_sub: __ sub (lreg, rreg, res); break; 1946 case lir_mul: __ mult (lreg, rreg, res); break; 1947 default: ShouldNotReachHere(); 1948 } 1949 } 1950 } else { 1951 assert (right->is_constant(), "must be constant"); 1952 1953 if (dest->is_single_cpu()) { 1954 Register lreg = left->as_register(); 1955 Register res = dest->as_register(); 1956 int simm13 = right->as_constant_ptr()->as_jint(); 1957 1958 switch (code) { 1959 case lir_add: __ add (lreg, simm13, res); break; 1960 case lir_sub: __ sub (lreg, simm13, res); break; 1961 case lir_mul: __ mult (lreg, simm13, res); break; 1962 default: ShouldNotReachHere(); 1963 } 1964 } else { 1965 Register lreg = left->as_pointer_register(); 1966 Register res = dest->as_register_lo(); 1967 long con = right->as_constant_ptr()->as_jlong(); 1968 assert(Assembler::is_simm13(con), "must be simm13"); 1969 1970 switch (code) { 1971 case lir_add: __ add (lreg, (int)con, res); break; 1972 case lir_sub: __ sub (lreg, (int)con, res); break; 1973 case lir_mul: __ mult (lreg, (int)con, res); break; 1974 default: ShouldNotReachHere(); 1975 } 1976 } 1977 } 1978 } 1979 1980 1981 void LIR_Assembler::fpop() { 1982 // do nothing 1983 } 1984 1985 1986 void LIR_Assembler::intrinsic_op(LIR_Code code, LIR_Opr value, LIR_Opr thread, LIR_Opr dest, LIR_Op* op) { 1987 switch (code) { 1988 case lir_sin: 1989 case lir_tan: 1990 case lir_cos: { 1991 assert(thread->is_valid(), "preserve the thread object for performance reasons"); 1992 assert(dest->as_double_reg() == F0, "the result will be in f0/f1"); 1993 break; 1994 } 1995 case lir_sqrt: { 1996 assert(!thread->is_valid(), "there is no need for a thread_reg for dsqrt"); 1997 FloatRegister src_reg = value->as_double_reg(); 1998 FloatRegister dst_reg = dest->as_double_reg(); 1999 __ fsqrt(FloatRegisterImpl::D, src_reg, dst_reg); 2000 break; 2001 } 2002 case lir_abs: { 2003 assert(!thread->is_valid(), "there is no need for a thread_reg for fabs"); 2004 FloatRegister src_reg = value->as_double_reg(); 2005 FloatRegister dst_reg = dest->as_double_reg(); 2006 __ fabs(FloatRegisterImpl::D, src_reg, dst_reg); 2007 break; 2008 } 2009 default: { 2010 ShouldNotReachHere(); 2011 break; 2012 } 2013 } 2014 } 2015 2016 2017 void LIR_Assembler::logic_op(LIR_Code code, LIR_Opr left, LIR_Opr right, LIR_Opr dest) { 2018 if (right->is_constant()) { 2019 if (dest->is_single_cpu()) { 2020 int simm13 = right->as_constant_ptr()->as_jint(); 2021 switch (code) { 2022 case lir_logic_and: __ and3 (left->as_register(), simm13, dest->as_register()); break; 2023 case lir_logic_or: __ or3 (left->as_register(), simm13, dest->as_register()); break; 2024 case lir_logic_xor: __ xor3 (left->as_register(), simm13, dest->as_register()); break; 2025 default: ShouldNotReachHere(); 2026 } 2027 } else { 2028 long c = right->as_constant_ptr()->as_jlong(); 2029 assert(c == (int)c && Assembler::is_simm13(c), "out of range"); 2030 int simm13 = (int)c; 2031 switch (code) { 2032 case lir_logic_and: 2033 #ifndef _LP64 2034 __ and3 (left->as_register_hi(), 0, dest->as_register_hi()); 2035 #endif 2036 __ and3 (left->as_register_lo(), simm13, dest->as_register_lo()); 2037 break; 2038 2039 case lir_logic_or: 2040 #ifndef _LP64 2041 __ or3 (left->as_register_hi(), 0, dest->as_register_hi()); 2042 #endif 2043 __ or3 (left->as_register_lo(), simm13, dest->as_register_lo()); 2044 break; 2045 2046 case lir_logic_xor: 2047 #ifndef _LP64 2048 __ xor3 (left->as_register_hi(), 0, dest->as_register_hi()); 2049 #endif 2050 __ xor3 (left->as_register_lo(), simm13, dest->as_register_lo()); 2051 break; 2052 2053 default: ShouldNotReachHere(); 2054 } 2055 } 2056 } else { 2057 assert(right->is_register(), "right should be in register"); 2058 2059 if (dest->is_single_cpu()) { 2060 switch (code) { 2061 case lir_logic_and: __ and3 (left->as_register(), right->as_register(), dest->as_register()); break; 2062 case lir_logic_or: __ or3 (left->as_register(), right->as_register(), dest->as_register()); break; 2063 case lir_logic_xor: __ xor3 (left->as_register(), right->as_register(), dest->as_register()); break; 2064 default: ShouldNotReachHere(); 2065 } 2066 } else { 2067 #ifdef _LP64 2068 Register l = (left->is_single_cpu() && left->is_oop_register()) ? left->as_register() : 2069 left->as_register_lo(); 2070 Register r = (right->is_single_cpu() && right->is_oop_register()) ? right->as_register() : 2071 right->as_register_lo(); 2072 2073 switch (code) { 2074 case lir_logic_and: __ and3 (l, r, dest->as_register_lo()); break; 2075 case lir_logic_or: __ or3 (l, r, dest->as_register_lo()); break; 2076 case lir_logic_xor: __ xor3 (l, r, dest->as_register_lo()); break; 2077 default: ShouldNotReachHere(); 2078 } 2079 #else 2080 switch (code) { 2081 case lir_logic_and: 2082 __ and3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); 2083 __ and3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); 2084 break; 2085 2086 case lir_logic_or: 2087 __ or3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); 2088 __ or3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); 2089 break; 2090 2091 case lir_logic_xor: 2092 __ xor3 (left->as_register_hi(), right->as_register_hi(), dest->as_register_hi()); 2093 __ xor3 (left->as_register_lo(), right->as_register_lo(), dest->as_register_lo()); 2094 break; 2095 2096 default: ShouldNotReachHere(); 2097 } 2098 #endif 2099 } 2100 } 2101 } 2102 2103 2104 int LIR_Assembler::shift_amount(BasicType t) { 2105 int elem_size = type2aelembytes(t); 2106 switch (elem_size) { 2107 case 1 : return 0; 2108 case 2 : return 1; 2109 case 4 : return 2; 2110 case 8 : return 3; 2111 } 2112 ShouldNotReachHere(); 2113 return -1; 2114 } 2115 2116 2117 void LIR_Assembler::throw_op(LIR_Opr exceptionPC, LIR_Opr exceptionOop, CodeEmitInfo* info) { 2118 assert(exceptionOop->as_register() == Oexception, "should match"); 2119 assert(exceptionPC->as_register() == Oissuing_pc, "should match"); 2120 2121 info->add_register_oop(exceptionOop); 2122 2123 // reuse the debug info from the safepoint poll for the throw op itself 2124 address pc_for_athrow = __ pc(); 2125 int pc_for_athrow_offset = __ offset(); 2126 RelocationHolder rspec = internal_word_Relocation::spec(pc_for_athrow); 2127 __ set(pc_for_athrow, Oissuing_pc, rspec); 2128 add_call_info(pc_for_athrow_offset, info); // for exception handler 2129 2130 __ call(Runtime1::entry_for(Runtime1::handle_exception_id), relocInfo::runtime_call_type); 2131 __ delayed()->nop(); 2132 } 2133 2134 2135 void LIR_Assembler::unwind_op(LIR_Opr exceptionOop) { 2136 assert(exceptionOop->as_register() == Oexception, "should match"); 2137 2138 __ br(Assembler::always, false, Assembler::pt, _unwind_handler_entry); 2139 __ delayed()->nop(); 2140 } 2141 2142 2143 void LIR_Assembler::emit_arraycopy(LIR_OpArrayCopy* op) { 2144 Register src = op->src()->as_register(); 2145 Register dst = op->dst()->as_register(); 2146 Register src_pos = op->src_pos()->as_register(); 2147 Register dst_pos = op->dst_pos()->as_register(); 2148 Register length = op->length()->as_register(); 2149 Register tmp = op->tmp()->as_register(); 2150 Register tmp2 = O7; 2151 2152 int flags = op->flags(); 2153 ciArrayKlass* default_type = op->expected_type(); 2154 BasicType basic_type = default_type != NULL ? default_type->element_type()->basic_type() : T_ILLEGAL; 2155 if (basic_type == T_ARRAY) basic_type = T_OBJECT; 2156 2157 // set up the arraycopy stub information 2158 ArrayCopyStub* stub = op->stub(); 2159 2160 // always do stub if no type information is available. it's ok if 2161 // the known type isn't loaded since the code sanity checks 2162 // in debug mode and the type isn't required when we know the exact type 2163 // also check that the type is an array type. 2164 // We also, for now, always call the stub if the barrier set requires a 2165 // write_ref_pre barrier (which the stub does, but none of the optimized 2166 // cases currently does). 2167 if (op->expected_type() == NULL || 2168 Universe::heap()->barrier_set()->has_write_ref_pre_barrier()) { 2169 __ mov(src, O0); 2170 __ mov(src_pos, O1); 2171 __ mov(dst, O2); 2172 __ mov(dst_pos, O3); 2173 __ mov(length, O4); 2174 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::arraycopy)); 2175 2176 __ br_zero(Assembler::less, false, Assembler::pn, O0, *stub->entry()); 2177 __ delayed()->nop(); 2178 __ bind(*stub->continuation()); 2179 return; 2180 } 2181 2182 assert(default_type != NULL && default_type->is_array_klass(), "must be true at this point"); 2183 2184 // make sure src and dst are non-null and load array length 2185 if (flags & LIR_OpArrayCopy::src_null_check) { 2186 __ tst(src); 2187 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); 2188 __ delayed()->nop(); 2189 } 2190 2191 if (flags & LIR_OpArrayCopy::dst_null_check) { 2192 __ tst(dst); 2193 __ br(Assembler::equal, false, Assembler::pn, *stub->entry()); 2194 __ delayed()->nop(); 2195 } 2196 2197 if (flags & LIR_OpArrayCopy::src_pos_positive_check) { 2198 // test src_pos register 2199 __ tst(src_pos); 2200 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); 2201 __ delayed()->nop(); 2202 } 2203 2204 if (flags & LIR_OpArrayCopy::dst_pos_positive_check) { 2205 // test dst_pos register 2206 __ tst(dst_pos); 2207 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); 2208 __ delayed()->nop(); 2209 } 2210 2211 if (flags & LIR_OpArrayCopy::length_positive_check) { 2212 // make sure length isn't negative 2213 __ tst(length); 2214 __ br(Assembler::less, false, Assembler::pn, *stub->entry()); 2215 __ delayed()->nop(); 2216 } 2217 2218 if (flags & LIR_OpArrayCopy::src_range_check) { 2219 __ ld(src, arrayOopDesc::length_offset_in_bytes(), tmp2); 2220 __ add(length, src_pos, tmp); 2221 __ cmp(tmp2, tmp); 2222 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); 2223 __ delayed()->nop(); 2224 } 2225 2226 if (flags & LIR_OpArrayCopy::dst_range_check) { 2227 __ ld(dst, arrayOopDesc::length_offset_in_bytes(), tmp2); 2228 __ add(length, dst_pos, tmp); 2229 __ cmp(tmp2, tmp); 2230 __ br(Assembler::carrySet, false, Assembler::pn, *stub->entry()); 2231 __ delayed()->nop(); 2232 } 2233 2234 if (flags & LIR_OpArrayCopy::type_check) { 2235 __ ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp); 2236 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2237 __ cmp(tmp, tmp2); 2238 __ br(Assembler::notEqual, false, Assembler::pt, *stub->entry()); 2239 __ delayed()->nop(); 2240 } 2241 2242 #ifdef ASSERT 2243 if (basic_type != T_OBJECT || !(flags & LIR_OpArrayCopy::type_check)) { 2244 // Sanity check the known type with the incoming class. For the 2245 // primitive case the types must match exactly with src.klass and 2246 // dst.klass each exactly matching the default type. For the 2247 // object array case, if no type check is needed then either the 2248 // dst type is exactly the expected type and the src type is a 2249 // subtype which we can't check or src is the same array as dst 2250 // but not necessarily exactly of type default_type. 2251 Label known_ok, halt; 2252 jobject2reg(op->expected_type()->constant_encoding(), tmp); 2253 __ ld_ptr(dst, oopDesc::klass_offset_in_bytes(), tmp2); 2254 if (basic_type != T_OBJECT) { 2255 __ cmp(tmp, tmp2); 2256 __ br(Assembler::notEqual, false, Assembler::pn, halt); 2257 __ delayed()->ld_ptr(src, oopDesc::klass_offset_in_bytes(), tmp2); 2258 __ cmp(tmp, tmp2); 2259 __ br(Assembler::equal, false, Assembler::pn, known_ok); 2260 __ delayed()->nop(); 2261 } else { 2262 __ cmp(tmp, tmp2); 2263 __ br(Assembler::equal, false, Assembler::pn, known_ok); 2264 __ delayed()->cmp(src, dst); 2265 __ br(Assembler::equal, false, Assembler::pn, known_ok); 2266 __ delayed()->nop(); 2267 } 2268 __ bind(halt); 2269 __ stop("incorrect type information in arraycopy"); 2270 __ bind(known_ok); 2271 } 2272 #endif 2273 2274 int shift = shift_amount(basic_type); 2275 2276 Register src_ptr = O0; 2277 Register dst_ptr = O1; 2278 Register len = O2; 2279 2280 __ add(src, arrayOopDesc::base_offset_in_bytes(basic_type), src_ptr); 2281 LP64_ONLY(__ sra(src_pos, 0, src_pos);) //higher 32bits must be null 2282 if (shift == 0) { 2283 __ add(src_ptr, src_pos, src_ptr); 2284 } else { 2285 __ sll(src_pos, shift, tmp); 2286 __ add(src_ptr, tmp, src_ptr); 2287 } 2288 2289 __ add(dst, arrayOopDesc::base_offset_in_bytes(basic_type), dst_ptr); 2290 LP64_ONLY(__ sra(dst_pos, 0, dst_pos);) //higher 32bits must be null 2291 if (shift == 0) { 2292 __ add(dst_ptr, dst_pos, dst_ptr); 2293 } else { 2294 __ sll(dst_pos, shift, tmp); 2295 __ add(dst_ptr, tmp, dst_ptr); 2296 } 2297 2298 if (basic_type != T_OBJECT) { 2299 if (shift == 0) { 2300 __ mov(length, len); 2301 } else { 2302 __ sll(length, shift, len); 2303 } 2304 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::primitive_arraycopy)); 2305 } else { 2306 // oop_arraycopy takes a length in number of elements, so don't scale it. 2307 __ mov(length, len); 2308 __ call_VM_leaf(tmp, CAST_FROM_FN_PTR(address, Runtime1::oop_arraycopy)); 2309 } 2310 2311 __ bind(*stub->continuation()); 2312 } 2313 2314 2315 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, LIR_Opr count, LIR_Opr dest, LIR_Opr tmp) { 2316 if (dest->is_single_cpu()) { 2317 #ifdef _LP64 2318 if (left->type() == T_OBJECT) { 2319 switch (code) { 2320 case lir_shl: __ sllx (left->as_register(), count->as_register(), dest->as_register()); break; 2321 case lir_shr: __ srax (left->as_register(), count->as_register(), dest->as_register()); break; 2322 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; 2323 default: ShouldNotReachHere(); 2324 } 2325 } else 2326 #endif 2327 switch (code) { 2328 case lir_shl: __ sll (left->as_register(), count->as_register(), dest->as_register()); break; 2329 case lir_shr: __ sra (left->as_register(), count->as_register(), dest->as_register()); break; 2330 case lir_ushr: __ srl (left->as_register(), count->as_register(), dest->as_register()); break; 2331 default: ShouldNotReachHere(); 2332 } 2333 } else { 2334 #ifdef _LP64 2335 switch (code) { 2336 case lir_shl: __ sllx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2337 case lir_shr: __ srax (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2338 case lir_ushr: __ srlx (left->as_register_lo(), count->as_register(), dest->as_register_lo()); break; 2339 default: ShouldNotReachHere(); 2340 } 2341 #else 2342 switch (code) { 2343 case lir_shl: __ lshl (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; 2344 case lir_shr: __ lshr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; 2345 case lir_ushr: __ lushr (left->as_register_hi(), left->as_register_lo(), count->as_register(), dest->as_register_hi(), dest->as_register_lo(), G3_scratch); break; 2346 default: ShouldNotReachHere(); 2347 } 2348 #endif 2349 } 2350 } 2351 2352 2353 void LIR_Assembler::shift_op(LIR_Code code, LIR_Opr left, jint count, LIR_Opr dest) { 2354 #ifdef _LP64 2355 if (left->type() == T_OBJECT) { 2356 count = count & 63; // shouldn't shift by more than sizeof(intptr_t) 2357 Register l = left->as_register(); 2358 Register d = dest->as_register_lo(); 2359 switch (code) { 2360 case lir_shl: __ sllx (l, count, d); break; 2361 case lir_shr: __ srax (l, count, d); break; 2362 case lir_ushr: __ srlx (l, count, d); break; 2363 default: ShouldNotReachHere(); 2364 } 2365 return; 2366 } 2367 #endif 2368 2369 if (dest->is_single_cpu()) { 2370 count = count & 0x1F; // Java spec 2371 switch (code) { 2372 case lir_shl: __ sll (left->as_register(), count, dest->as_register()); break; 2373 case lir_shr: __ sra (left->as_register(), count, dest->as_register()); break; 2374 case lir_ushr: __ srl (left->as_register(), count, dest->as_register()); break; 2375 default: ShouldNotReachHere(); 2376 } 2377 } else if (dest->is_double_cpu()) { 2378 count = count & 63; // Java spec 2379 switch (code) { 2380 case lir_shl: __ sllx (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2381 case lir_shr: __ srax (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2382 case lir_ushr: __ srlx (left->as_pointer_register(), count, dest->as_pointer_register()); break; 2383 default: ShouldNotReachHere(); 2384 } 2385 } else { 2386 ShouldNotReachHere(); 2387 } 2388 } 2389 2390 2391 void LIR_Assembler::emit_alloc_obj(LIR_OpAllocObj* op) { 2392 assert(op->tmp1()->as_register() == G1 && 2393 op->tmp2()->as_register() == G3 && 2394 op->tmp3()->as_register() == G4 && 2395 op->obj()->as_register() == O0 && 2396 op->klass()->as_register() == G5, "must be"); 2397 if (op->init_check()) { 2398 __ ld(op->klass()->as_register(), 2399 instanceKlass::init_state_offset_in_bytes() + sizeof(oopDesc), 2400 op->tmp1()->as_register()); 2401 add_debug_info_for_null_check_here(op->stub()->info()); 2402 __ cmp(op->tmp1()->as_register(), instanceKlass::fully_initialized); 2403 __ br(Assembler::notEqual, false, Assembler::pn, *op->stub()->entry()); 2404 __ delayed()->nop(); 2405 } 2406 __ allocate_object(op->obj()->as_register(), 2407 op->tmp1()->as_register(), 2408 op->tmp2()->as_register(), 2409 op->tmp3()->as_register(), 2410 op->header_size(), 2411 op->object_size(), 2412 op->klass()->as_register(), 2413 *op->stub()->entry()); 2414 __ bind(*op->stub()->continuation()); 2415 __ verify_oop(op->obj()->as_register()); 2416 } 2417 2418 2419 void LIR_Assembler::emit_alloc_array(LIR_OpAllocArray* op) { 2420 assert(op->tmp1()->as_register() == G1 && 2421 op->tmp2()->as_register() == G3 && 2422 op->tmp3()->as_register() == G4 && 2423 op->tmp4()->as_register() == O1 && 2424 op->klass()->as_register() == G5, "must be"); 2425 if (UseSlowPath || 2426 (!UseFastNewObjectArray && (op->type() == T_OBJECT || op->type() == T_ARRAY)) || 2427 (!UseFastNewTypeArray && (op->type() != T_OBJECT && op->type() != T_ARRAY))) { 2428 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2429 __ delayed()->nop(); 2430 } else { 2431 __ allocate_array(op->obj()->as_register(), 2432 op->len()->as_register(), 2433 op->tmp1()->as_register(), 2434 op->tmp2()->as_register(), 2435 op->tmp3()->as_register(), 2436 arrayOopDesc::header_size(op->type()), 2437 type2aelembytes(op->type()), 2438 op->klass()->as_register(), 2439 *op->stub()->entry()); 2440 } 2441 __ bind(*op->stub()->continuation()); 2442 } 2443 2444 2445 void LIR_Assembler::type_profile_helper(Register mdo, int mdo_offset_bias, 2446 ciMethodData *md, ciProfileData *data, 2447 Register recv, Register tmp1, Label* update_done) { 2448 uint i; 2449 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2450 Label next_test; 2451 // See if the receiver is receiver[n]. 2452 Address receiver_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - 2453 mdo_offset_bias); 2454 __ ld_ptr(receiver_addr, tmp1); 2455 __ verify_oop(tmp1); 2456 __ cmp(recv, tmp1); 2457 __ brx(Assembler::notEqual, false, Assembler::pt, next_test); 2458 __ delayed()->nop(); 2459 Address data_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - 2460 mdo_offset_bias); 2461 __ ld_ptr(data_addr, tmp1); 2462 __ add(tmp1, DataLayout::counter_increment, tmp1); 2463 __ st_ptr(tmp1, data_addr); 2464 __ ba(false, *update_done); 2465 __ delayed()->nop(); 2466 __ bind(next_test); 2467 } 2468 2469 // Didn't find receiver; find next empty slot and fill it in 2470 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2471 Label next_test; 2472 Address recv_addr(mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_offset(i)) - 2473 mdo_offset_bias); 2474 load(recv_addr, tmp1, T_OBJECT); 2475 __ br_notnull(tmp1, false, Assembler::pt, next_test); 2476 __ delayed()->nop(); 2477 __ st_ptr(recv, recv_addr); 2478 __ set(DataLayout::counter_increment, tmp1); 2479 __ st_ptr(tmp1, mdo, md->byte_offset_of_slot(data, ReceiverTypeData::receiver_count_offset(i)) - 2480 mdo_offset_bias); 2481 __ ba(false, *update_done); 2482 __ delayed()->nop(); 2483 __ bind(next_test); 2484 } 2485 } 2486 2487 2488 void LIR_Assembler::setup_md_access(ciMethod* method, int bci, 2489 ciMethodData*& md, ciProfileData*& data, int& mdo_offset_bias) { 2490 md = method->method_data(); 2491 if (md == NULL) { 2492 bailout("out of memory building methodDataOop"); 2493 return; 2494 } 2495 data = md->bci_to_data(bci); 2496 assert(data != NULL, "need data for checkcast"); 2497 assert(data->is_ReceiverTypeData(), "need ReceiverTypeData for type check"); 2498 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, DataLayout::header_offset()) + data->size_in_bytes())) { 2499 // The offset is large so bias the mdo by the base of the slot so 2500 // that the ld can use simm13s to reference the slots of the data 2501 mdo_offset_bias = md->byte_offset_of_slot(data, DataLayout::header_offset()); 2502 } 2503 } 2504 2505 void LIR_Assembler::emit_typecheck_helper(LIR_OpTypeCheck *op, Label* success, Label* failure, Label* obj_is_null) { 2506 // we always need a stub for the failure case. 2507 CodeStub* stub = op->stub(); 2508 Register obj = op->object()->as_register(); 2509 Register k_RInfo = op->tmp1()->as_register(); 2510 Register klass_RInfo = op->tmp2()->as_register(); 2511 Register dst = op->result_opr()->as_register(); 2512 Register Rtmp1 = op->tmp3()->as_register(); 2513 ciKlass* k = op->klass(); 2514 2515 2516 if (obj == k_RInfo) { 2517 k_RInfo = klass_RInfo; 2518 klass_RInfo = obj; 2519 } 2520 2521 ciMethodData* md; 2522 ciProfileData* data; 2523 int mdo_offset_bias = 0; 2524 if (op->should_profile()) { 2525 ciMethod* method = op->profiled_method(); 2526 assert(method != NULL, "Should have method"); 2527 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2528 2529 Label not_null; 2530 __ br_notnull(obj, false, Assembler::pn, not_null); 2531 __ delayed()->nop(); 2532 Register mdo = k_RInfo; 2533 Register data_val = Rtmp1; 2534 jobject2reg(md->constant_encoding(), mdo); 2535 if (mdo_offset_bias > 0) { 2536 __ set(mdo_offset_bias, data_val); 2537 __ add(mdo, data_val, mdo); 2538 } 2539 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); 2540 __ ldub(flags_addr, data_val); 2541 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); 2542 __ stb(data_val, flags_addr); 2543 __ ba(false, *obj_is_null); 2544 __ delayed()->nop(); 2545 __ bind(not_null); 2546 } else { 2547 __ br_null(obj, false, Assembler::pn, *obj_is_null); 2548 __ delayed()->nop(); 2549 } 2550 2551 Label profile_cast_failure, profile_cast_success; 2552 Label *failure_target = op->should_profile() ? &profile_cast_failure : failure; 2553 Label *success_target = op->should_profile() ? &profile_cast_success : success; 2554 2555 // patching may screw with our temporaries on sparc, 2556 // so let's do it before loading the class 2557 if (k->is_loaded()) { 2558 jobject2reg(k->constant_encoding(), k_RInfo); 2559 } else { 2560 jobject2reg_with_patching(k_RInfo, op->info_for_patch()); 2561 } 2562 assert(obj != k_RInfo, "must be different"); 2563 2564 // get object class 2565 // not a safepoint as obj null check happens earlier 2566 load(obj, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); 2567 if (op->fast_check()) { 2568 assert_different_registers(klass_RInfo, k_RInfo); 2569 __ cmp(k_RInfo, klass_RInfo); 2570 __ brx(Assembler::notEqual, false, Assembler::pt, *failure_target); 2571 __ delayed()->nop(); 2572 } else { 2573 bool need_slow_path = true; 2574 if (k->is_loaded()) { 2575 if (k->super_check_offset() != sizeof(oopDesc) + Klass::secondary_super_cache_offset_in_bytes()) 2576 need_slow_path = false; 2577 // perform the fast part of the checking logic 2578 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, noreg, 2579 (need_slow_path ? success_target : NULL), 2580 failure_target, NULL, 2581 RegisterOrConstant(k->super_check_offset())); 2582 } else { 2583 // perform the fast part of the checking logic 2584 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, 2585 failure_target, NULL); 2586 } 2587 if (need_slow_path) { 2588 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 2589 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); 2590 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2591 __ delayed()->nop(); 2592 __ cmp(G3, 0); 2593 __ br(Assembler::equal, false, Assembler::pn, *failure_target); 2594 __ delayed()->nop(); 2595 // Fall through to success case 2596 } 2597 } 2598 2599 if (op->should_profile()) { 2600 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; 2601 assert_different_registers(obj, mdo, recv, tmp1); 2602 __ bind(profile_cast_success); 2603 jobject2reg(md->constant_encoding(), mdo); 2604 if (mdo_offset_bias > 0) { 2605 __ set(mdo_offset_bias, tmp1); 2606 __ add(mdo, tmp1, mdo); 2607 } 2608 load(Address(obj, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT); 2609 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, success); 2610 // Jump over the failure case 2611 __ ba(false, *success); 2612 __ delayed()->nop(); 2613 // Cast failure case 2614 __ bind(profile_cast_failure); 2615 jobject2reg(md->constant_encoding(), mdo); 2616 if (mdo_offset_bias > 0) { 2617 __ set(mdo_offset_bias, tmp1); 2618 __ add(mdo, tmp1, mdo); 2619 } 2620 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2621 __ ld_ptr(data_addr, tmp1); 2622 __ sub(tmp1, DataLayout::counter_increment, tmp1); 2623 __ st_ptr(tmp1, data_addr); 2624 __ ba(false, *failure); 2625 __ delayed()->nop(); 2626 } 2627 __ ba(false, *success); 2628 __ delayed()->nop(); 2629 } 2630 2631 void LIR_Assembler::emit_opTypeCheck(LIR_OpTypeCheck* op) { 2632 LIR_Code code = op->code(); 2633 if (code == lir_store_check) { 2634 Register value = op->object()->as_register(); 2635 Register array = op->array()->as_register(); 2636 Register k_RInfo = op->tmp1()->as_register(); 2637 Register klass_RInfo = op->tmp2()->as_register(); 2638 Register Rtmp1 = op->tmp3()->as_register(); 2639 2640 __ verify_oop(value); 2641 CodeStub* stub = op->stub(); 2642 // check if it needs to be profiled 2643 ciMethodData* md; 2644 ciProfileData* data; 2645 int mdo_offset_bias = 0; 2646 if (op->should_profile()) { 2647 ciMethod* method = op->profiled_method(); 2648 assert(method != NULL, "Should have method"); 2649 setup_md_access(method, op->profiled_bci(), md, data, mdo_offset_bias); 2650 } 2651 Label profile_cast_success, profile_cast_failure, done; 2652 Label *success_target = op->should_profile() ? &profile_cast_success : &done; 2653 Label *failure_target = op->should_profile() ? &profile_cast_failure : stub->entry(); 2654 2655 if (op->should_profile()) { 2656 Label not_null; 2657 __ br_notnull(value, false, Assembler::pn, not_null); 2658 __ delayed()->nop(); 2659 Register mdo = k_RInfo; 2660 Register data_val = Rtmp1; 2661 jobject2reg(md->constant_encoding(), mdo); 2662 if (mdo_offset_bias > 0) { 2663 __ set(mdo_offset_bias, data_val); 2664 __ add(mdo, data_val, mdo); 2665 } 2666 Address flags_addr(mdo, md->byte_offset_of_slot(data, DataLayout::flags_offset()) - mdo_offset_bias); 2667 __ ldub(flags_addr, data_val); 2668 __ or3(data_val, BitData::null_seen_byte_constant(), data_val); 2669 __ stb(data_val, flags_addr); 2670 __ ba(false, done); 2671 __ delayed()->nop(); 2672 __ bind(not_null); 2673 } else { 2674 __ br_null(value, false, Assembler::pn, done); 2675 __ delayed()->nop(); 2676 } 2677 load(array, oopDesc::klass_offset_in_bytes(), k_RInfo, T_OBJECT, op->info_for_exception()); 2678 load(value, oopDesc::klass_offset_in_bytes(), klass_RInfo, T_OBJECT, NULL); 2679 2680 // get instance klass 2681 load(k_RInfo, objArrayKlass::element_klass_offset_in_bytes() + sizeof(oopDesc), k_RInfo, T_OBJECT, NULL); 2682 // perform the fast part of the checking logic 2683 __ check_klass_subtype_fast_path(klass_RInfo, k_RInfo, Rtmp1, O7, success_target, failure_target, NULL); 2684 2685 // call out-of-line instance of __ check_klass_subtype_slow_path(...): 2686 assert(klass_RInfo == G3 && k_RInfo == G1, "incorrect call setup"); 2687 __ call(Runtime1::entry_for(Runtime1::slow_subtype_check_id), relocInfo::runtime_call_type); 2688 __ delayed()->nop(); 2689 __ cmp(G3, 0); 2690 __ br(Assembler::equal, false, Assembler::pn, *failure_target); 2691 __ delayed()->nop(); 2692 // fall through to the success case 2693 2694 if (op->should_profile()) { 2695 Register mdo = klass_RInfo, recv = k_RInfo, tmp1 = Rtmp1; 2696 assert_different_registers(value, mdo, recv, tmp1); 2697 __ bind(profile_cast_success); 2698 jobject2reg(md->constant_encoding(), mdo); 2699 if (mdo_offset_bias > 0) { 2700 __ set(mdo_offset_bias, tmp1); 2701 __ add(mdo, tmp1, mdo); 2702 } 2703 load(Address(value, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT); 2704 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &done); 2705 __ ba(false, done); 2706 __ delayed()->nop(); 2707 // Cast failure case 2708 __ bind(profile_cast_failure); 2709 jobject2reg(md->constant_encoding(), mdo); 2710 if (mdo_offset_bias > 0) { 2711 __ set(mdo_offset_bias, tmp1); 2712 __ add(mdo, tmp1, mdo); 2713 } 2714 Address data_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2715 __ ld_ptr(data_addr, tmp1); 2716 __ sub(tmp1, DataLayout::counter_increment, tmp1); 2717 __ st_ptr(tmp1, data_addr); 2718 __ ba(false, *stub->entry()); 2719 __ delayed()->nop(); 2720 } 2721 __ bind(done); 2722 } else if (code == lir_checkcast) { 2723 Register obj = op->object()->as_register(); 2724 Register dst = op->result_opr()->as_register(); 2725 Label success; 2726 emit_typecheck_helper(op, &success, op->stub()->entry(), &success); 2727 __ bind(success); 2728 __ mov(obj, dst); 2729 } else if (code == lir_instanceof) { 2730 Register obj = op->object()->as_register(); 2731 Register dst = op->result_opr()->as_register(); 2732 Label success, failure, done; 2733 emit_typecheck_helper(op, &success, &failure, &failure); 2734 __ bind(failure); 2735 __ set(0, dst); 2736 __ ba(false, done); 2737 __ delayed()->nop(); 2738 __ bind(success); 2739 __ set(1, dst); 2740 __ bind(done); 2741 } else { 2742 ShouldNotReachHere(); 2743 } 2744 2745 } 2746 2747 2748 void LIR_Assembler::emit_compare_and_swap(LIR_OpCompareAndSwap* op) { 2749 if (op->code() == lir_cas_long) { 2750 assert(VM_Version::supports_cx8(), "wrong machine"); 2751 Register addr = op->addr()->as_pointer_register(); 2752 Register cmp_value_lo = op->cmp_value()->as_register_lo(); 2753 Register cmp_value_hi = op->cmp_value()->as_register_hi(); 2754 Register new_value_lo = op->new_value()->as_register_lo(); 2755 Register new_value_hi = op->new_value()->as_register_hi(); 2756 Register t1 = op->tmp1()->as_register(); 2757 Register t2 = op->tmp2()->as_register(); 2758 #ifdef _LP64 2759 __ mov(cmp_value_lo, t1); 2760 __ mov(new_value_lo, t2); 2761 #else 2762 // move high and low halves of long values into single registers 2763 __ sllx(cmp_value_hi, 32, t1); // shift high half into temp reg 2764 __ srl(cmp_value_lo, 0, cmp_value_lo); // clear upper 32 bits of low half 2765 __ or3(t1, cmp_value_lo, t1); // t1 holds 64-bit compare value 2766 __ sllx(new_value_hi, 32, t2); 2767 __ srl(new_value_lo, 0, new_value_lo); 2768 __ or3(t2, new_value_lo, t2); // t2 holds 64-bit value to swap 2769 #endif 2770 // perform the compare and swap operation 2771 __ casx(addr, t1, t2); 2772 // generate condition code - if the swap succeeded, t2 ("new value" reg) was 2773 // overwritten with the original value in "addr" and will be equal to t1. 2774 __ cmp(t1, t2); 2775 2776 } else if (op->code() == lir_cas_int || op->code() == lir_cas_obj) { 2777 Register addr = op->addr()->as_pointer_register(); 2778 Register cmp_value = op->cmp_value()->as_register(); 2779 Register new_value = op->new_value()->as_register(); 2780 Register t1 = op->tmp1()->as_register(); 2781 Register t2 = op->tmp2()->as_register(); 2782 __ mov(cmp_value, t1); 2783 __ mov(new_value, t2); 2784 #ifdef _LP64 2785 if (op->code() == lir_cas_obj) { 2786 __ casx(addr, t1, t2); 2787 } else 2788 #endif 2789 { 2790 __ cas(addr, t1, t2); 2791 } 2792 __ cmp(t1, t2); 2793 } else { 2794 Unimplemented(); 2795 } 2796 } 2797 2798 void LIR_Assembler::set_24bit_FPU() { 2799 Unimplemented(); 2800 } 2801 2802 2803 void LIR_Assembler::reset_FPU() { 2804 Unimplemented(); 2805 } 2806 2807 2808 void LIR_Assembler::breakpoint() { 2809 __ breakpoint_trap(); 2810 } 2811 2812 2813 void LIR_Assembler::push(LIR_Opr opr) { 2814 Unimplemented(); 2815 } 2816 2817 2818 void LIR_Assembler::pop(LIR_Opr opr) { 2819 Unimplemented(); 2820 } 2821 2822 2823 void LIR_Assembler::monitor_address(int monitor_no, LIR_Opr dst_opr) { 2824 Address mon_addr = frame_map()->address_for_monitor_lock(monitor_no); 2825 Register dst = dst_opr->as_register(); 2826 Register reg = mon_addr.base(); 2827 int offset = mon_addr.disp(); 2828 // compute pointer to BasicLock 2829 if (mon_addr.is_simm13()) { 2830 __ add(reg, offset, dst); 2831 } else { 2832 __ set(offset, dst); 2833 __ add(dst, reg, dst); 2834 } 2835 } 2836 2837 2838 void LIR_Assembler::emit_lock(LIR_OpLock* op) { 2839 Register obj = op->obj_opr()->as_register(); 2840 Register hdr = op->hdr_opr()->as_register(); 2841 Register lock = op->lock_opr()->as_register(); 2842 2843 // obj may not be an oop 2844 if (op->code() == lir_lock) { 2845 MonitorEnterStub* stub = (MonitorEnterStub*)op->stub(); 2846 if (UseFastLocking) { 2847 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2848 // add debug info for NullPointerException only if one is possible 2849 if (op->info() != NULL) { 2850 add_debug_info_for_null_check_here(op->info()); 2851 } 2852 __ lock_object(hdr, obj, lock, op->scratch_opr()->as_register(), *op->stub()->entry()); 2853 } else { 2854 // always do slow locking 2855 // note: the slow locking code could be inlined here, however if we use 2856 // slow locking, speed doesn't matter anyway and this solution is 2857 // simpler and requires less duplicated code - additionally, the 2858 // slow locking code is the same in either case which simplifies 2859 // debugging 2860 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2861 __ delayed()->nop(); 2862 } 2863 } else { 2864 assert (op->code() == lir_unlock, "Invalid code, expected lir_unlock"); 2865 if (UseFastLocking) { 2866 assert(BasicLock::displaced_header_offset_in_bytes() == 0, "lock_reg must point to the displaced header"); 2867 __ unlock_object(hdr, obj, lock, *op->stub()->entry()); 2868 } else { 2869 // always do slow unlocking 2870 // note: the slow unlocking code could be inlined here, however if we use 2871 // slow unlocking, speed doesn't matter anyway and this solution is 2872 // simpler and requires less duplicated code - additionally, the 2873 // slow unlocking code is the same in either case which simplifies 2874 // debugging 2875 __ br(Assembler::always, false, Assembler::pt, *op->stub()->entry()); 2876 __ delayed()->nop(); 2877 } 2878 } 2879 __ bind(*op->stub()->continuation()); 2880 } 2881 2882 2883 void LIR_Assembler::emit_profile_call(LIR_OpProfileCall* op) { 2884 ciMethod* method = op->profiled_method(); 2885 int bci = op->profiled_bci(); 2886 2887 // Update counter for all call types 2888 ciMethodData* md = method->method_data(); 2889 if (md == NULL) { 2890 bailout("out of memory building methodDataOop"); 2891 return; 2892 } 2893 ciProfileData* data = md->bci_to_data(bci); 2894 assert(data->is_CounterData(), "need CounterData for calls"); 2895 assert(op->mdo()->is_single_cpu(), "mdo must be allocated"); 2896 Register mdo = op->mdo()->as_register(); 2897 #ifdef _LP64 2898 assert(op->tmp1()->is_double_cpu(), "tmp1 must be allocated"); 2899 Register tmp1 = op->tmp1()->as_register_lo(); 2900 #else 2901 assert(op->tmp1()->is_single_cpu(), "tmp1 must be allocated"); 2902 Register tmp1 = op->tmp1()->as_register(); 2903 #endif 2904 jobject2reg(md->constant_encoding(), mdo); 2905 int mdo_offset_bias = 0; 2906 if (!Assembler::is_simm13(md->byte_offset_of_slot(data, CounterData::count_offset()) + 2907 data->size_in_bytes())) { 2908 // The offset is large so bias the mdo by the base of the slot so 2909 // that the ld can use simm13s to reference the slots of the data 2910 mdo_offset_bias = md->byte_offset_of_slot(data, CounterData::count_offset()); 2911 __ set(mdo_offset_bias, O7); 2912 __ add(mdo, O7, mdo); 2913 } 2914 2915 Address counter_addr(mdo, md->byte_offset_of_slot(data, CounterData::count_offset()) - mdo_offset_bias); 2916 Bytecodes::Code bc = method->java_code_at_bci(bci); 2917 // Perform additional virtual call profiling for invokevirtual and 2918 // invokeinterface bytecodes 2919 if ((bc == Bytecodes::_invokevirtual || bc == Bytecodes::_invokeinterface) && 2920 C1ProfileVirtualCalls) { 2921 assert(op->recv()->is_single_cpu(), "recv must be allocated"); 2922 Register recv = op->recv()->as_register(); 2923 assert_different_registers(mdo, tmp1, recv); 2924 assert(data->is_VirtualCallData(), "need VirtualCallData for virtual calls"); 2925 ciKlass* known_klass = op->known_holder(); 2926 if (C1OptimizeVirtualCallProfiling && known_klass != NULL) { 2927 // We know the type that will be seen at this call site; we can 2928 // statically update the methodDataOop rather than needing to do 2929 // dynamic tests on the receiver type 2930 2931 // NOTE: we should probably put a lock around this search to 2932 // avoid collisions by concurrent compilations 2933 ciVirtualCallData* vc_data = (ciVirtualCallData*) data; 2934 uint i; 2935 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2936 ciKlass* receiver = vc_data->receiver(i); 2937 if (known_klass->equals(receiver)) { 2938 Address data_addr(mdo, md->byte_offset_of_slot(data, 2939 VirtualCallData::receiver_count_offset(i)) - 2940 mdo_offset_bias); 2941 __ ld_ptr(data_addr, tmp1); 2942 __ add(tmp1, DataLayout::counter_increment, tmp1); 2943 __ st_ptr(tmp1, data_addr); 2944 return; 2945 } 2946 } 2947 2948 // Receiver type not found in profile data; select an empty slot 2949 2950 // Note that this is less efficient than it should be because it 2951 // always does a write to the receiver part of the 2952 // VirtualCallData rather than just the first time 2953 for (i = 0; i < VirtualCallData::row_limit(); i++) { 2954 ciKlass* receiver = vc_data->receiver(i); 2955 if (receiver == NULL) { 2956 Address recv_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_offset(i)) - 2957 mdo_offset_bias); 2958 jobject2reg(known_klass->constant_encoding(), tmp1); 2959 __ st_ptr(tmp1, recv_addr); 2960 Address data_addr(mdo, md->byte_offset_of_slot(data, VirtualCallData::receiver_count_offset(i)) - 2961 mdo_offset_bias); 2962 __ ld_ptr(data_addr, tmp1); 2963 __ add(tmp1, DataLayout::counter_increment, tmp1); 2964 __ st_ptr(tmp1, data_addr); 2965 return; 2966 } 2967 } 2968 } else { 2969 load(Address(recv, oopDesc::klass_offset_in_bytes()), recv, T_OBJECT); 2970 Label update_done; 2971 type_profile_helper(mdo, mdo_offset_bias, md, data, recv, tmp1, &update_done); 2972 // Receiver did not match any saved receiver and there is no empty row for it. 2973 // Increment total counter to indicate polymorphic case. 2974 __ ld_ptr(counter_addr, tmp1); 2975 __ add(tmp1, DataLayout::counter_increment, tmp1); 2976 __ st_ptr(tmp1, counter_addr); 2977 2978 __ bind(update_done); 2979 } 2980 } else { 2981 // Static call 2982 __ ld_ptr(counter_addr, tmp1); 2983 __ add(tmp1, DataLayout::counter_increment, tmp1); 2984 __ st_ptr(tmp1, counter_addr); 2985 } 2986 } 2987 2988 void LIR_Assembler::align_backward_branch_target() { 2989 __ align(OptoLoopAlignment); 2990 } 2991 2992 2993 void LIR_Assembler::emit_delay(LIR_OpDelay* op) { 2994 // make sure we are expecting a delay 2995 // this has the side effect of clearing the delay state 2996 // so we can use _masm instead of _masm->delayed() to do the 2997 // code generation. 2998 __ delayed(); 2999 3000 // make sure we only emit one instruction 3001 int offset = code_offset(); 3002 op->delay_op()->emit_code(this); 3003 #ifdef ASSERT 3004 if (code_offset() - offset != NativeInstruction::nop_instruction_size) { 3005 op->delay_op()->print(); 3006 } 3007 assert(code_offset() - offset == NativeInstruction::nop_instruction_size, 3008 "only one instruction can go in a delay slot"); 3009 #endif 3010 3011 // we may also be emitting the call info for the instruction 3012 // which we are the delay slot of. 3013 CodeEmitInfo* call_info = op->call_info(); 3014 if (call_info) { 3015 add_call_info(code_offset(), call_info); 3016 } 3017 3018 if (VerifyStackAtCalls) { 3019 _masm->sub(FP, SP, O7); 3020 _masm->cmp(O7, initial_frame_size_in_bytes()); 3021 _masm->trap(Assembler::notEqual, Assembler::ptr_cc, G0, ST_RESERVED_FOR_USER_0+2 ); 3022 } 3023 } 3024 3025 3026 void LIR_Assembler::negate(LIR_Opr left, LIR_Opr dest) { 3027 assert(left->is_register(), "can only handle registers"); 3028 3029 if (left->is_single_cpu()) { 3030 __ neg(left->as_register(), dest->as_register()); 3031 } else if (left->is_single_fpu()) { 3032 __ fneg(FloatRegisterImpl::S, left->as_float_reg(), dest->as_float_reg()); 3033 } else if (left->is_double_fpu()) { 3034 __ fneg(FloatRegisterImpl::D, left->as_double_reg(), dest->as_double_reg()); 3035 } else { 3036 assert (left->is_double_cpu(), "Must be a long"); 3037 Register Rlow = left->as_register_lo(); 3038 Register Rhi = left->as_register_hi(); 3039 #ifdef _LP64 3040 __ sub(G0, Rlow, dest->as_register_lo()); 3041 #else 3042 __ subcc(G0, Rlow, dest->as_register_lo()); 3043 __ subc (G0, Rhi, dest->as_register_hi()); 3044 #endif 3045 } 3046 } 3047 3048 3049 void LIR_Assembler::fxch(int i) { 3050 Unimplemented(); 3051 } 3052 3053 void LIR_Assembler::fld(int i) { 3054 Unimplemented(); 3055 } 3056 3057 void LIR_Assembler::ffree(int i) { 3058 Unimplemented(); 3059 } 3060 3061 void LIR_Assembler::rt_call(LIR_Opr result, address dest, 3062 const LIR_OprList* args, LIR_Opr tmp, CodeEmitInfo* info) { 3063 3064 // if tmp is invalid, then the function being called doesn't destroy the thread 3065 if (tmp->is_valid()) { 3066 __ save_thread(tmp->as_register()); 3067 } 3068 __ call(dest, relocInfo::runtime_call_type); 3069 __ delayed()->nop(); 3070 if (info != NULL) { 3071 add_call_info_here(info); 3072 } 3073 if (tmp->is_valid()) { 3074 __ restore_thread(tmp->as_register()); 3075 } 3076 3077 #ifdef ASSERT 3078 __ verify_thread(); 3079 #endif // ASSERT 3080 } 3081 3082 3083 void LIR_Assembler::volatile_move_op(LIR_Opr src, LIR_Opr dest, BasicType type, CodeEmitInfo* info) { 3084 #ifdef _LP64 3085 ShouldNotReachHere(); 3086 #endif 3087 3088 NEEDS_CLEANUP; 3089 if (type == T_LONG) { 3090 LIR_Address* mem_addr = dest->is_address() ? dest->as_address_ptr() : src->as_address_ptr(); 3091 3092 // (extended to allow indexed as well as constant displaced for JSR-166) 3093 Register idx = noreg; // contains either constant offset or index 3094 3095 int disp = mem_addr->disp(); 3096 if (mem_addr->index() == LIR_OprFact::illegalOpr) { 3097 if (!Assembler::is_simm13(disp)) { 3098 idx = O7; 3099 __ set(disp, idx); 3100 } 3101 } else { 3102 assert(disp == 0, "not both indexed and disp"); 3103 idx = mem_addr->index()->as_register(); 3104 } 3105 3106 int null_check_offset = -1; 3107 3108 Register base = mem_addr->base()->as_register(); 3109 if (src->is_register() && dest->is_address()) { 3110 // G4 is high half, G5 is low half 3111 if (VM_Version::v9_instructions_work()) { 3112 // clear the top bits of G5, and scale up G4 3113 __ srl (src->as_register_lo(), 0, G5); 3114 __ sllx(src->as_register_hi(), 32, G4); 3115 // combine the two halves into the 64 bits of G4 3116 __ or3(G4, G5, G4); 3117 null_check_offset = __ offset(); 3118 if (idx == noreg) { 3119 __ stx(G4, base, disp); 3120 } else { 3121 __ stx(G4, base, idx); 3122 } 3123 } else { 3124 __ mov (src->as_register_hi(), G4); 3125 __ mov (src->as_register_lo(), G5); 3126 null_check_offset = __ offset(); 3127 if (idx == noreg) { 3128 __ std(G4, base, disp); 3129 } else { 3130 __ std(G4, base, idx); 3131 } 3132 } 3133 } else if (src->is_address() && dest->is_register()) { 3134 null_check_offset = __ offset(); 3135 if (VM_Version::v9_instructions_work()) { 3136 if (idx == noreg) { 3137 __ ldx(base, disp, G5); 3138 } else { 3139 __ ldx(base, idx, G5); 3140 } 3141 __ srax(G5, 32, dest->as_register_hi()); // fetch the high half into hi 3142 __ mov (G5, dest->as_register_lo()); // copy low half into lo 3143 } else { 3144 if (idx == noreg) { 3145 __ ldd(base, disp, G4); 3146 } else { 3147 __ ldd(base, idx, G4); 3148 } 3149 // G4 is high half, G5 is low half 3150 __ mov (G4, dest->as_register_hi()); 3151 __ mov (G5, dest->as_register_lo()); 3152 } 3153 } else { 3154 Unimplemented(); 3155 } 3156 if (info != NULL) { 3157 add_debug_info_for_null_check(null_check_offset, info); 3158 } 3159 3160 } else { 3161 // use normal move for all other volatiles since they don't need 3162 // special handling to remain atomic. 3163 move_op(src, dest, type, lir_patch_none, info, false, false); 3164 } 3165 } 3166 3167 void LIR_Assembler::membar() { 3168 // only StoreLoad membars are ever explicitly needed on sparcs in TSO mode 3169 __ membar( Assembler::Membar_mask_bits(Assembler::StoreLoad) ); 3170 } 3171 3172 void LIR_Assembler::membar_acquire() { 3173 // no-op on TSO 3174 } 3175 3176 void LIR_Assembler::membar_release() { 3177 // no-op on TSO 3178 } 3179 3180 // Pack two sequential registers containing 32 bit values 3181 // into a single 64 bit register. 3182 // src and src->successor() are packed into dst 3183 // src and dst may be the same register. 3184 // Note: src is destroyed 3185 void LIR_Assembler::pack64(LIR_Opr src, LIR_Opr dst) { 3186 Register rs = src->as_register(); 3187 Register rd = dst->as_register_lo(); 3188 __ sllx(rs, 32, rs); 3189 __ srl(rs->successor(), 0, rs->successor()); 3190 __ or3(rs, rs->successor(), rd); 3191 } 3192 3193 // Unpack a 64 bit value in a register into 3194 // two sequential registers. 3195 // src is unpacked into dst and dst->successor() 3196 void LIR_Assembler::unpack64(LIR_Opr src, LIR_Opr dst) { 3197 Register rs = src->as_register_lo(); 3198 Register rd = dst->as_register_hi(); 3199 assert_different_registers(rs, rd, rd->successor()); 3200 __ srlx(rs, 32, rd); 3201 __ srl (rs, 0, rd->successor()); 3202 } 3203 3204 3205 void LIR_Assembler::leal(LIR_Opr addr_opr, LIR_Opr dest) { 3206 LIR_Address* addr = addr_opr->as_address_ptr(); 3207 assert(addr->index()->is_illegal() && addr->scale() == LIR_Address::times_1 && Assembler::is_simm13(addr->disp()), "can't handle complex addresses yet"); 3208 3209 __ add(addr->base()->as_pointer_register(), addr->disp(), dest->as_pointer_register()); 3210 } 3211 3212 3213 void LIR_Assembler::get_thread(LIR_Opr result_reg) { 3214 assert(result_reg->is_register(), "check"); 3215 __ mov(G2_thread, result_reg->as_register()); 3216 } 3217 3218 3219 void LIR_Assembler::peephole(LIR_List* lir) { 3220 LIR_OpList* inst = lir->instructions_list(); 3221 for (int i = 0; i < inst->length(); i++) { 3222 LIR_Op* op = inst->at(i); 3223 switch (op->code()) { 3224 case lir_cond_float_branch: 3225 case lir_branch: { 3226 LIR_OpBranch* branch = op->as_OpBranch(); 3227 assert(branch->info() == NULL, "shouldn't be state on branches anymore"); 3228 LIR_Op* delay_op = NULL; 3229 // we'd like to be able to pull following instructions into 3230 // this slot but we don't know enough to do it safely yet so 3231 // only optimize block to block control flow. 3232 if (LIRFillDelaySlots && branch->block()) { 3233 LIR_Op* prev = inst->at(i - 1); 3234 if (prev && LIR_Assembler::is_single_instruction(prev) && prev->info() == NULL) { 3235 // swap previous instruction into delay slot 3236 inst->at_put(i - 1, op); 3237 inst->at_put(i, new LIR_OpDelay(prev, op->info())); 3238 #ifndef PRODUCT 3239 if (LIRTracePeephole) { 3240 tty->print_cr("delayed"); 3241 inst->at(i - 1)->print(); 3242 inst->at(i)->print(); 3243 tty->cr(); 3244 } 3245 #endif 3246 continue; 3247 } 3248 } 3249 3250 if (!delay_op) { 3251 delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), NULL); 3252 } 3253 inst->insert_before(i + 1, delay_op); 3254 break; 3255 } 3256 case lir_static_call: 3257 case lir_virtual_call: 3258 case lir_icvirtual_call: 3259 case lir_optvirtual_call: 3260 case lir_dynamic_call: { 3261 LIR_Op* prev = inst->at(i - 1); 3262 if (LIRFillDelaySlots && prev && prev->code() == lir_move && prev->info() == NULL && 3263 (op->code() != lir_virtual_call || 3264 !prev->result_opr()->is_single_cpu() || 3265 prev->result_opr()->as_register() != O0) && 3266 LIR_Assembler::is_single_instruction(prev)) { 3267 // Only moves without info can be put into the delay slot. 3268 // Also don't allow the setup of the receiver in the delay 3269 // slot for vtable calls. 3270 inst->at_put(i - 1, op); 3271 inst->at_put(i, new LIR_OpDelay(prev, op->info())); 3272 #ifndef PRODUCT 3273 if (LIRTracePeephole) { 3274 tty->print_cr("delayed"); 3275 inst->at(i - 1)->print(); 3276 inst->at(i)->print(); 3277 tty->cr(); 3278 } 3279 #endif 3280 } else { 3281 LIR_Op* delay_op = new LIR_OpDelay(new LIR_Op0(lir_nop), op->as_OpJavaCall()->info()); 3282 inst->insert_before(i + 1, delay_op); 3283 i++; 3284 } 3285 3286 #if defined(TIERED) && !defined(_LP64) 3287 // fixup the return value from G1 to O0/O1 for long returns. 3288 // It's done here instead of in LIRGenerator because there's 3289 // such a mismatch between the single reg and double reg 3290 // calling convention. 3291 LIR_OpJavaCall* callop = op->as_OpJavaCall(); 3292 if (callop->result_opr() == FrameMap::out_long_opr) { 3293 LIR_OpJavaCall* call; 3294 LIR_OprList* arguments = new LIR_OprList(callop->arguments()->length()); 3295 for (int a = 0; a < arguments->length(); a++) { 3296 arguments[a] = callop->arguments()[a]; 3297 } 3298 if (op->code() == lir_virtual_call) { 3299 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, 3300 callop->vtable_offset(), arguments, callop->info()); 3301 } else { 3302 call = new LIR_OpJavaCall(op->code(), callop->method(), callop->receiver(), FrameMap::g1_long_single_opr, 3303 callop->addr(), arguments, callop->info()); 3304 } 3305 inst->at_put(i - 1, call); 3306 inst->insert_before(i + 1, new LIR_Op1(lir_unpack64, FrameMap::g1_long_single_opr, callop->result_opr(), 3307 T_LONG, lir_patch_none, NULL)); 3308 } 3309 #endif 3310 break; 3311 } 3312 } 3313 } 3314 } 3315 3316 3317 3318 3319 #undef __