1 /*
2 * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #include "incls/_precompiled.incl"
26 #include "incls/_sharedRuntime_sparc.cpp.incl"
27
28 #define __ masm->
29
30 #ifdef COMPILER2
31 UncommonTrapBlob* SharedRuntime::_uncommon_trap_blob;
32 #endif // COMPILER2
33
34 DeoptimizationBlob* SharedRuntime::_deopt_blob;
35 SafepointBlob* SharedRuntime::_polling_page_safepoint_handler_blob;
36 SafepointBlob* SharedRuntime::_polling_page_return_handler_blob;
37 RuntimeStub* SharedRuntime::_wrong_method_blob;
38 RuntimeStub* SharedRuntime::_ic_miss_blob;
39 RuntimeStub* SharedRuntime::_resolve_opt_virtual_call_blob;
40 RuntimeStub* SharedRuntime::_resolve_virtual_call_blob;
41 RuntimeStub* SharedRuntime::_resolve_static_call_blob;
42
43 class RegisterSaver {
44
45 // Used for saving volatile registers. This is Gregs, Fregs, I/L/O.
46 // The Oregs are problematic. In the 32bit build the compiler can
47 // have O registers live with 64 bit quantities. A window save will
48 // cut the heads off of the registers. We have to do a very extensive
49 // stack dance to save and restore these properly.
50
51 // Note that the Oregs problem only exists if we block at either a polling
52 // page exception a compiled code safepoint that was not originally a call
53 // or deoptimize following one of these kinds of safepoints.
54
55 // Lots of registers to save. For all builds, a window save will preserve
56 // the %i and %l registers. For the 32-bit longs-in-two entries and 64-bit
57 // builds a window-save will preserve the %o registers. In the LION build
58 // we need to save the 64-bit %o registers which requires we save them
59 // before the window-save (as then they become %i registers and get their
60 // heads chopped off on interrupt). We have to save some %g registers here
61 // as well.
62 enum {
63 // This frame's save area. Includes extra space for the native call:
64 // vararg's layout space and the like. Briefly holds the caller's
65 // register save area.
66 call_args_area = frame::register_save_words_sp_offset +
67 frame::memory_parameter_word_sp_offset*wordSize,
68 // Make sure save locations are always 8 byte aligned.
69 // can't use round_to because it doesn't produce compile time constant
70 start_of_extra_save_area = ((call_args_area + 7) & ~7),
71 g1_offset = start_of_extra_save_area, // g-regs needing saving
72 g3_offset = g1_offset+8,
73 g4_offset = g3_offset+8,
74 g5_offset = g4_offset+8,
75 o0_offset = g5_offset+8,
76 o1_offset = o0_offset+8,
77 o2_offset = o1_offset+8,
78 o3_offset = o2_offset+8,
79 o4_offset = o3_offset+8,
80 o5_offset = o4_offset+8,
81 start_of_flags_save_area = o5_offset+8,
82 ccr_offset = start_of_flags_save_area,
83 fsr_offset = ccr_offset + 8,
84 d00_offset = fsr_offset+8, // Start of float save area
85 register_save_size = d00_offset+8*32
86 };
87
88
89 public:
90
91 static int Oexception_offset() { return o0_offset; };
92 static int G3_offset() { return g3_offset; };
93 static int G5_offset() { return g5_offset; };
94 static OopMap* save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words);
95 static void restore_live_registers(MacroAssembler* masm);
96
97 // During deoptimization only the result register need to be restored
98 // all the other values have already been extracted.
99
100 static void restore_result_registers(MacroAssembler* masm);
101 };
102
103 OopMap* RegisterSaver::save_live_registers(MacroAssembler* masm, int additional_frame_words, int* total_frame_words) {
104 // Record volatile registers as callee-save values in an OopMap so their save locations will be
105 // propagated to the caller frame's RegisterMap during StackFrameStream construction (needed for
106 // deoptimization; see compiledVFrame::create_stack_value). The caller's I, L and O registers
107 // are saved in register windows - I's and L's in the caller's frame and O's in the stub frame
108 // (as the stub's I's) when the runtime routine called by the stub creates its frame.
109 int i;
110 // Always make the frame size 16 byte aligned.
111 int frame_size = round_to(additional_frame_words + register_save_size, 16);
112 // OopMap frame size is in c2 stack slots (sizeof(jint)) not bytes or words
113 int frame_size_in_slots = frame_size / sizeof(jint);
114 // CodeBlob frame size is in words.
115 *total_frame_words = frame_size / wordSize;
116 // OopMap* map = new OopMap(*total_frame_words, 0);
117 OopMap* map = new OopMap(frame_size_in_slots, 0);
118
119 #if !defined(_LP64)
120
121 // Save 64-bit O registers; they will get their heads chopped off on a 'save'.
122 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
123 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
124 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
125 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
126 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
127 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
128 #endif /* _LP64 */
129
130 __ save(SP, -frame_size, SP);
131
132 #ifndef _LP64
133 // Reload the 64 bit Oregs. Although they are now Iregs we load them
134 // to Oregs here to avoid interrupts cutting off their heads
135
136 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
137 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
138 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
139 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
140 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
141 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
142
143 __ stx(O0, SP, o0_offset+STACK_BIAS);
144 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset + 4)>>2), O0->as_VMReg());
145
146 __ stx(O1, SP, o1_offset+STACK_BIAS);
147
148 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset + 4)>>2), O1->as_VMReg());
149
150 __ stx(O2, SP, o2_offset+STACK_BIAS);
151 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset + 4)>>2), O2->as_VMReg());
152
153 __ stx(O3, SP, o3_offset+STACK_BIAS);
154 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset + 4)>>2), O3->as_VMReg());
155
156 __ stx(O4, SP, o4_offset+STACK_BIAS);
157 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset + 4)>>2), O4->as_VMReg());
158
159 __ stx(O5, SP, o5_offset+STACK_BIAS);
160 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset + 4)>>2), O5->as_VMReg());
161 #endif /* _LP64 */
162
163
164 #ifdef _LP64
165 int debug_offset = 0;
166 #else
167 int debug_offset = 4;
168 #endif
169 // Save the G's
170 __ stx(G1, SP, g1_offset+STACK_BIAS);
171 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset + debug_offset)>>2), G1->as_VMReg());
172
173 __ stx(G3, SP, g3_offset+STACK_BIAS);
174 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset + debug_offset)>>2), G3->as_VMReg());
175
176 __ stx(G4, SP, g4_offset+STACK_BIAS);
177 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset + debug_offset)>>2), G4->as_VMReg());
178
179 __ stx(G5, SP, g5_offset+STACK_BIAS);
180 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset + debug_offset)>>2), G5->as_VMReg());
181
182 // This is really a waste but we'll keep things as they were for now
183 if (true) {
184 #ifndef _LP64
185 map->set_callee_saved(VMRegImpl::stack2reg((o0_offset)>>2), O0->as_VMReg()->next());
186 map->set_callee_saved(VMRegImpl::stack2reg((o1_offset)>>2), O1->as_VMReg()->next());
187 map->set_callee_saved(VMRegImpl::stack2reg((o2_offset)>>2), O2->as_VMReg()->next());
188 map->set_callee_saved(VMRegImpl::stack2reg((o3_offset)>>2), O3->as_VMReg()->next());
189 map->set_callee_saved(VMRegImpl::stack2reg((o4_offset)>>2), O4->as_VMReg()->next());
190 map->set_callee_saved(VMRegImpl::stack2reg((o5_offset)>>2), O5->as_VMReg()->next());
191 map->set_callee_saved(VMRegImpl::stack2reg((g1_offset)>>2), G1->as_VMReg()->next());
192 map->set_callee_saved(VMRegImpl::stack2reg((g3_offset)>>2), G3->as_VMReg()->next());
193 map->set_callee_saved(VMRegImpl::stack2reg((g4_offset)>>2), G4->as_VMReg()->next());
194 map->set_callee_saved(VMRegImpl::stack2reg((g5_offset)>>2), G5->as_VMReg()->next());
195 #endif /* _LP64 */
196 }
197
198
199 // Save the flags
200 __ rdccr( G5 );
201 __ stx(G5, SP, ccr_offset+STACK_BIAS);
202 __ stxfsr(SP, fsr_offset+STACK_BIAS);
203
204 // Save all the FP registers: 32 doubles (32 floats correspond to the 2 halves of the first 16 doubles)
205 int offset = d00_offset;
206 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
207 FloatRegister f = as_FloatRegister(i);
208 __ stf(FloatRegisterImpl::D, f, SP, offset+STACK_BIAS);
209 // Record as callee saved both halves of double registers (2 float registers).
210 map->set_callee_saved(VMRegImpl::stack2reg(offset>>2), f->as_VMReg());
211 map->set_callee_saved(VMRegImpl::stack2reg((offset + sizeof(float))>>2), f->as_VMReg()->next());
212 offset += sizeof(double);
213 }
214
215 // And we're done.
216
217 return map;
218 }
219
220
221 // Pop the current frame and restore all the registers that we
222 // saved.
223 void RegisterSaver::restore_live_registers(MacroAssembler* masm) {
224
225 // Restore all the FP registers
226 for( int i=0; i<FloatRegisterImpl::number_of_registers; i+=2 ) {
227 __ ldf(FloatRegisterImpl::D, SP, d00_offset+i*sizeof(float)+STACK_BIAS, as_FloatRegister(i));
228 }
229
230 __ ldx(SP, ccr_offset+STACK_BIAS, G1);
231 __ wrccr (G1) ;
232
233 // Restore the G's
234 // Note that G2 (AKA GThread) must be saved and restored separately.
235 // TODO-FIXME: save and restore some of the other ASRs, viz., %asi and %gsr.
236
237 __ ldx(SP, g1_offset+STACK_BIAS, G1);
238 __ ldx(SP, g3_offset+STACK_BIAS, G3);
239 __ ldx(SP, g4_offset+STACK_BIAS, G4);
240 __ ldx(SP, g5_offset+STACK_BIAS, G5);
241
242
243 #if !defined(_LP64)
244 // Restore the 64-bit O's.
245 __ ldx(SP, o0_offset+STACK_BIAS, O0);
246 __ ldx(SP, o1_offset+STACK_BIAS, O1);
247 __ ldx(SP, o2_offset+STACK_BIAS, O2);
248 __ ldx(SP, o3_offset+STACK_BIAS, O3);
249 __ ldx(SP, o4_offset+STACK_BIAS, O4);
250 __ ldx(SP, o5_offset+STACK_BIAS, O5);
251
252 // And temporarily place them in TLS
253
254 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
255 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
256 __ stx(O2, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8);
257 __ stx(O3, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8);
258 __ stx(O4, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8);
259 __ stx(O5, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8);
260 #endif /* _LP64 */
261
262 // Restore flags
263
264 __ ldxfsr(SP, fsr_offset+STACK_BIAS);
265
266 __ restore();
267
268 #if !defined(_LP64)
269 // Now reload the 64bit Oregs after we've restore the window.
270 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
271 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
272 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+2*8, O2);
273 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+3*8, O3);
274 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+4*8, O4);
275 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+5*8, O5);
276 #endif /* _LP64 */
277
278 }
279
280 // Pop the current frame and restore the registers that might be holding
281 // a result.
282 void RegisterSaver::restore_result_registers(MacroAssembler* masm) {
283
284 #if !defined(_LP64)
285 // 32bit build returns longs in G1
286 __ ldx(SP, g1_offset+STACK_BIAS, G1);
287
288 // Retrieve the 64-bit O's.
289 __ ldx(SP, o0_offset+STACK_BIAS, O0);
290 __ ldx(SP, o1_offset+STACK_BIAS, O1);
291 // and save to TLS
292 __ stx(O0, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8);
293 __ stx(O1, G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8);
294 #endif /* _LP64 */
295
296 __ ldf(FloatRegisterImpl::D, SP, d00_offset+STACK_BIAS, as_FloatRegister(0));
297
298 __ restore();
299
300 #if !defined(_LP64)
301 // Now reload the 64bit Oregs after we've restore the window.
302 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+0*8, O0);
303 __ ldx(G2_thread, JavaThread::o_reg_temps_offset_in_bytes()+1*8, O1);
304 #endif /* _LP64 */
305
306 }
307
308 // The java_calling_convention describes stack locations as ideal slots on
309 // a frame with no abi restrictions. Since we must observe abi restrictions
310 // (like the placement of the register window) the slots must be biased by
311 // the following value.
312 static int reg2offset(VMReg r) {
313 return (r->reg2stack() + SharedRuntime::out_preserve_stack_slots()) * VMRegImpl::stack_slot_size;
314 }
315
316 // ---------------------------------------------------------------------------
317 // Read the array of BasicTypes from a signature, and compute where the
318 // arguments should go. Values in the VMRegPair regs array refer to 4-byte (VMRegImpl::stack_slot_size)
319 // quantities. Values less than VMRegImpl::stack0 are registers, those above
320 // refer to 4-byte stack slots. All stack slots are based off of the window
321 // top. VMRegImpl::stack0 refers to the first slot past the 16-word window,
322 // and VMRegImpl::stack0+1 refers to the memory word 4-byes higher. Register
323 // values 0-63 (up to RegisterImpl::number_of_registers) are the 64-bit
324 // integer registers. Values 64-95 are the (32-bit only) float registers.
325 // Each 32-bit quantity is given its own number, so the integer registers
326 // (in either 32- or 64-bit builds) use 2 numbers. For example, there is
327 // an O0-low and an O0-high. Essentially, all int register numbers are doubled.
328
329 // Register results are passed in O0-O5, for outgoing call arguments. To
330 // convert to incoming arguments, convert all O's to I's. The regs array
331 // refer to the low and hi 32-bit words of 64-bit registers or stack slots.
332 // If the regs[].second() field is set to VMRegImpl::Bad(), it means it's unused (a
333 // 32-bit value was passed). If both are VMRegImpl::Bad(), it means no value was
334 // passed (used as a placeholder for the other half of longs and doubles in
335 // the 64-bit build). regs[].second() is either VMRegImpl::Bad() or regs[].second() is
336 // regs[].first()+1 (regs[].first() may be misaligned in the C calling convention).
337 // Sparc never passes a value in regs[].second() but not regs[].first() (regs[].first()
338 // == VMRegImpl::Bad() && regs[].second() != VMRegImpl::Bad()) nor unrelated values in the
339 // same VMRegPair.
340
341 // Note: the INPUTS in sig_bt are in units of Java argument words, which are
342 // either 32-bit or 64-bit depending on the build. The OUTPUTS are in 32-bit
343 // units regardless of build.
344
345
346 // ---------------------------------------------------------------------------
347 // The compiled Java calling convention. The Java convention always passes
348 // 64-bit values in adjacent aligned locations (either registers or stack),
349 // floats in float registers and doubles in aligned float pairs. Values are
350 // packed in the registers. There is no backing varargs store for values in
351 // registers. In the 32-bit build, longs are passed in G1 and G4 (cannot be
352 // passed in I's, because longs in I's get their heads chopped off at
353 // interrupt).
354 int SharedRuntime::java_calling_convention(const BasicType *sig_bt,
355 VMRegPair *regs,
356 int total_args_passed,
357 int is_outgoing) {
358 assert(F31->as_VMReg()->is_reg(), "overlapping stack/register numbers");
359
360 // Convention is to pack the first 6 int/oop args into the first 6 registers
361 // (I0-I5), extras spill to the stack. Then pack the first 8 float args
362 // into F0-F7, extras spill to the stack. Then pad all register sets to
363 // align. Then put longs and doubles into the same registers as they fit,
364 // else spill to the stack.
365 const int int_reg_max = SPARC_ARGS_IN_REGS_NUM;
366 const int flt_reg_max = 8;
367 //
368 // Where 32-bit 1-reg longs start being passed
369 // In tiered we must pass on stack because c1 can't use a "pair" in a single reg.
370 // So make it look like we've filled all the G regs that c2 wants to use.
371 Register g_reg = TieredCompilation ? noreg : G1;
372
373 // Count int/oop and float args. See how many stack slots we'll need and
374 // where the longs & doubles will go.
375 int int_reg_cnt = 0;
376 int flt_reg_cnt = 0;
377 // int stk_reg_pairs = frame::register_save_words*(wordSize>>2);
378 // int stk_reg_pairs = SharedRuntime::out_preserve_stack_slots();
379 int stk_reg_pairs = 0;
380 for (int i = 0; i < total_args_passed; i++) {
381 switch (sig_bt[i]) {
382 case T_LONG: // LP64, longs compete with int args
383 assert(sig_bt[i+1] == T_VOID, "");
384 #ifdef _LP64
385 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
386 #endif
387 break;
388 case T_OBJECT:
389 case T_ARRAY:
390 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
391 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
392 #ifndef _LP64
393 else stk_reg_pairs++;
394 #endif
395 break;
396 case T_INT:
397 case T_SHORT:
398 case T_CHAR:
399 case T_BYTE:
400 case T_BOOLEAN:
401 if (int_reg_cnt < int_reg_max) int_reg_cnt++;
402 else stk_reg_pairs++;
403 break;
404 case T_FLOAT:
405 if (flt_reg_cnt < flt_reg_max) flt_reg_cnt++;
406 else stk_reg_pairs++;
407 break;
408 case T_DOUBLE:
409 assert(sig_bt[i+1] == T_VOID, "");
410 break;
411 case T_VOID:
412 break;
413 default:
414 ShouldNotReachHere();
415 }
416 }
417
418 // This is where the longs/doubles start on the stack.
419 stk_reg_pairs = (stk_reg_pairs+1) & ~1; // Round
420
421 int int_reg_pairs = (int_reg_cnt+1) & ~1; // 32-bit 2-reg longs only
422 int flt_reg_pairs = (flt_reg_cnt+1) & ~1;
423
424 // int stk_reg = frame::register_save_words*(wordSize>>2);
425 // int stk_reg = SharedRuntime::out_preserve_stack_slots();
426 int stk_reg = 0;
427 int int_reg = 0;
428 int flt_reg = 0;
429
430 // Now do the signature layout
431 for (int i = 0; i < total_args_passed; i++) {
432 switch (sig_bt[i]) {
433 case T_INT:
434 case T_SHORT:
435 case T_CHAR:
436 case T_BYTE:
437 case T_BOOLEAN:
438 #ifndef _LP64
439 case T_OBJECT:
440 case T_ARRAY:
441 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
442 #endif // _LP64
443 if (int_reg < int_reg_max) {
444 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
445 regs[i].set1(r->as_VMReg());
446 } else {
447 regs[i].set1(VMRegImpl::stack2reg(stk_reg++));
448 }
449 break;
450
451 #ifdef _LP64
452 case T_OBJECT:
453 case T_ARRAY:
454 case T_ADDRESS: // Used, e.g., in slow-path locking for the lock's stack address
455 if (int_reg < int_reg_max) {
456 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
457 regs[i].set2(r->as_VMReg());
458 } else {
459 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
460 stk_reg_pairs += 2;
461 }
462 break;
463 #endif // _LP64
464
465 case T_LONG:
466 assert(sig_bt[i+1] == T_VOID, "expecting VOID in other half");
467 #ifdef _LP64
468 if (int_reg < int_reg_max) {
469 Register r = is_outgoing ? as_oRegister(int_reg++) : as_iRegister(int_reg++);
470 regs[i].set2(r->as_VMReg());
471 } else {
472 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
473 stk_reg_pairs += 2;
474 }
475 #else
476 #ifdef COMPILER2
477 // For 32-bit build, can't pass longs in O-regs because they become
478 // I-regs and get trashed. Use G-regs instead. G1 and G4 are almost
479 // spare and available. This convention isn't used by the Sparc ABI or
480 // anywhere else. If we're tiered then we don't use G-regs because c1
481 // can't deal with them as a "pair". (Tiered makes this code think g's are filled)
482 // G0: zero
483 // G1: 1st Long arg
484 // G2: global allocated to TLS
485 // G3: used in inline cache check
486 // G4: 2nd Long arg
487 // G5: used in inline cache check
488 // G6: used by OS
489 // G7: used by OS
490
491 if (g_reg == G1) {
492 regs[i].set2(G1->as_VMReg()); // This long arg in G1
493 g_reg = G4; // Where the next arg goes
494 } else if (g_reg == G4) {
495 regs[i].set2(G4->as_VMReg()); // The 2nd long arg in G4
496 g_reg = noreg; // No more longs in registers
497 } else {
498 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
499 stk_reg_pairs += 2;
500 }
501 #else // COMPILER2
502 if (int_reg_pairs + 1 < int_reg_max) {
503 if (is_outgoing) {
504 regs[i].set_pair(as_oRegister(int_reg_pairs + 1)->as_VMReg(), as_oRegister(int_reg_pairs)->as_VMReg());
505 } else {
506 regs[i].set_pair(as_iRegister(int_reg_pairs + 1)->as_VMReg(), as_iRegister(int_reg_pairs)->as_VMReg());
507 }
508 int_reg_pairs += 2;
509 } else {
510 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
511 stk_reg_pairs += 2;
512 }
513 #endif // COMPILER2
514 #endif // _LP64
515 break;
516
517 case T_FLOAT:
518 if (flt_reg < flt_reg_max) regs[i].set1(as_FloatRegister(flt_reg++)->as_VMReg());
519 else regs[i].set1( VMRegImpl::stack2reg(stk_reg++));
520 break;
521 case T_DOUBLE:
522 assert(sig_bt[i+1] == T_VOID, "expecting half");
523 if (flt_reg_pairs + 1 < flt_reg_max) {
524 regs[i].set2(as_FloatRegister(flt_reg_pairs)->as_VMReg());
525 flt_reg_pairs += 2;
526 } else {
527 regs[i].set2(VMRegImpl::stack2reg(stk_reg_pairs));
528 stk_reg_pairs += 2;
529 }
530 break;
531 case T_VOID: regs[i].set_bad(); break; // Halves of longs & doubles
532 default:
533 ShouldNotReachHere();
534 }
535 }
536
537 // retun the amount of stack space these arguments will need.
538 return stk_reg_pairs;
539
540 }
541
542 // Helper class mostly to avoid passing masm everywhere, and handle
543 // store displacement overflow logic.
544 class AdapterGenerator {
545 MacroAssembler *masm;
546 Register Rdisp;
547 void set_Rdisp(Register r) { Rdisp = r; }
548
549 void patch_callers_callsite();
550
551 // base+st_off points to top of argument
552 int arg_offset(const int st_off) { return st_off; }
553 int next_arg_offset(const int st_off) {
554 return st_off - Interpreter::stackElementSize;
555 }
556
557 // Argument slot values may be loaded first into a register because
558 // they might not fit into displacement.
559 RegisterOrConstant arg_slot(const int st_off);
560 RegisterOrConstant next_arg_slot(const int st_off);
561
562 // Stores long into offset pointed to by base
563 void store_c2i_long(Register r, Register base,
564 const int st_off, bool is_stack);
565 void store_c2i_object(Register r, Register base,
566 const int st_off);
567 void store_c2i_int(Register r, Register base,
568 const int st_off);
569 void store_c2i_double(VMReg r_2,
570 VMReg r_1, Register base, const int st_off);
571 void store_c2i_float(FloatRegister f, Register base,
572 const int st_off);
573
574 public:
575 void gen_c2i_adapter(int total_args_passed,
576 // VMReg max_arg,
577 int comp_args_on_stack, // VMRegStackSlots
578 const BasicType *sig_bt,
579 const VMRegPair *regs,
580 Label& skip_fixup);
581 void gen_i2c_adapter(int total_args_passed,
582 // VMReg max_arg,
583 int comp_args_on_stack, // VMRegStackSlots
584 const BasicType *sig_bt,
585 const VMRegPair *regs);
586
587 AdapterGenerator(MacroAssembler *_masm) : masm(_masm) {}
588 };
589
590
591 // Patch the callers callsite with entry to compiled code if it exists.
592 void AdapterGenerator::patch_callers_callsite() {
593 Label L;
594 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
595 __ br_null(G3_scratch, false, __ pt, L);
596 // Schedule the branch target address early.
597 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
598 // Call into the VM to patch the caller, then jump to compiled callee
599 __ save_frame(4); // Args in compiled layout; do not blow them
600
601 // Must save all the live Gregs the list is:
602 // G1: 1st Long arg (32bit build)
603 // G2: global allocated to TLS
604 // G3: used in inline cache check (scratch)
605 // G4: 2nd Long arg (32bit build);
606 // G5: used in inline cache check (methodOop)
607
608 // The longs must go to the stack by hand since in the 32 bit build they can be trashed by window ops.
609
610 #ifdef _LP64
611 // mov(s,d)
612 __ mov(G1, L1);
613 __ mov(G4, L4);
614 __ mov(G5_method, L5);
615 __ mov(G5_method, O0); // VM needs target method
616 __ mov(I7, O1); // VM needs caller's callsite
617 // Must be a leaf call...
618 // can be very far once the blob has been relocated
619 AddressLiteral dest(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite));
620 __ relocate(relocInfo::runtime_call_type);
621 __ jumpl_to(dest, O7, O7);
622 __ delayed()->mov(G2_thread, L7_thread_cache);
623 __ mov(L7_thread_cache, G2_thread);
624 __ mov(L1, G1);
625 __ mov(L4, G4);
626 __ mov(L5, G5_method);
627 #else
628 __ stx(G1, FP, -8 + STACK_BIAS);
629 __ stx(G4, FP, -16 + STACK_BIAS);
630 __ mov(G5_method, L5);
631 __ mov(G5_method, O0); // VM needs target method
632 __ mov(I7, O1); // VM needs caller's callsite
633 // Must be a leaf call...
634 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::fixup_callers_callsite), relocInfo::runtime_call_type);
635 __ delayed()->mov(G2_thread, L7_thread_cache);
636 __ mov(L7_thread_cache, G2_thread);
637 __ ldx(FP, -8 + STACK_BIAS, G1);
638 __ ldx(FP, -16 + STACK_BIAS, G4);
639 __ mov(L5, G5_method);
640 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
641 #endif /* _LP64 */
642
643 __ restore(); // Restore args
644 __ bind(L);
645 }
646
647
648 RegisterOrConstant AdapterGenerator::arg_slot(const int st_off) {
649 RegisterOrConstant roc(arg_offset(st_off));
650 return __ ensure_simm13_or_reg(roc, Rdisp);
651 }
652
653 RegisterOrConstant AdapterGenerator::next_arg_slot(const int st_off) {
654 RegisterOrConstant roc(next_arg_offset(st_off));
655 return __ ensure_simm13_or_reg(roc, Rdisp);
656 }
657
658
659 // Stores long into offset pointed to by base
660 void AdapterGenerator::store_c2i_long(Register r, Register base,
661 const int st_off, bool is_stack) {
662 #ifdef _LP64
663 // In V9, longs are given 2 64-bit slots in the interpreter, but the
664 // data is passed in only 1 slot.
665 __ stx(r, base, next_arg_slot(st_off));
666 #else
667 #ifdef COMPILER2
668 // Misaligned store of 64-bit data
669 __ stw(r, base, arg_slot(st_off)); // lo bits
670 __ srlx(r, 32, r);
671 __ stw(r, base, next_arg_slot(st_off)); // hi bits
672 #else
673 if (is_stack) {
674 // Misaligned store of 64-bit data
675 __ stw(r, base, arg_slot(st_off)); // lo bits
676 __ srlx(r, 32, r);
677 __ stw(r, base, next_arg_slot(st_off)); // hi bits
678 } else {
679 __ stw(r->successor(), base, arg_slot(st_off) ); // lo bits
680 __ stw(r , base, next_arg_slot(st_off)); // hi bits
681 }
682 #endif // COMPILER2
683 #endif // _LP64
684 }
685
686 void AdapterGenerator::store_c2i_object(Register r, Register base,
687 const int st_off) {
688 __ st_ptr (r, base, arg_slot(st_off));
689 }
690
691 void AdapterGenerator::store_c2i_int(Register r, Register base,
692 const int st_off) {
693 __ st (r, base, arg_slot(st_off));
694 }
695
696 // Stores into offset pointed to by base
697 void AdapterGenerator::store_c2i_double(VMReg r_2,
698 VMReg r_1, Register base, const int st_off) {
699 #ifdef _LP64
700 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
701 // data is passed in only 1 slot.
702 __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
703 #else
704 // Need to marshal 64-bit value from misaligned Lesp loads
705 __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), base, next_arg_slot(st_off));
706 __ stf(FloatRegisterImpl::S, r_2->as_FloatRegister(), base, arg_slot(st_off) );
707 #endif
708 }
709
710 void AdapterGenerator::store_c2i_float(FloatRegister f, Register base,
711 const int st_off) {
712 __ stf(FloatRegisterImpl::S, f, base, arg_slot(st_off));
713 }
714
715 void AdapterGenerator::gen_c2i_adapter(
716 int total_args_passed,
717 // VMReg max_arg,
718 int comp_args_on_stack, // VMRegStackSlots
719 const BasicType *sig_bt,
720 const VMRegPair *regs,
721 Label& skip_fixup) {
722
723 // Before we get into the guts of the C2I adapter, see if we should be here
724 // at all. We've come from compiled code and are attempting to jump to the
725 // interpreter, which means the caller made a static call to get here
726 // (vcalls always get a compiled target if there is one). Check for a
727 // compiled target. If there is one, we need to patch the caller's call.
728 // However we will run interpreted if we come thru here. The next pass
729 // thru the call site will run compiled. If we ran compiled here then
730 // we can (theorectically) do endless i2c->c2i->i2c transitions during
731 // deopt/uncommon trap cycles. If we always go interpreted here then
732 // we can have at most one and don't need to play any tricks to keep
733 // from endlessly growing the stack.
734 //
735 // Actually if we detected that we had an i2c->c2i transition here we
736 // ought to be able to reset the world back to the state of the interpreted
737 // call and not bother building another interpreter arg area. We don't
738 // do that at this point.
739
740 patch_callers_callsite();
741
742 __ bind(skip_fixup);
743
744 // Since all args are passed on the stack, total_args_passed*wordSize is the
745 // space we need. Add in varargs area needed by the interpreter. Round up
746 // to stack alignment.
747 const int arg_size = total_args_passed * Interpreter::stackElementSize;
748 const int varargs_area =
749 (frame::varargs_offset - frame::register_save_words)*wordSize;
750 const int extraspace = round_to(arg_size + varargs_area, 2*wordSize);
751
752 int bias = STACK_BIAS;
753 const int interp_arg_offset = frame::varargs_offset*wordSize +
754 (total_args_passed-1)*Interpreter::stackElementSize;
755
756 Register base = SP;
757
758 #ifdef _LP64
759 // In the 64bit build because of wider slots and STACKBIAS we can run
760 // out of bits in the displacement to do loads and stores. Use g3 as
761 // temporary displacement.
762 if (! __ is_simm13(extraspace)) {
763 __ set(extraspace, G3_scratch);
764 __ sub(SP, G3_scratch, SP);
765 } else {
766 __ sub(SP, extraspace, SP);
767 }
768 set_Rdisp(G3_scratch);
769 #else
770 __ sub(SP, extraspace, SP);
771 #endif // _LP64
772
773 // First write G1 (if used) to where ever it must go
774 for (int i=0; i<total_args_passed; i++) {
775 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
776 VMReg r_1 = regs[i].first();
777 VMReg r_2 = regs[i].second();
778 if (r_1 == G1_scratch->as_VMReg()) {
779 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
780 store_c2i_object(G1_scratch, base, st_off);
781 } else if (sig_bt[i] == T_LONG) {
782 assert(!TieredCompilation, "should not use register args for longs");
783 store_c2i_long(G1_scratch, base, st_off, false);
784 } else {
785 store_c2i_int(G1_scratch, base, st_off);
786 }
787 }
788 }
789
790 // Now write the args into the outgoing interpreter space
791 for (int i=0; i<total_args_passed; i++) {
792 const int st_off = interp_arg_offset - (i*Interpreter::stackElementSize) + bias;
793 VMReg r_1 = regs[i].first();
794 VMReg r_2 = regs[i].second();
795 if (!r_1->is_valid()) {
796 assert(!r_2->is_valid(), "");
797 continue;
798 }
799 // Skip G1 if found as we did it first in order to free it up
800 if (r_1 == G1_scratch->as_VMReg()) {
801 continue;
802 }
803 #ifdef ASSERT
804 bool G1_forced = false;
805 #endif // ASSERT
806 if (r_1->is_stack()) { // Pretend stack targets are loaded into G1
807 #ifdef _LP64
808 Register ld_off = Rdisp;
809 __ set(reg2offset(r_1) + extraspace + bias, ld_off);
810 #else
811 int ld_off = reg2offset(r_1) + extraspace + bias;
812 #endif // _LP64
813 #ifdef ASSERT
814 G1_forced = true;
815 #endif // ASSERT
816 r_1 = G1_scratch->as_VMReg();// as part of the load/store shuffle
817 if (!r_2->is_valid()) __ ld (base, ld_off, G1_scratch);
818 else __ ldx(base, ld_off, G1_scratch);
819 }
820
821 if (r_1->is_Register()) {
822 Register r = r_1->as_Register()->after_restore();
823 if (sig_bt[i] == T_OBJECT || sig_bt[i] == T_ARRAY) {
824 store_c2i_object(r, base, st_off);
825 } else if (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) {
826 #ifndef _LP64
827 if (TieredCompilation) {
828 assert(G1_forced || sig_bt[i] != T_LONG, "should not use register args for longs");
829 }
830 #endif // _LP64
831 store_c2i_long(r, base, st_off, r_2->is_stack());
832 } else {
833 store_c2i_int(r, base, st_off);
834 }
835 } else {
836 assert(r_1->is_FloatRegister(), "");
837 if (sig_bt[i] == T_FLOAT) {
838 store_c2i_float(r_1->as_FloatRegister(), base, st_off);
839 } else {
840 assert(sig_bt[i] == T_DOUBLE, "wrong type");
841 store_c2i_double(r_2, r_1, base, st_off);
842 }
843 }
844 }
845
846 #ifdef _LP64
847 // Need to reload G3_scratch, used for temporary displacements.
848 __ ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
849
850 // Pass O5_savedSP as an argument to the interpreter.
851 // The interpreter will restore SP to this value before returning.
852 __ set(extraspace, G1);
853 __ add(SP, G1, O5_savedSP);
854 #else
855 // Pass O5_savedSP as an argument to the interpreter.
856 // The interpreter will restore SP to this value before returning.
857 __ add(SP, extraspace, O5_savedSP);
858 #endif // _LP64
859
860 __ mov((frame::varargs_offset)*wordSize -
861 1*Interpreter::stackElementSize+bias+BytesPerWord, G1);
862 // Jump to the interpreter just as if interpreter was doing it.
863 __ jmpl(G3_scratch, 0, G0);
864 // Setup Lesp for the call. Cannot actually set Lesp as the current Lesp
865 // (really L0) is in use by the compiled frame as a generic temp. However,
866 // the interpreter does not know where its args are without some kind of
867 // arg pointer being passed in. Pass it in Gargs.
868 __ delayed()->add(SP, G1, Gargs);
869 }
870
871 void AdapterGenerator::gen_i2c_adapter(
872 int total_args_passed,
873 // VMReg max_arg,
874 int comp_args_on_stack, // VMRegStackSlots
875 const BasicType *sig_bt,
876 const VMRegPair *regs) {
877
878 // Generate an I2C adapter: adjust the I-frame to make space for the C-frame
879 // layout. Lesp was saved by the calling I-frame and will be restored on
880 // return. Meanwhile, outgoing arg space is all owned by the callee
881 // C-frame, so we can mangle it at will. After adjusting the frame size,
882 // hoist register arguments and repack other args according to the compiled
883 // code convention. Finally, end in a jump to the compiled code. The entry
884 // point address is the start of the buffer.
885
886 // We will only enter here from an interpreted frame and never from after
887 // passing thru a c2i. Azul allowed this but we do not. If we lose the
888 // race and use a c2i we will remain interpreted for the race loser(s).
889 // This removes all sorts of headaches on the x86 side and also eliminates
890 // the possibility of having c2i -> i2c -> c2i -> ... endless transitions.
891
892 // As you can see from the list of inputs & outputs there are not a lot
893 // of temp registers to work with: mostly G1, G3 & G4.
894
895 // Inputs:
896 // G2_thread - TLS
897 // G5_method - Method oop
898 // G4 (Gargs) - Pointer to interpreter's args
899 // O0..O4 - free for scratch
900 // O5_savedSP - Caller's saved SP, to be restored if needed
901 // O6 - Current SP!
902 // O7 - Valid return address
903 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
904
905 // Outputs:
906 // G2_thread - TLS
907 // G1, G4 - Outgoing long args in 32-bit build
908 // O0-O5 - Outgoing args in compiled layout
909 // O6 - Adjusted or restored SP
910 // O7 - Valid return address
911 // L0-L7, I0-I7 - Caller's temps (no frame pushed yet)
912 // F0-F7 - more outgoing args
913
914
915 // Gargs is the incoming argument base, and also an outgoing argument.
916 __ sub(Gargs, BytesPerWord, Gargs);
917
918 // ON ENTRY TO THE CODE WE ARE MAKING, WE HAVE AN INTERPRETED FRAME
919 // WITH O7 HOLDING A VALID RETURN PC
920 //
921 // | |
922 // : java stack :
923 // | |
924 // +--------------+ <--- start of outgoing args
925 // | receiver | |
926 // : rest of args : |---size is java-arg-words
927 // | | |
928 // +--------------+ <--- O4_args (misaligned) and Lesp if prior is not C2I
929 // | | |
930 // : unused : |---Space for max Java stack, plus stack alignment
931 // | | |
932 // +--------------+ <--- SP + 16*wordsize
933 // | |
934 // : window :
935 // | |
936 // +--------------+ <--- SP
937
938 // WE REPACK THE STACK. We use the common calling convention layout as
939 // discovered by calling SharedRuntime::calling_convention. We assume it
940 // causes an arbitrary shuffle of memory, which may require some register
941 // temps to do the shuffle. We hope for (and optimize for) the case where
942 // temps are not needed. We may have to resize the stack slightly, in case
943 // we need alignment padding (32-bit interpreter can pass longs & doubles
944 // misaligned, but the compilers expect them aligned).
945 //
946 // | |
947 // : java stack :
948 // | |
949 // +--------------+ <--- start of outgoing args
950 // | pad, align | |
951 // +--------------+ |
952 // | ints, floats | |---Outgoing stack args, packed low.
953 // +--------------+ | First few args in registers.
954 // : doubles : |
955 // | longs | |
956 // +--------------+ <--- SP' + 16*wordsize
957 // | |
958 // : window :
959 // | |
960 // +--------------+ <--- SP'
961
962 // ON EXIT FROM THE CODE WE ARE MAKING, WE STILL HAVE AN INTERPRETED FRAME
963 // WITH O7 HOLDING A VALID RETURN PC - ITS JUST THAT THE ARGS ARE NOW SETUP
964 // FOR COMPILED CODE AND THE FRAME SLIGHTLY GROWN.
965
966 // Cut-out for having no stack args. Since up to 6 args are passed
967 // in registers, we will commonly have no stack args.
968 if (comp_args_on_stack > 0) {
969
970 // Convert VMReg stack slots to words.
971 int comp_words_on_stack = round_to(comp_args_on_stack*VMRegImpl::stack_slot_size, wordSize)>>LogBytesPerWord;
972 // Round up to miminum stack alignment, in wordSize
973 comp_words_on_stack = round_to(comp_words_on_stack, 2);
974 // Now compute the distance from Lesp to SP. This calculation does not
975 // include the space for total_args_passed because Lesp has not yet popped
976 // the arguments.
977 __ sub(SP, (comp_words_on_stack)*wordSize, SP);
978 }
979
980 // Will jump to the compiled code just as if compiled code was doing it.
981 // Pre-load the register-jump target early, to schedule it better.
982 __ ld_ptr(G5_method, in_bytes(methodOopDesc::from_compiled_offset()), G3);
983
984 // Now generate the shuffle code. Pick up all register args and move the
985 // rest through G1_scratch.
986 for (int i=0; i<total_args_passed; i++) {
987 if (sig_bt[i] == T_VOID) {
988 // Longs and doubles are passed in native word order, but misaligned
989 // in the 32-bit build.
990 assert(i > 0 && (sig_bt[i-1] == T_LONG || sig_bt[i-1] == T_DOUBLE), "missing half");
991 continue;
992 }
993
994 // Pick up 0, 1 or 2 words from Lesp+offset. Assume mis-aligned in the
995 // 32-bit build and aligned in the 64-bit build. Look for the obvious
996 // ldx/lddf optimizations.
997
998 // Load in argument order going down.
999 const int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
1000 set_Rdisp(G1_scratch);
1001
1002 VMReg r_1 = regs[i].first();
1003 VMReg r_2 = regs[i].second();
1004 if (!r_1->is_valid()) {
1005 assert(!r_2->is_valid(), "");
1006 continue;
1007 }
1008 if (r_1->is_stack()) { // Pretend stack targets are loaded into F8/F9
1009 r_1 = F8->as_VMReg(); // as part of the load/store shuffle
1010 if (r_2->is_valid()) r_2 = r_1->next();
1011 }
1012 if (r_1->is_Register()) { // Register argument
1013 Register r = r_1->as_Register()->after_restore();
1014 if (!r_2->is_valid()) {
1015 __ ld(Gargs, arg_slot(ld_off), r);
1016 } else {
1017 #ifdef _LP64
1018 // In V9, longs are given 2 64-bit slots in the interpreter, but the
1019 // data is passed in only 1 slot.
1020 RegisterOrConstant slot = (sig_bt[i] == T_LONG) ?
1021 next_arg_slot(ld_off) : arg_slot(ld_off);
1022 __ ldx(Gargs, slot, r);
1023 #else
1024 // Need to load a 64-bit value into G1/G4, but G1/G4 is being used in the
1025 // stack shuffle. Load the first 2 longs into G1/G4 later.
1026 #endif
1027 }
1028 } else {
1029 assert(r_1->is_FloatRegister(), "");
1030 if (!r_2->is_valid()) {
1031 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_1->as_FloatRegister());
1032 } else {
1033 #ifdef _LP64
1034 // In V9, doubles are given 2 64-bit slots in the interpreter, but the
1035 // data is passed in only 1 slot. This code also handles longs that
1036 // are passed on the stack, but need a stack-to-stack move through a
1037 // spare float register.
1038 RegisterOrConstant slot = (sig_bt[i] == T_LONG || sig_bt[i] == T_DOUBLE) ?
1039 next_arg_slot(ld_off) : arg_slot(ld_off);
1040 __ ldf(FloatRegisterImpl::D, Gargs, slot, r_1->as_FloatRegister());
1041 #else
1042 // Need to marshal 64-bit value from misaligned Lesp loads
1043 __ ldf(FloatRegisterImpl::S, Gargs, next_arg_slot(ld_off), r_1->as_FloatRegister());
1044 __ ldf(FloatRegisterImpl::S, Gargs, arg_slot(ld_off), r_2->as_FloatRegister());
1045 #endif
1046 }
1047 }
1048 // Was the argument really intended to be on the stack, but was loaded
1049 // into F8/F9?
1050 if (regs[i].first()->is_stack()) {
1051 assert(r_1->as_FloatRegister() == F8, "fix this code");
1052 // Convert stack slot to an SP offset
1053 int st_off = reg2offset(regs[i].first()) + STACK_BIAS;
1054 // Store down the shuffled stack word. Target address _is_ aligned.
1055 RegisterOrConstant slot = __ ensure_simm13_or_reg(st_off, Rdisp);
1056 if (!r_2->is_valid()) __ stf(FloatRegisterImpl::S, r_1->as_FloatRegister(), SP, slot);
1057 else __ stf(FloatRegisterImpl::D, r_1->as_FloatRegister(), SP, slot);
1058 }
1059 }
1060 bool made_space = false;
1061 #ifndef _LP64
1062 // May need to pick up a few long args in G1/G4
1063 bool g4_crushed = false;
1064 bool g3_crushed = false;
1065 for (int i=0; i<total_args_passed; i++) {
1066 if (regs[i].first()->is_Register() && regs[i].second()->is_valid()) {
1067 // Load in argument order going down
1068 int ld_off = (total_args_passed-i)*Interpreter::stackElementSize;
1069 // Need to marshal 64-bit value from misaligned Lesp loads
1070 Register r = regs[i].first()->as_Register()->after_restore();
1071 if (r == G1 || r == G4) {
1072 assert(!g4_crushed, "ordering problem");
1073 if (r == G4){
1074 g4_crushed = true;
1075 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
1076 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
1077 } else {
1078 // better schedule this way
1079 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
1080 __ lduw(Gargs, arg_slot(ld_off) , G3_scratch); // Load lo bits
1081 }
1082 g3_crushed = true;
1083 __ sllx(r, 32, r);
1084 __ or3(G3_scratch, r, r);
1085 } else {
1086 assert(r->is_out(), "longs passed in two O registers");
1087 __ ld (Gargs, arg_slot(ld_off) , r->successor()); // Load lo bits
1088 __ ld (Gargs, next_arg_slot(ld_off), r); // Load hi bits
1089 }
1090 }
1091 }
1092 #endif
1093
1094 // Jump to the compiled code just as if compiled code was doing it.
1095 //
1096 #ifndef _LP64
1097 if (g3_crushed) {
1098 // Rats load was wasted, at least it is in cache...
1099 __ ld_ptr(G5_method, methodOopDesc::from_compiled_offset(), G3);
1100 }
1101 #endif /* _LP64 */
1102
1103 // 6243940 We might end up in handle_wrong_method if
1104 // the callee is deoptimized as we race thru here. If that
1105 // happens we don't want to take a safepoint because the
1106 // caller frame will look interpreted and arguments are now
1107 // "compiled" so it is much better to make this transition
1108 // invisible to the stack walking code. Unfortunately if
1109 // we try and find the callee by normal means a safepoint
1110 // is possible. So we stash the desired callee in the thread
1111 // and the vm will find there should this case occur.
1112 Address callee_target_addr(G2_thread, JavaThread::callee_target_offset());
1113 __ st_ptr(G5_method, callee_target_addr);
1114
1115 if (StressNonEntrant) {
1116 // Open a big window for deopt failure
1117 __ save_frame(0);
1118 __ mov(G0, L0);
1119 Label loop;
1120 __ bind(loop);
1121 __ sub(L0, 1, L0);
1122 __ br_null(L0, false, Assembler::pt, loop);
1123 __ delayed()->nop();
1124
1125 __ restore();
1126 }
1127
1128
1129 __ jmpl(G3, 0, G0);
1130 __ delayed()->nop();
1131 }
1132
1133 // ---------------------------------------------------------------
1134 AdapterHandlerEntry* SharedRuntime::generate_i2c2i_adapters(MacroAssembler *masm,
1135 int total_args_passed,
1136 // VMReg max_arg,
1137 int comp_args_on_stack, // VMRegStackSlots
1138 const BasicType *sig_bt,
1139 const VMRegPair *regs,
1140 AdapterFingerPrint* fingerprint) {
1141 address i2c_entry = __ pc();
1142
1143 AdapterGenerator agen(masm);
1144
1145 agen.gen_i2c_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs);
1146
1147
1148 // -------------------------------------------------------------------------
1149 // Generate a C2I adapter. On entry we know G5 holds the methodOop. The
1150 // args start out packed in the compiled layout. They need to be unpacked
1151 // into the interpreter layout. This will almost always require some stack
1152 // space. We grow the current (compiled) stack, then repack the args. We
1153 // finally end in a jump to the generic interpreter entry point. On exit
1154 // from the interpreter, the interpreter will restore our SP (lest the
1155 // compiled code, which relys solely on SP and not FP, get sick).
1156
1157 address c2i_unverified_entry = __ pc();
1158 Label skip_fixup;
1159 {
1160 #if !defined(_LP64) && defined(COMPILER2)
1161 Register R_temp = L0; // another scratch register
1162 #else
1163 Register R_temp = G1; // another scratch register
1164 #endif
1165
1166 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1167
1168 __ verify_oop(O0);
1169 __ verify_oop(G5_method);
1170 __ load_klass(O0, G3_scratch);
1171 __ verify_oop(G3_scratch);
1172
1173 #if !defined(_LP64) && defined(COMPILER2)
1174 __ save(SP, -frame::register_save_words*wordSize, SP);
1175 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
1176 __ verify_oop(R_temp);
1177 __ cmp(G3_scratch, R_temp);
1178 __ restore();
1179 #else
1180 __ ld_ptr(G5_method, compiledICHolderOopDesc::holder_klass_offset(), R_temp);
1181 __ verify_oop(R_temp);
1182 __ cmp(G3_scratch, R_temp);
1183 #endif
1184
1185 Label ok, ok2;
1186 __ brx(Assembler::equal, false, Assembler::pt, ok);
1187 __ delayed()->ld_ptr(G5_method, compiledICHolderOopDesc::holder_method_offset(), G5_method);
1188 __ jump_to(ic_miss, G3_scratch);
1189 __ delayed()->nop();
1190
1191 __ bind(ok);
1192 // Method might have been compiled since the call site was patched to
1193 // interpreted if that is the case treat it as a miss so we can get
1194 // the call site corrected.
1195 __ ld_ptr(G5_method, in_bytes(methodOopDesc::code_offset()), G3_scratch);
1196 __ bind(ok2);
1197 __ br_null(G3_scratch, false, __ pt, skip_fixup);
1198 __ delayed()->ld_ptr(G5_method, in_bytes(methodOopDesc::interpreter_entry_offset()), G3_scratch);
1199 __ jump_to(ic_miss, G3_scratch);
1200 __ delayed()->nop();
1201
1202 }
1203
1204 address c2i_entry = __ pc();
1205
1206 agen.gen_c2i_adapter(total_args_passed, comp_args_on_stack, sig_bt, regs, skip_fixup);
1207
1208 __ flush();
1209 return AdapterHandlerLibrary::new_entry(fingerprint, i2c_entry, c2i_entry, c2i_unverified_entry);
1210
1211 }
1212
1213 // Helper function for native calling conventions
1214 static VMReg int_stk_helper( int i ) {
1215 // Bias any stack based VMReg we get by ignoring the window area
1216 // but not the register parameter save area.
1217 //
1218 // This is strange for the following reasons. We'd normally expect
1219 // the calling convention to return an VMReg for a stack slot
1220 // completely ignoring any abi reserved area. C2 thinks of that
1221 // abi area as only out_preserve_stack_slots. This does not include
1222 // the area allocated by the C abi to store down integer arguments
1223 // because the java calling convention does not use it. So
1224 // since c2 assumes that there are only out_preserve_stack_slots
1225 // to bias the optoregs (which impacts VMRegs) when actually referencing any actual stack
1226 // location the c calling convention must add in this bias amount
1227 // to make up for the fact that the out_preserve_stack_slots is
1228 // insufficient for C calls. What a mess. I sure hope those 6
1229 // stack words were worth it on every java call!
1230
1231 // Another way of cleaning this up would be for out_preserve_stack_slots
1232 // to take a parameter to say whether it was C or java calling conventions.
1233 // Then things might look a little better (but not much).
1234
1235 int mem_parm_offset = i - SPARC_ARGS_IN_REGS_NUM;
1236 if( mem_parm_offset < 0 ) {
1237 return as_oRegister(i)->as_VMReg();
1238 } else {
1239 int actual_offset = (mem_parm_offset + frame::memory_parameter_word_sp_offset) * VMRegImpl::slots_per_word;
1240 // Now return a biased offset that will be correct when out_preserve_slots is added back in
1241 return VMRegImpl::stack2reg(actual_offset - SharedRuntime::out_preserve_stack_slots());
1242 }
1243 }
1244
1245
1246 int SharedRuntime::c_calling_convention(const BasicType *sig_bt,
1247 VMRegPair *regs,
1248 int total_args_passed) {
1249
1250 // Return the number of VMReg stack_slots needed for the args.
1251 // This value does not include an abi space (like register window
1252 // save area).
1253
1254 // The native convention is V8 if !LP64
1255 // The LP64 convention is the V9 convention which is slightly more sane.
1256
1257 // We return the amount of VMReg stack slots we need to reserve for all
1258 // the arguments NOT counting out_preserve_stack_slots. Since we always
1259 // have space for storing at least 6 registers to memory we start with that.
1260 // See int_stk_helper for a further discussion.
1261 int max_stack_slots = (frame::varargs_offset * VMRegImpl::slots_per_word) - SharedRuntime::out_preserve_stack_slots();
1262
1263 #ifdef _LP64
1264 // V9 convention: All things "as-if" on double-wide stack slots.
1265 // Hoist any int/ptr/long's in the first 6 to int regs.
1266 // Hoist any flt/dbl's in the first 16 dbl regs.
1267 int j = 0; // Count of actual args, not HALVES
1268 for( int i=0; i<total_args_passed; i++, j++ ) {
1269 switch( sig_bt[i] ) {
1270 case T_BOOLEAN:
1271 case T_BYTE:
1272 case T_CHAR:
1273 case T_INT:
1274 case T_SHORT:
1275 regs[i].set1( int_stk_helper( j ) ); break;
1276 case T_LONG:
1277 assert( sig_bt[i+1] == T_VOID, "expecting half" );
1278 case T_ADDRESS: // raw pointers, like current thread, for VM calls
1279 case T_ARRAY:
1280 case T_OBJECT:
1281 regs[i].set2( int_stk_helper( j ) );
1282 break;
1283 case T_FLOAT:
1284 if ( j < 16 ) {
1285 // V9ism: floats go in ODD registers
1286 regs[i].set1(as_FloatRegister(1 + (j<<1))->as_VMReg());
1287 } else {
1288 // V9ism: floats go in ODD stack slot
1289 regs[i].set1(VMRegImpl::stack2reg(1 + (j<<1)));
1290 }
1291 break;
1292 case T_DOUBLE:
1293 assert( sig_bt[i+1] == T_VOID, "expecting half" );
1294 if ( j < 16 ) {
1295 // V9ism: doubles go in EVEN/ODD regs
1296 regs[i].set2(as_FloatRegister(j<<1)->as_VMReg());
1297 } else {
1298 // V9ism: doubles go in EVEN/ODD stack slots
1299 regs[i].set2(VMRegImpl::stack2reg(j<<1));
1300 }
1301 break;
1302 case T_VOID: regs[i].set_bad(); j--; break; // Do not count HALVES
1303 default:
1304 ShouldNotReachHere();
1305 }
1306 if (regs[i].first()->is_stack()) {
1307 int off = regs[i].first()->reg2stack();
1308 if (off > max_stack_slots) max_stack_slots = off;
1309 }
1310 if (regs[i].second()->is_stack()) {
1311 int off = regs[i].second()->reg2stack();
1312 if (off > max_stack_slots) max_stack_slots = off;
1313 }
1314 }
1315
1316 #else // _LP64
1317 // V8 convention: first 6 things in O-regs, rest on stack.
1318 // Alignment is willy-nilly.
1319 for( int i=0; i<total_args_passed; i++ ) {
1320 switch( sig_bt[i] ) {
1321 case T_ADDRESS: // raw pointers, like current thread, for VM calls
1322 case T_ARRAY:
1323 case T_BOOLEAN:
1324 case T_BYTE:
1325 case T_CHAR:
1326 case T_FLOAT:
1327 case T_INT:
1328 case T_OBJECT:
1329 case T_SHORT:
1330 regs[i].set1( int_stk_helper( i ) );
1331 break;
1332 case T_DOUBLE:
1333 case T_LONG:
1334 assert( sig_bt[i+1] == T_VOID, "expecting half" );
1335 regs[i].set_pair( int_stk_helper( i+1 ), int_stk_helper( i ) );
1336 break;
1337 case T_VOID: regs[i].set_bad(); break;
1338 default:
1339 ShouldNotReachHere();
1340 }
1341 if (regs[i].first()->is_stack()) {
1342 int off = regs[i].first()->reg2stack();
1343 if (off > max_stack_slots) max_stack_slots = off;
1344 }
1345 if (regs[i].second()->is_stack()) {
1346 int off = regs[i].second()->reg2stack();
1347 if (off > max_stack_slots) max_stack_slots = off;
1348 }
1349 }
1350 #endif // _LP64
1351
1352 return round_to(max_stack_slots + 1, 2);
1353
1354 }
1355
1356
1357 // ---------------------------------------------------------------------------
1358 void SharedRuntime::save_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1359 switch (ret_type) {
1360 case T_FLOAT:
1361 __ stf(FloatRegisterImpl::S, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS);
1362 break;
1363 case T_DOUBLE:
1364 __ stf(FloatRegisterImpl::D, F0, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS);
1365 break;
1366 }
1367 }
1368
1369 void SharedRuntime::restore_native_result(MacroAssembler *masm, BasicType ret_type, int frame_slots) {
1370 switch (ret_type) {
1371 case T_FLOAT:
1372 __ ldf(FloatRegisterImpl::S, SP, frame_slots*VMRegImpl::stack_slot_size - 4+STACK_BIAS, F0);
1373 break;
1374 case T_DOUBLE:
1375 __ ldf(FloatRegisterImpl::D, SP, frame_slots*VMRegImpl::stack_slot_size - 8+STACK_BIAS, F0);
1376 break;
1377 }
1378 }
1379
1380 // Check and forward and pending exception. Thread is stored in
1381 // L7_thread_cache and possibly NOT in G2_thread. Since this is a native call, there
1382 // is no exception handler. We merely pop this frame off and throw the
1383 // exception in the caller's frame.
1384 static void check_forward_pending_exception(MacroAssembler *masm, Register Rex_oop) {
1385 Label L;
1386 __ br_null(Rex_oop, false, Assembler::pt, L);
1387 __ delayed()->mov(L7_thread_cache, G2_thread); // restore in case we have exception
1388 // Since this is a native call, we *know* the proper exception handler
1389 // without calling into the VM: it's the empty function. Just pop this
1390 // frame and then jump to forward_exception_entry; O7 will contain the
1391 // native caller's return PC.
1392 AddressLiteral exception_entry(StubRoutines::forward_exception_entry());
1393 __ jump_to(exception_entry, G3_scratch);
1394 __ delayed()->restore(); // Pop this frame off.
1395 __ bind(L);
1396 }
1397
1398 // A simple move of integer like type
1399 static void simple_move32(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1400 if (src.first()->is_stack()) {
1401 if (dst.first()->is_stack()) {
1402 // stack to stack
1403 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1404 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1405 } else {
1406 // stack to reg
1407 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1408 }
1409 } else if (dst.first()->is_stack()) {
1410 // reg to stack
1411 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1412 } else {
1413 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1414 }
1415 }
1416
1417 // On 64 bit we will store integer like items to the stack as
1418 // 64 bits items (sparc abi) even though java would only store
1419 // 32bits for a parameter. On 32bit it will simply be 32 bits
1420 // So this routine will do 32->32 on 32bit and 32->64 on 64bit
1421 static void move32_64(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1422 if (src.first()->is_stack()) {
1423 if (dst.first()->is_stack()) {
1424 // stack to stack
1425 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1426 __ st_ptr(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1427 } else {
1428 // stack to reg
1429 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1430 }
1431 } else if (dst.first()->is_stack()) {
1432 // reg to stack
1433 __ st_ptr(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1434 } else {
1435 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1436 }
1437 }
1438
1439
1440 // An oop arg. Must pass a handle not the oop itself
1441 static void object_move(MacroAssembler* masm,
1442 OopMap* map,
1443 int oop_handle_offset,
1444 int framesize_in_slots,
1445 VMRegPair src,
1446 VMRegPair dst,
1447 bool is_receiver,
1448 int* receiver_offset) {
1449
1450 // must pass a handle. First figure out the location we use as a handle
1451
1452 if (src.first()->is_stack()) {
1453 // Oop is already on the stack
1454 Register rHandle = dst.first()->is_stack() ? L5 : dst.first()->as_Register();
1455 __ add(FP, reg2offset(src.first()) + STACK_BIAS, rHandle);
1456 __ ld_ptr(rHandle, 0, L4);
1457 #ifdef _LP64
1458 __ movr( Assembler::rc_z, L4, G0, rHandle );
1459 #else
1460 __ tst( L4 );
1461 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1462 #endif
1463 if (dst.first()->is_stack()) {
1464 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1465 }
1466 int offset_in_older_frame = src.first()->reg2stack() + SharedRuntime::out_preserve_stack_slots();
1467 if (is_receiver) {
1468 *receiver_offset = (offset_in_older_frame + framesize_in_slots) * VMRegImpl::stack_slot_size;
1469 }
1470 map->set_oop(VMRegImpl::stack2reg(offset_in_older_frame + framesize_in_slots));
1471 } else {
1472 // Oop is in an input register pass we must flush it to the stack
1473 const Register rOop = src.first()->as_Register();
1474 const Register rHandle = L5;
1475 int oop_slot = rOop->input_number() * VMRegImpl::slots_per_word + oop_handle_offset;
1476 int offset = oop_slot*VMRegImpl::stack_slot_size;
1477 Label skip;
1478 __ st_ptr(rOop, SP, offset + STACK_BIAS);
1479 if (is_receiver) {
1480 *receiver_offset = oop_slot * VMRegImpl::stack_slot_size;
1481 }
1482 map->set_oop(VMRegImpl::stack2reg(oop_slot));
1483 __ add(SP, offset + STACK_BIAS, rHandle);
1484 #ifdef _LP64
1485 __ movr( Assembler::rc_z, rOop, G0, rHandle );
1486 #else
1487 __ tst( rOop );
1488 __ movcc( Assembler::zero, false, Assembler::icc, G0, rHandle );
1489 #endif
1490
1491 if (dst.first()->is_stack()) {
1492 __ st_ptr(rHandle, SP, reg2offset(dst.first()) + STACK_BIAS);
1493 } else {
1494 __ mov(rHandle, dst.first()->as_Register());
1495 }
1496 }
1497 }
1498
1499 // A float arg may have to do float reg int reg conversion
1500 static void float_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1501 assert(!src.second()->is_valid() && !dst.second()->is_valid(), "bad float_move");
1502
1503 if (src.first()->is_stack()) {
1504 if (dst.first()->is_stack()) {
1505 // stack to stack the easiest of the bunch
1506 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1507 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1508 } else {
1509 // stack to reg
1510 if (dst.first()->is_Register()) {
1511 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1512 } else {
1513 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1514 }
1515 }
1516 } else if (dst.first()->is_stack()) {
1517 // reg to stack
1518 if (src.first()->is_Register()) {
1519 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1520 } else {
1521 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1522 }
1523 } else {
1524 // reg to reg
1525 if (src.first()->is_Register()) {
1526 if (dst.first()->is_Register()) {
1527 // gpr -> gpr
1528 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1529 } else {
1530 // gpr -> fpr
1531 __ st(src.first()->as_Register(), FP, -4 + STACK_BIAS);
1532 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.first()->as_FloatRegister());
1533 }
1534 } else if (dst.first()->is_Register()) {
1535 // fpr -> gpr
1536 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), FP, -4 + STACK_BIAS);
1537 __ ld(FP, -4 + STACK_BIAS, dst.first()->as_Register());
1538 } else {
1539 // fpr -> fpr
1540 // In theory these overlap but the ordering is such that this is likely a nop
1541 if ( src.first() != dst.first()) {
1542 __ fmov(FloatRegisterImpl::S, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1543 }
1544 }
1545 }
1546 }
1547
1548 static void split_long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1549 VMRegPair src_lo(src.first());
1550 VMRegPair src_hi(src.second());
1551 VMRegPair dst_lo(dst.first());
1552 VMRegPair dst_hi(dst.second());
1553 simple_move32(masm, src_lo, dst_lo);
1554 simple_move32(masm, src_hi, dst_hi);
1555 }
1556
1557 // A long move
1558 static void long_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1559
1560 // Do the simple ones here else do two int moves
1561 if (src.is_single_phys_reg() ) {
1562 if (dst.is_single_phys_reg()) {
1563 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1564 } else {
1565 // split src into two separate registers
1566 // Remember hi means hi address or lsw on sparc
1567 // Move msw to lsw
1568 if (dst.second()->is_reg()) {
1569 // MSW -> MSW
1570 __ srax(src.first()->as_Register(), 32, dst.first()->as_Register());
1571 // Now LSW -> LSW
1572 // this will only move lo -> lo and ignore hi
1573 VMRegPair split(dst.second());
1574 simple_move32(masm, src, split);
1575 } else {
1576 VMRegPair split(src.first(), L4->as_VMReg());
1577 // MSW -> MSW (lo ie. first word)
1578 __ srax(src.first()->as_Register(), 32, L4);
1579 split_long_move(masm, split, dst);
1580 }
1581 }
1582 } else if (dst.is_single_phys_reg()) {
1583 if (src.is_adjacent_aligned_on_stack(2)) {
1584 __ ldx(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1585 } else {
1586 // dst is a single reg.
1587 // Remember lo is low address not msb for stack slots
1588 // and lo is the "real" register for registers
1589 // src is
1590
1591 VMRegPair split;
1592
1593 if (src.first()->is_reg()) {
1594 // src.lo (msw) is a reg, src.hi is stk/reg
1595 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> src.lo [the MSW is in the LSW of the reg]
1596 split.set_pair(dst.first(), src.first());
1597 } else {
1598 // msw is stack move to L5
1599 // lsw is stack move to dst.lo (real reg)
1600 // we will move: src.hi (LSW) -> dst.lo, src.lo (MSW) -> L5
1601 split.set_pair(dst.first(), L5->as_VMReg());
1602 }
1603
1604 // src.lo -> src.lo/L5, src.hi -> dst.lo (the real reg)
1605 // msw -> src.lo/L5, lsw -> dst.lo
1606 split_long_move(masm, src, split);
1607
1608 // So dst now has the low order correct position the
1609 // msw half
1610 __ sllx(split.first()->as_Register(), 32, L5);
1611
1612 const Register d = dst.first()->as_Register();
1613 __ or3(L5, d, d);
1614 }
1615 } else {
1616 // For LP64 we can probably do better.
1617 split_long_move(masm, src, dst);
1618 }
1619 }
1620
1621 // A double move
1622 static void double_move(MacroAssembler* masm, VMRegPair src, VMRegPair dst) {
1623
1624 // The painful thing here is that like long_move a VMRegPair might be
1625 // 1: a single physical register
1626 // 2: two physical registers (v8)
1627 // 3: a physical reg [lo] and a stack slot [hi] (v8)
1628 // 4: two stack slots
1629
1630 // Since src is always a java calling convention we know that the src pair
1631 // is always either all registers or all stack (and aligned?)
1632
1633 // in a register [lo] and a stack slot [hi]
1634 if (src.first()->is_stack()) {
1635 if (dst.first()->is_stack()) {
1636 // stack to stack the easiest of the bunch
1637 // ought to be a way to do this where if alignment is ok we use ldd/std when possible
1638 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, L5);
1639 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1640 __ st(L5, SP, reg2offset(dst.first()) + STACK_BIAS);
1641 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1642 } else {
1643 // stack to reg
1644 if (dst.second()->is_stack()) {
1645 // stack -> reg, stack -> stack
1646 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1647 if (dst.first()->is_Register()) {
1648 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1649 } else {
1650 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1651 }
1652 // This was missing. (very rare case)
1653 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1654 } else {
1655 // stack -> reg
1656 // Eventually optimize for alignment QQQ
1657 if (dst.first()->is_Register()) {
1658 __ ld(FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_Register());
1659 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_Register());
1660 } else {
1661 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.first()) + STACK_BIAS, dst.first()->as_FloatRegister());
1662 __ ldf(FloatRegisterImpl::S, FP, reg2offset(src.second()) + STACK_BIAS, dst.second()->as_FloatRegister());
1663 }
1664 }
1665 }
1666 } else if (dst.first()->is_stack()) {
1667 // reg to stack
1668 if (src.first()->is_Register()) {
1669 // Eventually optimize for alignment QQQ
1670 __ st(src.first()->as_Register(), SP, reg2offset(dst.first()) + STACK_BIAS);
1671 if (src.second()->is_stack()) {
1672 __ ld(FP, reg2offset(src.second()) + STACK_BIAS, L4);
1673 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1674 } else {
1675 __ st(src.second()->as_Register(), SP, reg2offset(dst.second()) + STACK_BIAS);
1676 }
1677 } else {
1678 // fpr to stack
1679 if (src.second()->is_stack()) {
1680 ShouldNotReachHere();
1681 } else {
1682 // Is the stack aligned?
1683 if (reg2offset(dst.first()) & 0x7) {
1684 // No do as pairs
1685 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1686 __ stf(FloatRegisterImpl::S, src.second()->as_FloatRegister(), SP, reg2offset(dst.second()) + STACK_BIAS);
1687 } else {
1688 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), SP, reg2offset(dst.first()) + STACK_BIAS);
1689 }
1690 }
1691 }
1692 } else {
1693 // reg to reg
1694 if (src.first()->is_Register()) {
1695 if (dst.first()->is_Register()) {
1696 // gpr -> gpr
1697 __ mov(src.first()->as_Register(), dst.first()->as_Register());
1698 __ mov(src.second()->as_Register(), dst.second()->as_Register());
1699 } else {
1700 // gpr -> fpr
1701 // ought to be able to do a single store
1702 __ stx(src.first()->as_Register(), FP, -8 + STACK_BIAS);
1703 __ stx(src.second()->as_Register(), FP, -4 + STACK_BIAS);
1704 // ought to be able to do a single load
1705 __ ldf(FloatRegisterImpl::S, FP, -8 + STACK_BIAS, dst.first()->as_FloatRegister());
1706 __ ldf(FloatRegisterImpl::S, FP, -4 + STACK_BIAS, dst.second()->as_FloatRegister());
1707 }
1708 } else if (dst.first()->is_Register()) {
1709 // fpr -> gpr
1710 // ought to be able to do a single store
1711 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(), FP, -8 + STACK_BIAS);
1712 // ought to be able to do a single load
1713 // REMEMBER first() is low address not LSB
1714 __ ld(FP, -8 + STACK_BIAS, dst.first()->as_Register());
1715 if (dst.second()->is_Register()) {
1716 __ ld(FP, -4 + STACK_BIAS, dst.second()->as_Register());
1717 } else {
1718 __ ld(FP, -4 + STACK_BIAS, L4);
1719 __ st(L4, SP, reg2offset(dst.second()) + STACK_BIAS);
1720 }
1721 } else {
1722 // fpr -> fpr
1723 // In theory these overlap but the ordering is such that this is likely a nop
1724 if ( src.first() != dst.first()) {
1725 __ fmov(FloatRegisterImpl::D, src.first()->as_FloatRegister(), dst.first()->as_FloatRegister());
1726 }
1727 }
1728 }
1729 }
1730
1731 // Creates an inner frame if one hasn't already been created, and
1732 // saves a copy of the thread in L7_thread_cache
1733 static void create_inner_frame(MacroAssembler* masm, bool* already_created) {
1734 if (!*already_created) {
1735 __ save_frame(0);
1736 // Save thread in L7 (INNER FRAME); it crosses a bunch of VM calls below
1737 // Don't use save_thread because it smashes G2 and we merely want to save a
1738 // copy
1739 __ mov(G2_thread, L7_thread_cache);
1740 *already_created = true;
1741 }
1742 }
1743
1744 // ---------------------------------------------------------------------------
1745 // Generate a native wrapper for a given method. The method takes arguments
1746 // in the Java compiled code convention, marshals them to the native
1747 // convention (handlizes oops, etc), transitions to native, makes the call,
1748 // returns to java state (possibly blocking), unhandlizes any result and
1749 // returns.
1750 nmethod *SharedRuntime::generate_native_wrapper(MacroAssembler* masm,
1751 methodHandle method,
1752 int total_in_args,
1753 int comp_args_on_stack, // in VMRegStackSlots
1754 BasicType *in_sig_bt,
1755 VMRegPair *in_regs,
1756 BasicType ret_type) {
1757
1758 // Native nmethod wrappers never take possesion of the oop arguments.
1759 // So the caller will gc the arguments. The only thing we need an
1760 // oopMap for is if the call is static
1761 //
1762 // An OopMap for lock (and class if static), and one for the VM call itself
1763 OopMapSet *oop_maps = new OopMapSet();
1764 intptr_t start = (intptr_t)__ pc();
1765
1766 // First thing make an ic check to see if we should even be here
1767 {
1768 Label L;
1769 const Register temp_reg = G3_scratch;
1770 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
1771 __ verify_oop(O0);
1772 __ load_klass(O0, temp_reg);
1773 __ cmp(temp_reg, G5_inline_cache_reg);
1774 __ brx(Assembler::equal, true, Assembler::pt, L);
1775 __ delayed()->nop();
1776
1777 __ jump_to(ic_miss, temp_reg);
1778 __ delayed()->nop();
1779 __ align(CodeEntryAlignment);
1780 __ bind(L);
1781 }
1782
1783 int vep_offset = ((intptr_t)__ pc()) - start;
1784
1785 #ifdef COMPILER1
1786 if (InlineObjectHash && method->intrinsic_id() == vmIntrinsics::_hashCode) {
1787 // Object.hashCode can pull the hashCode from the header word
1788 // instead of doing a full VM transition once it's been computed.
1789 // Since hashCode is usually polymorphic at call sites we can't do
1790 // this optimization at the call site without a lot of work.
1791 Label slowCase;
1792 Register receiver = O0;
1793 Register result = O0;
1794 Register header = G3_scratch;
1795 Register hash = G3_scratch; // overwrite header value with hash value
1796 Register mask = G1; // to get hash field from header
1797
1798 // Read the header and build a mask to get its hash field. Give up if the object is not unlocked.
1799 // We depend on hash_mask being at most 32 bits and avoid the use of
1800 // hash_mask_in_place because it could be larger than 32 bits in a 64-bit
1801 // vm: see markOop.hpp.
1802 __ ld_ptr(receiver, oopDesc::mark_offset_in_bytes(), header);
1803 __ sethi(markOopDesc::hash_mask, mask);
1804 __ btst(markOopDesc::unlocked_value, header);
1805 __ br(Assembler::zero, false, Assembler::pn, slowCase);
1806 if (UseBiasedLocking) {
1807 // Check if biased and fall through to runtime if so
1808 __ delayed()->nop();
1809 __ btst(markOopDesc::biased_lock_bit_in_place, header);
1810 __ br(Assembler::notZero, false, Assembler::pn, slowCase);
1811 }
1812 __ delayed()->or3(mask, markOopDesc::hash_mask & 0x3ff, mask);
1813
1814 // Check for a valid (non-zero) hash code and get its value.
1815 #ifdef _LP64
1816 __ srlx(header, markOopDesc::hash_shift, hash);
1817 #else
1818 __ srl(header, markOopDesc::hash_shift, hash);
1819 #endif
1820 __ andcc(hash, mask, hash);
1821 __ br(Assembler::equal, false, Assembler::pn, slowCase);
1822 __ delayed()->nop();
1823
1824 // leaf return.
1825 __ retl();
1826 __ delayed()->mov(hash, result);
1827 __ bind(slowCase);
1828 }
1829 #endif // COMPILER1
1830
1831
1832 // We have received a description of where all the java arg are located
1833 // on entry to the wrapper. We need to convert these args to where
1834 // the jni function will expect them. To figure out where they go
1835 // we convert the java signature to a C signature by inserting
1836 // the hidden arguments as arg[0] and possibly arg[1] (static method)
1837
1838 int total_c_args = total_in_args + 1;
1839 if (method->is_static()) {
1840 total_c_args++;
1841 }
1842
1843 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_c_args);
1844 VMRegPair * out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_c_args);
1845
1846 int argc = 0;
1847 out_sig_bt[argc++] = T_ADDRESS;
1848 if (method->is_static()) {
1849 out_sig_bt[argc++] = T_OBJECT;
1850 }
1851
1852 for (int i = 0; i < total_in_args ; i++ ) {
1853 out_sig_bt[argc++] = in_sig_bt[i];
1854 }
1855
1856 // Now figure out where the args must be stored and how much stack space
1857 // they require (neglecting out_preserve_stack_slots but space for storing
1858 // the 1st six register arguments). It's weird see int_stk_helper.
1859 //
1860 int out_arg_slots;
1861 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
1862
1863 // Compute framesize for the wrapper. We need to handlize all oops in
1864 // registers. We must create space for them here that is disjoint from
1865 // the windowed save area because we have no control over when we might
1866 // flush the window again and overwrite values that gc has since modified.
1867 // (The live window race)
1868 //
1869 // We always just allocate 6 word for storing down these object. This allow
1870 // us to simply record the base and use the Ireg number to decide which
1871 // slot to use. (Note that the reg number is the inbound number not the
1872 // outbound number).
1873 // We must shuffle args to match the native convention, and include var-args space.
1874
1875 // Calculate the total number of stack slots we will need.
1876
1877 // First count the abi requirement plus all of the outgoing args
1878 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
1879
1880 // Now the space for the inbound oop handle area
1881
1882 int oop_handle_offset = stack_slots;
1883 stack_slots += 6*VMRegImpl::slots_per_word;
1884
1885 // Now any space we need for handlizing a klass if static method
1886
1887 int oop_temp_slot_offset = 0;
1888 int klass_slot_offset = 0;
1889 int klass_offset = -1;
1890 int lock_slot_offset = 0;
1891 bool is_static = false;
1892
1893 if (method->is_static()) {
1894 klass_slot_offset = stack_slots;
1895 stack_slots += VMRegImpl::slots_per_word;
1896 klass_offset = klass_slot_offset * VMRegImpl::stack_slot_size;
1897 is_static = true;
1898 }
1899
1900 // Plus a lock if needed
1901
1902 if (method->is_synchronized()) {
1903 lock_slot_offset = stack_slots;
1904 stack_slots += VMRegImpl::slots_per_word;
1905 }
1906
1907 // Now a place to save return value or as a temporary for any gpr -> fpr moves
1908 stack_slots += 2;
1909
1910 // Ok The space we have allocated will look like:
1911 //
1912 //
1913 // FP-> | |
1914 // |---------------------|
1915 // | 2 slots for moves |
1916 // |---------------------|
1917 // | lock box (if sync) |
1918 // |---------------------| <- lock_slot_offset
1919 // | klass (if static) |
1920 // |---------------------| <- klass_slot_offset
1921 // | oopHandle area |
1922 // |---------------------| <- oop_handle_offset
1923 // | outbound memory |
1924 // | based arguments |
1925 // | |
1926 // |---------------------|
1927 // | vararg area |
1928 // |---------------------|
1929 // | |
1930 // SP-> | out_preserved_slots |
1931 //
1932 //
1933
1934
1935 // Now compute actual number of stack words we need rounding to make
1936 // stack properly aligned.
1937 stack_slots = round_to(stack_slots, 2 * VMRegImpl::slots_per_word);
1938
1939 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
1940
1941 // Generate stack overflow check before creating frame
1942 __ generate_stack_overflow_check(stack_size);
1943
1944 // Generate a new frame for the wrapper.
1945 __ save(SP, -stack_size, SP);
1946
1947 int frame_complete = ((intptr_t)__ pc()) - start;
1948
1949 __ verify_thread();
1950
1951
1952 //
1953 // We immediately shuffle the arguments so that any vm call we have to
1954 // make from here on out (sync slow path, jvmti, etc.) we will have
1955 // captured the oops from our caller and have a valid oopMap for
1956 // them.
1957
1958 // -----------------
1959 // The Grand Shuffle
1960 //
1961 // Natives require 1 or 2 extra arguments over the normal ones: the JNIEnv*
1962 // (derived from JavaThread* which is in L7_thread_cache) and, if static,
1963 // the class mirror instead of a receiver. This pretty much guarantees that
1964 // register layout will not match. We ignore these extra arguments during
1965 // the shuffle. The shuffle is described by the two calling convention
1966 // vectors we have in our possession. We simply walk the java vector to
1967 // get the source locations and the c vector to get the destinations.
1968 // Because we have a new window and the argument registers are completely
1969 // disjoint ( I0 -> O1, I1 -> O2, ...) we have nothing to worry about
1970 // here.
1971
1972 // This is a trick. We double the stack slots so we can claim
1973 // the oops in the caller's frame. Since we are sure to have
1974 // more args than the caller doubling is enough to make
1975 // sure we can capture all the incoming oop args from the
1976 // caller.
1977 //
1978 OopMap* map = new OopMap(stack_slots * 2, 0 /* arg_slots*/);
1979 int c_arg = total_c_args - 1;
1980 // Record sp-based slot for receiver on stack for non-static methods
1981 int receiver_offset = -1;
1982
1983 // We move the arguments backward because the floating point registers
1984 // destination will always be to a register with a greater or equal register
1985 // number or the stack.
1986
1987 #ifdef ASSERT
1988 bool reg_destroyed[RegisterImpl::number_of_registers];
1989 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
1990 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
1991 reg_destroyed[r] = false;
1992 }
1993 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
1994 freg_destroyed[f] = false;
1995 }
1996
1997 #endif /* ASSERT */
1998
1999 for ( int i = total_in_args - 1; i >= 0 ; i--, c_arg-- ) {
2000
2001 #ifdef ASSERT
2002 if (in_regs[i].first()->is_Register()) {
2003 assert(!reg_destroyed[in_regs[i].first()->as_Register()->encoding()], "ack!");
2004 } else if (in_regs[i].first()->is_FloatRegister()) {
2005 assert(!freg_destroyed[in_regs[i].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)], "ack!");
2006 }
2007 if (out_regs[c_arg].first()->is_Register()) {
2008 reg_destroyed[out_regs[c_arg].first()->as_Register()->encoding()] = true;
2009 } else if (out_regs[c_arg].first()->is_FloatRegister()) {
2010 freg_destroyed[out_regs[c_arg].first()->as_FloatRegister()->encoding(FloatRegisterImpl::S)] = true;
2011 }
2012 #endif /* ASSERT */
2013
2014 switch (in_sig_bt[i]) {
2015 case T_ARRAY:
2016 case T_OBJECT:
2017 object_move(masm, map, oop_handle_offset, stack_slots, in_regs[i], out_regs[c_arg],
2018 ((i == 0) && (!is_static)),
2019 &receiver_offset);
2020 break;
2021 case T_VOID:
2022 break;
2023
2024 case T_FLOAT:
2025 float_move(masm, in_regs[i], out_regs[c_arg]);
2026 break;
2027
2028 case T_DOUBLE:
2029 assert( i + 1 < total_in_args &&
2030 in_sig_bt[i + 1] == T_VOID &&
2031 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2032 double_move(masm, in_regs[i], out_regs[c_arg]);
2033 break;
2034
2035 case T_LONG :
2036 long_move(masm, in_regs[i], out_regs[c_arg]);
2037 break;
2038
2039 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2040
2041 default:
2042 move32_64(masm, in_regs[i], out_regs[c_arg]);
2043 }
2044 }
2045
2046 // Pre-load a static method's oop into O1. Used both by locking code and
2047 // the normal JNI call code.
2048 if (method->is_static()) {
2049 __ set_oop_constant(JNIHandles::make_local(Klass::cast(method->method_holder())->java_mirror()), O1);
2050
2051 // Now handlize the static class mirror in O1. It's known not-null.
2052 __ st_ptr(O1, SP, klass_offset + STACK_BIAS);
2053 map->set_oop(VMRegImpl::stack2reg(klass_slot_offset));
2054 __ add(SP, klass_offset + STACK_BIAS, O1);
2055 }
2056
2057
2058 const Register L6_handle = L6;
2059
2060 if (method->is_synchronized()) {
2061 __ mov(O1, L6_handle);
2062 }
2063
2064 // We have all of the arguments setup at this point. We MUST NOT touch any Oregs
2065 // except O6/O7. So if we must call out we must push a new frame. We immediately
2066 // push a new frame and flush the windows.
2067
2068 #ifdef _LP64
2069 intptr_t thepc = (intptr_t) __ pc();
2070 {
2071 address here = __ pc();
2072 // Call the next instruction
2073 __ call(here + 8, relocInfo::none);
2074 __ delayed()->nop();
2075 }
2076 #else
2077 intptr_t thepc = __ load_pc_address(O7, 0);
2078 #endif /* _LP64 */
2079
2080 // We use the same pc/oopMap repeatedly when we call out
2081 oop_maps->add_gc_map(thepc - start, map);
2082
2083 // O7 now has the pc loaded that we will use when we finally call to native.
2084
2085 // Save thread in L7; it crosses a bunch of VM calls below
2086 // Don't use save_thread because it smashes G2 and we merely
2087 // want to save a copy
2088 __ mov(G2_thread, L7_thread_cache);
2089
2090
2091 // If we create an inner frame once is plenty
2092 // when we create it we must also save G2_thread
2093 bool inner_frame_created = false;
2094
2095 // dtrace method entry support
2096 {
2097 SkipIfEqual skip_if(
2098 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2099 // create inner frame
2100 __ save_frame(0);
2101 __ mov(G2_thread, L7_thread_cache);
2102 __ set_oop_constant(JNIHandles::make_local(method()), O1);
2103 __ call_VM_leaf(L7_thread_cache,
2104 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_entry),
2105 G2_thread, O1);
2106 __ restore();
2107 }
2108
2109 // RedefineClasses() tracing support for obsolete method entry
2110 if (RC_TRACE_IN_RANGE(0x00001000, 0x00002000)) {
2111 // create inner frame
2112 __ save_frame(0);
2113 __ mov(G2_thread, L7_thread_cache);
2114 __ set_oop_constant(JNIHandles::make_local(method()), O1);
2115 __ call_VM_leaf(L7_thread_cache,
2116 CAST_FROM_FN_PTR(address, SharedRuntime::rc_trace_method_entry),
2117 G2_thread, O1);
2118 __ restore();
2119 }
2120
2121 // We are in the jni frame unless saved_frame is true in which case
2122 // we are in one frame deeper (the "inner" frame). If we are in the
2123 // "inner" frames the args are in the Iregs and if the jni frame then
2124 // they are in the Oregs.
2125 // If we ever need to go to the VM (for locking, jvmti) then
2126 // we will always be in the "inner" frame.
2127
2128 // Lock a synchronized method
2129 int lock_offset = -1; // Set if locked
2130 if (method->is_synchronized()) {
2131 Register Roop = O1;
2132 const Register L3_box = L3;
2133
2134 create_inner_frame(masm, &inner_frame_created);
2135
2136 __ ld_ptr(I1, 0, O1);
2137 Label done;
2138
2139 lock_offset = (lock_slot_offset * VMRegImpl::stack_slot_size);
2140 __ add(FP, lock_offset+STACK_BIAS, L3_box);
2141 #ifdef ASSERT
2142 if (UseBiasedLocking) {
2143 // making the box point to itself will make it clear it went unused
2144 // but also be obviously invalid
2145 __ st_ptr(L3_box, L3_box, 0);
2146 }
2147 #endif // ASSERT
2148 //
2149 // Compiler_lock_object (Roop, Rmark, Rbox, Rscratch) -- kills Rmark, Rbox, Rscratch
2150 //
2151 __ compiler_lock_object(Roop, L1, L3_box, L2);
2152 __ br(Assembler::equal, false, Assembler::pt, done);
2153 __ delayed() -> add(FP, lock_offset+STACK_BIAS, L3_box);
2154
2155
2156 // None of the above fast optimizations worked so we have to get into the
2157 // slow case of monitor enter. Inline a special case of call_VM that
2158 // disallows any pending_exception.
2159 __ mov(Roop, O0); // Need oop in O0
2160 __ mov(L3_box, O1);
2161
2162 // Record last_Java_sp, in case the VM code releases the JVM lock.
2163
2164 __ set_last_Java_frame(FP, I7);
2165
2166 // do the call
2167 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_locking_C), relocInfo::runtime_call_type);
2168 __ delayed()->mov(L7_thread_cache, O2);
2169
2170 __ restore_thread(L7_thread_cache); // restore G2_thread
2171 __ reset_last_Java_frame();
2172
2173 #ifdef ASSERT
2174 { Label L;
2175 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2176 __ br_null(O0, false, Assembler::pt, L);
2177 __ delayed()->nop();
2178 __ stop("no pending exception allowed on exit from IR::monitorenter");
2179 __ bind(L);
2180 }
2181 #endif
2182 __ bind(done);
2183 }
2184
2185
2186 // Finally just about ready to make the JNI call
2187
2188 __ flush_windows();
2189 if (inner_frame_created) {
2190 __ restore();
2191 } else {
2192 // Store only what we need from this frame
2193 // QQQ I think that non-v9 (like we care) we don't need these saves
2194 // either as the flush traps and the current window goes too.
2195 __ st_ptr(FP, SP, FP->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2196 __ st_ptr(I7, SP, I7->sp_offset_in_saved_window()*wordSize + STACK_BIAS);
2197 }
2198
2199 // get JNIEnv* which is first argument to native
2200
2201 __ add(G2_thread, in_bytes(JavaThread::jni_environment_offset()), O0);
2202
2203 // Use that pc we placed in O7 a while back as the current frame anchor
2204
2205 __ set_last_Java_frame(SP, O7);
2206
2207 // Transition from _thread_in_Java to _thread_in_native.
2208 __ set(_thread_in_native, G3_scratch);
2209 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2210
2211 // We flushed the windows ages ago now mark them as flushed
2212
2213 // mark windows as flushed
2214 __ set(JavaFrameAnchor::flushed, G3_scratch);
2215
2216 Address flags(G2_thread, JavaThread::frame_anchor_offset() + JavaFrameAnchor::flags_offset());
2217
2218 #ifdef _LP64
2219 AddressLiteral dest(method->native_function());
2220 __ relocate(relocInfo::runtime_call_type);
2221 __ jumpl_to(dest, O7, O7);
2222 #else
2223 __ call(method->native_function(), relocInfo::runtime_call_type);
2224 #endif
2225 __ delayed()->st(G3_scratch, flags);
2226
2227 __ restore_thread(L7_thread_cache); // restore G2_thread
2228
2229 // Unpack native results. For int-types, we do any needed sign-extension
2230 // and move things into I0. The return value there will survive any VM
2231 // calls for blocking or unlocking. An FP or OOP result (handle) is done
2232 // specially in the slow-path code.
2233 switch (ret_type) {
2234 case T_VOID: break; // Nothing to do!
2235 case T_FLOAT: break; // Got it where we want it (unless slow-path)
2236 case T_DOUBLE: break; // Got it where we want it (unless slow-path)
2237 // In 64 bits build result is in O0, in O0, O1 in 32bit build
2238 case T_LONG:
2239 #ifndef _LP64
2240 __ mov(O1, I1);
2241 #endif
2242 // Fall thru
2243 case T_OBJECT: // Really a handle
2244 case T_ARRAY:
2245 case T_INT:
2246 __ mov(O0, I0);
2247 break;
2248 case T_BOOLEAN: __ subcc(G0, O0, G0); __ addc(G0, 0, I0); break; // !0 => true; 0 => false
2249 case T_BYTE : __ sll(O0, 24, O0); __ sra(O0, 24, I0); break;
2250 case T_CHAR : __ sll(O0, 16, O0); __ srl(O0, 16, I0); break; // cannot use and3, 0xFFFF too big as immediate value!
2251 case T_SHORT : __ sll(O0, 16, O0); __ sra(O0, 16, I0); break;
2252 break; // Cannot de-handlize until after reclaiming jvm_lock
2253 default:
2254 ShouldNotReachHere();
2255 }
2256
2257 // must we block?
2258
2259 // Block, if necessary, before resuming in _thread_in_Java state.
2260 // In order for GC to work, don't clear the last_Java_sp until after blocking.
2261 { Label no_block;
2262 AddressLiteral sync_state(SafepointSynchronize::address_of_state());
2263
2264 // Switch thread to "native transition" state before reading the synchronization state.
2265 // This additional state is necessary because reading and testing the synchronization
2266 // state is not atomic w.r.t. GC, as this scenario demonstrates:
2267 // Java thread A, in _thread_in_native state, loads _not_synchronized and is preempted.
2268 // VM thread changes sync state to synchronizing and suspends threads for GC.
2269 // Thread A is resumed to finish this native method, but doesn't block here since it
2270 // didn't see any synchronization is progress, and escapes.
2271 __ set(_thread_in_native_trans, G3_scratch);
2272 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2273 if(os::is_MP()) {
2274 if (UseMembar) {
2275 // Force this write out before the read below
2276 __ membar(Assembler::StoreLoad);
2277 } else {
2278 // Write serialization page so VM thread can do a pseudo remote membar.
2279 // We use the current thread pointer to calculate a thread specific
2280 // offset to write to within the page. This minimizes bus traffic
2281 // due to cache line collision.
2282 __ serialize_memory(G2_thread, G1_scratch, G3_scratch);
2283 }
2284 }
2285 __ load_contents(sync_state, G3_scratch);
2286 __ cmp(G3_scratch, SafepointSynchronize::_not_synchronized);
2287
2288 Label L;
2289 Address suspend_state(G2_thread, JavaThread::suspend_flags_offset());
2290 __ br(Assembler::notEqual, false, Assembler::pn, L);
2291 __ delayed()->ld(suspend_state, G3_scratch);
2292 __ cmp(G3_scratch, 0);
2293 __ br(Assembler::equal, false, Assembler::pt, no_block);
2294 __ delayed()->nop();
2295 __ bind(L);
2296
2297 // Block. Save any potential method result value before the operation and
2298 // use a leaf call to leave the last_Java_frame setup undisturbed. Doing this
2299 // lets us share the oopMap we used when we went native rather the create
2300 // a distinct one for this pc
2301 //
2302 save_native_result(masm, ret_type, stack_slots);
2303 __ call_VM_leaf(L7_thread_cache,
2304 CAST_FROM_FN_PTR(address, JavaThread::check_special_condition_for_native_trans),
2305 G2_thread);
2306
2307 // Restore any method result value
2308 restore_native_result(masm, ret_type, stack_slots);
2309 __ bind(no_block);
2310 }
2311
2312 // thread state is thread_in_native_trans. Any safepoint blocking has already
2313 // happened so we can now change state to _thread_in_Java.
2314
2315
2316 __ set(_thread_in_Java, G3_scratch);
2317 __ st(G3_scratch, G2_thread, JavaThread::thread_state_offset());
2318
2319
2320 Label no_reguard;
2321 __ ld(G2_thread, JavaThread::stack_guard_state_offset(), G3_scratch);
2322 __ cmp(G3_scratch, JavaThread::stack_guard_yellow_disabled);
2323 __ br(Assembler::notEqual, false, Assembler::pt, no_reguard);
2324 __ delayed()->nop();
2325
2326 save_native_result(masm, ret_type, stack_slots);
2327 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::reguard_yellow_pages));
2328 __ delayed()->nop();
2329
2330 __ restore_thread(L7_thread_cache); // restore G2_thread
2331 restore_native_result(masm, ret_type, stack_slots);
2332
2333 __ bind(no_reguard);
2334
2335 // Handle possible exception (will unlock if necessary)
2336
2337 // native result if any is live in freg or I0 (and I1 if long and 32bit vm)
2338
2339 // Unlock
2340 if (method->is_synchronized()) {
2341 Label done;
2342 Register I2_ex_oop = I2;
2343 const Register L3_box = L3;
2344 // Get locked oop from the handle we passed to jni
2345 __ ld_ptr(L6_handle, 0, L4);
2346 __ add(SP, lock_offset+STACK_BIAS, L3_box);
2347 // Must save pending exception around the slow-path VM call. Since it's a
2348 // leaf call, the pending exception (if any) can be kept in a register.
2349 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), I2_ex_oop);
2350 // Now unlock
2351 // (Roop, Rmark, Rbox, Rscratch)
2352 __ compiler_unlock_object(L4, L1, L3_box, L2);
2353 __ br(Assembler::equal, false, Assembler::pt, done);
2354 __ delayed()-> add(SP, lock_offset+STACK_BIAS, L3_box);
2355
2356 // save and restore any potential method result value around the unlocking
2357 // operation. Will save in I0 (or stack for FP returns).
2358 save_native_result(masm, ret_type, stack_slots);
2359
2360 // Must clear pending-exception before re-entering the VM. Since this is
2361 // a leaf call, pending-exception-oop can be safely kept in a register.
2362 __ st_ptr(G0, G2_thread, in_bytes(Thread::pending_exception_offset()));
2363
2364 // slow case of monitor enter. Inline a special case of call_VM that
2365 // disallows any pending_exception.
2366 __ mov(L3_box, O1);
2367
2368 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::complete_monitor_unlocking_C), relocInfo::runtime_call_type);
2369 __ delayed()->mov(L4, O0); // Need oop in O0
2370
2371 __ restore_thread(L7_thread_cache); // restore G2_thread
2372
2373 #ifdef ASSERT
2374 { Label L;
2375 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O0);
2376 __ br_null(O0, false, Assembler::pt, L);
2377 __ delayed()->nop();
2378 __ stop("no pending exception allowed on exit from IR::monitorexit");
2379 __ bind(L);
2380 }
2381 #endif
2382 restore_native_result(masm, ret_type, stack_slots);
2383 // check_forward_pending_exception jump to forward_exception if any pending
2384 // exception is set. The forward_exception routine expects to see the
2385 // exception in pending_exception and not in a register. Kind of clumsy,
2386 // since all folks who branch to forward_exception must have tested
2387 // pending_exception first and hence have it in a register already.
2388 __ st_ptr(I2_ex_oop, G2_thread, in_bytes(Thread::pending_exception_offset()));
2389 __ bind(done);
2390 }
2391
2392 // Tell dtrace about this method exit
2393 {
2394 SkipIfEqual skip_if(
2395 masm, G3_scratch, &DTraceMethodProbes, Assembler::zero);
2396 save_native_result(masm, ret_type, stack_slots);
2397 __ set_oop_constant(JNIHandles::make_local(method()), O1);
2398 __ call_VM_leaf(L7_thread_cache,
2399 CAST_FROM_FN_PTR(address, SharedRuntime::dtrace_method_exit),
2400 G2_thread, O1);
2401 restore_native_result(masm, ret_type, stack_slots);
2402 }
2403
2404 // Clear "last Java frame" SP and PC.
2405 __ verify_thread(); // G2_thread must be correct
2406 __ reset_last_Java_frame();
2407
2408 // Unpack oop result
2409 if (ret_type == T_OBJECT || ret_type == T_ARRAY) {
2410 Label L;
2411 __ addcc(G0, I0, G0);
2412 __ brx(Assembler::notZero, true, Assembler::pt, L);
2413 __ delayed()->ld_ptr(I0, 0, I0);
2414 __ mov(G0, I0);
2415 __ bind(L);
2416 __ verify_oop(I0);
2417 }
2418
2419 // reset handle block
2420 __ ld_ptr(G2_thread, in_bytes(JavaThread::active_handles_offset()), L5);
2421 __ st_ptr(G0, L5, JNIHandleBlock::top_offset_in_bytes());
2422
2423 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), G3_scratch);
2424 check_forward_pending_exception(masm, G3_scratch);
2425
2426
2427 // Return
2428
2429 #ifndef _LP64
2430 if (ret_type == T_LONG) {
2431
2432 // Must leave proper result in O0,O1 and G1 (c2/tiered only)
2433 __ sllx(I0, 32, G1); // Shift bits into high G1
2434 __ srl (I1, 0, I1); // Zero extend O1 (harmless?)
2435 __ or3 (I1, G1, G1); // OR 64 bits into G1
2436 }
2437 #endif
2438
2439 __ ret();
2440 __ delayed()->restore();
2441
2442 __ flush();
2443
2444 nmethod *nm = nmethod::new_native_nmethod(method,
2445 masm->code(),
2446 vep_offset,
2447 frame_complete,
2448 stack_slots / VMRegImpl::slots_per_word,
2449 (is_static ? in_ByteSize(klass_offset) : in_ByteSize(receiver_offset)),
2450 in_ByteSize(lock_offset),
2451 oop_maps);
2452 return nm;
2453
2454 }
2455
2456 #ifdef HAVE_DTRACE_H
2457 // ---------------------------------------------------------------------------
2458 // Generate a dtrace nmethod for a given signature. The method takes arguments
2459 // in the Java compiled code convention, marshals them to the native
2460 // abi and then leaves nops at the position you would expect to call a native
2461 // function. When the probe is enabled the nops are replaced with a trap
2462 // instruction that dtrace inserts and the trace will cause a notification
2463 // to dtrace.
2464 //
2465 // The probes are only able to take primitive types and java/lang/String as
2466 // arguments. No other java types are allowed. Strings are converted to utf8
2467 // strings so that from dtrace point of view java strings are converted to C
2468 // strings. There is an arbitrary fixed limit on the total space that a method
2469 // can use for converting the strings. (256 chars per string in the signature).
2470 // So any java string larger then this is truncated.
2471
2472 static int fp_offset[ConcreteRegisterImpl::number_of_registers] = { 0 };
2473 static bool offsets_initialized = false;
2474
2475 static VMRegPair reg64_to_VMRegPair(Register r) {
2476 VMRegPair ret;
2477 if (wordSize == 8) {
2478 ret.set2(r->as_VMReg());
2479 } else {
2480 ret.set_pair(r->successor()->as_VMReg(), r->as_VMReg());
2481 }
2482 return ret;
2483 }
2484
2485
2486 nmethod *SharedRuntime::generate_dtrace_nmethod(
2487 MacroAssembler *masm, methodHandle method) {
2488
2489
2490 // generate_dtrace_nmethod is guarded by a mutex so we are sure to
2491 // be single threaded in this method.
2492 assert(AdapterHandlerLibrary_lock->owned_by_self(), "must be");
2493
2494 // Fill in the signature array, for the calling-convention call.
2495 int total_args_passed = method->size_of_parameters();
2496
2497 BasicType* in_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed);
2498 VMRegPair *in_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed);
2499
2500 // The signature we are going to use for the trap that dtrace will see
2501 // java/lang/String is converted. We drop "this" and any other object
2502 // is converted to NULL. (A one-slot java/lang/Long object reference
2503 // is converted to a two-slot long, which is why we double the allocation).
2504 BasicType* out_sig_bt = NEW_RESOURCE_ARRAY(BasicType, total_args_passed * 2);
2505 VMRegPair* out_regs = NEW_RESOURCE_ARRAY(VMRegPair, total_args_passed * 2);
2506
2507 int i=0;
2508 int total_strings = 0;
2509 int first_arg_to_pass = 0;
2510 int total_c_args = 0;
2511
2512 // Skip the receiver as dtrace doesn't want to see it
2513 if( !method->is_static() ) {
2514 in_sig_bt[i++] = T_OBJECT;
2515 first_arg_to_pass = 1;
2516 }
2517
2518 SignatureStream ss(method->signature());
2519 for ( ; !ss.at_return_type(); ss.next()) {
2520 BasicType bt = ss.type();
2521 in_sig_bt[i++] = bt; // Collect remaining bits of signature
2522 out_sig_bt[total_c_args++] = bt;
2523 if( bt == T_OBJECT) {
2524 symbolOop s = ss.as_symbol_or_null();
2525 if (s == vmSymbols::java_lang_String()) {
2526 total_strings++;
2527 out_sig_bt[total_c_args-1] = T_ADDRESS;
2528 } else if (s == vmSymbols::java_lang_Boolean() ||
2529 s == vmSymbols::java_lang_Byte()) {
2530 out_sig_bt[total_c_args-1] = T_BYTE;
2531 } else if (s == vmSymbols::java_lang_Character() ||
2532 s == vmSymbols::java_lang_Short()) {
2533 out_sig_bt[total_c_args-1] = T_SHORT;
2534 } else if (s == vmSymbols::java_lang_Integer() ||
2535 s == vmSymbols::java_lang_Float()) {
2536 out_sig_bt[total_c_args-1] = T_INT;
2537 } else if (s == vmSymbols::java_lang_Long() ||
2538 s == vmSymbols::java_lang_Double()) {
2539 out_sig_bt[total_c_args-1] = T_LONG;
2540 out_sig_bt[total_c_args++] = T_VOID;
2541 }
2542 } else if ( bt == T_LONG || bt == T_DOUBLE ) {
2543 in_sig_bt[i++] = T_VOID; // Longs & doubles take 2 Java slots
2544 // We convert double to long
2545 out_sig_bt[total_c_args-1] = T_LONG;
2546 out_sig_bt[total_c_args++] = T_VOID;
2547 } else if ( bt == T_FLOAT) {
2548 // We convert float to int
2549 out_sig_bt[total_c_args-1] = T_INT;
2550 }
2551 }
2552
2553 assert(i==total_args_passed, "validly parsed signature");
2554
2555 // Now get the compiled-Java layout as input arguments
2556 int comp_args_on_stack;
2557 comp_args_on_stack = SharedRuntime::java_calling_convention(
2558 in_sig_bt, in_regs, total_args_passed, false);
2559
2560 // We have received a description of where all the java arg are located
2561 // on entry to the wrapper. We need to convert these args to where
2562 // the a native (non-jni) function would expect them. To figure out
2563 // where they go we convert the java signature to a C signature and remove
2564 // T_VOID for any long/double we might have received.
2565
2566
2567 // Now figure out where the args must be stored and how much stack space
2568 // they require (neglecting out_preserve_stack_slots but space for storing
2569 // the 1st six register arguments). It's weird see int_stk_helper.
2570 //
2571 int out_arg_slots;
2572 out_arg_slots = c_calling_convention(out_sig_bt, out_regs, total_c_args);
2573
2574 // Calculate the total number of stack slots we will need.
2575
2576 // First count the abi requirement plus all of the outgoing args
2577 int stack_slots = SharedRuntime::out_preserve_stack_slots() + out_arg_slots;
2578
2579 // Plus a temp for possible converion of float/double/long register args
2580
2581 int conversion_temp = stack_slots;
2582 stack_slots += 2;
2583
2584
2585 // Now space for the string(s) we must convert
2586
2587 int string_locs = stack_slots;
2588 stack_slots += total_strings *
2589 (max_dtrace_string_size / VMRegImpl::stack_slot_size);
2590
2591 // Ok The space we have allocated will look like:
2592 //
2593 //
2594 // FP-> | |
2595 // |---------------------|
2596 // | string[n] |
2597 // |---------------------| <- string_locs[n]
2598 // | string[n-1] |
2599 // |---------------------| <- string_locs[n-1]
2600 // | ... |
2601 // | ... |
2602 // |---------------------| <- string_locs[1]
2603 // | string[0] |
2604 // |---------------------| <- string_locs[0]
2605 // | temp |
2606 // |---------------------| <- conversion_temp
2607 // | outbound memory |
2608 // | based arguments |
2609 // | |
2610 // |---------------------|
2611 // | |
2612 // SP-> | out_preserved_slots |
2613 //
2614 //
2615
2616 // Now compute actual number of stack words we need rounding to make
2617 // stack properly aligned.
2618 stack_slots = round_to(stack_slots, 4 * VMRegImpl::slots_per_word);
2619
2620 int stack_size = stack_slots * VMRegImpl::stack_slot_size;
2621
2622 intptr_t start = (intptr_t)__ pc();
2623
2624 // First thing make an ic check to see if we should even be here
2625
2626 {
2627 Label L;
2628 const Register temp_reg = G3_scratch;
2629 AddressLiteral ic_miss(SharedRuntime::get_ic_miss_stub());
2630 __ verify_oop(O0);
2631 __ ld_ptr(O0, oopDesc::klass_offset_in_bytes(), temp_reg);
2632 __ cmp(temp_reg, G5_inline_cache_reg);
2633 __ brx(Assembler::equal, true, Assembler::pt, L);
2634 __ delayed()->nop();
2635
2636 __ jump_to(ic_miss, temp_reg);
2637 __ delayed()->nop();
2638 __ align(CodeEntryAlignment);
2639 __ bind(L);
2640 }
2641
2642 int vep_offset = ((intptr_t)__ pc()) - start;
2643
2644
2645 // The instruction at the verified entry point must be 5 bytes or longer
2646 // because it can be patched on the fly by make_non_entrant. The stack bang
2647 // instruction fits that requirement.
2648
2649 // Generate stack overflow check before creating frame
2650 __ generate_stack_overflow_check(stack_size);
2651
2652 assert(((intptr_t)__ pc() - start - vep_offset) >= 5,
2653 "valid size for make_non_entrant");
2654
2655 // Generate a new frame for the wrapper.
2656 __ save(SP, -stack_size, SP);
2657
2658 // Frame is now completed as far a size and linkage.
2659
2660 int frame_complete = ((intptr_t)__ pc()) - start;
2661
2662 #ifdef ASSERT
2663 bool reg_destroyed[RegisterImpl::number_of_registers];
2664 bool freg_destroyed[FloatRegisterImpl::number_of_registers];
2665 for ( int r = 0 ; r < RegisterImpl::number_of_registers ; r++ ) {
2666 reg_destroyed[r] = false;
2667 }
2668 for ( int f = 0 ; f < FloatRegisterImpl::number_of_registers ; f++ ) {
2669 freg_destroyed[f] = false;
2670 }
2671
2672 #endif /* ASSERT */
2673
2674 VMRegPair zero;
2675 const Register g0 = G0; // without this we get a compiler warning (why??)
2676 zero.set2(g0->as_VMReg());
2677
2678 int c_arg, j_arg;
2679
2680 Register conversion_off = noreg;
2681
2682 for (j_arg = first_arg_to_pass, c_arg = 0 ;
2683 j_arg < total_args_passed ; j_arg++, c_arg++ ) {
2684
2685 VMRegPair src = in_regs[j_arg];
2686 VMRegPair dst = out_regs[c_arg];
2687
2688 #ifdef ASSERT
2689 if (src.first()->is_Register()) {
2690 assert(!reg_destroyed[src.first()->as_Register()->encoding()], "ack!");
2691 } else if (src.first()->is_FloatRegister()) {
2692 assert(!freg_destroyed[src.first()->as_FloatRegister()->encoding(
2693 FloatRegisterImpl::S)], "ack!");
2694 }
2695 if (dst.first()->is_Register()) {
2696 reg_destroyed[dst.first()->as_Register()->encoding()] = true;
2697 } else if (dst.first()->is_FloatRegister()) {
2698 freg_destroyed[dst.first()->as_FloatRegister()->encoding(
2699 FloatRegisterImpl::S)] = true;
2700 }
2701 #endif /* ASSERT */
2702
2703 switch (in_sig_bt[j_arg]) {
2704 case T_ARRAY:
2705 case T_OBJECT:
2706 {
2707 if (out_sig_bt[c_arg] == T_BYTE || out_sig_bt[c_arg] == T_SHORT ||
2708 out_sig_bt[c_arg] == T_INT || out_sig_bt[c_arg] == T_LONG) {
2709 // need to unbox a one-slot value
2710 Register in_reg = L0;
2711 Register tmp = L2;
2712 if ( src.first()->is_reg() ) {
2713 in_reg = src.first()->as_Register();
2714 } else {
2715 assert(Assembler::is_simm13(reg2offset(src.first()) + STACK_BIAS),
2716 "must be");
2717 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, in_reg);
2718 }
2719 // If the final destination is an acceptable register
2720 if ( dst.first()->is_reg() ) {
2721 if ( dst.is_single_phys_reg() || out_sig_bt[c_arg] != T_LONG ) {
2722 tmp = dst.first()->as_Register();
2723 }
2724 }
2725
2726 Label skipUnbox;
2727 if ( wordSize == 4 && out_sig_bt[c_arg] == T_LONG ) {
2728 __ mov(G0, tmp->successor());
2729 }
2730 __ br_null(in_reg, true, Assembler::pn, skipUnbox);
2731 __ delayed()->mov(G0, tmp);
2732
2733 BasicType bt = out_sig_bt[c_arg];
2734 int box_offset = java_lang_boxing_object::value_offset_in_bytes(bt);
2735 switch (bt) {
2736 case T_BYTE:
2737 __ ldub(in_reg, box_offset, tmp); break;
2738 case T_SHORT:
2739 __ lduh(in_reg, box_offset, tmp); break;
2740 case T_INT:
2741 __ ld(in_reg, box_offset, tmp); break;
2742 case T_LONG:
2743 __ ld_long(in_reg, box_offset, tmp); break;
2744 default: ShouldNotReachHere();
2745 }
2746
2747 __ bind(skipUnbox);
2748 // If tmp wasn't final destination copy to final destination
2749 if (tmp == L2) {
2750 VMRegPair tmp_as_VM = reg64_to_VMRegPair(L2);
2751 if (out_sig_bt[c_arg] == T_LONG) {
2752 long_move(masm, tmp_as_VM, dst);
2753 } else {
2754 move32_64(masm, tmp_as_VM, out_regs[c_arg]);
2755 }
2756 }
2757 if (out_sig_bt[c_arg] == T_LONG) {
2758 assert(out_sig_bt[c_arg+1] == T_VOID, "must be");
2759 ++c_arg; // move over the T_VOID to keep the loop indices in sync
2760 }
2761 } else if (out_sig_bt[c_arg] == T_ADDRESS) {
2762 Register s =
2763 src.first()->is_reg() ? src.first()->as_Register() : L2;
2764 Register d =
2765 dst.first()->is_reg() ? dst.first()->as_Register() : L2;
2766
2767 // We store the oop now so that the conversion pass can reach
2768 // while in the inner frame. This will be the only store if
2769 // the oop is NULL.
2770 if (s != L2) {
2771 // src is register
2772 if (d != L2) {
2773 // dst is register
2774 __ mov(s, d);
2775 } else {
2776 assert(Assembler::is_simm13(reg2offset(dst.first()) +
2777 STACK_BIAS), "must be");
2778 __ st_ptr(s, SP, reg2offset(dst.first()) + STACK_BIAS);
2779 }
2780 } else {
2781 // src not a register
2782 assert(Assembler::is_simm13(reg2offset(src.first()) +
2783 STACK_BIAS), "must be");
2784 __ ld_ptr(FP, reg2offset(src.first()) + STACK_BIAS, d);
2785 if (d == L2) {
2786 assert(Assembler::is_simm13(reg2offset(dst.first()) +
2787 STACK_BIAS), "must be");
2788 __ st_ptr(d, SP, reg2offset(dst.first()) + STACK_BIAS);
2789 }
2790 }
2791 } else if (out_sig_bt[c_arg] != T_VOID) {
2792 // Convert the arg to NULL
2793 if (dst.first()->is_reg()) {
2794 __ mov(G0, dst.first()->as_Register());
2795 } else {
2796 assert(Assembler::is_simm13(reg2offset(dst.first()) +
2797 STACK_BIAS), "must be");
2798 __ st_ptr(G0, SP, reg2offset(dst.first()) + STACK_BIAS);
2799 }
2800 }
2801 }
2802 break;
2803 case T_VOID:
2804 break;
2805
2806 case T_FLOAT:
2807 if (src.first()->is_stack()) {
2808 // Stack to stack/reg is simple
2809 move32_64(masm, src, dst);
2810 } else {
2811 if (dst.first()->is_reg()) {
2812 // freg -> reg
2813 int off =
2814 STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2815 Register d = dst.first()->as_Register();
2816 if (Assembler::is_simm13(off)) {
2817 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2818 SP, off);
2819 __ ld(SP, off, d);
2820 } else {
2821 if (conversion_off == noreg) {
2822 __ set(off, L6);
2823 conversion_off = L6;
2824 }
2825 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2826 SP, conversion_off);
2827 __ ld(SP, conversion_off , d);
2828 }
2829 } else {
2830 // freg -> mem
2831 int off = STACK_BIAS + reg2offset(dst.first());
2832 if (Assembler::is_simm13(off)) {
2833 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2834 SP, off);
2835 } else {
2836 if (conversion_off == noreg) {
2837 __ set(off, L6);
2838 conversion_off = L6;
2839 }
2840 __ stf(FloatRegisterImpl::S, src.first()->as_FloatRegister(),
2841 SP, conversion_off);
2842 }
2843 }
2844 }
2845 break;
2846
2847 case T_DOUBLE:
2848 assert( j_arg + 1 < total_args_passed &&
2849 in_sig_bt[j_arg + 1] == T_VOID &&
2850 out_sig_bt[c_arg+1] == T_VOID, "bad arg list");
2851 if (src.first()->is_stack()) {
2852 // Stack to stack/reg is simple
2853 long_move(masm, src, dst);
2854 } else {
2855 Register d = dst.first()->is_reg() ? dst.first()->as_Register() : L2;
2856
2857 // Destination could be an odd reg on 32bit in which case
2858 // we can't load direct to the destination.
2859
2860 if (!d->is_even() && wordSize == 4) {
2861 d = L2;
2862 }
2863 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2864 if (Assembler::is_simm13(off)) {
2865 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
2866 SP, off);
2867 __ ld_long(SP, off, d);
2868 } else {
2869 if (conversion_off == noreg) {
2870 __ set(off, L6);
2871 conversion_off = L6;
2872 }
2873 __ stf(FloatRegisterImpl::D, src.first()->as_FloatRegister(),
2874 SP, conversion_off);
2875 __ ld_long(SP, conversion_off, d);
2876 }
2877 if (d == L2) {
2878 long_move(masm, reg64_to_VMRegPair(L2), dst);
2879 }
2880 }
2881 break;
2882
2883 case T_LONG :
2884 // 32bit can't do a split move of something like g1 -> O0, O1
2885 // so use a memory temp
2886 if (src.is_single_phys_reg() && wordSize == 4) {
2887 Register tmp = L2;
2888 if (dst.first()->is_reg() &&
2889 (wordSize == 8 || dst.first()->as_Register()->is_even())) {
2890 tmp = dst.first()->as_Register();
2891 }
2892
2893 int off = STACK_BIAS + conversion_temp * VMRegImpl::stack_slot_size;
2894 if (Assembler::is_simm13(off)) {
2895 __ stx(src.first()->as_Register(), SP, off);
2896 __ ld_long(SP, off, tmp);
2897 } else {
2898 if (conversion_off == noreg) {
2899 __ set(off, L6);
2900 conversion_off = L6;
2901 }
2902 __ stx(src.first()->as_Register(), SP, conversion_off);
2903 __ ld_long(SP, conversion_off, tmp);
2904 }
2905
2906 if (tmp == L2) {
2907 long_move(masm, reg64_to_VMRegPair(L2), dst);
2908 }
2909 } else {
2910 long_move(masm, src, dst);
2911 }
2912 break;
2913
2914 case T_ADDRESS: assert(false, "found T_ADDRESS in java args");
2915
2916 default:
2917 move32_64(masm, src, dst);
2918 }
2919 }
2920
2921
2922 // If we have any strings we must store any register based arg to the stack
2923 // This includes any still live xmm registers too.
2924
2925 if (total_strings > 0 ) {
2926
2927 // protect all the arg registers
2928 __ save_frame(0);
2929 __ mov(G2_thread, L7_thread_cache);
2930 const Register L2_string_off = L2;
2931
2932 // Get first string offset
2933 __ set(string_locs * VMRegImpl::stack_slot_size, L2_string_off);
2934
2935 for (c_arg = 0 ; c_arg < total_c_args ; c_arg++ ) {
2936 if (out_sig_bt[c_arg] == T_ADDRESS) {
2937
2938 VMRegPair dst = out_regs[c_arg];
2939 const Register d = dst.first()->is_reg() ?
2940 dst.first()->as_Register()->after_save() : noreg;
2941
2942 // It's a string the oop and it was already copied to the out arg
2943 // position
2944 if (d != noreg) {
2945 __ mov(d, O0);
2946 } else {
2947 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
2948 "must be");
2949 __ ld_ptr(FP, reg2offset(dst.first()) + STACK_BIAS, O0);
2950 }
2951 Label skip;
2952
2953 __ br_null(O0, false, Assembler::pn, skip);
2954 __ delayed()->add(FP, L2_string_off, O1);
2955
2956 if (d != noreg) {
2957 __ mov(O1, d);
2958 } else {
2959 assert(Assembler::is_simm13(reg2offset(dst.first()) + STACK_BIAS),
2960 "must be");
2961 __ st_ptr(O1, FP, reg2offset(dst.first()) + STACK_BIAS);
2962 }
2963
2964 __ call(CAST_FROM_FN_PTR(address, SharedRuntime::get_utf),
2965 relocInfo::runtime_call_type);
2966 __ delayed()->add(L2_string_off, max_dtrace_string_size, L2_string_off);
2967
2968 __ bind(skip);
2969
2970 }
2971
2972 }
2973 __ mov(L7_thread_cache, G2_thread);
2974 __ restore();
2975
2976 }
2977
2978
2979 // Ok now we are done. Need to place the nop that dtrace wants in order to
2980 // patch in the trap
2981
2982 int patch_offset = ((intptr_t)__ pc()) - start;
2983
2984 __ nop();
2985
2986
2987 // Return
2988
2989 __ ret();
2990 __ delayed()->restore();
2991
2992 __ flush();
2993
2994 nmethod *nm = nmethod::new_dtrace_nmethod(
2995 method, masm->code(), vep_offset, patch_offset, frame_complete,
2996 stack_slots / VMRegImpl::slots_per_word);
2997 return nm;
2998
2999 }
3000
3001 #endif // HAVE_DTRACE_H
3002
3003 // this function returns the adjust size (in number of words) to a c2i adapter
3004 // activation for use during deoptimization
3005 int Deoptimization::last_frame_adjust(int callee_parameters, int callee_locals) {
3006 assert(callee_locals >= callee_parameters,
3007 "test and remove; got more parms than locals");
3008 if (callee_locals < callee_parameters)
3009 return 0; // No adjustment for negative locals
3010 int diff = (callee_locals - callee_parameters) * Interpreter::stackElementWords;
3011 return round_to(diff, WordsPerLong);
3012 }
3013
3014 // "Top of Stack" slots that may be unused by the calling convention but must
3015 // otherwise be preserved.
3016 // On Intel these are not necessary and the value can be zero.
3017 // On Sparc this describes the words reserved for storing a register window
3018 // when an interrupt occurs.
3019 uint SharedRuntime::out_preserve_stack_slots() {
3020 return frame::register_save_words * VMRegImpl::slots_per_word;
3021 }
3022
3023 static void gen_new_frame(MacroAssembler* masm, bool deopt) {
3024 //
3025 // Common out the new frame generation for deopt and uncommon trap
3026 //
3027 Register G3pcs = G3_scratch; // Array of new pcs (input)
3028 Register Oreturn0 = O0;
3029 Register Oreturn1 = O1;
3030 Register O2UnrollBlock = O2;
3031 Register O3array = O3; // Array of frame sizes (input)
3032 Register O4array_size = O4; // number of frames (input)
3033 Register O7frame_size = O7; // number of frames (input)
3034
3035 __ ld_ptr(O3array, 0, O7frame_size);
3036 __ sub(G0, O7frame_size, O7frame_size);
3037 __ save(SP, O7frame_size, SP);
3038 __ ld_ptr(G3pcs, 0, I7); // load frame's new pc
3039
3040 #ifdef ASSERT
3041 // make sure that the frames are aligned properly
3042 #ifndef _LP64
3043 __ btst(wordSize*2-1, SP);
3044 __ breakpoint_trap(Assembler::notZero);
3045 #endif
3046 #endif
3047
3048 // Deopt needs to pass some extra live values from frame to frame
3049
3050 if (deopt) {
3051 __ mov(Oreturn0->after_save(), Oreturn0);
3052 __ mov(Oreturn1->after_save(), Oreturn1);
3053 }
3054
3055 __ mov(O4array_size->after_save(), O4array_size);
3056 __ sub(O4array_size, 1, O4array_size);
3057 __ mov(O3array->after_save(), O3array);
3058 __ mov(O2UnrollBlock->after_save(), O2UnrollBlock);
3059 __ add(G3pcs, wordSize, G3pcs); // point to next pc value
3060
3061 #ifdef ASSERT
3062 // trash registers to show a clear pattern in backtraces
3063 __ set(0xDEAD0000, I0);
3064 __ add(I0, 2, I1);
3065 __ add(I0, 4, I2);
3066 __ add(I0, 6, I3);
3067 __ add(I0, 8, I4);
3068 // Don't touch I5 could have valuable savedSP
3069 __ set(0xDEADBEEF, L0);
3070 __ mov(L0, L1);
3071 __ mov(L0, L2);
3072 __ mov(L0, L3);
3073 __ mov(L0, L4);
3074 __ mov(L0, L5);
3075
3076 // trash the return value as there is nothing to return yet
3077 __ set(0xDEAD0001, O7);
3078 #endif
3079
3080 __ mov(SP, O5_savedSP);
3081 }
3082
3083
3084 static void make_new_frames(MacroAssembler* masm, bool deopt) {
3085 //
3086 // loop through the UnrollBlock info and create new frames
3087 //
3088 Register G3pcs = G3_scratch;
3089 Register Oreturn0 = O0;
3090 Register Oreturn1 = O1;
3091 Register O2UnrollBlock = O2;
3092 Register O3array = O3;
3093 Register O4array_size = O4;
3094 Label loop;
3095
3096 // Before we make new frames, check to see if stack is available.
3097 // Do this after the caller's return address is on top of stack
3098 if (UseStackBanging) {
3099 // Get total frame size for interpreted frames
3100 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::total_frame_sizes_offset_in_bytes(), O4);
3101 __ bang_stack_size(O4, O3, G3_scratch);
3102 }
3103
3104 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::number_of_frames_offset_in_bytes(), O4array_size);
3105 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_pcs_offset_in_bytes(), G3pcs);
3106 __ ld_ptr(O2UnrollBlock, Deoptimization::UnrollBlock::frame_sizes_offset_in_bytes(), O3array);
3107
3108 // Adjust old interpreter frame to make space for new frame's extra java locals
3109 //
3110 // We capture the original sp for the transition frame only because it is needed in
3111 // order to properly calculate interpreter_sp_adjustment. Even though in real life
3112 // every interpreter frame captures a savedSP it is only needed at the transition
3113 // (fortunately). If we had to have it correct everywhere then we would need to
3114 // be told the sp_adjustment for each frame we create. If the frame size array
3115 // were to have twice the frame count entries then we could have pairs [sp_adjustment, frame_size]
3116 // for each frame we create and keep up the illusion every where.
3117 //
3118
3119 __ ld(O2UnrollBlock, Deoptimization::UnrollBlock::caller_adjustment_offset_in_bytes(), O7);
3120 __ mov(SP, O5_savedSP); // remember initial sender's original sp before adjustment
3121 __ sub(SP, O7, SP);
3122
3123 #ifdef ASSERT
3124 // make sure that there is at least one entry in the array
3125 __ tst(O4array_size);
3126 __ breakpoint_trap(Assembler::zero);
3127 #endif
3128
3129 // Now push the new interpreter frames
3130 __ bind(loop);
3131
3132 // allocate a new frame, filling the registers
3133
3134 gen_new_frame(masm, deopt); // allocate an interpreter frame
3135
3136 __ tst(O4array_size);
3137 __ br(Assembler::notZero, false, Assembler::pn, loop);
3138 __ delayed()->add(O3array, wordSize, O3array);
3139 __ ld_ptr(G3pcs, 0, O7); // load final frame new pc
3140
3141 }
3142
3143 //------------------------------generate_deopt_blob----------------------------
3144 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3145 // instead.
3146 void SharedRuntime::generate_deopt_blob() {
3147 // allocate space for the code
3148 ResourceMark rm;
3149 // setup code generation tools
3150 int pad = VerifyThread ? 512 : 0;// Extra slop space for more verify code
3151 #ifdef _LP64
3152 CodeBuffer buffer("deopt_blob", 2100+pad, 512);
3153 #else
3154 // Measured 8/7/03 at 1212 in 32bit debug build (no VerifyThread)
3155 // Measured 8/7/03 at 1396 in 32bit debug build (VerifyThread)
3156 CodeBuffer buffer("deopt_blob", 1600+pad, 512);
3157 #endif /* _LP64 */
3158 MacroAssembler* masm = new MacroAssembler(&buffer);
3159 FloatRegister Freturn0 = F0;
3160 Register Greturn1 = G1;
3161 Register Oreturn0 = O0;
3162 Register Oreturn1 = O1;
3163 Register O2UnrollBlock = O2;
3164 Register L0deopt_mode = L0;
3165 Register G4deopt_mode = G4_scratch;
3166 int frame_size_words;
3167 Address saved_Freturn0_addr(FP, -sizeof(double) + STACK_BIAS);
3168 #if !defined(_LP64) && defined(COMPILER2)
3169 Address saved_Greturn1_addr(FP, -sizeof(double) -sizeof(jlong) + STACK_BIAS);
3170 #endif
3171 Label cont;
3172
3173 OopMapSet *oop_maps = new OopMapSet();
3174
3175 //
3176 // This is the entry point for code which is returning to a de-optimized
3177 // frame.
3178 // The steps taken by this frame are as follows:
3179 // - push a dummy "register_save" and save the return values (O0, O1, F0/F1, G1)
3180 // and all potentially live registers (at a pollpoint many registers can be live).
3181 //
3182 // - call the C routine: Deoptimization::fetch_unroll_info (this function
3183 // returns information about the number and size of interpreter frames
3184 // which are equivalent to the frame which is being deoptimized)
3185 // - deallocate the unpack frame, restoring only results values. Other
3186 // volatile registers will now be captured in the vframeArray as needed.
3187 // - deallocate the deoptimization frame
3188 // - in a loop using the information returned in the previous step
3189 // push new interpreter frames (take care to propagate the return
3190 // values through each new frame pushed)
3191 // - create a dummy "unpack_frame" and save the return values (O0, O1, F0)
3192 // - call the C routine: Deoptimization::unpack_frames (this function
3193 // lays out values on the interpreter frame which was just created)
3194 // - deallocate the dummy unpack_frame
3195 // - ensure that all the return values are correctly set and then do
3196 // a return to the interpreter entry point
3197 //
3198 // Refer to the following methods for more information:
3199 // - Deoptimization::fetch_unroll_info
3200 // - Deoptimization::unpack_frames
3201
3202 OopMap* map = NULL;
3203
3204 int start = __ offset();
3205
3206 // restore G2, the trampoline destroyed it
3207 __ get_thread();
3208
3209 // On entry we have been called by the deoptimized nmethod with a call that
3210 // replaced the original call (or safepoint polling location) so the deoptimizing
3211 // pc is now in O7. Return values are still in the expected places
3212
3213 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3214 __ ba(false, cont);
3215 __ delayed()->mov(Deoptimization::Unpack_deopt, L0deopt_mode);
3216
3217 int exception_offset = __ offset() - start;
3218
3219 // restore G2, the trampoline destroyed it
3220 __ get_thread();
3221
3222 // On entry we have been jumped to by the exception handler (or exception_blob
3223 // for server). O0 contains the exception oop and O7 contains the original
3224 // exception pc. So if we push a frame here it will look to the
3225 // stack walking code (fetch_unroll_info) just like a normal call so
3226 // state will be extracted normally.
3227
3228 // save exception oop in JavaThread and fall through into the
3229 // exception_in_tls case since they are handled in same way except
3230 // for where the pending exception is kept.
3231 __ st_ptr(Oexception, G2_thread, JavaThread::exception_oop_offset());
3232
3233 //
3234 // Vanilla deoptimization with an exception pending in exception_oop
3235 //
3236 int exception_in_tls_offset = __ offset() - start;
3237
3238 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
3239 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3240
3241 // Restore G2_thread
3242 __ get_thread();
3243
3244 #ifdef ASSERT
3245 {
3246 // verify that there is really an exception oop in exception_oop
3247 Label has_exception;
3248 __ ld_ptr(G2_thread, JavaThread::exception_oop_offset(), Oexception);
3249 __ br_notnull(Oexception, false, Assembler::pt, has_exception);
3250 __ delayed()-> nop();
3251 __ stop("no exception in thread");
3252 __ bind(has_exception);
3253
3254 // verify that there is no pending exception
3255 Label no_pending_exception;
3256 Address exception_addr(G2_thread, Thread::pending_exception_offset());
3257 __ ld_ptr(exception_addr, Oexception);
3258 __ br_null(Oexception, false, Assembler::pt, no_pending_exception);
3259 __ delayed()->nop();
3260 __ stop("must not have pending exception here");
3261 __ bind(no_pending_exception);
3262 }
3263 #endif
3264
3265 __ ba(false, cont);
3266 __ delayed()->mov(Deoptimization::Unpack_exception, L0deopt_mode);;
3267
3268 //
3269 // Reexecute entry, similar to c2 uncommon trap
3270 //
3271 int reexecute_offset = __ offset() - start;
3272
3273 // No need to update oop_map as each call to save_live_registers will produce identical oopmap
3274 (void) RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3275
3276 __ mov(Deoptimization::Unpack_reexecute, L0deopt_mode);
3277
3278 __ bind(cont);
3279
3280 __ set_last_Java_frame(SP, noreg);
3281
3282 // do the call by hand so we can get the oopmap
3283
3284 __ mov(G2_thread, L7_thread_cache);
3285 __ call(CAST_FROM_FN_PTR(address, Deoptimization::fetch_unroll_info), relocInfo::runtime_call_type);
3286 __ delayed()->mov(G2_thread, O0);
3287
3288 // Set an oopmap for the call site this describes all our saved volatile registers
3289
3290 oop_maps->add_gc_map( __ offset()-start, map);
3291
3292 __ mov(L7_thread_cache, G2_thread);
3293
3294 __ reset_last_Java_frame();
3295
3296 // NOTE: we know that only O0/O1 will be reloaded by restore_result_registers
3297 // so this move will survive
3298
3299 __ mov(L0deopt_mode, G4deopt_mode);
3300
3301 __ mov(O0, O2UnrollBlock->after_save());
3302
3303 RegisterSaver::restore_result_registers(masm);
3304
3305 Label noException;
3306 __ cmp(G4deopt_mode, Deoptimization::Unpack_exception); // Was exception pending?
3307 __ br(Assembler::notEqual, false, Assembler::pt, noException);
3308 __ delayed()->nop();
3309
3310 // Move the pending exception from exception_oop to Oexception so
3311 // the pending exception will be picked up the interpreter.
3312 __ ld_ptr(G2_thread, in_bytes(JavaThread::exception_oop_offset()), Oexception);
3313 __ st_ptr(G0, G2_thread, in_bytes(JavaThread::exception_oop_offset()));
3314 __ bind(noException);
3315
3316 // deallocate the deoptimization frame taking care to preserve the return values
3317 __ mov(Oreturn0, Oreturn0->after_save());
3318 __ mov(Oreturn1, Oreturn1->after_save());
3319 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3320 __ restore();
3321
3322 // Allocate new interpreter frame(s) and possible c2i adapter frame
3323
3324 make_new_frames(masm, true);
3325
3326 // push a dummy "unpack_frame" taking care of float return values and
3327 // call Deoptimization::unpack_frames to have the unpacker layout
3328 // information in the interpreter frames just created and then return
3329 // to the interpreter entry point
3330 __ save(SP, -frame_size_words*wordSize, SP);
3331 __ stf(FloatRegisterImpl::D, Freturn0, saved_Freturn0_addr);
3332 #if !defined(_LP64)
3333 #if defined(COMPILER2)
3334 // 32-bit 1-register longs return longs in G1
3335 __ stx(Greturn1, saved_Greturn1_addr);
3336 #endif
3337 __ set_last_Java_frame(SP, noreg);
3338 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, G4deopt_mode);
3339 #else
3340 // LP64 uses g4 in set_last_Java_frame
3341 __ mov(G4deopt_mode, O1);
3342 __ set_last_Java_frame(SP, G0);
3343 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O1);
3344 #endif
3345 __ reset_last_Java_frame();
3346 __ ldf(FloatRegisterImpl::D, saved_Freturn0_addr, Freturn0);
3347
3348 #if !defined(_LP64) && defined(COMPILER2)
3349 // In 32 bit, C2 returns longs in G1 so restore the saved G1 into
3350 // I0/I1 if the return value is long.
3351 Label not_long;
3352 __ cmp(O0,T_LONG);
3353 __ br(Assembler::notEqual, false, Assembler::pt, not_long);
3354 __ delayed()->nop();
3355 __ ldd(saved_Greturn1_addr,I0);
3356 __ bind(not_long);
3357 #endif
3358 __ ret();
3359 __ delayed()->restore();
3360
3361 masm->flush();
3362 _deopt_blob = DeoptimizationBlob::create(&buffer, oop_maps, 0, exception_offset, reexecute_offset, frame_size_words);
3363 _deopt_blob->set_unpack_with_exception_in_tls_offset(exception_in_tls_offset);
3364 }
3365
3366 #ifdef COMPILER2
3367
3368 //------------------------------generate_uncommon_trap_blob--------------------
3369 // Ought to generate an ideal graph & compile, but here's some SPARC ASM
3370 // instead.
3371 void SharedRuntime::generate_uncommon_trap_blob() {
3372 // allocate space for the code
3373 ResourceMark rm;
3374 // setup code generation tools
3375 int pad = VerifyThread ? 512 : 0;
3376 #ifdef _LP64
3377 CodeBuffer buffer("uncommon_trap_blob", 2700+pad, 512);
3378 #else
3379 // Measured 8/7/03 at 660 in 32bit debug build (no VerifyThread)
3380 // Measured 8/7/03 at 1028 in 32bit debug build (VerifyThread)
3381 CodeBuffer buffer("uncommon_trap_blob", 2000+pad, 512);
3382 #endif
3383 MacroAssembler* masm = new MacroAssembler(&buffer);
3384 Register O2UnrollBlock = O2;
3385 Register O2klass_index = O2;
3386
3387 //
3388 // This is the entry point for all traps the compiler takes when it thinks
3389 // it cannot handle further execution of compilation code. The frame is
3390 // deoptimized in these cases and converted into interpreter frames for
3391 // execution
3392 // The steps taken by this frame are as follows:
3393 // - push a fake "unpack_frame"
3394 // - call the C routine Deoptimization::uncommon_trap (this function
3395 // packs the current compiled frame into vframe arrays and returns
3396 // information about the number and size of interpreter frames which
3397 // are equivalent to the frame which is being deoptimized)
3398 // - deallocate the "unpack_frame"
3399 // - deallocate the deoptimization frame
3400 // - in a loop using the information returned in the previous step
3401 // push interpreter frames;
3402 // - create a dummy "unpack_frame"
3403 // - call the C routine: Deoptimization::unpack_frames (this function
3404 // lays out values on the interpreter frame which was just created)
3405 // - deallocate the dummy unpack_frame
3406 // - return to the interpreter entry point
3407 //
3408 // Refer to the following methods for more information:
3409 // - Deoptimization::uncommon_trap
3410 // - Deoptimization::unpack_frame
3411
3412 // the unloaded class index is in O0 (first parameter to this blob)
3413
3414 // push a dummy "unpack_frame"
3415 // and call Deoptimization::uncommon_trap to pack the compiled frame into
3416 // vframe array and return the UnrollBlock information
3417 __ save_frame(0);
3418 __ set_last_Java_frame(SP, noreg);
3419 __ mov(I0, O2klass_index);
3420 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::uncommon_trap), G2_thread, O2klass_index);
3421 __ reset_last_Java_frame();
3422 __ mov(O0, O2UnrollBlock->after_save());
3423 __ restore();
3424
3425 // deallocate the deoptimized frame taking care to preserve the return values
3426 __ mov(O2UnrollBlock, O2UnrollBlock->after_save());
3427 __ restore();
3428
3429 // Allocate new interpreter frame(s) and possible c2i adapter frame
3430
3431 make_new_frames(masm, false);
3432
3433 // push a dummy "unpack_frame" taking care of float return values and
3434 // call Deoptimization::unpack_frames to have the unpacker layout
3435 // information in the interpreter frames just created and then return
3436 // to the interpreter entry point
3437 __ save_frame(0);
3438 __ set_last_Java_frame(SP, noreg);
3439 __ mov(Deoptimization::Unpack_uncommon_trap, O3); // indicate it is the uncommon trap case
3440 __ call_VM_leaf(L7_thread_cache, CAST_FROM_FN_PTR(address, Deoptimization::unpack_frames), G2_thread, O3);
3441 __ reset_last_Java_frame();
3442 __ ret();
3443 __ delayed()->restore();
3444
3445 masm->flush();
3446 _uncommon_trap_blob = UncommonTrapBlob::create(&buffer, NULL, __ total_frame_size_in_bytes(0)/wordSize);
3447 }
3448
3449 #endif // COMPILER2
3450
3451 //------------------------------generate_handler_blob-------------------
3452 //
3453 // Generate a special Compile2Runtime blob that saves all registers, and sets
3454 // up an OopMap.
3455 //
3456 // This blob is jumped to (via a breakpoint and the signal handler) from a
3457 // safepoint in compiled code. On entry to this blob, O7 contains the
3458 // address in the original nmethod at which we should resume normal execution.
3459 // Thus, this blob looks like a subroutine which must preserve lots of
3460 // registers and return normally. Note that O7 is never register-allocated,
3461 // so it is guaranteed to be free here.
3462 //
3463
3464 // The hardest part of what this blob must do is to save the 64-bit %o
3465 // registers in the 32-bit build. A simple 'save' turn the %o's to %i's and
3466 // an interrupt will chop off their heads. Making space in the caller's frame
3467 // first will let us save the 64-bit %o's before save'ing, but we cannot hand
3468 // the adjusted FP off to the GC stack-crawler: this will modify the caller's
3469 // SP and mess up HIS OopMaps. So we first adjust the caller's SP, then save
3470 // the 64-bit %o's, then do a save, then fixup the caller's SP (our FP).
3471 // Tricky, tricky, tricky...
3472
3473 static SafepointBlob* generate_handler_blob(address call_ptr, bool cause_return) {
3474 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3475
3476 // allocate space for the code
3477 ResourceMark rm;
3478 // setup code generation tools
3479 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3480 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3481 // even larger with TraceJumps
3482 int pad = TraceJumps ? 512 : 0;
3483 CodeBuffer buffer("handler_blob", 1600 + pad, 512);
3484 MacroAssembler* masm = new MacroAssembler(&buffer);
3485 int frame_size_words;
3486 OopMapSet *oop_maps = new OopMapSet();
3487 OopMap* map = NULL;
3488
3489 int start = __ offset();
3490
3491 // If this causes a return before the processing, then do a "restore"
3492 if (cause_return) {
3493 __ restore();
3494 } else {
3495 // Make it look like we were called via the poll
3496 // so that frame constructor always sees a valid return address
3497 __ ld_ptr(G2_thread, in_bytes(JavaThread::saved_exception_pc_offset()), O7);
3498 __ sub(O7, frame::pc_return_offset, O7);
3499 }
3500
3501 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3502
3503 // setup last_Java_sp (blows G4)
3504 __ set_last_Java_frame(SP, noreg);
3505
3506 // call into the runtime to handle illegal instructions exception
3507 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3508 __ mov(G2_thread, O0);
3509 __ save_thread(L7_thread_cache);
3510 __ call(call_ptr);
3511 __ delayed()->nop();
3512
3513 // Set an oopmap for the call site.
3514 // We need this not only for callee-saved registers, but also for volatile
3515 // registers that the compiler might be keeping live across a safepoint.
3516
3517 oop_maps->add_gc_map( __ offset() - start, map);
3518
3519 __ restore_thread(L7_thread_cache);
3520 // clear last_Java_sp
3521 __ reset_last_Java_frame();
3522
3523 // Check for exceptions
3524 Label pending;
3525
3526 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3527 __ tst(O1);
3528 __ brx(Assembler::notEqual, true, Assembler::pn, pending);
3529 __ delayed()->nop();
3530
3531 RegisterSaver::restore_live_registers(masm);
3532
3533 // We are back the the original state on entry and ready to go.
3534
3535 __ retl();
3536 __ delayed()->nop();
3537
3538 // Pending exception after the safepoint
3539
3540 __ bind(pending);
3541
3542 RegisterSaver::restore_live_registers(masm);
3543
3544 // We are back the the original state on entry.
3545
3546 // Tail-call forward_exception_entry, with the issuing PC in O7,
3547 // so it looks like the original nmethod called forward_exception_entry.
3548 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3549 __ JMP(O0, 0);
3550 __ delayed()->nop();
3551
3552 // -------------
3553 // make sure all code is generated
3554 masm->flush();
3555
3556 // return exception blob
3557 return SafepointBlob::create(&buffer, oop_maps, frame_size_words);
3558 }
3559
3560 //
3561 // generate_resolve_blob - call resolution (static/virtual/opt-virtual/ic-miss
3562 //
3563 // Generate a stub that calls into vm to find out the proper destination
3564 // of a java call. All the argument registers are live at this point
3565 // but since this is generic code we don't know what they are and the caller
3566 // must do any gc of the args.
3567 //
3568 static RuntimeStub* generate_resolve_blob(address destination, const char* name) {
3569 assert (StubRoutines::forward_exception_entry() != NULL, "must be generated before");
3570
3571 // allocate space for the code
3572 ResourceMark rm;
3573 // setup code generation tools
3574 // Measured 8/7/03 at 896 in 32bit debug build (no VerifyThread)
3575 // Measured 8/7/03 at 1080 in 32bit debug build (VerifyThread)
3576 // even larger with TraceJumps
3577 int pad = TraceJumps ? 512 : 0;
3578 CodeBuffer buffer(name, 1600 + pad, 512);
3579 MacroAssembler* masm = new MacroAssembler(&buffer);
3580 int frame_size_words;
3581 OopMapSet *oop_maps = new OopMapSet();
3582 OopMap* map = NULL;
3583
3584 int start = __ offset();
3585
3586 map = RegisterSaver::save_live_registers(masm, 0, &frame_size_words);
3587
3588 int frame_complete = __ offset();
3589
3590 // setup last_Java_sp (blows G4)
3591 __ set_last_Java_frame(SP, noreg);
3592
3593 // call into the runtime to handle illegal instructions exception
3594 // Do not use call_VM_leaf, because we need to make a GC map at this call site.
3595 __ mov(G2_thread, O0);
3596 __ save_thread(L7_thread_cache);
3597 __ call(destination, relocInfo::runtime_call_type);
3598 __ delayed()->nop();
3599
3600 // O0 contains the address we are going to jump to assuming no exception got installed
3601
3602 // Set an oopmap for the call site.
3603 // We need this not only for callee-saved registers, but also for volatile
3604 // registers that the compiler might be keeping live across a safepoint.
3605
3606 oop_maps->add_gc_map( __ offset() - start, map);
3607
3608 __ restore_thread(L7_thread_cache);
3609 // clear last_Java_sp
3610 __ reset_last_Java_frame();
3611
3612 // Check for exceptions
3613 Label pending;
3614
3615 __ ld_ptr(G2_thread, in_bytes(Thread::pending_exception_offset()), O1);
3616 __ tst(O1);
3617 __ brx(Assembler::notEqual, true, Assembler::pn, pending);
3618 __ delayed()->nop();
3619
3620 // get the returned methodOop
3621
3622 __ get_vm_result(G5_method);
3623 __ stx(G5_method, SP, RegisterSaver::G5_offset()+STACK_BIAS);
3624
3625 // O0 is where we want to jump, overwrite G3 which is saved and scratch
3626
3627 __ stx(O0, SP, RegisterSaver::G3_offset()+STACK_BIAS);
3628
3629 RegisterSaver::restore_live_registers(masm);
3630
3631 // We are back the the original state on entry and ready to go.
3632
3633 __ JMP(G3, 0);
3634 __ delayed()->nop();
3635
3636 // Pending exception after the safepoint
3637
3638 __ bind(pending);
3639
3640 RegisterSaver::restore_live_registers(masm);
3641
3642 // We are back the the original state on entry.
3643
3644 // Tail-call forward_exception_entry, with the issuing PC in O7,
3645 // so it looks like the original nmethod called forward_exception_entry.
3646 __ set((intptr_t)StubRoutines::forward_exception_entry(), O0);
3647 __ JMP(O0, 0);
3648 __ delayed()->nop();
3649
3650 // -------------
3651 // make sure all code is generated
3652 masm->flush();
3653
3654 // return the blob
3655 // frame_size_words or bytes??
3656 return RuntimeStub::new_runtime_stub(name, &buffer, frame_complete, frame_size_words, oop_maps, true);
3657 }
3658
3659 void SharedRuntime::generate_stubs() {
3660
3661 _wrong_method_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method),
3662 "wrong_method_stub");
3663
3664 _ic_miss_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::handle_wrong_method_ic_miss),
3665 "ic_miss_stub");
3666
3667 _resolve_opt_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_opt_virtual_call_C),
3668 "resolve_opt_virtual_call");
3669
3670 _resolve_virtual_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_virtual_call_C),
3671 "resolve_virtual_call");
3672
3673 _resolve_static_call_blob = generate_resolve_blob(CAST_FROM_FN_PTR(address, SharedRuntime::resolve_static_call_C),
3674 "resolve_static_call");
3675
3676 _polling_page_safepoint_handler_blob =
3677 generate_handler_blob(CAST_FROM_FN_PTR(address,
3678 SafepointSynchronize::handle_polling_page_exception), false);
3679
3680 _polling_page_return_handler_blob =
3681 generate_handler_blob(CAST_FROM_FN_PTR(address,
3682 SafepointSynchronize::handle_polling_page_exception), true);
3683
3684 generate_deopt_blob();
3685
3686 #ifdef COMPILER2
3687 generate_uncommon_trap_blob();
3688 #endif // COMPILER2
3689 }