1 /*
2 * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
3 * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
4 *
5 * This code is free software; you can redistribute it and/or modify it
6 * under the terms of the GNU General Public License version 2 only, as
7 * published by the Free Software Foundation.
8 *
9 * This code is distributed in the hope that it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License
12 * version 2 for more details (a copy is included in the LICENSE file that
13 * accompanied this code).
14 *
15 * You should have received a copy of the GNU General Public License version
16 * 2 along with this work; if not, write to the Free Software Foundation,
17 * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
18 *
19 * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
20 * or visit www.oracle.com if you need additional information or have any
21 * questions.
22 *
23 */
24
25 #ifndef CPU_SPARC_VM_VM_VERSION_SPARC_HPP
26 #define CPU_SPARC_VM_VM_VERSION_SPARC_HPP
27
28 #include "runtime/globals_extension.hpp"
29 #include "runtime/vm_version.hpp"
30
31 class VM_Version: public Abstract_VM_Version {
32 protected:
33 enum Feature_Flag {
34 v8_instructions = 0,
35 hardware_mul32 = 1,
36 hardware_div32 = 2,
37 hardware_fsmuld = 3,
38 hardware_popc = 4,
39 v9_instructions = 5,
40 vis1_instructions = 6,
41 vis2_instructions = 7,
42 sun4v_instructions = 8
43 };
44
45 enum Feature_Flag_Set {
46 unknown_m = 0,
47 all_features_m = -1,
48
49 v8_instructions_m = 1 << v8_instructions,
50 hardware_mul32_m = 1 << hardware_mul32,
51 hardware_div32_m = 1 << hardware_div32,
52 hardware_fsmuld_m = 1 << hardware_fsmuld,
53 hardware_popc_m = 1 << hardware_popc,
54 v9_instructions_m = 1 << v9_instructions,
55 vis1_instructions_m = 1 << vis1_instructions,
56 vis2_instructions_m = 1 << vis2_instructions,
57 sun4v_m = 1 << sun4v_instructions,
58
59 generic_v8_m = v8_instructions_m | hardware_mul32_m | hardware_div32_m | hardware_fsmuld_m,
60 generic_v9_m = generic_v8_m | v9_instructions_m,
61 ultra3_m = generic_v9_m | vis1_instructions_m | vis2_instructions_m,
62
63 // Temporary until we have something more accurate
64 niagara1_unique_m = sun4v_m,
65 niagara1_m = generic_v9_m | niagara1_unique_m
66 };
67
68 static int _features;
69 static const char* _features_str;
70
71 static void print_features();
72 static int determine_features();
73 static int platform_features(int features);
74
75 static bool is_niagara1(int features) { return (features & sun4v_m) != 0; }
76
77 static int maximum_niagara1_processor_count() { return 32; }
78 // Returns true if the platform is in the niagara line and
79 // newer than the niagara1.
80 static bool is_niagara1_plus();
81
82 public:
83 // Initialization
84 static void initialize();
85
86 // Instruction support
87 static bool has_v8() { return (_features & v8_instructions_m) != 0; }
88 static bool has_v9() { return (_features & v9_instructions_m) != 0; }
89 static bool has_hardware_mul32() { return (_features & hardware_mul32_m) != 0; }
90 static bool has_hardware_div32() { return (_features & hardware_div32_m) != 0; }
91 static bool has_hardware_fsmuld() { return (_features & hardware_fsmuld_m) != 0; }
92 static bool has_hardware_popc() { return (_features & hardware_popc_m) != 0; }
93 static bool has_vis1() { return (_features & vis1_instructions_m) != 0; }
94 static bool has_vis2() { return (_features & vis2_instructions_m) != 0; }
95
96 static bool supports_compare_and_exchange()
97 { return has_v9(); }
98
99 static bool is_ultra3() { return (_features & ultra3_m) == ultra3_m; }
100 static bool is_sun4v() { return (_features & sun4v_m) != 0; }
101 static bool is_niagara1() { return is_niagara1(_features); }
102
103 static bool has_fast_fxtof() { return has_v9() && !is_ultra3(); }
104
105 static const char* cpu_features() { return _features_str; }
106
107 static intx L1_data_cache_line_size() {
108 return 64; // default prefetch block size on sparc
109 }
110
111 // Prefetch
112 static intx prefetch_copy_interval_in_bytes() {
113 intx interval = PrefetchCopyIntervalInBytes;
114 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
115 }
116 static intx prefetch_scan_interval_in_bytes() {
117 intx interval = PrefetchScanIntervalInBytes;
118 return interval >= 0 ? interval : (has_v9() ? 512 : 0);
119 }
120 static intx prefetch_fields_ahead() {
121 intx count = PrefetchFieldsAhead;
122 return count >= 0 ? count : (is_ultra3() ? 1 : 0);
123 }
124
125 static intx allocate_prefetch_distance() {
126 // This method should be called before allocate_prefetch_style().
127 intx count = AllocatePrefetchDistance;
128 if (count < 0) { // default is not defined ?
129 count = 512;
130 }
131 return count;
132 }
133 static intx allocate_prefetch_style() {
134 assert(AllocatePrefetchStyle >= 0, "AllocatePrefetchStyle should be positive");
135 // Return 0 if AllocatePrefetchDistance was not defined.
136 return AllocatePrefetchDistance > 0 ? AllocatePrefetchStyle : 0;
137 }
138
139 // Legacy
140 static bool v8_instructions_work() { return has_v8() && !has_v9(); }
141 static bool v9_instructions_work() { return has_v9(); }
142
143 // Assembler testing
144 static void allow_all();
145 static void revert();
146
147 // Override the Abstract_VM_Version implementation.
148 static uint page_size_count() { return is_sun4v() ? 4 : 2; }
149
150 // Calculates the number of parallel threads
151 static unsigned int calc_parallel_worker_threads();
152 };
153
154 #endif // CPU_SPARC_VM_VM_VERSION_SPARC_HPP