src/cpu/x86/vm/icache_x86.hpp

*** 1,7 ****
  /*
!  * Copyright (c) 1997, 2004, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
--- 1,7 ----
  /*
!  * Copyright (c) 1997, 2010, Oracle and/or its affiliates. All rights reserved.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
   * published by the Free Software Foundation.
*** 20,29 ****
--- 20,32 ----
   * or visit www.oracle.com if you need additional information or have any
   * questions.
   *
   */
  
+ #ifndef CPU_X86_VM_ICACHE_X86_HPP
+ #define CPU_X86_VM_ICACHE_X86_HPP
+ 
  // Interface for updating the instruction cache.  Whenever the VM modifies
  // code, part of the processor instruction cache potentially has to be flushed.
  
  // On the x86, this is a no-op -- the I-cache is guaranteed to be consistent
  // after the next jump, and the VM never modifies instructions directly ahead
*** 51,55 ****
--- 54,60 ----
      line_size      = BytesPerWord,      // conservative
      log2_line_size = LogBytesPerWord    // log2(line_size)
    };
  #endif // AMD64
  };
+ 
+ #endif // CPU_X86_VM_ICACHE_X86_HPP