src/cpu/x86/vm/vm_version_x86.hpp

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   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 






  25 class VM_Version : public Abstract_VM_Version {
  26 public:
  27   // cpuid result register layouts.  These are all unions of a uint32_t
  28   // (in case anyone wants access to the register as a whole) and a bitfield.
  29 
  30   union StdCpuid1Eax {
  31     uint32_t value;
  32     struct {
  33       uint32_t stepping   : 4,
  34                model      : 4,
  35                family     : 4,
  36                proc_type  : 2,
  37                           : 2,
  38                ext_model  : 4,
  39                ext_family : 8,
  40                           : 4;
  41     } bits;
  42   };
  43 
  44   union StdCpuid1Ebx { // example, unused


 499   // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
 500   // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
 501 
 502   // gc copy/scan is disabled if prefetchw isn't supported, because
 503   // Prefetch::write emits an inlined prefetchw on Linux.
 504   // Do not use the 3dnow prefetchw instruction.  It isn't supported on em64t.
 505   // The used prefetcht0 instruction works for both amd64 and em64t.
 506   static intx prefetch_copy_interval_in_bytes() {
 507     intx interval = PrefetchCopyIntervalInBytes;
 508     return interval >= 0 ? interval : 576;
 509   }
 510   static intx prefetch_scan_interval_in_bytes() {
 511     intx interval = PrefetchScanIntervalInBytes;
 512     return interval >= 0 ? interval : 576;
 513   }
 514   static intx prefetch_fields_ahead() {
 515     intx count = PrefetchFieldsAhead;
 516     return count >= 0 ? count : 1;
 517   }
 518 };




   5  * This code is free software; you can redistribute it and/or modify it
   6  * under the terms of the GNU General Public License version 2 only, as
   7  * published by the Free Software Foundation.
   8  *
   9  * This code is distributed in the hope that it will be useful, but WITHOUT
  10  * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
  11  * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  12  * version 2 for more details (a copy is included in the LICENSE file that
  13  * accompanied this code).
  14  *
  15  * You should have received a copy of the GNU General Public License version
  16  * 2 along with this work; if not, write to the Free Software Foundation,
  17  * Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA.
  18  *
  19  * Please contact Oracle, 500 Oracle Parkway, Redwood Shores, CA 94065 USA
  20  * or visit www.oracle.com if you need additional information or have any
  21  * questions.
  22  *
  23  */
  24 
  25 #ifndef CPU_X86_VM_VM_VERSION_X86_HPP
  26 #define CPU_X86_VM_VM_VERSION_X86_HPP
  27 
  28 #include "runtime/globals_extension.hpp"
  29 #include "runtime/vm_version.hpp"
  30 
  31 class VM_Version : public Abstract_VM_Version {
  32 public:
  33   // cpuid result register layouts.  These are all unions of a uint32_t
  34   // (in case anyone wants access to the register as a whole) and a bitfield.
  35 
  36   union StdCpuid1Eax {
  37     uint32_t value;
  38     struct {
  39       uint32_t stepping   : 4,
  40                model      : 4,
  41                family     : 4,
  42                proc_type  : 2,
  43                           : 2,
  44                ext_model  : 4,
  45                ext_family : 8,
  46                           : 4;
  47     } bits;
  48   };
  49 
  50   union StdCpuid1Ebx { // example, unused


 505   // Tested intervals from 128 to 2048 in increments of 64 == one cache line.
 506   // 256 bytes (4 dcache lines) was the nearest runner-up to 576.
 507 
 508   // gc copy/scan is disabled if prefetchw isn't supported, because
 509   // Prefetch::write emits an inlined prefetchw on Linux.
 510   // Do not use the 3dnow prefetchw instruction.  It isn't supported on em64t.
 511   // The used prefetcht0 instruction works for both amd64 and em64t.
 512   static intx prefetch_copy_interval_in_bytes() {
 513     intx interval = PrefetchCopyIntervalInBytes;
 514     return interval >= 0 ? interval : 576;
 515   }
 516   static intx prefetch_scan_interval_in_bytes() {
 517     intx interval = PrefetchScanIntervalInBytes;
 518     return interval >= 0 ? interval : 576;
 519   }
 520   static intx prefetch_fields_ahead() {
 521     intx count = PrefetchFieldsAhead;
 522     return count >= 0 ? count : 1;
 523   }
 524 };
 525 
 526 #endif // CPU_X86_VM_VM_VERSION_X86_HPP