src/cpu/zero/vm/icache_zero.hpp

*** 1,7 ****
  /*
!  * Copyright (c) 2003, 2004, Oracle and/or its affiliates. All rights reserved.
   * Copyright 2007, 2009 Red Hat, Inc.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
--- 1,7 ----
  /*
!  * Copyright (c) 2003, 2010, Oracle and/or its affiliates. All rights reserved.
   * Copyright 2007, 2009 Red Hat, Inc.
   * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
   *
   * This code is free software; you can redistribute it and/or modify it
   * under the terms of the GNU General Public License version 2 only, as
*** 21,30 ****
--- 21,33 ----
   * or visit www.oracle.com if you need additional information or have any
   * questions.
   *
   */
  
+ #ifndef CPU_ZERO_VM_ICACHE_ZERO_HPP
+ #define CPU_ZERO_VM_ICACHE_ZERO_HPP
+ 
  // Interface for updating the instruction cache.  Whenever the VM
  // modifies code, part of the processor instruction cache potentially
  // has to be flushed.  This implementation is empty: Zero never deals
  // with code, and LLVM handles cache flushing for Shark.
  
*** 32,36 ****
--- 35,41 ----
   public:
    static void initialize() {}
    static void invalidate_word(address addr) {}
    static void invalidate_range(address start, int nbytes) {}
  };
+ 
+ #endif // CPU_ZERO_VM_ICACHE_ZERO_HPP